1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_rcc.c
4 * @author MCD Application Team
5 * @brief RCC LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32h5xx_ll_rcc.h"
22 #ifdef USE_FULL_ASSERT
23 #include "stm32_assert.h"
24 #else
25 #define assert_param(expr) ((void)0U)
26 #endif /* USE_FULL_ASSERT */
27 /** @addtogroup STM32H5xx_LL_Driver
28 * @{
29 */
30
31 #if defined(RCC)
32
33 /** @addtogroup RCC_LL
34 * @{
35 */
36
37 /* Private types -------------------------------------------------------------*/
38 /* Private variables ---------------------------------------------------------*/
39 /* Private constants ---------------------------------------------------------*/
40 /* Private macros ------------------------------------------------------------*/
41 /** @addtogroup RCC_LL_Private_Macros
42 * @{
43 */
44 #if defined(USART10)
45 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
46 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
47 || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE) \
48 || ((__VALUE__) == LL_RCC_USART6_CLKSOURCE) \
49 || ((__VALUE__) == LL_RCC_USART10_CLKSOURCE) \
50 || ((__VALUE__) == LL_RCC_USART11_CLKSOURCE))
51 #elif defined(USART6)
52 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
53 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
54 || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE) \
55 || ((__VALUE__) == LL_RCC_USART6_CLKSOURCE))
56 #else
57 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
58 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
59 || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
60 #endif /* USART6 */
61
62 #if defined(UART7)
63 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
64 || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE) \
65 || ((__VALUE__) == LL_RCC_UART7_CLKSOURCE) \
66 || ((__VALUE__) == LL_RCC_UART8_CLKSOURCE) \
67 || ((__VALUE__) == LL_RCC_UART9_CLKSOURCE) \
68 || ((__VALUE__) == LL_RCC_UART12_CLKSOURCE))
69 #elif defined(UART5)
70 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
71 || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE))
72 #endif /* UART7 */
73
74 #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE))
75
76 #if defined(I2C4)
77 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
78 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
79 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \
80 || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
81 #elif defined(I2C3)
82 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
83 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
84 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
85 #else
86 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
87 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE))
88 #endif /* I2C3*/
89
90 #if defined(I3C2)
91 #define IS_LL_RCC_I3C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I3C1_CLKSOURCE) \
92 || ((__VALUE__) == LL_RCC_I3C2_CLKSOURCE))
93 #else
94 #define IS_LL_RCC_I3C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I3C1_CLKSOURCE))
95 #endif /* I3C2 */
96
97 #if defined(SPI5)
98 #define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPI1_CLKSOURCE) \
99 || ((__VALUE__) == LL_RCC_SPI2_CLKSOURCE) \
100 || ((__VALUE__) == LL_RCC_SPI3_CLKSOURCE) \
101 || ((__VALUE__) == LL_RCC_SPI4_CLKSOURCE) \
102 || ((__VALUE__) == LL_RCC_SPI5_CLKSOURCE) \
103 || ((__VALUE__) == LL_RCC_SPI6_CLKSOURCE))
104 #elif defined(SPI4)
105 #define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPI1_CLKSOURCE) \
106 || ((__VALUE__) == LL_RCC_SPI2_CLKSOURCE) \
107 || ((__VALUE__) == LL_RCC_SPI3_CLKSOURCE) \
108 || ((__VALUE__) == LL_RCC_SPI4_CLKSOURCE))
109 #else
110 #define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPI1_CLKSOURCE) \
111 || ((__VALUE__) == LL_RCC_SPI2_CLKSOURCE) \
112 || ((__VALUE__) == LL_RCC_SPI3_CLKSOURCE))
113 #endif /* SPI5 */
114
115 #if defined(LPTIM3)
116 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
117 || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE) \
118 || ((__VALUE__) == LL_RCC_LPTIM3_CLKSOURCE) \
119 || ((__VALUE__) == LL_RCC_LPTIM4_CLKSOURCE) \
120 || ((__VALUE__) == LL_RCC_LPTIM5_CLKSOURCE) \
121 || ((__VALUE__) == LL_RCC_LPTIM6_CLKSOURCE))
122 #else
123 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
124 || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE))
125 #endif /* LPTIM3 */
126
127 #if defined(SAI1)
128 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
129 || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
130 #endif /* SAI1 */
131
132 #if defined (SDMMC2)
133 #define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE) \
134 || ((__VALUE__) == LL_RCC_SDMMC2_CLKSOURCE))
135 #elif defined (SDMMC1)
136 #define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE))
137 #endif /* SDMMC2*/
138
139 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
140
141 #if defined(USB_DRD_FS)
142 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
143 #endif /* USB_DRD_FS */
144
145 #define IS_LL_RCC_ADCDAC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADCDAC_CLKSOURCE))
146
147 #define IS_LL_RCC_DAC_LP_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DAC_LP_CLKSOURCE))
148
149 #define IS_LL_RCC_OCTOSPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_OCTOSPI_CLKSOURCE))
150
151 #define IS_LL_RCC_FDCAN_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_FDCAN_CLKSOURCE)
152
153 #if defined(CEC)
154 #define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
155 #endif /* CEC */
156
157 /**
158 * @}
159 */
160
161 /* Private function prototypes -----------------------------------------------*/
162 /** @defgroup RCC_LL_Private_Functions RCC Private functions
163 * @{
164 */
165 uint32_t RCC_GetSystemClockFreq(void);
166 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
167 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
168 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
169 uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency);
170 uint32_t RCC_PLL1_GetFreqSystem(void);
171 /**
172 * @}
173 */
174
175 /* Exported functions --------------------------------------------------------*/
176 /** @addtogroup RCC_LL_Exported_Functions
177 * @{
178 */
179
180 /** @addtogroup RCC_LL_EF_Init
181 * @{
182 */
183
184 /**
185 * @brief Reset the RCC clock configuration to the default reset state.
186 * @note The default reset state of the clock configuration is given below:
187 * - HSI ON and used as system clock source
188 * - HSE, CSI, PLL1, PLL2 and PLL3 OFF
189 * - AHB, APB1, APB2 and APB3 prescaler set to 1.
190 * - CSS OFF
191 * - All interrupts disabled
192 * @note This function doesn't modify the configuration of the
193 * - Peripheral clocks
194 * - LSI, LSE and RTC clocks
195 * @retval An ErrorStatus enumeration value:
196 * - SUCCESS: RCC registers are de-initialized
197 * - ERROR: not applicable
198 */
LL_RCC_DeInit(void)199 ErrorStatus LL_RCC_DeInit(void)
200 {
201
202 /* Set HSION bit */
203 LL_RCC_HSI_Enable();
204
205 /* Wait for HSI READY bit */
206 while (LL_RCC_HSI_IsReady() == 0U)
207 {
208 }
209
210 /* Set HSIDIV Default value */
211 CLEAR_BIT(RCC->CR, RCC_CR_HSIDIV);
212
213 /* Set HSITRIM bits to the reset value*/
214 LL_RCC_HSI_SetCalibTrimming(0x40U);
215
216 /* Reset CFGR register */
217 LL_RCC_WriteReg(CFGR1, 0x00000000U);
218 LL_RCC_WriteReg(CFGR2, 0x00000000U);
219
220 /* Wait till clock switch is ready */
221 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
222 {
223 }
224
225 #if defined(RCC_CR_PLL3ON)
226 /* Reset HSECSSON, HSEON, HSIKERON, CSION, CSIKERON, HSI48ON, PLL1ON, PLL2ON and PLL3ON bits */
227 CLEAR_BIT(RCC->CR, RCC_CR_CSION | RCC_CR_CSIKERON | RCC_CR_HSECSSON | RCC_CR_HSIKERON | RCC_CR_HSI48ON |
228 RCC_CR_HSEON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
229 #else
230 /* Reset HSECSSON, HSEON, HSIKERON, CSION, CSIKERON, HSI48ON, PLL1ON, PLL2ON and PLL3ON bits */
231 CLEAR_BIT(RCC->CR, RCC_CR_CSION | RCC_CR_CSIKERON | RCC_CR_HSECSSON | RCC_CR_HSIKERON | RCC_CR_HSI48ON |
232 RCC_CR_HSEON | RCC_CR_PLL1ON | RCC_CR_PLL2ON);
233 #endif /* PLL3 */
234
235 /* Wait for PLL1 READY bit to be reset */
236 while (LL_RCC_PLL1_IsReady() != 0U)
237 {}
238
239 /* Wait for PLL2 READY bit to be reset */
240 while (LL_RCC_PLL2_IsReady() != 0U)
241 {}
242
243 #if defined(RCC_CR_PLL3ON)
244 /* Wait for PLL3 READY bit to be reset */
245 while (LL_RCC_PLL3_IsReady() != 0U)
246 {}
247 #endif /* PLL3 */
248
249 /* Reset PLL1CFGR register */
250 CLEAR_REG(RCC->PLL1CFGR);
251
252 /* Reset PLL1DIVR register */
253 LL_RCC_WriteReg(PLL1DIVR, 0x01010280U);
254
255 /* Reset PLL1FRACR register */
256 CLEAR_REG(RCC->PLL1FRACR);
257
258 /* Reset PLL2CFGR register */
259 CLEAR_REG(RCC->PLL2CFGR);
260
261 /* Reset PLL2DIVR register */
262 LL_RCC_WriteReg(PLL2DIVR, 0x01010280U);
263
264 /* Reset PLL2FRACR register */
265 CLEAR_REG(RCC->PLL2FRACR);
266
267 #if defined(RCC_CR_PLL3ON)
268 /* Reset PLL3CFGR register */
269 CLEAR_REG(RCC->PLL3CFGR);
270
271 /* Reset PLL3DIVR register */
272 LL_RCC_WriteReg(PLL3DIVR, 0x01010280U);
273
274 /* Reset PLL3FRACR register */
275 CLEAR_REG(RCC->PLL3FRACR);
276 #endif /* PLL3 */
277
278 /* Reset HSEBYP bit */
279 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
280
281 /* Reset HSEEXT bit */
282 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);
283
284 #if defined(RCC_CR_PLL3ON)
285 /* Disable all interrupts */
286 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE | RCC_CIER_LSERDYIE | RCC_CIER_HSIRDYIE | RCC_CIER_HSERDYIE
287 | RCC_CIER_CSIRDYIE | RCC_CIER_HSI48RDYIE | RCC_CIER_PLL1RDYIE | RCC_CIER_PLL2RDYIE
288 | RCC_CIER_PLL3RDYIE);
289
290 /* Clear all interrupt flags */
291 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC
292 | RCC_CICR_CSIRDYC | RCC_CICR_HSI48RDYC | RCC_CICR_PLL1RDYC | RCC_CICR_PLL2RDYC
293 | RCC_CICR_PLL3RDYC | RCC_CICR_HSECSSC);
294 #else
295 /* Disable all interrupts */
296 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE | RCC_CIER_LSERDYIE | RCC_CIER_HSIRDYIE | RCC_CIER_HSERDYIE
297 | RCC_CIER_CSIRDYIE | RCC_CIER_HSI48RDYIE | RCC_CIER_PLL1RDYIE | RCC_CIER_PLL2RDYIE);
298
299 /* Clear all interrupt flags */
300 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC
301 | RCC_CICR_CSIRDYC | RCC_CICR_HSI48RDYC | RCC_CICR_PLL1RDYC | RCC_CICR_PLL2RDYC
302 | RCC_CICR_HSECSSC);
303 #endif /* PLL3 */
304
305
306 /* Clear all reset flags */
307 LL_RCC_ClearResetFlags();
308
309 /* Update the SystemCoreClock global variable */
310 SystemCoreClock = HSI_VALUE;
311
312 return SUCCESS;
313 }
314
315 /**
316 * @}
317 */
318
319 /** @addtogroup RCC_LL_EF_Get_Freq
320 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
321 * and different peripheral clocks available on the device.
322 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
323 * @note If SYSCLK source is CSI, function returns values based on CSI_VALUE(**)
324 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
325 * @note If SYSCLK source is PLL1, function returns values based on HSE_VALUE(***)
326 * or HSI_VALUE(**) or CSI_VALUE(*) multiplied/divided by the main PLL factors.
327 * @note (*) HSI_VALUE is a constant defined in this file (default value
328 * 64 MHz) but the real value may vary depending on the variations
329 * in voltage and temperature.
330 * @note (**) CSI_VALUE is a constant defined in this file (default value
331 * 4 MHz) but the real value may vary depending on the variations
332 * in voltage and temperature.
333 * @note (***) HSE_VALUE is a constant defined in this file (default value
334 * 32 MHz), user has to ensure that HSE_VALUE is same as the real
335 * frequency of the crystal used. Otherwise, this function may
336 * have wrong result.
337 * @note The result of this function could be incorrect when using fractional
338 * value for HSE crystal.
339 * @note This function can be used by the user application to compute the
340 * baud-rate for the communication peripherals or configure other parameters.
341 * @{
342 */
343
344 /**
345 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1, APB2 and APB3 buses clocks
346 * @note Each time SYSCLK, HCLK, PCLK1, PCLK2 and PCLK3 clock changes, this function
347 * must be called to update structure fields. Otherwise, any
348 * configuration based on this function will be incorrect.
349 * @param pRCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
350 * @retval None
351 */
LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef * pRCC_Clocks)352 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *pRCC_Clocks)
353 {
354 /* Get SYSCLK frequency */
355 pRCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
356
357 /* HCLK clock frequency */
358 pRCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(pRCC_Clocks->SYSCLK_Frequency);
359
360 /* PCLK1 clock frequency */
361 pRCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(pRCC_Clocks->HCLK_Frequency);
362
363 /* PCLK2 clock frequency */
364 pRCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(pRCC_Clocks->HCLK_Frequency);
365
366 /* PCLK3 clock frequency */
367 pRCC_Clocks->PCLK3_Frequency = RCC_GetPCLK3ClockFreq(pRCC_Clocks->HCLK_Frequency);
368 }
369
370 /**
371 * @brief Return PLL1 clocks frequencies
372 * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
373 * @retval None
374 */
LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef * pPLL_Clocks)375 void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *pPLL_Clocks)
376 {
377 uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO;
378 uint32_t pllsource;
379 uint32_t pllm;
380 uint32_t plln;
381 uint32_t fracn = 0U;
382
383 /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
384 SYSCLK = PLL_VCO / PLLP
385 */
386
387 pPLL_Clocks->PLL_P_Frequency = LL_RCC_PERIPH_FREQUENCY_NO;
388 pPLL_Clocks->PLL_Q_Frequency = LL_RCC_PERIPH_FREQUENCY_NO;
389 pPLL_Clocks->PLL_R_Frequency = LL_RCC_PERIPH_FREQUENCY_NO;
390
391 if (LL_RCC_PLL1_IsReady() != 0U)
392 {
393
394 pllsource = LL_RCC_PLL1_GetSource();
395
396 switch (pllsource)
397 {
398 case LL_RCC_PLL1SOURCE_HSI:
399 if (LL_RCC_HSI_IsReady() != 0U)
400 {
401 pllinputfreq = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
402 }
403 break;
404
405 case LL_RCC_PLL1SOURCE_CSI:
406 if (LL_RCC_CSI_IsReady() != 0U)
407 {
408 pllinputfreq = CSI_VALUE;
409 }
410 break;
411
412 case LL_RCC_PLL1SOURCE_HSE:
413 if (LL_RCC_HSE_IsReady() != 0U)
414 {
415 pllinputfreq = HSE_VALUE;
416 }
417 break;
418
419 case LL_RCC_PLL1SOURCE_NONE:
420 default:
421 /* PLL clock disabled */
422 break;
423 }
424
425 pllm = LL_RCC_PLL1_GetM();
426 plln = LL_RCC_PLL1_GetN();
427
428 if (LL_RCC_PLL1FRACN_IsEnabled() != 0U)
429 {
430 fracn = LL_RCC_PLL1_GetFRACN();
431 }
432
433 if ((pllinputfreq != LL_RCC_PERIPH_FREQUENCY_NO) && (pllm != 0U))
434 {
435 if (LL_RCC_PLL1P_IsEnabled() != 0U)
436 {
437 pPLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL1_GetP());
438 }
439
440 if (LL_RCC_PLL1Q_IsEnabled() != 0U)
441 {
442 pPLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL1_GetQ());
443 }
444
445 if (LL_RCC_PLL1R_IsEnabled() != 0U)
446 {
447 pPLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL1_GetR());
448 }
449 }
450 }
451 }
452
453 /**
454 * @brief Return PLL2 clocks frequencies
455 * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
456 * @retval None
457 */
LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef * pPLL_Clocks)458 void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *pPLL_Clocks)
459 {
460 uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO;
461 uint32_t pllsource;
462 uint32_t pllm;
463 uint32_t plln;
464 uint32_t fracn = 0U;
465
466 /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
467 SYSCLK = PLL_VCO / PLLP
468 */
469
470 pPLL_Clocks->PLL_P_Frequency = LL_RCC_PERIPH_FREQUENCY_NO;
471 pPLL_Clocks->PLL_Q_Frequency = LL_RCC_PERIPH_FREQUENCY_NO;
472 pPLL_Clocks->PLL_R_Frequency = LL_RCC_PERIPH_FREQUENCY_NO;
473
474 if (LL_RCC_PLL2_IsReady() != 0U)
475 {
476
477 pllsource = LL_RCC_PLL2_GetSource();
478
479 switch (pllsource)
480 {
481 case LL_RCC_PLL2SOURCE_HSI:
482 if (LL_RCC_HSI_IsReady() != 0U)
483 {
484 pllinputfreq = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
485 }
486 break;
487
488 case LL_RCC_PLL2SOURCE_CSI:
489 if (LL_RCC_CSI_IsReady() != 0U)
490 {
491 pllinputfreq = CSI_VALUE;
492 }
493 break;
494
495 case LL_RCC_PLL2SOURCE_HSE:
496 if (LL_RCC_HSE_IsReady() != 0U)
497 {
498 pllinputfreq = HSE_VALUE;
499 }
500 break;
501
502 case LL_RCC_PLL2SOURCE_NONE:
503 default:
504 /* PLL clock disabled */
505 break;
506 }
507
508 pllm = LL_RCC_PLL2_GetM();
509 plln = LL_RCC_PLL2_GetN();
510
511 if (LL_RCC_PLL2FRACN_IsEnabled() != 0U)
512 {
513 fracn = LL_RCC_PLL2_GetFRACN();
514 }
515
516 if ((pllinputfreq != LL_RCC_PERIPH_FREQUENCY_NO) && (pllm != 0U))
517 {
518 if (LL_RCC_PLL2P_IsEnabled() != 0U)
519 {
520 pPLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL2_GetP());
521 }
522
523 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
524 {
525 pPLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL2_GetQ());
526 }
527
528 if (LL_RCC_PLL2R_IsEnabled() != 0U)
529 {
530 pPLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL2_GetR());
531 }
532 }
533 }
534 }
535
536 #if defined(RCC_CR_PLL3ON)
537 /**
538 * @brief Return PLL3 clocks frequencies
539 * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
540 * @retval None
541 */
LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef * pPLL_Clocks)542 void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *pPLL_Clocks)
543 {
544 uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO;
545 uint32_t pllsource;
546 uint32_t pllm;
547 uint32_t plln;
548 uint32_t fracn = 0U;
549
550 /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
551 SYSCLK = PLL_VCO / PLLP
552 */
553
554 pPLL_Clocks->PLL_P_Frequency = LL_RCC_PERIPH_FREQUENCY_NO;
555 pPLL_Clocks->PLL_Q_Frequency = LL_RCC_PERIPH_FREQUENCY_NO;
556 pPLL_Clocks->PLL_R_Frequency = LL_RCC_PERIPH_FREQUENCY_NO;
557
558 if (LL_RCC_PLL3_IsReady() != 0U)
559 {
560
561 pllsource = LL_RCC_PLL3_GetSource();
562
563 switch (pllsource)
564 {
565 case LL_RCC_PLL3SOURCE_HSI:
566 if (LL_RCC_HSI_IsReady() != 0U)
567 {
568 pllinputfreq = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
569 }
570 break;
571
572 case LL_RCC_PLL3SOURCE_CSI:
573 if (LL_RCC_CSI_IsReady() != 0U)
574 {
575 pllinputfreq = CSI_VALUE;
576 }
577 break;
578
579 case LL_RCC_PLL3SOURCE_HSE:
580 if (LL_RCC_HSE_IsReady() != 0U)
581 {
582 pllinputfreq = HSE_VALUE;
583 }
584 break;
585
586 case LL_RCC_PLL3SOURCE_NONE:
587 default:
588 /* PLL clock disabled */
589 break;
590 }
591
592 pllm = LL_RCC_PLL3_GetM();
593 plln = LL_RCC_PLL3_GetN();
594 if (LL_RCC_PLL3FRACN_IsEnabled() != 0U)
595 {
596 fracn = LL_RCC_PLL3_GetFRACN();
597 }
598
599 if ((pllinputfreq != LL_RCC_PERIPH_FREQUENCY_NO) && (pllm != 0U))
600 {
601 if (LL_RCC_PLL3P_IsEnabled() != 0U)
602 {
603 pPLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL3_GetP());
604 }
605
606 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
607 {
608 pPLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL3_GetQ());
609 }
610
611 if (LL_RCC_PLL3R_IsEnabled() != 0U)
612 {
613 pPLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL3_GetR());
614 }
615 }
616 }
617 }
618 #endif /* PLL3 */
619
620 /**
621 * @brief Helper function to calculate the PLL1 frequency output
622 * @note ex: @ref LL_RCC_CalcPLLClockFreq (HSE_VALUE, @ref LL_RCC_PLL1_GetM (),
623 * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetFRACN (), @ref LL_RCC_PLL1_GetP ());
624 * @param PLLInputFreq PLL Input frequency (based on HSE/(HSI/HSIDIV)/CSI)
625 * @param M Between 1 and 63
626 * @param N Between 4 and 512
627 * @param FRACN Between 0 and 0x1FFF
628 * @param PQR VCO output divider (P, Q or R)
629 * Between 1 and 128, except for PLL1P Odd value not allowed
630 * @retval PLL1 output clock frequency (in Hz)
631 */
LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq,uint32_t M,uint32_t N,uint32_t FRACN,uint32_t PQR)632 uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR)
633 {
634 float_t freq;
635
636 freq = ((float_t)PLLInputFreq / (float_t)M) * ((float_t)N + ((float_t)FRACN / (float_t)0x2000));
637
638 freq = freq / (float_t)PQR;
639
640 return (uint32_t)freq;
641 }
642
643
644 /**
645 * @brief Return USARTx clock frequency
646 * @param USARTxSource This parameter can be one of the following values:
647 * @arg @ref LL_RCC_USART1_CLKSOURCE
648 * @arg @ref LL_RCC_USART2_CLKSOURCE
649 * @arg @ref LL_RCC_USART3_CLKSOURCE
650 * @arg @ref LL_RCC_USART6_CLKSOURCE (*)
651 * @arg @ref LL_RCC_USART10_CLKSOURCE (*)
652 * @arg @ref LL_RCC_USART11_CLKSOURCE (*)
653 *
654 * (*) : For stm32h56xxx and stm32h57xxx family lines only.
655 * @retval USART clock frequency (in Hz)
656 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready
657 */
LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)658 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
659 {
660 uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
661 LL_PLL_ClocksTypeDef PLL_Clocks;
662
663 /* Check parameter */
664 assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
665
666 if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
667 {
668 /* USART1CLK clock frequency */
669 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
670 {
671 case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */
672 usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
673 break;
674
675 case LL_RCC_USART1_CLKSOURCE_PLL2Q: /* USART1 Clock is PLL2 Q */
676 if (LL_RCC_PLL2_IsReady() != 0U)
677 {
678 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
679 {
680 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
681 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
682 }
683 }
684 break;
685
686 #if defined(LL_RCC_USART1_CLKSOURCE_PLL3Q)
687 case LL_RCC_USART1_CLKSOURCE_PLL3Q: /* USART1 Clock is PLL3 Q */
688 if (LL_RCC_PLL3_IsReady() != 0U)
689 {
690 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
691 {
692 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
693 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
694 }
695 }
696 break;
697 #endif /* LL_RCC_USART1_CLKSOURCE_PLL3 */
698
699 case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
700 if (LL_RCC_HSI_IsReady() == 1U)
701 {
702 usart_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
703 }
704 break;
705
706 case LL_RCC_USART1_CLKSOURCE_CSI: /* USART1 Clock is CSI Osc. */
707 if (LL_RCC_CSI_IsReady() == 1U)
708 {
709 usart_frequency = CSI_VALUE;
710 }
711 break;
712
713 case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
714 if (LL_RCC_LSE_IsReady() == 1U)
715 {
716 usart_frequency = LSE_VALUE;
717 }
718 break;
719
720 default:
721 /* unreachable code */
722 break;
723 }
724 }
725 else if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
726 {
727 /* USART2CLK clock frequency */
728 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
729 {
730 case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
731 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
732 break;
733
734 case LL_RCC_USART2_CLKSOURCE_PLL2Q: /* USART2 Clock is PLL2 Q */
735 if (LL_RCC_PLL2_IsReady() != 0U)
736 {
737 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
738 {
739 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
740 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
741 }
742 }
743 break;
744
745 #if defined(LL_RCC_USART2_CLKSOURCE_PLL3Q)
746 case LL_RCC_USART2_CLKSOURCE_PLL3Q: /* USART2 Clock is PLL3 Q */
747 if (LL_RCC_PLL3_IsReady() != 0U)
748 {
749 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
750 {
751 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
752 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
753 }
754 }
755 break;
756 #endif /* LL_RCC_USART2_CLKSOURCE_PLL3 */
757
758 case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
759 if (LL_RCC_HSI_IsReady() == 1U)
760 {
761 usart_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
762 }
763 break;
764
765 case LL_RCC_USART2_CLKSOURCE_CSI: /* USART2 Clock is CSI Osc. */
766 if (LL_RCC_CSI_IsReady() == 1U)
767 {
768 usart_frequency = CSI_VALUE;
769 }
770 break;
771
772 case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
773 if (LL_RCC_LSE_IsReady() == 1U)
774 {
775 usart_frequency = LSE_VALUE;
776 }
777 break;
778
779 default:
780 /* unreachable code */
781 break;
782 }
783 }
784 else if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
785 {
786 /* USART3CLK clock frequency */
787 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
788 {
789 case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */
790 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
791 break;
792
793 case LL_RCC_USART3_CLKSOURCE_PLL2Q: /* USART3 Clock is PLL2 Q */
794 if (LL_RCC_PLL2_IsReady() != 0U)
795 {
796 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
797 {
798 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
799 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
800 }
801 }
802 break;
803
804 #if defined(LL_RCC_USART3_CLKSOURCE_PLL3Q)
805 case LL_RCC_USART3_CLKSOURCE_PLL3Q: /* USART3 Clock is PLL3 Q */
806 if (LL_RCC_PLL3_IsReady() != 0U)
807 {
808 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
809 {
810 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
811 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
812 }
813 }
814 break;
815 #endif /* LL_RCC_USART3_CLKSOURCE_PLL3 */
816
817 case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */
818 if (LL_RCC_HSI_IsReady() == 1U)
819 {
820 usart_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
821 }
822 break;
823
824 case LL_RCC_USART3_CLKSOURCE_CSI: /* USART3 Clock is CSI Osc. */
825 if (LL_RCC_CSI_IsReady() == 1U)
826 {
827 usart_frequency = CSI_VALUE;
828 }
829 break;
830
831 case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */
832 if (LL_RCC_LSE_IsReady() == 1U)
833 {
834 usart_frequency = LSE_VALUE;
835 }
836 break;
837
838 default:
839 /* unreachable code */
840 break;
841 }
842 }
843
844 #if defined(USART6)
845 else if (USARTxSource == LL_RCC_USART6_CLKSOURCE)
846 {
847 /* USART6CLK clock frequency */
848 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
849 {
850 case LL_RCC_USART6_CLKSOURCE_PCLK1: /* USART6 Clock is PCLK1 */
851 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
852 break;
853
854 case LL_RCC_USART6_CLKSOURCE_PLL2Q: /* USART6 Clock is PLL2 Q */
855 if (LL_RCC_PLL2_IsReady() != 0U)
856 {
857 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
858 {
859 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
860 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
861 }
862 }
863 break;
864
865 case LL_RCC_USART6_CLKSOURCE_PLL3Q: /* USART6 Clock is PLL3 Q */
866 if (LL_RCC_PLL3_IsReady() != 0U)
867 {
868 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
869 {
870 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
871 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
872 }
873 }
874 break;
875
876 case LL_RCC_USART6_CLKSOURCE_HSI: /* USART6 Clock is HSI Osc. */
877 if (LL_RCC_HSI_IsReady() == 1U)
878 {
879 usart_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
880 }
881 break;
882
883 case LL_RCC_USART6_CLKSOURCE_CSI: /* USART6 Clock is CSI Osc. */
884 if (LL_RCC_CSI_IsReady() == 1U)
885 {
886 usart_frequency = CSI_VALUE;
887 }
888 break;
889
890 case LL_RCC_USART6_CLKSOURCE_LSE: /* USART6 Clock is LSE Osc. */
891 if (LL_RCC_LSE_IsReady() == 1U)
892 {
893 usart_frequency = LSE_VALUE;
894 }
895 break;
896
897 default:
898 /* unreachable code */
899 break;
900 }
901 }
902 #endif /* USART6 */
903
904 #if defined(USART10)
905 else if (USARTxSource == LL_RCC_USART10_CLKSOURCE)
906 {
907 /* USART10CLK clock frequency */
908 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
909 {
910 case LL_RCC_USART10_CLKSOURCE_PCLK1: /* USART10 Clock is PCLK1 */
911 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
912 break;
913
914 case LL_RCC_USART10_CLKSOURCE_PLL2Q: /* USART10 Clock is PLL2 Q */
915 if (LL_RCC_PLL2_IsReady() != 0U)
916 {
917 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
918 {
919 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
920 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
921 }
922 }
923 break;
924
925 case LL_RCC_USART10_CLKSOURCE_PLL3Q: /* USART10 Clock is PLL3 Q */
926 if (LL_RCC_PLL3_IsReady() != 0U)
927 {
928 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
929 {
930 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
931 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
932 }
933 }
934 break;
935
936 case LL_RCC_USART10_CLKSOURCE_HSI: /* USART10 Clock is HSI Osc. */
937 if (LL_RCC_HSI_IsReady() == 1U)
938 {
939 usart_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
940 }
941 break;
942
943 case LL_RCC_USART10_CLKSOURCE_CSI: /* USART10 Clock is CSI Osc. */
944 if (LL_RCC_CSI_IsReady() == 1U)
945 {
946 usart_frequency = CSI_VALUE;
947 }
948 break;
949
950 case LL_RCC_USART10_CLKSOURCE_LSE: /* USART10 Clock is LSE Osc. */
951 if (LL_RCC_LSE_IsReady() == 1U)
952 {
953 usart_frequency = LSE_VALUE;
954 }
955 break;
956
957 default:
958 /* unreachable code */
959 break;
960 }
961 }
962 #endif /* USART10 */
963
964 #if defined(USART11)
965 else if (USARTxSource == LL_RCC_USART11_CLKSOURCE)
966 {
967 /* USART11CLK clock frequency */
968 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
969 {
970 case LL_RCC_USART11_CLKSOURCE_PCLK1: /* USART11 Clock is PCLK1 */
971 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
972 break;
973
974 case LL_RCC_USART11_CLKSOURCE_PLL2Q: /* USART11 Clock is PLL2 Q */
975 if (LL_RCC_PLL2_IsReady() != 0U)
976 {
977 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
978 {
979 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
980 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
981 }
982 }
983 break;
984
985 case LL_RCC_USART11_CLKSOURCE_PLL3Q: /* USART11 Clock is PLL3 Q */
986 if (LL_RCC_PLL3_IsReady() != 0U)
987 {
988 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
989 {
990 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
991 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
992 }
993 }
994 break;
995
996 case LL_RCC_USART11_CLKSOURCE_HSI: /* USART11 Clock is HSI Osc. */
997 if (LL_RCC_HSI_IsReady() == 1U)
998 {
999 usart_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
1000 }
1001 break;
1002
1003 case LL_RCC_USART11_CLKSOURCE_CSI: /* USART11 Clock is CSI Osc. */
1004 if (LL_RCC_CSI_IsReady() == 1U)
1005 {
1006 usart_frequency = CSI_VALUE;
1007 }
1008 break;
1009
1010 case LL_RCC_USART11_CLKSOURCE_LSE: /* USART11 Clock is LSE Osc. */
1011 if (LL_RCC_LSE_IsReady() == 1U)
1012 {
1013 usart_frequency = LSE_VALUE;
1014 }
1015 break;
1016
1017 default:
1018 /* unreachable code */
1019 break;
1020 }
1021 }
1022 #endif /* USART11 */
1023 else
1024 {
1025 /* nothing to do */
1026 }
1027
1028 return usart_frequency;
1029 }
1030
1031 #if defined(UART4)
1032 /**
1033 * @brief Return UARTx clock frequency
1034 * @param UARTxSource This parameter can be one of the following values:
1035 * @arg @ref LL_RCC_UART4_CLKSOURCE
1036 * @arg @ref LL_RCC_UART5_CLKSOURCE
1037 * @arg @ref LL_RCC_UART7_CLKSOURCE
1038 * @arg @ref LL_RCC_UART8_CLKSOURCE
1039 * @arg @ref LL_RCC_UART9_CLKSOURCE
1040 * @arg @ref LL_RCC_UART12_CLKSOURCE
1041 * @retval UART clock frequency (in Hz)
1042 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready
1043 */
LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)1044 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
1045 {
1046 uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1047 LL_PLL_ClocksTypeDef PLL_Clocks;
1048
1049 /* Check parameter */
1050 assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
1051
1052 if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
1053 {
1054 /* UART4CLK clock frequency */
1055 switch (LL_RCC_GetUARTClockSource(UARTxSource))
1056 {
1057 case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */
1058 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1059 break;
1060
1061 case LL_RCC_UART4_CLKSOURCE_PLL2Q: /* UART4 Clock is PLL2 Q */
1062 if (LL_RCC_PLL2_IsReady() != 0U)
1063 {
1064 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
1065 {
1066 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1067 uart_frequency = PLL_Clocks.PLL_Q_Frequency;
1068 }
1069 }
1070 break;
1071
1072 case LL_RCC_UART4_CLKSOURCE_PLL3Q: /* UART4 Clock is PLL3 Q */
1073 if (LL_RCC_PLL3_IsReady() != 0U)
1074 {
1075 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
1076 {
1077 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1078 uart_frequency = PLL_Clocks.PLL_Q_Frequency;
1079 }
1080 }
1081 break;
1082
1083 case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */
1084 if (LL_RCC_HSI_IsReady() == 1U)
1085 {
1086 uart_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
1087 }
1088 break;
1089
1090 case LL_RCC_UART4_CLKSOURCE_CSI: /* UART4 Clock is CSI Osc. */
1091 if (LL_RCC_CSI_IsReady() == 1U)
1092 {
1093 uart_frequency = CSI_VALUE;
1094 }
1095 break;
1096
1097 case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */
1098 if (LL_RCC_LSE_IsReady() == 1U)
1099 {
1100 uart_frequency = LSE_VALUE;
1101 }
1102 break;
1103
1104 default:
1105 /* unreachable code */
1106 break;
1107 }
1108 }
1109 else if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
1110 {
1111 /* UART5CLK clock frequency */
1112 switch (LL_RCC_GetUARTClockSource(UARTxSource))
1113 {
1114 case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */
1115 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1116 break;
1117
1118 case LL_RCC_UART5_CLKSOURCE_PLL2Q: /* UART5 Clock is PLL2 Q */
1119 if (LL_RCC_PLL2_IsReady() != 0U)
1120 {
1121 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
1122 {
1123 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1124 uart_frequency = PLL_Clocks.PLL_Q_Frequency;
1125 }
1126 }
1127 break;
1128
1129 case LL_RCC_UART5_CLKSOURCE_PLL3Q: /* UART5 Clock is PLL3 Q */
1130 if (LL_RCC_PLL3_IsReady() != 0U)
1131 {
1132 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
1133 {
1134 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1135 uart_frequency = PLL_Clocks.PLL_Q_Frequency;
1136 }
1137 }
1138 break;
1139
1140 case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */
1141 if (LL_RCC_HSI_IsReady() == 1U)
1142 {
1143 uart_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
1144 }
1145 break;
1146
1147 case LL_RCC_UART5_CLKSOURCE_CSI: /* UART5 Clock is CSI Osc. */
1148 if (LL_RCC_CSI_IsReady() == 1U)
1149 {
1150 uart_frequency = CSI_VALUE;
1151 }
1152 break;
1153
1154 case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */
1155 if (LL_RCC_LSE_IsReady() == 1U)
1156 {
1157 uart_frequency = LSE_VALUE;
1158 }
1159 break;
1160
1161 default:
1162 /* unreachable code */
1163 break;
1164 }
1165 }
1166 #if defined(UART7)
1167 else if (UARTxSource == LL_RCC_UART7_CLKSOURCE)
1168 {
1169 /* UART7CLK clock frequency */
1170 switch (LL_RCC_GetUARTClockSource(UARTxSource))
1171 {
1172 case LL_RCC_UART7_CLKSOURCE_PCLK1: /* UART7 Clock is PCLK1 */
1173 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1174 break;
1175
1176 case LL_RCC_UART7_CLKSOURCE_PLL2Q: /* UART7 Clock is PLL2 Q */
1177 if (LL_RCC_PLL2_IsReady() != 0U)
1178 {
1179 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
1180 {
1181 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1182 uart_frequency = PLL_Clocks.PLL_Q_Frequency;
1183 }
1184 }
1185 break;
1186
1187 case LL_RCC_UART7_CLKSOURCE_PLL3Q: /* UART7 Clock is PLL3 Q */
1188 if (LL_RCC_PLL3_IsReady() != 0U)
1189 {
1190 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
1191 {
1192 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1193 uart_frequency = PLL_Clocks.PLL_Q_Frequency;
1194 }
1195 }
1196 break;
1197
1198 case LL_RCC_UART7_CLKSOURCE_HSI: /* UART7 Clock is HSI Osc. */
1199 if (LL_RCC_HSI_IsReady() == 1U)
1200 {
1201 uart_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
1202 }
1203 break;
1204
1205 case LL_RCC_UART7_CLKSOURCE_CSI: /* UART7 Clock is CSI Osc. */
1206 if (LL_RCC_CSI_IsReady() == 1U)
1207 {
1208 uart_frequency = CSI_VALUE;
1209 }
1210 break;
1211
1212 case LL_RCC_UART7_CLKSOURCE_LSE: /* UART7 Clock is LSE Osc. */
1213 if (LL_RCC_LSE_IsReady() == 1U)
1214 {
1215 uart_frequency = LSE_VALUE;
1216 }
1217 break;
1218
1219 default:
1220 /* unreachable code */
1221 break;
1222 }
1223 }
1224 #endif /* UART7 */
1225 #if defined(UART8)
1226 else if (UARTxSource == LL_RCC_UART8_CLKSOURCE)
1227 {
1228 /* UART8CLK clock frequency */
1229 switch (LL_RCC_GetUARTClockSource(UARTxSource))
1230 {
1231 case LL_RCC_UART8_CLKSOURCE_PCLK1: /* UART8 Clock is PCLK1 */
1232 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1233 break;
1234
1235 case LL_RCC_UART8_CLKSOURCE_PLL2Q: /* UART8 Clock is PLL2 Q */
1236 if (LL_RCC_PLL2_IsReady() != 0U)
1237 {
1238 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
1239 {
1240 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1241 uart_frequency = PLL_Clocks.PLL_Q_Frequency;
1242 }
1243 }
1244 break;
1245
1246 case LL_RCC_UART8_CLKSOURCE_PLL3Q: /* UART8 Clock is PLL3 Q */
1247 if (LL_RCC_PLL3_IsReady() != 0U)
1248 {
1249 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
1250 {
1251 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1252 uart_frequency = PLL_Clocks.PLL_Q_Frequency;
1253 }
1254 }
1255 break;
1256
1257 case LL_RCC_UART8_CLKSOURCE_HSI: /* UART8 Clock is HSI Osc. */
1258 if (LL_RCC_HSI_IsReady() == 1U)
1259 {
1260 uart_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
1261 }
1262 break;
1263
1264 case LL_RCC_UART8_CLKSOURCE_CSI: /* UART8 Clock is CSI Osc. */
1265 if (LL_RCC_CSI_IsReady() == 1U)
1266 {
1267 uart_frequency = CSI_VALUE;
1268 }
1269 break;
1270
1271 case LL_RCC_UART8_CLKSOURCE_LSE: /* UART8 Clock is LSE Osc. */
1272 if (LL_RCC_LSE_IsReady() == 1U)
1273 {
1274 uart_frequency = LSE_VALUE;
1275 }
1276 break;
1277
1278 default:
1279 /* unreachable code */
1280 break;
1281 }
1282 }
1283 #endif /* UART8 */
1284 #if defined(UART9)
1285 else if (UARTxSource == LL_RCC_UART9_CLKSOURCE)
1286 {
1287 /* UART9CLK clock frequency */
1288 switch (LL_RCC_GetUARTClockSource(UARTxSource))
1289 {
1290 case LL_RCC_UART9_CLKSOURCE_PCLK1: /* UART9 Clock is PCLK1 */
1291 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1292 break;
1293
1294 case LL_RCC_UART9_CLKSOURCE_PLL2Q: /* UART9 Clock is PLL2 Q */
1295 if (LL_RCC_PLL2_IsReady() != 0U)
1296 {
1297 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
1298 {
1299 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1300 uart_frequency = PLL_Clocks.PLL_Q_Frequency;
1301 }
1302 }
1303 break;
1304
1305 case LL_RCC_UART9_CLKSOURCE_PLL3Q: /* UART9 Clock is PLL3 Q */
1306 if (LL_RCC_PLL3_IsReady() != 0U)
1307 {
1308 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
1309 {
1310 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1311 uart_frequency = PLL_Clocks.PLL_Q_Frequency;
1312 }
1313 }
1314 break;
1315
1316 case LL_RCC_UART9_CLKSOURCE_HSI: /* UART9 Clock is HSI Osc. */
1317 if (LL_RCC_HSI_IsReady() == 1U)
1318 {
1319 uart_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
1320 }
1321 break;
1322
1323 case LL_RCC_UART9_CLKSOURCE_CSI: /* UART9 Clock is CSI Osc. */
1324 if (LL_RCC_CSI_IsReady() == 1U)
1325 {
1326 uart_frequency = CSI_VALUE;
1327 }
1328 break;
1329
1330 case LL_RCC_UART9_CLKSOURCE_LSE: /* UART9 Clock is LSE Osc. */
1331 if (LL_RCC_LSE_IsReady() == 1U)
1332 {
1333 uart_frequency = LSE_VALUE;
1334 }
1335 break;
1336
1337 default:
1338 /* unreachable code */
1339 break;
1340 }
1341 }
1342 #endif /* UART9 */
1343 #if defined(UART12)
1344 else if (UARTxSource == LL_RCC_UART12_CLKSOURCE)
1345 {
1346 /* UART12CLK clock frequency */
1347 switch (LL_RCC_GetUARTClockSource(UARTxSource))
1348 {
1349 case LL_RCC_UART12_CLKSOURCE_PCLK1: /* UART12 Clock is PCLK1 */
1350 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1351 break;
1352
1353 case LL_RCC_UART12_CLKSOURCE_PLL2Q: /* UART12 Clock is PLL2 Q */
1354 if (LL_RCC_PLL2_IsReady() != 0U)
1355 {
1356 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
1357 {
1358 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1359 uart_frequency = PLL_Clocks.PLL_Q_Frequency;
1360 }
1361 }
1362 break;
1363
1364 case LL_RCC_UART12_CLKSOURCE_PLL3Q: /* UART12 Clock is PLL3 Q */
1365 if (LL_RCC_PLL3_IsReady() != 0U)
1366 {
1367 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
1368 {
1369 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1370 uart_frequency = PLL_Clocks.PLL_Q_Frequency;
1371 }
1372 }
1373 break;
1374
1375 case LL_RCC_UART12_CLKSOURCE_HSI: /* UART12 Clock is HSI Osc. */
1376 if (LL_RCC_HSI_IsReady() == 1U)
1377 {
1378 uart_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
1379 }
1380 break;
1381
1382 case LL_RCC_UART12_CLKSOURCE_CSI: /* UART12 Clock is CSI Osc. */
1383 if (LL_RCC_CSI_IsReady() == 1U)
1384 {
1385 uart_frequency = CSI_VALUE;
1386 }
1387 break;
1388
1389 case LL_RCC_UART12_CLKSOURCE_LSE: /* UART12 Clock is LSE Osc. */
1390 if (LL_RCC_LSE_IsReady() == 1U)
1391 {
1392 uart_frequency = LSE_VALUE;
1393 }
1394 break;
1395
1396 default:
1397 /* unreachable code */
1398 break;
1399 }
1400 }
1401 #endif /* UART12 */
1402 else
1403 {
1404 /* nothing to do */
1405 }
1406
1407 return uart_frequency;
1408 }
1409 #endif /* UART4 */
1410
1411 /**
1412 * @brief Return SPIx clock frequency
1413 * @param SPIxSource This parameter can be one of the following values:
1414 * @arg @ref LL_RCC_SPI1_CLKSOURCE
1415 * @arg @ref LL_RCC_SPI2_CLKSOURCE
1416 * @arg @ref LL_RCC_SPI3_CLKSOURCE
1417 * @arg @ref LL_RCC_SPI4_CLKSOURCE (*)
1418 * @arg @ref LL_RCC_SPI5_CLKSOURCE (*)
1419 * @arg @ref LL_RCC_SPI6_CLKSOURCE (*)
1420 *
1421 * (*) : For stm32h56xxx and stm32h57xxx family lines only.
1422 * @retval SPI clock frequency (in Hz)
1423 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready
1424 */
LL_RCC_GetSPIClockFreq(uint32_t SPIxSource)1425 uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource)
1426 {
1427 uint32_t spi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1428 LL_PLL_ClocksTypeDef PLL_Clocks;
1429
1430 /* Check parameter */
1431 assert_param(IS_LL_RCC_SPI_CLKSOURCE(SPIxSource));
1432
1433 if (SPIxSource == LL_RCC_SPI1_CLKSOURCE)
1434 {
1435 /* SPI1 CLK clock frequency */
1436 switch (LL_RCC_GetSPIClockSource(SPIxSource))
1437 {
1438 case LL_RCC_SPI1_CLKSOURCE_PLL1Q: /* SPI1 Clock is PLL1 Q */
1439 if (LL_RCC_PLL1_IsReady() != 0U)
1440 {
1441 if (LL_RCC_PLL1Q_IsEnabled() != 0U)
1442 {
1443 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1444 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1445 }
1446 }
1447 break;
1448
1449 case LL_RCC_SPI1_CLKSOURCE_PLL2P: /* SPI1 Clock is PLL2 P */
1450 if (LL_RCC_PLL2_IsReady() != 0U)
1451 {
1452 if (LL_RCC_PLL2P_IsEnabled() != 0U)
1453 {
1454 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1455 spi_frequency = PLL_Clocks.PLL_P_Frequency;
1456 }
1457 }
1458 break;
1459
1460 #if defined(LL_RCC_SPI1_CLKSOURCE_PLL3P)
1461 case LL_RCC_SPI1_CLKSOURCE_PLL3P: /* SPI1 Clock is PLL3 P */
1462 if (LL_RCC_PLL3_IsReady() != 0U)
1463 {
1464 if (LL_RCC_PLL3P_IsEnabled() != 0U)
1465 {
1466 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1467 spi_frequency = PLL_Clocks.PLL_P_Frequency;
1468 }
1469 }
1470 break;
1471 #endif /* PLL3 */
1472
1473 case LL_RCC_SPI1_CLKSOURCE_PIN: /* SPI1 Clock is External Clock */
1474 spi_frequency = EXTERNAL_CLOCK_VALUE;
1475 break;
1476
1477 case LL_RCC_SPI1_CLKSOURCE_CLKP: /* SPI1 Clock is CLKP */
1478 spi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_GetCLKPClockSource(LL_RCC_CLKP_CLKSOURCE));
1479 break;
1480
1481 default:
1482 /* unreachable code */
1483 break;
1484 }
1485 }
1486 else if (SPIxSource == LL_RCC_SPI2_CLKSOURCE)
1487 {
1488 /* SPI2 CLK clock frequency */
1489 switch (LL_RCC_GetSPIClockSource(SPIxSource))
1490 {
1491 case LL_RCC_SPI2_CLKSOURCE_PLL1Q: /* SPI2 Clock is PLL1 Q */
1492 if (LL_RCC_PLL1_IsReady() != 0U)
1493 {
1494 if (LL_RCC_PLL1Q_IsEnabled() != 0U)
1495 {
1496 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1497 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1498 }
1499 }
1500 break;
1501
1502 case LL_RCC_SPI2_CLKSOURCE_PLL2P: /* SPI2 Clock is PLL2 P */
1503 if (LL_RCC_PLL2_IsReady() != 0U)
1504 {
1505 if (LL_RCC_PLL2P_IsEnabled() != 0U)
1506 {
1507 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1508 spi_frequency = PLL_Clocks.PLL_P_Frequency;
1509 }
1510 }
1511 break;
1512
1513 #if defined(LL_RCC_SPI2_CLKSOURCE_PLL3P)
1514 case LL_RCC_SPI2_CLKSOURCE_PLL3P: /* SPI2 Clock is PLL3 P */
1515 if (LL_RCC_PLL3_IsReady() != 0U)
1516 {
1517 if (LL_RCC_PLL3P_IsEnabled() != 0U)
1518 {
1519 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1520 spi_frequency = PLL_Clocks.PLL_P_Frequency;
1521 }
1522 }
1523 break;
1524 #endif /* PLL3 */
1525
1526 case LL_RCC_SPI2_CLKSOURCE_PIN: /* SPI2 Clock is External Clock */
1527 spi_frequency = EXTERNAL_CLOCK_VALUE;
1528 break;
1529
1530 case LL_RCC_SPI2_CLKSOURCE_CLKP: /* SPI2 Clock is CLKP */
1531 spi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_GetCLKPClockSource(LL_RCC_CLKP_CLKSOURCE));
1532 break;
1533
1534 default:
1535 /* unreachable code */
1536 break;
1537 }
1538 }
1539 else if (SPIxSource == LL_RCC_SPI3_CLKSOURCE)
1540 {
1541 /* SPI3 CLK clock frequency */
1542 switch (LL_RCC_GetSPIClockSource(SPIxSource))
1543 {
1544 case LL_RCC_SPI3_CLKSOURCE_PLL1Q: /* SPI3 Clock is PLL1 Q */
1545 if (LL_RCC_PLL1_IsReady() != 0U)
1546 {
1547 if (LL_RCC_PLL1Q_IsEnabled() != 0U)
1548 {
1549 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1550 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1551 }
1552 }
1553 break;
1554
1555 case LL_RCC_SPI3_CLKSOURCE_PLL2P: /* SPI3 Clock is PLL2 P*/
1556 if (LL_RCC_PLL2_IsReady() != 0U)
1557 {
1558 if (LL_RCC_PLL2P_IsEnabled() != 0U)
1559 {
1560 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1561 spi_frequency = PLL_Clocks.PLL_P_Frequency;
1562 }
1563 }
1564 break;
1565
1566 #if defined(LL_RCC_SPI3_CLKSOURCE_PLL3P)
1567 case LL_RCC_SPI3_CLKSOURCE_PLL3P: /* SPI3 Clock is PLL3 P*/
1568 if (LL_RCC_PLL3_IsReady() != 0U)
1569 {
1570 if (LL_RCC_PLL3P_IsEnabled() != 0U)
1571 {
1572 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1573 spi_frequency = PLL_Clocks.PLL_P_Frequency;
1574 }
1575 }
1576 break;
1577 #endif /* PLL3 */
1578 case LL_RCC_SPI3_CLKSOURCE_PIN: /* SPI3 Clock is External Clock */
1579 spi_frequency = EXTERNAL_CLOCK_VALUE;
1580 break;
1581
1582 case LL_RCC_SPI3_CLKSOURCE_CLKP: /* SPI3 Clock is CLKP */
1583 spi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_GetCLKPClockSource(LL_RCC_CLKP_CLKSOURCE));
1584 break;
1585
1586 default:
1587 /* unreachable code */
1588 break;
1589 }
1590 }
1591 #if defined(SPI4)
1592 else if (SPIxSource == LL_RCC_SPI4_CLKSOURCE)
1593 {
1594 /* SPI4 CLK clock frequency */
1595 switch (LL_RCC_GetSPIClockSource(SPIxSource))
1596 {
1597 case LL_RCC_SPI4_CLKSOURCE_PCLK2: /* SPI4 Clock is PCLK2 */
1598 spi_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1599 break;
1600
1601 case LL_RCC_SPI4_CLKSOURCE_PLL2Q: /* SPI4 Clock is PLL2 Q*/
1602 if (LL_RCC_PLL2_IsReady() != 0U)
1603 {
1604 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
1605 {
1606 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1607 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1608 }
1609 }
1610 break;
1611
1612 case LL_RCC_SPI4_CLKSOURCE_PLL3Q: /* SPI4 Clock is PLL3 Q*/
1613 if (LL_RCC_PLL3_IsReady() != 0U)
1614 {
1615 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
1616 {
1617 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1618 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1619 }
1620 }
1621 break;
1622
1623 case LL_RCC_SPI4_CLKSOURCE_HSI: /* SPI4 Clock is HSI Osc. */
1624 if (LL_RCC_HSI_IsReady() == 1U)
1625 {
1626 spi_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
1627 }
1628 break;
1629
1630 case LL_RCC_SPI4_CLKSOURCE_CSI: /* SPI4 Clock is CSI Osc. */
1631 if (LL_RCC_CSI_IsReady() == 1U)
1632 {
1633 spi_frequency = CSI_VALUE;
1634 }
1635 break;
1636
1637 case LL_RCC_SPI4_CLKSOURCE_HSE: /* SPI4 Clock is HSE Osc. */
1638 if (LL_RCC_HSE_IsReady() == 1U)
1639 {
1640 spi_frequency = HSE_VALUE;
1641 }
1642 break;
1643
1644 default:
1645 /* unreachable code */
1646 break;
1647 }
1648 }
1649 #endif /* SPI4 */
1650 #if defined(SPI5)
1651 else if (SPIxSource == LL_RCC_SPI5_CLKSOURCE)
1652 {
1653 /* SPI5 CLK clock frequency */
1654 switch (LL_RCC_GetSPIClockSource(SPIxSource))
1655 {
1656 case LL_RCC_SPI5_CLKSOURCE_PCLK3: /* SPI5 Clock is PCLK3 */
1657 spi_frequency = RCC_GetPCLK3ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1658 break;
1659
1660 case LL_RCC_SPI5_CLKSOURCE_PLL2Q: /* SPI5 Clock is PLL2 Q*/
1661 if (LL_RCC_PLL2_IsReady() != 0U)
1662 {
1663 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
1664 {
1665 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1666 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1667 }
1668 }
1669 break;
1670
1671 case LL_RCC_SPI5_CLKSOURCE_PLL3Q: /* SPI5 Clock is PLL3 Q*/
1672 if (LL_RCC_PLL3_IsReady() != 0U)
1673 {
1674 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
1675 {
1676 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1677 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1678 }
1679 }
1680 break;
1681
1682 case LL_RCC_SPI5_CLKSOURCE_HSI: /* SPI5 Clock is HSI Osc. */
1683 if (LL_RCC_HSI_IsReady() == 1U)
1684 {
1685 spi_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
1686 }
1687 break;
1688
1689 case LL_RCC_SPI5_CLKSOURCE_CSI: /* SPI5 Clock is CSI Osc. */
1690 if (LL_RCC_CSI_IsReady() == 1U)
1691 {
1692 spi_frequency = CSI_VALUE;
1693 }
1694 break;
1695
1696 case LL_RCC_SPI5_CLKSOURCE_HSE: /* SPI5 Clock is HSE Osc. */
1697 if (LL_RCC_HSE_IsReady() == 1U)
1698 {
1699 spi_frequency = HSE_VALUE;
1700 }
1701 break;
1702
1703 default:
1704 /* unreachable code */
1705 break;
1706 }
1707 }
1708 #endif /* SPI5 */
1709 #if defined(SPI6)
1710 else if (SPIxSource == LL_RCC_SPI6_CLKSOURCE)
1711 {
1712 /* SPI6 CLK clock frequency */
1713 switch (LL_RCC_GetSPIClockSource(SPIxSource))
1714 {
1715 case LL_RCC_SPI6_CLKSOURCE_PCLK2: /* SPI6 Clock is PCLK2 */
1716 spi_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1717 break;
1718
1719 case LL_RCC_SPI6_CLKSOURCE_PLL2Q: /* SPI6 Clock is PLL2 Q*/
1720 if (LL_RCC_PLL2_IsReady() != 0U)
1721 {
1722 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
1723 {
1724 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1725 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1726 }
1727 }
1728 break;
1729
1730 case LL_RCC_SPI6_CLKSOURCE_PLL3Q: /* SPI6 Clock is PLL3 Q*/
1731 if (LL_RCC_PLL3_IsReady() != 0U)
1732 {
1733 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
1734 {
1735 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1736 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1737 }
1738 }
1739 break;
1740
1741 case LL_RCC_SPI6_CLKSOURCE_HSI: /* SPI6 Clock is HSI Osc. */
1742 if (LL_RCC_HSI_IsReady() == 1U)
1743 {
1744 spi_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
1745 }
1746 break;
1747
1748 case LL_RCC_SPI6_CLKSOURCE_CSI: /* SPI6 Clock is CSI Osc. */
1749 if (LL_RCC_CSI_IsReady() == 1U)
1750 {
1751 spi_frequency = CSI_VALUE;
1752 }
1753 break;
1754
1755 case LL_RCC_SPI6_CLKSOURCE_HSE: /* SPI6 Clock is HSE Osc. */
1756 if (LL_RCC_HSE_IsReady() == 1U)
1757 {
1758 spi_frequency = HSE_VALUE;
1759 }
1760 break;
1761
1762 default:
1763 /* unreachable code */
1764 break;
1765 }
1766 }
1767 #endif /* SPI6 */
1768
1769 else
1770 {
1771 /* nothing to do */
1772 }
1773
1774 return spi_frequency;
1775 }
1776
1777 /**
1778 * @brief Return I2Cx clock frequency
1779 * @param I2CxSource This parameter can be one of the following values:
1780 * @arg @ref LL_RCC_I2C1_CLKSOURCE
1781 * @arg @ref LL_RCC_I2C2_CLKSOURCE
1782 * @arg @ref LL_RCC_I2C3_CLKSOURCE (*)
1783 * @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
1784 *
1785 * (*) : For stm32h56xxx and stm32h57xxx family lines only.
1786 * @retval I2C clock frequency (in Hz)
1787 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready
1788 */
LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)1789 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
1790 {
1791 uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1792 LL_PLL_ClocksTypeDef PLL_Clocks;
1793
1794 /* Check parameter */
1795 assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
1796
1797 if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
1798 {
1799 /* I2C1 CLK clock frequency */
1800 switch (LL_RCC_GetI2CClockSource(I2CxSource))
1801 {
1802 case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */
1803 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1804 break;
1805
1806 #if defined(LL_RCC_I2C1_CLKSOURCE_PLL3R)
1807 case LL_RCC_I2C1_CLKSOURCE_PLL3R: /* I2C1 Clock is PLL3 R */
1808 if (LL_RCC_PLL3_IsReady() != 0U)
1809 {
1810 if (LL_RCC_PLL3R_IsEnabled() != 0U)
1811 {
1812 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1813 i2c_frequency = PLL_Clocks.PLL_R_Frequency;
1814 }
1815 }
1816 break;
1817 #else
1818 case LL_RCC_I2C1_CLKSOURCE_PLL2R: /* I2C1 Clock is PLL2 R */
1819 if (LL_RCC_PLL2_IsReady() != 0U)
1820 {
1821 if (LL_RCC_PLL2R_IsEnabled() != 0U)
1822 {
1823 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1824 i2c_frequency = PLL_Clocks.PLL_R_Frequency;
1825 }
1826 }
1827 break;
1828 #endif /* PLL3 */
1829
1830 case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
1831 if (LL_RCC_HSI_IsReady() == 1U)
1832 {
1833 i2c_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
1834 }
1835 break;
1836
1837 case LL_RCC_I2C1_CLKSOURCE_CSI: /* I2C1 Clock is CSI Osc. */
1838 if (LL_RCC_CSI_IsReady() == 1U)
1839 {
1840 i2c_frequency = CSI_VALUE;
1841 }
1842 break;
1843
1844 default:
1845 /* unreachable code */
1846 break;
1847 }
1848 }
1849 else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
1850 {
1851 /* I2C2 CLK clock frequency */
1852 switch (LL_RCC_GetI2CClockSource(I2CxSource))
1853 {
1854 case LL_RCC_I2C2_CLKSOURCE_PCLK1: /* I2C2 Clock is PCLK1 */
1855 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1856 break;
1857
1858 #if defined(LL_RCC_I2C2_CLKSOURCE_PLL3R)
1859 case LL_RCC_I2C2_CLKSOURCE_PLL3R: /* I2C2 Clock is PLL3 R */
1860 if (LL_RCC_PLL3_IsReady() != 0U)
1861 {
1862 if (LL_RCC_PLL3R_IsEnabled() != 0U)
1863 {
1864 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1865 i2c_frequency = PLL_Clocks.PLL_R_Frequency;
1866 }
1867 }
1868 break;
1869 #else
1870 case LL_RCC_I2C2_CLKSOURCE_PLL2R: /* I2C2 Clock is PLL2 R */
1871 if (LL_RCC_PLL2_IsReady() != 0U)
1872 {
1873 if (LL_RCC_PLL2R_IsEnabled() != 0U)
1874 {
1875 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1876 i2c_frequency = PLL_Clocks.PLL_R_Frequency;
1877 }
1878 }
1879 break;
1880 #endif /* PLL3 */
1881
1882 case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */
1883 if (LL_RCC_HSI_IsReady() == 1U)
1884 {
1885 i2c_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
1886 }
1887 break;
1888
1889 case LL_RCC_I2C2_CLKSOURCE_CSI: /* I2C2 Clock is CSI Osc. */
1890 if (LL_RCC_CSI_IsReady() == 1U)
1891 {
1892 i2c_frequency = CSI_VALUE;
1893 }
1894 break;
1895
1896 default:
1897 /* unreachable code */
1898 break;
1899 }
1900 }
1901 #if defined(I2C3)
1902 else if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
1903 {
1904 /* I2C3 CLK clock frequency */
1905 switch (LL_RCC_GetI2CClockSource(I2CxSource))
1906
1907 {
1908 case LL_RCC_I2C3_CLKSOURCE_PCLK3: /* I2C3 Clock is PCLK3 */
1909 i2c_frequency = RCC_GetPCLK3ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1910 break;
1911
1912 case LL_RCC_I2C3_CLKSOURCE_PLL3R: /* I2C3 Clock is PLL3 R */
1913 if (LL_RCC_PLL3_IsReady() != 0U)
1914 {
1915 if (LL_RCC_PLL3R_IsEnabled() != 0U)
1916 {
1917 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1918 i2c_frequency = PLL_Clocks.PLL_R_Frequency;
1919 }
1920 }
1921 break;
1922
1923 case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
1924 if (LL_RCC_HSI_IsReady() == 1U)
1925 {
1926 i2c_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
1927 }
1928 break;
1929
1930 case LL_RCC_I2C3_CLKSOURCE_CSI: /* I2C3 Clock is CSI Osc. */
1931 if (LL_RCC_CSI_IsReady() == 1U)
1932 {
1933 i2c_frequency = CSI_VALUE;
1934 }
1935 break;
1936
1937 default:
1938 /* unreachable code */
1939 break;
1940 }
1941 }
1942 #endif /* I2C3 */
1943 #if defined(I2C4)
1944 else if (I2CxSource == LL_RCC_I2C4_CLKSOURCE)
1945 {
1946 /* I2C4 CLK clock frequency */
1947 switch (LL_RCC_GetI2CClockSource(I2CxSource))
1948 {
1949 case LL_RCC_I2C4_CLKSOURCE_PCLK3: /* I2C4 Clock is PCLK3 */
1950 i2c_frequency = RCC_GetPCLK3ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1951 break;
1952
1953 case LL_RCC_I2C4_CLKSOURCE_PLL3R: /* I2C4 Clock is PLL3 R */
1954 if (LL_RCC_PLL3_IsReady() != 0U)
1955 {
1956 if (LL_RCC_PLL3R_IsEnabled() != 0U)
1957 {
1958 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1959 i2c_frequency = PLL_Clocks.PLL_R_Frequency;
1960 }
1961 }
1962 break;
1963
1964 case LL_RCC_I2C4_CLKSOURCE_HSI: /* I2C4 Clock is HSI Osc. */
1965 if (LL_RCC_HSI_IsReady() == 1U)
1966 {
1967 i2c_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
1968 }
1969 break;
1970
1971 case LL_RCC_I2C4_CLKSOURCE_CSI: /* I2C4 Clock is CSI Osc. */
1972 if (LL_RCC_CSI_IsReady() == 1U)
1973 {
1974 i2c_frequency = CSI_VALUE;
1975 }
1976 break;
1977
1978 default:
1979 /* unreachable code */
1980 break;
1981 }
1982 }
1983 #endif /* I2C4 */
1984 else
1985 {
1986 /* nothing to do */
1987 }
1988
1989 return i2c_frequency;
1990 }
1991
1992 /**
1993 * @brief Return I3Cx clock frequency
1994 * @param I3CxSource This parameter can be one of the following values:
1995 * @arg @ref LL_RCC_I3C1_CLKSOURCE
1996 * @arg @ref LL_RCC_I3C2_CLKSOURCE (*)
1997 *
1998 * (*) : For stm32h503xx family line only.
1999 * @retval I3C clock frequency (in Hz)
2000 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready or no clock is selected
2001 */
LL_RCC_GetI3CClockFreq(uint32_t I3CxSource)2002 uint32_t LL_RCC_GetI3CClockFreq(uint32_t I3CxSource)
2003 {
2004 uint32_t I3C_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
2005 LL_PLL_ClocksTypeDef PLL_Clocks;
2006
2007 /* Check parameter */
2008 assert_param(IS_LL_RCC_I3C_CLKSOURCE(I3CxSource));
2009
2010
2011 if (I3CxSource == LL_RCC_I3C1_CLKSOURCE)
2012 {
2013 /* I3C1 CLK clock frequency */
2014 switch (LL_RCC_GetI3CClockSource(I3CxSource))
2015 {
2016 case LL_RCC_I3C1_CLKSOURCE_PCLK1: /* I3C1 Clock is PCLK1 */
2017 I3C_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
2018 break;
2019
2020 #if defined(LL_RCC_I3C1_CLKSOURCE_PLL3R)
2021 case LL_RCC_I3C1_CLKSOURCE_PLL3R: /* I3C1 Clock is PLL3 R */
2022 if (LL_RCC_PLL3_IsReady() != 0U)
2023 {
2024 if (LL_RCC_PLL3R_IsEnabled() != 0U)
2025 {
2026 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
2027 I3C_frequency = PLL_Clocks.PLL_R_Frequency;
2028 }
2029 }
2030 break;
2031 #else
2032 case LL_RCC_I3C1_CLKSOURCE_PLL2R: /* I3C1 Clock is PLL2 R */
2033 if (LL_RCC_PLL2_IsReady() != 0U)
2034 {
2035 if (LL_RCC_PLL2R_IsEnabled() != 0U)
2036 {
2037 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2038 I3C_frequency = PLL_Clocks.PLL_R_Frequency;
2039 }
2040 }
2041 break;
2042 #endif /* LL_RCC_I3C1_CLKSOURCE_PLL3R */
2043
2044 case LL_RCC_I3C1_CLKSOURCE_HSI: /* I3C1 Clock is HSI Osc. */
2045 if (LL_RCC_HSI_IsReady() == 1U)
2046 {
2047 I3C_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
2048 }
2049 break;
2050
2051 case LL_RCC_I3C1_CLKSOURCE_NONE: /* No Clock used for I3C1 */
2052 break;
2053
2054 default:
2055 /* unreachable code */
2056 break;
2057 }
2058
2059 }
2060
2061 #if defined (I3C2)
2062 else if (I3CxSource == LL_RCC_I3C2_CLKSOURCE)
2063 {
2064 /* I3C2 CLK clock frequency */
2065 switch (LL_RCC_GetI3CClockSource(I3CxSource))
2066 {
2067 case LL_RCC_I3C2_CLKSOURCE_PCLK3: /* I3C2 Clock is PCLK3 */
2068 I3C_frequency = RCC_GetPCLK3ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
2069 break;
2070
2071 #if defined(RCC_CR_PLL3ON)
2072 case LL_RCC_I3C2_CLKSOURCE_PLL3R: /* I3C2 Clock is PLL3 R */
2073 if (LL_RCC_PLL3_IsReady() != 0U)
2074 {
2075 if (LL_RCC_PLL3R_IsEnabled() != 0U)
2076 {
2077 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
2078 I3C_frequency = PLL_Clocks.PLL_R_Frequency;
2079 }
2080 }
2081 #else
2082 case LL_RCC_I3C2_CLKSOURCE_PLL2R: /* I3C2 Clock is PLL2 R */
2083 if (LL_RCC_PLL2_IsReady() != 0U)
2084 {
2085 if (LL_RCC_PLL2R_IsEnabled() != 0U)
2086 {
2087 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2088 I3C_frequency = PLL_Clocks.PLL_R_Frequency;
2089 }
2090 }
2091 #endif /* PLL3 */
2092 break;
2093
2094 case LL_RCC_I3C2_CLKSOURCE_HSI: /* I3C2 Clock is HSI Osc. */
2095 if (LL_RCC_HSI_IsReady() == 1U)
2096 {
2097 I3C_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
2098 }
2099 break;
2100
2101
2102 case LL_RCC_I3C2_CLKSOURCE_NONE: /* No Clock used for I3C2 */
2103 break;
2104
2105 default:
2106 /* unreachable code */
2107 break;
2108 }
2109 }
2110 #endif /* I3C2 */
2111 else
2112 {
2113 /* nothing to do */
2114 }
2115
2116 return I3C_frequency;
2117 }
2118
2119 /**
2120 * @brief Return LPUARTx clock frequency
2121 * @param LPUARTxSource This parameter can be one of the following values:
2122 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
2123 * @retval LPUART clock frequency (in Hz)
2124 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready
2125 */
LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)2126 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
2127 {
2128 uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
2129 LL_PLL_ClocksTypeDef PLL_Clocks;
2130
2131 /* Check parameter */
2132 assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource));
2133
2134 /* LPUART1CLK clock frequency */
2135 switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
2136 {
2137 case LL_RCC_LPUART1_CLKSOURCE_PCLK3: /* LPUART1 Clock is is PCLK3 */
2138 lpuart_frequency = RCC_GetPCLK3ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
2139 break;
2140
2141 case LL_RCC_LPUART1_CLKSOURCE_PLL2Q: /* LPUART1 Clock is PLL2 Q */
2142 if (LL_RCC_PLL2_IsReady() != 0U)
2143 {
2144 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
2145 {
2146 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2147 lpuart_frequency = PLL_Clocks.PLL_Q_Frequency;
2148 }
2149 }
2150 break;
2151
2152 #if defined(LL_RCC_LPUART1_CLKSOURCE_PLL3Q)
2153 case LL_RCC_LPUART1_CLKSOURCE_PLL3Q: /* LPUART1 Clock is PLL3 Q */
2154 if (LL_RCC_PLL3_IsReady() != 0U)
2155 {
2156 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
2157 {
2158 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
2159 lpuart_frequency = PLL_Clocks.PLL_Q_Frequency;
2160 }
2161 }
2162 break;
2163 #endif /* PLL3 */
2164
2165 case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */
2166 if (LL_RCC_HSI_IsReady() == 1U)
2167 {
2168 lpuart_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
2169 }
2170 break;
2171
2172 case LL_RCC_LPUART1_CLKSOURCE_CSI: /* LPUART1 Clock is CSI Osc. */
2173 if (LL_RCC_CSI_IsReady() == 1U)
2174 {
2175 lpuart_frequency = CSI_VALUE;
2176 }
2177 break;
2178
2179 case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */
2180 if (LL_RCC_LSE_IsReady() == 1U)
2181 {
2182 lpuart_frequency = LSE_VALUE;
2183 }
2184 break;
2185
2186 default:
2187 /* unreachable code */
2188 break;
2189 }
2190
2191 return lpuart_frequency;
2192 }
2193
2194 /**
2195 * @brief Return LPTIMx clock frequency
2196 * @param LPTIMxSource This parameter can be one of the following values:
2197 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
2198 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
2199 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE (*)
2200 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE (*)
2201 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE (*)
2202 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE (*)
2203 *
2204 * (*) : For stm32h56xxx and stm32h57xxx family lines only.
2205 * @retval LPTIM clock frequency (in Hz)
2206 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready
2207 */
LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)2208 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
2209 {
2210 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
2211 LL_PLL_ClocksTypeDef PLL_Clocks;
2212
2213 /* Check parameter */
2214 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
2215
2216 if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
2217 {
2218 /* LPTIM1CLK clock frequency */
2219 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
2220 {
2221 case LL_RCC_LPTIM1_CLKSOURCE_PCLK3: /* LPTIM1 Clock is is PCLK3 */
2222 lptim_frequency = RCC_GetPCLK3ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
2223 break;
2224
2225 case LL_RCC_LPTIM1_CLKSOURCE_PLL2P: /* LPTIM1 Clock is PLL2 P */
2226 if (LL_RCC_PLL2_IsReady() != 0U)
2227 {
2228 if (LL_RCC_PLL2P_IsEnabled() != 0U)
2229 {
2230 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2231 lptim_frequency = PLL_Clocks.PLL_P_Frequency;
2232 }
2233 }
2234 break;
2235
2236 #if defined(LL_RCC_LPTIM1_CLKSOURCE_PLL3R)
2237 case LL_RCC_LPTIM1_CLKSOURCE_PLL3R: /* LPTIM1 Clock is PLL3 R */
2238 if (LL_RCC_PLL3_IsReady() != 0U)
2239 {
2240 if (LL_RCC_PLL3R_IsEnabled() != 0U)
2241 {
2242 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
2243 lptim_frequency = PLL_Clocks.PLL_R_Frequency;
2244 }
2245 }
2246 break;
2247 #endif /* PLL3 */
2248
2249 case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
2250 if (LL_RCC_LSE_IsReady() == 1U)
2251 {
2252 lptim_frequency = LSE_VALUE;
2253 }
2254 break;
2255
2256 case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
2257 if (LL_RCC_LSI_IsReady() == 1U)
2258 {
2259 lptim_frequency = LSI_VALUE;
2260 }
2261 break;
2262
2263 case LL_RCC_LPTIM1_CLKSOURCE_CLKP: /* LPTIM1 Clock is CLKP */
2264 lptim_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_GetCLKPClockSource(LL_RCC_CLKP_CLKSOURCE));
2265 break;
2266
2267 default:
2268 /* unreachable code */
2269 break;
2270 }
2271 }
2272 else if (LPTIMxSource == LL_RCC_LPTIM2_CLKSOURCE)
2273 {
2274 /* LPTIM2CLK clock frequency */
2275 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
2276 {
2277 case LL_RCC_LPTIM2_CLKSOURCE_PCLK1: /* LPTIM2 Clock is is PCLK1 */
2278 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
2279 break;
2280
2281 case LL_RCC_LPTIM2_CLKSOURCE_PLL2P: /* LPTIM2 Clock is PLL2 P */
2282 if (LL_RCC_PLL2_IsReady() != 0U)
2283 {
2284 if (LL_RCC_PLL2P_IsEnabled() != 0U)
2285 {
2286 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2287 lptim_frequency = PLL_Clocks.PLL_P_Frequency;
2288 }
2289 }
2290 break;
2291
2292 #if defined(LL_RCC_LPTIM2_CLKSOURCE_PLL3R)
2293 case LL_RCC_LPTIM2_CLKSOURCE_PLL3R: /* LPTIM2 Clock is PLL3 R */
2294 if (LL_RCC_PLL3_IsReady() != 0U)
2295 {
2296 if (LL_RCC_PLL3R_IsEnabled() != 0U)
2297 {
2298 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
2299 lptim_frequency = PLL_Clocks.PLL_R_Frequency;
2300 }
2301 }
2302 break;
2303 #endif /* PLL3 */
2304
2305 case LL_RCC_LPTIM2_CLKSOURCE_LSE: /* LPTIM2 Clock is LSE Osc. */
2306 if (LL_RCC_LSE_IsReady() == 1U)
2307 {
2308 lptim_frequency = LSE_VALUE;
2309 }
2310 break;
2311
2312 case LL_RCC_LPTIM2_CLKSOURCE_LSI: /* LPTIM2 Clock is LSI Osc. */
2313 if (LL_RCC_LSI_IsReady() == 1U)
2314 {
2315 lptim_frequency = LSI_VALUE;
2316 }
2317 break;
2318
2319 case LL_RCC_LPTIM2_CLKSOURCE_CLKP: /* LPTIM2 Clock is CLKP */
2320 lptim_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_GetCLKPClockSource(LL_RCC_CLKP_CLKSOURCE));
2321 break;
2322
2323 default:
2324 /* unreachable code */
2325 break;
2326 }
2327 }
2328 #if defined(LPTIM3)
2329 else if (LPTIMxSource == LL_RCC_LPTIM3_CLKSOURCE)
2330 {
2331 /* LPTIM3CLK clock frequency */
2332 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
2333 {
2334 case LL_RCC_LPTIM3_CLKSOURCE_PCLK3: /* LPTIM3 Clock is is PCLK3 */
2335 lptim_frequency = RCC_GetPCLK3ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
2336 break;
2337
2338 case LL_RCC_LPTIM3_CLKSOURCE_PLL2P: /* LPTIM3 Clock is PLL2 P */
2339 if (LL_RCC_PLL2_IsReady() != 0U)
2340 {
2341 if (LL_RCC_PLL2P_IsEnabled() != 0U)
2342 {
2343 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2344 lptim_frequency = PLL_Clocks.PLL_P_Frequency;
2345 }
2346 }
2347 break;
2348
2349 case LL_RCC_LPTIM3_CLKSOURCE_PLL3R: /* LPTIM3 Clock is PLL3 R */
2350 if (LL_RCC_PLL3_IsReady() != 0U)
2351 {
2352 if (LL_RCC_PLL3R_IsEnabled() != 0U)
2353 {
2354 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
2355 lptim_frequency = PLL_Clocks.PLL_R_Frequency;
2356 }
2357 }
2358 break;
2359
2360 case LL_RCC_LPTIM3_CLKSOURCE_LSE: /* LPTIM3 Clock is LSE Osc. */
2361 if (LL_RCC_LSE_IsReady() == 1U)
2362 {
2363 lptim_frequency = LSE_VALUE;
2364 }
2365 break;
2366
2367 case LL_RCC_LPTIM3_CLKSOURCE_LSI: /* LPTIM3 Clock is LSI Osc. */
2368 if (LL_RCC_LSI_IsReady() == 1U)
2369 {
2370 lptim_frequency = LSI_VALUE;
2371 }
2372 break;
2373
2374 case LL_RCC_LPTIM3_CLKSOURCE_CLKP: /* LPTIM3 Clock is CLKP */
2375 lptim_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_GetCLKPClockSource(LL_RCC_CLKP_CLKSOURCE));
2376 break;
2377
2378 default:
2379 /* unreachable code */
2380 break;
2381 }
2382 }
2383 #endif /* LPTIM3 */
2384 #if defined(LPTIM4)
2385 else if (LPTIMxSource == LL_RCC_LPTIM4_CLKSOURCE)
2386 {
2387 /* LPTIM4CLK clock frequency */
2388 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
2389 {
2390 case LL_RCC_LPTIM4_CLKSOURCE_PCLK3: /* LPTIM4 Clock is is PCLK3 */
2391 lptim_frequency = RCC_GetPCLK3ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
2392 break;
2393
2394 case LL_RCC_LPTIM4_CLKSOURCE_PLL2P: /* LPTIM4 Clock is PLL2 P */
2395 if (LL_RCC_PLL2_IsReady() != 0U)
2396 {
2397 if (LL_RCC_PLL2P_IsEnabled() != 0U)
2398 {
2399 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2400 lptim_frequency = PLL_Clocks.PLL_P_Frequency;
2401 }
2402 }
2403 break;
2404
2405 case LL_RCC_LPTIM4_CLKSOURCE_PLL3R: /* LPTIM4 Clock is PLL3 R */
2406 if (LL_RCC_PLL3_IsReady() != 0U)
2407 {
2408 if (LL_RCC_PLL3R_IsEnabled() != 0U)
2409 {
2410 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
2411 lptim_frequency = PLL_Clocks.PLL_R_Frequency;
2412 }
2413 }
2414 break;
2415
2416 case LL_RCC_LPTIM4_CLKSOURCE_LSE: /* LPTIM4 Clock is LSE Osc. */
2417 if (LL_RCC_LSE_IsReady() == 1U)
2418 {
2419 lptim_frequency = LSE_VALUE;
2420 }
2421 break;
2422
2423 case LL_RCC_LPTIM4_CLKSOURCE_LSI: /* LPTIM4 Clock is LSI Osc. */
2424 if (LL_RCC_LSI_IsReady() == 1U)
2425 {
2426 lptim_frequency = LSI_VALUE;
2427 }
2428 break;
2429
2430 case LL_RCC_LPTIM4_CLKSOURCE_CLKP: /* LPTIM4 Clock is CLKP */
2431 lptim_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_GetCLKPClockSource(LL_RCC_CLKP_CLKSOURCE));
2432 break;
2433
2434 default:
2435 /* unreachable code */
2436 break;
2437 }
2438 }
2439 #endif /* LPTIM4 */
2440 #if defined(LPTIM5)
2441 else if (LPTIMxSource == LL_RCC_LPTIM5_CLKSOURCE)
2442 {
2443 /* LPTIM5CLK clock frequency */
2444 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
2445 {
2446 case LL_RCC_LPTIM5_CLKSOURCE_PCLK3: /* LPTIM5 Clock is is PCLK3 */
2447 lptim_frequency = RCC_GetPCLK3ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
2448 break;
2449
2450 case LL_RCC_LPTIM5_CLKSOURCE_PLL2P: /* LPTIM5 Clock is PLL2 P */
2451 if (LL_RCC_PLL2_IsReady() != 0U)
2452 {
2453 if (LL_RCC_PLL2P_IsEnabled() != 0U)
2454 {
2455 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2456 lptim_frequency = PLL_Clocks.PLL_P_Frequency;
2457 }
2458 }
2459 break;
2460
2461 case LL_RCC_LPTIM5_CLKSOURCE_PLL3R: /* LPTIM5 Clock is PLL3 R */
2462 if (LL_RCC_PLL3_IsReady() != 0U)
2463 {
2464 if (LL_RCC_PLL3R_IsEnabled() != 0U)
2465 {
2466 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
2467 lptim_frequency = PLL_Clocks.PLL_R_Frequency;
2468 }
2469 }
2470 break;
2471
2472 case LL_RCC_LPTIM5_CLKSOURCE_LSE: /* LPTIM5 Clock is LSE Osc. */
2473 if (LL_RCC_LSE_IsReady() == 1U)
2474 {
2475 lptim_frequency = LSE_VALUE;
2476 }
2477 break;
2478
2479 case LL_RCC_LPTIM5_CLKSOURCE_LSI: /* LPTIM5 Clock is LSI Osc. */
2480 if (LL_RCC_LSI_IsReady() == 1U)
2481 {
2482 lptim_frequency = LSI_VALUE;
2483 }
2484 break;
2485
2486 case LL_RCC_LPTIM5_CLKSOURCE_CLKP: /* LPTIM5 Clock is CLKP */
2487 lptim_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_GetCLKPClockSource(LL_RCC_CLKP_CLKSOURCE));
2488 break;
2489
2490 default:
2491 /* unreachable code */
2492 break;
2493 }
2494 }
2495 #endif /* LPTIM5 */
2496 #if defined(LPTIM6)
2497 else if (LPTIMxSource == LL_RCC_LPTIM6_CLKSOURCE)
2498 {
2499 /* LPTIM6CLK clock frequency */
2500 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
2501 {
2502 case LL_RCC_LPTIM6_CLKSOURCE_PCLK3: /* LPTIM6 Clock is is PCLK3 */
2503 lptim_frequency = RCC_GetPCLK3ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
2504 break;
2505
2506 case LL_RCC_LPTIM6_CLKSOURCE_PLL2P: /* LPTIM6 Clock is PLL2 P */
2507 if (LL_RCC_PLL2_IsReady() != 0U)
2508 {
2509 if (LL_RCC_PLL2P_IsEnabled() != 0U)
2510 {
2511 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2512 lptim_frequency = PLL_Clocks.PLL_P_Frequency;
2513 }
2514 }
2515 break;
2516
2517 case LL_RCC_LPTIM6_CLKSOURCE_PLL3R: /* LPTIM6 Clock is PLL3 R */
2518 if (LL_RCC_PLL3_IsReady() != 0U)
2519 {
2520 if (LL_RCC_PLL3R_IsEnabled() != 0U)
2521 {
2522 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
2523 lptim_frequency = PLL_Clocks.PLL_R_Frequency;
2524 }
2525 }
2526 break;
2527
2528 case LL_RCC_LPTIM6_CLKSOURCE_LSE: /* LPTIM6 Clock is LSE Osc. */
2529 if (LL_RCC_LSE_IsReady() == 1U)
2530 {
2531 lptim_frequency = LSE_VALUE;
2532 }
2533 break;
2534
2535 case LL_RCC_LPTIM6_CLKSOURCE_LSI: /* LPTIM6 Clock is LSI Osc. */
2536 if (LL_RCC_LSI_IsReady() == 1U)
2537 {
2538 lptim_frequency = LSI_VALUE;
2539 }
2540 break;
2541
2542 case LL_RCC_LPTIM6_CLKSOURCE_CLKP: /* LPTIM6 Clock is CLKP */
2543 lptim_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_GetCLKPClockSource(LL_RCC_CLKP_CLKSOURCE));
2544 break;
2545
2546 default:
2547 /* unreachable code */
2548 break;
2549 }
2550 }
2551 #endif /* LPTIM6 */
2552 else
2553 {
2554 /* nothing to do */
2555 }
2556
2557 return lptim_frequency;
2558 }
2559
2560 #if defined(SAI1)
2561 /**
2562 * @brief Return SAIx clock frequency
2563 * @param SAIxSource This parameter can be one of the following values:
2564 * @arg @ref LL_RCC_SAI1_CLKSOURCE
2565 * @arg @ref LL_RCC_SAI2_CLKSOURCE
2566 * @retval SAI clock frequency (in Hz)
2567 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
2568 */
LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)2569 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
2570 {
2571 uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
2572 LL_PLL_ClocksTypeDef PLL_Clocks;
2573
2574 /* Check parameter */
2575 assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
2576
2577 if (SAIxSource == LL_RCC_SAI1_CLKSOURCE)
2578 {
2579 /* SAI1CLK clock frequency */
2580 switch (LL_RCC_GetSAIClockSource(SAIxSource))
2581 {
2582 case LL_RCC_SAI1_CLKSOURCE_PLL1Q: /* PLL1 Q clock used as SAI1 clock source */
2583 if (LL_RCC_PLL1_IsReady() != 0U)
2584 {
2585 if (LL_RCC_PLL1Q_IsEnabled() != 0U)
2586 {
2587 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
2588 sai_frequency = PLL_Clocks.PLL_Q_Frequency;
2589 }
2590 }
2591 break;
2592
2593 case LL_RCC_SAI1_CLKSOURCE_PLL2P: /* PLL2 P clock used as SAI1 clock source */
2594 if (LL_RCC_PLL2_IsReady() != 0U)
2595 {
2596 if (LL_RCC_PLL2P_IsEnabled() != 0U)
2597 {
2598 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2599 sai_frequency = PLL_Clocks.PLL_P_Frequency;
2600 }
2601 }
2602 break;
2603
2604 case LL_RCC_SAI1_CLKSOURCE_PLL3P: /* PLL3 P clock used as SAI1 clock source */
2605 if (LL_RCC_PLL3_IsReady() != 0U)
2606 {
2607 if (LL_RCC_PLL3P_IsEnabled() != 0U)
2608 {
2609 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
2610 sai_frequency = PLL_Clocks.PLL_P_Frequency;
2611 }
2612 }
2613 break;
2614
2615 case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */
2616 sai_frequency = EXTERNAL_CLOCK_VALUE;
2617 break;
2618
2619 case LL_RCC_SAI1_CLKSOURCE_CLKP: /* CLKP used as SAI1 clock source */
2620 sai_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_GetCLKPClockSource(LL_RCC_CLKP_CLKSOURCE));
2621 break;
2622
2623 default:
2624 /* unreachable code */
2625 break;
2626 }
2627 }
2628 else if (SAIxSource == LL_RCC_SAI2_CLKSOURCE)
2629 {
2630 /* SAI2CLK clock frequency */
2631 switch (LL_RCC_GetSAIClockSource(SAIxSource))
2632 {
2633 case LL_RCC_SAI2_CLKSOURCE_PLL1Q: /* PLL1 Q clock used as SAI2 clock source */
2634 if (LL_RCC_PLL1_IsReady() != 0U)
2635 {
2636 if (LL_RCC_PLL1Q_IsEnabled() != 0U)
2637 {
2638 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
2639 sai_frequency = PLL_Clocks.PLL_Q_Frequency;
2640 }
2641 }
2642 break;
2643
2644 case LL_RCC_SAI2_CLKSOURCE_PLL2P: /* PLL2 P clock used as SAI2 clock source */
2645 if (LL_RCC_PLL2_IsReady() != 0U)
2646 {
2647 if (LL_RCC_PLL2P_IsEnabled() != 0U)
2648 {
2649 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2650 sai_frequency = PLL_Clocks.PLL_P_Frequency;
2651 }
2652 }
2653 break;
2654
2655 case LL_RCC_SAI2_CLKSOURCE_PLL3P: /* PLL3 P clock used as SAI2 clock source */
2656 if (LL_RCC_PLL3_IsReady() != 0U)
2657 {
2658 if (LL_RCC_PLL3P_IsEnabled() != 0U)
2659 {
2660 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
2661 sai_frequency = PLL_Clocks.PLL_P_Frequency;
2662 }
2663 }
2664 break;
2665
2666 case LL_RCC_SAI2_CLKSOURCE_PIN: /* External input clock used as SAI2 clock source */
2667 sai_frequency = EXTERNAL_CLOCK_VALUE;
2668 break;
2669
2670 case LL_RCC_SAI2_CLKSOURCE_CLKP: /* SAI2 Clock is CLKP */
2671 sai_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_GetCLKPClockSource(LL_RCC_CLKP_CLKSOURCE));
2672 break;
2673
2674 default:
2675 /* unreachable code */
2676 break;
2677 }
2678 }
2679 else
2680 {
2681 /* nothing to do */
2682 }
2683
2684 return sai_frequency;
2685 }
2686 #endif /* SAI1 */
2687
2688 #if defined(SDMMC1)
2689 /**
2690 * @brief Return SDMMCx clock frequency
2691 * @param SDMMCxSource This parameter can be one of the following values:
2692 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE
2693 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE (*)
2694 * @retval SDMMC clock frequency (in Hz)
2695 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready
2696 *
2697 * (*) : Available on some STM32H5 lines only.
2698 */
LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)2699 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
2700 {
2701 uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
2702 LL_PLL_ClocksTypeDef PLL_Clocks;
2703
2704 /* Check parameter */
2705 assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource));
2706
2707 if (SDMMCxSource == LL_RCC_SDMMC1_CLKSOURCE)
2708 {
2709 /* SDMMC1CLK clock frequency */
2710 switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
2711 {
2712 case LL_RCC_SDMMC1_CLKSOURCE_PLL1Q: /* PLL1 Q clock used as SDMMC1 clock source */
2713 if (LL_RCC_PLL1_IsReady() != 0U)
2714 {
2715 if (LL_RCC_PLL1Q_IsEnabled() != 0U)
2716 {
2717 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
2718 sdmmc_frequency = PLL_Clocks.PLL_Q_Frequency;
2719 }
2720 }
2721 break;
2722
2723 case LL_RCC_SDMMC1_CLKSOURCE_PLL2R: /* PLL2 R clock used as SDMMC1 clock source */
2724 if (LL_RCC_PLL2_IsReady() != 0U)
2725 {
2726 if (LL_RCC_PLL2R_IsEnabled() != 0U)
2727 {
2728 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2729 sdmmc_frequency = PLL_Clocks.PLL_R_Frequency;
2730 }
2731 }
2732 break;
2733
2734 default:
2735 /* unreachable code */
2736 break;
2737 }
2738 }
2739
2740 #if defined(SDMMC2)
2741 else if (SDMMCxSource == LL_RCC_SDMMC2_CLKSOURCE)
2742 {
2743 /* SDMMC2CLK clock frequency */
2744 switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
2745 {
2746 case LL_RCC_SDMMC2_CLKSOURCE_PLL1Q: /* PLL1 Q clock used as SDMMC2 clock source */
2747 if (LL_RCC_PLL1_IsReady() != 0U)
2748 {
2749 if (LL_RCC_PLL1Q_IsEnabled() != 0U)
2750 {
2751 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
2752 sdmmc_frequency = PLL_Clocks.PLL_Q_Frequency;
2753 }
2754 }
2755 break;
2756
2757 case LL_RCC_SDMMC2_CLKSOURCE_PLL2R: /* PLL2 R clock used as SDMMC2 clock source */
2758 if (LL_RCC_PLL2_IsReady() != 0U)
2759 {
2760 if (LL_RCC_PLL2R_IsEnabled() != 0U)
2761 {
2762 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2763 sdmmc_frequency = PLL_Clocks.PLL_R_Frequency;
2764 }
2765 }
2766 break;
2767
2768 default:
2769 /* unreachable code */
2770 break;
2771 }
2772 }
2773 #endif /* SDMMC2 */
2774
2775 else
2776 {
2777 /* nothing to do */
2778 }
2779
2780 return sdmmc_frequency;
2781 }
2782 #endif /* SDMMC1 */
2783
2784 /**
2785 * @brief Return RNGx clock frequency
2786 * @param RNGxSource This parameter can be one of the following values:
2787 * @arg @ref LL_RCC_RNG_CLKSOURCE
2788 * @retval RNG clock frequency (in Hz)
2789 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready
2790 */
LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)2791 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
2792 {
2793 uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
2794 LL_PLL_ClocksTypeDef PLL_Clocks;
2795
2796 /* Check parameter */
2797 assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
2798
2799 /* RNGCLK clock frequency */
2800 switch (LL_RCC_GetRNGClockSource(RNGxSource))
2801 {
2802 case LL_RCC_RNG_CLKSOURCE_HSI48: /* HSI48 clock used as RNG clock source */
2803 if (LL_RCC_HSI48_IsReady() == 1U)
2804 {
2805 rng_frequency = HSI48_VALUE;
2806 }
2807 break;
2808
2809 case LL_RCC_RNG_CLKSOURCE_PLL1Q: /* PLL1 Q clock used as RNG clock source */
2810 if (LL_RCC_PLL1_IsReady() != 0U)
2811 {
2812 if (LL_RCC_PLL1Q_IsEnabled() != 0U)
2813 {
2814 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
2815 rng_frequency = PLL_Clocks.PLL_Q_Frequency;
2816 }
2817 }
2818 break;
2819
2820 case LL_RCC_RNG_CLKSOURCE_LSE: /* LSE clock used as RNG clock source */
2821 if (LL_RCC_LSE_IsReady() == 1U)
2822 {
2823 rng_frequency = LSE_VALUE;
2824 }
2825 break;
2826
2827 case LL_RCC_RNG_CLKSOURCE_LSI: /* LSI clock used as RNG clock source */
2828 if (LL_RCC_LSI_IsReady() == 1U)
2829 {
2830 rng_frequency = LSI_VALUE;
2831 }
2832 break;
2833
2834 default:
2835 /* unreachable code */
2836 break;
2837
2838 }
2839
2840 return rng_frequency;
2841 }
2842
2843 #if defined(USB_DRD_FS)
2844 /**
2845 * @brief Return USBx clock frequency
2846 * @param USBxSource This parameter can be one of the following values:
2847 * @arg @ref LL_RCC_USB_CLKSOURCE
2848 * @retval USB clock frequency (in Hz)
2849 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready or no clock is selected
2850 */
LL_RCC_GetUSBClockFreq(uint32_t USBxSource)2851 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
2852 {
2853 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
2854 LL_PLL_ClocksTypeDef PLL_Clocks;
2855
2856 /* Check parameter */
2857 assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
2858
2859 /* USBCLK clock frequency */
2860 switch (LL_RCC_GetUSBClockSource(USBxSource))
2861 {
2862
2863 case LL_RCC_USB_CLKSOURCE_NONE: /* NO clock used as USB clock source */
2864 break;
2865
2866 case LL_RCC_USB_CLKSOURCE_PLL1Q: /* PLL1 Q clock used as USB clock source */
2867 if (LL_RCC_PLL1_IsReady() != 0U)
2868 {
2869 if (LL_RCC_PLL1Q_IsEnabled() != 0U)
2870 {
2871 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
2872 usb_frequency = PLL_Clocks.PLL_Q_Frequency;
2873 }
2874 }
2875 break;
2876
2877 #if defined(LL_RCC_USB_CLKSOURCE_PLL3Q)
2878 case LL_RCC_USB_CLKSOURCE_PLL3Q: /* PLL3 Q clock used as USB clock source */
2879 if (LL_RCC_PLL3_IsReady() != 0U)
2880 {
2881 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
2882 {
2883 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
2884 usb_frequency = PLL_Clocks.PLL_Q_Frequency;
2885 }
2886 }
2887 break;
2888 #else
2889 case LL_RCC_USB_CLKSOURCE_PLL2Q: /* PLL2 Q clock used as USB clock source */
2890 if (LL_RCC_PLL2_IsReady() != 0U)
2891 {
2892 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
2893 {
2894 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2895 usb_frequency = PLL_Clocks.PLL_Q_Frequency;
2896 }
2897 }
2898 break;
2899 #endif /* LL_RCC_USB_CLKSOURCE_PLL3Q */
2900
2901 case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 clock used as USB clock source */
2902 if (LL_RCC_HSI48_IsReady() == 1U)
2903 {
2904 usb_frequency = HSI48_VALUE;
2905 }
2906 break;
2907
2908 default:
2909 /* unreachable code */
2910 break;
2911 }
2912
2913 return usb_frequency;
2914 }
2915 #endif /* USB_DRD_FS */
2916
2917 /**
2918 * @brief Return ADCxDAC clock frequency
2919 * @param ADCDACxSource This parameter can be one of the following values:
2920 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE
2921 * @retval ADCDAC clock frequency (in Hz)
2922 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready
2923 */
LL_RCC_GetADCDACClockFreq(uint32_t ADCDACxSource)2924 uint32_t LL_RCC_GetADCDACClockFreq(uint32_t ADCDACxSource)
2925 {
2926 uint32_t adcdac_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
2927 LL_PLL_ClocksTypeDef PLL_Clocks;
2928
2929 /* Check parameter */
2930 assert_param(IS_LL_RCC_ADCDAC_CLKSOURCE(ADCDACxSource));
2931
2932 /* ADCCLK clock frequency */
2933 switch (LL_RCC_GetADCDACClockSource(ADCDACxSource))
2934 {
2935 case LL_RCC_ADCDAC_CLKSOURCE_HCLK: /* ADCDAC Clock is AHB clock */
2936 adcdac_frequency = RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq());
2937 break;
2938
2939 case LL_RCC_ADCDAC_CLKSOURCE_SYSCLK: /* ADCDAC Clock is SYSCLK clock */
2940 adcdac_frequency = RCC_GetSystemClockFreq();
2941 break;
2942
2943 case LL_RCC_ADCDAC_CLKSOURCE_PLL2R: /* ADCDAC Clock is PLL2 R */
2944 if (LL_RCC_PLL2_IsReady() != 0U)
2945 {
2946 if (LL_RCC_PLL2R_IsEnabled() != 0U)
2947 {
2948 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2949 adcdac_frequency = PLL_Clocks.PLL_R_Frequency;
2950 }
2951 }
2952 break;
2953
2954 case LL_RCC_ADCDAC_CLKSOURCE_HSE: /* ADCDAC Clock is HSE Osc. */
2955 if (LL_RCC_HSE_IsReady() == 1U)
2956 {
2957 adcdac_frequency = HSE_VALUE;
2958 }
2959 break;
2960
2961 case LL_RCC_ADCDAC_CLKSOURCE_HSI: /* ADCDAC Clock is HSI Osc. */
2962 if (LL_RCC_HSI_IsReady() == 1U)
2963 {
2964 adcdac_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
2965 }
2966 break;
2967
2968 case LL_RCC_ADCDAC_CLKSOURCE_CSI: /* ADCDAC Clock is CSI Osc. */
2969 if (LL_RCC_CSI_IsReady() == 1U)
2970 {
2971 adcdac_frequency = CSI_VALUE;
2972 }
2973 break;
2974
2975 default:
2976 /* unreachable code */
2977 break;
2978 }
2979
2980 return adcdac_frequency;
2981 }
2982
2983 /**
2984 * @brief Return DAC low-power clock frequency
2985 * @param DACLPxSource This parameter can be one of the following values:
2986 * @arg @ref LL_RCC_DAC_LP_CLKSOURCE
2987 * @retval DAC low-power clock frequency (in Hz)
2988 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that LSI or LSE oscillator is not ready
2989 */
LL_RCC_GetDACLPClockFreq(uint32_t DACLPxSource)2990 uint32_t LL_RCC_GetDACLPClockFreq(uint32_t DACLPxSource)
2991 {
2992 uint32_t daclp_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
2993
2994 /* Check parameter */
2995 assert_param(IS_LL_RCC_DAC_LP_CLKSOURCE(DACLPxSource));
2996
2997 /* DAC clock frequency */
2998 switch (LL_RCC_GetDACLPClockSource(DACLPxSource))
2999 {
3000 case LL_RCC_DAC_LP_CLKSOURCE_LSE: /* DAC low-power Clock is LSE Osc. */
3001 if (LL_RCC_LSE_IsReady() == 1U)
3002 {
3003 daclp_frequency = LSE_VALUE;
3004 }
3005 break;
3006
3007 case LL_RCC_DAC_LP_CLKSOURCE_LSI: /* DAC low-power Clock is LSI Osc. */
3008 if (LL_RCC_LSI_IsReady() == 1U)
3009 {
3010 daclp_frequency = LSI_VALUE;
3011 }
3012 break;
3013
3014 default:
3015 /* unreachable code */
3016 break;
3017 }
3018
3019 return daclp_frequency;
3020 }
3021
3022 #if defined( OCTOSPI1)
3023 /**
3024 * @brief Return OCTOSPI clock frequency
3025 * @param OCTOSPIxSource This parameter can be one of the following values:
3026 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE
3027 * @retval OCTOSPI clock frequency (in Hz)
3028 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready
3029 */
LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource)3030 uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource)
3031 {
3032 uint32_t octospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
3033 LL_PLL_ClocksTypeDef PLL_Clocks;
3034
3035 /* Check parameter */
3036 assert_param(IS_LL_RCC_OCTOSPI_CLKSOURCE(OCTOSPIxSource));
3037
3038 /* OCTOSPI clock frequency */
3039 switch (LL_RCC_GetOCTOSPIClockSource(OCTOSPIxSource))
3040 {
3041 case LL_RCC_OSPI_CLKSOURCE_HCLK: /* OCTOSPI clock is SYSCLK */
3042 octospi_frequency = RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq());
3043 break;
3044
3045 case LL_RCC_OSPI_CLKSOURCE_PLL1Q: /* OSPI Clock is PLL1 Q */
3046 if (LL_RCC_PLL1_IsReady() != 0U)
3047 {
3048 if (LL_RCC_PLL1Q_IsEnabled() != 0U)
3049 {
3050 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
3051 octospi_frequency = PLL_Clocks.PLL_Q_Frequency;
3052 }
3053 }
3054 break;
3055
3056 case LL_RCC_OSPI_CLKSOURCE_PLL2R: /* OSPI Clock is PLL2 R */
3057 if (LL_RCC_PLL2_IsReady() != 0U)
3058 {
3059 if (LL_RCC_PLL2R_IsEnabled() != 0U)
3060 {
3061 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
3062 octospi_frequency = PLL_Clocks.PLL_R_Frequency;
3063 }
3064 }
3065 break;
3066
3067 case LL_RCC_OSPI_CLKSOURCE_CLKP: /* OSPI Clock is CLKP */
3068 octospi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_GetCLKPClockSource(LL_RCC_CLKP_CLKSOURCE));
3069 break;
3070
3071 default:
3072 /* unreachable code */
3073 break;
3074 }
3075
3076 return octospi_frequency;
3077 }
3078 #endif /* OCTOSPI1 */
3079
3080 /**
3081 * @brief Return FDCAN kernel clock frequency
3082 * @param FDCANxSource This parameter can be one of the following values:
3083 * @arg @ref LL_RCC_FDCAN_CLKSOURCE
3084 * @retval FDCAN kernel clock frequency (in Hz)
3085 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready or no clock is selected
3086 *
3087 */
LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)3088 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)
3089 {
3090 uint32_t fdcan_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
3091 LL_PLL_ClocksTypeDef PLL_Clocks;
3092
3093 /* Check parameter */
3094 assert_param(IS_LL_RCC_FDCAN_CLKSOURCE(FDCANxSource));
3095
3096 /* FDCANCLK clock frequency */
3097 switch (LL_RCC_GetFDCANClockSource(FDCANxSource))
3098 {
3099 case LL_RCC_FDCAN_CLKSOURCE_HSE: /* HSE clock used as FDCAN clock source */
3100 if (LL_RCC_HSE_IsReady() == 1U)
3101 {
3102 fdcan_frequency = HSE_VALUE;
3103 }
3104 break;
3105
3106 case LL_RCC_FDCAN_CLKSOURCE_PLL1Q: /* PLL1 Q clock used as FDCAN clock source */
3107 if (LL_RCC_PLL1_IsReady() != 0U)
3108 {
3109 if (LL_RCC_PLL1Q_IsEnabled() != 0U)
3110 {
3111 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
3112 fdcan_frequency = PLL_Clocks.PLL_Q_Frequency;
3113 }
3114 }
3115 break;
3116
3117 case LL_RCC_FDCAN_CLKSOURCE_PLL2Q: /* PLL2 Q clock used as FDCAN clock source */
3118 if (LL_RCC_PLL2_IsReady() != 0U)
3119 {
3120 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
3121 {
3122 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
3123 fdcan_frequency = PLL_Clocks.PLL_Q_Frequency;
3124 }
3125 }
3126 break;
3127
3128 case LL_RCC_FDCAN_CLKSOURCE_NONE: /* No clock used as FDCAN clock source */
3129 break;
3130
3131 default:
3132 /* unreachable code */
3133 break;
3134 }
3135
3136 return fdcan_frequency;
3137 }
3138
3139 #if defined(CEC)
3140 /**
3141 * @brief Return CEC clock frequency
3142 * @param CECxSource This parameter can be one of the following values:
3143 * @arg @ref LL_RCC_CEC_CLKSOURCE
3144 * @retval CEC clock frequency (in Hz)
3145 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready or no clock is selected
3146 */
LL_RCC_GetCECClockFreq(uint32_t CECxSource)3147 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
3148 {
3149 uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
3150
3151 switch (LL_RCC_GetCECClockSource(CECxSource))
3152 {
3153 case LL_RCC_CEC_CLKSOURCE_LSE: /* CEC Clock is LSE */
3154 if (LL_RCC_LSE_IsReady() != 0U)
3155 {
3156 cec_frequency = LSE_VALUE;
3157 }
3158 break;
3159
3160 case LL_RCC_CEC_CLKSOURCE_LSI: /* CEC Clock is LSI */
3161 if (LL_RCC_LSI_IsReady() != 0U)
3162 {
3163 cec_frequency = LSI_VALUE;
3164 }
3165 break;
3166
3167 case LL_RCC_CEC_CLKSOURCE_CSI_DIV122: /* CEC Clock is CSI divided by 122 */
3168 if (LL_RCC_CSI_IsReady() != 0U)
3169 {
3170 cec_frequency = CSI_VALUE / 122U;
3171 }
3172 break;
3173
3174 case LL_RCC_CEC_CLKSOURCE_NONE: /* No Clock selected for CEC */
3175 break;
3176
3177 default:
3178 /* Kernel clock disabled */
3179 break;
3180 }
3181
3182 return cec_frequency;
3183 }
3184 #endif /* CEC */
3185
3186 /**
3187 * @brief Return CLKP clock frequency
3188 * @param CLKPxSource This parameter can be one of the following values:
3189 * @arg @ref LL_RCC_CLKP_CLKSOURCE
3190 * @retval CLKP clock frequency (in Hz)
3191 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready or no clock is selected
3192 */
LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource)3193 uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource)
3194 {
3195 uint32_t clkp_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
3196
3197 switch (LL_RCC_GetCLKPClockSource(CLKPxSource))
3198 {
3199 case LL_RCC_CLKP_CLKSOURCE_HSI: /* HSI used as CLKP clock source */
3200 if (LL_RCC_HSI_IsReady() != 0U)
3201 {
3202 clkp_frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
3203 }
3204 break;
3205
3206 case LL_RCC_CLKP_CLKSOURCE_CSI: /* CSI used as CLKP clock source */
3207 if (LL_RCC_CSI_IsReady() != 0U)
3208 {
3209 clkp_frequency = CSI_VALUE;
3210 }
3211 break;
3212
3213 case LL_RCC_CLKP_CLKSOURCE_HSE: /* HSE used as CLKP clock source */
3214 if (LL_RCC_HSE_IsReady() != 0U)
3215 {
3216 clkp_frequency = HSE_VALUE;
3217 }
3218 break;
3219
3220 case LL_RCC_CLKP_CLKSOURCE_NONE: /* NO clock used as CLKP clock source */
3221 break;
3222
3223 default:
3224 /* CLKP clock disabled */
3225 break;
3226 }
3227
3228 return clkp_frequency;
3229 }
3230
3231 /**
3232 * @}
3233 */
3234
3235 /**
3236 * @}
3237 */
3238
3239 /** @addtogroup RCC_LL_Private_Functions
3240 * @{
3241 */
3242
3243 /**
3244 * @brief Return SYSTEM clock frequency
3245 * @retval SYSTEM clock frequency (in Hz)
3246 */
RCC_GetSystemClockFreq(void)3247 uint32_t RCC_GetSystemClockFreq(void)
3248 {
3249 uint32_t frequency;
3250
3251 /* Get SYSCLK source -------------------------------------------------------*/
3252 switch (LL_RCC_GetSysClkSource())
3253 {
3254 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
3255 frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
3256 break;
3257
3258 case LL_RCC_SYS_CLKSOURCE_STATUS_CSI: /* CSI used as system clock source */
3259 frequency = CSI_VALUE;
3260 break;
3261
3262 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
3263 frequency = HSE_VALUE;
3264 break;
3265
3266 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL1: /* PLL1 used as system clock source */
3267 frequency = RCC_PLL1_GetFreqSystem();
3268 break;
3269
3270 default:
3271 frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
3272 break;
3273 }
3274
3275 return frequency;
3276 }
3277
3278 /**
3279 * @brief Return HCLK clock frequency
3280 * @param SYSCLK_Frequency SYSCLK clock frequency
3281 * @retval HCLK clock frequency (in Hz)
3282 */
RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)3283 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
3284 {
3285 /* HCLK clock frequency */
3286 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
3287 }
3288
3289 /**
3290 * @brief Return PCLK1 clock frequency
3291 * @param HCLK_Frequency HCLK clock frequency
3292 * @retval PCLK1 clock frequency (in Hz)
3293 */
RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)3294 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
3295 {
3296 /* PCLK1 clock frequency */
3297 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
3298 }
3299
3300 /**
3301 * @brief Return PCLK2 clock frequency
3302 * @param HCLK_Frequency HCLK clock frequency
3303 * @retval PCLK2 clock frequency (in Hz)
3304 */
RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)3305 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
3306 {
3307 /* PCLK2 clock frequency */
3308 return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
3309 }
3310
3311
3312 /**
3313 * @brief Return PCLK3 clock frequency
3314 * @param HCLK_Frequency HCLK clock frequency
3315 * @retval PCLK3 clock frequency (in Hz)
3316 */
RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency)3317 uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency)
3318 {
3319 /* PCLK3 clock frequency */
3320 return __LL_RCC_CALC_PCLK3_FREQ(HCLK_Frequency, LL_RCC_GetAPB3Prescaler());
3321 }
3322
3323 /**
3324 * @brief Return PLL1 clock frequency used for system clock
3325 * @retval PLL1 clock frequency (in Hz)
3326 */
RCC_PLL1_GetFreqSystem(void)3327 uint32_t RCC_PLL1_GetFreqSystem(void)
3328 {
3329 uint32_t pllinputfreq;
3330 uint32_t pllsource;
3331
3332 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
3333 SYSCLK = PLL_VCO / PLLP
3334 */
3335 pllsource = LL_RCC_PLL1_GetSource();
3336
3337 switch (pllsource)
3338 {
3339 case LL_RCC_PLL1SOURCE_HSI: /* HSI used as PLL1 clock source */
3340 pllinputfreq = __LL_RCC_CALC_HSI_FREQ(LL_RCC_HSI_GetDivider());
3341 break;
3342
3343 case LL_RCC_PLL1SOURCE_CSI: /* CSI used as PLL1 clock source */
3344 pllinputfreq = CSI_VALUE;
3345 break;
3346
3347 case LL_RCC_PLL1SOURCE_HSE: /* HSE used as PLL1 clock source */
3348 pllinputfreq = HSE_VALUE;
3349 break;
3350
3351 default:
3352 pllinputfreq = 0;
3353 break;
3354 }
3355 return __LL_RCC_CALC_PLL1CLK_P_FREQ(pllinputfreq, LL_RCC_PLL1_GetM(),
3356 LL_RCC_PLL1_GetN(), LL_RCC_PLL1_GetP());
3357 }
3358
3359
3360 /**
3361 * @}
3362 */
3363
3364
3365 /**
3366 * @}
3367 */
3368
3369 #endif /* defined(RCC) */
3370
3371 /**
3372 * @}
3373 */
3374
3375 #endif /* USE_FULL_LL_DRIVER */
3376
