1 /**
2   ******************************************************************************
3   * @file    stm32h5xx_ll_fmc.c
4   * @author  MCD Application Team
5   * @brief   FMC Low Layer HAL module driver.
6   *
7   *          This file provides firmware functions to manage the following
8   *          functionalities of the Flexible Memory Controller (FMC) peripheral memories:
9   *           + Initialization/de-initialization functions
10   *           + Peripheral Control functions
11   *           + Peripheral State functions
12   *
13   ******************************************************************************
14   * @attention
15   *
16   * Copyright (c) 2023 STMicroelectronics.
17   * All rights reserved.
18   *
19   * This software is licensed under terms that can be found in the LICENSE file
20   * in the root directory of this software component.
21   * If no LICENSE file comes with this software, it is provided AS-IS.
22   *
23   ******************************************************************************
24   @verbatim
25   ==============================================================================
26                         ##### FMC peripheral features #####
27   ==============================================================================
28   [..] The Flexible memory controller (FMC) includes following memory controllers:
29        (+) The NOR/PSRAM memory controller
30      (+) The NAND memory controller
31        (+) The Synchronous DRAM (SDRAM) controller
32 
33   [..] The FMC functional block makes the interface with synchronous and asynchronous static
34        memories and SDRAM memories. Its main purposes are:
35        (+) to translate AHB transactions into the appropriate external device protocol
36        (+) to meet the access time requirements of the external memory devices
37 
38   [..] All external memories share the addresses, data and control signals with the controller.
39        Each external device is accessed by means of a unique Chip Select. The FMC performs
40        only one access at a time to an external device.
41        The main features of the FMC controller are the following:
42         (+) Interface with static-memory mapped devices including:
43            (++) Static random access memory (SRAM)
44            (++) Read-only memory (ROM)
45            (++) NOR Flash memory/OneNAND Flash memory
46            (++) PSRAM (4 memory banks)
47            (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
48                 data
49         (+) Interface with synchronous DRAM (SDRAM) memories
50         (+) Independent Chip Select control for each memory bank
51         (+) Independent configuration for each memory bank
52 
53   @endverbatim
54   ******************************************************************************
55   */
56 
57 /* Includes ------------------------------------------------------------------*/
58 #include "stm32h5xx_hal.h"
59 
60 /** @addtogroup STM32H5xx_HAL_Driver
61   * @{
62   */
63 #if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)\
64     || defined(HAL_SRAM_MODULE_ENABLED)
65 
66 /** @defgroup FMC_LL  FMC Low Layer
67   * @brief FMC driver modules
68   * @{
69   */
70 
71 /* Private typedef -----------------------------------------------------------*/
72 /* Private define ------------------------------------------------------------*/
73 
74 /** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants
75   * @{
76   */
77 
78 /* ----------------------- FMC registers bit mask --------------------------- */
79 
80 #if defined(FMC_BANK1)
81 /* --- BCR Register ---*/
82 /* BCR register clear mask */
83 
84 /* --- BTR Register ---*/
85 /* BTR register clear mask */
86 #define BTR_CLEAR_MASK    ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD  |\
87                                       FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\
88                                       FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT  |\
89                                       FMC_BTRx_ACCMOD | FMC_BTRx_DATAHLD))
90 
91 /* --- BWTR Register ---*/
92 /* BWTR register clear mask */
93 #define BWTR_CLEAR_MASK   ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD  |\
94                                       FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\
95                                       FMC_BWTRx_ACCMOD | FMC_BWTRx_DATAHLD))
96 #endif /* FMC_BANK1 */
97 #if defined(FMC_BANK3)
98 
99 /* --- PCR Register ---*/
100 /* PCR register clear mask */
101 #define PCR_CLEAR_MASK    ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN  | \
102                                       FMC_PCR_PTYP    | FMC_PCR_PWID   | \
103                                       FMC_PCR_ECCEN   | FMC_PCR_TCLR   | \
104                                       FMC_PCR_TAR     | FMC_PCR_ECCPS))
105 /* --- PMEM Register ---*/
106 /* PMEM register clear mask */
107 #define PMEM_CLEAR_MASK   ((uint32_t)(FMC_PMEM_MEMSET  | FMC_PMEM_MEMWAIT |\
108                                       FMC_PMEM_MEMHOLD | FMC_PMEM_MEMHIZ))
109 
110 /* --- PATT Register ---*/
111 /* PATT register clear mask */
112 #define PATT_CLEAR_MASK   ((uint32_t)(FMC_PATT_ATTSET  | FMC_PATT_ATTWAIT |\
113                                       FMC_PATT_ATTHOLD | FMC_PATT_ATTHIZ))
114 
115 #endif /* FMC_BANK3 */
116 #if defined(FMC_Bank5_6_R)
117 
118 /* --- SDCR Register ---*/
119 /* SDCR register clear mask */
120 #define SDCR_CLEAR_MASK   ((uint32_t)(FMC_SDCRx_NC    | FMC_SDCRx_NR     | \
121                                       FMC_SDCRx_MWID  | FMC_SDCRx_NB     | \
122                                       FMC_SDCRx_CAS   | FMC_SDCRx_WP     | \
123                                       FMC_SDCRx_SDCLK | FMC_SDCRx_RBURST | \
124                                       FMC_SDCRx_RPIPE))
125 
126 /* --- SDTR Register ---*/
127 /* SDTR register clear mask */
128 #define SDTR_CLEAR_MASK   ((uint32_t)(FMC_SDTRx_TMRD  | FMC_SDTRx_TXSR   | \
129                                       FMC_SDTRx_TRAS  | FMC_SDTRx_TRC    | \
130                                       FMC_SDTRx_TWR   | FMC_SDTRx_TRP    | \
131                                       FMC_SDTRx_TRCD))
132 #endif /* FMC_Bank5_6_R */
133 
134 /**
135   * @}
136   */
137 
138 /* Private macro -------------------------------------------------------------*/
139 /* Private variables ---------------------------------------------------------*/
140 /* Private function prototypes -----------------------------------------------*/
141 /* Exported functions --------------------------------------------------------*/
142 
143 /** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
144   * @{
145   */
146 
147 #if defined(FMC_BANK1)
148 
149 /** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions
150   * @brief  NORSRAM Controller functions
151   *
152   @verbatim
153   ==============================================================================
154                    ##### How to use NORSRAM device driver #####
155   ==============================================================================
156 
157   [..]
158     This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
159     to run the NORSRAM external devices.
160 
161     (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
162     (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
163     (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
164     (+) FMC NORSRAM bank extended timing configuration using the function
165         FMC_NORSRAM_Extended_Timing_Init()
166     (+) FMC NORSRAM bank enable/disable write operation using the functions
167         FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
168 
169 @endverbatim
170   * @{
171   */
172 
173 /** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
174   * @brief    Initialization and Configuration functions
175   *
176   @verbatim
177   ==============================================================================
178               ##### Initialization and de_initialization functions #####
179   ==============================================================================
180   [..]
181     This section provides functions allowing to:
182     (+) Initialize and configure the FMC NORSRAM interface
183     (+) De-initialize the FMC NORSRAM interface
184     (+) Configure the FMC clock and associated GPIOs
185 
186 @endverbatim
187   * @{
188   */
189 
190 /**
191   * @brief  Initialize the FMC_NORSRAM device according to the specified
192   *         control parameters in the FMC_NORSRAM_InitTypeDef
193   * @param  Device Pointer to NORSRAM device instance
194   * @param  Init Pointer to NORSRAM Initialization structure
195   * @retval HAL status
196   */
FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef * Device,const FMC_NORSRAM_InitTypeDef * Init)197 HAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
198                                     const FMC_NORSRAM_InitTypeDef *Init)
199 {
200   uint32_t flashaccess;
201   uint32_t btcr_reg;
202   uint32_t mask;
203 
204   /* Check the parameters */
205   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
206   assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
207   assert_param(IS_FMC_MUX(Init->DataAddressMux));
208   assert_param(IS_FMC_MEMORY(Init->MemoryType));
209   assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
210   assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
211   assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
212   assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
213   assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
214   assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
215   assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
216   assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
217   assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
218   assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
219   assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
220   assert_param(IS_FMC_PAGESIZE(Init->PageSize));
221   assert_param(IS_FMC_NBL_SETUPTIME(Init->NBLSetupTime));
222   assert_param(IS_FUNCTIONAL_STATE(Init->MaxChipSelectPulse));
223 
224   /* Disable NORSRAM Device */
225   __FMC_NORSRAM_DISABLE(Device, Init->NSBank);
226 
227   /* Set NORSRAM device control parameters */
228   if (Init->MemoryType == FMC_MEMORY_TYPE_NOR)
229   {
230     flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE;
231   }
232   else
233   {
234     flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE;
235   }
236 
237   btcr_reg = (flashaccess                   | \
238               Init->DataAddressMux          | \
239               Init->MemoryType              | \
240               Init->MemoryDataWidth         | \
241               Init->BurstAccessMode         | \
242               Init->WaitSignalPolarity      | \
243               Init->WaitSignalActive        | \
244               Init->WriteOperation          | \
245               Init->WaitSignal              | \
246               Init->ExtendedMode            | \
247               Init->AsynchronousWait        | \
248               Init->WriteBurst);
249 
250   btcr_reg |= Init->ContinuousClock;
251   btcr_reg |= Init->WriteFifo;
252   btcr_reg |= Init->NBLSetupTime;
253   btcr_reg |= Init->PageSize;
254 
255   mask = (FMC_BCRx_MBKEN                |
256           FMC_BCRx_MUXEN                |
257           FMC_BCRx_MTYP                 |
258           FMC_BCRx_MWID                 |
259           FMC_BCRx_FACCEN               |
260           FMC_BCRx_BURSTEN              |
261           FMC_BCRx_WAITPOL              |
262           FMC_BCRx_WAITCFG              |
263           FMC_BCRx_WREN                 |
264           FMC_BCRx_WAITEN               |
265           FMC_BCRx_EXTMOD               |
266           FMC_BCRx_ASYNCWAIT            |
267           FMC_BCRx_CBURSTRW);
268 
269   mask |= FMC_BCR1_CCLKEN;
270   mask |= FMC_BCR1_WFDIS;
271   mask |= FMC_BCRx_NBLSET;
272   mask |= FMC_BCRx_CPSIZE;
273 
274   MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
275 
276   /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
277   if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
278   {
279     MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);
280   }
281 
282   if (Init->NSBank != FMC_NORSRAM_BANK1)
283   {
284     /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */
285     SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));
286   }
287 
288   /* Check PSRAM chip select counter state */
289   if (Init->MaxChipSelectPulse == ENABLE)
290   {
291     /* Check the parameters */
292     assert_param(IS_FMC_MAX_CHIP_SELECT_PULSE_TIME(Init->MaxChipSelectPulseTime));
293 
294     /* Configure PSRAM chip select counter value */
295     MODIFY_REG(Device->PCSCNTR, FMC_PCSCNTR_CSCOUNT, (uint32_t)(Init->MaxChipSelectPulseTime));
296 
297     /* Enable PSRAM chip select counter for the bank */
298     switch (Init->NSBank)
299     {
300       case FMC_NORSRAM_BANK1 :
301         SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN);
302         break;
303 
304       case FMC_NORSRAM_BANK2 :
305         SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN);
306         break;
307 
308       case FMC_NORSRAM_BANK3 :
309         SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN);
310         break;
311 
312       default :
313         SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN);
314         break;
315     }
316   }
317 
318   return HAL_OK;
319 }
320 
321 /**
322   * @brief  DeInitialize the FMC_NORSRAM peripheral
323   * @param  Device Pointer to NORSRAM device instance
324   * @param  ExDevice Pointer to NORSRAM extended mode device instance
325   * @param  Bank NORSRAM bank number
326   * @retval HAL status
327   */
FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef * Device,FMC_NORSRAM_EXTENDED_TypeDef * ExDevice,uint32_t Bank)328 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
329                                      FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
330 {
331   /* Check the parameters */
332   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
333   assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
334   assert_param(IS_FMC_NORSRAM_BANK(Bank));
335 
336   /* Disable the FMC_NORSRAM device */
337   __FMC_NORSRAM_DISABLE(Device, Bank);
338 
339   /* De-initialize the FMC_NORSRAM device */
340   /* FMC_NORSRAM_BANK1 */
341   if (Bank == FMC_NORSRAM_BANK1)
342   {
343     Device->BTCR[Bank] = 0x000030DBU;
344   }
345   /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
346   else
347   {
348     Device->BTCR[Bank] = 0x000030D2U;
349   }
350 
351   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
352   ExDevice->BWTR[Bank]   = 0x0FFFFFFFU;
353 
354   /* De-initialize PSRAM chip select counter */
355   switch (Bank)
356   {
357     case FMC_NORSRAM_BANK1 :
358       CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN);
359       break;
360 
361     case FMC_NORSRAM_BANK2 :
362       CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN);
363       break;
364 
365     case FMC_NORSRAM_BANK3 :
366       CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN);
367       break;
368 
369     default :
370       CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN);
371       break;
372   }
373 
374   return HAL_OK;
375 }
376 
377 /**
378   * @brief  Initialize the FMC_NORSRAM Timing according to the specified
379   *         parameters in the FMC_NORSRAM_TimingTypeDef
380   * @param  Device Pointer to NORSRAM device instance
381   * @param  Timing Pointer to NORSRAM Timing structure
382   * @param  Bank NORSRAM bank number
383   * @retval HAL status
384   */
FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef * Device,const FMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank)385 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
386                                           const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
387 {
388   uint32_t tmpr;
389 
390   /* Check the parameters */
391   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
392   assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
393   assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
394   assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime));
395   assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
396   assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
397   assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
398   assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
399   assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
400   assert_param(IS_FMC_NORSRAM_BANK(Bank));
401 
402   /* Set FMC_NORSRAM device timing parameters */
403   Device->BTCR[Bank + 1U] =
404     (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) |
405     (Timing->AddressHoldTime << FMC_BTRx_ADDHLD_Pos) |
406     (Timing->DataSetupTime << FMC_BTRx_DATAST_Pos) |
407     (Timing->DataHoldTime << FMC_BTRx_DATAHLD_Pos) |
408     (Timing->BusTurnAroundDuration << FMC_BTRx_BUSTURN_Pos) |
409     ((Timing->CLKDivision - 1U) << FMC_BTRx_CLKDIV_Pos) |
410     ((Timing->DataLatency - 2U) << FMC_BTRx_DATLAT_Pos) |
411     Timing->AccessMode;
412 
413   /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
414   if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
415   {
416     tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos));
417     tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos);
418     MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr);
419   }
420 
421   return HAL_OK;
422 }
423 
424 /**
425   * @brief  Initialize the FMC_NORSRAM Extended mode Timing according to the specified
426   *         parameters in the FMC_NORSRAM_TimingTypeDef
427   * @param  Device Pointer to NORSRAM device instance
428   * @param  Timing Pointer to NORSRAM Timing structure
429   * @param  Bank NORSRAM bank number
430   * @param  ExtendedMode FMC Extended Mode
431   *          This parameter can be one of the following values:
432   *            @arg FMC_EXTENDED_MODE_DISABLE
433   *            @arg FMC_EXTENDED_MODE_ENABLE
434   * @retval HAL status
435   */
FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef * Device,const FMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank,uint32_t ExtendedMode)436 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
437                                                    const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
438                                                    uint32_t ExtendedMode)
439 {
440   /* Check the parameters */
441   assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
442 
443   /* Set NORSRAM device timing register for write configuration, if extended mode is used */
444   if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
445   {
446     /* Check the parameters */
447     assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
448     assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
449     assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
450     assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
451     assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime));
452     assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
453     assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
454     assert_param(IS_FMC_NORSRAM_BANK(Bank));
455 
456     /* Set NORSRAM device timing register for write configuration, if extended mode is used */
457     MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                                    |
458                                                      ((Timing->AddressHoldTime)        << FMC_BWTRx_ADDHLD_Pos)  |
459                                                      ((Timing->DataSetupTime)          << FMC_BWTRx_DATAST_Pos)  |
460                                                      ((Timing->DataHoldTime)           << FMC_BWTRx_DATAHLD_Pos) |
461                                                      Timing->AccessMode                                          |
462                                                      ((Timing->BusTurnAroundDuration)  << FMC_BWTRx_BUSTURN_Pos)));
463   }
464   else
465   {
466     Device->BWTR[Bank] = 0x0FFFFFFFU;
467   }
468 
469   return HAL_OK;
470 }
471 /**
472   * @}
473   */
474 
475 /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
476   *  @brief   management functions
477   *
478 @verbatim
479   ==============================================================================
480                       ##### FMC_NORSRAM Control functions #####
481   ==============================================================================
482   [..]
483     This subsection provides a set of functions allowing to control dynamically
484     the FMC NORSRAM interface.
485 
486 @endverbatim
487   * @{
488   */
489 
490 /**
491   * @brief  Enables dynamically FMC_NORSRAM write operation.
492   * @param  Device Pointer to NORSRAM device instance
493   * @param  Bank NORSRAM bank number
494   * @retval HAL status
495   */
FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef * Device,uint32_t Bank)496 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
497 {
498   /* Check the parameters */
499   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
500   assert_param(IS_FMC_NORSRAM_BANK(Bank));
501 
502   /* Enable write operation */
503   SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
504 
505   return HAL_OK;
506 }
507 
508 /**
509   * @brief  Disables dynamically FMC_NORSRAM write operation.
510   * @param  Device Pointer to NORSRAM device instance
511   * @param  Bank NORSRAM bank number
512   * @retval HAL status
513   */
FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef * Device,uint32_t Bank)514 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
515 {
516   /* Check the parameters */
517   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
518   assert_param(IS_FMC_NORSRAM_BANK(Bank));
519 
520   /* Disable write operation */
521   CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
522 
523   return HAL_OK;
524 }
525 
526 /**
527   * @}
528   */
529 
530 /**
531   * @}
532   */
533 #endif /* FMC_BANK1 */
534 
535 #if defined(FMC_BANK3)
536 
537 /** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions
538   * @brief    NAND Controller functions
539   *
540   @verbatim
541   ==============================================================================
542                     ##### How to use NAND device driver #####
543   ==============================================================================
544   [..]
545     This driver contains a set of APIs to interface with the FMC NAND banks in order
546     to run the NAND external devices.
547 
548     (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
549     (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
550     (+) FMC NAND bank common space timing configuration using the function
551         FMC_NAND_CommonSpace_Timing_Init()
552     (+) FMC NAND bank attribute space timing configuration using the function
553         FMC_NAND_AttributeSpace_Timing_Init()
554     (+) FMC NAND bank enable/disable ECC correction feature using the functions
555         FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
556     (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
557 
558 @endverbatim
559   * @{
560   */
561 
562 /** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
563   *  @brief    Initialization and Configuration functions
564   *
565 @verbatim
566   ==============================================================================
567               ##### Initialization and de_initialization functions #####
568   ==============================================================================
569   [..]
570     This section provides functions allowing to:
571     (+) Initialize and configure the FMC NAND interface
572     (+) De-initialize the FMC NAND interface
573     (+) Configure the FMC clock and associated GPIOs
574 
575 @endverbatim
576   * @{
577   */
578 
579 /**
580   * @brief  Initializes the FMC_NAND device according to the specified
581   *         control parameters in the FMC_NAND_HandleTypeDef
582   * @param  Device Pointer to NAND device instance
583   * @param  Init Pointer to NAND Initialization structure
584   * @retval HAL status
585   */
FMC_NAND_Init(FMC_NAND_TypeDef * Device,const FMC_NAND_InitTypeDef * Init)586 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init)
587 {
588   /* Check the parameters */
589   assert_param(IS_FMC_NAND_DEVICE(Device));
590   assert_param(IS_FMC_NAND_BANK(Init->NandBank));
591   assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
592   assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
593   assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
594   assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
595   assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
596   assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
597 
598   /* NAND bank 3 registers configuration */
599   MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature                            |
600                                            FMC_PCR_MEMORY_TYPE_NAND                     |
601                                            Init->MemoryDataWidth                        |
602                                            Init->EccComputation                         |
603                                            Init->ECCPageSize                            |
604                                            ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos)  |
605                                            ((Init->TARSetupTime)  << FMC_PCR_TAR_Pos)));
606 
607   return HAL_OK;
608 }
609 
610 /**
611   * @brief  Initializes the FMC_NAND Common space Timing according to the specified
612   *         parameters in the FMC_NAND_PCC_TimingTypeDef
613   * @param  Device Pointer to NAND device instance
614   * @param  Timing Pointer to NAND timing structure
615   * @param  Bank NAND bank number
616   * @retval HAL status
617   */
FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef * Device,const FMC_NAND_PCC_TimingTypeDef * Timing,uint32_t Bank)618 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
619                                                    const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
620 {
621   /* Check the parameters */
622   assert_param(IS_FMC_NAND_DEVICE(Device));
623   assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
624   assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
625   assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
626   assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
627   assert_param(IS_FMC_NAND_BANK(Bank));
628 
629   /* Prevent unused argument(s) compilation warning if no assert_param check */
630   UNUSED(Bank);
631 
632   /* NAND bank 3 registers configuration */
633   Device->PMEM = (Timing->SetupTime |
634                   ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) |
635                   ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) |
636                   ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos));
637 
638   return HAL_OK;
639 }
640 
641 /**
642   * @brief  Initializes the FMC_NAND Attribute space Timing according to the specified
643   *         parameters in the FMC_NAND_PCC_TimingTypeDef
644   * @param  Device Pointer to NAND device instance
645   * @param  Timing Pointer to NAND timing structure
646   * @param  Bank NAND bank number
647   * @retval HAL status
648   */
FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef * Device,const FMC_NAND_PCC_TimingTypeDef * Timing,uint32_t Bank)649 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
650                                                       const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
651 {
652   /* Check the parameters */
653   assert_param(IS_FMC_NAND_DEVICE(Device));
654   assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
655   assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
656   assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
657   assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
658   assert_param(IS_FMC_NAND_BANK(Bank));
659 
660   /* Prevent unused argument(s) compilation warning if no assert_param check */
661   UNUSED(Bank);
662 
663   /* NAND bank 3 registers configuration */
664   Device->PATT = (Timing->SetupTime |
665                   ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) |
666                   ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) |
667                   ((Timing->HiZSetupTime)  << FMC_PATT_ATTHIZ_Pos));
668 
669   return HAL_OK;
670 }
671 
672 /**
673   * @brief  DeInitializes the FMC_NAND device
674   * @param  Device Pointer to NAND device instance
675   * @param  Bank NAND bank number
676   * @retval HAL status
677   */
FMC_NAND_DeInit(FMC_NAND_TypeDef * Device,uint32_t Bank)678 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
679 {
680   /* Check the parameters */
681   assert_param(IS_FMC_NAND_DEVICE(Device));
682   assert_param(IS_FMC_NAND_BANK(Bank));
683 
684   /* Disable the NAND Bank */
685   __FMC_NAND_DISABLE(Device, Bank);
686 
687   /* De-initialize the NAND Bank */
688   /* Prevent unused argument(s) compilation warning if no assert_param check */
689   UNUSED(Bank);
690 
691   /* Set the FMC_NAND_BANK3 registers to their reset values */
692   WRITE_REG(Device->PCR,  0x00000018U);
693   WRITE_REG(Device->SR,   0x00000040U);
694   WRITE_REG(Device->PMEM, 0xFCFCFCFCU);
695   WRITE_REG(Device->PATT, 0xFCFCFCFCU);
696 
697   return HAL_OK;
698 }
699 
700 /**
701   * @}
702   */
703 
704 /** @defgroup HAL_FMC_NAND_Group2 Peripheral Control functions
705   *  @brief   management functions
706   *
707 @verbatim
708   ==============================================================================
709                        ##### FMC_NAND Control functions #####
710   ==============================================================================
711   [..]
712     This subsection provides a set of functions allowing to control dynamically
713     the FMC NAND interface.
714 
715 @endverbatim
716   * @{
717   */
718 
719 
720 /**
721   * @brief  Enables dynamically FMC_NAND ECC feature.
722   * @param  Device Pointer to NAND device instance
723   * @param  Bank NAND bank number
724   * @retval HAL status
725   */
FMC_NAND_ECC_Enable(FMC_NAND_TypeDef * Device,uint32_t Bank)726 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
727 {
728   /* Check the parameters */
729   assert_param(IS_FMC_NAND_DEVICE(Device));
730   assert_param(IS_FMC_NAND_BANK(Bank));
731 
732   /* Enable ECC feature */
733   /* Prevent unused argument(s) compilation warning if no assert_param check */
734   UNUSED(Bank);
735 
736   SET_BIT(Device->PCR, FMC_PCR_ECCEN);
737 
738   return HAL_OK;
739 }
740 
741 
742 /**
743   * @brief  Disables dynamically FMC_NAND ECC feature.
744   * @param  Device Pointer to NAND device instance
745   * @param  Bank NAND bank number
746   * @retval HAL status
747   */
FMC_NAND_ECC_Disable(FMC_NAND_TypeDef * Device,uint32_t Bank)748 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
749 {
750   /* Check the parameters */
751   assert_param(IS_FMC_NAND_DEVICE(Device));
752   assert_param(IS_FMC_NAND_BANK(Bank));
753 
754   /* Disable ECC feature */
755   /* Prevent unused argument(s) compilation warning if no assert_param check */
756   UNUSED(Bank);
757 
758   CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);
759 
760   return HAL_OK;
761 }
762 
763 /**
764   * @brief  Disables dynamically FMC_NAND ECC feature.
765   * @param  Device Pointer to NAND device instance
766   * @param  ECCval Pointer to ECC value
767   * @param  Bank NAND bank number
768   * @param  Timeout Timeout wait value
769   * @retval HAL status
770   */
FMC_NAND_GetECC(const FMC_NAND_TypeDef * Device,uint32_t * ECCval,uint32_t Bank,uint32_t Timeout)771 HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
772                                   uint32_t Timeout)
773 {
774   uint32_t tickstart;
775 
776   /* Check the parameters */
777   assert_param(IS_FMC_NAND_DEVICE(Device));
778   assert_param(IS_FMC_NAND_BANK(Bank));
779 
780   /* Get tick */
781   tickstart = HAL_GetTick();
782 
783   /* Wait until FIFO is empty */
784   while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
785   {
786     /* Check for the Timeout */
787     if (Timeout != HAL_MAX_DELAY)
788     {
789       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
790       {
791         return HAL_TIMEOUT;
792       }
793     }
794   }
795 
796   /* Prevent unused argument(s) compilation warning if no assert_param check */
797   UNUSED(Bank);
798 
799   /* Get the ECCR register value */
800   *ECCval = (uint32_t)Device->ECCR;
801 
802   return HAL_OK;
803 }
804 
805 /**
806   * @}
807   */
808 #endif /* FMC_BANK3 */
809 
810 
811 #if defined(FMC_Bank5_6_R)
812 
813 /** @defgroup FMC_LL_SDRAM
814   * @brief    SDRAM Controller functions
815   *
816   @verbatim
817   ==============================================================================
818                      ##### How to use SDRAM device driver #####
819   ==============================================================================
820   [..]
821     This driver contains a set of APIs to interface with the FMC SDRAM banks in order
822     to run the SDRAM external devices.
823 
824     (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
825     (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
826     (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
827     (+) FMC SDRAM bank enable/disable write operation using the functions
828         FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
829     (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
830 
831 @endverbatim
832   * @{
833   */
834 
835 /** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
836   *  @brief    Initialization and Configuration functions
837   *
838 @verbatim
839   ==============================================================================
840               ##### Initialization and de_initialization functions #####
841   ==============================================================================
842   [..]
843     This section provides functions allowing to:
844     (+) Initialize and configure the FMC SDRAM interface
845     (+) De-initialize the FMC SDRAM interface
846     (+) Configure the FMC clock and associated GPIOs
847 
848 @endverbatim
849   * @{
850   */
851 
852 /**
853   * @brief  Initializes the FMC_SDRAM device according to the specified
854   *         control parameters in the FMC_SDRAM_InitTypeDef
855   * @param  Device Pointer to SDRAM device instance
856   * @param  Init Pointer to SDRAM Initialization structure
857   * @retval HAL status
858   */
FMC_SDRAM_Init(FMC_SDRAM_TypeDef * Device,const FMC_SDRAM_InitTypeDef * Init)859 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init)
860 {
861   /* Check the parameters */
862   assert_param(IS_FMC_SDRAM_DEVICE(Device));
863   assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
864   assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
865   assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
866   assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
867   assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
868   assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
869   assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
870   assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
871   assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
872   assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
873 
874   /* Set SDRAM bank configuration parameters */
875   if (Init->SDBank == FMC_SDRAM_BANK1)
876   {
877     MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
878                SDCR_CLEAR_MASK,
879                (Init->ColumnBitsNumber   |
880                 Init->RowBitsNumber      |
881                 Init->MemoryDataWidth    |
882                 Init->InternalBankNumber |
883                 Init->CASLatency         |
884                 Init->WriteProtection    |
885                 Init->SDClockPeriod      |
886                 Init->ReadBurst          |
887                 Init->ReadPipeDelay));
888   }
889   else /* FMC_Bank2_SDRAM */
890   {
891     MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
892                FMC_SDCRx_SDCLK           |
893                FMC_SDCRx_RBURST          |
894                FMC_SDCRx_RPIPE,
895                (Init->SDClockPeriod      |
896                 Init->ReadBurst          |
897                 Init->ReadPipeDelay));
898 
899     MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2],
900                SDCR_CLEAR_MASK,
901                (Init->ColumnBitsNumber   |
902                 Init->RowBitsNumber      |
903                 Init->MemoryDataWidth    |
904                 Init->InternalBankNumber |
905                 Init->CASLatency         |
906                 Init->WriteProtection));
907   }
908 
909   return HAL_OK;
910 }
911 
912 
913 /**
914   * @brief  Initializes the FMC_SDRAM device timing according to the specified
915   *         parameters in the FMC_SDRAM_TimingTypeDef
916   * @param  Device Pointer to SDRAM device instance
917   * @param  Timing Pointer to SDRAM Timing structure
918   * @param  Bank SDRAM bank number
919   * @retval HAL status
920   */
FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef * Device,const FMC_SDRAM_TimingTypeDef * Timing,uint32_t Bank)921 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device,
922                                         const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
923 {
924   /* Check the parameters */
925   assert_param(IS_FMC_SDRAM_DEVICE(Device));
926   assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
927   assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
928   assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
929   assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
930   assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
931   assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
932   assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
933   assert_param(IS_FMC_SDRAM_BANK(Bank));
934 
935   /* Set SDRAM device timing parameters */
936   if (Bank == FMC_SDRAM_BANK1)
937   {
938     MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
939                SDTR_CLEAR_MASK,
940                (((Timing->LoadToActiveDelay) - 1U)                                      |
941                 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTRx_TXSR_Pos) |
942                 (((Timing->SelfRefreshTime) - 1U)      << FMC_SDTRx_TRAS_Pos) |
943                 (((Timing->RowCycleDelay) - 1U)        << FMC_SDTRx_TRC_Pos)  |
944                 (((Timing->WriteRecoveryTime) - 1U)    << FMC_SDTRx_TWR_Pos)  |
945                 (((Timing->RPDelay) - 1U)              << FMC_SDTRx_TRP_Pos)  |
946                 (((Timing->RCDDelay) - 1U)             << FMC_SDTRx_TRCD_Pos)));
947   }
948   else /* FMC_Bank2_SDRAM */
949   {
950     MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
951                FMC_SDTRx_TRC |
952                FMC_SDTRx_TRP,
953                (((Timing->RowCycleDelay) - 1U)         << FMC_SDTRx_TRC_Pos)  |
954                (((Timing->RPDelay) - 1U)               << FMC_SDTRx_TRP_Pos));
955 
956     MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2],
957                SDTR_CLEAR_MASK,
958                (((Timing->LoadToActiveDelay) - 1U)                                      |
959                 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTRx_TXSR_Pos) |
960                 (((Timing->SelfRefreshTime) - 1U)      << FMC_SDTRx_TRAS_Pos) |
961                 (((Timing->WriteRecoveryTime) - 1U)    << FMC_SDTRx_TWR_Pos)  |
962                 (((Timing->RCDDelay) - 1U)             << FMC_SDTRx_TRCD_Pos)));
963   }
964 
965   return HAL_OK;
966 }
967 
968 /**
969   * @brief  DeInitializes the FMC_SDRAM peripheral
970   * @param  Device Pointer to SDRAM device instance
971   * @retval HAL status
972   */
FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef * Device,uint32_t Bank)973 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
974 {
975   /* Check the parameters */
976   assert_param(IS_FMC_SDRAM_DEVICE(Device));
977   assert_param(IS_FMC_SDRAM_BANK(Bank));
978 
979   /* De-initialize the SDRAM device */
980   Device->SDCR[Bank] = 0x000002D0U;
981   Device->SDTR[Bank] = 0x0FFFFFFFU;
982   Device->SDCMR      = 0x00000000U;
983   Device->SDRTR      = 0x00000000U;
984   Device->SDSR       = 0x00000000U;
985 
986   return HAL_OK;
987 }
988 
989 /**
990   * @}
991   */
992 
993 /** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
994   *  @brief   management functions
995   *
996 @verbatim
997   ==============================================================================
998                       ##### FMC_SDRAM Control functions #####
999   ==============================================================================
1000   [..]
1001     This subsection provides a set of functions allowing to control dynamically
1002     the FMC SDRAM interface.
1003 
1004 @endverbatim
1005   * @{
1006   */
1007 
1008 /**
1009   * @brief  Enables dynamically FMC_SDRAM write protection.
1010   * @param  Device Pointer to SDRAM device instance
1011   * @param  Bank SDRAM bank number
1012   * @retval HAL status
1013   */
FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef * Device,uint32_t Bank)1014 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1015 {
1016   /* Check the parameters */
1017   assert_param(IS_FMC_SDRAM_DEVICE(Device));
1018   assert_param(IS_FMC_SDRAM_BANK(Bank));
1019 
1020   /* Enable write protection */
1021   SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
1022 
1023   return HAL_OK;
1024 }
1025 
1026 /**
1027   * @brief  Disables dynamically FMC_SDRAM write protection.
1028   * @param  hsdram FMC_SDRAM handle
1029   * @retval HAL status
1030   */
FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef * Device,uint32_t Bank)1031 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1032 {
1033   /* Check the parameters */
1034   assert_param(IS_FMC_SDRAM_DEVICE(Device));
1035   assert_param(IS_FMC_SDRAM_BANK(Bank));
1036 
1037   /* Disable write protection */
1038   CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
1039 
1040   return HAL_OK;
1041 }
1042 
1043 /**
1044   * @brief  Send Command to the FMC SDRAM bank
1045   * @param  Device Pointer to SDRAM device instance
1046   * @param  Command Pointer to SDRAM command structure
1047   * @param  Timing Pointer to SDRAM Timing structure
1048   * @param  Timeout Timeout wait value
1049   * @retval HAL state
1050   */
FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef * Device,const FMC_SDRAM_CommandTypeDef * Command,uint32_t Timeout)1051 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device,
1052                                         const FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
1053 {
1054   /* Check the parameters */
1055   assert_param(IS_FMC_SDRAM_DEVICE(Device));
1056   assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
1057   assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
1058   assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
1059   assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
1060 
1061   /* Set command register */
1062   MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC_SDCMR_MRD),
1063              ((Command->CommandMode) | (Command->CommandTarget) |
1064               (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) |
1065               ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos)));
1066   /* Prevent unused argument(s) compilation warning */
1067   UNUSED(Timeout);
1068   return HAL_OK;
1069 }
1070 
1071 /**
1072   * @brief  Program the SDRAM Memory Refresh rate.
1073   * @param  Device Pointer to SDRAM device instance
1074   * @param  RefreshRate The SDRAM refresh rate value.
1075   * @retval HAL state
1076   */
FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef * Device,uint32_t RefreshRate)1077 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
1078 {
1079   /* Check the parameters */
1080   assert_param(IS_FMC_SDRAM_DEVICE(Device));
1081   assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
1082 
1083   /* Set the refresh rate in command register */
1084   MODIFY_REG(Device->SDRTR, FMC_SDRTR_COUNT, (RefreshRate << FMC_SDRTR_COUNT_Pos));
1085 
1086   return HAL_OK;
1087 }
1088 
1089 /**
1090   * @brief  Set the Number of consecutive SDRAM Memory auto Refresh commands.
1091   * @param  Device Pointer to SDRAM device instance
1092   * @param  AutoRefreshNumber Specifies the auto Refresh number.
1093   * @retval None
1094   */
FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef * Device,uint32_t AutoRefreshNumber)1095 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device,
1096                                                  uint32_t AutoRefreshNumber)
1097 {
1098   /* Check the parameters */
1099   assert_param(IS_FMC_SDRAM_DEVICE(Device));
1100   assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
1101 
1102   /* Set the Auto-refresh number in command register */
1103   MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos));
1104 
1105   return HAL_OK;
1106 }
1107 
1108 /**
1109   * @brief  Returns the indicated FMC SDRAM bank mode status.
1110   * @param  Device Pointer to SDRAM device instance
1111   * @param  Bank Defines the FMC SDRAM bank. This parameter can be
1112   *                     FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
1113   * @retval The FMC SDRAM bank mode status, could be on of the following values:
1114   *         FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
1115   *         FMC_SDRAM_POWER_DOWN_MODE.
1116   */
FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef * Device,uint32_t Bank)1117 uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1118 {
1119   uint32_t tmpreg;
1120 
1121   /* Check the parameters */
1122   assert_param(IS_FMC_SDRAM_DEVICE(Device));
1123   assert_param(IS_FMC_SDRAM_BANK(Bank));
1124 
1125   /* Get the corresponding bank mode */
1126   if (Bank == FMC_SDRAM_BANK1)
1127   {
1128     tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
1129   }
1130   else
1131   {
1132     tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U);
1133   }
1134 
1135   /* Return the mode status */
1136   return tmpreg;
1137 }
1138 
1139 /**
1140   * @}
1141   */
1142 
1143 /**
1144   * @}
1145   */
1146 
1147 #endif /* FMC_Bank5_6_R */
1148 
1149 /**
1150   * @}
1151   */
1152 
1153 /**
1154   * @}
1155   */
1156 
1157 #endif /* HAL_NOR_MODULE_ENABLED */
1158 /**
1159   * @}
1160   */
1161 /**
1162   * @}
1163   */
1164