1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_adc.c
4 * @author MCD Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32h5xx_ll_adc.h"
22 #include "stm32h5xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32H5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1) || defined (ADC2)
35
36 /** @addtogroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @addtogroup ADC_LL_Private_Constants
44 * @{
45 */
46
47 /* Definitions of ADC hardware constraints delays */
48 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
49 /* not timeout values: */
50 /* Timeout values for ADC operations are dependent to device clock */
51 /* configuration (system clock versus ADC clock), */
52 /* and therefore must be defined in user application. */
53 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
54 /* values definition. */
55 /* Note: ADC timeout values are defined here in CPU cycles to be independent */
56 /* of device clock setting. */
57 /* In user application, ADC timeout values should be defined with */
58 /* temporal values, in function of device clock settings. */
59 /* Highest ratio CPU clock frequency vs ADC clock frequency: */
60 /* - ADC clock from synchronous clock with AHB prescaler 512, */
61 /* ADC prescaler 4. */
62 /* Ratio max = 512 *4 = 2048 */
63 /* - ADC clock from asynchronous clock (PLLP) with prescaler 256. */
64 /* Highest CPU clock PLL (PLLR). */
65 /* Ratio max = PLLRmax /PPLPmin * 256 = (VCO/2) / (VCO/31) * 256 */
66 /* = 3968 */
67 /* Unit: CPU cycles. */
68 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (3968UL)
69 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
70 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
71
72 /**
73 * @}
74 */
75
76 /* Private macros ------------------------------------------------------------*/
77
78 /** @addtogroup ADC_LL_Private_Macros
79 * @{
80 */
81
82 /* Check of parameters for configuration of ADC hierarchical scope: */
83 /* common to several ADC instances. */
84 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
85 (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
86 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
87 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
88 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
89 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
90 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
91 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
92 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
93 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
94 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
95 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
96 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
97 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
98 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
99 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
100 )
101
102 /* Check of parameters for configuration of ADC hierarchical scope: */
103 /* ADC instance. */
104 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
105 (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
106 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
107 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
108 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
109 )
110
111 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
112 (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
113 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
114 )
115
116 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
117 (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
118 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
119 )
120
121 /* Check of parameters for configuration of ADC hierarchical scope: */
122 /* ADC group regular */
123 #if defined(TIM8)
124 /* Devices STM32H563/H573xx */
125 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
126 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
127 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
128 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
129 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
130 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
131 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
132 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
133 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
134 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
135 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
136 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
137 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
138 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
139 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
140 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
141 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
142 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
143 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE15) \
144 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM1_CH1) \
145 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM2_CH1) \
146 )
147 #else
148 /* Devices STM32H503xx */
149 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
150 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
151 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
152 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
153 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
154 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
155 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
156 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
157 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
158 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
159 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
160 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
161 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
162 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE15) \
163 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \
164 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM1_CH1) \
165 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM2_CH1) \
166 )
167 #endif /* Devices STM32H563/H573xx or STM32H503xx */
168
169 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
170 (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
171 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
172 )
173
174 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
175 (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
176 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
177 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
178 )
179
180 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
181 (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
182 || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
183 )
184
185 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
186 (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
187 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
188 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
189 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
190 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
191 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
192 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
193 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
194 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
195 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
196 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
197 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
198 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
199 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
200 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
201 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
202 )
203
204 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
205 (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
206 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
207 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
208 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
209 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
210 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
211 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
212 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
213 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
214 )
215
216 /* Check of parameters for configuration of ADC hierarchical scope: */
217 /* ADC group injected */
218 #if defined(TIM8)
219 /* Devices STM32H563/H573xx */
220 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
221 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
222 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
223 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
224 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
225 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
226 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
227 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
228 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
229 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
230 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
231 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
232 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
233 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
234 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
235 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
236 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
237 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
238 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM1_CH1) \
239 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM2_CH1) \
240 )
241 #else
242 /* Devices STM32H503xx */
243 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
244 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
245 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
246 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
247 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
248 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
249 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
250 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
251 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
252 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
253 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
254 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
255 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
256 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \
257 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM1_CH1) \
258 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM2_CH1) \
259 )
260 #endif /* Devices STM32H563/H573xx or STM32H503xx */
261
262 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
263 (((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
264 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
265 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
266 )
267
268 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
269 (((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
270 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
271 )
272
273 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
274 (((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
275 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
276 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
277 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
278 )
279
280 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
281 (((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
282 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
283 )
284
285 #if defined(ADC_MULTIMODE_SUPPORT)
286 /* Check of parameters for configuration of ADC hierarchical scope: */
287 /* multimode. */
288 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
289 (((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
290 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
291 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
292 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
293 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
294 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
295 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
296 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
297 )
298
299 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
300 (((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
301 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B) \
302 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B) \
303 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B) \
304 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B) \
305 )
306
307 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
308 (((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \
309 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) \
310 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) \
311 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) \
312 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \
313 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
314 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \
315 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
316 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
317 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \
318 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \
319 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \
320 )
321
322 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
323 (((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
324 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
325 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
326 )
327
328 #endif /* ADC_MULTIMODE_SUPPORT */
329 /**
330 * @}
331 */
332
333
334 /* Private function prototypes -----------------------------------------------*/
335
336 /* Exported functions --------------------------------------------------------*/
337 /** @addtogroup ADC_LL_Exported_Functions
338 * @{
339 */
340
341 /** @addtogroup ADC_LL_EF_Init
342 * @{
343 */
344
345 /**
346 * @brief De-initialize registers of all ADC instances belonging to
347 * the same ADC common instance to their default reset values.
348 * @note This function is performing a hard reset, using high level
349 * clock source RCC ADC reset.
350 * Caution: On this STM32 series, if several ADC instances are available
351 * on the selected device, RCC ADC reset will reset
352 * all ADC instances belonging to the common ADC instance.
353 * To de-initialize only 1 ADC instance, use
354 * function @ref LL_ADC_DeInit().
355 * @param ADCxy_COMMON ADC common instance
356 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
357 * @retval An ErrorStatus enumeration value:
358 * - SUCCESS: ADC common registers are de-initialized
359 * - ERROR: not applicable
360 */
LL_ADC_CommonDeInit(const ADC_Common_TypeDef * ADCxy_COMMON)361 ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON)
362 {
363 /* Check the parameters */
364 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
365
366 /* Prevent unused argument compilation warning */
367 (void)(ADCxy_COMMON);
368
369 /* Force reset of ADC clock (core clock) */
370 LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC);
371
372 /* Release reset of ADC clock (core clock) */
373 LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC);
374
375 return SUCCESS;
376 }
377
378 /**
379 * @brief Initialize some features of ADC common parameters
380 * (all ADC instances belonging to the same ADC common instance)
381 * and multimode (for devices with several ADC instances available).
382 * @note The setting of ADC common parameters is conditioned to
383 * ADC instances state:
384 * All ADC instances belonging to the same ADC common instance
385 * must be disabled.
386 * @param ADCxy_COMMON ADC common instance
387 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
388 * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
389 * @retval An ErrorStatus enumeration value:
390 * - SUCCESS: ADC common registers are initialized
391 * - ERROR: ADC common registers are not initialized
392 */
LL_ADC_CommonInit(ADC_Common_TypeDef * ADCxy_COMMON,const LL_ADC_CommonInitTypeDef * pADC_CommonInitStruct)393 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
394 {
395 ErrorStatus status = SUCCESS;
396
397 /* Check the parameters */
398 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
399 assert_param(IS_LL_ADC_COMMON_CLOCK(pADC_CommonInitStruct->CommonClock));
400
401 #if defined(ADC_MULTIMODE_SUPPORT)
402 assert_param(IS_LL_ADC_MULTI_MODE(pADC_CommonInitStruct->Multimode));
403 if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
404 {
405 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(pADC_CommonInitStruct->MultiDMATransfer));
406 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(pADC_CommonInitStruct->MultiTwoSamplingDelay));
407 }
408 #endif /* ADC_MULTIMODE_SUPPORT */
409
410 /* Note: Hardware constraint (refer to description of functions */
411 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
412 /* On this STM32 series, setting of these features is conditioned to */
413 /* ADC state: */
414 /* All ADC instances of the ADC common group must be disabled. */
415 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
416 {
417 /* Configuration of ADC hierarchical scope: */
418 /* - common to several ADC */
419 /* (all ADC instances belonging to the same ADC common instance) */
420 /* - Set ADC clock (conversion clock) */
421 /* - multimode (if several ADC instances available on the */
422 /* selected device) */
423 /* - Set ADC multimode configuration */
424 /* - Set ADC multimode DMA transfer */
425 /* - Set ADC multimode: delay between 2 sampling phases */
426 #if defined(ADC_MULTIMODE_SUPPORT)
427 if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
428 {
429 MODIFY_REG(ADCxy_COMMON->CCR,
430 ADC_CCR_CKMODE
431 | ADC_CCR_PRESC
432 | ADC_CCR_DUAL
433 | ADC_CCR_MDMA
434 | ADC_CCR_DELAY
435 ,
436 pADC_CommonInitStruct->CommonClock
437 | pADC_CommonInitStruct->Multimode
438 | pADC_CommonInitStruct->MultiDMATransfer
439 | pADC_CommonInitStruct->MultiTwoSamplingDelay
440 );
441 }
442 else
443 {
444 MODIFY_REG(ADCxy_COMMON->CCR,
445 ADC_CCR_CKMODE
446 | ADC_CCR_PRESC
447 | ADC_CCR_DUAL
448 | ADC_CCR_MDMA
449 | ADC_CCR_DELAY
450 ,
451 pADC_CommonInitStruct->CommonClock
452 | LL_ADC_MULTI_INDEPENDENT
453 );
454 }
455 #else
456 LL_ADC_SetCommonClock(ADCxy_COMMON, pADC_CommonInitStruct->CommonClock);
457 #endif /* ADC_MULTIMODE_SUPPORT */
458 }
459 else
460 {
461 /* Initialization error: One or several ADC instances belonging to */
462 /* the same ADC common instance are not disabled. */
463 status = ERROR;
464 }
465
466 return status;
467 }
468
469 /**
470 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
471 * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
472 * whose fields will be set to default values.
473 * @retval None
474 */
LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef * pADC_CommonInitStruct)475 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
476 {
477 /* Set pADC_CommonInitStruct fields to default values */
478 /* Set fields of ADC common */
479 /* (all ADC instances belonging to the same ADC common instance) */
480 pADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
481
482 #if defined(ADC_MULTIMODE_SUPPORT)
483 /* Set fields of ADC multimode */
484 pADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
485 pADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
486 pADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE;
487 #endif /* ADC_MULTIMODE_SUPPORT */
488 }
489
490 /**
491 * @brief De-initialize registers of the selected ADC instance
492 * to their default reset values.
493 * @note To reset all ADC instances quickly (perform a hard reset),
494 * use function @ref LL_ADC_CommonDeInit().
495 * @note If this functions returns error status, it means that ADC instance
496 * is in an unknown state.
497 * In this case, perform a hard reset using high level
498 * clock source RCC ADC reset.
499 * Caution: On this STM32 series, if several ADC instances are available
500 * on the selected device, RCC ADC reset will reset
501 * all ADC instances belonging to the common ADC instance.
502 * Refer to function @ref LL_ADC_CommonDeInit().
503 * @param ADCx ADC instance
504 * @retval An ErrorStatus enumeration value:
505 * - SUCCESS: ADC registers are de-initialized
506 * - ERROR: ADC registers are not de-initialized
507 */
LL_ADC_DeInit(ADC_TypeDef * ADCx)508 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
509 {
510 ErrorStatus status = SUCCESS;
511
512 __IO uint32_t timeout_cpu_cycles = 0UL;
513
514 /* Check the parameters */
515 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
516
517 /* Disable ADC instance if not already disabled. */
518 if (LL_ADC_IsEnabled(ADCx) == 1UL)
519 {
520 /* Stop potential ADC conversion on going on ADC group regular. */
521 if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
522 {
523 if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL)
524 {
525 LL_ADC_REG_StopConversion(ADCx);
526 }
527 }
528
529 /* Stop potential ADC conversion on going on ADC group injected. */
530 if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL)
531 {
532 if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL)
533 {
534 LL_ADC_INJ_StopConversion(ADCx);
535 }
536 }
537
538 /* Wait for ADC conversions are effectively stopped */
539 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
540 while ((LL_ADC_REG_IsStopConversionOngoing(ADCx)
541 | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL)
542 {
543 timeout_cpu_cycles--;
544 if (timeout_cpu_cycles == 0UL)
545 {
546 /* Time-out error */
547 status = ERROR;
548 break;
549 }
550 }
551
552 /* Flush group injected contexts queue (register JSQR): */
553 /* Note: Bit JQM must be set to empty the contexts queue (otherwise */
554 /* contexts queue is maintained with the last active context). */
555 LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
556
557 /* Disable the ADC instance */
558 LL_ADC_Disable(ADCx);
559
560 /* Wait for ADC instance is effectively disabled */
561 timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
562 while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
563 {
564 timeout_cpu_cycles--;
565 if (timeout_cpu_cycles == 0UL)
566 {
567 /* Time-out error */
568 status = ERROR;
569 break;
570 }
571 }
572 }
573
574 /* Check whether ADC state is compliant with expected state */
575 if (READ_BIT(ADCx->CR,
576 (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
577 | ADC_CR_ADDIS | ADC_CR_ADEN)
578 )
579 == 0UL)
580 {
581 /* ========== Reset ADC registers ========== */
582 /* Reset register IER */
583 CLEAR_BIT(ADCx->IER,
584 (LL_ADC_IT_ADRDY
585 | LL_ADC_IT_EOC
586 | LL_ADC_IT_EOS
587 | LL_ADC_IT_OVR
588 | LL_ADC_IT_EOSMP
589 | LL_ADC_IT_JEOC
590 | LL_ADC_IT_JEOS
591 | LL_ADC_IT_JQOVF
592 | LL_ADC_IT_AWD1
593 | LL_ADC_IT_AWD2
594 | LL_ADC_IT_AWD3
595 )
596 );
597
598 /* Reset register ISR */
599 SET_BIT(ADCx->ISR,
600 (LL_ADC_FLAG_ADRDY
601 | LL_ADC_FLAG_EOC
602 | LL_ADC_FLAG_EOS
603 | LL_ADC_FLAG_OVR
604 | LL_ADC_FLAG_EOSMP
605 | LL_ADC_FLAG_JEOC
606 | LL_ADC_FLAG_JEOS
607 | LL_ADC_FLAG_JQOVF
608 | LL_ADC_FLAG_AWD1
609 | LL_ADC_FLAG_AWD2
610 | LL_ADC_FLAG_AWD3
611 )
612 );
613
614 /* Reset register CR */
615 /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */
616 /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */
617 /* access mode "read-set": no direct reset applicable. */
618 /* - Reset Calibration mode to default setting (single ended). */
619 /* - Disable ADC internal voltage regulator. */
620 /* - Enable ADC deep power down. */
621 /* Note: ADC internal voltage regulator disable and ADC deep power */
622 /* down enable are conditioned to ADC state disabled: */
623 /* already done above. */
624 CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
625 SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
626
627 /* Reset register CFGR */
628 MODIFY_REG(ADCx->CFGR,
629 (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN
630 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
631 | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
632 | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD
633 | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN
634 | ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN),
635 ADC_CFGR_JQDIS
636 );
637
638 /* Reset register CFGR2 */
639 CLEAR_BIT(ADCx->CFGR2,
640 (ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS
641 | ADC_CFGR2_SWTRIG | ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG
642 | ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
643 );
644
645 /* Reset register SMPR1 */
646 CLEAR_BIT(ADCx->SMPR1,
647 (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
648 | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
649 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
650 );
651
652 /* Reset register SMPR2 */
653 CLEAR_BIT(ADCx->SMPR2,
654 (ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16
655 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13
656 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10)
657 );
658
659 /* Reset register TR1 */
660 MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT | ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
661
662 /* Reset register TR2 */
663 MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2);
664
665 /* Reset register TR3 */
666 MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3);
667
668 /* Reset register SQR1 */
669 CLEAR_BIT(ADCx->SQR1,
670 (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
671 | ADC_SQR1_SQ1 | ADC_SQR1_L)
672 );
673
674 /* Reset register SQR2 */
675 CLEAR_BIT(ADCx->SQR2,
676 (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
677 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
678 );
679
680 /* Reset register SQR3 */
681 CLEAR_BIT(ADCx->SQR3,
682 (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
683 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
684 );
685
686 /* Reset register SQR4 */
687 CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
688
689 /* Reset register JSQR */
690 CLEAR_BIT(ADCx->JSQR,
691 (ADC_JSQR_JL
692 | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
693 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
694 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1)
695 );
696
697 /* Reset register DR */
698 /* Note: bits in access mode read only, no direct reset applicable */
699
700 /* Reset register OFR1 */
701 CLEAR_BIT(ADCx->OFR1,
702 ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1 | ADC_OFR1_SATEN | ADC_OFR1_OFFSETPOS);
703 /* Reset register OFR2 */
704 CLEAR_BIT(ADCx->OFR2,
705 ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2 | ADC_OFR2_SATEN | ADC_OFR2_OFFSETPOS);
706 /* Reset register OFR3 */
707 CLEAR_BIT(ADCx->OFR3,
708 ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3 | ADC_OFR3_SATEN | ADC_OFR3_OFFSETPOS);
709 /* Reset register OFR4 */
710 CLEAR_BIT(ADCx->OFR4,
711 ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4 | ADC_OFR4_SATEN | ADC_OFR4_OFFSETPOS);
712
713 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
714 /* Note: bits in access mode read only, no direct reset applicable */
715
716 /* Reset register AWD2CR */
717 CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
718
719 /* Reset register AWD3CR */
720 CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
721
722 /* Reset register DIFSEL */
723 CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
724
725 /* Reset register CALFACT */
726 CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
727 }
728 else
729 {
730 /* ADC instance is in an unknown state */
731 /* Need to performing a hard reset of ADC instance, using high level */
732 /* clock source RCC ADC reset. */
733 /* Caution: On this STM32 series, if several ADC instances are available */
734 /* on the selected device, RCC ADC reset will reset */
735 /* all ADC instances belonging to the common ADC instance. */
736 /* Caution: On this STM32 series, if several ADC instances are available */
737 /* on the selected device, RCC ADC reset will reset */
738 /* all ADC instances belonging to the common ADC instance. */
739 status = ERROR;
740 }
741
742 return status;
743 }
744
745 /**
746 * @brief Initialize some features of ADC instance.
747 * @note These parameters have an impact on ADC scope: ADC instance.
748 * Affects both group regular and group injected (availability
749 * of ADC group injected depends on STM32 series).
750 * Refer to corresponding unitary functions into
751 * @ref ADC_LL_EF_Configuration_ADC_Instance .
752 * @note The setting of these parameters by function @ref LL_ADC_Init()
753 * is conditioned to ADC state:
754 * ADC instance must be disabled.
755 * This condition is applied to all ADC features, for efficiency
756 * and compatibility over all STM32 series. However, the different
757 * features can be set under different ADC state conditions
758 * (setting possible with ADC enabled without conversion on going,
759 * ADC enabled with conversion on going, ...)
760 * Each feature can be updated afterwards with a unitary function
761 * and potentially with ADC in a different state than disabled,
762 * refer to description of each function for setting
763 * conditioned to ADC state.
764 * @note After using this function, some other features must be configured
765 * using LL unitary functions.
766 * The minimum configuration remaining to be done is:
767 * - Set ADC group regular or group injected sequencer:
768 * map channel on the selected sequencer rank.
769 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
770 * - Set ADC channel sampling time
771 * Refer to function LL_ADC_SetChannelSamplingTime();
772 * @param ADCx ADC instance
773 * @param pADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
774 * @retval An ErrorStatus enumeration value:
775 * - SUCCESS: ADC registers are initialized
776 * - ERROR: ADC registers are not initialized
777 */
LL_ADC_Init(ADC_TypeDef * ADCx,const LL_ADC_InitTypeDef * pADC_InitStruct)778 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct)
779 {
780 ErrorStatus status = SUCCESS;
781
782 /* Check the parameters */
783 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
784
785 assert_param(IS_LL_ADC_RESOLUTION(pADC_InitStruct->Resolution));
786 assert_param(IS_LL_ADC_DATA_ALIGN(pADC_InitStruct->DataAlignment));
787 assert_param(IS_LL_ADC_LOW_POWER(pADC_InitStruct->LowPowerMode));
788
789 /* Note: Hardware constraint (refer to description of this function): */
790 /* ADC instance must be disabled. */
791 if (LL_ADC_IsEnabled(ADCx) == 0UL)
792 {
793 /* Configuration of ADC hierarchical scope: */
794 /* - ADC instance */
795 /* - Set ADC data resolution */
796 /* - Set ADC conversion data alignment */
797 /* - Set ADC low power mode */
798 MODIFY_REG(ADCx->CFGR,
799 ADC_CFGR_RES
800 | ADC_CFGR_ALIGN
801 | ADC_CFGR_AUTDLY
802 ,
803 pADC_InitStruct->Resolution
804 | pADC_InitStruct->DataAlignment
805 | pADC_InitStruct->LowPowerMode
806 );
807
808 }
809 else
810 {
811 /* Initialization error: ADC instance is not disabled. */
812 status = ERROR;
813 }
814
815 return status;
816 }
817
818 /**
819 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
820 * @param pADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
821 * whose fields will be set to default values.
822 * @retval None
823 */
LL_ADC_StructInit(LL_ADC_InitTypeDef * pADC_InitStruct)824 void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct)
825 {
826 /* Set pADC_InitStruct fields to default values */
827 /* Set fields of ADC instance */
828 pADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
829 pADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
830 pADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
831
832 }
833
834 /**
835 * @brief Initialize some features of ADC group regular.
836 * @note These parameters have an impact on ADC scope: ADC group regular.
837 * Refer to corresponding unitary functions into
838 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
839 * (functions with prefix "REG").
840 * @note The setting of these parameters by function @ref LL_ADC_Init()
841 * is conditioned to ADC state:
842 * ADC instance must be disabled.
843 * This condition is applied to all ADC features, for efficiency
844 * and compatibility over all STM32 series. However, the different
845 * features can be set under different ADC state conditions
846 * (setting possible with ADC enabled without conversion on going,
847 * ADC enabled with conversion on going, ...)
848 * Each feature can be updated afterwards with a unitary function
849 * and potentially with ADC in a different state than disabled,
850 * refer to description of each function for setting
851 * conditioned to ADC state.
852 * @note After using this function, other features must be configured
853 * using LL unitary functions.
854 * The minimum configuration remaining to be done is:
855 * - Set ADC group regular or group injected sequencer:
856 * map channel on the selected sequencer rank.
857 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
858 * - Set ADC channel sampling time
859 * Refer to function LL_ADC_SetChannelSamplingTime();
860 * @param ADCx ADC instance
861 * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
862 * @retval An ErrorStatus enumeration value:
863 * - SUCCESS: ADC registers are initialized
864 * - ERROR: ADC registers are not initialized
865 */
LL_ADC_REG_Init(ADC_TypeDef * ADCx,const LL_ADC_REG_InitTypeDef * pADC_RegInitStruct)866 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
867 {
868 ErrorStatus status = SUCCESS;
869
870 /* Check the parameters */
871 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
872 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(pADC_RegInitStruct->TriggerSource));
873 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct->SequencerLength));
874 if (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
875 {
876 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(pADC_RegInitStruct->SequencerDiscont));
877
878 /* ADC group regular continuous mode and discontinuous mode */
879 /* can not be enabled simultenaeously */
880 assert_param((pADC_RegInitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
881 || (pADC_RegInitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
882 }
883 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(pADC_RegInitStruct->ContinuousMode));
884 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(pADC_RegInitStruct->DMATransfer));
885 assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(pADC_RegInitStruct->Overrun));
886
887 /* Note: Hardware constraint (refer to description of this function): */
888 /* ADC instance must be disabled. */
889 if (LL_ADC_IsEnabled(ADCx) == 0UL)
890 {
891 /* Configuration of ADC hierarchical scope: */
892 /* - ADC group regular */
893 /* - Set ADC group regular trigger source */
894 /* - Set ADC group regular sequencer length */
895 /* - Set ADC group regular sequencer discontinuous mode */
896 /* - Set ADC group regular continuous mode */
897 /* - Set ADC group regular conversion data transfer: no transfer or */
898 /* transfer by DMA, and DMA requests mode */
899 /* - Set ADC group regular overrun behavior */
900 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
901 /* setting of trigger source to SW start. */
902 if (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
903 {
904 MODIFY_REG(ADCx->CFGR,
905 ADC_CFGR_EXTSEL
906 | ADC_CFGR_EXTEN
907 | ADC_CFGR_DISCEN
908 | ADC_CFGR_DISCNUM
909 | ADC_CFGR_CONT
910 | ADC_CFGR_DMAEN
911 | ADC_CFGR_DMACFG
912 | ADC_CFGR_OVRMOD
913 ,
914 pADC_RegInitStruct->TriggerSource
915 | pADC_RegInitStruct->SequencerDiscont
916 | pADC_RegInitStruct->ContinuousMode
917 | pADC_RegInitStruct->DMATransfer
918 | pADC_RegInitStruct->Overrun
919 );
920 }
921 else
922 {
923 MODIFY_REG(ADCx->CFGR,
924 ADC_CFGR_EXTSEL
925 | ADC_CFGR_EXTEN
926 | ADC_CFGR_DISCEN
927 | ADC_CFGR_DISCNUM
928 | ADC_CFGR_CONT
929 | ADC_CFGR_DMAEN
930 | ADC_CFGR_DMACFG
931 | ADC_CFGR_OVRMOD
932 ,
933 pADC_RegInitStruct->TriggerSource
934 | LL_ADC_REG_SEQ_DISCONT_DISABLE
935 | pADC_RegInitStruct->ContinuousMode
936 | pADC_RegInitStruct->DMATransfer
937 | pADC_RegInitStruct->Overrun
938 );
939 }
940
941 /* Set ADC group regular sequencer length and scan direction */
942 LL_ADC_REG_SetSequencerLength(ADCx, pADC_RegInitStruct->SequencerLength);
943 }
944 else
945 {
946 /* Initialization error: ADC instance is not disabled. */
947 status = ERROR;
948 }
949 return status;
950 }
951
952 /**
953 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
954 * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
955 * whose fields will be set to default values.
956 * @retval None
957 */
LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef * pADC_RegInitStruct)958 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
959 {
960 /* Set pADC_RegInitStruct fields to default values */
961 /* Set fields of ADC group regular */
962 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
963 /* setting of trigger source to SW start. */
964 pADC_RegInitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
965 pADC_RegInitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
966 pADC_RegInitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
967 pADC_RegInitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
968 pADC_RegInitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
969 pADC_RegInitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
970 }
971
972 /**
973 * @brief Initialize some features of ADC group injected.
974 * @note These parameters have an impact on ADC scope: ADC group injected.
975 * Refer to corresponding unitary functions into
976 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
977 * (functions with prefix "INJ").
978 * @note The setting of these parameters by function @ref LL_ADC_Init()
979 * is conditioned to ADC state:
980 * ADC instance must be disabled.
981 * This condition is applied to all ADC features, for efficiency
982 * and compatibility over all STM32 series. However, the different
983 * features can be set under different ADC state conditions
984 * (setting possible with ADC enabled without conversion on going,
985 * ADC enabled with conversion on going, ...)
986 * Each feature can be updated afterwards with a unitary function
987 * and potentially with ADC in a different state than disabled,
988 * refer to description of each function for setting
989 * conditioned to ADC state.
990 * @note After using this function, other features must be configured
991 * using LL unitary functions.
992 * The minimum configuration remaining to be done is:
993 * - Set ADC group injected sequencer:
994 * map channel on the selected sequencer rank.
995 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
996 * - Set ADC channel sampling time
997 * Refer to function LL_ADC_SetChannelSamplingTime();
998 * @note Caution if feature ADC group injected contexts queue is enabled
999 * (refer to with function @ref LL_ADC_INJ_SetQueueMode() ):
1000 * using successively several times this function will appear as
1001 * having no effect.
1002 * To set several features of ADC group injected, use
1003 * function @ref LL_ADC_INJ_ConfigQueueContext().
1004 * @param ADCx ADC instance
1005 * @param pADC_InjInitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1006 * @retval An ErrorStatus enumeration value:
1007 * - SUCCESS: ADC registers are initialized
1008 * - ERROR: ADC registers are not initialized
1009 */
LL_ADC_INJ_Init(ADC_TypeDef * ADCx,const LL_ADC_INJ_InitTypeDef * pADC_InjInitStruct)1010 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct)
1011 {
1012 ErrorStatus status = SUCCESS;
1013
1014 /* Check the parameters */
1015 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
1016 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(pADC_InjInitStruct->TriggerSource));
1017 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(pADC_InjInitStruct->SequencerLength));
1018 if (pADC_InjInitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
1019 {
1020 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(pADC_InjInitStruct->SequencerDiscont));
1021 }
1022 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(pADC_InjInitStruct->TrigAuto));
1023
1024 /* Note: Hardware constraint (refer to description of this function): */
1025 /* ADC instance must be disabled. */
1026 if (LL_ADC_IsEnabled(ADCx) == 0UL)
1027 {
1028 /* Configuration of ADC hierarchical scope: */
1029 /* - ADC group injected */
1030 /* - Set ADC group injected trigger source */
1031 /* - Set ADC group injected sequencer length */
1032 /* - Set ADC group injected sequencer discontinuous mode */
1033 /* - Set ADC group injected conversion trigger: independent or */
1034 /* from ADC group regular */
1035 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
1036 /* setting of trigger source to SW start. */
1037 if (pADC_InjInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1038 {
1039 MODIFY_REG(ADCx->CFGR,
1040 ADC_CFGR_JDISCEN
1041 | ADC_CFGR_JAUTO
1042 ,
1043 pADC_InjInitStruct->SequencerDiscont
1044 | pADC_InjInitStruct->TrigAuto
1045 );
1046 }
1047 else
1048 {
1049 MODIFY_REG(ADCx->CFGR,
1050 ADC_CFGR_JDISCEN
1051 | ADC_CFGR_JAUTO
1052 ,
1053 LL_ADC_REG_SEQ_DISCONT_DISABLE
1054 | pADC_InjInitStruct->TrigAuto
1055 );
1056 }
1057
1058 MODIFY_REG(ADCx->JSQR,
1059 ADC_JSQR_JEXTSEL
1060 | ADC_JSQR_JEXTEN
1061 | ADC_JSQR_JL
1062 ,
1063 pADC_InjInitStruct->TriggerSource
1064 | pADC_InjInitStruct->SequencerLength
1065 );
1066 }
1067 else
1068 {
1069 /* Initialization error: ADC instance is not disabled. */
1070 status = ERROR;
1071 }
1072 return status;
1073 }
1074
1075 /**
1076 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
1077 * @param pADC_InjInitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1078 * whose fields will be set to default values.
1079 * @retval None
1080 */
LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef * pADC_InjInitStruct)1081 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct)
1082 {
1083 /* Set pADC_InjInitStruct fields to default values */
1084 /* Set fields of ADC group injected */
1085 pADC_InjInitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
1086 pADC_InjInitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
1087 pADC_InjInitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
1088 pADC_InjInitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
1089 }
1090
1091 /**
1092 * @}
1093 */
1094
1095 /**
1096 * @}
1097 */
1098
1099 /**
1100 * @}
1101 */
1102
1103 #endif /* ADC1 || ADC2 */
1104
1105 /**
1106 * @}
1107 */
1108
1109 #endif /* USE_FULL_LL_DRIVER */
1110
