1 /**
2 ******************************************************************************
3 * @file stm32h5xx_hal_sram.c
4 * @author MCD Application Team
5 * @brief SRAM HAL module driver.
6 * This file provides a generic firmware to drive SRAM memories
7 * mounted as external device.
8 *
9 ******************************************************************************
10 * @attention
11 *
12 * Copyright (c) 2023 STMicroelectronics.
13 * All rights reserved.
14 *
15 * This software is licensed under terms that can be found in the LICENSE file
16 * in the root directory of this software component.
17 * If no LICENSE file comes with this software, it is provided AS-IS.
18 *
19 ******************************************************************************
20 @verbatim
21 ==============================================================================
22 ##### How to use this driver #####
23 ==============================================================================
24 [..]
25 This driver is a generic layered driver which contains a set of APIs used to
26 control SRAM memories. It uses the FMC layer functions to interface
27 with SRAM devices.
28 The following sequence should be followed to configure the FMC to interface
29 with SRAM/PSRAM memories:
30
31 (#) Declare a SRAM_HandleTypeDef handle structure, for example:
32 SRAM_HandleTypeDef hsram; and:
33
34 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
35 values of the structure member.
36
37 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
38 base register instance for NOR or SRAM device
39
40 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
41 base register instance for NOR or SRAM extended mode
42
43 (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
44 mode timings; for example:
45 FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
46 and fill its fields with the allowed values of the structure member.
47
48 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
49 performs the following sequence:
50
51 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
52 (##) Control register configuration using the FMC NORSRAM interface function
53 FMC_NORSRAM_Init()
54 (##) Timing register configuration using the FMC NORSRAM interface function
55 FMC_NORSRAM_Timing_Init()
56 (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
57 FMC_NORSRAM_Extended_Timing_Init()
58 (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
59
60 (#) At this stage you can perform read/write accesses from/to the memory connected
61 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
62 following APIs:
63 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
64 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
65
66 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
67 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
68
69 (#) You can continuously monitor the SRAM device HAL state by calling the function
70 HAL_SRAM_GetState()
71
72 *** Callback registration ***
73 =============================================
74 [..]
75 The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
76 allows the user to configure dynamically the driver callbacks.
77
78 Use Functions HAL_SRAM_RegisterCallback() to register a user callback,
79 it allows to register following callbacks:
80 (+) MspInitCallback : SRAM MspInit.
81 (+) MspDeInitCallback : SRAM MspDeInit.
82 This function takes as parameters the HAL peripheral handle, the Callback ID
83 and a pointer to the user callback function.
84
85 Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default
86 weak (overridden) function. It allows to reset following callbacks:
87 (+) MspInitCallback : SRAM MspInit.
88 (+) MspDeInitCallback : SRAM MspDeInit.
89 This function) takes as parameters the HAL peripheral handle and the Callback ID.
90
91 By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
92 all callbacks are reset to the corresponding legacy weak (overridden) functions.
93 Exception done for MspInit and MspDeInit callbacks that are respectively
94 reset to the legacy weak (overridden) functions in the HAL_SRAM_Init
95 and HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
96 If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit
97 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
98
99 Callbacks can be registered/unregistered in READY state only.
100 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
101 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
102 during the Init/DeInit.
103 In that case first register the MspInit/MspDeInit user callbacks
104 using HAL_SRAM_RegisterCallback before calling HAL_SRAM_DeInit
105 or HAL_SRAM_Init function.
106
107 When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
108 not defined, the callback registering feature is not available
109 and weak (overridden) callbacks are used.
110
111 @endverbatim
112 ******************************************************************************
113 */
114
115 /* Includes ------------------------------------------------------------------*/
116 #include "stm32h5xx_hal.h"
117
118 #if defined(FMC_BANK1)
119
120 /** @addtogroup STM32H5xx_HAL_Driver
121 * @{
122 */
123
124 #ifdef HAL_SRAM_MODULE_ENABLED
125
126 /** @defgroup SRAM SRAM
127 * @brief SRAM driver modules
128 * @{
129 */
130
131 /* Private typedef -----------------------------------------------------------*/
132 /* Private define ------------------------------------------------------------*/
133 /* Private macro -------------------------------------------------------------*/
134 /* Private variables ---------------------------------------------------------*/
135 /* Private function prototypes -----------------------------------------------*/
136 /** @addtogroup SRAM_Private_Functions SRAM Private Functions
137 * @{
138 */
139 static void SRAM_DMACplt(DMA_HandleTypeDef *hdma);
140 static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
141 static void SRAM_DMAError(DMA_HandleTypeDef *hdma);
142 /**
143 * @}
144 */
145
146 /* Exported functions --------------------------------------------------------*/
147
148 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
149 * @{
150 */
151
152 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
153 * @brief Initialization and Configuration functions.
154 *
155 @verbatim
156 ==============================================================================
157 ##### SRAM Initialization and de_initialization functions #####
158 ==============================================================================
159 [..] This section provides functions allowing to initialize/de-initialize
160 the SRAM memory
161
162 @endverbatim
163 * @{
164 */
165
166 /**
167 * @brief Performs the SRAM device initialization sequence
168 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
169 * the configuration information for SRAM module.
170 * @param Timing Pointer to SRAM control timing structure
171 * @param ExtTiming Pointer to SRAM extended mode timing structure
172 * @retval HAL status
173 */
HAL_SRAM_Init(SRAM_HandleTypeDef * hsram,FMC_NORSRAM_TimingTypeDef * Timing,FMC_NORSRAM_TimingTypeDef * ExtTiming)174 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
175 FMC_NORSRAM_TimingTypeDef *ExtTiming)
176 {
177 /* Check the SRAM handle parameter */
178 if (hsram == NULL)
179 {
180 return HAL_ERROR;
181 }
182
183 if (hsram->State == HAL_SRAM_STATE_RESET)
184 {
185 /* Allocate lock resource and initialize it */
186 hsram->Lock = HAL_UNLOCKED;
187
188 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
189 if (hsram->MspInitCallback == NULL)
190 {
191 hsram->MspInitCallback = HAL_SRAM_MspInit;
192 }
193 hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
194 hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
195
196 /* Init the low level hardware */
197 hsram->MspInitCallback(hsram);
198 #else
199 /* Initialize the low level hardware (MSP) */
200 HAL_SRAM_MspInit(hsram);
201 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
202 }
203
204 /* Initialize SRAM control Interface */
205 (void)FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
206
207 /* Initialize SRAM timing Interface */
208 (void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
209
210 /* Initialize SRAM extended mode timing Interface */
211 (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,
212 hsram->Init.ExtendedMode);
213
214 /* Enable the NORSRAM device */
215 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
216
217 /* Enable FMC Peripheral */
218 __FMC_ENABLE();
219
220 /* Initialize the SRAM controller state */
221 hsram->State = HAL_SRAM_STATE_READY;
222
223 return HAL_OK;
224 }
225
226 /**
227 * @brief Performs the SRAM device De-initialization sequence.
228 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
229 * the configuration information for SRAM module.
230 * @retval HAL status
231 */
HAL_SRAM_DeInit(SRAM_HandleTypeDef * hsram)232 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
233 {
234 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
235 if (hsram->MspDeInitCallback == NULL)
236 {
237 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
238 }
239
240 /* DeInit the low level hardware */
241 hsram->MspDeInitCallback(hsram);
242 #else
243 /* De-Initialize the low level hardware (MSP) */
244 HAL_SRAM_MspDeInit(hsram);
245 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
246
247 /* Configure the SRAM registers with their reset values */
248 (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
249
250 /* Reset the SRAM controller state */
251 hsram->State = HAL_SRAM_STATE_RESET;
252
253 /* Release Lock */
254 __HAL_UNLOCK(hsram);
255
256 return HAL_OK;
257 }
258
259 /**
260 * @brief SRAM MSP Init.
261 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
262 * the configuration information for SRAM module.
263 * @retval None
264 */
HAL_SRAM_MspInit(SRAM_HandleTypeDef * hsram)265 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
266 {
267 /* Prevent unused argument(s) compilation warning */
268 UNUSED(hsram);
269
270 /* NOTE : This function Should not be modified, when the callback is needed,
271 the HAL_SRAM_MspInit could be implemented in the user file
272 */
273 }
274
275 /**
276 * @brief SRAM MSP DeInit.
277 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
278 * the configuration information for SRAM module.
279 * @retval None
280 */
HAL_SRAM_MspDeInit(SRAM_HandleTypeDef * hsram)281 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
282 {
283 /* Prevent unused argument(s) compilation warning */
284 UNUSED(hsram);
285
286 /* NOTE : This function Should not be modified, when the callback is needed,
287 the HAL_SRAM_MspDeInit could be implemented in the user file
288 */
289 }
290
291 /**
292 * @brief DMA transfer complete callback.
293 * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
294 * the configuration information for SRAM module.
295 * @retval None
296 */
HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef * hdma)297 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
298 {
299 /* Prevent unused argument(s) compilation warning */
300 UNUSED(hdma);
301
302 /* NOTE : This function Should not be modified, when the callback is needed,
303 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
304 */
305 }
306
307 /**
308 * @brief DMA transfer complete error callback.
309 * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
310 * the configuration information for SRAM module.
311 * @retval None
312 */
HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef * hdma)313 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
314 {
315 /* Prevent unused argument(s) compilation warning */
316 UNUSED(hdma);
317
318 /* NOTE : This function Should not be modified, when the callback is needed,
319 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
320 */
321 }
322
323 /**
324 * @}
325 */
326
327 /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
328 * @brief Input Output and memory control functions
329 *
330 @verbatim
331 ==============================================================================
332 ##### SRAM Input and Output functions #####
333 ==============================================================================
334 [..]
335 This section provides functions allowing to use and control the SRAM memory
336
337 @endverbatim
338 * @{
339 */
340
341 /**
342 * @brief Reads 8-bit buffer from SRAM memory.
343 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
344 * the configuration information for SRAM module.
345 * @param pAddress Pointer to read start address
346 * @param pDstBuffer Pointer to destination buffer
347 * @param BufferSize Size of the buffer to read from memory
348 * @retval HAL status
349 */
HAL_SRAM_Read_8b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint8_t * pDstBuffer,uint32_t BufferSize)350 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
351 uint32_t BufferSize)
352 {
353 uint32_t size;
354 __IO uint8_t *psramaddress = (uint8_t *)pAddress;
355 uint8_t *pdestbuff = pDstBuffer;
356 HAL_SRAM_StateTypeDef state = hsram->State;
357
358 /* Check the SRAM controller state */
359 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
360 {
361 /* Process Locked */
362 __HAL_LOCK(hsram);
363
364 /* Update the SRAM controller state */
365 hsram->State = HAL_SRAM_STATE_BUSY;
366
367 /* Read data from memory */
368 for (size = BufferSize; size != 0U; size--)
369 {
370 *pdestbuff = *psramaddress;
371 pdestbuff++;
372 psramaddress++;
373 }
374
375 /* Update the SRAM controller state */
376 hsram->State = state;
377
378 /* Process unlocked */
379 __HAL_UNLOCK(hsram);
380 }
381 else
382 {
383 return HAL_ERROR;
384 }
385
386 return HAL_OK;
387 }
388
389 /**
390 * @brief Writes 8-bit buffer to SRAM memory.
391 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
392 * the configuration information for SRAM module.
393 * @param pAddress Pointer to write start address
394 * @param pSrcBuffer Pointer to source buffer to write
395 * @param BufferSize Size of the buffer to write to memory
396 * @retval HAL status
397 */
HAL_SRAM_Write_8b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint8_t * pSrcBuffer,uint32_t BufferSize)398 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
399 uint32_t BufferSize)
400 {
401 uint32_t size;
402 __IO uint8_t *psramaddress = (uint8_t *)pAddress;
403 uint8_t *psrcbuff = pSrcBuffer;
404
405 /* Check the SRAM controller state */
406 if (hsram->State == HAL_SRAM_STATE_READY)
407 {
408 /* Process Locked */
409 __HAL_LOCK(hsram);
410
411 /* Update the SRAM controller state */
412 hsram->State = HAL_SRAM_STATE_BUSY;
413
414 /* Write data to memory */
415 for (size = BufferSize; size != 0U; size--)
416 {
417 *psramaddress = *psrcbuff;
418 psrcbuff++;
419 psramaddress++;
420 }
421
422 /* Update the SRAM controller state */
423 hsram->State = HAL_SRAM_STATE_READY;
424
425 /* Process unlocked */
426 __HAL_UNLOCK(hsram);
427 }
428 else
429 {
430 return HAL_ERROR;
431 }
432
433 return HAL_OK;
434 }
435
436 /**
437 * @brief Reads 16-bit buffer from SRAM memory.
438 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
439 * the configuration information for SRAM module.
440 * @param pAddress Pointer to read start address
441 * @param pDstBuffer Pointer to destination buffer
442 * @param BufferSize Size of the buffer to read from memory
443 * @retval HAL status
444 */
HAL_SRAM_Read_16b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint16_t * pDstBuffer,uint32_t BufferSize)445 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
446 uint32_t BufferSize)
447 {
448 uint32_t size;
449 __IO uint32_t *psramaddress = pAddress;
450 uint16_t *pdestbuff = pDstBuffer;
451 uint8_t limit;
452 HAL_SRAM_StateTypeDef state = hsram->State;
453
454 /* Check the SRAM controller state */
455 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
456 {
457 /* Process Locked */
458 __HAL_LOCK(hsram);
459
460 /* Update the SRAM controller state */
461 hsram->State = HAL_SRAM_STATE_BUSY;
462
463 /* Check if the size is a 32-bits multiple */
464 limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
465
466 /* Read data from memory */
467 for (size = BufferSize; size != limit; size -= 2U)
468 {
469 *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
470 pdestbuff++;
471 *pdestbuff = (uint16_t)(((*psramaddress) & 0xFFFF0000U) >> 16U);
472 pdestbuff++;
473 psramaddress++;
474 }
475
476 /* Read last 16-bits if size is not 32-bits multiple */
477 if (limit != 0U)
478 {
479 *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
480 }
481
482 /* Update the SRAM controller state */
483 hsram->State = state;
484
485 /* Process unlocked */
486 __HAL_UNLOCK(hsram);
487 }
488 else
489 {
490 return HAL_ERROR;
491 }
492
493 return HAL_OK;
494 }
495
496 /**
497 * @brief Writes 16-bit buffer to SRAM memory.
498 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
499 * the configuration information for SRAM module.
500 * @param pAddress Pointer to write start address
501 * @param pSrcBuffer Pointer to source buffer to write
502 * @param BufferSize Size of the buffer to write to memory
503 * @retval HAL status
504 */
HAL_SRAM_Write_16b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint16_t * pSrcBuffer,uint32_t BufferSize)505 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
506 uint32_t BufferSize)
507 {
508 uint32_t size;
509 __IO uint32_t *psramaddress = pAddress;
510 uint16_t *psrcbuff = pSrcBuffer;
511 uint8_t limit;
512
513 /* Check the SRAM controller state */
514 if (hsram->State == HAL_SRAM_STATE_READY)
515 {
516 /* Process Locked */
517 __HAL_LOCK(hsram);
518
519 /* Update the SRAM controller state */
520 hsram->State = HAL_SRAM_STATE_BUSY;
521
522 /* Check if the size is a 32-bits multiple */
523 limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
524
525 /* Write data to memory */
526 for (size = BufferSize; size != limit; size -= 2U)
527 {
528 *psramaddress = (uint32_t)(*psrcbuff);
529 psrcbuff++;
530 *psramaddress |= ((uint32_t)(*psrcbuff) << 16U);
531 psrcbuff++;
532 psramaddress++;
533 }
534
535 /* Write last 16-bits if size is not 32-bits multiple */
536 if (limit != 0U)
537 {
538 *psramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psramaddress) & 0xFFFF0000U);
539 }
540
541 /* Update the SRAM controller state */
542 hsram->State = HAL_SRAM_STATE_READY;
543
544 /* Process unlocked */
545 __HAL_UNLOCK(hsram);
546 }
547 else
548 {
549 return HAL_ERROR;
550 }
551
552 return HAL_OK;
553 }
554
555 /**
556 * @brief Reads 32-bit buffer from SRAM memory.
557 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
558 * the configuration information for SRAM module.
559 * @param pAddress Pointer to read start address
560 * @param pDstBuffer Pointer to destination buffer
561 * @param BufferSize Size of the buffer to read from memory
562 * @retval HAL status
563 */
HAL_SRAM_Read_32b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)564 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
565 uint32_t BufferSize)
566 {
567 uint32_t size;
568 __IO uint32_t *psramaddress = pAddress;
569 uint32_t *pdestbuff = pDstBuffer;
570 HAL_SRAM_StateTypeDef state = hsram->State;
571
572 /* Check the SRAM controller state */
573 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
574 {
575 /* Process Locked */
576 __HAL_LOCK(hsram);
577
578 /* Update the SRAM controller state */
579 hsram->State = HAL_SRAM_STATE_BUSY;
580
581 /* Read data from memory */
582 for (size = BufferSize; size != 0U; size--)
583 {
584 *pdestbuff = *psramaddress;
585 pdestbuff++;
586 psramaddress++;
587 }
588
589 /* Update the SRAM controller state */
590 hsram->State = state;
591
592 /* Process unlocked */
593 __HAL_UNLOCK(hsram);
594 }
595 else
596 {
597 return HAL_ERROR;
598 }
599
600 return HAL_OK;
601 }
602
603 /**
604 * @brief Writes 32-bit buffer to SRAM memory.
605 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
606 * the configuration information for SRAM module.
607 * @param pAddress Pointer to write start address
608 * @param pSrcBuffer Pointer to source buffer to write
609 * @param BufferSize Size of the buffer to write to memory
610 * @retval HAL status
611 */
HAL_SRAM_Write_32b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)612 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
613 uint32_t BufferSize)
614 {
615 uint32_t size;
616 __IO uint32_t *psramaddress = pAddress;
617 uint32_t *psrcbuff = pSrcBuffer;
618
619 /* Check the SRAM controller state */
620 if (hsram->State == HAL_SRAM_STATE_READY)
621 {
622 /* Process Locked */
623 __HAL_LOCK(hsram);
624
625 /* Update the SRAM controller state */
626 hsram->State = HAL_SRAM_STATE_BUSY;
627
628 /* Write data to memory */
629 for (size = BufferSize; size != 0U; size--)
630 {
631 *psramaddress = *psrcbuff;
632 psrcbuff++;
633 psramaddress++;
634 }
635
636 /* Update the SRAM controller state */
637 hsram->State = HAL_SRAM_STATE_READY;
638
639 /* Process unlocked */
640 __HAL_UNLOCK(hsram);
641 }
642 else
643 {
644 return HAL_ERROR;
645 }
646
647 return HAL_OK;
648 }
649
650 /**
651 * @brief Reads a Words data from the SRAM memory using DMA transfer.
652 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
653 * the configuration information for SRAM module.
654 * @param pAddress Pointer to read start address
655 * @param pDstBuffer Pointer to destination buffer
656 * @param BufferSize Size of the buffer to read from memory
657 * @retval HAL status
658 */
HAL_SRAM_Read_DMA(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)659 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
660 uint32_t BufferSize)
661 {
662 HAL_StatusTypeDef status;
663 HAL_SRAM_StateTypeDef state = hsram->State;
664 uint32_t size;
665 uint32_t data_width;
666
667 /* Check the SRAM controller state */
668 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
669 {
670 /* Process Locked */
671 __HAL_LOCK(hsram);
672
673 /* Update the SRAM controller state */
674 hsram->State = HAL_SRAM_STATE_BUSY;
675
676 /* Configure DMA user callbacks */
677 if (state == HAL_SRAM_STATE_READY)
678 {
679 hsram->hdma->XferCpltCallback = SRAM_DMACplt;
680 }
681 else
682 {
683 hsram->hdma->XferCpltCallback = SRAM_DMACpltProt;
684 }
685 hsram->hdma->XferErrorCallback = SRAM_DMAError;
686
687 if ((hsram->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
688 {
689 if ((hsram->hdma->LinkedListQueue != 0U) && (hsram->hdma->LinkedListQueue->Head != 0U))
690 {
691 /* Check destination data width and set the size to be transferred */
692 data_width = hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2;
693
694 if (data_width == DMA_DEST_DATAWIDTH_WORD)
695 {
696 size = (BufferSize * 4U);
697 }
698 else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
699 {
700 size = (BufferSize * 2U);
701 }
702 else
703 {
704 size = (BufferSize);
705 }
706 /* Set Source , destination , buffer size */
707 /* Set DMA data size */
708 hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = size;
709 /* Set DMA source address */
710 hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pAddress;
711 /* Set DMA destination address */
712 hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pDstBuffer;
713
714 /* Enable the DMA Stream */
715 status = HAL_DMAEx_List_Start_IT(hsram->hdma);
716 }
717 else
718 {
719 /* Change SRAM state */
720 hsram->State = HAL_SRAM_STATE_READY;
721
722 __HAL_UNLOCK(hsram);
723
724 status = HAL_ERROR;
725 }
726 }
727 else
728 {
729 /* Check destination data width and set the size to be transferred */
730 data_width = hsram->hdma->Init.DestDataWidth;
731
732 if (data_width == DMA_DEST_DATAWIDTH_WORD)
733 {
734 size = (BufferSize * 4U);
735 }
736 else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
737 {
738 size = (BufferSize * 2U);
739 }
740 else
741 {
742 size = (BufferSize);
743 }
744
745 /* Enable the DMA Stream */
746 status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, size);
747 }
748
749 /* Process unlocked */
750 __HAL_UNLOCK(hsram);
751 }
752 else
753 {
754 status = HAL_ERROR;
755 }
756
757 return status;
758 }
759
760 /**
761 * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
762 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
763 * the configuration information for SRAM module.
764 * @param pAddress Pointer to write start address
765 * @param pSrcBuffer Pointer to source buffer to write
766 * @param BufferSize Size of the buffer to write to memory
767 * @retval HAL status
768 */
HAL_SRAM_Write_DMA(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)769 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
770 uint32_t BufferSize)
771 {
772 HAL_StatusTypeDef status;
773 uint32_t size;
774 uint32_t data_width;
775
776 /* Check the SRAM controller state */
777 if (hsram->State == HAL_SRAM_STATE_READY)
778 {
779 /* Process Locked */
780 __HAL_LOCK(hsram);
781
782 /* Update the SRAM controller state */
783 hsram->State = HAL_SRAM_STATE_BUSY;
784
785 /* Configure DMA user callbacks */
786 hsram->hdma->XferCpltCallback = SRAM_DMACplt;
787 hsram->hdma->XferErrorCallback = SRAM_DMAError;
788
789 if ((hsram->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
790 {
791 if ((hsram->hdma->LinkedListQueue != 0U) && (hsram->hdma->LinkedListQueue->Head != 0U))
792 {
793 /* Check destination data width and set the size to be transferred */
794 data_width = hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2;
795
796 if (data_width == DMA_DEST_DATAWIDTH_WORD)
797 {
798 size = (BufferSize * 4U);
799 }
800 else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
801 {
802 size = (BufferSize * 2U);
803 }
804 else
805 {
806 size = (BufferSize);
807 }
808 /* Set Source , destination , buffer size */
809 /* Set DMA data size */
810 hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = size;
811 /* Set DMA source address */
812 hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pSrcBuffer;
813 /* Set DMA destination address */
814 hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pAddress;
815 /* Enable the DMA Stream */
816 status = HAL_DMAEx_List_Start_IT(hsram->hdma);
817 }
818 else
819 {
820 /* Change SRAM state */
821 hsram->State = HAL_SRAM_STATE_READY;
822
823 __HAL_UNLOCK(hsram);
824
825 status = HAL_ERROR;
826 }
827 }
828 else
829 {
830 /* Check destination data width and set the size to be transferred */
831 data_width = hsram->hdma->Init.DestDataWidth;
832
833 if (data_width == DMA_DEST_DATAWIDTH_WORD)
834 {
835 size = (BufferSize * 4U);
836 }
837 else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
838 {
839 size = (BufferSize * 2U);
840 }
841 else
842 {
843 size = (BufferSize);
844 }
845
846 /* Enable the DMA Stream */
847 status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, size);
848 }
849
850 /* Process unlocked */
851 __HAL_UNLOCK(hsram);
852 }
853 else
854 {
855 status = HAL_ERROR;
856 }
857
858 return status;
859 }
860
861 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
862 /**
863 * @brief Register a User SRAM Callback
864 * To be used to override the weak predefined callback
865 * @param hsram : SRAM handle
866 * @param CallbackId : ID of the callback to be registered
867 * This parameter can be one of the following values:
868 * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
869 * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
870 * @param pCallback : pointer to the Callback function
871 * @retval status
872 */
HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef * hsram,HAL_SRAM_CallbackIDTypeDef CallbackId,pSRAM_CallbackTypeDef pCallback)873 HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
874 pSRAM_CallbackTypeDef pCallback)
875 {
876 HAL_StatusTypeDef status = HAL_OK;
877 HAL_SRAM_StateTypeDef state;
878
879 if (pCallback == NULL)
880 {
881 return HAL_ERROR;
882 }
883
884 state = hsram->State;
885 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
886 {
887 switch (CallbackId)
888 {
889 case HAL_SRAM_MSP_INIT_CB_ID :
890 hsram->MspInitCallback = pCallback;
891 break;
892 case HAL_SRAM_MSP_DEINIT_CB_ID :
893 hsram->MspDeInitCallback = pCallback;
894 break;
895 default :
896 /* update return status */
897 status = HAL_ERROR;
898 break;
899 }
900 }
901 else
902 {
903 /* update return status */
904 status = HAL_ERROR;
905 }
906
907 return status;
908 }
909
910 /**
911 * @brief Unregister a User SRAM Callback
912 * SRAM Callback is redirected to the weak predefined callback
913 * @param hsram : SRAM handle
914 * @param CallbackId : ID of the callback to be unregistered
915 * This parameter can be one of the following values:
916 * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
917 * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
918 * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
919 * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
920 * @retval status
921 */
HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef * hsram,HAL_SRAM_CallbackIDTypeDef CallbackId)922 HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
923 {
924 HAL_StatusTypeDef status = HAL_OK;
925 HAL_SRAM_StateTypeDef state;
926
927 state = hsram->State;
928 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
929 {
930 switch (CallbackId)
931 {
932 case HAL_SRAM_MSP_INIT_CB_ID :
933 hsram->MspInitCallback = HAL_SRAM_MspInit;
934 break;
935 case HAL_SRAM_MSP_DEINIT_CB_ID :
936 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
937 break;
938 case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
939 hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
940 break;
941 case HAL_SRAM_DMA_XFER_ERR_CB_ID :
942 hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
943 break;
944 default :
945 /* update return status */
946 status = HAL_ERROR;
947 break;
948 }
949 }
950 else if (state == HAL_SRAM_STATE_RESET)
951 {
952 switch (CallbackId)
953 {
954 case HAL_SRAM_MSP_INIT_CB_ID :
955 hsram->MspInitCallback = HAL_SRAM_MspInit;
956 break;
957 case HAL_SRAM_MSP_DEINIT_CB_ID :
958 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
959 break;
960 default :
961 /* update return status */
962 status = HAL_ERROR;
963 break;
964 }
965 }
966 else
967 {
968 /* update return status */
969 status = HAL_ERROR;
970 }
971
972 return status;
973 }
974
975 /**
976 * @brief Register a User SRAM Callback for DMA transfers
977 * To be used to override the weak predefined callback
978 * @param hsram : SRAM handle
979 * @param CallbackId : ID of the callback to be registered
980 * This parameter can be one of the following values:
981 * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
982 * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
983 * @param pCallback : pointer to the Callback function
984 * @retval status
985 */
HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef * hsram,HAL_SRAM_CallbackIDTypeDef CallbackId,pSRAM_DmaCallbackTypeDef pCallback)986 HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
987 pSRAM_DmaCallbackTypeDef pCallback)
988 {
989 HAL_StatusTypeDef status = HAL_OK;
990 HAL_SRAM_StateTypeDef state;
991
992 if (pCallback == NULL)
993 {
994 return HAL_ERROR;
995 }
996
997 /* Process locked */
998 __HAL_LOCK(hsram);
999
1000 state = hsram->State;
1001 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
1002 {
1003 switch (CallbackId)
1004 {
1005 case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
1006 hsram->DmaXferCpltCallback = pCallback;
1007 break;
1008 case HAL_SRAM_DMA_XFER_ERR_CB_ID :
1009 hsram->DmaXferErrorCallback = pCallback;
1010 break;
1011 default :
1012 /* update return status */
1013 status = HAL_ERROR;
1014 break;
1015 }
1016 }
1017 else
1018 {
1019 /* update return status */
1020 status = HAL_ERROR;
1021 }
1022
1023 /* Release Lock */
1024 __HAL_UNLOCK(hsram);
1025 return status;
1026 }
1027 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
1028
1029 /**
1030 * @}
1031 */
1032
1033 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
1034 * @brief Control functions
1035 *
1036 @verbatim
1037 ==============================================================================
1038 ##### SRAM Control functions #####
1039 ==============================================================================
1040 [..]
1041 This subsection provides a set of functions allowing to control dynamically
1042 the SRAM interface.
1043
1044 @endverbatim
1045 * @{
1046 */
1047
1048 /**
1049 * @brief Enables dynamically SRAM write operation.
1050 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
1051 * the configuration information for SRAM module.
1052 * @retval HAL status
1053 */
HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef * hsram)1054 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
1055 {
1056 /* Check the SRAM controller state */
1057 if (hsram->State == HAL_SRAM_STATE_PROTECTED)
1058 {
1059 /* Process Locked */
1060 __HAL_LOCK(hsram);
1061
1062 /* Update the SRAM controller state */
1063 hsram->State = HAL_SRAM_STATE_BUSY;
1064
1065 /* Enable write operation */
1066 (void)FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
1067
1068 /* Update the SRAM controller state */
1069 hsram->State = HAL_SRAM_STATE_READY;
1070
1071 /* Process unlocked */
1072 __HAL_UNLOCK(hsram);
1073 }
1074 else
1075 {
1076 return HAL_ERROR;
1077 }
1078
1079 return HAL_OK;
1080 }
1081
1082 /**
1083 * @brief Disables dynamically SRAM write operation.
1084 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
1085 * the configuration information for SRAM module.
1086 * @retval HAL status
1087 */
HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef * hsram)1088 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
1089 {
1090 /* Check the SRAM controller state */
1091 if (hsram->State == HAL_SRAM_STATE_READY)
1092 {
1093 /* Process Locked */
1094 __HAL_LOCK(hsram);
1095
1096 /* Update the SRAM controller state */
1097 hsram->State = HAL_SRAM_STATE_BUSY;
1098
1099 /* Disable write operation */
1100 (void)FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
1101
1102 /* Update the SRAM controller state */
1103 hsram->State = HAL_SRAM_STATE_PROTECTED;
1104
1105 /* Process unlocked */
1106 __HAL_UNLOCK(hsram);
1107 }
1108 else
1109 {
1110 return HAL_ERROR;
1111 }
1112
1113 return HAL_OK;
1114 }
1115
1116 /**
1117 * @}
1118 */
1119
1120 /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
1121 * @brief Peripheral State functions
1122 *
1123 @verbatim
1124 ==============================================================================
1125 ##### SRAM State functions #####
1126 ==============================================================================
1127 [..]
1128 This subsection permits to get in run-time the status of the SRAM controller
1129 and the data flow.
1130
1131 @endverbatim
1132 * @{
1133 */
1134
1135 /**
1136 * @brief Returns the SRAM controller state
1137 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
1138 * the configuration information for SRAM module.
1139 * @retval HAL state
1140 */
HAL_SRAM_GetState(const SRAM_HandleTypeDef * hsram)1141 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram)
1142 {
1143 return hsram->State;
1144 }
1145
1146 /**
1147 * @}
1148 */
1149
1150 /**
1151 * @}
1152 */
1153
1154 /** @addtogroup SRAM_Private_Functions SRAM Private Functions
1155 * @{
1156 */
1157
1158 /**
1159 * @brief DMA SRAM process complete callback.
1160 * @param hdma : DMA handle
1161 * @retval None
1162 */
SRAM_DMACplt(DMA_HandleTypeDef * hdma)1163 static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
1164 {
1165 /* Derogation MISRAC2012-Rule-11.5 */
1166 SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
1167
1168 /* Disable the DMA channel */
1169 __HAL_DMA_DISABLE(hdma);
1170
1171 /* Update the SRAM controller state */
1172 hsram->State = HAL_SRAM_STATE_READY;
1173
1174 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
1175 hsram->DmaXferCpltCallback(hdma);
1176 #else
1177 HAL_SRAM_DMA_XferCpltCallback(hdma);
1178 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
1179 }
1180
1181 /**
1182 * @brief DMA SRAM process complete callback.
1183 * @param hdma : DMA handle
1184 * @retval None
1185 */
SRAM_DMACpltProt(DMA_HandleTypeDef * hdma)1186 static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
1187 {
1188 /* Derogation MISRAC2012-Rule-11.5 */
1189 SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
1190
1191 /* Disable the DMA channel */
1192 __HAL_DMA_DISABLE(hdma);
1193
1194 /* Update the SRAM controller state */
1195 hsram->State = HAL_SRAM_STATE_PROTECTED;
1196
1197 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
1198 hsram->DmaXferCpltCallback(hdma);
1199 #else
1200 HAL_SRAM_DMA_XferCpltCallback(hdma);
1201 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
1202 }
1203
1204 /**
1205 * @brief DMA SRAM error callback.
1206 * @param hdma : DMA handle
1207 * @retval None
1208 */
SRAM_DMAError(DMA_HandleTypeDef * hdma)1209 static void SRAM_DMAError(DMA_HandleTypeDef *hdma)
1210 {
1211 /* Derogation MISRAC2012-Rule-11.5 */
1212 SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
1213
1214 /* Disable the DMA channel */
1215 __HAL_DMA_DISABLE(hdma);
1216
1217 /* Update the SRAM controller state */
1218 hsram->State = HAL_SRAM_STATE_ERROR;
1219
1220 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
1221 hsram->DmaXferErrorCallback(hdma);
1222 #else
1223 HAL_SRAM_DMA_XferErrorCallback(hdma);
1224 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
1225 }
1226
1227 /**
1228 * @}
1229 */
1230
1231 /**
1232 * @}
1233 */
1234
1235 #endif /* HAL_SRAM_MODULE_ENABLED */
1236
1237 /**
1238 * @}
1239 */
1240
1241 #endif /* FMC_BANK1 */
1242
