1 /**
2 ******************************************************************************
3 * @file stm32h5xx_hal_sdram.c
4 * @author MCD Application Team
5 * @brief SDRAM HAL module driver.
6 * This file provides a generic firmware to drive SDRAM memories mounted
7 * as external device.
8 *
9 ******************************************************************************
10 * @attention
11 *
12 * Copyright (c) 2023 STMicroelectronics.
13 * All rights reserved.
14 *
15 * This software is licensed under terms that can be found in the LICENSE file
16 * in the root directory of this software component.
17 * If no LICENSE file comes with this software, it is provided AS-IS.
18 *
19 ******************************************************************************
20 @verbatim
21 ==============================================================================
22 ##### How to use this driver #####
23 ==============================================================================
24 [..]
25 This driver is a generic layered driver which contains a set of APIs used to
26 control SDRAM memories. It uses the FMC layer functions to interface
27 with SDRAM devices.
28 The following sequence should be followed to configure the FMC to interface
29 with SDRAM memories:
30
31 (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
32 SDRAM_HandleTypeDef hsdram
33
34 (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
35 values of the structure member.
36
37 (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
38 base register instance for NOR or SDRAM device
39
40 (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
41 FMC_SDRAM_TimingTypeDef Timing;
42 and fill its fields with the allowed values of the structure member.
43
44 (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
45 performs the following sequence:
46
47 (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
48 (##) Control register configuration using the FMC SDRAM interface function
49 FMC_SDRAM_Init()
50 (##) Timing register configuration using the FMC SDRAM interface function
51 FMC_SDRAM_Timing_Init()
52 (##) Program the SDRAM external device by applying its initialization sequence
53 according to the device plugged in your hardware. This step is mandatory
54 for accessing the SDRAM device.
55
56 (#) At this stage you can perform read/write accesses from/to the memory connected
57 to the SDRAM Bank. You can perform either polling or DMA transfer using the
58 following APIs:
59 (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
60 (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
61
62 (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
63 HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
64 the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
65 device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
66 structure.
67
68 (#) You can continuously monitor the SDRAM device HAL state by calling the function
69 HAL_SDRAM_GetState()
70
71 *** Callback registration ***
72 =============================================
73 [..]
74 The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS when set to 1
75 allows the user to configure dynamically the driver callbacks.
76
77 Use Functions HAL_SDRAM_RegisterCallback() to register a user callback,
78 it allows to register following callbacks:
79 (+) MspInitCallback : SDRAM MspInit.
80 (+) MspDeInitCallback : SDRAM MspDeInit.
81 This function takes as parameters the HAL peripheral handle, the Callback ID
82 and a pointer to the user callback function.
83
84 Use function HAL_SDRAM_UnRegisterCallback() to reset a callback to the default
85 weak (overridden) function. It allows to reset following callbacks:
86 (+) MspInitCallback : SDRAM MspInit.
87 (+) MspDeInitCallback : SDRAM MspDeInit.
88 This function) takes as parameters the HAL peripheral handle and the Callback ID.
89
90 By default, after the HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET
91 all callbacks are reset to the corresponding legacy weak (overridden) functions.
92 Exception done for MspInit and MspDeInit callbacks that are respectively
93 reset to the legacy weak (overridden) functions in the HAL_SDRAM_Init
94 and HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand).
95 If not, MspInit or MspDeInit are not null, the HAL_SDRAM_Init and HAL_SDRAM_DeInit
96 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
97
98 Callbacks can be registered/unregistered in READY state only.
99 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
100 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
101 during the Init/DeInit.
102 In that case first register the MspInit/MspDeInit user callbacks
103 using HAL_SDRAM_RegisterCallback before calling HAL_SDRAM_DeInit
104 or HAL_SDRAM_Init function.
105
106 When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or
107 not defined, the callback registering feature is not available
108 and weak (overridden) callbacks are used.
109
110 @endverbatim
111 ******************************************************************************
112 */
113
114 /* Includes ------------------------------------------------------------------*/
115 #include "stm32h5xx_hal.h"
116
117 #if defined(FMC_Bank5_6_R)
118
119 /** @addtogroup STM32H5xx_HAL_Driver
120 * @{
121 */
122
123 #ifdef HAL_SDRAM_MODULE_ENABLED
124
125 /** @defgroup SDRAM SDRAM
126 * @brief SDRAM driver modules
127 * @{
128 */
129
130 /* Private typedef -----------------------------------------------------------*/
131 /* Private define ------------------------------------------------------------*/
132 /* Private macro -------------------------------------------------------------*/
133 /* Private variables ---------------------------------------------------------*/
134 /* Private function prototypes -----------------------------------------------*/
135 /** @addtogroup SDRAM_Private_Functions SDRAM Private Functions
136 * @{
137 */
138 static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma);
139 static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
140 static void SDRAM_DMAError(DMA_HandleTypeDef *hdma);
141 /**
142 * @}
143 */
144
145 /* Exported functions --------------------------------------------------------*/
146 /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
147 * @{
148 */
149
150 /** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions
151 * @brief Initialization and Configuration functions
152 *
153 @verbatim
154 ==============================================================================
155 ##### SDRAM Initialization and de_initialization functions #####
156 ==============================================================================
157 [..]
158 This section provides functions allowing to initialize/de-initialize
159 the SDRAM memory
160
161 @endverbatim
162 * @{
163 */
164
165 /**
166 * @brief Performs the SDRAM device initialization sequence.
167 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
168 * the configuration information for SDRAM module.
169 * @param Timing Pointer to SDRAM control timing structure
170 * @retval HAL status
171 */
HAL_SDRAM_Init(SDRAM_HandleTypeDef * hsdram,FMC_SDRAM_TimingTypeDef * Timing)172 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
173 {
174 /* Check the SDRAM handle parameter */
175 if (hsdram == NULL)
176 {
177 return HAL_ERROR;
178 }
179
180 if (hsdram->State == HAL_SDRAM_STATE_RESET)
181 {
182 /* Allocate lock resource and initialize it */
183 hsdram->Lock = HAL_UNLOCKED;
184 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
185 if (hsdram->MspInitCallback == NULL)
186 {
187 hsdram->MspInitCallback = HAL_SDRAM_MspInit;
188 }
189 hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
190 hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
191 hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
192
193 /* Init the low level hardware */
194 hsdram->MspInitCallback(hsdram);
195 #else
196 /* Initialize the low level hardware (MSP) */
197 HAL_SDRAM_MspInit(hsdram);
198 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
199 }
200
201 /* Initialize the SDRAM controller state */
202 hsdram->State = HAL_SDRAM_STATE_BUSY;
203
204 /* Initialize SDRAM control Interface */
205 (void)FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
206
207 /* Initialize SDRAM timing Interface */
208 (void)FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
209
210 /* Enable FMC Peripheral */
211 __FMC_ENABLE();
212 /* Update the SDRAM controller state */
213 hsdram->State = HAL_SDRAM_STATE_READY;
214
215 return HAL_OK;
216 }
217
218 /**
219 * @brief Perform the SDRAM device initialization sequence.
220 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
221 * the configuration information for SDRAM module.
222 * @retval HAL status
223 */
HAL_SDRAM_DeInit(SDRAM_HandleTypeDef * hsdram)224 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
225 {
226 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
227 if (hsdram->MspDeInitCallback == NULL)
228 {
229 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
230 }
231
232 /* DeInit the low level hardware */
233 hsdram->MspDeInitCallback(hsdram);
234 #else
235 /* Initialize the low level hardware (MSP) */
236 HAL_SDRAM_MspDeInit(hsdram);
237 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
238
239 /* Configure the SDRAM registers with their reset values */
240 (void)FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
241
242 /* Reset the SDRAM controller state */
243 hsdram->State = HAL_SDRAM_STATE_RESET;
244
245 /* Release Lock */
246 __HAL_UNLOCK(hsdram);
247
248 return HAL_OK;
249 }
250
251 /**
252 * @brief SDRAM MSP Init.
253 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
254 * the configuration information for SDRAM module.
255 * @retval None
256 */
HAL_SDRAM_MspInit(SDRAM_HandleTypeDef * hsdram)257 __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
258 {
259 /* Prevent unused argument(s) compilation warning */
260 UNUSED(hsdram);
261
262 /* NOTE: This function Should not be modified, when the callback is needed,
263 the HAL_SDRAM_MspInit could be implemented in the user file
264 */
265 }
266
267 /**
268 * @brief SDRAM MSP DeInit.
269 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
270 * the configuration information for SDRAM module.
271 * @retval None
272 */
HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef * hsdram)273 __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
274 {
275 /* Prevent unused argument(s) compilation warning */
276 UNUSED(hsdram);
277
278 /* NOTE: This function Should not be modified, when the callback is needed,
279 the HAL_SDRAM_MspDeInit could be implemented in the user file
280 */
281 }
282
283 /**
284 * @brief This function handles SDRAM refresh error interrupt request.
285 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
286 * the configuration information for SDRAM module.
287 * @retval HAL status
288 */
HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef * hsdram)289 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
290 {
291 /* Check SDRAM interrupt Rising edge flag */
292 if (__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
293 {
294 /* SDRAM refresh error interrupt callback */
295 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
296 hsdram->RefreshErrorCallback(hsdram);
297 #else
298 HAL_SDRAM_RefreshErrorCallback(hsdram);
299 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
300
301 /* Clear SDRAM refresh error interrupt pending bit */
302 __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
303 }
304 }
305
306 /**
307 * @brief SDRAM Refresh error callback.
308 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
309 * the configuration information for SDRAM module.
310 * @retval None
311 */
HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef * hsdram)312 __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
313 {
314 /* Prevent unused argument(s) compilation warning */
315 UNUSED(hsdram);
316
317 /* NOTE: This function Should not be modified, when the callback is needed,
318 the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
319 */
320 }
321
322 /**
323 * @brief DMA transfer complete callback.
324 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
325 * the configuration information for the specified DMA module.
326 * @retval None
327 */
HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef * hdma)328 __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
329 {
330 /* Prevent unused argument(s) compilation warning */
331 UNUSED(hdma);
332
333 /* NOTE: This function Should not be modified, when the callback is needed,
334 the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
335 */
336 }
337
338 /**
339 * @brief DMA transfer complete error callback.
340 * @param hdma DMA handle
341 * @retval None
342 */
HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef * hdma)343 __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
344 {
345 /* Prevent unused argument(s) compilation warning */
346 UNUSED(hdma);
347
348 /* NOTE: This function Should not be modified, when the callback is needed,
349 the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
350 */
351 }
352
353 /**
354 * @}
355 */
356
357 /** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions
358 * @brief Input Output and memory control functions
359 *
360 @verbatim
361 ==============================================================================
362 ##### SDRAM Input and Output functions #####
363 ==============================================================================
364 [..]
365 This section provides functions allowing to use and control the SDRAM memory
366
367 @endverbatim
368 * @{
369 */
370
371 /**
372 * @brief Reads 8-bit data buffer from the SDRAM memory.
373 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
374 * the configuration information for SDRAM module.
375 * @param pAddress Pointer to read start address
376 * @param pDstBuffer Pointer to destination buffer
377 * @param BufferSize Size of the buffer to read from memory
378 * @retval HAL status
379 */
HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint8_t * pDstBuffer,uint32_t BufferSize)380 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer,
381 uint32_t BufferSize)
382 {
383 uint32_t size;
384 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
385 uint8_t *pdestbuff = pDstBuffer;
386 HAL_SDRAM_StateTypeDef state = hsdram->State;
387
388 /* Check the SDRAM controller state */
389 if (state == HAL_SDRAM_STATE_BUSY)
390 {
391 return HAL_BUSY;
392 }
393 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
394 {
395 /* Process Locked */
396 __HAL_LOCK(hsdram);
397
398 /* Update the SDRAM controller state */
399 hsdram->State = HAL_SDRAM_STATE_BUSY;
400
401 /* Read data from source */
402 for (size = BufferSize; size != 0U; size--)
403 {
404 *pdestbuff = *(__IO uint8_t *)pSdramAddress;
405 pdestbuff++;
406 pSdramAddress++;
407 }
408
409 /* Update the SDRAM controller state */
410 hsdram->State = state;
411
412 /* Process Unlocked */
413 __HAL_UNLOCK(hsdram);
414 }
415 else
416 {
417 return HAL_ERROR;
418 }
419
420 return HAL_OK;
421 }
422
423 /**
424 * @brief Writes 8-bit data buffer to SDRAM memory.
425 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
426 * the configuration information for SDRAM module.
427 * @param pAddress Pointer to write start address
428 * @param pSrcBuffer Pointer to source buffer to write
429 * @param BufferSize Size of the buffer to write to memory
430 * @retval HAL status
431 */
HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint8_t * pSrcBuffer,uint32_t BufferSize)432 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer,
433 uint32_t BufferSize)
434 {
435 uint32_t size;
436 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
437 uint8_t *psrcbuff = pSrcBuffer;
438
439 /* Check the SDRAM controller state */
440 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
441 {
442 return HAL_BUSY;
443 }
444 else if (hsdram->State == HAL_SDRAM_STATE_READY)
445 {
446 /* Process Locked */
447 __HAL_LOCK(hsdram);
448
449 /* Update the SDRAM controller state */
450 hsdram->State = HAL_SDRAM_STATE_BUSY;
451
452 /* Write data to memory */
453 for (size = BufferSize; size != 0U; size--)
454 {
455 *(__IO uint8_t *)pSdramAddress = *psrcbuff;
456 psrcbuff++;
457 pSdramAddress++;
458 }
459
460 /* Update the SDRAM controller state */
461 hsdram->State = HAL_SDRAM_STATE_READY;
462
463 /* Process Unlocked */
464 __HAL_UNLOCK(hsdram);
465 }
466 else
467 {
468 return HAL_ERROR;
469 }
470
471 return HAL_OK;
472 }
473
474 /**
475 * @brief Reads 16-bit data buffer from the SDRAM memory.
476 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
477 * the configuration information for SDRAM module.
478 * @param pAddress Pointer to read start address
479 * @param pDstBuffer Pointer to destination buffer
480 * @param BufferSize Size of the buffer to read from memory
481 * @retval HAL status
482 */
HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint16_t * pDstBuffer,uint32_t BufferSize)483 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer,
484 uint32_t BufferSize)
485 {
486 uint32_t size;
487 __IO uint32_t *pSdramAddress = pAddress;
488 uint16_t *pdestbuff = pDstBuffer;
489 HAL_SDRAM_StateTypeDef state = hsdram->State;
490
491 /* Check the SDRAM controller state */
492 if (state == HAL_SDRAM_STATE_BUSY)
493 {
494 return HAL_BUSY;
495 }
496 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
497 {
498 /* Process Locked */
499 __HAL_LOCK(hsdram);
500
501 /* Update the SDRAM controller state */
502 hsdram->State = HAL_SDRAM_STATE_BUSY;
503
504 /* Read data from memory */
505 for (size = BufferSize; size >= 2U ; size -= 2U)
506 {
507 *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
508 pdestbuff++;
509 *pdestbuff = (uint16_t)(((*pSdramAddress) & 0xFFFF0000U) >> 16U);
510 pdestbuff++;
511 pSdramAddress++;
512 }
513
514 /* Read last 16-bits if size is not 32-bits multiple */
515 if ((BufferSize % 2U) != 0U)
516 {
517 *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
518 }
519
520 /* Update the SDRAM controller state */
521 hsdram->State = state;
522
523 /* Process Unlocked */
524 __HAL_UNLOCK(hsdram);
525 }
526 else
527 {
528 return HAL_ERROR;
529 }
530
531 return HAL_OK;
532 }
533
534 /**
535 * @brief Writes 16-bit data buffer to SDRAM memory.
536 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
537 * the configuration information for SDRAM module.
538 * @param pAddress Pointer to write start address
539 * @param pSrcBuffer Pointer to source buffer to write
540 * @param BufferSize Size of the buffer to write to memory
541 * @retval HAL status
542 */
HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint16_t * pSrcBuffer,uint32_t BufferSize)543 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer,
544 uint32_t BufferSize)
545 {
546 uint32_t size;
547 __IO uint32_t *psdramaddress = pAddress;
548 uint16_t *psrcbuff = pSrcBuffer;
549
550 /* Check the SDRAM controller state */
551 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
552 {
553 return HAL_BUSY;
554 }
555 else if (hsdram->State == HAL_SDRAM_STATE_READY)
556 {
557 /* Process Locked */
558 __HAL_LOCK(hsdram);
559
560 /* Update the SDRAM controller state */
561 hsdram->State = HAL_SDRAM_STATE_BUSY;
562
563 /* Write data to memory */
564 for (size = BufferSize; size >= 2U ; size -= 2U)
565 {
566 *psdramaddress = (uint32_t)(*psrcbuff);
567 psrcbuff++;
568 *psdramaddress |= ((uint32_t)(*psrcbuff) << 16U);
569 psrcbuff++;
570 psdramaddress++;
571 }
572
573 /* Write last 16-bits if size is not 32-bits multiple */
574 if ((BufferSize % 2U) != 0U)
575 {
576 *psdramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psdramaddress) & 0xFFFF0000U);
577 }
578
579 /* Update the SDRAM controller state */
580 hsdram->State = HAL_SDRAM_STATE_READY;
581
582 /* Process Unlocked */
583 __HAL_UNLOCK(hsdram);
584 }
585 else
586 {
587 return HAL_ERROR;
588 }
589
590 return HAL_OK;
591 }
592
593 /**
594 * @brief Reads 32-bit data buffer from the SDRAM memory.
595 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
596 * the configuration information for SDRAM module.
597 * @param pAddress Pointer to read start address
598 * @param pDstBuffer Pointer to destination buffer
599 * @param BufferSize Size of the buffer to read from memory
600 * @retval HAL status
601 */
HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)602 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
603 uint32_t BufferSize)
604 {
605 uint32_t size;
606 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
607 uint32_t *pdestbuff = pDstBuffer;
608 HAL_SDRAM_StateTypeDef state = hsdram->State;
609
610 /* Check the SDRAM controller state */
611 if (state == HAL_SDRAM_STATE_BUSY)
612 {
613 return HAL_BUSY;
614 }
615 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
616 {
617 /* Process Locked */
618 __HAL_LOCK(hsdram);
619
620 /* Update the SDRAM controller state */
621 hsdram->State = HAL_SDRAM_STATE_BUSY;
622
623 /* Read data from source */
624 for (size = BufferSize; size != 0U; size--)
625 {
626 *pdestbuff = *(__IO uint32_t *)pSdramAddress;
627 pdestbuff++;
628 pSdramAddress++;
629 }
630
631 /* Update the SDRAM controller state */
632 hsdram->State = state;
633
634 /* Process Unlocked */
635 __HAL_UNLOCK(hsdram);
636 }
637 else
638 {
639 return HAL_ERROR;
640 }
641
642 return HAL_OK;
643 }
644
645 /**
646 * @brief Writes 32-bit data buffer to SDRAM memory.
647 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
648 * the configuration information for SDRAM module.
649 * @param pAddress Pointer to write start address
650 * @param pSrcBuffer Pointer to source buffer to write
651 * @param BufferSize Size of the buffer to write to memory
652 * @retval HAL status
653 */
HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)654 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
655 uint32_t BufferSize)
656 {
657 uint32_t size;
658 __IO uint32_t *pSdramAddress = pAddress;
659 uint32_t *psrcbuff = pSrcBuffer;
660
661 /* Check the SDRAM controller state */
662 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
663 {
664 return HAL_BUSY;
665 }
666 else if (hsdram->State == HAL_SDRAM_STATE_READY)
667 {
668 /* Process Locked */
669 __HAL_LOCK(hsdram);
670
671 /* Update the SDRAM controller state */
672 hsdram->State = HAL_SDRAM_STATE_BUSY;
673
674 /* Write data to memory */
675 for (size = BufferSize; size != 0U; size--)
676 {
677 *pSdramAddress = *psrcbuff;
678 psrcbuff++;
679 pSdramAddress++;
680 }
681
682 /* Update the SDRAM controller state */
683 hsdram->State = HAL_SDRAM_STATE_READY;
684
685 /* Process Unlocked */
686 __HAL_UNLOCK(hsdram);
687 }
688 else
689 {
690 return HAL_ERROR;
691 }
692
693 return HAL_OK;
694 }
695
696 /**
697 * @brief Reads a Words data from the SDRAM memory using DMA transfer.
698 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
699 * the configuration information for SDRAM module.
700 * @param pAddress Pointer to read start address
701 * @param pDstBuffer Pointer to destination buffer
702 * @param BufferSize Size of the buffer to read from memory
703 * @retval HAL status
704 */
HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)705 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
706 uint32_t BufferSize)
707 {
708 HAL_StatusTypeDef status;
709 HAL_SDRAM_StateTypeDef state = hsdram->State;
710 uint32_t size;
711 uint32_t data_width;
712
713 /* Check the SDRAM controller state */
714 if (state == HAL_SDRAM_STATE_BUSY)
715 {
716 status = HAL_BUSY;
717 }
718 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
719 {
720 /* Process Locked */
721 __HAL_LOCK(hsdram);
722
723 /* Update the SDRAM controller state */
724 hsdram->State = HAL_SDRAM_STATE_BUSY;
725
726 /* Configure DMA user callbacks */
727 if (state == HAL_SDRAM_STATE_READY)
728 {
729 hsdram->hdma->XferCpltCallback = SDRAM_DMACplt;
730 }
731 else
732 {
733 hsdram->hdma->XferCpltCallback = SDRAM_DMACpltProt;
734 }
735 hsdram->hdma->XferErrorCallback = SDRAM_DMAError;
736
737 if ((hsdram->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
738 {
739 if ((hsdram->hdma->LinkedListQueue != 0U) && (hsdram->hdma->LinkedListQueue->Head != 0U))
740 {
741 /* Check destination data width and set the size to be transferred */
742 data_width = hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2;
743
744 if (data_width == DMA_DEST_DATAWIDTH_WORD)
745 {
746 size = (BufferSize * 4U);
747 }
748 else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
749 {
750 size = (BufferSize * 2U);
751 }
752 else
753 {
754 size = (BufferSize);
755 }
756 /* Set Source , destination , buffer size */
757 /* Set DMA data size */
758 hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = size;
759 /* Set DMA source address */
760 hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pAddress;
761 /* Set DMA destination address */
762 hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pDstBuffer;
763
764 /* Enable the DMA Stream */
765 status = HAL_DMAEx_List_Start_IT(hsdram->hdma);
766 }
767 else
768 {
769 /* Process Unlocked */
770 __HAL_UNLOCK(hsdram);
771
772 status = HAL_ERROR;
773 }
774 }
775 else
776 {
777 /* Check destination data width and set the size to be transferred */
778 data_width = hsdram->hdma->Init.DestDataWidth;
779
780 if (data_width == DMA_DEST_DATAWIDTH_WORD)
781 {
782 size = (BufferSize * 4U);
783 }
784 else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
785 {
786 size = (BufferSize * 2U);
787 }
788 else
789 {
790 size = (BufferSize);
791 }
792
793 /* Enable the DMA Stream */
794 status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, size);
795 }
796
797 /* Process Unlocked */
798 __HAL_UNLOCK(hsdram);
799 }
800 else
801 {
802 status = HAL_ERROR;
803 }
804
805 return status;
806 }
807
808 /**
809 * @brief Writes a Words data buffer to SDRAM memory using DMA transfer.
810 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
811 * the configuration information for SDRAM module.
812 * @param pAddress Pointer to write start address
813 * @param pSrcBuffer Pointer to source buffer to write
814 * @param BufferSize Size of the buffer to write to memory
815 * @retval HAL status
816 */
HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)817 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
818 uint32_t BufferSize)
819 {
820 HAL_StatusTypeDef status;
821 uint32_t size;
822 uint32_t data_width;
823
824 /* Check the SDRAM controller state */
825 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
826 {
827 status = HAL_BUSY;
828 }
829 else if (hsdram->State == HAL_SDRAM_STATE_READY)
830 {
831 /* Process Locked */
832 __HAL_LOCK(hsdram);
833
834 /* Update the SDRAM controller state */
835 hsdram->State = HAL_SDRAM_STATE_BUSY;
836
837 /* Configure DMA user callbacks */
838 hsdram->hdma->XferCpltCallback = SDRAM_DMACplt;
839 hsdram->hdma->XferErrorCallback = SDRAM_DMAError;
840
841 if ((hsdram->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
842 {
843 if ((hsdram->hdma->LinkedListQueue != 0U) && (hsdram->hdma->LinkedListQueue->Head != 0U))
844 {
845 /* Check destination data width and set the size to be transferred */
846 data_width = hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2;
847
848 if (data_width == DMA_DEST_DATAWIDTH_WORD)
849 {
850 size = (BufferSize * 4U);
851 }
852 else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
853 {
854 size = (BufferSize * 2U);
855 }
856 else
857 {
858 size = (BufferSize);
859 }
860 /* Set Source , destination , buffer size */
861 /* Set DMA data size */
862 hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = size;
863 /* Set DMA source address */
864 hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pSrcBuffer;
865 /* Set DMA destination address */
866 hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pAddress;
867
868 /* Enable the DMA Stream */
869 status = HAL_DMAEx_List_Start_IT(hsdram->hdma);
870 }
871 else
872 {
873 /* Process Unlocked */
874 __HAL_UNLOCK(hsdram);
875
876 status = HAL_ERROR;
877 }
878 }
879 else
880 {
881 /* Check destination data width and set the size to be transferred */
882 data_width = hsdram->hdma->Init.DestDataWidth;
883
884 if (data_width == DMA_DEST_DATAWIDTH_WORD)
885 {
886 size = (BufferSize * 4U);
887 }
888 else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
889 {
890 size = (BufferSize * 2U);
891 }
892 else
893 {
894 size = (BufferSize);
895 }
896
897 /* Enable the DMA Stream */
898 status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, size);
899 }
900
901 /* Process Unlocked */
902 __HAL_UNLOCK(hsdram);
903 }
904 else
905 {
906 status = HAL_ERROR;
907 }
908
909 return status;
910 }
911
912 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
913 /**
914 * @brief Register a User SDRAM Callback
915 * To be used to override the weak predefined callback
916 * @param hsdram : SDRAM handle
917 * @param CallbackId : ID of the callback to be registered
918 * This parameter can be one of the following values:
919 * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID
920 * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID
921 * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID
922 * @param pCallback : pointer to the Callback function
923 * @retval status
924 */
HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef * hsdram,HAL_SDRAM_CallbackIDTypeDef CallbackId,pSDRAM_CallbackTypeDef pCallback)925 HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
926 pSDRAM_CallbackTypeDef pCallback)
927 {
928 HAL_StatusTypeDef status = HAL_OK;
929 HAL_SDRAM_StateTypeDef state;
930
931 if (pCallback == NULL)
932 {
933 return HAL_ERROR;
934 }
935
936 state = hsdram->State;
937 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
938 {
939 switch (CallbackId)
940 {
941 case HAL_SDRAM_MSP_INIT_CB_ID :
942 hsdram->MspInitCallback = pCallback;
943 break;
944 case HAL_SDRAM_MSP_DEINIT_CB_ID :
945 hsdram->MspDeInitCallback = pCallback;
946 break;
947 case HAL_SDRAM_REFRESH_ERR_CB_ID :
948 hsdram->RefreshErrorCallback = pCallback;
949 break;
950 default :
951 /* update return status */
952 status = HAL_ERROR;
953 break;
954 }
955 }
956 else if (hsdram->State == HAL_SDRAM_STATE_RESET)
957 {
958 switch (CallbackId)
959 {
960 case HAL_SDRAM_MSP_INIT_CB_ID :
961 hsdram->MspInitCallback = pCallback;
962 break;
963 case HAL_SDRAM_MSP_DEINIT_CB_ID :
964 hsdram->MspDeInitCallback = pCallback;
965 break;
966 default :
967 /* update return status */
968 status = HAL_ERROR;
969 break;
970 }
971 }
972 else
973 {
974 /* update return status */
975 status = HAL_ERROR;
976 }
977
978 return status;
979 }
980
981 /**
982 * @brief Unregister a User SDRAM Callback
983 * SDRAM Callback is redirected to the weak predefined callback
984 * @param hsdram : SDRAM handle
985 * @param CallbackId : ID of the callback to be unregistered
986 * This parameter can be one of the following values:
987 * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID
988 * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID
989 * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID
990 * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID
991 * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID
992 * @retval status
993 */
HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef * hsdram,HAL_SDRAM_CallbackIDTypeDef CallbackId)994 HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId)
995 {
996 HAL_StatusTypeDef status = HAL_OK;
997 HAL_SDRAM_StateTypeDef state;
998
999 state = hsdram->State;
1000 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
1001 {
1002 switch (CallbackId)
1003 {
1004 case HAL_SDRAM_MSP_INIT_CB_ID :
1005 hsdram->MspInitCallback = HAL_SDRAM_MspInit;
1006 break;
1007 case HAL_SDRAM_MSP_DEINIT_CB_ID :
1008 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
1009 break;
1010 case HAL_SDRAM_REFRESH_ERR_CB_ID :
1011 hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
1012 break;
1013 case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
1014 hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
1015 break;
1016 case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
1017 hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
1018 break;
1019 default :
1020 /* update return status */
1021 status = HAL_ERROR;
1022 break;
1023 }
1024 }
1025 else if (hsdram->State == HAL_SDRAM_STATE_RESET)
1026 {
1027 switch (CallbackId)
1028 {
1029 case HAL_SDRAM_MSP_INIT_CB_ID :
1030 hsdram->MspInitCallback = HAL_SDRAM_MspInit;
1031 break;
1032 case HAL_SDRAM_MSP_DEINIT_CB_ID :
1033 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
1034 break;
1035 default :
1036 /* update return status */
1037 status = HAL_ERROR;
1038 break;
1039 }
1040 }
1041 else
1042 {
1043 /* update return status */
1044 status = HAL_ERROR;
1045 }
1046
1047 return status;
1048 }
1049
1050 /**
1051 * @brief Register a User SDRAM Callback for DMA transfers
1052 * To be used to override the weak predefined callback
1053 * @param hsdram : SDRAM handle
1054 * @param CallbackId : ID of the callback to be registered
1055 * This parameter can be one of the following values:
1056 * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID
1057 * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID
1058 * @param pCallback : pointer to the Callback function
1059 * @retval status
1060 */
HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef * hsdram,HAL_SDRAM_CallbackIDTypeDef CallbackId,pSDRAM_DmaCallbackTypeDef pCallback)1061 HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
1062 pSDRAM_DmaCallbackTypeDef pCallback)
1063 {
1064 HAL_StatusTypeDef status = HAL_OK;
1065 HAL_SDRAM_StateTypeDef state;
1066
1067 if (pCallback == NULL)
1068 {
1069 return HAL_ERROR;
1070 }
1071
1072 /* Process locked */
1073 __HAL_LOCK(hsdram);
1074
1075 state = hsdram->State;
1076 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
1077 {
1078 switch (CallbackId)
1079 {
1080 case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
1081 hsdram->DmaXferCpltCallback = pCallback;
1082 break;
1083 case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
1084 hsdram->DmaXferErrorCallback = pCallback;
1085 break;
1086 default :
1087 /* update return status */
1088 status = HAL_ERROR;
1089 break;
1090 }
1091 }
1092 else
1093 {
1094 /* update return status */
1095 status = HAL_ERROR;
1096 }
1097
1098 /* Release Lock */
1099 __HAL_UNLOCK(hsdram);
1100 return status;
1101 }
1102 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
1103
1104 /**
1105 * @}
1106 */
1107
1108 /** @defgroup SDRAM_Exported_Functions_Group3 Control functions
1109 * @brief management functions
1110 *
1111 @verbatim
1112 ==============================================================================
1113 ##### SDRAM Control functions #####
1114 ==============================================================================
1115 [..]
1116 This subsection provides a set of functions allowing to control dynamically
1117 the SDRAM interface.
1118
1119 @endverbatim
1120 * @{
1121 */
1122
1123 /**
1124 * @brief Enables dynamically SDRAM write protection.
1125 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1126 * the configuration information for SDRAM module.
1127 * @retval HAL status
1128 */
HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef * hsdram)1129 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
1130 {
1131 /* Check the SDRAM controller state */
1132 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
1133 {
1134 return HAL_BUSY;
1135 }
1136 else if (hsdram->State == HAL_SDRAM_STATE_READY)
1137 {
1138 /* Update the SDRAM state */
1139 hsdram->State = HAL_SDRAM_STATE_BUSY;
1140
1141 /* Enable write protection */
1142 (void)FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
1143
1144 /* Update the SDRAM state */
1145 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
1146 }
1147 else
1148 {
1149 return HAL_ERROR;
1150 }
1151
1152 return HAL_OK;
1153 }
1154
1155 /**
1156 * @brief Disables dynamically SDRAM write protection.
1157 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1158 * the configuration information for SDRAM module.
1159 * @retval HAL status
1160 */
HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef * hsdram)1161 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
1162 {
1163 HAL_SDRAM_StateTypeDef state = hsdram->State;
1164
1165 /* Check the SDRAM controller state */
1166 if (state == HAL_SDRAM_STATE_BUSY)
1167 {
1168 return HAL_BUSY;
1169 }
1170 else if (state == HAL_SDRAM_STATE_WRITE_PROTECTED)
1171 {
1172 /* Update the SDRAM state */
1173 hsdram->State = HAL_SDRAM_STATE_BUSY;
1174
1175 /* Disable write protection */
1176 (void)FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
1177
1178 /* Update the SDRAM state */
1179 hsdram->State = HAL_SDRAM_STATE_READY;
1180 }
1181 else
1182 {
1183 return HAL_ERROR;
1184 }
1185
1186 return HAL_OK;
1187 }
1188
1189 /**
1190 * @brief Sends Command to the SDRAM bank.
1191 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1192 * the configuration information for SDRAM module.
1193 * @param Command SDRAM command structure
1194 * @param Timeout Timeout duration
1195 * @retval HAL status
1196 */
HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef * hsdram,FMC_SDRAM_CommandTypeDef * Command,uint32_t Timeout)1197 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command,
1198 uint32_t Timeout)
1199 {
1200 HAL_SDRAM_StateTypeDef state = hsdram->State;
1201
1202 /* Check the SDRAM controller state */
1203 if (state == HAL_SDRAM_STATE_BUSY)
1204 {
1205 return HAL_BUSY;
1206 }
1207 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_PRECHARGED))
1208 {
1209 /* Update the SDRAM state */
1210 hsdram->State = HAL_SDRAM_STATE_BUSY;
1211
1212 /* Send SDRAM command */
1213 (void)FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
1214
1215 /* Update the SDRAM controller state state */
1216 if (Command->CommandMode == FMC_SDRAM_CMD_PALL)
1217 {
1218 hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
1219 }
1220 else
1221 {
1222 hsdram->State = HAL_SDRAM_STATE_READY;
1223 }
1224 }
1225 else
1226 {
1227 return HAL_ERROR;
1228 }
1229
1230 return HAL_OK;
1231 }
1232
1233 /**
1234 * @brief Programs the SDRAM Memory Refresh rate.
1235 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1236 * the configuration information for SDRAM module.
1237 * @param RefreshRate The SDRAM refresh rate value
1238 * @retval HAL status
1239 */
HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef * hsdram,uint32_t RefreshRate)1240 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
1241 {
1242 /* Check the SDRAM controller state */
1243 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
1244 {
1245 return HAL_BUSY;
1246 }
1247 else if (hsdram->State == HAL_SDRAM_STATE_READY)
1248 {
1249 /* Update the SDRAM state */
1250 hsdram->State = HAL_SDRAM_STATE_BUSY;
1251
1252 /* Program the refresh rate */
1253 (void)FMC_SDRAM_ProgramRefreshRate(hsdram->Instance, RefreshRate);
1254
1255 /* Update the SDRAM state */
1256 hsdram->State = HAL_SDRAM_STATE_READY;
1257 }
1258 else
1259 {
1260 return HAL_ERROR;
1261 }
1262
1263 return HAL_OK;
1264 }
1265
1266 /**
1267 * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
1268 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1269 * the configuration information for SDRAM module.
1270 * @param AutoRefreshNumber The SDRAM auto Refresh number
1271 * @retval HAL status
1272 */
HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef * hsdram,uint32_t AutoRefreshNumber)1273 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
1274 {
1275 /* Check the SDRAM controller state */
1276 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
1277 {
1278 return HAL_BUSY;
1279 }
1280 else if (hsdram->State == HAL_SDRAM_STATE_READY)
1281 {
1282 /* Update the SDRAM state */
1283 hsdram->State = HAL_SDRAM_STATE_BUSY;
1284
1285 /* Set the Auto-Refresh number */
1286 (void)FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance, AutoRefreshNumber);
1287
1288 /* Update the SDRAM state */
1289 hsdram->State = HAL_SDRAM_STATE_READY;
1290 }
1291 else
1292 {
1293 return HAL_ERROR;
1294 }
1295
1296 return HAL_OK;
1297 }
1298
1299 /**
1300 * @brief Returns the SDRAM memory current mode.
1301 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1302 * the configuration information for SDRAM module.
1303 * @retval The SDRAM memory mode.
1304 */
HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef * hsdram)1305 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
1306 {
1307 /* Return the SDRAM memory current mode */
1308 return (FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
1309 }
1310
1311 /**
1312 * @}
1313 */
1314
1315 /** @defgroup SDRAM_Exported_Functions_Group4 State functions
1316 * @brief Peripheral State functions
1317 *
1318 @verbatim
1319 ==============================================================================
1320 ##### SDRAM State functions #####
1321 ==============================================================================
1322 [..]
1323 This subsection permits to get in run-time the status of the SDRAM controller
1324 and the data flow.
1325
1326 @endverbatim
1327 * @{
1328 */
1329
1330 /**
1331 * @brief Returns the SDRAM state.
1332 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1333 * the configuration information for SDRAM module.
1334 * @retval HAL state
1335 */
HAL_SDRAM_GetState(const SDRAM_HandleTypeDef * hsdram)1336 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(const SDRAM_HandleTypeDef *hsdram)
1337 {
1338 return hsdram->State;
1339 }
1340
1341 /**
1342 * @}
1343 */
1344
1345 /**
1346 * @}
1347 */
1348
1349 /** @addtogroup SDRAM_Private_Functions SDRAM Private Functions
1350 * @{
1351 */
1352 /**
1353 * @brief DMA SDRAM process complete callback.
1354 * @param hdma : DMA handle
1355 * @retval None
1356 */
SDRAM_DMACplt(DMA_HandleTypeDef * hdma)1357 static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma)
1358 {
1359 /* Derogation MISRAC2012-Rule-11.5 */
1360 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
1361
1362 /* Disable the DMA channel */
1363 __HAL_DMA_DISABLE(hdma);
1364
1365 /* Update the SDRAM controller state */
1366 hsdram->State = HAL_SDRAM_STATE_READY;
1367
1368 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
1369 hsdram->DmaXferCpltCallback(hdma);
1370 #else
1371 HAL_SDRAM_DMA_XferCpltCallback(hdma);
1372 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
1373 }
1374
1375 /**
1376 * @brief DMA SRAM process complete callback.
1377 * @param hdma : DMA handle
1378 * @retval None
1379 */
SDRAM_DMACpltProt(DMA_HandleTypeDef * hdma)1380 static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
1381 {
1382 /* Derogation MISRAC2012-Rule-11.5 */
1383 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
1384
1385 /* Disable the DMA channel */
1386 __HAL_DMA_DISABLE(hdma);
1387
1388 /* Update the SDRAM controller state */
1389 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
1390
1391 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
1392 hsdram->DmaXferCpltCallback(hdma);
1393 #else
1394 HAL_SDRAM_DMA_XferCpltCallback(hdma);
1395 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
1396 }
1397
1398 /**
1399 * @brief DMA SDRAM error callback.
1400 * @param hdma : DMA handle
1401 * @retval None
1402 */
SDRAM_DMAError(DMA_HandleTypeDef * hdma)1403 static void SDRAM_DMAError(DMA_HandleTypeDef *hdma)
1404 {
1405 /* Derogation MISRAC2012-Rule-11.5 */
1406 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
1407
1408 /* Disable the DMA channel */
1409 __HAL_DMA_DISABLE(hdma);
1410
1411 /* Update the SDRAM controller state */
1412 hsdram->State = HAL_SDRAM_STATE_ERROR;
1413
1414 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
1415 hsdram->DmaXferErrorCallback(hdma);
1416 #else
1417 HAL_SDRAM_DMA_XferErrorCallback(hdma);
1418 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
1419 }
1420
1421 /**
1422 * @}
1423 */
1424 /**
1425 * @}
1426 */
1427
1428 #endif /* HAL_SDRAM_MODULE_ENABLED */
1429
1430 /**
1431 * @}
1432 */
1433
1434 #endif /* FMC_Bank5_6_R */
1435
