1 /**
2 ******************************************************************************
3 * @file stm32h5xx_hal_rcc_ex.c
4 * @author MCD Application Team
5 * @brief Extended RCC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities RCC extended peripheral:
8 * + Extended Peripheral Control functions
9 * + Extended Clock management functions
10 * + Extended Clock Recovery System Control functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2023 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 */
24
25 /* Includes ------------------------------------------------------------------*/
26 #include "stm32h5xx_hal.h"
27
28 /** @addtogroup STM32H5xx_HAL_Driver
29 * @{
30 */
31
32 /** @defgroup RCCEx RCCEx
33 * @brief RCC Extended HAL module driver
34 * @{
35 */
36
37 #ifdef HAL_RCC_MODULE_ENABLED
38
39 /* Private typedef -----------------------------------------------------------*/
40 /* Private defines -----------------------------------------------------------*/
41 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants
42 * @{
43 */
44 #define PLL1_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
45 #define PLL2_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
46 #if defined(RCC_CR_PLL3ON)
47 #define PLL3_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
48 #endif /* RCC_CR_PLL3ON */
49
50 /**
51 * @}
52 */
53
54 /* Private macros ------------------------------------------------------------*/
55 /* Private variables ---------------------------------------------------------*/
56 /* Private function prototypes -----------------------------------------------*/
57 /** @defgroup RCCEx_Private_Functions RCCEx Private Functions
58 * @{
59 */
60 static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource);
61 static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *Pll2);
62 #if defined(RCC_CR_PLL3ON)
63 static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *Pll3);
64 #endif /* RCC_CR_PLL3ON */
65 /**
66 * @}
67 */
68
69 /* Exported functions --------------------------------------------------------*/
70
71 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
72 * @{
73 */
74
75 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
76 * @brief Extended Peripheral Control functions
77 *
78 @verbatim
79 ===============================================================================
80 ##### Extended Peripheral Control functions #####
81 ===============================================================================
82 [..]
83 This subsection provides a set of functions allowing to control the RCC Clocks
84 frequencies.
85 [..]
86 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
87 select the RTC clock source; in this case the Backup domain will be reset in
88 order to modify the RTC Clock source, as consequence RTC registers (including
89 the backup registers) are set to their reset values.
90
91 @endverbatim
92 * @{
93 */
94 /**
95 * @brief Initialize the RCC extended peripherals clocks according to the specified
96 * parameters in the RCC_PeriphCLKInitTypeDef.
97 * @param pPeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
98 * contains a field PeriphClockSelection which can be a combination of the following values:
99 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
100 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
101 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
102 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (*)
103 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (*)
104 * @arg @ref RCC_PERIPHCLK_USART6 USART6 peripheral clock (*)
105 * @arg @ref RCC_PERIPHCLK_UART7 UART7 peripheral clock (*)
106 * @arg @ref RCC_PERIPHCLK_UART8 UART8 peripheral clock (*)
107 * @arg @ref RCC_PERIPHCLK_UART9 UART9 peripheral clock (*)
108 * @arg @ref RCC_PERIPHCLK_USART10 USART10 peripheral clock (*)
109 * @arg @ref RCC_PERIPHCLK_USART11 USART11 peripheral clock (*)
110 * @arg @ref RCC_PERIPHCLK_UART12 UART12 peripheral clock (*)
111 * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
112 * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
113 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
114 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock (*)
115 * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (*)
116 * @arg @ref RCC_PERIPHCLK_I3C1 I3C1 peripheral clock
117 * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
118 * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
119 * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock (*)
120 * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (*)
121 * @arg @ref RCC_PERIPHCLK_ADCDAC ADCDAC peripheral clock
122 * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock
123 * @arg @ref RCC_PERIPHCLK_SDMMC1 SDMMC1 peripheral clock (*)
124 * @arg @ref RCC_PERIPHCLK_SDMMC2 SDMMC2 peripheral clock (**)
125 * @arg @ref RCC_PERIPHCLK_CKPER CKPER peripheral clock
126 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
127 * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
128 * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock
129 * @arg @ref RCC_PERIPHCLK_SPI2 SPI2 peripheral clock
130 * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock
131 * @arg @ref RCC_PERIPHCLK_SPI4 SPI4 peripheral clock (*)
132 * @arg @ref RCC_PERIPHCLK_SPI5 SPI5 peripheral clock (*)
133 * @arg @ref RCC_PERIPHCLK_SPI6 SPI6 peripheral clock (*)
134 * @arg @ref RCC_PERIPHCLK_OSPI OCTOSPI peripheral clock (*)
135 * @arg @ref RCC_PERIPHCLK_FDCAN FDCAN peripheral clock
136 * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock (*)
137 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
138 * @arg @ref RCC_PERIPHCLK_LPTIM3 LPTIM3 peripheral clock (*)
139 * @arg @ref RCC_PERIPHCLK_LPTIM4 LPTIM4 peripheral clock (*)
140 * @arg @ref RCC_PERIPHCLK_LPTIM5 LPTIM5 peripheral clock (*)
141 * @arg @ref RCC_PERIPHCLK_LPTIM6 LPTIM6 peripheral clock (*)
142 * @arg @ref RCC_PERIPHCLK_DAC_LP DAC peripheral low-power clock
143 * @arg @ref RCC_PERIPHCLK_TIM TIM peripheral clock
144 *
145 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
146 * the RTC clock source: in this case the access to Backup domain is enabled.
147 *
148 * @retval HAL status
149 *
150 * (*) : For stm32h56xxx and stm32h57xxx family lines only.
151 * (**) : For stm32h563xx and stm32h57xxx family lines only.
152 * (***) : For stm32h503xx family line only.
153 */
HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef * pPeriphClkInit)154 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPeriphClkInit)
155 {
156 uint32_t tmpregister;
157 uint32_t tickstart;
158 HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
159 HAL_StatusTypeDef status = HAL_OK; /* Final status */
160
161 /* Check the parameters */
162 assert_param(IS_RCC_PERIPHCLOCK(pPeriphClkInit->PeriphClockSelection));
163
164 /*------------------------------------ CKPER configuration --------------------------------------*/
165 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER)
166 {
167 /* Check the parameters */
168 assert_param(IS_RCC_CLKPSOURCE(pPeriphClkInit->CkperClockSelection));
169
170 /* Configure the CKPER clock source */
171 __HAL_RCC_CLKP_CONFIG(pPeriphClkInit->CkperClockSelection);
172 }
173
174 /*-------------------------- USART1 clock source configuration -------------------*/
175 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
176 {
177 /* Check the parameters */
178 assert_param(IS_RCC_USART1CLKSOURCE(pPeriphClkInit->Usart1ClockSelection));
179
180 switch (pPeriphClkInit->Usart1ClockSelection)
181 {
182 case RCC_USART1CLKSOURCE_PCLK2: /* PCLK2 is used as clock source for USART1*/
183
184 /* USART1 clock source config set later after clock selection check */
185 break;
186
187 case RCC_USART1CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for USART1*/
188 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
189 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
190 /* USART1 clock source config set later after clock selection check */
191 break;
192 #if defined(RCC_USART1CLKSOURCE_PLL3Q)
193 case RCC_USART1CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for USART1*/
194 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
195 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
196 /* USART1 clock source config set later after clock selection check */
197 break;
198 #endif /* RCC_CR_PLL3ON */
199
200 case RCC_USART1CLKSOURCE_HSI: /* HSI clock is used as source of USART1 clock*/
201 /* USART1 clock source config set later after clock selection check */
202 break;
203
204 case RCC_USART1CLKSOURCE_CSI: /* CSI clock is used as source of USART1 clock*/
205 /* USART1 clock source config set later after clock selection check */
206 break;
207
208 case RCC_USART1CLKSOURCE_LSE: /* LSE clock is used as source of USART1 clock*/
209 /* USART1 clock source config set later after clock selection check */
210 break;
211
212 default:
213 ret = HAL_ERROR;
214 break;
215 }
216
217 if (ret == HAL_OK)
218 {
219 /* Set the source of USART1 clock*/
220 __HAL_RCC_USART1_CONFIG(pPeriphClkInit->Usart1ClockSelection);
221 }
222 else
223 {
224 /* set overall return value */
225 status = ret;
226 }
227 }
228
229 /*-------------------------- USART2 clock source configuration -------------------*/
230 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
231 {
232 /* Check the parameters */
233 assert_param(IS_RCC_USART2CLKSOURCE(pPeriphClkInit->Usart2ClockSelection));
234
235 switch (pPeriphClkInit->Usart2ClockSelection)
236 {
237 case RCC_USART2CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for USART2*/
238
239 /* USART2 clock source config set later after clock selection check */
240 break;
241
242 case RCC_USART2CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for USART2*/
243 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
244 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
245 /* USART2 clock source config set later after clock selection check */
246 break;
247
248 #if defined(RCC_USART2CLKSOURCE_PLL3Q)
249 case RCC_USART2CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for USART2*/
250 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
251 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
252 /* USART2 clock source config set later after clock selection check */
253 break;
254 #endif /* RCC_USART2CLKSOURCE_PLL3 */
255
256 case RCC_USART2CLKSOURCE_HSI: /* HSI clock is used as source of USART2 clock*/
257 /* USART2 clock source config set later after clock selection check */
258 break;
259
260 case RCC_USART2CLKSOURCE_CSI: /* CSI clock is used as source of USART2 clock*/
261 /* USART2 clock source config set later after clock selection check */
262 break;
263
264 case RCC_USART2CLKSOURCE_LSE: /* LSE clock is used as source of USART2 clock*/
265 /* USART2 clock source config set later after clock selection check */
266 break;
267
268 default:
269 ret = HAL_ERROR;
270 break;
271 }
272
273 if (ret == HAL_OK)
274 {
275 /* Set the source of USART2 clock*/
276 __HAL_RCC_USART2_CONFIG(pPeriphClkInit->Usart2ClockSelection);
277 }
278 else
279 {
280 /* set overall return value */
281 status = ret;
282 }
283 }
284
285 /*-------------------------- USART3 clock source configuration -------------------*/
286 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
287 {
288 /* Check the parameters */
289 assert_param(IS_RCC_USART3CLKSOURCE(pPeriphClkInit->Usart3ClockSelection));
290
291 switch (pPeriphClkInit->Usart3ClockSelection)
292 {
293 case RCC_USART3CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for USART3*/
294
295 /* USART3 clock source config set later after clock selection check */
296 break;
297
298 case RCC_USART3CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for USART3*/
299 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
300 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
301 /* USART3 clock source config set later after clock selection check */
302 break;
303
304 #if defined(RCC_USART3CLKSOURCE_PLL3Q)
305 case RCC_USART3CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for USART3*/
306 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
307 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
308 /* USART3 clock source config set later after clock selection check */
309 break;
310 #endif /* RCC_USART3CLKSOURCE_PLL3 */
311
312 case RCC_USART3CLKSOURCE_HSI: /* HSI clock is used as source of USART3 clock*/
313 /* USART3 clock source config set later after clock selection check */
314 break;
315
316 case RCC_USART3CLKSOURCE_CSI: /* CSI clock is used as source of USART3 clock*/
317 /* USART3 clock source config set later after clock selection check */
318 break;
319
320 case RCC_USART3CLKSOURCE_LSE: /* LSE clock is used as source of USART3 clock*/
321 /* USART3 clock source config set later after clock selection check */
322 break;
323
324 default:
325 ret = HAL_ERROR;
326 break;
327 }
328
329 if (ret == HAL_OK)
330 {
331 /* Set the source of USART3 clock*/
332 __HAL_RCC_USART3_CONFIG(pPeriphClkInit->Usart3ClockSelection);
333 }
334 else
335 {
336 /* set overall return value */
337 status = ret;
338 }
339 }
340
341 #if defined(UART4)
342 /*-------------------------- UART4 clock source configuration --------------------*/
343 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
344 {
345 /* Check the parameters */
346 assert_param(IS_RCC_UART4CLKSOURCE(pPeriphClkInit->Uart4ClockSelection));
347
348 switch (pPeriphClkInit->Uart4ClockSelection)
349 {
350 case RCC_UART4CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for UART4*/
351
352 /* UART4 clock source config set later after clock selection check */
353 break;
354
355 case RCC_UART4CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for UART4*/
356 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
357 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
358 /* UART4 clock source config set later after clock selection check */
359 break;
360
361 case RCC_UART4CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for UART4*/
362 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
363 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
364 /* UART4 clock source config set later after clock selection check */
365 break;
366
367 case RCC_UART4CLKSOURCE_HSI: /* HSI clock is used as source of UART4 clock*/
368 /* UART4 clock source config set later after clock selection check */
369 break;
370
371 case RCC_UART4CLKSOURCE_CSI: /* CSI clock is used as source of UART4 clock*/
372 /* UART4 clock source config set later after clock selection check */
373 break;
374
375 case RCC_UART4CLKSOURCE_LSE: /* LSE clock is used as source of UART4 clock*/
376 /* UART4 clock source config set later after clock selection check */
377 break;
378
379 default:
380 ret = HAL_ERROR;
381 break;
382 }
383
384 if (ret == HAL_OK)
385 {
386 /* Set the source of UART4 clock*/
387 __HAL_RCC_UART4_CONFIG(pPeriphClkInit->Uart4ClockSelection);
388 }
389 else
390 {
391 /* set overall return value */
392 status = ret;
393 }
394 }
395 #endif /* UART4 */
396
397 #if defined(UART5)
398 /*-------------------------- UART5 clock source configuration --------------------*/
399 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
400 {
401 /* Check the parameters */
402 assert_param(IS_RCC_UART5CLKSOURCE(pPeriphClkInit->Uart5ClockSelection));
403
404 switch (pPeriphClkInit->Uart5ClockSelection)
405 {
406 case RCC_UART5CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for UART5*/
407
408 /* UART5 clock source config set later after clock selection check */
409 break;
410
411 case RCC_UART5CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for UART5*/
412 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
413 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
414 /* UART5 clock source config set later after clock selection check */
415 break;
416
417 case RCC_UART5CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for UART5*/
418 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
419 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
420 /* UART5 clock source config set later after clock selection check */
421 break;
422
423 case RCC_UART5CLKSOURCE_HSI: /* HSI clock is used as source of UART5 clock*/
424 /* UART5 clock source config set later after clock selection check */
425 break;
426
427 case RCC_UART5CLKSOURCE_CSI: /* CSI clock is used as source of UART5 clock*/
428 /* UART5 clock source config set later after clock selection check */
429 break;
430
431 case RCC_UART5CLKSOURCE_LSE: /* LSE clock is used as source of UART5 clock*/
432 /* UART5 clock source config set later after clock selection check */
433 break;
434
435 default:
436 ret = HAL_ERROR;
437 break;
438 }
439
440 if (ret == HAL_OK)
441 {
442 /* Set the source of UART5 clock*/
443 __HAL_RCC_UART5_CONFIG(pPeriphClkInit->Uart5ClockSelection);
444 }
445 else
446 {
447 /* set overall return value */
448 status = ret;
449 }
450 }
451 #endif /* UART5 */
452
453 #if defined(USART6)
454 /*-------------------------- USART6 clock source configuration -------------------*/
455 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
456 {
457 /* Check the parameters */
458 assert_param(IS_RCC_USART6CLKSOURCE(pPeriphClkInit->Usart6ClockSelection));
459
460 switch (pPeriphClkInit->Usart6ClockSelection)
461 {
462 case RCC_USART6CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for USART6*/
463
464 /* USART6 clock source config set later after clock selection check */
465 break;
466
467 case RCC_USART6CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for USART6*/
468 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
469 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
470 /* USART6 clock source config set later after clock selection check */
471 break;
472
473 case RCC_USART6CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for USART6*/
474 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
475 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
476 /* USART6 clock source config set later after clock selection check */
477 break;
478
479 case RCC_USART6CLKSOURCE_HSI: /* HSI clock is used as source of USART6 clock*/
480 /* USART6 clock source config set later after clock selection check */
481 break;
482
483 case RCC_USART6CLKSOURCE_CSI: /* CSI clock is used as source of USART6 clock*/
484 /* USART6 clock source config set later after clock selection check */
485 break;
486
487 case RCC_USART6CLKSOURCE_LSE: /* LSE clock is used as source of USART6 clock*/
488 /* USART6 clock source config set later after clock selection check */
489 break;
490
491 default:
492 ret = HAL_ERROR;
493 break;
494 }
495
496 if (ret == HAL_OK)
497 {
498 /* Set the source of USART6 clock*/
499 __HAL_RCC_USART6_CONFIG(pPeriphClkInit->Usart6ClockSelection);
500 }
501 else
502 {
503 /* set overall return value */
504 status = ret;
505 }
506 }
507 #endif /* USART6 */
508
509 #if defined(UART7)
510 /*-------------------------- UART7 clock source configuration -------------------*/
511 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
512 {
513 /* Check the parameters */
514 assert_param(IS_RCC_UART7CLKSOURCE(pPeriphClkInit->Uart7ClockSelection));
515
516 switch (pPeriphClkInit->Uart7ClockSelection)
517 {
518 case RCC_UART7CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for UART7*/
519
520 /* UART7 clock source config set later after clock selection check */
521 break;
522
523 case RCC_UART7CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for UART7*/
524 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
525 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
526 /* UART7 clock source config set later after clock selection check */
527 break;
528
529 case RCC_UART7CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for UART7*/
530 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
531 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
532 /* UART7 clock source config set later after clock selection check */
533 break;
534
535 case RCC_UART7CLKSOURCE_HSI: /* HSI clock is used as source of UART7 clock*/
536 /* UART7 clock source config set later after clock selection check */
537 break;
538
539 case RCC_UART7CLKSOURCE_CSI: /* CSI clock is used as source of UART7 clock*/
540 /* UART7 clock source config set later after clock selection check */
541 break;
542
543 case RCC_UART7CLKSOURCE_LSE: /* LSE clock is used as source of UART7 clock*/
544 /* UART7 clock source config set later after clock selection check */
545 break;
546
547 default:
548 ret = HAL_ERROR;
549 break;
550 }
551
552 if (ret == HAL_OK)
553 {
554 /* Set the source of UART7 clock*/
555 __HAL_RCC_UART7_CONFIG(pPeriphClkInit->Uart7ClockSelection);
556 }
557 else
558 {
559 /* set overall return value */
560 status = ret;
561 }
562 }
563 #endif /* UART7 */
564
565 #if defined(UART8)
566 /*-------------------------- UART8 clock source configuration -------------------*/
567 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
568 {
569 /* Check the parameters */
570 assert_param(IS_RCC_UART8CLKSOURCE(pPeriphClkInit->Uart8ClockSelection));
571
572 switch (pPeriphClkInit->Uart8ClockSelection)
573 {
574 case RCC_UART8CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for UART8*/
575
576 /* UART8 clock source config set later after clock selection check */
577 break;
578
579 case RCC_UART8CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for UART8*/
580 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
581 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
582 /* UART8 clock source config set later after clock selection check */
583 break;
584
585 case RCC_UART8CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for UART8*/
586 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
587 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
588 /* UART8 clock source config set later after clock selection check */
589 break;
590
591 case RCC_UART8CLKSOURCE_HSI: /* HSI clock is used as source of UART8 clock*/
592 /* UART8 clock source config set later after clock selection check */
593 break;
594
595 case RCC_UART8CLKSOURCE_CSI: /* CSI clock is used as source of UART8 clock*/
596 /* UART8 clock source config set later after clock selection check */
597 break;
598
599 case RCC_UART8CLKSOURCE_LSE: /* LSE clock is used as source of UART8 clock*/
600 /* UART8 clock source config set later after clock selection check */
601 break;
602
603 default:
604 ret = HAL_ERROR;
605 break;
606 }
607
608 if (ret == HAL_OK)
609 {
610 /* Set the source of UART8 clock*/
611 __HAL_RCC_UART8_CONFIG(pPeriphClkInit->Uart8ClockSelection);
612 }
613 else
614 {
615 /* set overall return value */
616 status = ret;
617 }
618 }
619 #endif /* UART9 */
620
621 #if defined(UART9)
622 /*-------------------------- UART9 clock source configuration -------------------*/
623 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART9) == RCC_PERIPHCLK_UART9)
624 {
625 /* Check the parameters */
626 assert_param(IS_RCC_UART9CLKSOURCE(pPeriphClkInit->Uart9ClockSelection));
627
628 switch (pPeriphClkInit->Uart9ClockSelection)
629 {
630 case RCC_UART9CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for UART9*/
631
632 /* UART9 clock source config set later after clock selection check */
633 break;
634
635 case RCC_UART9CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for UART9*/
636 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
637 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
638 /* UART9 clock source config set later after clock selection check */
639 break;
640
641 case RCC_UART9CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for UART9*/
642 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
643 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
644 /* UART9 clock source config set later after clock selection check */
645 break;
646
647 case RCC_UART9CLKSOURCE_HSI: /* HSI clock is used as source of UART9 clock*/
648 /* UART9 clock source config set later after clock selection check */
649 break;
650
651 case RCC_UART9CLKSOURCE_CSI: /* CSI clock is used as source of UART9 clock*/
652 /* UART9 clock source config set later after clock selection check */
653 break;
654
655 case RCC_UART9CLKSOURCE_LSE: /* LSE clock is used as source of UART9 clock*/
656 /* UART9 clock source config set later after clock selection check */
657 break;
658
659 default:
660 ret = HAL_ERROR;
661 break;
662 }
663
664 if (ret == HAL_OK)
665 {
666 /* Set the source of UART9 clock*/
667 __HAL_RCC_UART9_CONFIG(pPeriphClkInit->Uart9ClockSelection);
668 }
669 else
670 {
671 /* set overall return value */
672 status = ret;
673 }
674 }
675 #endif /* UART9 */
676
677 #if defined(USART10)
678 /*-------------------------- USART10 clock source configuration -------------------*/
679 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART10) == RCC_PERIPHCLK_USART10)
680 {
681 /* Check the parameters */
682 assert_param(IS_RCC_USART10CLKSOURCE(pPeriphClkInit->Usart10ClockSelection));
683
684 switch (pPeriphClkInit->Usart10ClockSelection)
685 {
686 case RCC_USART10CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for USART10*/
687
688 /* USART10 clock source config set later after clock selection check */
689 break;
690
691 case RCC_USART10CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for USART10*/
692 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
693 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
694 /* USART10 clock source config set later after clock selection check */
695 break;
696
697 case RCC_USART10CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for USART10*/
698 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
699 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
700 /* USART10 clock source config set later after clock selection check */
701 break;
702
703 case RCC_USART10CLKSOURCE_HSI: /* HSI clock is used as source of USART10 clock*/
704 /* USART10 clock source config set later after clock selection check */
705 break;
706
707 case RCC_USART10CLKSOURCE_CSI: /* CSI clock is used as source of USART10 clock*/
708 /* USART10 clock source config set later after clock selection check */
709 break;
710
711 case RCC_USART10CLKSOURCE_LSE: /* LSE clock is used as source of USART10 clock*/
712 /* USART10 clock source config set later after clock selection check */
713 break;
714
715 default:
716 ret = HAL_ERROR;
717 break;
718 }
719
720 if (ret == HAL_OK)
721 {
722 /* Set the source of USART10 clock*/
723 __HAL_RCC_USART10_CONFIG(pPeriphClkInit->Usart10ClockSelection);
724 }
725 else
726 {
727 /* set overall return value */
728 status = ret;
729 }
730 }
731 #endif /* USART10 */
732
733 #if defined(USART11)
734 /*-------------------------- USART11 clock source configuration -------------------*/
735 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART11) == RCC_PERIPHCLK_USART11)
736 {
737 /* Check the parameters */
738 assert_param(IS_RCC_USART11CLKSOURCE(pPeriphClkInit->Usart11ClockSelection));
739
740 switch (pPeriphClkInit->Usart11ClockSelection)
741 {
742 case RCC_USART11CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for USART11*/
743
744 /* USART11 clock source config set later after clock selection check */
745 break;
746
747 case RCC_USART11CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for USART11*/
748 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
749 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
750 /* USART11 clock source config set later after clock selection check */
751 break;
752
753 case RCC_USART11CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for USART11*/
754 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
755 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
756 /* USART11 clock source config set later after clock selection check */
757 break;
758
759 case RCC_USART11CLKSOURCE_HSI: /* HSI clock is used as source of USART11 clock*/
760 /* USART11 clock source config set later after clock selection check */
761 break;
762
763 case RCC_USART11CLKSOURCE_CSI: /* CSI clock is used as source of USART11 clock*/
764 /* USART11 clock source config set later after clock selection check */
765 break;
766
767 case RCC_USART11CLKSOURCE_LSE: /* LSE clock is used as source of USART11 clock*/
768 /* USART11 clock source config set later after clock selection check */
769 break;
770
771 default:
772 ret = HAL_ERROR;
773 break;
774 }
775
776 if (ret == HAL_OK)
777 {
778 /* Set the source of USART11 clock*/
779 __HAL_RCC_USART11_CONFIG(pPeriphClkInit->Usart11ClockSelection);
780 }
781 else
782 {
783 /* set overall return value */
784 status = ret;
785 }
786 }
787 #endif /*USART11*/
788
789 #if defined(UART12)
790 /*-------------------------- UART12 clock source configuration -------------------*/
791 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART12) == RCC_PERIPHCLK_UART12)
792 {
793 /* Check the parameters */
794 assert_param(IS_RCC_UART12CLKSOURCE(pPeriphClkInit->Uart12ClockSelection));
795
796 switch (pPeriphClkInit->Uart12ClockSelection)
797 {
798 case RCC_UART12CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for UART12*/
799
800 /* UART12 clock source config set later after clock selection check */
801 break;
802
803 case RCC_UART12CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for UART12*/
804 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
805 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
806 /* UART12 clock source config set later after clock selection check */
807 break;
808
809 case RCC_UART12CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for UART12*/
810 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
811 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
812 /* UART12 clock source config set later after clock selection check */
813 break;
814
815 case RCC_UART12CLKSOURCE_HSI: /* HSI clock is used as source of UART12 clock*/
816 /* UART12 clock source config set later after clock selection check */
817 break;
818
819 case RCC_UART12CLKSOURCE_CSI: /* CSI clock is used as source of UART12 clock*/
820 /* UART12 clock source config set later after clock selection check */
821 break;
822
823 case RCC_UART12CLKSOURCE_LSE: /* LSE clock is used as source of UART12 clock*/
824 /* UART12 clock source config set later after clock selection check */
825 break;
826
827 default:
828 ret = HAL_ERROR;
829 break;
830 }
831
832 if (ret == HAL_OK)
833 {
834 /* Set the source of UART12 clock*/
835 __HAL_RCC_UART12_CONFIG(pPeriphClkInit->Uart12ClockSelection);
836 }
837 else
838 {
839 /* set overall return value */
840 status = ret;
841 }
842 }
843 #endif /* UART12 */
844
845 /*-------------------------- LPUART1 clock source configuration ------------------*/
846 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
847 {
848 /* Check the parameters */
849 assert_param(IS_RCC_LPUART1CLKSOURCE(pPeriphClkInit->Lpuart1ClockSelection));
850
851 switch (pPeriphClkInit->Lpuart1ClockSelection)
852 {
853 case RCC_LPUART1CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for LPUART1*/
854
855 /* LPUART1 clock source config set later after clock selection check */
856 break;
857
858 case RCC_LPUART1CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for LPUART1*/
859 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
860 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
861 /* LPUART1 clock source config set later after clock selection check */
862 break;
863
864 #if defined(RCC_LPUART1CLKSOURCE_PLL3Q)
865 case RCC_LPUART1CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for LPUART1*/
866 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
867 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
868 /* LPUART1 clock source config set later after clock selection check */
869 break;
870 #endif /* RCC_LPUART1CLKSOURCE_PLL3Q */
871
872 case RCC_LPUART1CLKSOURCE_HSI: /* HSI clock is used as source of LPUART1 clock*/
873 /* LPUART1 clock source config set later after clock selection check */
874 break;
875
876 case RCC_LPUART1CLKSOURCE_CSI: /* CSI clock is used as source of LPUART1 clock*/
877 /* LPUART1 clock source config set later after clock selection check */
878 break;
879
880 case RCC_LPUART1CLKSOURCE_LSE: /* LSE clock is used as source of LPUART1 clock*/
881 /* LPUART1 clock source config set later after clock selection check */
882 break;
883
884 default:
885 ret = HAL_ERROR;
886 break;
887 }
888
889 if (ret == HAL_OK)
890 {
891 /* Set the source of LPUART1 clock*/
892 __HAL_RCC_LPUART1_CONFIG(pPeriphClkInit->Lpuart1ClockSelection);
893 }
894 else
895 {
896 /* set overall return value */
897 status = ret;
898 }
899 }
900
901 /*-------------------------- I2C1 clock source configuration ---------------------*/
902 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
903 {
904 /* Check the parameters */
905 assert_param(IS_RCC_I2C1CLKSOURCE(pPeriphClkInit->I2c1ClockSelection));
906
907 switch (pPeriphClkInit->I2c1ClockSelection)
908 {
909 case RCC_I2C1CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for I2C1*/
910
911 /* I2C1 clock source config set later after clock selection check */
912 break;
913
914 #if defined(RCC_I2C1CLKSOURCE_PLL3R)
915 case RCC_I2C1CLKSOURCE_PLL3R: /* PLL3 is used as clock source for I2C1*/
916 /* PLL3 input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
917 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
918 #else
919 case RCC_I2C1CLKSOURCE_PLL2R: /* PLL2 is used as clock source for I2C1*/
920 /* PLL2 input clock, parameters M, N & R configuration clock output (PLL2ClockOut) */
921 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
922 #endif /* RCC_I2C1CLKSOURCE_PLL3R */
923 /* I2C1 clock source config set later after clock selection check */
924 break;
925
926
927 case RCC_I2C1CLKSOURCE_HSI: /* HSI clock is used as source of I2C1 clock*/
928 /* I2C1 clock source config set later after clock selection check */
929 break;
930
931 case RCC_I2C1CLKSOURCE_CSI: /* CSI clock is used as source of I2C1 clock*/
932 /* I2C1 clock source config set later after clock selection check */
933 break;
934
935 default:
936 ret = HAL_ERROR;
937 break;
938 }
939
940 if (ret == HAL_OK)
941 {
942 /* Set the source of I2C1 clock*/
943 __HAL_RCC_I2C1_CONFIG(pPeriphClkInit->I2c1ClockSelection);
944 }
945 else
946 {
947 /* set overall return value */
948 status = ret;
949 }
950 }
951
952 /*-------------------------- I2C2 clock source configuration ---------------------*/
953 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
954 {
955 /* Check the parameters */
956 assert_param(IS_RCC_I2C2CLKSOURCE(pPeriphClkInit->I2c2ClockSelection));
957
958 switch (pPeriphClkInit->I2c2ClockSelection)
959 {
960 case RCC_I2C2CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for I2C2*/
961
962 /* I2C2 clock source config set later after clock selection check */
963 break;
964
965 #if defined(RCC_I2C2CLKSOURCE_PLL3R)
966 case RCC_I2C2CLKSOURCE_PLL3R: /* PLL3 is used as clock source for I2C2*/
967 /* PLL3 input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
968 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
969 #else
970 case RCC_I2C2CLKSOURCE_PLL2R: /* PLL32 is used as clock source for I2C2*/
971 /* PLL2 input clock, parameters M, N & R configuration clock output (PLL2ClockOut) */
972 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
973 #endif /* RCC_I2C2CLKSOURCE_PLL3R */
974 /* I2C2 clock source config set later after clock selection check */
975 break;
976
977 case RCC_I2C2CLKSOURCE_HSI: /* HSI clock is used as source of I2C2 clock*/
978 /* I2C2 clock source config set later after clock selection check */
979 break;
980
981 case RCC_I2C2CLKSOURCE_CSI: /* CSI clock is used as source of I2C2 clock*/
982 /* I2C2 clock source config set later after clock selection check */
983 break;
984
985 default:
986 ret = HAL_ERROR;
987 break;
988 }
989
990 if (ret == HAL_OK)
991 {
992 /* Set the source of I2C2 clock*/
993 __HAL_RCC_I2C2_CONFIG(pPeriphClkInit->I2c2ClockSelection);
994 }
995 else
996 {
997 /* set overall return value */
998 status = ret;
999 }
1000 }
1001
1002 #if defined(I2C3)
1003 /*-------------------------- I2C3 clock source configuration ---------------------*/
1004 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
1005 {
1006 /* Check the parameters */
1007 assert_param(IS_RCC_I2C3CLKSOURCE(pPeriphClkInit->I2c3ClockSelection));
1008
1009 switch (pPeriphClkInit->I2c3ClockSelection)
1010 {
1011 case RCC_I2C3CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for I2C3*/
1012
1013 /* I2C3 clock source config set later after clock selection check */
1014 break;
1015
1016 case RCC_I2C3CLKSOURCE_PLL3R: /* PLL3 is used as clock source for I2C3*/
1017 /* PLL3 input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
1018 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1019 /* I2C3 clock source config set later after clock selection check */
1020 break;
1021
1022 case RCC_I2C3CLKSOURCE_HSI: /* HSI clock is used as source of I2C3 clock*/
1023 /* I2C3 clock source config set later after clock selection check */
1024 break;
1025
1026 case RCC_I2C3CLKSOURCE_CSI: /* CSI clock is used as source of I2C3 clock*/
1027 /* I2C3 clock source config set later after clock selection check */
1028 break;
1029
1030 default:
1031 ret = HAL_ERROR;
1032 break;
1033 }
1034
1035 if (ret == HAL_OK)
1036 {
1037 /* Set the source of I2C3 clock*/
1038 __HAL_RCC_I2C3_CONFIG(pPeriphClkInit->I2c3ClockSelection);
1039 }
1040 else
1041 {
1042 /* set overall return value */
1043 status = ret;
1044 }
1045 }
1046 #endif /* I2C3 */
1047
1048 #if defined(I2C4)
1049 /*-------------------------- I2C4 clock source configuration ---------------------*/
1050 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
1051 {
1052 /* Check the parameters */
1053 assert_param(IS_RCC_I2C4CLKSOURCE(pPeriphClkInit->I2c4ClockSelection));
1054
1055 switch (pPeriphClkInit->I2c4ClockSelection)
1056 {
1057 case RCC_I2C4CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for I2C4*/
1058
1059 /* I2C4 clock source config set later after clock selection check */
1060 break;
1061
1062 case RCC_I2C4CLKSOURCE_PLL3R: /* PLL3 is used as clock source for I2C4*/
1063 /* PLL3 input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
1064 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1065 /* I2C4 clock source config set later after clock selection check */
1066 break;
1067
1068 case RCC_I2C4CLKSOURCE_HSI: /* HSI clock is used as source of I2C4 clock*/
1069 /* I2C4 clock source config set later after clock selection check */
1070 break;
1071
1072 case RCC_I2C4CLKSOURCE_CSI: /* CSI clock is used as source of I2C4 clock*/
1073 /* I2C4 clock source config set later after clock selection check */
1074 break;
1075
1076 default:
1077 ret = HAL_ERROR;
1078 break;
1079 }
1080
1081 if (ret == HAL_OK)
1082 {
1083 /* Set the source of I2C4 clock*/
1084 __HAL_RCC_I2C4_CONFIG(pPeriphClkInit->I2c4ClockSelection);
1085 }
1086 else
1087 {
1088 /* set overall return value */
1089 status = ret;
1090 }
1091 }
1092 #endif /* I2C4 */
1093
1094 /*-------------------------- I3C1 clock source configuration ---------------------*/
1095 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I3C1) == RCC_PERIPHCLK_I3C1)
1096 {
1097 /* Check the parameters */
1098 assert_param(IS_RCC_I3C1CLKSOURCE(pPeriphClkInit->I3c1ClockSelection));
1099
1100 switch (pPeriphClkInit->I3c1ClockSelection)
1101 {
1102 case RCC_I3C1CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for I3C1*/
1103
1104 /* I3C1 clock source config set later after clock selection check */
1105 break;
1106
1107 #if defined(RCC_I3C1CLKSOURCE_PLL3R)
1108 case RCC_I3C1CLKSOURCE_PLL3R: /* PLL3 is used as clock source for I3C1*/
1109 /* PLL3 input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
1110 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1111 #else
1112 case RCC_I3C1CLKSOURCE_PLL2R: /* PLL2 is used as clock source for I3C1*/
1113 /* PLL2 input clock, parameters M, N & R configuration clock output (PLL2ClockOut) */
1114 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1115 #endif /* RCC_I3C1CLKSOURCE_PLL3R */
1116 /* I3C1 clock source config set later after clock selection check */
1117 break;
1118
1119 case RCC_I3C1CLKSOURCE_HSI: /* HSI clock is used as source of I3C1 clock*/
1120 /* I3C1 clock source config set later after clock selection check */
1121 break;
1122
1123 default:
1124 ret = HAL_ERROR;
1125 break;
1126 }
1127
1128 if (ret == HAL_OK)
1129 {
1130 /* Set the source of I3C1 clock*/
1131 __HAL_RCC_I3C1_CONFIG(pPeriphClkInit->I3c1ClockSelection);
1132 }
1133 else
1134 {
1135 /* set overall return value */
1136 status = ret;
1137 }
1138 }
1139
1140 #if defined (I3C2)
1141 /*-------------------------- I3C2 clock source configuration ---------------------*/
1142 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I3C2) == RCC_PERIPHCLK_I3C2)
1143 {
1144 /* Check the parameters */
1145 assert_param(IS_RCC_I3C2CLKSOURCE(pPeriphClkInit->I3c2ClockSelection));
1146
1147 switch (pPeriphClkInit->I3c2ClockSelection)
1148 {
1149 case RCC_I3C2CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for I3C2*/
1150
1151 /* I3C2 clock source config set later after clock selection check */
1152 break;
1153
1154 #if defined(RCC_I3C2CLKSOURCE_PLL3R)
1155 case RCC_I3C2CLKSOURCE_PLL3R: /* PLL3 is used as clock source for I3C2*/
1156 /* PLL3 input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
1157 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1158 #else
1159 case RCC_I3C2CLKSOURCE_PLL2R: /* PLL2 is used as clock source for I3C2*/
1160 /* PLL2 input clock, parameters M, N & R configuration clock output (PLL2ClockOut) */
1161 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1162 #endif /* RCC_I3C2CLKSOURCE_PLL3R */
1163 /* I3C2 clock source config set later after clock selection check */
1164 break;
1165
1166 case RCC_I3C2CLKSOURCE_HSI: /* HSI clock is used as source of I3C2 clock*/
1167 /* I3C2 clock source config set later after clock selection check */
1168 break;
1169
1170 default:
1171 ret = HAL_ERROR;
1172 break;
1173 }
1174 if (ret == HAL_OK)
1175 {
1176 /* Set the source of I3C2 clock*/
1177 __HAL_RCC_I3C2_CONFIG(pPeriphClkInit->I3c2ClockSelection);
1178 }
1179 else
1180 {
1181 /* set overall return value */
1182 status = ret;
1183 }
1184 }
1185 #endif /* I3C2 */
1186
1187 /*------------------------------------ TIM configuration --------------------------------------*/
1188 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM)
1189 {
1190 /* Check the parameters */
1191 assert_param(IS_RCC_TIMPRES(pPeriphClkInit->TimPresSelection));
1192
1193 /* Configure Timer Prescaler */
1194 __HAL_RCC_TIMCLKPRESCALER(pPeriphClkInit->TimPresSelection);
1195 }
1196
1197 /*-------------------------- LPTIM1 clock source configuration ---------------------*/
1198 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
1199 {
1200 /* Check the parameters */
1201 assert_param(IS_RCC_LPTIM1CLK(pPeriphClkInit->Lptim1ClockSelection));
1202
1203 switch (pPeriphClkInit->Lptim1ClockSelection)
1204 {
1205 case RCC_LPTIM1CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for LPTIM1*/
1206
1207 /* LPTIM1 clock source config set later after clock selection check */
1208 break;
1209
1210 case RCC_LPTIM1CLKSOURCE_PLL2P: /* PLL2 is used as clock source for LPTIM1*/
1211 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1212 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1213 /* LPTIM1 clock source config set later after clock selection check */
1214 break;
1215
1216 #if defined(RCC_LPTIM1CLKSOURCE_PLL3R)
1217 case RCC_LPTIM1CLKSOURCE_PLL3R: /* PLL3 is used as clock source for LPTIM1*/
1218 /* PLL3 R input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
1219 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1220 /* LPTIM1 clock source config set later after clock selection check */
1221 break;
1222 #endif /* RCC_LPTIM1CLKSOURCE_PLL3R */
1223
1224 case RCC_LPTIM1CLKSOURCE_LSE: /* LSE clock is used as source of LPTIM1 clock*/
1225 /* LPTIM1 clock source config set later after clock selection check */
1226 break;
1227
1228 case RCC_LPTIM1CLKSOURCE_LSI: /* LSI clock is used as source of LPTIM1 clock*/
1229 /* LPTIM1 clock source config set later after clock selection check */
1230 break;
1231
1232 case RCC_LPTIM1CLKSOURCE_CLKP: /* CLKP is used as source of LPTIM1 clock*/
1233 /* LPTIM1 clock source config set later after clock selection check */
1234 break;
1235
1236 default:
1237 ret = HAL_ERROR;
1238 break;
1239 }
1240
1241 if (ret == HAL_OK)
1242 {
1243 /* Set the source of LPTIM1 clock*/
1244 __HAL_RCC_LPTIM1_CONFIG(pPeriphClkInit->Lptim1ClockSelection);
1245 }
1246 else
1247 {
1248 /* set overall return value */
1249 status = ret;
1250 }
1251 }
1252
1253 /*-------------------------- LPTIM2 clock source configuration ---------------------*/
1254 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)
1255 {
1256 /* Check the parameters */
1257 assert_param(IS_RCC_LPTIM2CLK(pPeriphClkInit->Lptim2ClockSelection));
1258
1259 switch (pPeriphClkInit->Lptim2ClockSelection)
1260 {
1261 case RCC_LPTIM2CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for LPTIM2*/
1262
1263 /* LPTIM2 clock source config set later after clock selection check */
1264 break;
1265
1266 case RCC_LPTIM2CLKSOURCE_PLL2P: /* PLL2 is used as clock source for LPTIM2*/
1267 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1268 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1269 /* LPTIM2 clock source config set later after clock selection check */
1270 break;
1271
1272 #if defined(RCC_LPTIM2CLKSOURCE_PLL3R)
1273 case RCC_LPTIM2CLKSOURCE_PLL3R: /* PLL3 is used as clock source for LPTIM2*/
1274 /* PLL3 R input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
1275 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1276 /* LPTIM2 clock source config set later after clock selection check */
1277 break;
1278 #endif /* RCC_LPTIM2CLKSOURCE_PLL3R */
1279
1280 case RCC_LPTIM2CLKSOURCE_LSE: /* LSE clock is used as source of LPTIM2 clock*/
1281 /* LPTIM2 clock source config set later after clock selection check */
1282 break;
1283
1284 case RCC_LPTIM2CLKSOURCE_LSI: /* LSI clock is used as source of LPTIM2 clock*/
1285 /* LPTIM2 clock source config set later after clock selection check */
1286 break;
1287
1288 case RCC_LPTIM2CLKSOURCE_CLKP: /* CLKP is used as source of LPTIM2 clock*/
1289 /* LPTIM2 clock source config set later after clock selection check */
1290 break;
1291
1292 default:
1293 ret = HAL_ERROR;
1294 break;
1295 }
1296
1297 if (ret == HAL_OK)
1298 {
1299 /* Set the source of LPTIM2 clock*/
1300 __HAL_RCC_LPTIM2_CONFIG(pPeriphClkInit->Lptim2ClockSelection);
1301 }
1302 else
1303 {
1304 /* set overall return value */
1305 status = ret;
1306 }
1307 }
1308
1309 #if defined(LPTIM3)
1310 /*-------------------------- LPTIM3 clock source configuration ---------------------*/
1311 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM3) == RCC_PERIPHCLK_LPTIM3)
1312 {
1313 /* Check the parameters */
1314 assert_param(IS_RCC_LPTIM3CLK(pPeriphClkInit->Lptim3ClockSelection));
1315
1316 switch (pPeriphClkInit->Lptim3ClockSelection)
1317 {
1318 case RCC_LPTIM3CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for LPTIM3*/
1319
1320 /* LPTIM3 clock source config set later after clock selection check */
1321 break;
1322
1323 case RCC_LPTIM3CLKSOURCE_PLL2P: /* PLL2 is used as clock source for LPTIM3*/
1324 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1325 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1326 /* LPTIM3 clock source config set later after clock selection check */
1327 break;
1328
1329 case RCC_LPTIM3CLKSOURCE_PLL3R: /* PLL3 is used as clock source for LPTIM3*/
1330 /* PLL3 R input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
1331 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1332 /* LPTIM3 clock source config set later after clock selection check */
1333 break;
1334
1335 case RCC_LPTIM3CLKSOURCE_LSE: /* LSE clock is used as source of LPTIM3 clock*/
1336 /* LPTIM3 clock source config set later after clock selection check */
1337 break;
1338
1339 case RCC_LPTIM3CLKSOURCE_LSI: /* LSI clock is used as source of LPTIM3 clock*/
1340 /* LPTIM3 clock source config set later after clock selection check */
1341 break;
1342
1343 case RCC_LPTIM3CLKSOURCE_CLKP: /* CLKP is used as source of LPTIM3 clock*/
1344 /* LPTIM3 clock source config set later after clock selection check */
1345 break;
1346
1347 default:
1348 ret = HAL_ERROR;
1349 break;
1350 }
1351
1352 if (ret == HAL_OK)
1353 {
1354 /* Set the source of LPTIM3 clock*/
1355 __HAL_RCC_LPTIM3_CONFIG(pPeriphClkInit->Lptim3ClockSelection);
1356 }
1357 else
1358 {
1359 /* set overall return value */
1360 status = ret;
1361 }
1362 }
1363 #endif /* LPTIM3 */
1364
1365 #if defined(LPTIM4)
1366 /*-------------------------- LPTIM4 clock source configuration ---------------------*/
1367 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM4) == RCC_PERIPHCLK_LPTIM4)
1368 {
1369 /* Check the parameters */
1370 assert_param(IS_RCC_LPTIM4CLK(pPeriphClkInit->Lptim4ClockSelection));
1371
1372 switch (pPeriphClkInit->Lptim4ClockSelection)
1373 {
1374 case RCC_LPTIM4CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for LPTIM4*/
1375
1376 /* LPTIM4 clock source config set later after clock selection check */
1377 break;
1378
1379 case RCC_LPTIM4CLKSOURCE_PLL2P: /* PLL2 is used as clock source for LPTIM4*/
1380 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1381 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1382 /* LPTIM4 clock source config set later after clock selection check */
1383 break;
1384
1385 case RCC_LPTIM4CLKSOURCE_PLL3R: /* PLL3 is used as clock source for LPTIM4*/
1386 /* PLL3 R input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
1387 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1388 /* LPTIM4 clock source config set later after clock selection check */
1389 break;
1390
1391 case RCC_LPTIM4CLKSOURCE_LSE: /* LSE clock is used as source of LPTIM4 clock*/
1392 /* LPTIM4 clock source config set later after clock selection check */
1393 break;
1394
1395 case RCC_LPTIM4CLKSOURCE_LSI: /* LSI clock is used as source of LPTIM4 clock*/
1396 /* LPTIM4 clock source config set later after clock selection check */
1397 break;
1398
1399 case RCC_LPTIM4CLKSOURCE_CLKP: /* CLKP is used as source of LPTIM4 clock*/
1400 /* LPTIM4 clock source config set later after clock selection check */
1401 break;
1402
1403 default:
1404 ret = HAL_ERROR;
1405 break;
1406 }
1407
1408 if (ret == HAL_OK)
1409 {
1410 /* Set the source of LPTIM4 clock*/
1411 __HAL_RCC_LPTIM4_CONFIG(pPeriphClkInit->Lptim4ClockSelection);
1412 }
1413 else
1414 {
1415 /* set overall return value */
1416 status = ret;
1417 }
1418 }
1419 #endif /* LPTIM4 */
1420
1421 #if defined(LPTIM5)
1422 /*-------------------------- LPTIM5 clock source configuration ---------------------*/
1423 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM5) == RCC_PERIPHCLK_LPTIM5)
1424 {
1425 /* Check the parameters */
1426 assert_param(IS_RCC_LPTIM5CLK(pPeriphClkInit->Lptim5ClockSelection));
1427
1428 switch (pPeriphClkInit->Lptim5ClockSelection)
1429 {
1430 case RCC_LPTIM5CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for LPTIM5*/
1431
1432 /* LPTIM5 clock source config set later after clock selection check */
1433 break;
1434
1435 case RCC_LPTIM5CLKSOURCE_PLL2P: /* PLL2 is used as clock source for LPTIM5*/
1436 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1437 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1438 /* LPTIM5 clock source config set later after clock selection check */
1439 break;
1440
1441 case RCC_LPTIM5CLKSOURCE_PLL3R: /* PLL3 is used as clock source for LPTIM5*/
1442 /* PLL3 R input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
1443 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1444 /* LPTIM5 clock source config set later after clock selection check */
1445 break;
1446
1447 case RCC_LPTIM5CLKSOURCE_LSE: /* LSE clock is used as source of LPTIM5 clock*/
1448 /* LPTIM5 clock source config set later after clock selection check */
1449 break;
1450
1451 case RCC_LPTIM5CLKSOURCE_LSI: /* LSI clock is used as source of LPTIM5 clock*/
1452 /* LPTIM5 clock source config set later after clock selection check */
1453 break;
1454
1455 case RCC_LPTIM5CLKSOURCE_CLKP: /* CLKP is used as source of LPTIM5 clock*/
1456 /* LPTIM5 clock source config set later after clock selection check */
1457 break;
1458
1459 default:
1460 ret = HAL_ERROR;
1461 break;
1462 }
1463
1464 if (ret == HAL_OK)
1465 {
1466 /* Set the source of LPTIM5 clock*/
1467 __HAL_RCC_LPTIM5_CONFIG(pPeriphClkInit->Lptim5ClockSelection);
1468 }
1469 else
1470 {
1471 /* set overall return value */
1472 status = ret;
1473 }
1474 }
1475 #endif /* LPTIM5 */
1476
1477 #if defined(LPTIM6)
1478 /*-------------------------- LPTIM6 clock source configuration ---------------------*/
1479 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM6) == RCC_PERIPHCLK_LPTIM6)
1480 {
1481 /* Check the parameters */
1482 assert_param(IS_RCC_LPTIM6CLK(pPeriphClkInit->Lptim6ClockSelection));
1483
1484 switch (pPeriphClkInit->Lptim6ClockSelection)
1485 {
1486 case RCC_LPTIM6CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for LPTIM6*/
1487
1488 /* LPTIM6 clock source config set later after clock selection check */
1489 break;
1490
1491 case RCC_LPTIM6CLKSOURCE_PLL2P: /* PLL2 is used as clock source for LPTIM6*/
1492 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1493 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1494 /* LPTIM6 clock source config set later after clock selection check */
1495 break;
1496
1497 case RCC_LPTIM6CLKSOURCE_PLL3R: /* PLL3 is used as clock source for LPTIM6*/
1498 /* PLL3 R input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
1499 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1500 /* LPTIM6 clock source config set later after clock selection check */
1501 break;
1502
1503 case RCC_LPTIM6CLKSOURCE_LSE: /* LSE clock is used as source of LPTIM6 clock*/
1504 /* LPTIM6 clock source config set later after clock selection check */
1505 break;
1506
1507 case RCC_LPTIM6CLKSOURCE_LSI: /* LSI clock is used as source of LPTIM6 clock*/
1508 /* LPTIM6 clock source config set later after clock selection check */
1509 break;
1510
1511 case RCC_LPTIM6CLKSOURCE_CLKP: /* CLKP is used as source of LPTIM6 clock*/
1512 /* LPTIM6 clock source config set later after clock selection check */
1513 break;
1514
1515 default:
1516 ret = HAL_ERROR;
1517 break;
1518 }
1519
1520 if (ret == HAL_OK)
1521 {
1522 /* Set the source of LPTIM6 clock*/
1523 __HAL_RCC_LPTIM6_CONFIG(pPeriphClkInit->Lptim6ClockSelection);
1524 }
1525 else
1526 {
1527 /* set overall return value */
1528 status = ret;
1529 }
1530 }
1531 #endif /* LPTIM6 */
1532
1533 #if defined(SAI1)
1534 /*-------------------------- SAI1 clock source configuration ---------------------*/
1535 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
1536 {
1537 /* Check the parameters */
1538 assert_param(IS_RCC_SAI1CLK(pPeriphClkInit->Sai1ClockSelection));
1539
1540 switch (pPeriphClkInit->Sai1ClockSelection)
1541 {
1542 case RCC_SAI1CLKSOURCE_PLL1Q: /* PLL is used as clock source for SAI1*/
1543 /* Enable SAI Clock output generated from System PLL . */
1544 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
1545 /* SAI1 clock source config set later after clock selection check */
1546 break;
1547
1548 case RCC_SAI1CLKSOURCE_PLL2P: /* PLL2 is used as clock source for SAI1*/
1549 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1550 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1551 /* SAI1 clock source config set later after clock selection check */
1552 break;
1553
1554 case RCC_SAI1CLKSOURCE_PLL3P: /* PLL3 is used as clock source for SAI1*/
1555 /* PLL3 P input clock, parameters M, N & P configuration clock output (PLL3ClockOut) */
1556 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1557 /* SAI1 clock source config set later after clock selection check */
1558 break;
1559
1560 case RCC_SAI1CLKSOURCE_PIN: /* External clock is used as source of SAI1 clock*/
1561 break;
1562
1563 case RCC_SAI1CLKSOURCE_CLKP: /* CLKP is used as source of SAI1 clock*/
1564 /* SAI1 clock source config set later after clock selection check */
1565 break;
1566
1567 default:
1568 ret = HAL_ERROR;
1569 break;
1570 }
1571
1572 if (ret == HAL_OK)
1573 {
1574 /* Set the source of SAI1 clock*/
1575 __HAL_RCC_SAI1_CONFIG(pPeriphClkInit->Sai1ClockSelection);
1576 }
1577 else
1578 {
1579 /* set overall return value */
1580 status = ret;
1581 }
1582 }
1583 #endif /* SAI1*/
1584
1585 #if defined(SAI2)
1586 /*-------------------------- SAI2 clock source configuration ---------------------*/
1587 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2)
1588 {
1589 /* Check the parameters */
1590 assert_param(IS_RCC_SAI2CLK(pPeriphClkInit->Sai2ClockSelection));
1591
1592 switch (pPeriphClkInit->Sai2ClockSelection)
1593 {
1594 case RCC_SAI2CLKSOURCE_PLL1Q: /* PLL is used as clock source for SAI2*/
1595 /* Enable SAI Clock output generated from System PLL . */
1596 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
1597 /* SAI2 clock source config set later after clock selection check */
1598 break;
1599
1600 case RCC_SAI2CLKSOURCE_PLL2P: /* PLL2 is used as clock source for SAI2*/
1601 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1602 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1603 /* SAI2 clock source config set later after clock selection check */
1604 break;
1605
1606 case RCC_SAI2CLKSOURCE_PLL3P: /* PLL3 is used as clock source for SAI2*/
1607 /* PLL3 P input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
1608 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1609 /* SAI2 clock source config set later after clock selection check */
1610 break;
1611
1612 case RCC_SAI2CLKSOURCE_PIN: /* External clock is used as source of SAI2 clock*/
1613 case RCC_SAI2CLKSOURCE_CLKP: /* CLKP is used as source of SAI2 clock*/
1614 /* SAI2 clock source config set later after clock selection check */
1615 break;
1616
1617 default:
1618 ret = HAL_ERROR;
1619 break;
1620 }
1621
1622 if (ret == HAL_OK)
1623 {
1624 /* Set the source of SAI2 clock*/
1625 __HAL_RCC_SAI2_CONFIG(pPeriphClkInit->Sai2ClockSelection);
1626 }
1627 else
1628 {
1629 /* set overall return value */
1630 status = ret;
1631 }
1632 }
1633 #endif /* SAI2*/
1634
1635 /*-------------------------- ADCDAC clock source configuration ----------------------*/
1636 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADCDAC) == RCC_PERIPHCLK_ADCDAC)
1637 {
1638 /* Check the parameters */
1639 assert_param(IS_RCC_ADCDACCLKSOURCE(pPeriphClkInit->AdcDacClockSelection));
1640
1641 switch (pPeriphClkInit->AdcDacClockSelection)
1642 {
1643
1644 case RCC_ADCDACCLKSOURCE_HCLK: /* Bus clock is used as source of ADCDAC clock*/
1645 case RCC_ADCDACCLKSOURCE_SYSCLK: /* System clock is used as source of ADCDAC clock*/
1646 /* ADCDAC clock source config set later after clock selection check */
1647 break;
1648
1649 case RCC_ADCDACCLKSOURCE_PLL2R:
1650 /* PLL2 input clock, parameters M, N & R configuration and clock output (PLL2ClockOut) */
1651 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1652 break;
1653
1654 case RCC_ADCDACCLKSOURCE_HSE:/* HSE clock is used as source of ADCDAC clock*/
1655 case RCC_ADCDACCLKSOURCE_HSI:/* HSI clock is used as source of ADCDAC clock*/
1656 case RCC_ADCDACCLKSOURCE_CSI:/* CSI clock is used as source of ADCDAC clock*/
1657 /* ADCDAC clock source configuration done later after clock selection check */
1658 break;
1659
1660
1661 default:
1662 ret = HAL_ERROR;
1663 break;
1664 }
1665
1666 if (ret == HAL_OK)
1667 {
1668 /* Configure the ADCDAC interface clock source */
1669 __HAL_RCC_ADCDAC_CONFIG(pPeriphClkInit->AdcDacClockSelection);
1670 }
1671 else
1672 {
1673 /* set overall return value */
1674 status = ret;
1675 }
1676
1677 }
1678
1679 /*-------------------------- DAC low-power clock source configuration ----------------------*/
1680 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DAC_LP) == RCC_PERIPHCLK_DAC_LP)
1681 {
1682 /* Check the parameters */
1683 assert_param(IS_RCC_DACLPCLKSOURCE(pPeriphClkInit->DacLowPowerClockSelection));
1684
1685 switch (pPeriphClkInit->DacLowPowerClockSelection)
1686 {
1687
1688 case RCC_DACLPCLKSOURCE_LSE:
1689 /* LSE oscillator is used as source of DAC low-power clock */
1690 /* DAC clock source configuration done later after clock selection check */
1691 break;
1692
1693 case RCC_DACLPCLKSOURCE_LSI:
1694 /* LSI is used as clock source for DAC low-power clock */
1695 /* DAC clock source configuration done later after clock selection check */
1696 break;
1697
1698 default:
1699 ret = HAL_ERROR;
1700 break;
1701 }
1702
1703 if (ret == HAL_OK)
1704 {
1705 /* Configure the DAC low-power interface clock source */
1706 __HAL_RCC_DAC_LP_CONFIG(pPeriphClkInit->DacLowPowerClockSelection);
1707 }
1708 else
1709 {
1710 /* set overall return value */
1711 status = ret;
1712 }
1713
1714 }
1715
1716 /*-------------------------- RTC clock source configuration ----------------------*/
1717 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
1718 {
1719
1720 /* Check for RTC Parameters used to output RTCCLK */
1721 assert_param(IS_RCC_RTCCLKSOURCE(pPeriphClkInit->RTCClockSelection));
1722
1723 /* Enable write access to Backup domain */
1724 SET_BIT(PWR->DBPCR, PWR_DBPCR_DBP);
1725
1726 /* Wait for Backup domain Write protection disable */
1727 tickstart = HAL_GetTick();
1728
1729 while (HAL_IS_BIT_CLR(PWR->DBPCR, PWR_DBPCR_DBP))
1730 {
1731 if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
1732 {
1733 ret = HAL_TIMEOUT;
1734 break;
1735 }
1736 }
1737
1738 if (ret == HAL_OK)
1739 {
1740 /* Reset the Backup domain only if the RTC Clock source selection is modified from default */
1741 tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
1742
1743 if ((tmpregister != RCC_RTCCLKSOURCE_NO_CLK) && (tmpregister != pPeriphClkInit->RTCClockSelection))
1744 {
1745 /* Store the content of BDCR register before the reset of Backup Domain */
1746 tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
1747 /* RTC Clock selection can be changed only if the Backup Domain is reset */
1748 __HAL_RCC_BACKUPRESET_FORCE();
1749 __HAL_RCC_BACKUPRESET_RELEASE();
1750 /* Restore the Content of BDCR register */
1751 RCC->BDCR = tmpregister;
1752 }
1753
1754 /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
1755 if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
1756 {
1757 /* Get Start Tick*/
1758 tickstart = HAL_GetTick();
1759
1760 /* Wait till LSE is ready */
1761 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
1762 {
1763 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
1764 {
1765 ret = HAL_TIMEOUT;
1766 break;
1767 }
1768 }
1769 }
1770
1771 if (ret == HAL_OK)
1772 {
1773 /* Apply new RTC clock source selection */
1774 __HAL_RCC_RTC_CONFIG(pPeriphClkInit->RTCClockSelection);
1775 }
1776 else
1777 {
1778 /* set overall return value */
1779 status = ret;
1780 }
1781 }
1782 else
1783 {
1784 /* set overall return value */
1785 status = ret;
1786 }
1787
1788 }
1789
1790 /*------------------------------ RNG Configuration -------------------------*/
1791 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
1792 {
1793
1794 /* Check the parameters */
1795 assert_param(IS_RCC_RNGCLKSOURCE(pPeriphClkInit->RngClockSelection));
1796
1797 switch (pPeriphClkInit->RngClockSelection)
1798 {
1799
1800 case RCC_RNGCLKSOURCE_HSI48: /* HSI48 is used as clock source for RNG*/
1801
1802 /* RNG clock source configuration done later after clock selection check */
1803 break;
1804
1805 case RCC_RNGCLKSOURCE_PLL1Q: /* PLL1 is used as clock source for RNG*/
1806 /* Enable PLL1Q Clock output generated from System PLL . */
1807 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
1808 /* RNG clock source configuration done later after clock selection check */
1809 break;
1810 case RCC_RNGCLKSOURCE_LSE:
1811 /* LSE oscillator is used as source of RNG clock */
1812 /* RNG clock source configuration done later after clock selection check */
1813 break;
1814
1815 case RCC_RNGCLKSOURCE_LSI: /* HSI48 is used as clock source for RNG*/
1816
1817 /* RNG clock source configuration done later after clock selection check */
1818 break;
1819
1820 default:
1821 ret = HAL_ERROR;
1822 break;
1823 }
1824
1825 if (ret == HAL_OK)
1826 {
1827 /* Set the source of RNG clock*/
1828 __HAL_RCC_RNG_CONFIG(pPeriphClkInit->RngClockSelection);
1829 }
1830 else
1831 {
1832 /* set overall return value */
1833 status = ret;
1834 }
1835
1836 }
1837
1838 #if defined(SDMMC1)
1839 /*-------------------------- SDMMC1 clock source configuration -------------------*/
1840 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
1841 {
1842
1843 /* Check the parameters */
1844 assert_param(IS_RCC_SDMMC1CLKSOURCE(pPeriphClkInit->Sdmmc1ClockSelection));
1845
1846 switch (pPeriphClkInit->Sdmmc1ClockSelection)
1847 {
1848 case RCC_SDMMC1CLKSOURCE_PLL1Q: /* PLL1 is used as clock source for SDMMC1 kernel clock*/
1849 /* Enable PLL1Q Clock output generated from System PLL . */
1850 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
1851 /* SDMMC1 kernel clock source config set later after clock selection check */
1852 break;
1853
1854 case RCC_SDMMC1CLKSOURCE_PLL2R: /* PLL2 is used as clock source for SDMMC1 kernel clock*/
1855 /* PLL2R input clock, parameters M, N & R configuration and clock output (PLL2ClockOut) */
1856 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1857 /* SDMMC1 kernel clock source config set later after clock selection check */
1858 break;
1859
1860 default:
1861 ret = HAL_ERROR;
1862 break;
1863 }
1864
1865 if (ret == HAL_OK)
1866 {
1867 /* Configure the SDMMC1 clock source */
1868 __HAL_RCC_SDMMC1_CONFIG(pPeriphClkInit->Sdmmc1ClockSelection);
1869 }
1870 else
1871 {
1872 /* set overall return value */
1873 status = ret;
1874 }
1875
1876 }
1877 #endif /* SDMMC1 */
1878
1879 #if defined(SDMMC2)
1880 /*-------------------------- SDMMC2 clock source configuration -------------------*/
1881 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
1882 {
1883
1884 /* Check the parameters */
1885 assert_param(IS_RCC_SDMMC2CLKSOURCE(pPeriphClkInit->Sdmmc2ClockSelection));
1886
1887 switch (pPeriphClkInit->Sdmmc2ClockSelection)
1888 {
1889 case RCC_SDMMC2CLKSOURCE_PLL1Q: /* PLL1 is used as clock source for SDMMC2 kernel clock*/
1890 /* Enable PLL1Q Clock output generated from System PLL . */
1891 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
1892 /* SDMMC2 kernel clock source config set later after clock selection check */
1893 break;
1894
1895 case RCC_SDMMC2CLKSOURCE_PLL2R: /* PLL2 is used as clock source for SDMMC2 kernel clock*/
1896 /* PLL2R input clock, parameters M, N & R configuration and clock output (PLL2ClockOut) */
1897 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1898 /* SDMMC2 kernel clock source config set later after clock selection check */
1899 break;
1900
1901 default:
1902 ret = HAL_ERROR;
1903 break;
1904 }
1905
1906 if (ret == HAL_OK)
1907 {
1908 /* Configure the SDMMC2 clock source */
1909 __HAL_RCC_SDMMC2_CONFIG(pPeriphClkInit->Sdmmc2ClockSelection);
1910 }
1911 else
1912 {
1913 /* set overall return value */
1914 status = ret;
1915 }
1916
1917 }
1918 #endif /* SDMMC2 */
1919
1920 /*-------------------------- SPI1 clock source configuration ----------------*/
1921 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI1) == RCC_PERIPHCLK_SPI1)
1922 {
1923
1924 /* Check the parameters */
1925 assert_param(IS_RCC_SPI1CLKSOURCE(pPeriphClkInit->Spi1ClockSelection));
1926
1927 switch (pPeriphClkInit->Spi1ClockSelection)
1928 {
1929 case RCC_SPI1CLKSOURCE_PLL1Q: /* PLL1 is used as clock source for SPI1 */
1930 /* Enable SPI Clock output generated from System PLL . */
1931 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
1932
1933 /* SPI1 clock source configuration done later after clock selection check */
1934 break;
1935
1936 case RCC_SPI1CLKSOURCE_PLL2P: /* PLL2 is used as clock source for SPI1*/
1937 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1938 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1939
1940 /* SPI1 clock source configuration done later after clock selection check */
1941 break;
1942
1943 #if defined(RCC_SPI1CLKSOURCE_PLL3P)
1944 case RCC_SPI1CLKSOURCE_PLL3P: /* PLL3 is used as clock source for SPI1 */
1945 /* PLL3 P input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
1946 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1947
1948 /* SPI1 clock source configuration done later after clock selection check */
1949 break;
1950 #endif /* RCC_SPI1CLKSOURCE_PLL3P */
1951
1952 case RCC_SPI1CLKSOURCE_PIN:
1953 /* External clock is used as source of SPI1 clock*/
1954 /* SPI1 clock source configuration done later after clock selection check */
1955 break;
1956
1957 case RCC_SPI1CLKSOURCE_CLKP:
1958 /* HSI, HSE, or CSI oscillator is used as source of SPI1 clock */
1959 /* SPI1 clock source configuration done later after clock selection check */
1960 break;
1961
1962 default:
1963 ret = HAL_ERROR;
1964 break;
1965 }
1966
1967 if (ret == HAL_OK)
1968 {
1969 /* Configure the SPI1 clock source */
1970 __HAL_RCC_SPI1_CONFIG(pPeriphClkInit->Spi1ClockSelection);
1971 }
1972 else
1973 {
1974 /* set overall return value */
1975 status = ret;
1976 }
1977
1978 }
1979
1980 /*-------------------------- SPI2 clock source configuration ----------------*/
1981 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI2) == RCC_PERIPHCLK_SPI2)
1982 {
1983
1984 /* Check the parameters */
1985 assert_param(IS_RCC_SPI2CLKSOURCE(pPeriphClkInit->Spi2ClockSelection));
1986
1987 switch (pPeriphClkInit->Spi2ClockSelection)
1988 {
1989 case RCC_SPI2CLKSOURCE_PLL1Q: /* PLL1 is used as clock source for SPI2 */
1990 /* Enable SPI Clock output generated from System PLL . */
1991 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
1992
1993 /* SPI2 clock source configuration done later after clock selection check */
1994 break;
1995
1996 case RCC_SPI2CLKSOURCE_PLL2P: /* PLL2 is used as clock source for SPI2*/
1997 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1998 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1999
2000 /* SPI2 clock source configuration done later after clock selection check */
2001 break;
2002
2003 #if defined(RCC_SPI2CLKSOURCE_PLL3P)
2004 case RCC_SPI2CLKSOURCE_PLL3P: /* PLL3 is used as clock source for SPI2 */
2005 /* PLL3 P input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
2006 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
2007
2008 /* SPI2 clock source configuration done later after clock selection check */
2009 break;
2010 #endif /* RCC_SPI2CLKSOURCE_PLL3P */
2011
2012 case RCC_SPI2CLKSOURCE_PIN:
2013 /* External clock is used as source of SPI2 clock*/
2014 /* SPI2 clock source configuration done later after clock selection check */
2015 break;
2016
2017 case RCC_SPI2CLKSOURCE_CLKP:
2018 /* HSI, HSE, or CSI oscillator is used as source of SPI2 clock */
2019 /* SPI2 clock source configuration done later after clock selection check */
2020 break;
2021
2022 default:
2023 ret = HAL_ERROR;
2024 break;
2025 }
2026
2027 if (ret == HAL_OK)
2028 {
2029 /* Configure the SPI2 clock source */
2030 __HAL_RCC_SPI2_CONFIG(pPeriphClkInit->Spi2ClockSelection);
2031 }
2032 else
2033 {
2034 /* set overall return value */
2035 status = ret;
2036 }
2037
2038 }
2039
2040 /*-------------------------- SPI3 clock source configuration ----------------*/
2041 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI3) == RCC_PERIPHCLK_SPI3)
2042 {
2043
2044 /* Check the parameters */
2045 assert_param(IS_RCC_SPI3CLKSOURCE(pPeriphClkInit->Spi3ClockSelection));
2046
2047 switch (pPeriphClkInit->Spi3ClockSelection)
2048 {
2049 case RCC_SPI3CLKSOURCE_PLL1Q: /* PLL1 is used as clock source for SPI3 */
2050 /* Enable SPI Clock output generated from System PLL . */
2051 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
2052
2053 /* SPI3 clock source configuration done later after clock selection check */
2054 break;
2055
2056 case RCC_SPI3CLKSOURCE_PLL2P: /* PLL2 is used as clock source for SPI3*/
2057 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
2058 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
2059
2060 /* SPI3 clock source configuration done later after clock selection check */
2061 break;
2062
2063 #if defined(RCC_SPI3CLKSOURCE_PLL3P)
2064 case RCC_SPI3CLKSOURCE_PLL3P: /* PLL3 is used as clock source for SPI3 */
2065 /* PLL3 P input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
2066 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
2067
2068 /* SPI3 clock source configuration done later after clock selection check */
2069 break;
2070 #endif /* RCC_SPI3CLKSOURCE_PLL3P */
2071
2072 case RCC_SPI3CLKSOURCE_PIN:
2073 /* External clock is used as source of SPI3 clock*/
2074 /* SPI3 clock source configuration done later after clock selection check */
2075 break;
2076
2077 case RCC_SPI3CLKSOURCE_CLKP:
2078 /* HSI, HSE, or CSI oscillator is used as source of SPI3 clock */
2079 /* SPI3 clock source configuration done later after clock selection check */
2080 break;
2081
2082 default:
2083 ret = HAL_ERROR;
2084 break;
2085 }
2086
2087 if (ret == HAL_OK)
2088 {
2089 /* Configure the SPI3 clock source */
2090 __HAL_RCC_SPI3_CONFIG(pPeriphClkInit->Spi3ClockSelection);
2091 }
2092 else
2093 {
2094 /* set overall return value */
2095 status = ret;
2096 }
2097
2098 }
2099
2100 #if defined(SPI4)
2101 /*-------------------------- SPI4 clock source configuration ----------------*/
2102 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI4) == RCC_PERIPHCLK_SPI4)
2103 {
2104
2105 /* Check the parameters */
2106 assert_param(IS_RCC_SPI4CLKSOURCE(pPeriphClkInit->Spi4ClockSelection));
2107
2108 switch (pPeriphClkInit->Spi4ClockSelection)
2109 {
2110 case RCC_SPI4CLKSOURCE_PCLK2: /* PCLK2 (APB2 Clock) is used as clock source for SPI4 */
2111 /* SPI4 clock source configuration done later after clock selection check */
2112 break;
2113
2114 case RCC_SPI4CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for SPI4*/
2115 /* PLL2 Q input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
2116 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
2117
2118 /* SPI4 clock source configuration done later after clock selection check */
2119 break;
2120
2121 case RCC_SPI4CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for SPI4 */
2122 /* PLL3 Q input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
2123 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
2124
2125 /* SPI4 clock source configuration done later after clock selection check */
2126 break;
2127
2128 case RCC_SPI4CLKSOURCE_HSI:
2129 /* HSI oscillator is used as source of SPI4 clock*/
2130 /* SPI4 clock source configuration done later after clock selection check */
2131 break;
2132
2133 case RCC_SPI4CLKSOURCE_CSI:
2134 /* CSI oscillator is used as source of SPI4 clock */
2135 /* SPI4 clock source configuration done later after clock selection check */
2136 break;
2137
2138 case RCC_SPI4CLKSOURCE_HSE:
2139 /* HSE oscillator is used as source of SPI4 clock */
2140 /* SPI4 clock source configuration done later after clock selection check */
2141 break;
2142
2143 default:
2144 ret = HAL_ERROR;
2145 break;
2146 }
2147
2148 if (ret == HAL_OK)
2149 {
2150 /* Configure the SPI4 clock source */
2151 __HAL_RCC_SPI4_CONFIG(pPeriphClkInit->Spi4ClockSelection);
2152 }
2153 else
2154 {
2155 /* set overall return value */
2156 status = ret;
2157 }
2158
2159 }
2160 #endif /* SPI4 */
2161
2162 #if defined(SPI5)
2163 /*-------------------------- SPI5 clock source configuration ----------------*/
2164 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI5) == RCC_PERIPHCLK_SPI5)
2165 {
2166
2167 /* Check the parameters */
2168 assert_param(IS_RCC_SPI5CLKSOURCE(pPeriphClkInit->Spi5ClockSelection));
2169
2170 switch (pPeriphClkInit->Spi5ClockSelection)
2171 {
2172 case RCC_SPI5CLKSOURCE_PCLK3: /* PCLK3 (APB3 Clock) is used as clock source for SPI5 */
2173 /* SPI5 clock source configuration done later after clock selection check */
2174 break;
2175
2176 case RCC_SPI5CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for SPI5*/
2177 /* PLL2 Q input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
2178 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
2179
2180 /* SPI5 clock source configuration done later after clock selection check */
2181 break;
2182
2183 case RCC_SPI5CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for SPI5 */
2184 /* PLL3 Q input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
2185 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
2186
2187 /* SPI5 clock source configuration done later after clock selection check */
2188 break;
2189
2190 case RCC_SPI5CLKSOURCE_HSI:
2191 /* HSI oscillator is used as source of SPI5 clock*/
2192 /* SPI5 clock source configuration done later after clock selection check */
2193 break;
2194
2195 case RCC_SPI5CLKSOURCE_CSI:
2196 /* CSI oscillator is used as source of SPI5 clock */
2197 /* SPI5 clock source configuration done later after clock selection check */
2198 break;
2199
2200 case RCC_SPI5CLKSOURCE_HSE:
2201 /* HSE oscillator is used as source of SPI5 clock */
2202 /* SPI5 clock source configuration done later after clock selection check */
2203 break;
2204
2205 default:
2206 ret = HAL_ERROR;
2207 break;
2208 }
2209
2210 if (ret == HAL_OK)
2211 {
2212 /* Configure the SPI5 clock source */
2213 __HAL_RCC_SPI5_CONFIG(pPeriphClkInit->Spi5ClockSelection);
2214 }
2215 else
2216 {
2217 /* set overall return value */
2218 status = ret;
2219 }
2220
2221 }
2222 #endif /* SPI5 */
2223
2224 #if defined(SPI6)
2225 /*-------------------------- SPI6 clock source configuration ----------------*/
2226 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
2227 {
2228
2229 /* Check the parameters */
2230 assert_param(IS_RCC_SPI6CLKSOURCE(pPeriphClkInit->Spi6ClockSelection));
2231
2232 switch (pPeriphClkInit->Spi6ClockSelection)
2233 {
2234 case RCC_SPI6CLKSOURCE_PCLK2: /* PCLK2 (APB2 Clock) is used as clock source for SPI6 */
2235 /* SPI6 clock source configuration done later after clock selection check */
2236 break;
2237
2238 case RCC_SPI6CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for SPI6*/
2239 /* PLL2 Q input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
2240 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
2241
2242 /* SPI6 clock source configuration done later after clock selection check */
2243 break;
2244
2245 case RCC_SPI6CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for SPI6 */
2246 /* PLL3 Q input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
2247 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
2248
2249 /* SPI6 clock source configuration done later after clock selection check */
2250 break;
2251
2252 case RCC_SPI6CLKSOURCE_HSI:
2253 /* HSI oscillator is used as source of SPI6 clock*/
2254 /* SPI6 clock source configuration done later after clock selection check */
2255 break;
2256
2257 case RCC_SPI6CLKSOURCE_CSI:
2258 /* CSI oscillator is used as source of SPI6 clock */
2259 /* SPI6 clock source configuration done later after clock selection check */
2260 break;
2261
2262 case RCC_SPI6CLKSOURCE_HSE:
2263 /* HSE oscillator is used as source of SPI6 clock */
2264 /* SPI6 clock source configuration done later after clock selection check */
2265 break;
2266
2267 default:
2268 ret = HAL_ERROR;
2269 break;
2270 }
2271
2272 if (ret == HAL_OK)
2273 {
2274 /* Configure the SPI6 clock source */
2275 __HAL_RCC_SPI6_CONFIG(pPeriphClkInit->Spi6ClockSelection);
2276 }
2277 else
2278 {
2279 /* set overall return value */
2280 status = ret;
2281 }
2282
2283 }
2284 #endif /* SPI6 */
2285
2286 #if defined(OCTOSPI1)
2287 /*-------------------------- OctoSPIx clock source configuration ----------------*/
2288 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)
2289 {
2290 /* Check the parameters */
2291 assert_param(IS_RCC_OSPICLKSOURCE(pPeriphClkInit->OspiClockSelection));
2292
2293 switch (pPeriphClkInit->OspiClockSelection)
2294 {
2295 case RCC_OSPICLKSOURCE_HCLK: /* HCLK is used as clock source for OCTOSPI */
2296
2297 /* OCTOSPI clock source config set later after clock selection check */
2298 break;
2299
2300 case RCC_OSPICLKSOURCE_PLL1Q: /* PLL1 Q is used as clock source for OCTOSPI*/
2301
2302 /* Enable PLL1 Q CLK output */
2303 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
2304 break;
2305
2306 case RCC_OSPICLKSOURCE_PLL2R: /* PLL2 is used as clock source for OCTOSPI*/
2307 /* PLL2 R input clock, parameters M, N & R configuration and clock output (PLL2ClockOut) */
2308 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
2309 /* OCTOSPI clock source config set later after clock selection check */
2310 break;
2311
2312 case RCC_OSPICLKSOURCE_CLKP: /* CLKP is used as source of OCTOSPI clock*/
2313 /* OCTOSPI clock source config set later after clock selection check */
2314 break;
2315
2316 default:
2317 ret = HAL_ERROR;
2318 break;
2319 }
2320
2321 if (ret == HAL_OK)
2322 {
2323 /* Configure the OctoSPI clock source */
2324 __HAL_RCC_OSPI_CONFIG(pPeriphClkInit->OspiClockSelection);
2325 }
2326 else
2327 {
2328 /* set overall return value */
2329 status = ret;
2330 }
2331 }
2332 #endif /* OCTOSPI1*/
2333
2334 /*-------------------------- FDCAN kernel clock source configuration -------------*/
2335 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
2336 {
2337 assert_param(IS_RCC_FDCANCLK(pPeriphClkInit->FdcanClockSelection));
2338
2339 switch (pPeriphClkInit->FdcanClockSelection)
2340 {
2341 case RCC_FDCANCLKSOURCE_HSE: /* HSE is used as source of FDCAN kernel clock*/
2342 /* FDCAN kernel clock source config set later after clock selection check */
2343 break;
2344
2345 case RCC_FDCANCLKSOURCE_PLL1Q: /* PLL1 is used as clock source for FDCAN kernel clock*/
2346 /* Enable PLL1Q Clock output generated from System PLL . */
2347 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
2348 /* FDCAN kernel clock source config set later after clock selection check */
2349 break;
2350
2351 case RCC_FDCANCLKSOURCE_PLL2Q: /* PLL2 is used as clock source for FDCAN kernel clock*/
2352 /* PLL2Q input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
2353 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
2354 /* FDCAN kernel clock source config set later after clock selection check */
2355 break;
2356
2357 default:
2358 ret = HAL_ERROR;
2359 break;
2360 }
2361
2362 if (ret == HAL_OK)
2363 {
2364 /* Set the source of FDCAN kernel clock*/
2365 __HAL_RCC_FDCAN_CONFIG(pPeriphClkInit->FdcanClockSelection);
2366 }
2367 else
2368 {
2369 /* set overall return value */
2370 status = ret;
2371 }
2372 }
2373
2374 #if defined(USB_DRD_FS)
2375 /*------------------------------ USB Configuration -------------------------*/
2376 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
2377 {
2378
2379 /* Check the parameters */
2380 assert_param(IS_RCC_USBCLKSOURCE(pPeriphClkInit->UsbClockSelection));
2381
2382 switch (pPeriphClkInit->UsbClockSelection)
2383 {
2384 case RCC_USBCLKSOURCE_PLL1Q: /* PLL is used as clock source for USB*/
2385 /* Enable USB Clock output generated form System USB . */
2386 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
2387
2388 /* USB clock source configuration done later after clock selection check */
2389 break;
2390
2391 #if defined(RCC_USBCLKSOURCE_PLL3Q)
2392 case RCC_USBCLKSOURCE_PLL3Q: /* PLL3 is used as clock source for USB*/
2393 /* PLL3Q input clock, parameters M, N & Q configuration and clock output (PLL3ClockOut) */
2394 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
2395 #else
2396 case RCC_USBCLKSOURCE_PLL2Q: /* PLL2 is used as clock source for USB*/
2397 /* PLL2Q input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
2398 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
2399 #endif /* RCC_USBCLKSOURCE_PLL3Q */
2400 /* USB clock source configuration done later after clock selection check */
2401 break;
2402
2403 case RCC_USBCLKSOURCE_HSI48:
2404 /* HSI48 oscillator is used as source of USB clock */
2405 /* USB clock source configuration done later after clock selection check */
2406 break;
2407
2408 default:
2409 ret = HAL_ERROR;
2410 break;
2411 }
2412
2413 if (ret == HAL_OK)
2414 {
2415 /* Set the source of USB clock*/
2416 __HAL_RCC_USB_CONFIG(pPeriphClkInit->UsbClockSelection);
2417 }
2418 else
2419 {
2420 /* set overall return value */
2421 status = ret;
2422 }
2423
2424 }
2425 #endif /* USB_DRD_FS */
2426
2427 #if defined(CEC)
2428 /*-------------------------- CEC clock source configuration ----------------*/
2429 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
2430 {
2431
2432 /* Check the parameters */
2433 assert_param(IS_RCC_CECCLKSOURCE(pPeriphClkInit->CecClockSelection));
2434
2435 /* Configure the CEC clock source */
2436 __HAL_RCC_CEC_CONFIG(pPeriphClkInit->CecClockSelection);
2437
2438 }
2439 #endif /* CEC */
2440
2441 return status;
2442 }
2443
2444 /**
2445 * @brief Get the pPeriphClkInit according to the internal RCC configuration registers.
2446 * @param pPeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
2447 * returns the configuration information for the Extended Peripherals
2448 * clocks (ADC12, DAC, SDMMC1, SDMMC2, OCTOSPI1, TIM, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPTIM6,
2449 * SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, USART1, USART2, USART3, UART4, UART5, USART6, UART7, UART8,
2450 * UART9, USART10, USART11, UART12, LPUART1, I2C1, I2C2, I2C3, I2C4, I3C1, I3C2, CEC, FDCAN, SAI1,
2451 * SAI2, USB), PLL2 and PLL3.
2452 * @retval None
2453 */
HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef * pPeriphClkInit)2454 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit)
2455 {
2456 /* Set all possible values for the extended clock type parameter------------*/
2457 pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
2458 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
2459 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_ADCDAC | \
2460 RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | \
2461 RCC_PERIPHCLK_I3C1 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \
2462 RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_CKPER;
2463
2464 #if defined(USB_DRD_FS)
2465 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
2466 #endif /* USB_DRD_FS */
2467 #if defined(UART4)
2468 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_UART4;
2469 #endif /* UART4 */
2470 #if defined(UART5)
2471 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_UART5;
2472 #endif /* UART5 */
2473 #if defined(USART6)
2474 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART6;
2475 #endif /* UART6 */
2476 #if defined(UART7)
2477 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_UART7;
2478 #endif /* UART7 */
2479 #if defined(UART8)
2480 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_UART8;
2481 #endif /* UART8 */
2482 #if defined(UART9)
2483 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_UART9;
2484 #endif /* UART9 */
2485 #if defined(USART10)
2486 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART10;
2487 #endif /* UART10 */
2488 #if defined(USART11)
2489 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART11;
2490 #endif /* UART11 */
2491 #if defined(UART12)
2492 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_UART12;
2493 #endif /* UART12 */
2494 #if defined(I2C3)
2495 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C3;
2496 #endif /* I2C3 */
2497 #if defined(I2C4)
2498 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C4;
2499 #endif /* I2C4 */
2500 #if defined(I3C2)
2501 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I3C2;
2502 #endif /* I3C2 */
2503 #if defined(LPTIM3)
2504 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPTIM3;
2505 #endif /* LPTIM3 */
2506 #if defined(LPTIM4)
2507 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPTIM4;
2508 #endif /* LPTIM4 */
2509 #if defined(LPTIM5)
2510 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPTIM5;
2511 #endif /* LPTIM5 */
2512 #if defined(LPTIM6)
2513 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPTIM6;
2514 #endif /* LPTIM6 */
2515 #if defined(SPI4)
2516 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SPI4;
2517 #endif /* SPI4 */
2518 #if defined(SPI5)
2519 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SPI5;
2520 #endif /* SPI5 */
2521 #if defined(SPI6)
2522 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SPI6;
2523 #endif /* SPI6 */
2524 #if defined(SAI1)
2525 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI1;
2526 #endif /* SAI1 */
2527 #if defined(SAI2)
2528 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2;
2529 #endif /* SAI2 */
2530 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_FDCAN;
2531 #if defined(SDMMC1)
2532 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SDMMC1;
2533 #endif /* SDMMC1*/
2534 #if defined(SDMMC2)
2535 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SDMMC2;
2536 #endif /* SDMMC2*/
2537 #if defined(OCTOSPI1)
2538 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_OSPI;
2539 #endif /* OCTOSPI1 */
2540 #if defined(CEC)
2541 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC;
2542 #endif /* CEC */
2543
2544 /* Get the PLL2 Clock configuration -----------------------------------------------*/
2545 pPeriphClkInit->PLL2.PLL2Source = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC) >> RCC_PLL2CFGR_PLL2SRC_Pos);
2546 pPeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos);
2547 pPeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) >> RCC_PLL2DIVR_PLL2N_Pos) + 1U;
2548 pPeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P_Pos) + 1U;
2549 pPeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + 1U;
2550 pPeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2R) >> RCC_PLL2DIVR_PLL2R_Pos) + 1U;
2551 pPeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2RGE) >> RCC_PLL2CFGR_PLL2RGE_Pos);
2552 pPeriphClkInit->PLL2.PLL2FRACN = (uint32_t)((RCC->PLL2FRACR & RCC_PLL2FRACR_PLL2FRACN) >> \
2553 RCC_PLL2FRACR_PLL2FRACN_Pos);
2554
2555 #if defined(RCC_CR_PLL3ON)
2556 /* Get the PLL3 Clock configuration -----------------------------------------------*/
2557 pPeriphClkInit->PLL3.PLL3Source = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC) >> RCC_PLL3CFGR_PLL3SRC_Pos);
2558 pPeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos);
2559 pPeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) >> RCC_PLL3DIVR_PLL3N_Pos) + 1U;
2560 pPeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3P) >> RCC_PLL3DIVR_PLL3P_Pos) + 1U;
2561 pPeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3Q) >> RCC_PLL3DIVR_PLL3Q_Pos) + 1U;
2562 pPeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3R) >> RCC_PLL3DIVR_PLL3R_Pos) + 1U;
2563 pPeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3RGE) >> RCC_PLL3CFGR_PLL3RGE_Pos);
2564 pPeriphClkInit->PLL3.PLL3FRACN = (uint32_t)((RCC->PLL3FRACR & RCC_PLL3FRACR_PLL3FRACN) >> \
2565 RCC_PLL3FRACR_PLL3FRACN_Pos);
2566 #endif /* RCC_CR_PLL3ON */
2567
2568 /* Get the USART1 clock source ---------------------------------------------*/
2569 pPeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
2570
2571 /* Get the USART2 clock source ---------------------------------------------*/
2572 pPeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
2573
2574 /* Get the USART3 clock source ---------------------------------------------*/
2575 pPeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
2576
2577 #if defined(UART4)
2578 /* Get the UART4 clock source ----------------------------------------------*/
2579 pPeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
2580 #endif /* UART4 */
2581
2582 #if defined(UART5)
2583 /* Get the UART5 clock source ----------------------------------------------*/
2584 pPeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
2585 #endif /* UART5 */
2586
2587 #if defined(USART6)
2588 /* Get the USART6 clock source ---------------------------------------------*/
2589 pPeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();
2590 #endif /* USART6 */
2591
2592 #if defined(UART7)
2593 /* Get the UART7 clock source ---------------------------------------------*/
2594 pPeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE();
2595 #endif /* UART7 */
2596
2597 #if defined(UART8)
2598 /* Get the UART8 clock source ---------------------------------------------*/
2599 pPeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE();
2600 #endif /* UART8 */
2601
2602 #if defined(UART9)
2603 /* Get the UART9 clock source ---------------------------------------------*/
2604 pPeriphClkInit->Uart9ClockSelection = __HAL_RCC_GET_UART9_SOURCE();
2605 #endif /* UART9 */
2606
2607 #if defined(USART10)
2608 /* Get the USART10 clock source ---------------------------------------------*/
2609 pPeriphClkInit->Usart10ClockSelection = __HAL_RCC_GET_USART10_SOURCE();
2610 #endif /* USART10 */
2611
2612 #if defined(USART11)
2613 /* Get the USART11 clock source ---------------------------------------------*/
2614 pPeriphClkInit->Usart11ClockSelection = __HAL_RCC_GET_USART11_SOURCE();
2615 #endif /* USART11 */
2616
2617 #if defined(UART12)
2618 /* Get the UART12 clock source ---------------------------------------------*/
2619 pPeriphClkInit->Uart12ClockSelection = __HAL_RCC_GET_UART12_SOURCE();
2620 #endif /* UART12 */
2621
2622 /* Get the LPUART1 clock source --------------------------------------------*/
2623 pPeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
2624
2625 /* Get the I2C1 clock source -----------------------------------------------*/
2626 pPeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
2627
2628 /* Get the I2C2 clock source -----------------------------------------------*/
2629 pPeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
2630
2631 #if defined(I2C3)
2632 /* Get the I2C3 clock source -----------------------------------------------*/
2633 pPeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
2634 #endif /* I2C3 */
2635
2636 #if defined(I2C4)
2637 /* Get the I2C4 clock source -----------------------------------------------*/
2638 pPeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();
2639 #endif /* I2C4 */
2640
2641 /* Get the I3C1 clock source -----------------------------------------------*/
2642 pPeriphClkInit->I3c1ClockSelection = __HAL_RCC_GET_I3C1_SOURCE();
2643
2644 #if defined(I3C2)
2645 /* Get the I3C2 clock source -----------------------------------------------*/
2646 pPeriphClkInit->I3c2ClockSelection = __HAL_RCC_GET_I3C2_SOURCE();
2647 #endif /* I3C2 */
2648
2649 /* Get the LPTIM1 clock source ---------------------------------------------*/
2650 pPeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
2651
2652 /* Get the LPTIM2 clock source ---------------------------------------------*/
2653 pPeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE();
2654
2655 #if defined(LPTIM3)
2656 /* Get the LPTIM3 clock source ---------------------------------------------*/
2657 pPeriphClkInit->Lptim3ClockSelection = __HAL_RCC_GET_LPTIM3_SOURCE();
2658 #endif /* LPTIM3 */
2659
2660 #if defined(LPTIM4)
2661 /* Get the LPTIM4 clock source ---------------------------------------------*/
2662 pPeriphClkInit->Lptim4ClockSelection = __HAL_RCC_GET_LPTIM4_SOURCE();
2663 #endif /* LPTIM4 */
2664
2665 #if defined(LPTIM5)
2666 /* Get the LPTIM5 clock source ---------------------------------------------*/
2667 pPeriphClkInit->Lptim5ClockSelection = __HAL_RCC_GET_LPTIM5_SOURCE();
2668 #endif /* LPTIM5 */
2669
2670 #if defined(LPTIM6)
2671 /* Get the LPTIM6 clock source ---------------------------------------------*/
2672 pPeriphClkInit->Lptim6ClockSelection = __HAL_RCC_GET_LPTIM6_SOURCE();
2673 #endif /* LPTIM6 */
2674
2675 /* Get the FDCAN clock source ---------------------------------------------*/
2676 pPeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE();
2677
2678 #if defined(SAI1)
2679 /* Get the SAI1 clock source -----------------------------------------------*/
2680 pPeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
2681 #endif /* SAI1 */
2682
2683 #if defined(SAI2)
2684 /* Get the SAI2 clock source -----------------------------------------------*/
2685 pPeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
2686 #endif /* SAI2 */
2687
2688 #if defined(SDMMC1)
2689 /* Get the SDMMC1 clock source ----------------------------------------------*/
2690 pPeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();
2691 #endif /* SDMMC1 */
2692
2693 #if defined(SDMMC2)
2694 /* Get the SDMMC2 clock source ----------------------------------------------*/
2695 pPeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE();
2696 #endif /* SDMMC2 */
2697
2698 /* Get the ADCDAC clock source ---------------------------------------------*/
2699 pPeriphClkInit->AdcDacClockSelection = __HAL_RCC_GET_ADCDAC_SOURCE();
2700
2701 /* Get the DAC low-power clock source ---------------------------------------------*/
2702 pPeriphClkInit->DacLowPowerClockSelection = __HAL_RCC_GET_DAC_LP_SOURCE();
2703
2704 #if defined(OCTOSPI1)
2705 /* Get the OSPI clock source -----------------------------------------------*/
2706 pPeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE();
2707 #endif /* OCTOSPI1 */
2708
2709 /* Get the SPI1 clock source -----------------------------------------------*/
2710 pPeriphClkInit->Spi1ClockSelection = __HAL_RCC_GET_SPI1_SOURCE();
2711
2712 /* Get the SPI2 clock source -----------------------------------------------*/
2713 pPeriphClkInit->Spi2ClockSelection = __HAL_RCC_GET_SPI2_SOURCE();
2714
2715 /* Get the SPI3 clock source -----------------------------------------------*/
2716 pPeriphClkInit->Spi3ClockSelection = __HAL_RCC_GET_SPI3_SOURCE();
2717
2718 #if defined(SPI4)
2719 /* Get the SPI4 clock source -----------------------------------------------*/
2720 pPeriphClkInit->Spi4ClockSelection = __HAL_RCC_GET_SPI4_SOURCE();
2721 #endif /* SPI4 */
2722
2723 #if defined(SPI5)
2724 /* Get the SPI5 clock source -----------------------------------------------*/
2725 pPeriphClkInit->Spi5ClockSelection = __HAL_RCC_GET_SPI5_SOURCE();
2726 #endif /* SPI5 */
2727
2728 #if defined(SPI6)
2729 /* Get the SPI6 clock source -----------------------------------------------*/
2730 pPeriphClkInit->Spi6ClockSelection = __HAL_RCC_GET_SPI6_SOURCE();
2731 #endif /* SPI6 */
2732
2733 /* Get the RTC clock source ------------------------------------------------*/
2734 pPeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
2735
2736 /* Get the RNG clock source ------------------------------------------------*/
2737 pPeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE();
2738
2739 /* Get the CKPER clock source ------------------------------------------------*/
2740 pPeriphClkInit->CkperClockSelection = __HAL_RCC_GET_CLKP_SOURCE();
2741
2742 #if defined(CEC)
2743 /* Get the CEC clock source ------------------------------------------------*/
2744 pPeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
2745 #endif /* CEC */
2746
2747 #if defined(USB_DRD_FS)
2748 /* Get the USB clock source ------------------------------------------------*/
2749 pPeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
2750 #endif /* USB_DRD_FS */
2751
2752 /* Get the TIM Prescaler configuration -------------------------------------*/
2753 if ((RCC->CFGR1 & RCC_CFGR1_TIMPRE) == 0U)
2754 {
2755 pPeriphClkInit->TimPresSelection = RCC_TIMPRES_DEACTIVATED;
2756 }
2757 else
2758 {
2759 pPeriphClkInit->TimPresSelection = RCC_TIMPRES_ACTIVATED;
2760 }
2761 }
2762
2763 /**
2764 * @brief Returns the PLL1 clock frequencies : PLL1_P_Frequency, PLL1_R_Frequency and PLL1_Q_Frequency
2765 * @note The PLL1 clock frequencies computed by this function may not be the real
2766 * frequency in the chip. It is calculated based on the predefined
2767 * constant and the selected clock source:
2768 * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by
2769 the PLL factors.
2770 * @note This function can be used by the user application to compute the
2771 * baud-rate for the communication peripherals or configure other parameters.
2772 *
2773 * @note Each time PLL1CLK changes, this function must be called to update the
2774 * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect.
2775 * @param pPLL1_Clocks pointer to PLL1_ClocksTypeDef structure.
2776 * @retval None
2777 */
HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef * pPLL1_Clocks)2778 void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *pPLL1_Clocks)
2779 {
2780 uint32_t pll1source;
2781 uint32_t pll1m;
2782 uint32_t pll1n;
2783 uint32_t pll1fracen;
2784 uint32_t hsivalue;
2785 float_t fracn1;
2786 float_t pll1vco;
2787
2788 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL1M) * PLL1N
2789 PLL1xCLK = PLL1_VCO / PLL1x
2790 */
2791
2792 pll1n = (RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N);
2793 pll1source = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC);
2794 pll1m = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos);
2795 pll1fracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN) >> RCC_PLL1CFGR_PLL1FRACEN_Pos);
2796 fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \
2797 RCC_PLL1FRACR_PLL1FRACN_Pos));
2798
2799 if (pll1m != 0U)
2800 {
2801 switch (pll1source)
2802 {
2803
2804 case RCC_PLL1_SOURCE_HSI: /* HSI used as PLL1 clock source */
2805 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
2806 pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)pll1n + (fracn1 / (float_t)0x2000) + \
2807 (float_t)1);
2808 break;
2809
2810 case RCC_PLL1_SOURCE_CSI: /* CSI used as PLL1 clock source */
2811 pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)pll1n + (fracn1 / (float_t)0x2000) + \
2812 (float_t)1);
2813 break;
2814
2815 case RCC_PLL1_SOURCE_HSE: /* HSE used as PLL1 clock source */
2816 pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)pll1n + (fracn1 / (float_t)0x2000) + \
2817 (float_t)1);
2818 break;
2819
2820 default:
2821 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
2822 pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)pll1n + (fracn1 / (float_t)0x2000) + \
2823 (float_t)1);
2824 break;
2825 }
2826
2827 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2828 {
2829 if (__HAL_RCC_GET_PLL1_CLKOUT_CONFIG(RCC_PLL1_DIVP) != 0U)
2830 {
2831 pPLL1_Clocks->PLL1_P_Frequency = \
2832 (uint32_t)(float_t)(pll1vco / \
2833 ((float_t)(uint32_t)((RCC->PLL1DIVR & \
2834 RCC_PLL1DIVR_PLL1P) >> \
2835 RCC_PLL1DIVR_PLL1P_Pos) + \
2836 (float_t)1));
2837 }
2838 else
2839 {
2840 pPLL1_Clocks->PLL1_P_Frequency = 0U;
2841 }
2842 }
2843 else
2844 {
2845 pPLL1_Clocks->PLL1_P_Frequency = 0U;
2846 }
2847
2848 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2849 {
2850 if (__HAL_RCC_GET_PLL1_CLKOUT_CONFIG(RCC_PLL1_DIVQ) != 0U)
2851 {
2852 pPLL1_Clocks->PLL1_Q_Frequency = \
2853 (uint32_t)(float_t)(pll1vco / \
2854 ((float_t)(uint32_t)((RCC->PLL1DIVR & \
2855 RCC_PLL1DIVR_PLL1Q) >> \
2856 RCC_PLL1DIVR_PLL1Q_Pos) + \
2857 (float_t)1));
2858 }
2859 else
2860 {
2861 pPLL1_Clocks->PLL1_Q_Frequency = 0U;
2862 }
2863 }
2864 else
2865 {
2866 pPLL1_Clocks->PLL1_Q_Frequency = 0U;
2867 }
2868
2869 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2870 {
2871 if (__HAL_RCC_GET_PLL1_CLKOUT_CONFIG(RCC_PLL1_DIVR) != 0U)
2872 {
2873 pPLL1_Clocks->PLL1_R_Frequency = \
2874 (uint32_t)(float_t)(pll1vco / \
2875 ((float_t)(uint32_t)((RCC->PLL1DIVR & \
2876 RCC_PLL1DIVR_PLL1R) >> \
2877 RCC_PLL1DIVR_PLL1R_Pos) + \
2878 (float_t)1)) ;
2879 }
2880 else
2881 {
2882 pPLL1_Clocks->PLL1_R_Frequency = 0U;
2883 }
2884 }
2885 else
2886 {
2887 pPLL1_Clocks->PLL1_R_Frequency = 0U;
2888 }
2889
2890 }
2891 else
2892 {
2893 pPLL1_Clocks->PLL1_P_Frequency = 0U;
2894 pPLL1_Clocks->PLL1_Q_Frequency = 0U;
2895 pPLL1_Clocks->PLL1_R_Frequency = 0U;
2896 }
2897
2898 }
2899
2900 /**
2901 * @brief Returns the PLL2 clock frequencies: PLL2_P_Frequency, PLL2_R_Frequency and PLL2_Q_Frequency
2902 * @note The PLL2 clock frequencies computed by this function may not be the real
2903 * frequency in the chip. It is calculated based on the predefined
2904 * constant and the selected clock source:
2905 * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by
2906 the PLL factors.
2907 * @note This function can be used by the user application to compute the
2908 * baud-rate for the communication peripherals or configure other parameters.
2909 *
2910 * @note Each time PLL2CLK changes, this function must be called to update the
2911 * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect.
2912 * @param pPLL2_Clocks pointer to PLL2_ClocksTypeDef structure.
2913 * @retval None
2914 */
HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef * pPLL2_Clocks)2915 void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *pPLL2_Clocks)
2916 {
2917 uint32_t pll2source;
2918 uint32_t pll2m;
2919 uint32_t pll2n;
2920 uint32_t pll2fracen;
2921 uint32_t hsivalue;
2922 float_t fracn2;
2923 float_t pll2vco;
2924
2925 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N
2926 PLL2xCLK = PLL2_VCO / PLL2x
2927 */
2928 pll2n = (RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N);
2929 pll2source = (RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC);
2930 pll2m = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos);
2931 pll2fracen = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2FRACEN) >> RCC_PLL2CFGR_PLL2FRACEN_Pos);
2932 fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_PLL2FRACN) >> \
2933 RCC_PLL2FRACR_PLL2FRACN_Pos));
2934
2935 if (pll2m != 0U)
2936 {
2937 switch (pll2source)
2938 {
2939 case RCC_PLL2_SOURCE_HSI: /* HSI used as PLL clock source */
2940 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
2941 pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)pll2n + (fracn2 / (float_t)0x2000) + \
2942 (float_t)1);
2943 break;
2944
2945 case RCC_PLL2_SOURCE_CSI: /* CSI used as PLL clock source */
2946 pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)pll2n + (fracn2 / (float_t)0x2000) + \
2947 (float_t)1);
2948 break;
2949
2950 case RCC_PLL2_SOURCE_HSE: /* HSE used as PLL clock source */
2951 pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)pll2n + (fracn2 / (float_t)0x2000) + \
2952 (float_t)1);
2953 break;
2954
2955 default:
2956 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
2957 pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)pll2n + (fracn2 / (float_t)0x2000) + \
2958 (float_t)1);
2959 break;
2960 }
2961
2962 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2963 {
2964 if (__HAL_RCC_GET_PLL2_CLKOUT_CONFIG(RCC_PLL2_DIVP) != 0U)
2965 {
2966 pPLL2_Clocks->PLL2_P_Frequency = \
2967 (uint32_t)(float_t)(pll2vco / \
2968 ((float_t)(uint32_t)((RCC->PLL2DIVR & \
2969 RCC_PLL2DIVR_PLL2P) >> \
2970 RCC_PLL2DIVR_PLL2P_Pos) + \
2971 (float_t)1));
2972 }
2973 else
2974 {
2975 pPLL2_Clocks->PLL2_P_Frequency = 0U;
2976 }
2977 }
2978 else
2979 {
2980 pPLL2_Clocks->PLL2_P_Frequency = 0U;
2981 }
2982
2983 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2984 {
2985 if (__HAL_RCC_GET_PLL2_CLKOUT_CONFIG(RCC_PLL2_DIVQ) != 0U)
2986 {
2987 pPLL2_Clocks->PLL2_Q_Frequency = \
2988 (uint32_t)(float_t)(pll2vco / \
2989 ((float_t)(uint32_t)((RCC->PLL2DIVR & \
2990 RCC_PLL2DIVR_PLL2Q) >> \
2991 RCC_PLL2DIVR_PLL2Q_Pos) + \
2992 (float_t)1));
2993 }
2994 else
2995 {
2996 pPLL2_Clocks->PLL2_Q_Frequency = 0U;
2997 }
2998 }
2999 else
3000 {
3001 pPLL2_Clocks->PLL2_Q_Frequency = 0U;
3002 }
3003
3004 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
3005 {
3006 if (__HAL_RCC_GET_PLL2_CLKOUT_CONFIG(RCC_PLL2_DIVR) != 0U)
3007 {
3008 pPLL2_Clocks->PLL2_R_Frequency = \
3009 (uint32_t)(float_t)(pll2vco / \
3010 ((float_t)(uint32_t)((RCC->PLL2DIVR & \
3011 RCC_PLL2DIVR_PLL2R) >> \
3012 RCC_PLL2DIVR_PLL2R_Pos) + \
3013 (float_t)1));
3014 }
3015 else
3016 {
3017 pPLL2_Clocks->PLL2_R_Frequency = 0U;
3018 }
3019 }
3020 else
3021 {
3022 pPLL2_Clocks->PLL2_R_Frequency = 0U;
3023 }
3024 }
3025 else
3026 {
3027 pPLL2_Clocks->PLL2_P_Frequency = 0U;
3028 pPLL2_Clocks->PLL2_Q_Frequency = 0U;
3029 pPLL2_Clocks->PLL2_R_Frequency = 0U;
3030 }
3031 }
3032
3033 #if defined(RCC_CR_PLL3ON)
3034 /**
3035 * @brief Returns the PLL3 clock frequencies: PLL3_P_Frequency, PLL3_R_Frequency and PLL3_Q_Frequency
3036 * @note The PLL3 clock frequencies computed by this function may not be the real
3037 * frequency in the chip. It is calculated based on the predefined
3038 * constant and the selected clock source:
3039 * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by
3040 the PLL factors.
3041 * @note This function can be used by the user application to compute the
3042 * baud-rate for the communication peripherals or configure other parameters.
3043 *
3044 * @note Each time PLL3CLK changes, this function must be called to update the
3045 * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect.
3046 * @param pPLL3_Clocks pointer to PLL3_ClocksTypeDef structure.
3047 * @retval None
3048 */
HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef * pPLL3_Clocks)3049 void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *pPLL3_Clocks)
3050 {
3051 uint32_t pll3source;
3052 uint32_t pll3m;
3053 uint32_t pll3n;
3054 uint32_t pll3fracen;
3055 uint32_t hsivalue;
3056 float_t fracn3;
3057 float_t pll3vco;
3058
3059 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N
3060 PLL3xCLK = PLL3_VCO / PLL3x
3061 */
3062 pll3n = (RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N);
3063 pll3source = (RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC);
3064 pll3m = ((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos);
3065 pll3fracen = ((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3FRACEN) >> RCC_PLL3CFGR_PLL3FRACEN_Pos);
3066 fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_PLL3FRACN) >> \
3067 RCC_PLL3FRACR_PLL3FRACN_Pos));
3068
3069 if (pll3m != 0U)
3070 {
3071 switch (pll3source)
3072 {
3073 case RCC_PLL3_SOURCE_HSI: /* HSI used as PLL clock source */
3074 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3075 pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)pll3n + (fracn3 / (float_t)0x2000) + \
3076 (float_t)1);
3077 break;
3078
3079 case RCC_PLL3_SOURCE_CSI: /* CSI used as PLL clock source */
3080 pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)pll3n + (fracn3 / (float_t)0x2000) + \
3081 (float_t)1);
3082 break;
3083
3084 case RCC_PLL3_SOURCE_HSE: /* HSE used as PLL clock source */
3085 pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)pll3n + (fracn3 / (float_t)0x2000) + \
3086 (float_t)1);
3087 break;
3088
3089 default:
3090 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3091 pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)pll3n + (fracn3 / (float_t)0x2000) + \
3092 (float_t)1);
3093 break;
3094 }
3095
3096 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
3097 {
3098 if (__HAL_RCC_GET_PLL3_CLKOUT_CONFIG(RCC_PLL3_DIVP) != 0U)
3099 {
3100 pPLL3_Clocks->PLL3_P_Frequency = \
3101 (uint32_t)(float_t)(pll3vco / \
3102 ((float_t)(uint32_t)((RCC->PLL3DIVR & \
3103 RCC_PLL3DIVR_PLL3P) >> \
3104 RCC_PLL3DIVR_PLL3P_Pos) + \
3105 (float_t)1));
3106 }
3107 else
3108 {
3109 pPLL3_Clocks->PLL3_P_Frequency = 0U;
3110 }
3111 }
3112 else
3113 {
3114 pPLL3_Clocks->PLL3_P_Frequency = 0U;
3115 }
3116
3117 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
3118 {
3119 if (__HAL_RCC_GET_PLL3_CLKOUT_CONFIG(RCC_PLL3_DIVQ) != 0U)
3120 {
3121 pPLL3_Clocks->PLL3_Q_Frequency = \
3122 (uint32_t)(float_t)(pll3vco / \
3123 ((float_t)(uint32_t)((RCC->PLL3DIVR & \
3124 RCC_PLL3DIVR_PLL3Q) >> \
3125 RCC_PLL3DIVR_PLL3Q_Pos) + \
3126 (float_t)1));
3127 }
3128 else
3129 {
3130 pPLL3_Clocks->PLL3_Q_Frequency = 0U;
3131 }
3132 }
3133 else
3134 {
3135 pPLL3_Clocks->PLL3_Q_Frequency = 0U;
3136 }
3137
3138 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
3139 {
3140 if (__HAL_RCC_GET_PLL3_CLKOUT_CONFIG(RCC_PLL3_DIVR) != 0U)
3141 {
3142 pPLL3_Clocks->PLL3_R_Frequency = \
3143 (uint32_t)(float_t)(pll3vco / \
3144 ((float_t)(uint32_t)((RCC->PLL3DIVR & \
3145 RCC_PLL3DIVR_PLL3R) >> \
3146 RCC_PLL3DIVR_PLL3R_Pos) + \
3147 (float_t)1));
3148 }
3149 else
3150 {
3151 pPLL3_Clocks->PLL3_R_Frequency = 0U;
3152 }
3153 }
3154 else
3155 {
3156 pPLL3_Clocks->PLL3_R_Frequency = 0U;
3157 }
3158 }
3159 else
3160 {
3161 pPLL3_Clocks->PLL3_P_Frequency = 0U;
3162 pPLL3_Clocks->PLL3_Q_Frequency = 0U;
3163 pPLL3_Clocks->PLL3_R_Frequency = 0U;
3164 }
3165 }
3166 #endif /* RCC_CR_PLL3ON */
3167
3168 /**
3169 * @brief Return the peripheral clock frequency for peripherals
3170 * @note Return 0 if peripheral clock identifier not managed by this API
3171 * @param PeriphClk Peripheral clock identifier
3172 * This parameter can be one of the following values:
3173 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
3174 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
3175 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
3176 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (*)
3177 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (*)
3178 * @arg @ref RCC_PERIPHCLK_USART6 USART6 peripheral clock (*)
3179 * @arg @ref RCC_PERIPHCLK_UART7 UART7 peripheral clock (*)
3180 * @arg @ref RCC_PERIPHCLK_UART8 UART8 peripheral clock (*)
3181 * @arg @ref RCC_PERIPHCLK_UART9 UART9 peripheral clock (*)
3182 * @arg @ref RCC_PERIPHCLK_USART10 USART10 peripheral clock (*)
3183 * @arg @ref RCC_PERIPHCLK_USART11 USART11 peripheral clock (*)
3184 * @arg @ref RCC_PERIPHCLK_UART12 UART12 peripheral clock (*)
3185 * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
3186 * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
3187 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
3188 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock (*)
3189 * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (*)
3190 * @arg @ref RCC_PERIPHCLK_I3C1 I3C1 peripheral clock
3191 * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
3192 * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
3193 * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock (*)
3194 * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (*)
3195 * @arg @ref RCC_PERIPHCLK_ADCDAC ADCDAC peripheral clock
3196 * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock
3197 * @arg @ref RCC_PERIPHCLK_SDMMC1 SDMMC1 peripheral clock (*)
3198 * @arg @ref RCC_PERIPHCLK_SDMMC2 SDMMC2 peripheral clock (**)
3199 * @arg @ref RCC_PERIPHCLK_CKPER CKPER peripheral clock
3200 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
3201 * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
3202 * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock
3203 * @arg @ref RCC_PERIPHCLK_SPI2 SPI2 peripheral clock
3204 * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock
3205 * @arg @ref RCC_PERIPHCLK_SPI4 SPI4 peripheral clock (*)
3206 * @arg @ref RCC_PERIPHCLK_SPI5 SPI5 peripheral clock (*)
3207 * @arg @ref RCC_PERIPHCLK_SPI6 SPI6 peripheral clock (*)
3208 * @arg @ref RCC_PERIPHCLK_OSPI OCTOSPI peripheral clock (*)
3209 * @arg @ref RCC_PERIPHCLK_FDCAN FDCAN peripheral clock
3210 * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock (*)
3211 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
3212 * @arg @ref RCC_PERIPHCLK_LPTIM3 LPTIM3 peripheral clock (*)
3213 * @arg @ref RCC_PERIPHCLK_LPTIM4 LPTIM4 peripheral clock (*)
3214 * @arg @ref RCC_PERIPHCLK_LPTIM5 LPTIM5 peripheral clock (*)
3215 * @arg @ref RCC_PERIPHCLK_LPTIM6 LPTIM6 peripheral clock (*)
3216 * @arg @ref RCC_PERIPHCLK_DAC_LP DAC low-power peripheral clock
3217 * @arg @ref RCC_PERIPHCLK_TIM TIM peripheral clock
3218 *
3219 * @retval Frequency in Hz
3220 *
3221 * (*) : For stm32h56xxx and stm32h57xxx family lines only.
3222 * (**) : For stm32h563xx and stm32h57xxx family lines only.
3223 * (***) : For stm32h503xx family line only.
3224 */
HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)3225 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)
3226 {
3227 PLL1_ClocksTypeDef pll1_clocks;
3228 PLL2_ClocksTypeDef pll2_clocks;
3229 #if defined(RCC_CR_PLL3ON)
3230 PLL3_ClocksTypeDef pll3_clocks;
3231 #endif /* RCC_CR_PLL3ON */
3232
3233 uint32_t frequency;
3234 uint32_t ckpclocksource;
3235 uint32_t srcclk;
3236
3237 /* Check the parameters */
3238 assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
3239
3240 if (PeriphClk == RCC_PERIPHCLK_RTC)
3241 {
3242 /* Get the current RTC source */
3243 srcclk = __HAL_RCC_GET_RTC_SOURCE();
3244
3245 /* Check if LSE is ready and if RTC clock selection is LSE */
3246 if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_RTCCLKSOURCE_LSE))
3247 {
3248 frequency = LSE_VALUE;
3249 }
3250 /* Check if LSI is ready and if RTC clock selection is LSI */
3251 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_RTCCLKSOURCE_LSI))
3252 {
3253 frequency = LSI_VALUE;
3254 }
3255 /* Check if HSE is ready and if RTC clock selection is HSE_DIVx*/
3256 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_RTCCLKSOURCE_HSE_DIVx))
3257 {
3258 if (__HAL_RCC_GET_RTC_HSE_PRESCALER() >= RCC_RTC_HSE_DIV2)
3259 {
3260 frequency = (HSE_VALUE / ((uint32_t)(__HAL_RCC_GET_RTC_HSE_PRESCALER() >> RCC_CFGR1_RTCPRE_Pos)));
3261 }
3262 else
3263 {
3264 frequency = 0U;
3265 }
3266
3267 }
3268 /* Clock not enabled for RTC*/
3269 else
3270 {
3271 frequency = 0U;
3272 }
3273 }
3274 else
3275 {
3276 /* Other external peripheral clock source than RTC */
3277 switch (PeriphClk)
3278 {
3279 #if defined (SAI1)
3280 case RCC_PERIPHCLK_SAI1:
3281
3282 srcclk = __HAL_RCC_GET_SAI1_SOURCE();
3283
3284 switch (srcclk)
3285 {
3286 case RCC_SAI1CLKSOURCE_PLL1Q: /* PLL1Q is the clock source for SAI1 */
3287 {
3288 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
3289 frequency = pll1_clocks.PLL1_Q_Frequency;
3290 break;
3291 }
3292 case RCC_SAI1CLKSOURCE_PLL2P: /* PLL2P is the clock source for SAI1 */
3293 {
3294 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3295 frequency = pll2_clocks.PLL2_P_Frequency;
3296 break;
3297 }
3298 case RCC_SAI1CLKSOURCE_PLL3P: /* PLLI3P is the clock source for SAI1 */
3299 {
3300 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3301 frequency = pll3_clocks.PLL3_P_Frequency;
3302 break;
3303 }
3304 case RCC_SAI1CLKSOURCE_PIN:
3305 {
3306 frequency = EXTERNAL_CLOCK_VALUE;
3307 break;
3308 }
3309 case RCC_SAI1CLKSOURCE_CLKP: /* CLKP is the clock source for SAI1 */
3310 {
3311
3312 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
3313
3314 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
3315 {
3316 /* In Case the CKPER Source is HSI */
3317 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3318 }
3319
3320 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
3321 {
3322 /* In Case the CKPER Source is CSI */
3323 frequency = CSI_VALUE;
3324 }
3325
3326 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
3327 {
3328 /* In Case the CKPER Source is HSE */
3329 frequency = HSE_VALUE;
3330 }
3331
3332 else
3333 {
3334 /* In Case the CKPER is disabled*/
3335 frequency = 0U;
3336 }
3337
3338 break;
3339 }
3340 default :
3341 {
3342 frequency = 0U;
3343 break;
3344 }
3345 }
3346 break;
3347 #endif /*SAI1*/
3348
3349 #if defined(SAI2)
3350 case RCC_PERIPHCLK_SAI2:
3351
3352 srcclk = __HAL_RCC_GET_SAI2_SOURCE();
3353
3354 switch (srcclk)
3355 {
3356 case RCC_SAI2CLKSOURCE_PLL1Q: /* PLL1Q is the clock source for SAI2 */
3357 {
3358 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
3359 frequency = pll1_clocks.PLL1_Q_Frequency;
3360 break;
3361 }
3362 case RCC_SAI2CLKSOURCE_PLL2P: /* PLL2P is the clock source for SAI2 */
3363 {
3364 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3365 frequency = pll2_clocks.PLL2_P_Frequency;
3366 break;
3367 }
3368 case RCC_SAI2CLKSOURCE_PLL3P: /* PLLI3P is the clock source for SAI2 */
3369 {
3370 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3371 frequency = pll3_clocks.PLL3_P_Frequency;
3372 break;
3373 }
3374 case RCC_SAI2CLKSOURCE_PIN:
3375 {
3376 frequency = EXTERNAL_CLOCK_VALUE;
3377 break;
3378 }
3379 case RCC_SAI2CLKSOURCE_CLKP: /* CLKP is the clock source for SAI2 */
3380 {
3381
3382 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
3383
3384 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
3385 {
3386 /* In Case the CKPER Source is HSI */
3387 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3388 }
3389
3390 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
3391 {
3392 /* In Case the CKPER Source is CSI */
3393 frequency = CSI_VALUE;
3394 }
3395
3396 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
3397 {
3398 /* In Case the CKPER Source is HSE */
3399 frequency = HSE_VALUE;
3400 }
3401
3402 else
3403 {
3404 /* In Case the CKPER is disabled*/
3405 frequency = 0U;
3406 }
3407
3408 break;
3409 }
3410 default :
3411 {
3412 frequency = 0U;
3413 break;
3414 }
3415 }
3416 break;
3417 #endif /* SAI2 */
3418
3419 #if defined(SDMMC1)
3420 case RCC_PERIPHCLK_SDMMC1:
3421 srcclk = __HAL_RCC_GET_SDMMC1_SOURCE();
3422 if (srcclk == RCC_SDMMC1CLKSOURCE_PLL1Q)
3423 {
3424 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
3425 frequency = pll1_clocks.PLL1_Q_Frequency;
3426 }
3427 else if (srcclk == RCC_SDMMC1CLKSOURCE_PLL2R)
3428 {
3429 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3430 frequency = pll2_clocks.PLL2_R_Frequency;
3431 }
3432 else
3433 {
3434 frequency = 0U;
3435 }
3436 break;
3437 #endif /* SDMMC1 */
3438
3439 #if defined(SDMMC2)
3440 case RCC_PERIPHCLK_SDMMC2:
3441 srcclk = __HAL_RCC_GET_SDMMC2_SOURCE();
3442 if (srcclk == RCC_SDMMC2CLKSOURCE_PLL1Q)
3443 {
3444 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
3445 frequency = pll1_clocks.PLL1_Q_Frequency;
3446 }
3447 else if (srcclk == RCC_SDMMC2CLKSOURCE_PLL2R)
3448 {
3449 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3450 frequency = pll2_clocks.PLL2_R_Frequency;
3451 }
3452 else
3453 {
3454 frequency = 0U;
3455 }
3456 break;
3457 #endif /* SDMMC2 */
3458
3459 case RCC_PERIPHCLK_USART1:
3460 /* Get the current USART1 source */
3461 srcclk = __HAL_RCC_GET_USART1_SOURCE();
3462
3463 if (srcclk == RCC_USART1CLKSOURCE_PCLK2)
3464 {
3465 frequency = HAL_RCC_GetPCLK2Freq();
3466 }
3467 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_USART1CLKSOURCE_PLL2Q))
3468 {
3469 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3470 frequency = pll2_clocks.PLL2_Q_Frequency;
3471 }
3472 #if defined(RCC_USART1CLKSOURCE_PLL3Q)
3473 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_USART1CLKSOURCE_PLL3Q))
3474 {
3475 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3476 frequency = pll3_clocks.PLL3_Q_Frequency;
3477 }
3478 #endif /* RCC_USART1CLKSOURCE_PLL3Q */
3479 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_HSI))
3480 {
3481 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3482 }
3483 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_CSI))
3484 {
3485 frequency = CSI_VALUE;
3486 }
3487 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE))
3488 {
3489 frequency = LSE_VALUE;
3490 }
3491 /* Clock not enabled for USART1 */
3492 else
3493 {
3494 frequency = 0U;
3495 }
3496 break;
3497
3498 case RCC_PERIPHCLK_USART2:
3499 /* Get the current USART2 source */
3500 srcclk = __HAL_RCC_GET_USART2_SOURCE();
3501
3502 if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
3503 {
3504 frequency = HAL_RCC_GetPCLK1Freq();
3505 }
3506 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_USART2CLKSOURCE_PLL2Q))
3507 {
3508 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3509 frequency = pll2_clocks.PLL2_Q_Frequency;
3510 }
3511 #if defined(RCC_USART2CLKSOURCE_PLL3Q)
3512 else if ((srcclk == RCC_USART2CLKSOURCE_PLL3Q))
3513 {
3514 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3515 frequency = pll3_clocks.PLL3_Q_Frequency;
3516 }
3517 #endif /* RCC_USART2CLKSOURCE_PLL3Q */
3518 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_HSI))
3519 {
3520 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3521 }
3522 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_CSI))
3523 {
3524 frequency = CSI_VALUE;
3525 }
3526 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART2CLKSOURCE_LSE))
3527 {
3528 frequency = LSE_VALUE;
3529 }
3530 /* Clock not enabled for USART2 */
3531 else
3532 {
3533 frequency = 0U;
3534 }
3535 break;
3536
3537 case RCC_PERIPHCLK_USART3:
3538 /* Get the current USART3 source */
3539 srcclk = __HAL_RCC_GET_USART3_SOURCE();
3540
3541 if (srcclk == RCC_USART3CLKSOURCE_PCLK1)
3542 {
3543 frequency = HAL_RCC_GetPCLK1Freq();
3544 }
3545 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_USART3CLKSOURCE_PLL2Q))
3546 {
3547 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3548 frequency = pll2_clocks.PLL2_Q_Frequency;
3549 }
3550 #if defined(RCC_USART3CLKSOURCE_PLL3Q)
3551 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_USART3CLKSOURCE_PLL3Q))
3552 {
3553 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3554 frequency = pll3_clocks.PLL3_Q_Frequency;
3555 }
3556 #endif /* RCC_USART3CLKSOURCE_PLL3S */
3557 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_HSI))
3558 {
3559 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3560 }
3561 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_CSI))
3562 {
3563 frequency = CSI_VALUE;
3564 }
3565 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART3CLKSOURCE_LSE))
3566 {
3567 frequency = LSE_VALUE;
3568 }
3569 /* Clock not enabled for USART3 */
3570 else
3571 {
3572 frequency = 0U;
3573 }
3574 break;
3575
3576 #if defined(UART4)
3577 case RCC_PERIPHCLK_UART4:
3578 /* Get the current UART4 source */
3579 srcclk = __HAL_RCC_GET_UART4_SOURCE();
3580
3581 if (srcclk == RCC_UART4CLKSOURCE_PCLK1)
3582 {
3583 frequency = HAL_RCC_GetPCLK1Freq();
3584 }
3585 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_UART4CLKSOURCE_PLL2Q))
3586 {
3587 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3588 frequency = pll2_clocks.PLL2_Q_Frequency;
3589 }
3590 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_UART4CLKSOURCE_PLL3Q))
3591 {
3592 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3593 frequency = pll3_clocks.PLL3_Q_Frequency;
3594 }
3595 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART4CLKSOURCE_HSI))
3596 {
3597 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3598 }
3599 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_UART4CLKSOURCE_CSI))
3600 {
3601 frequency = CSI_VALUE;
3602 }
3603 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART4CLKSOURCE_LSE))
3604 {
3605 frequency = LSE_VALUE;
3606 }
3607 /* Clock not enabled for UART4 */
3608 else
3609 {
3610 frequency = 0U;
3611 }
3612 break;
3613 #endif /* UART4 */
3614
3615 #if defined(UART5)
3616 case RCC_PERIPHCLK_UART5:
3617 /* Get the current UART5 source */
3618 srcclk = __HAL_RCC_GET_UART5_SOURCE();
3619
3620 if (srcclk == RCC_UART5CLKSOURCE_PCLK1)
3621 {
3622 frequency = HAL_RCC_GetPCLK1Freq();
3623 }
3624 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_UART5CLKSOURCE_PLL2Q))
3625 {
3626 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3627 frequency = pll2_clocks.PLL2_Q_Frequency;
3628 }
3629 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_UART5CLKSOURCE_PLL3Q))
3630 {
3631 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3632 frequency = pll3_clocks.PLL3_Q_Frequency;
3633 }
3634 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART5CLKSOURCE_HSI))
3635 {
3636 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3637 }
3638 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_UART5CLKSOURCE_CSI))
3639 {
3640 frequency = CSI_VALUE;
3641 }
3642 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART5CLKSOURCE_LSE))
3643 {
3644 frequency = LSE_VALUE;
3645 }
3646 /* Clock not enabled for UART5 */
3647 else
3648 {
3649 frequency = 0U;
3650 }
3651 break;
3652 #endif /* UART5 */
3653
3654 #if defined(USART6)
3655 case RCC_PERIPHCLK_USART6:
3656 /* Get the current USART6 source */
3657 srcclk = __HAL_RCC_GET_USART6_SOURCE();
3658
3659 if (srcclk == RCC_USART6CLKSOURCE_PCLK1)
3660 {
3661 frequency = HAL_RCC_GetPCLK1Freq();
3662 }
3663 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_USART6CLKSOURCE_PLL2Q))
3664 {
3665 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3666 frequency = pll2_clocks.PLL2_Q_Frequency;
3667 }
3668 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_USART6CLKSOURCE_PLL3Q))
3669 {
3670 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3671 frequency = pll3_clocks.PLL3_Q_Frequency;
3672 }
3673 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART6CLKSOURCE_HSI))
3674 {
3675 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3676 }
3677 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_USART6CLKSOURCE_CSI))
3678 {
3679 frequency = CSI_VALUE;
3680 }
3681 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART6CLKSOURCE_LSE))
3682 {
3683 frequency = LSE_VALUE;
3684 }
3685 /* Clock not enabled for USART6 */
3686 else
3687 {
3688 frequency = 0U;
3689 }
3690 break;
3691 #endif /* USART6 */
3692
3693 #if defined(UART7)
3694 case RCC_PERIPHCLK_UART7:
3695 /* Get the current UART7 source */
3696 srcclk = __HAL_RCC_GET_UART7_SOURCE();
3697
3698 if (srcclk == RCC_UART7CLKSOURCE_PCLK1)
3699 {
3700 frequency = HAL_RCC_GetPCLK1Freq();
3701 }
3702 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_UART7CLKSOURCE_PLL2Q))
3703 {
3704 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3705 frequency = pll2_clocks.PLL2_Q_Frequency;
3706 }
3707 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_UART7CLKSOURCE_PLL3Q))
3708 {
3709 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3710 frequency = pll3_clocks.PLL3_Q_Frequency;
3711 }
3712 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART7CLKSOURCE_HSI))
3713 {
3714 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3715 }
3716 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_UART7CLKSOURCE_CSI))
3717 {
3718 frequency = CSI_VALUE;
3719 }
3720 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART7CLKSOURCE_LSE))
3721 {
3722 frequency = LSE_VALUE;
3723 }
3724 /* Clock not enabled for UART7 */
3725 else
3726 {
3727 frequency = 0U;
3728 }
3729 break;
3730 #endif /* UART7 */
3731
3732 #if defined(UART8)
3733 case RCC_PERIPHCLK_UART8:
3734 /* Get the current UART8 source */
3735 srcclk = __HAL_RCC_GET_UART8_SOURCE();
3736
3737 if (srcclk == RCC_UART8CLKSOURCE_PCLK1)
3738 {
3739 frequency = HAL_RCC_GetPCLK1Freq();
3740 }
3741 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_UART8CLKSOURCE_PLL2Q))
3742 {
3743 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3744 frequency = pll2_clocks.PLL2_Q_Frequency;
3745 }
3746 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_UART8CLKSOURCE_PLL3Q))
3747 {
3748 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3749 frequency = pll3_clocks.PLL3_Q_Frequency;
3750 }
3751 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART8CLKSOURCE_HSI))
3752 {
3753 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3754 }
3755 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_UART8CLKSOURCE_CSI))
3756 {
3757 frequency = CSI_VALUE;
3758 }
3759 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART8CLKSOURCE_LSE))
3760 {
3761 frequency = LSE_VALUE;
3762 }
3763 /* Clock not enabled for UART8 */
3764 else
3765 {
3766 frequency = 0U;
3767 }
3768 break;
3769 #endif /* UART8 */
3770
3771 #if defined(UART9)
3772 case RCC_PERIPHCLK_UART9:
3773 /* Get the current UART9 source */
3774 srcclk = __HAL_RCC_GET_UART9_SOURCE();
3775
3776 if (srcclk == RCC_UART9CLKSOURCE_PCLK1)
3777 {
3778 frequency = HAL_RCC_GetPCLK1Freq();
3779 }
3780 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_UART9CLKSOURCE_PLL2Q))
3781 {
3782 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3783 frequency = pll2_clocks.PLL2_Q_Frequency;
3784 }
3785 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_UART9CLKSOURCE_PLL3Q))
3786 {
3787 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3788 frequency = pll3_clocks.PLL3_Q_Frequency;
3789 }
3790 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART9CLKSOURCE_HSI))
3791 {
3792 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3793 }
3794 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_UART9CLKSOURCE_CSI))
3795 {
3796 frequency = CSI_VALUE;
3797 }
3798 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART9CLKSOURCE_LSE))
3799 {
3800 frequency = LSE_VALUE;
3801 }
3802 /* Clock not enabled for UART9 */
3803 else
3804 {
3805 frequency = 0U;
3806 }
3807 break;
3808 #endif /* UART9 */
3809
3810 #if defined(USART10)
3811 case RCC_PERIPHCLK_USART10:
3812 /* Get the current USART10 source */
3813 srcclk = __HAL_RCC_GET_USART10_SOURCE();
3814
3815 if (srcclk == RCC_USART10CLKSOURCE_PCLK1)
3816 {
3817 frequency = HAL_RCC_GetPCLK1Freq();
3818 }
3819 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_USART10CLKSOURCE_PLL2Q))
3820 {
3821 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3822 frequency = pll2_clocks.PLL2_Q_Frequency;
3823 }
3824 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_USART10CLKSOURCE_PLL3Q))
3825 {
3826 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3827 frequency = pll3_clocks.PLL3_Q_Frequency;
3828 }
3829 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART10CLKSOURCE_HSI))
3830 {
3831 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3832 }
3833 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_USART10CLKSOURCE_CSI))
3834 {
3835 frequency = CSI_VALUE;
3836 }
3837 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART10CLKSOURCE_LSE))
3838 {
3839 frequency = LSE_VALUE;
3840 }
3841 /* Clock not enabled for USART10 */
3842 else
3843 {
3844 frequency = 0U;
3845 }
3846 break;
3847 #endif /* USART10 */
3848
3849 #if defined(USART11)
3850 case RCC_PERIPHCLK_USART11:
3851 /* Get the current USART11 source */
3852 srcclk = __HAL_RCC_GET_USART11_SOURCE();
3853
3854 if (srcclk == RCC_USART11CLKSOURCE_PCLK1)
3855 {
3856 frequency = HAL_RCC_GetPCLK1Freq();
3857 }
3858 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_USART11CLKSOURCE_PLL2Q))
3859 {
3860 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3861 frequency = pll2_clocks.PLL2_Q_Frequency;
3862 }
3863 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_USART11CLKSOURCE_PLL3Q))
3864 {
3865 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3866 frequency = pll3_clocks.PLL3_Q_Frequency;
3867 }
3868 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART11CLKSOURCE_HSI))
3869 {
3870 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3871 }
3872 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_USART11CLKSOURCE_CSI))
3873 {
3874 frequency = CSI_VALUE;
3875 }
3876 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART11CLKSOURCE_LSE))
3877 {
3878 frequency = LSE_VALUE;
3879 }
3880 /* Clock not enabled for USART11 */
3881 else
3882 {
3883 frequency = 0U;
3884 }
3885 break;
3886 #endif /* USART11 */
3887
3888 #if defined(UART12)
3889 case RCC_PERIPHCLK_UART12:
3890 /* Get the current UART12 source */
3891 srcclk = __HAL_RCC_GET_UART12_SOURCE();
3892
3893 if (srcclk == RCC_UART12CLKSOURCE_PCLK1)
3894 {
3895 frequency = HAL_RCC_GetPCLK1Freq();
3896 }
3897 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_UART12CLKSOURCE_PLL2Q))
3898 {
3899 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3900 frequency = pll2_clocks.PLL2_Q_Frequency;
3901 }
3902 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_UART12CLKSOURCE_PLL3Q))
3903 {
3904 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3905 frequency = pll3_clocks.PLL3_Q_Frequency;
3906 }
3907 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART12CLKSOURCE_HSI))
3908 {
3909 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3910 }
3911 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_UART12CLKSOURCE_CSI))
3912 {
3913 frequency = CSI_VALUE;
3914 }
3915 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART12CLKSOURCE_LSE))
3916 {
3917 frequency = LSE_VALUE;
3918 }
3919 /* Clock not enabled for UART12 */
3920 else
3921 {
3922 frequency = 0U;
3923 }
3924 break;
3925 #endif /* UART12 */
3926
3927 case RCC_PERIPHCLK_LPUART1:
3928 /* Get the current LPUART1 source */
3929 srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
3930
3931 if (srcclk == RCC_LPUART1CLKSOURCE_PCLK3)
3932 {
3933 frequency = HAL_RCC_GetPCLK3Freq();
3934 }
3935 else if (srcclk == RCC_LPUART1CLKSOURCE_PLL2Q)
3936 {
3937 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3938 frequency = pll2_clocks.PLL2_Q_Frequency;
3939 }
3940 #if defined(RCC_LPUART1CLKSOURCE_PLL3Q)
3941 else if (srcclk == RCC_LPUART1CLKSOURCE_PLL3Q)
3942 {
3943 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3944 frequency = pll3_clocks.PLL3_Q_Frequency;
3945 }
3946 #endif /* RCC_LPUART1CLKSOURCE_PLL3Q */
3947 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_HSI))
3948 {
3949 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3950 }
3951 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_CSI))
3952 {
3953 frequency = CSI_VALUE;
3954 }
3955 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART1CLKSOURCE_LSE))
3956 {
3957 frequency = LSE_VALUE;
3958 }
3959 /* Clock not enabled for LPUART1 */
3960 else
3961 {
3962 frequency = 0U;
3963 }
3964 break;
3965
3966 case RCC_PERIPHCLK_ADCDAC:
3967 /* Get the current ADCDAC source */
3968 srcclk = __HAL_RCC_GET_ADCDAC_SOURCE();
3969
3970 if (srcclk == RCC_ADCDACCLKSOURCE_HCLK)
3971 {
3972 frequency = HAL_RCC_GetHCLKFreq();
3973 }
3974 else if (srcclk == RCC_ADCDACCLKSOURCE_SYSCLK)
3975 {
3976 frequency = HAL_RCC_GetSysClockFreq();
3977 }
3978 else if (srcclk == RCC_ADCDACCLKSOURCE_PLL2R)
3979 {
3980 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3981 frequency = pll2_clocks.PLL2_R_Frequency;
3982 }
3983 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSE))
3984 {
3985 frequency = HSE_VALUE;
3986 }
3987 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSI))
3988 {
3989 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3990 }
3991 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_ADCDACCLKSOURCE_CSI))
3992 {
3993 frequency = CSI_VALUE;
3994 }
3995 /* Clock not enabled for ADCDAC */
3996 else
3997 {
3998 frequency = 0U;
3999 }
4000 break;
4001
4002
4003 case RCC_PERIPHCLK_DAC_LP:
4004 /* Get the current DAC low-power source */
4005 srcclk = __HAL_RCC_GET_DAC_LP_SOURCE();
4006
4007 if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_DACLPCLKSOURCE_LSE))
4008 {
4009 frequency = LSE_VALUE;
4010 }
4011 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_DACLPCLKSOURCE_LSI))
4012 {
4013 frequency = LSI_VALUE;
4014 }
4015
4016 /* Clock not enabled for DAC */
4017 else
4018 {
4019 frequency = 0U;
4020 }
4021 break;
4022
4023 case RCC_PERIPHCLK_I2C1:
4024 /* Get the current I2C1 source */
4025 srcclk = __HAL_RCC_GET_I2C1_SOURCE();
4026
4027 if (srcclk == RCC_I2C1CLKSOURCE_PCLK1)
4028 {
4029 frequency = HAL_RCC_GetPCLK1Freq();
4030 }
4031 #if defined(RCC_I2C1CLKSOURCE_PLL3R)
4032 else if (srcclk == RCC_I2C1CLKSOURCE_PLL3R)
4033 {
4034 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4035 frequency = pll3_clocks.PLL3_R_Frequency;
4036 }
4037 #else
4038 else if (srcclk == RCC_I2C1CLKSOURCE_PLL2R)
4039 {
4040 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4041 frequency = pll2_clocks.PLL2_R_Frequency;
4042 }
4043 #endif /* RCC_I2C1CLKSOURCE_PLL3R */
4044 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_HSI))
4045 {
4046 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4047 }
4048 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_CSI))
4049 {
4050 frequency = CSI_VALUE;
4051 }
4052 /* Clock not enabled for I2C1 */
4053 else
4054 {
4055 frequency = 0U;
4056 }
4057 break;
4058
4059 case RCC_PERIPHCLK_I2C2:
4060 /* Get the current I2C2 source */
4061 srcclk = __HAL_RCC_GET_I2C2_SOURCE();
4062
4063 if (srcclk == RCC_I2C2CLKSOURCE_PCLK1)
4064 {
4065 frequency = HAL_RCC_GetPCLK1Freq();
4066 }
4067 #if defined(RCC_I2C2CLKSOURCE_PLL3R)
4068 else if (srcclk == RCC_I2C2CLKSOURCE_PLL3R)
4069 {
4070 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4071 frequency = pll3_clocks.PLL3_R_Frequency;
4072 }
4073 #else
4074 else if (srcclk == RCC_I2C2CLKSOURCE_PLL2R)
4075 {
4076 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4077 frequency = pll2_clocks.PLL2_R_Frequency;
4078 }
4079 #endif /* RCC_I2C2CLKSOURCE_PLL3R */
4080 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_HSI))
4081 {
4082 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4083 }
4084 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_CSI))
4085 {
4086 frequency = CSI_VALUE;
4087 }
4088 /* Clock not enabled for I2C2 */
4089 else
4090 {
4091 frequency = 0U;
4092 }
4093 break;
4094
4095 #if defined(I2C3)
4096 case RCC_PERIPHCLK_I2C3:
4097 /* Get the current I2C3 source */
4098 srcclk = __HAL_RCC_GET_I2C3_SOURCE();
4099
4100 if (srcclk == RCC_I2C3CLKSOURCE_PCLK3)
4101 {
4102 frequency = HAL_RCC_GetPCLK3Freq();
4103 }
4104 else if (srcclk == RCC_I2C3CLKSOURCE_PLL3R)
4105 {
4106 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4107 frequency = pll3_clocks.PLL3_R_Frequency;
4108 }
4109 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C3CLKSOURCE_HSI))
4110 {
4111 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4112 }
4113 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_I2C3CLKSOURCE_CSI))
4114 {
4115 frequency = CSI_VALUE;
4116 }
4117 /* Clock not enabled for I2C3 */
4118 else
4119 {
4120 frequency = 0U;
4121 }
4122 break;
4123 #endif /* I2C3 */
4124
4125 #if defined(I2C4)
4126 case RCC_PERIPHCLK_I2C4:
4127 /* Get the current I2C4 source */
4128 srcclk = __HAL_RCC_GET_I2C4_SOURCE();
4129
4130 if (srcclk == RCC_I2C4CLKSOURCE_PCLK3)
4131 {
4132 frequency = HAL_RCC_GetPCLK3Freq();
4133 }
4134 else if (srcclk == RCC_I2C4CLKSOURCE_PLL3R)
4135 {
4136 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4137 frequency = pll3_clocks.PLL3_R_Frequency;
4138 }
4139 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C4CLKSOURCE_HSI))
4140 {
4141 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4142 }
4143 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_I2C4CLKSOURCE_CSI))
4144 {
4145 frequency = CSI_VALUE;
4146 }
4147 /* Clock not enabled for I2C4 */
4148 else
4149 {
4150 frequency = 0U;
4151 }
4152 break;
4153 #endif /* I2C4 */
4154
4155 case RCC_PERIPHCLK_I3C1:
4156 /* Get the current I3C1 source */
4157 srcclk = __HAL_RCC_GET_I3C1_SOURCE();
4158
4159 if (srcclk == RCC_I3C1CLKSOURCE_PCLK1)
4160 {
4161 frequency = HAL_RCC_GetPCLK1Freq();
4162 }
4163 #if defined(RCC_I3C1CLKSOURCE_PLL3R)
4164 else if (srcclk == RCC_I3C1CLKSOURCE_PLL3R)
4165 {
4166 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4167 frequency = pll3_clocks.PLL3_R_Frequency;
4168 }
4169 #else
4170 else if (srcclk == RCC_I3C1CLKSOURCE_PLL2R)
4171 {
4172 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4173 frequency = pll2_clocks.PLL2_R_Frequency;
4174 }
4175 #endif /* RCC_I3C1CLKSOURCE_PLL3R */
4176 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I3C1CLKSOURCE_HSI))
4177 {
4178 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4179 }
4180 /* Clock not enabled for I3C1 */
4181 else
4182 {
4183 frequency = 0U;
4184 }
4185 break;
4186
4187 #if defined(I3C2)
4188 case RCC_PERIPHCLK_I3C2:
4189 /* Get the current I3C2 source */
4190 srcclk = __HAL_RCC_GET_I3C2_SOURCE();
4191 if (srcclk == RCC_I3C2CLKSOURCE_PCLK3)
4192 {
4193 frequency = HAL_RCC_GetPCLK3Freq();
4194 }
4195 #if defined(RCC_I3C1CLKSOURCE_PLL3R)
4196 else if (srcclk == RCC_I3C2CLKSOURCE_PLL3R)
4197 {
4198 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4199 frequency = pll3_clocks.PLL3_R_Frequency;
4200 }
4201 #else
4202 else if (srcclk == RCC_I3C2CLKSOURCE_PLL2R)
4203 {
4204 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4205 frequency = pll2_clocks.PLL2_R_Frequency;
4206 }
4207 #endif /* RCC_I3C1CLKSOURCE_PLL3R */
4208 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I3C2CLKSOURCE_HSI))
4209 {
4210 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4211 }
4212 #if defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx)
4213 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_I3C2CLKSOURCE_CSI))
4214 {
4215 frequency = CSI_VALUE;
4216 }
4217 #endif /* defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) */
4218 /* Clock not enabled for I3C2 */
4219 else
4220 {
4221 frequency = 0U;
4222 }
4223 break;
4224 #endif /* I3C2*/
4225
4226 case RCC_PERIPHCLK_LPTIM1:
4227 /* Get the current LPTIM1 source */
4228 srcclk = __HAL_RCC_GET_LPTIM1_SOURCE();
4229
4230 switch (srcclk)
4231 {
4232 case RCC_LPTIM1CLKSOURCE_PCLK3:
4233 {
4234 frequency = HAL_RCC_GetPCLK3Freq();
4235 break;
4236 }
4237 case RCC_LPTIM1CLKSOURCE_PLL2P:
4238 {
4239 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4240 frequency = pll2_clocks.PLL2_P_Frequency;
4241 break;
4242 }
4243 #if defined(RCC_LPTIM1CLKSOURCE_PLL3R)
4244 case RCC_LPTIM1CLKSOURCE_PLL3R:
4245 {
4246 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4247 frequency = pll3_clocks.PLL3_R_Frequency;
4248 break;
4249 }
4250 #endif /* RCC_LPTIM1CLKSOURCE_PLL3R */
4251 case RCC_LPTIM1CLKSOURCE_LSE:
4252 {
4253 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
4254 {
4255 frequency = LSE_VALUE;
4256 }
4257 else
4258 {
4259 frequency = 0;
4260 }
4261 break;
4262 }
4263 case RCC_LPTIM1CLKSOURCE_LSI:
4264 {
4265 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY))
4266 {
4267 frequency = LSI_VALUE;
4268 }
4269 else
4270 {
4271 frequency = 0;
4272 }
4273 break;
4274 }
4275 case RCC_LPTIM1CLKSOURCE_CLKP: /* CLKP is the clock source for LPTIM1 */
4276 {
4277 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
4278
4279 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
4280 {
4281 /* In Case the CKPER Source is HSI */
4282 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4283 }
4284
4285 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
4286 {
4287 /* In Case the CKPER Source is CSI */
4288 frequency = CSI_VALUE;
4289 }
4290
4291 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
4292 {
4293 /* In Case the CKPER Source is HSE */
4294 frequency = HSE_VALUE;
4295 }
4296
4297 else
4298 {
4299 /* In Case the CKPER is disabled*/
4300 frequency = 0;
4301 }
4302
4303 break;
4304 }
4305 default :
4306 {
4307 frequency = 0U;
4308 break;
4309 }
4310 }
4311 break;
4312
4313 case RCC_PERIPHCLK_LPTIM2:
4314 /* Get the current LPTIM2 source */
4315 srcclk = __HAL_RCC_GET_LPTIM2_SOURCE();
4316
4317 switch (srcclk)
4318 {
4319 case RCC_LPTIM2CLKSOURCE_PCLK1:
4320 {
4321 frequency = HAL_RCC_GetPCLK1Freq();
4322 break;
4323 }
4324 case RCC_LPTIM2CLKSOURCE_PLL2P:
4325 {
4326 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4327 frequency = pll2_clocks.PLL2_P_Frequency;
4328 break;
4329 }
4330 #if defined(RCC_LPTIM2CLKSOURCE_PLL3R)
4331 case RCC_LPTIM2CLKSOURCE_PLL3R:
4332 {
4333 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4334 frequency = pll3_clocks.PLL3_R_Frequency;
4335 break;
4336 }
4337 #endif /* RCC_LPTIM2CLKSOURCE_PLL3R */
4338 case RCC_LPTIM2CLKSOURCE_LSE:
4339 {
4340 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
4341 {
4342 frequency = LSE_VALUE;
4343 }
4344 else
4345 {
4346 frequency = 0;
4347 }
4348 break;
4349 }
4350 case RCC_LPTIM2CLKSOURCE_LSI:
4351 {
4352 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY))
4353 {
4354 frequency = LSI_VALUE;
4355 }
4356 else
4357 {
4358 frequency = 0;
4359 }
4360 break;
4361 }
4362 case RCC_LPTIM2CLKSOURCE_CLKP: /* CLKP is the clock source for LPTIM2 */
4363 {
4364 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
4365
4366 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
4367 {
4368 /* In Case the CKPER Source is HSI */
4369 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4370 }
4371
4372 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
4373 {
4374 /* In Case the CKPER Source is CSI */
4375 frequency = CSI_VALUE;
4376 }
4377
4378 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
4379 {
4380 /* In Case the CKPER Source is HSE */
4381 frequency = HSE_VALUE;
4382 }
4383
4384 else
4385 {
4386 /* In Case the CKPER is disabled*/
4387 frequency = 0;
4388 }
4389
4390 break;
4391 }
4392 default :
4393 {
4394 frequency = 0U;
4395 break;
4396 }
4397 }
4398 break;
4399
4400 #if defined(LPTIM3)
4401 case RCC_PERIPHCLK_LPTIM3:
4402 /* Get the current LPTIM3 source */
4403 srcclk = __HAL_RCC_GET_LPTIM3_SOURCE();
4404
4405 switch (srcclk)
4406 {
4407 case RCC_LPTIM3CLKSOURCE_PCLK3:
4408 {
4409 frequency = HAL_RCC_GetPCLK3Freq();
4410 break;
4411 }
4412 case RCC_LPTIM3CLKSOURCE_PLL2P:
4413 {
4414 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4415 frequency = pll2_clocks.PLL2_P_Frequency;
4416 break;
4417 }
4418 case RCC_LPTIM3CLKSOURCE_PLL3R:
4419 {
4420 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4421 frequency = pll3_clocks.PLL3_R_Frequency;
4422 break;
4423 }
4424 case RCC_LPTIM3CLKSOURCE_LSE:
4425 {
4426 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
4427 {
4428 frequency = LSE_VALUE;
4429 }
4430 else
4431 {
4432 frequency = 0;
4433 }
4434 break;
4435 }
4436 case RCC_LPTIM3CLKSOURCE_LSI:
4437 {
4438 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY))
4439 {
4440 frequency = LSI_VALUE;
4441 }
4442 else
4443 {
4444 frequency = 0;
4445 }
4446 break;
4447 }
4448 case RCC_LPTIM3CLKSOURCE_CLKP: /* CLKP is the clock source for LPTIM3 */
4449 {
4450 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
4451
4452 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
4453 {
4454 /* In Case the CKPER Source is HSI */
4455 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4456 }
4457
4458 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
4459 {
4460 /* In Case the CKPER Source is CSI */
4461 frequency = CSI_VALUE;
4462 }
4463
4464 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
4465 {
4466 /* In Case the CKPER Source is HSE */
4467 frequency = HSE_VALUE;
4468 }
4469
4470 else
4471 {
4472 /* In Case the CKPER is disabled*/
4473 frequency = 0;
4474 }
4475
4476 break;
4477 }
4478 default :
4479 {
4480 frequency = 0U;
4481 break;
4482 }
4483 }
4484 break;
4485 #endif /* LPTIM3 */
4486
4487 #if defined(LPTIM4)
4488 case RCC_PERIPHCLK_LPTIM4:
4489 /* Get the current LPTIM4 source */
4490 srcclk = __HAL_RCC_GET_LPTIM4_SOURCE();
4491
4492 switch (srcclk)
4493 {
4494 case RCC_LPTIM4CLKSOURCE_PCLK3:
4495 {
4496 frequency = HAL_RCC_GetPCLK3Freq();
4497 break;
4498 }
4499 case RCC_LPTIM4CLKSOURCE_PLL2P:
4500 {
4501 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4502 frequency = pll2_clocks.PLL2_P_Frequency;
4503 break;
4504 }
4505 case RCC_LPTIM4CLKSOURCE_PLL3R:
4506 {
4507 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4508 frequency = pll3_clocks.PLL3_R_Frequency;
4509 break;
4510 }
4511 case RCC_LPTIM4CLKSOURCE_LSE:
4512 {
4513 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
4514 {
4515 frequency = LSE_VALUE;
4516 }
4517 else
4518 {
4519 frequency = 0;
4520 }
4521 break;
4522 }
4523 case RCC_LPTIM4CLKSOURCE_LSI:
4524 {
4525 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY))
4526 {
4527 frequency = LSI_VALUE;
4528 }
4529 else
4530 {
4531 frequency = 0;
4532 }
4533 break;
4534 }
4535 case RCC_LPTIM4CLKSOURCE_CLKP: /* CLKP is the clock source for LPTIM4 */
4536 {
4537 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
4538
4539 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
4540 {
4541 /* In Case the CKPER Source is HSI */
4542 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4543 }
4544
4545 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
4546 {
4547 /* In Case the CKPER Source is CSI */
4548 frequency = CSI_VALUE;
4549 }
4550
4551 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
4552 {
4553 /* In Case the CKPER Source is HSE */
4554 frequency = HSE_VALUE;
4555 }
4556
4557 else
4558 {
4559 /* In Case the CKPER is disabled*/
4560 frequency = 0;
4561 }
4562
4563 break;
4564 }
4565 default :
4566 {
4567 frequency = 0U;
4568 break;
4569 }
4570 }
4571 break;
4572 #endif /* LPTIM4 */
4573
4574 #if defined(LPTIM5)
4575 case RCC_PERIPHCLK_LPTIM5:
4576 /* Get the current LPTIM5 source */
4577 srcclk = __HAL_RCC_GET_LPTIM5_SOURCE();
4578
4579 switch (srcclk)
4580 {
4581 case RCC_LPTIM5CLKSOURCE_PCLK3:
4582 {
4583 frequency = HAL_RCC_GetPCLK3Freq();
4584 break;
4585 }
4586 case RCC_LPTIM5CLKSOURCE_PLL2P:
4587 {
4588 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4589 frequency = pll2_clocks.PLL2_P_Frequency;
4590 break;
4591 }
4592 case RCC_LPTIM5CLKSOURCE_PLL3R:
4593 {
4594 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4595 frequency = pll3_clocks.PLL3_R_Frequency;
4596 break;
4597 }
4598 case RCC_LPTIM5CLKSOURCE_LSE:
4599 {
4600 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
4601 {
4602 frequency = LSE_VALUE;
4603 }
4604 else
4605 {
4606 frequency = 0;
4607 }
4608 break;
4609 }
4610 case RCC_LPTIM5CLKSOURCE_LSI:
4611 {
4612 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY))
4613 {
4614 frequency = LSI_VALUE;
4615 }
4616 else
4617 {
4618 frequency = 0;
4619 }
4620 break;
4621 }
4622 case RCC_LPTIM5CLKSOURCE_CLKP: /* CLKP is the clock source for LPTIM5 */
4623 {
4624 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
4625
4626 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
4627 {
4628 /* In Case the CKPER Source is HSI */
4629 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4630 }
4631
4632 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
4633 {
4634 /* In Case the CKPER Source is CSI */
4635 frequency = CSI_VALUE;
4636 }
4637
4638 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
4639 {
4640 /* In Case the CKPER Source is HSE */
4641 frequency = HSE_VALUE;
4642 }
4643
4644 else
4645 {
4646 /* In Case the CKPER is disabled*/
4647 frequency = 0;
4648 }
4649
4650 break;
4651 }
4652 default :
4653 {
4654 frequency = 0U;
4655 break;
4656 }
4657 }
4658 break;
4659 #endif /* LPTIM5 */
4660
4661 #if defined(LPTIM6)
4662 case RCC_PERIPHCLK_LPTIM6:
4663 /* Get the current LPTIM6 source */
4664 srcclk = __HAL_RCC_GET_LPTIM6_SOURCE();
4665
4666 switch (srcclk)
4667 {
4668 case RCC_LPTIM6CLKSOURCE_PCLK3:
4669 {
4670 frequency = HAL_RCC_GetPCLK3Freq();
4671 break;
4672 }
4673 case RCC_LPTIM6CLKSOURCE_PLL2P:
4674 {
4675 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4676 frequency = pll2_clocks.PLL2_P_Frequency;
4677 break;
4678 }
4679 case RCC_LPTIM6CLKSOURCE_PLL3R:
4680 {
4681 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4682 frequency = pll3_clocks.PLL3_R_Frequency;
4683 break;
4684 }
4685 case RCC_LPTIM6CLKSOURCE_LSE:
4686 {
4687 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
4688 {
4689 frequency = LSE_VALUE;
4690 }
4691 else
4692 {
4693 frequency = 0;
4694 }
4695 break;
4696 }
4697 case RCC_LPTIM6CLKSOURCE_LSI:
4698 {
4699 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY))
4700 {
4701 frequency = LSI_VALUE;
4702 }
4703 else
4704 {
4705 frequency = 0;
4706 }
4707 break;
4708 }
4709 case RCC_LPTIM6CLKSOURCE_CLKP: /* CLKP is the clock source for LPTIM6 */
4710 {
4711 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
4712
4713 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
4714 {
4715 /* In Case the CKPER Source is HSI */
4716 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4717 }
4718
4719 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
4720 {
4721 /* In Case the CKPER Source is CSI */
4722 frequency = CSI_VALUE;
4723 }
4724
4725 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
4726 {
4727 /* In Case the CKPER Source is HSE */
4728 frequency = HSE_VALUE;
4729 }
4730
4731 else
4732 {
4733 /* In Case the CKPER is disabled*/
4734 frequency = 0;
4735 }
4736
4737 break;
4738 }
4739 default :
4740 {
4741 frequency = 0U;
4742 break;
4743 }
4744 }
4745 break;
4746 #endif /* LPTIM6 */
4747
4748 case RCC_PERIPHCLK_FDCAN:
4749 /* Get the current FDCAN kernel source */
4750 srcclk = __HAL_RCC_GET_FDCAN_SOURCE();
4751
4752 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_FDCANCLKSOURCE_HSE))
4753 {
4754 frequency = HSE_VALUE;
4755 }
4756 else if (srcclk == RCC_FDCANCLKSOURCE_PLL1Q)
4757 {
4758 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
4759 frequency = pll1_clocks.PLL1_Q_Frequency;
4760 }
4761 else if (srcclk == RCC_FDCANCLKSOURCE_PLL2Q)
4762 {
4763 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4764 frequency = pll2_clocks.PLL2_Q_Frequency;
4765 }
4766 /* Clock not enabled for FDCAN */
4767 else
4768 {
4769 frequency = 0U;
4770 }
4771 break;
4772
4773 case RCC_PERIPHCLK_SPI1:
4774 /* Get the current SPI1 kernel source */
4775 srcclk = __HAL_RCC_GET_SPI1_SOURCE();
4776 switch (srcclk)
4777 {
4778 case RCC_SPI1CLKSOURCE_PLL1Q:
4779 {
4780 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
4781 frequency = pll1_clocks.PLL1_Q_Frequency;
4782 break;
4783 }
4784 case RCC_SPI1CLKSOURCE_PLL2P:
4785 {
4786 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4787 frequency = pll2_clocks.PLL2_P_Frequency;
4788 break;
4789 }
4790 #if defined(RCC_SPI1CLKSOURCE_PLL3P)
4791 case RCC_SPI1CLKSOURCE_PLL3P:
4792 {
4793 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4794 frequency = pll3_clocks.PLL3_P_Frequency;
4795 break;
4796 }
4797 #endif /* RCC_SPI1CLKSOURCE_PLL3P */
4798 case RCC_SPI1CLKSOURCE_PIN:
4799 {
4800 frequency = EXTERNAL_CLOCK_VALUE;
4801 break;
4802 }
4803 case RCC_SPI1CLKSOURCE_CLKP:
4804 {
4805 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
4806
4807 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
4808 {
4809 /* In Case the CKPER Source is HSI */
4810 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4811 }
4812
4813 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
4814 {
4815 /* In Case the CKPER Source is CSI */
4816 frequency = CSI_VALUE;
4817 }
4818
4819 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
4820 {
4821 /* In Case the CKPER Source is HSE */
4822 frequency = HSE_VALUE;
4823 }
4824
4825 else
4826 {
4827 /* In Case the CKPER is disabled*/
4828 frequency = 0;
4829 }
4830
4831 break;
4832 }
4833 default:
4834 {
4835 frequency = 0;
4836 break;
4837 }
4838 }
4839 break;
4840
4841 case RCC_PERIPHCLK_SPI2:
4842 /* Get the current SPI2 kernel source */
4843 srcclk = __HAL_RCC_GET_SPI2_SOURCE();
4844 switch (srcclk)
4845 {
4846 case RCC_SPI2CLKSOURCE_PLL1Q:
4847 {
4848 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
4849 frequency = pll1_clocks.PLL1_Q_Frequency;
4850 break;
4851 }
4852 case RCC_SPI2CLKSOURCE_PLL2P:
4853 {
4854 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4855 frequency = pll2_clocks.PLL2_P_Frequency;
4856 break;
4857 }
4858 #if defined(RCC_SPI2CLKSOURCE_PLL3P)
4859 case RCC_SPI2CLKSOURCE_PLL3P:
4860 {
4861 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4862 frequency = pll3_clocks.PLL3_P_Frequency;
4863 break;
4864 }
4865 #endif /* RCC_SPI2CLKSOURCE_PLL3P */
4866 case RCC_SPI2CLKSOURCE_PIN:
4867 {
4868 frequency = EXTERNAL_CLOCK_VALUE;
4869 break;
4870 }
4871 case RCC_SPI2CLKSOURCE_CLKP:
4872 {
4873 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
4874
4875 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
4876 {
4877 /* In Case the CKPER Source is HSI */
4878 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4879 }
4880
4881 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
4882 {
4883 /* In Case the CKPER Source is CSI */
4884 frequency = CSI_VALUE;
4885 }
4886
4887 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
4888 {
4889 /* In Case the CKPER Source is HSE */
4890 frequency = HSE_VALUE;
4891 }
4892
4893 else
4894 {
4895 /* In Case the CKPER is disabled*/
4896 frequency = 0;
4897 }
4898
4899 break;
4900 }
4901 default:
4902 {
4903 frequency = 0;
4904 break;
4905 }
4906 }
4907 break;
4908
4909 case RCC_PERIPHCLK_SPI3:
4910 /* Get the current SPI3 kernel source */
4911 srcclk = __HAL_RCC_GET_SPI3_SOURCE();
4912 switch (srcclk)
4913 {
4914 case RCC_SPI3CLKSOURCE_PLL1Q:
4915 {
4916 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
4917 frequency = pll1_clocks.PLL1_Q_Frequency;
4918 break;
4919 }
4920 case RCC_SPI3CLKSOURCE_PLL2P:
4921 {
4922 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4923 frequency = pll2_clocks.PLL2_P_Frequency;
4924 break;
4925 }
4926 #if defined(RCC_SPI3CLKSOURCE_PLL3P)
4927 case RCC_SPI3CLKSOURCE_PLL3P:
4928 {
4929 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4930 frequency = pll3_clocks.PLL3_P_Frequency;
4931 break;
4932 }
4933 #endif /* RCC_SPI3CLKSOURCE_PLL3P */
4934 case RCC_SPI3CLKSOURCE_PIN:
4935 {
4936 frequency = EXTERNAL_CLOCK_VALUE;
4937 break;
4938 }
4939 case RCC_SPI3CLKSOURCE_CLKP:
4940 {
4941 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
4942
4943 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
4944 {
4945 /* In Case the CKPER Source is HSI */
4946 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4947 }
4948
4949 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
4950 {
4951 /* In Case the CKPER Source is CSI */
4952 frequency = CSI_VALUE;
4953 }
4954
4955 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
4956 {
4957 /* In Case the CKPER Source is HSE */
4958 frequency = HSE_VALUE;
4959 }
4960
4961 else
4962 {
4963 /* In Case the CKPER is disabled*/
4964 frequency = 0;
4965 }
4966
4967 break;
4968 }
4969 default:
4970 {
4971 frequency = 0;
4972 break;
4973 }
4974 }
4975 break;
4976
4977 #if defined(SPI4)
4978 case RCC_PERIPHCLK_SPI4:
4979 /* Get the current SPI4 kernel source */
4980 srcclk = __HAL_RCC_GET_SPI4_SOURCE();
4981
4982 if (srcclk == RCC_SPI4CLKSOURCE_PCLK2)
4983 {
4984 frequency = HAL_RCC_GetPCLK2Freq();
4985 }
4986 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_SPI4CLKSOURCE_PLL2Q))
4987 {
4988 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4989 frequency = pll2_clocks.PLL2_Q_Frequency;
4990 }
4991 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_SPI4CLKSOURCE_PLL3Q))
4992 {
4993 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4994 frequency = pll3_clocks.PLL3_Q_Frequency;
4995 }
4996 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_SPI4CLKSOURCE_HSI))
4997 {
4998 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4999 }
5000 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_SPI4CLKSOURCE_CSI))
5001 {
5002 frequency = CSI_VALUE;
5003 }
5004 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_SPI4CLKSOURCE_HSE))
5005 {
5006 frequency = HSE_VALUE;
5007 }
5008 /* Clock not enabled for SPI4 */
5009 else
5010 {
5011 frequency = 0U;
5012 }
5013
5014 break;
5015 #endif /* SPI4 */
5016
5017 #if defined(SPI5)
5018 case RCC_PERIPHCLK_SPI5:
5019 /* Get the current SPI5 kernel source */
5020 srcclk = __HAL_RCC_GET_SPI5_SOURCE();
5021
5022 if (srcclk == RCC_SPI5CLKSOURCE_PCLK3)
5023 {
5024 frequency = HAL_RCC_GetPCLK3Freq();
5025 }
5026 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_SPI5CLKSOURCE_PLL2Q))
5027 {
5028 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
5029 frequency = pll2_clocks.PLL2_Q_Frequency;
5030 }
5031 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_SPI5CLKSOURCE_PLL3Q))
5032 {
5033 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
5034 frequency = pll3_clocks.PLL3_Q_Frequency;
5035 }
5036 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_SPI5CLKSOURCE_HSI))
5037 {
5038 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
5039 }
5040 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_SPI5CLKSOURCE_CSI))
5041 {
5042 frequency = CSI_VALUE;
5043 }
5044 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_SPI5CLKSOURCE_HSE))
5045 {
5046 frequency = HSE_VALUE;
5047 }
5048 /* Clock not enabled for SPI5 */
5049 else
5050 {
5051 frequency = 0U;
5052 }
5053
5054 break;
5055 #endif /* SPI5 */
5056
5057 #if defined(SPI6)
5058 case RCC_PERIPHCLK_SPI6:
5059 /* Get the current SPI6 kernel source */
5060 srcclk = __HAL_RCC_GET_SPI6_SOURCE();
5061
5062 if (srcclk == RCC_SPI6CLKSOURCE_PCLK2)
5063 {
5064 frequency = HAL_RCC_GetPCLK2Freq();
5065 }
5066 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_SPI6CLKSOURCE_PLL2Q))
5067 {
5068 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
5069 frequency = pll2_clocks.PLL2_Q_Frequency;
5070 }
5071 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_SPI6CLKSOURCE_PLL3Q))
5072 {
5073 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
5074 frequency = pll3_clocks.PLL3_Q_Frequency;
5075 }
5076 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_SPI6CLKSOURCE_HSI))
5077 {
5078 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
5079 }
5080 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_SPI6CLKSOURCE_CSI))
5081 {
5082 frequency = CSI_VALUE;
5083 }
5084 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_SPI6CLKSOURCE_HSE))
5085 {
5086 frequency = HSE_VALUE;
5087 }
5088 /* Clock not enabled for SPI6 */
5089 else
5090 {
5091 frequency = 0U;
5092 }
5093
5094 break;
5095 #endif /* SPI6 */
5096
5097 #if defined(OCTOSPI1)
5098 case RCC_PERIPHCLK_OSPI:
5099 /* Get the current OSPI kernel source */
5100 srcclk = __HAL_RCC_GET_OSPI_SOURCE();
5101
5102 switch (srcclk)
5103 {
5104 case RCC_OSPICLKSOURCE_HCLK:
5105 {
5106 frequency = HAL_RCC_GetHCLKFreq();
5107 break;
5108 }
5109 case RCC_OSPICLKSOURCE_PLL1Q:
5110 {
5111 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
5112 frequency = pll1_clocks.PLL1_Q_Frequency;
5113 break;
5114 }
5115 case RCC_OSPICLKSOURCE_PLL2R:
5116 {
5117 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
5118 frequency = pll2_clocks.PLL2_R_Frequency;
5119 break;
5120 }
5121 case RCC_OSPICLKSOURCE_CLKP:
5122 {
5123 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
5124
5125 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
5126 {
5127 /* In Case the CKPER Source is HSI */
5128 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
5129 }
5130
5131 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
5132 {
5133 /* In Case the CKPER Source is CSI */
5134 frequency = CSI_VALUE;
5135 }
5136
5137 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
5138 {
5139 /* In Case the CKPER Source is HSE */
5140 frequency = HSE_VALUE;
5141 }
5142
5143 else
5144 {
5145 /* In Case the CKPER is disabled*/
5146 frequency = 0U;
5147 }
5148
5149 break;
5150 }
5151 default:
5152 {
5153 frequency = 0U;
5154 break;
5155 }
5156 }
5157 break;
5158 #endif /* OCTOSPI1*/
5159
5160 #if defined(CEC)
5161 case RCC_PERIPHCLK_CEC:
5162 /* Get the current CEC source */
5163 srcclk = __HAL_RCC_GET_CEC_SOURCE();
5164
5165 if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_CECCLKSOURCE_LSE))
5166 {
5167 frequency = LSE_VALUE;
5168 }
5169 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_CECCLKSOURCE_LSI))
5170 {
5171 frequency = LSI_VALUE;
5172 }
5173 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_CECCLKSOURCE_CSI_DIV122))
5174 {
5175 frequency = CSI_VALUE / 122U;
5176 }
5177
5178 /* Clock not enabled for CEC */
5179 else
5180 {
5181 frequency = 0U;
5182 }
5183 break;
5184 #endif /* CEC */
5185
5186 case RCC_PERIPHCLK_RNG:
5187 /* Get the current RNG source */
5188 srcclk = __HAL_RCC_GET_RNG_SOURCE();
5189
5190 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI48))
5191 {
5192 frequency = HSI48_VALUE;
5193 }
5194 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) && (srcclk == RCC_RNGCLKSOURCE_PLL1Q))
5195 {
5196 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
5197 frequency = pll1_clocks.PLL1_Q_Frequency;
5198 }
5199 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_RNGCLKSOURCE_LSE))
5200 {
5201 frequency = LSE_VALUE;
5202 }
5203 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_RNGCLKSOURCE_LSI))
5204 {
5205 frequency = LSI_VALUE;
5206 }
5207
5208 /* Clock not enabled for RNG */
5209 else
5210 {
5211 frequency = 0U;
5212 }
5213 break;
5214
5215 #if defined(USB_DRD_FS)
5216 case RCC_PERIPHCLK_USB:
5217 /* Get the current USB kernel source */
5218 srcclk = __HAL_RCC_GET_USB_SOURCE();
5219
5220 if (srcclk == RCC_USBCLKSOURCE_PLL1Q)
5221 {
5222 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
5223 frequency = pll1_clocks.PLL1_Q_Frequency;
5224 break;
5225 }
5226 #if defined(RCC_USBCLKSOURCE_PLL3Q)
5227 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_USBCLKSOURCE_PLL3Q))
5228 {
5229 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
5230 frequency = pll3_clocks.PLL3_Q_Frequency;
5231 }
5232 #else
5233 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_USBCLKSOURCE_PLL2Q))
5234 {
5235 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
5236 frequency = pll2_clocks.PLL2_Q_Frequency;
5237 }
5238 #endif /* RCC_USBCLKSOURCE_PLL3 */
5239 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) && (srcclk == RCC_USBCLKSOURCE_HSI48))
5240 {
5241 frequency = HSI48_VALUE;
5242 }
5243 /* Clock not enabled for USB */
5244 else
5245 {
5246 frequency = 0U;
5247 }
5248
5249 break;
5250
5251
5252 default:
5253 frequency = 0U;
5254 break;
5255 #endif /* USB_DRD_FS */
5256 }
5257 }
5258 return (frequency);
5259 }
5260
5261 /**
5262 * @}
5263 */
5264
5265 /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
5266 * @brief Extended Clock management functions
5267 *
5268 @verbatim
5269 ===============================================================================
5270 ##### Extended clock management functions #####
5271 ===============================================================================
5272 [..]
5273 This subsection provides a set of functions allowing to control the
5274 activation or deactivation of PLL2, PLL3, LSE CSS,
5275 Low speed clock output and clock after wake-up from STOP mode.
5276 @endverbatim
5277 * @{
5278 */
5279
5280 /**
5281 * @brief Initialize and Enable the PLL2 according to the specified
5282 * parameters in the RCC_PLL2InitTypeDef.
5283 * @param pPLL2Init pointer to an RCC_PLL2InitTypeDef structure that
5284 * contains the configuration information for the PLL2
5285 * @retval HAL status
5286 */
HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef * pPLL2Init)5287 HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *pPLL2Init)
5288 {
5289 uint32_t tickstart;
5290 HAL_StatusTypeDef status = HAL_OK;
5291
5292 /* check for PLL2 Parameters used to output PLL2CLK */
5293 assert_param(IS_RCC_PLL2_SOURCE(pPLL2Init->PLL2Source));
5294 assert_param(IS_RCC_PLL2_DIVM_VALUE(pPLL2Init->PLL2M));
5295 assert_param(IS_RCC_PLL2_MULN_VALUE(pPLL2Init->PLL2N));
5296 assert_param(IS_RCC_PLL2_DIVP_VALUE(pPLL2Init->PLL2P));
5297 assert_param(IS_RCC_PLL2_DIVQ_VALUE(pPLL2Init->PLL2Q));
5298 assert_param(IS_RCC_PLL2_DIVR_VALUE(pPLL2Init->PLL2R));
5299 assert_param(IS_RCC_PLL2_CLOCKOUT_VALUE(pPLL2Init->PLL2ClockOut));
5300 assert_param(IS_RCC_PLL2_VCIRGE_VALUE(pPLL2Init->PLL2RGE));
5301 assert_param(IS_RCC_PLL2_VCORGE_VALUE(pPLL2Init->PLL2VCOSEL));
5302 assert_param(IS_RCC_PLL2_FRACN_VALUE(pPLL2Init->PLL2FRACN));
5303
5304 /* Disable the PLL2 */
5305 __HAL_RCC_PLL2_DISABLE();
5306
5307 /* Get Start Tick*/
5308 tickstart = HAL_GetTick();
5309
5310 /* Wait till PLL2 is ready to be updated */
5311 while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U)
5312 {
5313 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
5314 {
5315 status = HAL_TIMEOUT;
5316 break;
5317 }
5318 }
5319
5320 if (status == HAL_OK)
5321 {
5322 /* Make sure PLL2Source is ready */
5323 status = RCCEx_PLLSource_Enable(pPLL2Init->PLL2Source);
5324
5325 if (status == HAL_OK)
5326 {
5327 /* Configure the PLL2 clock source, multiplication factor N, */
5328 /* and division factors M, P, Q and R */
5329 __HAL_RCC_PLL2_CONFIG(pPLL2Init->PLL2Source, pPLL2Init->PLL2M, pPLL2Init->PLL2N,
5330 pPLL2Init->PLL2P, pPLL2Init->PLL2Q, pPLL2Init->PLL2R);
5331
5332 /* Disable PLL2FRACN . */
5333 __HAL_RCC_PLL2_FRACN_DISABLE();
5334
5335 /* Configure PLL2 FRACN */
5336 __HAL_RCC_PLL2_FRACN_CONFIG(pPLL2Init->PLL2FRACN);
5337
5338 /* Enable PLL2FRACN */
5339 __HAL_RCC_PLL2_FRACN_ENABLE();
5340
5341 /* Select PLL2 input reference frequency range: VCI */
5342 __HAL_RCC_PLL2_VCIRANGE(pPLL2Init->PLL2RGE);
5343
5344 /* Select PLL2 output frequency range : VCO */
5345 __HAL_RCC_PLL2_VCORANGE(pPLL2Init->PLL2VCOSEL);
5346
5347 /* Configure the PLL2 Clock output(s) */
5348 __HAL_RCC_PLL2_CLKOUT_ENABLE(pPLL2Init->PLL2ClockOut);
5349
5350 /* Enable the PLL2 again by setting PLL2ON to 1*/
5351 __HAL_RCC_PLL2_ENABLE();
5352
5353 /* Get Start Tick*/
5354 tickstart = HAL_GetTick();
5355
5356 /* Wait till PLL2 is ready */
5357 while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == 0U)
5358 {
5359 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
5360 {
5361 status = HAL_TIMEOUT;
5362 break;
5363 }
5364 }
5365 }
5366 }
5367
5368 return status;
5369 }
5370
5371 /**
5372 * @brief Disable PLL2.
5373 * @retval HAL status
5374 */
HAL_RCCEx_DisablePLL2(void)5375 HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void)
5376 {
5377 uint32_t tickstart;
5378 HAL_StatusTypeDef status = HAL_OK;
5379
5380 /* Disable the PLL2 */
5381 __HAL_RCC_PLL2_DISABLE();
5382
5383 /* Get Start Tick*/
5384 tickstart = HAL_GetTick();
5385
5386 /* Wait till PLL2 is disabled */
5387 while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U)
5388 {
5389 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
5390 {
5391 status = HAL_TIMEOUT;
5392 break;
5393 }
5394 }
5395
5396 /* To save power, disable the PLL2 Source, FRACN and Clock outputs */
5397 CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN | RCC_PLL2CFGR_PLL2QEN | RCC_PLL2CFGR_PLL2REN | RCC_PLL2CFGR_PLL2SRC |
5398 RCC_PLL2CFGR_PLL2FRACEN);
5399
5400 return status;
5401 }
5402
5403 #if defined(RCC_CR_PLL3ON)
5404 /**
5405 * @brief Initialize and Enable the PLL3 according to the specified
5406 * parameters in the RCC_PLL3InitTypeDef.
5407 * @param pPLL3Init pointer to an RCC_PLL3InitTypeDef structure that
5408 * contains the configuration information for the PLL3
5409 * @retval HAL status.
5410 */
HAL_RCCEx_EnablePLL3(RCC_PLL3InitTypeDef * pPLL3Init)5411 HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(RCC_PLL3InitTypeDef *pPLL3Init)
5412 {
5413 uint32_t tickstart;
5414 HAL_StatusTypeDef status = HAL_OK;
5415
5416 /* check for PLL3 Parameters used to output PLL3CLK */
5417 assert_param(IS_RCC_PLL3_SOURCE(pPLL3Init->PLL3Source));
5418 assert_param(IS_RCC_PLL3_DIVM_VALUE(pPLL3Init->PLL3M));
5419 assert_param(IS_RCC_PLL3_MULN_VALUE(pPLL3Init->PLL3N));
5420 assert_param(IS_RCC_PLL3_DIVP_VALUE(pPLL3Init->PLL3P));
5421 assert_param(IS_RCC_PLL3_DIVQ_VALUE(pPLL3Init->PLL3Q));
5422 assert_param(IS_RCC_PLL3_DIVR_VALUE(pPLL3Init->PLL3R));
5423 assert_param(IS_RCC_PLL3_CLOCKOUT_VALUE(pPLL3Init->PLL3ClockOut));
5424 assert_param(IS_RCC_PLL3_VCIRGE_VALUE(pPLL3Init->PLL3RGE));
5425 assert_param(IS_RCC_PLL3_VCORGE_VALUE(pPLL3Init->PLL3VCOSEL));
5426 assert_param(IS_RCC_PLL3_FRACN_VALUE(pPLL3Init->PLL3FRACN));
5427
5428 /* Disable the PLL3 */
5429 __HAL_RCC_PLL3_DISABLE();
5430
5431 /* Get Start Tick*/
5432 tickstart = HAL_GetTick();
5433
5434 /* Wait till PLL3 is ready to be updated */
5435 while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U)
5436 {
5437 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
5438 {
5439 status = HAL_TIMEOUT;
5440 break;
5441 }
5442 }
5443
5444 if (status == HAL_OK)
5445 {
5446 /* Make sure PLL3Source is ready */
5447 status = RCCEx_PLLSource_Enable(pPLL3Init->PLL3Source);
5448
5449 if (status == HAL_OK)
5450 {
5451 /* Configure the PLL3 clock source, multiplication factor N, */
5452 /* and division factors M and P */
5453 __HAL_RCC_PLL3_CONFIG(pPLL3Init->PLL3Source, pPLL3Init->PLL3M, pPLL3Init->PLL3N, pPLL3Init->PLL3P,
5454 pPLL3Init->PLL3Q, pPLL3Init->PLL3R);
5455
5456 /* Disable PLL3FRACN . */
5457 __HAL_RCC_PLL3_FRACN_DISABLE();
5458
5459 /* Configure PLL3 FRACN */
5460 __HAL_RCC_PLL3_FRACN_CONFIG(pPLL3Init->PLL3FRACN);
5461
5462 /* Enable PLL3FRACN . */
5463 __HAL_RCC_PLL3_FRACN_ENABLE();
5464
5465 /* Select PLL3 input reference frequency range: VCI */
5466 __HAL_RCC_PLL3_VCIRANGE(pPLL3Init->PLL3RGE);
5467
5468 /* Select PLL3 output frequency range : VCO */
5469 __HAL_RCC_PLL3_VCORANGE(pPLL3Init->PLL3VCOSEL);
5470
5471 /* Configure the PLL3 Clock output(s) */
5472 __HAL_RCC_PLL3_CLKOUT_ENABLE(pPLL3Init->PLL3ClockOut);
5473
5474 /* Enable the PLL3 again by setting PLL3ON to 1*/
5475 __HAL_RCC_PLL3_ENABLE();
5476
5477 /* Get Start Tick*/
5478 tickstart = HAL_GetTick();
5479
5480 /* Wait till PLL3 is ready */
5481 while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == 0U)
5482 {
5483 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
5484 {
5485 status = HAL_TIMEOUT;
5486 break;
5487 }
5488 }
5489 }
5490 }
5491
5492 return status;
5493 }
5494
5495
5496 /**
5497 * @brief Disable PLL3.
5498 * @retval HAL status.
5499 */
HAL_RCCEx_DisablePLL3(void)5500 HAL_StatusTypeDef HAL_RCCEx_DisablePLL3(void)
5501 {
5502 uint32_t tickstart;
5503 HAL_StatusTypeDef status = HAL_OK;
5504
5505 /* Disable the PLL3 */
5506 __HAL_RCC_PLL3_DISABLE();
5507
5508 /* Get Start Tick*/
5509 tickstart = HAL_GetTick();
5510
5511 /* Wait till PLL3 is ready */
5512 while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U)
5513 {
5514 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
5515 {
5516 status = HAL_TIMEOUT;
5517 break;
5518 }
5519 }
5520
5521 /* To save power, disable the PLL3 Source and Clock outputs */
5522 CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN | RCC_PLL3CFGR_PLL3QEN | RCC_PLL3CFGR_PLL3REN | RCC_PLL3CFGR_PLL3SRC |
5523 RCC_PLL3CFGR_PLL3FRACEN);
5524
5525 return status;
5526 }
5527 #endif /* RCC_CR_PLL3ON */
5528
5529 /**
5530 * @brief Configure the oscillator clock source for wakeup from Stop and HSE CSS backup clock.
5531 * @param WakeUpClk Wakeup clock
5532 * This parameter can be one of the following values:
5533 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI oscillator selection
5534 * @arg @ref RCC_STOP_WAKEUPCLOCK_CSI CSI oscillator selection
5535 * @note This function shall not be called after the Clock Security System on HSE has been
5536 * enabled.
5537 * @retval None
5538 */
HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)5539 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
5540 {
5541 assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
5542
5543 __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
5544 }
5545
5546 /**
5547 * @brief Configure the oscillator Kernel clock source for wakeup from Stop
5548 * @param WakeUpClk: Kernel Wakeup clock
5549 * This parameter can be one of the following values:
5550 * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection
5551 * @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI oscillator selection
5552 * @retval None
5553 */
HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)5554 void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)
5555 {
5556 assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk));
5557
5558 __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk);
5559 }
5560
5561 /**
5562 * @brief Enable the LSE Clock Security System.
5563 * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
5564 * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
5565 * clock with HAL_RCCEx_PeriphCLKConfig().
5566 * @retval None
5567 */
HAL_RCCEx_EnableLSECSS(void)5568 void HAL_RCCEx_EnableLSECSS(void)
5569 {
5570 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
5571 }
5572
5573 /**
5574 * @brief Disable the LSE Clock Security System.
5575 * @note LSE Clock Security System can only be disabled after a LSE failure detection.
5576 * @retval None
5577 */
HAL_RCCEx_DisableLSECSS(void)5578 void HAL_RCCEx_DisableLSECSS(void)
5579 {
5580 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
5581 }
5582
5583 /**
5584 * @brief Handle the RCC LSE Clock Security System interrupt request.
5585 * @retval None
5586 */
HAL_RCCEx_LSECSS_IRQHandler(void)5587 void HAL_RCCEx_LSECSS_IRQHandler(void)
5588 {
5589 if (READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) != 0U)
5590 {
5591 /* RCC LSE Clock Security System interrupt user callback */
5592 HAL_RCCEx_LSECSS_Callback();
5593 }
5594 }
5595
5596 /**
5597 * @brief RCCEx LSE Clock Security System interrupt callback.
5598 * @retval none
5599 */
HAL_RCCEx_LSECSS_Callback(void)5600 __weak void HAL_RCCEx_LSECSS_Callback(void)
5601 {
5602 /* NOTE : This function should not be modified, when the callback is needed,
5603 the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
5604 */
5605 }
5606
5607 /**
5608 * @brief Select the Low Speed Microcontroller Clock source to output on LSCO pin (PB2).
5609 * @param LSCOSource specifies the Low Speed clock source to output.
5610 * This parameter can be one of the following values:
5611 * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source
5612 * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source
5613 * @retval None
5614 */
HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)5615 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
5616 {
5617 FlagStatus backupchanged = RESET;
5618
5619 /* Check the parameters */
5620 assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
5621
5622 /* Update LSCOSEL clock source in Backup Domain control register */
5623 if (HAL_IS_BIT_CLR(PWR->DBPCR, PWR_DBPCR_DBP))
5624 {
5625 HAL_PWR_EnableBkUpAccess();
5626 backupchanged = SET;
5627 }
5628
5629 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN);
5630
5631 if (backupchanged == SET)
5632 {
5633 HAL_PWR_DisableBkUpAccess();
5634 }
5635 }
5636
5637 /**
5638 * @brief Disable the Low Speed Microcontroller Clock Output.
5639 * @retval None
5640 */
HAL_RCCEx_DisableLSCO(void)5641 void HAL_RCCEx_DisableLSCO(void)
5642 {
5643 FlagStatus backupchanged = RESET;
5644
5645 /* Update LSCOEN bit in Backup Domain control register */
5646 if (HAL_IS_BIT_CLR(PWR->DBPCR, PWR_DBPCR_DBP))
5647 {
5648 /* Enable access to the backup domain */
5649 HAL_PWR_EnableBkUpAccess();
5650 backupchanged = SET;
5651 }
5652
5653 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
5654
5655 /* Restore previous configuration */
5656 if (backupchanged == SET)
5657 {
5658 /* Disable access to the backup domain */
5659 HAL_PWR_DisableBkUpAccess();
5660 }
5661 }
5662
5663 /**
5664 * @}
5665 */
5666
5667 #if defined(CRS)
5668
5669 /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
5670 * @brief Extended Clock Recovery System Control functions
5671 *
5672 @verbatim
5673 ===============================================================================
5674 ##### Extended Clock Recovery System Control functions #####
5675 ===============================================================================
5676 [..]
5677 For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:
5678
5679 (#) In System clock config, HSI48 needs to be enabled
5680
5681 (#) Enable CRS clock in IP MSP init which will use CRS functions
5682
5683 (#) Call CRS functions as follows:
5684 (##) Prepare synchronization configuration necessary for HSI48 calibration
5685 (+++) Default values can be set for frequency Error Measurement (reload and error limit)
5686 and also HSI48 oscillator smooth trimming.
5687 (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
5688 directly reload value with target and synchronization frequencies values
5689 (##) Call function HAL_RCCEx_CRSConfig which
5690 (+++) Resets CRS registers to their default values.
5691 (+++) Configures CRS registers with synchronization configuration
5692 (+++) Enables automatic calibration and frequency error counter feature
5693 Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
5694 periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
5695 provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
5696 precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
5697 should be used as SYNC signal.
5698
5699 (##) A polling function is provided to wait for complete synchronization
5700 (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
5701 (+++) According to CRS status, user can decide to adjust again the calibration or continue
5702 application if synchronization is OK
5703
5704 (#) User can retrieve information related to synchronization in calling function
5705 HAL_RCCEx_CRSGetSynchronizationInfo()
5706
5707 (#) Regarding synchronization status and synchronization information, user can try a new calibration
5708 in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
5709 Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
5710 it means that the actual frequency is lower than the target (and so, that the TRIM value should be
5711 incremented), while when it is detected during the upcounting phase it means that the actual frequency
5712 is higher (and that the TRIM value should be decremented).
5713
5714 (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
5715 through CRS Handler (CRS_IRQn/CRS_IRQHandler)
5716 (++) Call function HAL_RCCEx_CRSConfig()
5717 (++) Enable CRS_IRQn (thanks to NVIC functions)
5718 (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
5719 (++) Implement CRS status management in the following user callbacks called from
5720 HAL_RCCEx_CRS_IRQHandler():
5721 (+++) HAL_RCCEx_CRS_SyncOkCallback()
5722 (+++) HAL_RCCEx_CRS_SyncWarnCallback()
5723 (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
5724 (+++) HAL_RCCEx_CRS_ErrorCallback()
5725
5726 (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
5727 This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
5728
5729 @endverbatim
5730 * @{
5731 */
5732
5733 /**
5734 * @brief Start automatic synchronization for polling mode
5735 * @param pInit Pointer on RCC_CRSInitTypeDef structure
5736 * @retval None
5737 */
HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef * pInit)5738 void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *pInit)
5739 {
5740 uint32_t value;
5741
5742 /* Check the parameters */
5743 assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
5744 assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
5745 assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
5746 assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
5747 assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
5748 assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
5749
5750 /* CONFIGURATION */
5751
5752 /* Before configuration, reset CRS registers to their default values*/
5753 __HAL_RCC_CRS_FORCE_RESET();
5754 __HAL_RCC_CRS_RELEASE_RESET();
5755
5756 /* Set the SYNCDIV[2:0] bits according to Prescaler value */
5757 /* Set the SYNCSRC[1:0] bits according to Source value */
5758 /* Set the SYNCSPOL bit according to Polarity value */
5759 value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
5760 /* Set the RELOAD[15:0] bits according to ReloadValue value */
5761 value |= pInit->ReloadValue;
5762 /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
5763 value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
5764 WRITE_REG(CRS->CFGR, value);
5765
5766 /* Adjust HSI48 oscillator smooth trimming */
5767 /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
5768 MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
5769
5770 /* START AUTOMATIC SYNCHRONIZATION*/
5771
5772 /* Enable Automatic trimming & Frequency error counter */
5773 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
5774 }
5775
5776 /**
5777 * @brief Generate the software synchronization event
5778 * @retval None
5779 */
HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)5780 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
5781 {
5782 SET_BIT(CRS->CR, CRS_CR_SWSYNC);
5783 }
5784
5785 /**
5786 * @brief Return synchronization info
5787 * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
5788 * @retval None
5789 */
HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef * pSynchroInfo)5790 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
5791 {
5792 /* Check the parameter */
5793 assert_param(pSynchroInfo != (void *)NULL);
5794
5795 /* Get the reload value */
5796 pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
5797
5798 /* Get HSI48 oscillator smooth trimming */
5799 pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
5800
5801 /* Get Frequency error capture */
5802 pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
5803
5804 /* Get Frequency error direction */
5805 pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
5806 }
5807
5808 /**
5809 * @brief Wait for CRS Synchronization status.
5810 * @param Timeout Duration of the timeout
5811 * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization
5812 * frequency.
5813 * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
5814 * @retval Combination of Synchronization status
5815 * This parameter can be a combination of the following values:
5816 * @arg @ref RCC_CRS_TIMEOUT
5817 * @arg @ref RCC_CRS_SYNCOK
5818 * @arg @ref RCC_CRS_SYNCWARN
5819 * @arg @ref RCC_CRS_SYNCERR
5820 * @arg @ref RCC_CRS_SYNCMISS
5821 * @arg @ref RCC_CRS_TRIMOVF
5822 */
HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)5823 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
5824 {
5825 uint32_t crsstatus = RCC_CRS_NONE;
5826 uint32_t tickstart;
5827
5828 /* Get timeout */
5829 tickstart = HAL_GetTick();
5830
5831 /* Wait for CRS flag or timeout detection */
5832 do
5833 {
5834 if (Timeout != HAL_MAX_DELAY)
5835 {
5836 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
5837 {
5838 crsstatus = RCC_CRS_TIMEOUT;
5839 }
5840 }
5841 /* Check CRS SYNCOK flag */
5842 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
5843 {
5844 /* CRS SYNC event OK */
5845 crsstatus |= RCC_CRS_SYNCOK;
5846
5847 /* Clear CRS SYNC event OK bit */
5848 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
5849 }
5850
5851 /* Check CRS SYNCWARN flag */
5852 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
5853 {
5854 /* CRS SYNC warning */
5855 crsstatus |= RCC_CRS_SYNCWARN;
5856
5857 /* Clear CRS SYNCWARN bit */
5858 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
5859 }
5860
5861 /* Check CRS TRIM overflow flag */
5862 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
5863 {
5864 /* CRS SYNC Error */
5865 crsstatus |= RCC_CRS_TRIMOVF;
5866
5867 /* Clear CRS Error bit */
5868 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
5869 }
5870
5871 /* Check CRS Error flag */
5872 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
5873 {
5874 /* CRS SYNC Error */
5875 crsstatus |= RCC_CRS_SYNCERR;
5876
5877 /* Clear CRS Error bit */
5878 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
5879 }
5880
5881 /* Check CRS SYNC Missed flag */
5882 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
5883 {
5884 /* CRS SYNC Missed */
5885 crsstatus |= RCC_CRS_SYNCMISS;
5886
5887 /* Clear CRS SYNC Missed bit */
5888 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
5889 }
5890
5891 /* Check CRS Expected SYNC flag */
5892 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
5893 {
5894 /* frequency error counter reached a zero value */
5895 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
5896 }
5897 } while (RCC_CRS_NONE == crsstatus);
5898
5899 return crsstatus;
5900 }
5901
5902 /**
5903 * @brief Handle the Clock Recovery System interrupt request.
5904 * @retval None
5905 */
HAL_RCCEx_CRS_IRQHandler(void)5906 void HAL_RCCEx_CRS_IRQHandler(void)
5907 {
5908 uint32_t crserror = RCC_CRS_NONE;
5909 /* Get current IT flags and IT sources values */
5910 uint32_t itflags = READ_REG(CRS->ISR);
5911 uint32_t itsources = READ_REG(CRS->CR);
5912
5913 /* Check CRS SYNCOK flag */
5914 if (((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))
5915 {
5916 /* Clear CRS SYNC event OK flag */
5917 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
5918
5919 /* user callback */
5920 HAL_RCCEx_CRS_SyncOkCallback();
5921 }
5922 /* Check CRS SYNCWARN flag */
5923 else if (((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))
5924 {
5925 /* Clear CRS SYNCWARN flag */
5926 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
5927
5928 /* user callback */
5929 HAL_RCCEx_CRS_SyncWarnCallback();
5930 }
5931 /* Check CRS Expected SYNC flag */
5932 else if (((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))
5933 {
5934 /* frequency error counter reached a zero value */
5935 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
5936
5937 /* user callback */
5938 HAL_RCCEx_CRS_ExpectedSyncCallback();
5939 }
5940 /* Check CRS Error flags */
5941 else
5942 {
5943 if (((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))
5944 {
5945 if ((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)
5946 {
5947 crserror |= RCC_CRS_SYNCERR;
5948 }
5949 if ((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)
5950 {
5951 crserror |= RCC_CRS_SYNCMISS;
5952 }
5953 if ((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)
5954 {
5955 crserror |= RCC_CRS_TRIMOVF;
5956 }
5957
5958 /* Clear CRS Error flags */
5959 WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
5960
5961 /* user error callback */
5962 HAL_RCCEx_CRS_ErrorCallback(crserror);
5963 }
5964 }
5965 }
5966
5967 /**
5968 * @brief RCCEx Clock Recovery System SYNCOK interrupt callback.
5969 * @retval none
5970 */
HAL_RCCEx_CRS_SyncOkCallback(void)5971 __weak void HAL_RCCEx_CRS_SyncOkCallback(void)
5972 {
5973 /* NOTE : This function should not be modified, when the callback is needed,
5974 the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
5975 */
5976 }
5977
5978 /**
5979 * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback.
5980 * @retval none
5981 */
HAL_RCCEx_CRS_SyncWarnCallback(void)5982 __weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
5983 {
5984 /* NOTE : This function should not be modified, when the callback is needed,
5985 the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
5986 */
5987 }
5988
5989 /**
5990 * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback.
5991 * @retval none
5992 */
HAL_RCCEx_CRS_ExpectedSyncCallback(void)5993 __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
5994 {
5995 /* NOTE : This function should not be modified, when the callback is needed,
5996 the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
5997 */
5998 }
5999
6000 /**
6001 * @brief RCCEx Clock Recovery System Error interrupt callback.
6002 * @param Error Combination of Error status.
6003 * This parameter can be a combination of the following values:
6004 * @arg @ref RCC_CRS_SYNCERR
6005 * @arg @ref RCC_CRS_SYNCMISS
6006 * @arg @ref RCC_CRS_TRIMOVF
6007 * @retval none
6008 */
HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)6009 __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
6010 {
6011 /* Prevent unused argument(s) compilation warning */
6012 UNUSED(Error);
6013
6014 /* NOTE : This function should not be modified, when the callback is needed,
6015 the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
6016 */
6017 }
6018
6019 /**
6020 * @}
6021 */
6022
6023 #endif /* CRS */
6024
6025 /**
6026 * @}
6027 */
6028
6029 /** @addtogroup RCCEx_Private_Functions
6030 * @{
6031 */
6032
6033 /**
6034 * @brief Enable PLLx source clock and check ready flag
6035 * @param PllSource contains the selected PLLx source clock (HSE, HSI or CSI)
6036 * @retval HAL status
6037 */
RCCEx_PLLSource_Enable(uint32_t PllSource)6038 static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource)
6039 {
6040 uint32_t tickstart;
6041 HAL_StatusTypeDef status = HAL_OK;
6042
6043 switch (PllSource)
6044 {
6045 case RCC_PLL1_SOURCE_CSI:
6046 /* Check whether CSI in not ready and enable it */
6047 if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) == 0U)
6048 {
6049 /* Enable the Internal Low power oscillator (CSI). */
6050 __HAL_RCC_CSI_ENABLE();
6051
6052 /* Get timeout */
6053 tickstart = HAL_GetTick();
6054
6055 /* Wait till CSI is ready */
6056 while (READ_BIT(RCC->CR, RCC_CR_CSIRDY) == 0U)
6057 {
6058 if ((HAL_GetTick() - tickstart) > RCC_CSI_TIMEOUT_VALUE)
6059 {
6060 status = HAL_TIMEOUT;
6061 break;
6062 }
6063 }
6064 }
6065 break;
6066
6067 case RCC_PLL1_SOURCE_HSI:
6068 /* Check whether HSI in not ready and enable it */
6069 if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
6070 {
6071 /* Enable the Internal High Speed oscillator (HSI). */
6072 __HAL_RCC_HSI_ENABLE();
6073
6074 /* Get timeout */
6075 tickstart = HAL_GetTick();
6076
6077 /* Wait till HSI is ready */
6078 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
6079 {
6080 if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE)
6081 {
6082 status = HAL_TIMEOUT;
6083 break;
6084 }
6085 }
6086 }
6087 break;
6088
6089 case RCC_PLL1_SOURCE_HSE:
6090 /* Check whether HSE in not ready and enable it */
6091 if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
6092 {
6093 /* Enable the External High Speed oscillator (HSE). */
6094 SET_BIT(RCC->CR, RCC_CR_HSEON);
6095
6096 /* Get Start Tick*/
6097 tickstart = HAL_GetTick();
6098
6099 /* Wait till HSE is ready */
6100 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
6101 {
6102 if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE)
6103 {
6104 status = HAL_TIMEOUT;
6105 break;
6106 }
6107 }
6108 }
6109 break;
6110
6111 default:
6112 status = HAL_ERROR;
6113 break;
6114 }
6115
6116 return status;
6117 }
6118
6119 /**
6120 * @brief Configure the PLL2 VCI/VCO ranges, multiplication and division factors and its output clock(s)
6121 * @param pll2 pointer to an RCC_PLL2InitTypeDef structure that
6122 * contains the configuration parameters M, N, FRACN, VCI/VCO ranges as well as PLL2 output clocks dividers
6123 * @note PLL2 is temporary disabled to apply new parameters
6124 * @retval HAL status
6125 */
RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef * pll2)6126 static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *pll2)
6127 {
6128
6129 uint32_t tickstart;
6130 assert_param(IS_RCC_PLL2_SOURCE(pll2->PLL2Source));
6131 assert_param(IS_RCC_PLL2_DIVM_VALUE(pll2->PLL2M));
6132 assert_param(IS_RCC_PLL2_MULN_VALUE(pll2->PLL2N));
6133 assert_param(IS_RCC_PLL2_DIVP_VALUE(pll2->PLL2P));
6134 assert_param(IS_RCC_PLL2_DIVQ_VALUE(pll2->PLL2Q));
6135 assert_param(IS_RCC_PLL2_DIVR_VALUE(pll2->PLL2R));
6136 assert_param(IS_RCC_PLL2_CLOCKOUT_VALUE(pll2->PLL2ClockOut));
6137 assert_param(IS_RCC_PLL2_VCIRGE_VALUE(pll2->PLL2RGE));
6138 assert_param(IS_RCC_PLL2_VCORGE_VALUE(pll2->PLL2VCOSEL));
6139 assert_param(IS_RCC_PLL2_FRACN_VALUE(pll2->PLL2FRACN));
6140
6141 /* Disable PLL2. */
6142 __HAL_RCC_PLL2_DISABLE();
6143
6144 /* Get Start Tick*/
6145 tickstart = HAL_GetTick();
6146
6147 /* Wait till PLL2 is disabled */
6148 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
6149 {
6150 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
6151 {
6152 return HAL_TIMEOUT;
6153 }
6154 }
6155
6156 /* Configure PLL2 multiplication and division factors. */
6157 __HAL_RCC_PLL2_CONFIG(pll2->PLL2Source,
6158 pll2->PLL2M,
6159 pll2->PLL2N,
6160 pll2->PLL2P,
6161 pll2->PLL2Q,
6162 pll2->PLL2R);
6163
6164 /* Select PLL2 input reference frequency range: VCI */
6165 __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE);
6166
6167 /* Select PLL2 output frequency range : VCO */
6168 __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL);
6169
6170 /* Configure the PLL2 Clock output(s) */
6171 __HAL_RCC_PLL2_CLKOUT_ENABLE(pll2->PLL2ClockOut);
6172
6173 /* Disable PLL2FRACN . */
6174 __HAL_RCC_PLL2_FRACN_DISABLE();
6175
6176 /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */
6177 __HAL_RCC_PLL2_FRACN_CONFIG(pll2->PLL2FRACN);
6178
6179 /* Enable PLL2FRACN . */
6180 __HAL_RCC_PLL2_FRACN_ENABLE();
6181
6182 /* Enable PLL2. */
6183 __HAL_RCC_PLL2_ENABLE();
6184
6185 /* Get Start Tick*/
6186 tickstart = HAL_GetTick();
6187
6188 /* Wait till PLL2 is ready */
6189 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
6190 {
6191 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
6192 {
6193 return HAL_TIMEOUT;
6194 }
6195 }
6196 return HAL_OK;
6197
6198 }
6199
6200 #if defined(RCC_CR_PLL3ON)
6201 /**
6202 * @brief Configure the PLL3 VCI/VCO ranges, multiplication and division factors and its output clock(s)
6203 * @param pll3 pointer to an RCC_PLL3InitTypeDef structure that
6204 * contains the configuration parameters M, N, FRACN, VCI/VCO ranges as well as PLL3 output clocks dividers
6205 * @note PLL3 is temporary disabled to apply new parameters
6206 * @retval HAL status.
6207 */
RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef * pll3)6208 static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *pll3)
6209 {
6210
6211 uint32_t tickstart;
6212 assert_param(IS_RCC_PLL3_SOURCE(pll3->PLL3Source));
6213 assert_param(IS_RCC_PLL3_DIVM_VALUE(pll3->PLL3M));
6214 assert_param(IS_RCC_PLL3_MULN_VALUE(pll3->PLL3N));
6215 assert_param(IS_RCC_PLL3_DIVP_VALUE(pll3->PLL3P));
6216 assert_param(IS_RCC_PLL3_DIVQ_VALUE(pll3->PLL3Q));
6217 assert_param(IS_RCC_PLL3_DIVR_VALUE(pll3->PLL3R));
6218 assert_param(IS_RCC_PLL3_CLOCKOUT_VALUE(pll3->PLL3ClockOut));
6219 assert_param(IS_RCC_PLL3_VCIRGE_VALUE(pll3->PLL3RGE));
6220 assert_param(IS_RCC_PLL3_VCORGE_VALUE(pll3->PLL3VCOSEL));
6221 assert_param(IS_RCC_PLL3_FRACN_VALUE(pll3->PLL3FRACN));
6222
6223 /* Disable PLL3. */
6224 __HAL_RCC_PLL3_DISABLE();
6225
6226 /* Get Start Tick*/
6227 tickstart = HAL_GetTick();
6228
6229 /* Wait till PLL3 is disabled */
6230 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
6231 {
6232 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
6233 {
6234 return HAL_TIMEOUT;
6235 }
6236 }
6237
6238 /* Configure PLL3 multiplication and division factors. */
6239 __HAL_RCC_PLL3_CONFIG(pll3->PLL3Source,
6240 pll3->PLL3M,
6241 pll3->PLL3N,
6242 pll3->PLL3P,
6243 pll3->PLL3Q,
6244 pll3->PLL3R);
6245
6246 /* Select PLL3 input reference frequency range: VCI */
6247 __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ;
6248
6249 /* Select PLL3 output frequency range : VCO */
6250 __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL);
6251
6252 /* Configure the PLL3 Clock output(s) */
6253 __HAL_RCC_PLL3_CLKOUT_ENABLE(pll3->PLL3ClockOut);
6254
6255 /* Disable PLL3FRACN . */
6256 __HAL_RCC_PLL3_FRACN_DISABLE();
6257
6258 /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */
6259 __HAL_RCC_PLL3_FRACN_CONFIG(pll3->PLL3FRACN);
6260
6261 /* Enable PLL3FRACN . */
6262 __HAL_RCC_PLL3_FRACN_ENABLE();
6263
6264 /* Enable PLL3. */
6265 __HAL_RCC_PLL3_ENABLE();
6266
6267 /* Get Start Tick*/
6268 tickstart = HAL_GetTick();
6269
6270 /* Wait till PLL3 is ready */
6271 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
6272 {
6273 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
6274 {
6275 return HAL_TIMEOUT;
6276 }
6277 }
6278 return HAL_OK;
6279 }
6280 #endif /* RCC_CR_PLL3ON */
6281
6282 /**
6283 * @}
6284 */
6285
6286 #endif /* HAL_RCC_MODULE_ENABLED */
6287 /**
6288 * @}
6289 */
6290
6291 /**
6292 * @}
6293 */
6294
