1 /**
2 ******************************************************************************
3 * @file stm32h5xx_hal_i2s.c
4 * @author MCD Application Team
5 * @brief I2S HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Integrated Interchip Sound (I2S) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral State and Errors functions
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2023 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file
18 * in the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 *
21 ******************************************************************************
22 @verbatim
23 ===============================================================================
24 ##### How to use this driver #####
25 ===============================================================================
26 [..]
27 The I2S HAL driver can be used as follow:
28
29 (#) Declare a I2S_HandleTypeDef handle structure.
30 (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
31 (##) Enable the SPIx interface clock.
32 (##) I2S pins configuration:
33 (+++) Enable the clock for the I2S GPIOs.
34 (+++) Configure these I2S pins as alternate function pull-up.
35 (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
36 and HAL_I2S_Receive_IT() APIs).
37 (+++) Configure the I2Sx interrupt priority.
38 (+++) Enable the NVIC I2S IRQ handle.
39 (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
40 and HAL_I2S_Receive_DMA() APIs:
41 (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel.
42 (+++) Enable the DMAx interface clock.
43 (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
44 (+++) Configure the DMA Tx/Rx Stream/Channel.
45 (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
46 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
47 DMA Tx/Rx Stream/Channel.
48
49 (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
50 using HAL_I2S_Init() function.
51
52 -@- The specific I2S interrupts (Transmission complete interrupt,
53 RXNE interrupt and Error Interrupts) will be managed using the macros
54 __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
55
56 (+@) External clock source is configured after setting correctly
57 the define constant EXTERNAL_CLOCK_VALUE in the stm32h5xx_hal_conf.h file.
58
59 (#) Three mode of operations are available within this driver :
60
61 *** Polling mode IO operation ***
62 =================================
63 [..]
64 (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
65 (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
66
67 *** Interrupt mode IO operation ***
68 ===================================
69 [..]
70 (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
71 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
72 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
73 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
74 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
75 (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
76 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
77 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
78 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
79 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
80 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
81 add his own code by customization of function pointer HAL_I2S_ErrorCallback
82
83 *** DMA mode IO operation ***
84 ==============================
85 [..]
86 (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
87 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
88 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
89 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
90 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
91 (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
92 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
93 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
94 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
95 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
96 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
97 add his own code by customization of function pointer HAL_I2S_ErrorCallback
98 (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
99 (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
100 (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
101
102 *** I2S HAL driver macros list ***
103 ===================================
104 [..]
105 Below the list of most used macros in I2S HAL driver.
106
107 (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
108 (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
109 (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
110 (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
111 (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
112
113 [..]
114 (@) You can refer to the I2S HAL driver header file for more useful macros
115
116 *** I2S HAL driver macros list ***
117 ===================================
118 [..]
119 Callback registration:
120
121 (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1UL
122 allows the user to configure dynamically the driver callbacks.
123 Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback.
124
125 Function HAL_I2S_RegisterCallback() allows to register following callbacks:
126 (+) TxCpltCallback : I2S Tx Completed callback
127 (+) RxCpltCallback : I2S Rx Completed callback
128 (+) TxRxCpltCallback : I2S TxRx Completed callback
129 (+) TxHalfCpltCallback : I2S Tx Half Completed callback
130 (+) RxHalfCpltCallback : I2S Rx Half Completed callback
131 (+) TxRxHalfCpltCallback : I2S TxRx Half Completed callback
132 (+) ErrorCallback : I2S Error callback
133 (+) MspInitCallback : I2S Msp Init callback
134 (+) MspDeInitCallback : I2S Msp DeInit callback
135 This function takes as parameters the HAL peripheral handle, the Callback ID
136 and a pointer to the user callback function.
137
138
139 (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default
140 weak function.
141 HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle,
142 and the Callback ID.
143 This function allows to reset following callbacks:
144 (+) TxCpltCallback : I2S Tx Completed callback
145 (+) RxCpltCallback : I2S Rx Completed callback
146 (+) TxRxCpltCallback : I2S TxRx Completed callback
147 (+) TxHalfCpltCallback : I2S Tx Half Completed callback
148 (+) RxHalfCpltCallback : I2S Rx Half Completed callback
149 (+) TxRxHalfCpltCallback : I2S TxRx Half Completed callback
150 (+) ErrorCallback : I2S Error callback
151 (+) MspInitCallback : I2S Msp Init callback
152 (+) MspDeInitCallback : I2S Msp DeInit callback
153
154 By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET
155 all callbacks are set to the corresponding weak functions:
156 examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback().
157 Exception done for MspInit and MspDeInit functions that are
158 reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when
159 these callbacks are null (not registered beforehand).
160 If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit()
161 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
162
163 Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only.
164 Exception done MspInit/MspDeInit functions that can be registered/unregistered
165 in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state,
166 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
167 Then, the user first registers the MspInit/MspDeInit user callbacks
168 using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit()
169 or HAL_I2S_Init() function.
170
171 When The compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
172 not defined, the callback registering feature is not available
173 and weak callbacks are used.
174
175
176 @endverbatim
177 */
178
179 /* Includes ------------------------------------------------------------------*/
180 #include "stm32h5xx_hal.h"
181
182 #ifdef HAL_I2S_MODULE_ENABLED
183
184 /** @addtogroup STM32H5xx_HAL_Driver
185 * @{
186 */
187
188 /** @defgroup I2S I2S
189 * @brief I2S HAL module driver
190 * @{
191 */
192
193 /* Private typedef -----------------------------------------------------------*/
194 /* Private define ------------------------------------------------------------*/
195 /** @defgroup I2S_Private_Define I2S Private Define
196 * @{
197 */
198 #define I2S_TIMEOUT 0xFFFFUL
199 /**
200 * @}
201 */
202
203 /* Private macro -------------------------------------------------------------*/
204 /* Private variables ---------------------------------------------------------*/
205 /* Private function prototypes -----------------------------------------------*/
206 /** @defgroup I2S_Private_Functions I2S Private Functions
207 * @{
208 */
209 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
210 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
211 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
212 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
213 static void I2SEx_DMATxRxCplt(DMA_HandleTypeDef *hdma);
214 static void I2SEx_DMATxRxHalfCplt(DMA_HandleTypeDef *hdma);
215 static void I2S_DMAError(DMA_HandleTypeDef *hdma);
216 static void I2S_Transmit_16Bit_IT(I2S_HandleTypeDef *hi2s);
217 static void I2S_Transmit_32Bit_IT(I2S_HandleTypeDef *hi2s);
218 static void I2S_Receive_16Bit_IT(I2S_HandleTypeDef *hi2s);
219 static void I2S_Receive_32Bit_IT(I2S_HandleTypeDef *hi2s);
220 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
221 uint32_t Tickstart, uint32_t Timeout);
222 /**
223 * @}
224 */
225
226 /* Exported functions ---------------------------------------------------------*/
227
228 /** @defgroup I2S_Exported_Functions I2S Exported Functions
229 * @{
230 */
231
232 /** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
233 * @brief Initialization and Configuration functions
234 *
235 @verbatim
236 ===============================================================================
237 ##### Initialization and de-initialization functions #####
238 ===============================================================================
239 [..] This subsection provides a set of functions allowing to initialize and
240 de-initialize the I2Sx peripheral in simplex mode:
241
242 (+) User must Implement HAL_I2S_MspInit() function in which he configures
243 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
244
245 (+) Call the function HAL_I2S_Init() to configure the selected device with
246 the selected configuration:
247 (++) Mode
248 (++) Standard
249 (++) Data Format
250 (++) MCLK Output
251 (++) Audio frequency
252 (++) Polarity
253
254 (+) Call the function HAL_I2S_DeInit() to restore the default configuration
255 of the selected I2Sx peripheral.
256 @endverbatim
257 * @{
258 */
259
260 /**
261 * @brief Initializes the I2S according to the specified parameters
262 * in the I2S_InitTypeDef and create the associated handle.
263 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
264 * the configuration information for I2S module
265 * @retval HAL status
266 */
HAL_I2S_Init(I2S_HandleTypeDef * hi2s)267 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
268 {
269 uint32_t i2sdiv;
270 uint32_t i2sodd;
271 uint32_t packetlength;
272 uint32_t tmp;
273 uint32_t i2sclk;
274 uint32_t ispcm;
275
276 /* Check the I2S handle allocation */
277 if (hi2s == NULL)
278 {
279 return HAL_ERROR;
280 }
281
282 /* Check the I2S parameters */
283 assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
284 assert_param(IS_I2S_MODE(hi2s->Init.Mode));
285 assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
286 assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
287 assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
288 assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
289 assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
290 assert_param(IS_I2S_FIRST_BIT(hi2s->Init.FirstBit));
291 assert_param(IS_I2S_WS_INVERSION(hi2s->Init.WSInversion));
292 assert_param(IS_I2S_DATA_24BIT_ALIGNMENT(hi2s->Init.Data24BitAlignment));
293 assert_param(IS_I2S_MASTER_KEEP_IO_STATE(hi2s->Init.MasterKeepIOState));
294
295 if (hi2s->State == HAL_I2S_STATE_RESET)
296 {
297 /* Allocate lock resource and initialize it */
298 hi2s->Lock = HAL_UNLOCKED;
299
300 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
301 /* Init the I2S Callback settings */
302 hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
303 hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
304 hi2s->TxRxCpltCallback = HAL_I2SEx_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
305 hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
306 hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
307 hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
308 hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
309
310 if (hi2s->MspInitCallback == NULL)
311 {
312 hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
313 }
314
315 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
316 hi2s->MspInitCallback(hi2s);
317 #else
318 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
319 HAL_I2S_MspInit(hi2s);
320 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
321 }
322
323 hi2s->State = HAL_I2S_STATE_BUSY;
324
325 /* Disable the selected I2S peripheral */
326 if ((hi2s->Instance->CR1 & SPI_CR1_SPE) == SPI_CR1_SPE)
327 {
328 /* Disable I2S peripheral */
329 __HAL_I2S_DISABLE(hi2s);
330 }
331
332 /* Clear I2S configuration register */
333 CLEAR_REG(hi2s->Instance->I2SCFGR);
334
335 if (IS_I2S_MASTER(hi2s->Init.Mode))
336 {
337 /*------------------------- I2SDIV and ODD Calculation ---------------------*/
338 /* If the requested audio frequency is not the default, compute the prescaler */
339 if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
340 {
341 /* Check the frame length (For the Prescaler computing) ********************/
342 if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
343 {
344 /* Channel length is 32 bits */
345 packetlength = 2UL;
346 }
347 else
348 {
349 /* Channel length is 16 bits */
350 packetlength = 1UL;
351 }
352
353 /* Check if PCM standard is used */
354 if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) ||
355 (hi2s->Init.Standard == I2S_STANDARD_PCM_LONG))
356 {
357 ispcm = 1UL;
358 }
359 else
360 {
361 ispcm = 0UL;
362 }
363
364 /* Get the source clock value: based on System Clock value */
365 if (hi2s->Instance == SPI1)
366 {
367 i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI1);
368 }
369 else if (hi2s->Instance == SPI2)
370 {
371 i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI2);
372 }
373 else /* SPI3 source clock */
374 {
375 i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI3);
376 }
377
378 /* Compute the Real divider depending on the MCLK output state, with a floating point */
379 if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
380 {
381 /* MCLK output is enabled */
382 tmp = (uint32_t)((((i2sclk / (256UL >> ispcm)) * 10UL) / hi2s->Init.AudioFreq) + 5UL);
383 }
384 else
385 {
386 /* MCLK output is disabled */
387 tmp = (uint32_t)((((i2sclk / ((32UL >> ispcm) * packetlength)) * 10UL) / hi2s->Init.AudioFreq) + 5UL);
388 }
389
390 /* Remove the flatting point */
391 tmp = tmp / 10UL;
392
393 /* Check the parity of the divider */
394 i2sodd = (uint32_t)(tmp & (uint32_t)1UL);
395
396 /* Compute the i2sdiv prescaler */
397 i2sdiv = (uint32_t)((tmp - i2sodd) / 2UL);
398 }
399 else
400 {
401 /* Set the default values */
402 i2sdiv = 2UL;
403 i2sodd = 0UL;
404 }
405
406 /* Test if the obtain values are forbidden or out of range */
407 if (((i2sodd == 1UL) && (i2sdiv == 1UL)) || (i2sdiv > 0xFFUL))
408 {
409 /* Set the error code */
410 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
411 return HAL_ERROR;
412 }
413
414 /* Force i2smod to 1 just to be sure that (2xi2sdiv + i2sodd) is always higher than 0 */
415 if (i2sdiv == 0UL)
416 {
417 i2sodd = 1UL;
418 }
419
420 MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_I2SDIV | SPI_I2SCFGR_ODD),
421 ((i2sdiv << SPI_I2SCFGR_I2SDIV_Pos) | (i2sodd << SPI_I2SCFGR_ODD_Pos)));
422 }
423
424 /*-------------------------- I2Sx I2SCFGR Configuration --------------------*/
425 /* Configure I2SMOD, I2SCFG, I2SSTD, PCMSYNC, DATLEN ,CHLEN ,CKPOL, WSINV, DATAFMT, I2SDIV, ODD and MCKOE bits bits */
426 /* And configure the I2S with the I2S_InitStruct values */
427 MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SCFG | \
428 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | \
429 SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | \
430 SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_WSINV | \
431 SPI_I2SCFGR_DATFMT | SPI_I2SCFGR_MCKOE),
432 (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \
433 hi2s->Init.Standard | hi2s->Init.DataFormat | \
434 hi2s->Init.CPOL | hi2s->Init.WSInversion | \
435 hi2s->Init.Data24BitAlignment | hi2s->Init.MCLKOutput));
436 /*Clear status register*/
437 WRITE_REG(hi2s->Instance->IFCR, 0x0FF8);
438
439 /*---------------------------- I2Sx CFG2 Configuration ----------------------*/
440
441 /* Unlock the AF configuration to configure CFG2 register*/
442 CLEAR_BIT(hi2s->Instance->CR1, SPI_CR1_IOLOCK);
443
444 MODIFY_REG(hi2s->Instance->CFG2, SPI_CFG2_LSBFRST, hi2s->Init.FirstBit);
445
446 /* Insure that AFCNTR is managed only by Master */
447 if (IS_I2S_MASTER(hi2s->Init.Mode))
448 {
449 /* Alternate function GPIOs control */
450 MODIFY_REG(hi2s->Instance->CFG2, SPI_CFG2_AFCNTR, (hi2s->Init.MasterKeepIOState));
451 }
452
453 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
454 hi2s->State = HAL_I2S_STATE_READY;
455
456 return HAL_OK;
457 }
458
459 /**
460 * @brief DeInitializes the I2S peripheral
461 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
462 * the configuration information for I2S module
463 * @retval HAL status
464 */
HAL_I2S_DeInit(I2S_HandleTypeDef * hi2s)465 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
466 {
467 /* Check the I2S handle allocation */
468 if (hi2s == NULL)
469 {
470 return HAL_ERROR;
471 }
472
473 /* Check the parameters */
474 assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
475
476 hi2s->State = HAL_I2S_STATE_BUSY;
477
478 /* Disable the I2S Peripheral Clock */
479 __HAL_I2S_DISABLE(hi2s);
480
481 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
482 if (hi2s->MspDeInitCallback == NULL)
483 {
484 hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
485 }
486
487 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
488 hi2s->MspDeInitCallback(hi2s);
489 #else
490 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
491 HAL_I2S_MspDeInit(hi2s);
492 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
493
494 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
495 hi2s->State = HAL_I2S_STATE_RESET;
496
497 /* Release Lock */
498 __HAL_UNLOCK(hi2s);
499
500 return HAL_OK;
501 }
502
503 /**
504 * @brief I2S MSP Init
505 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
506 * the configuration information for I2S module
507 * @retval None
508 */
HAL_I2S_MspInit(I2S_HandleTypeDef * hi2s)509 __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
510 {
511 /* Prevent unused argument(s) compilation warning */
512 UNUSED(hi2s);
513
514 /* NOTE : This function Should not be modified, when the callback is needed,
515 the HAL_I2S_MspInit could be implemented in the user file
516 */
517 }
518
519 /**
520 * @brief I2S MSP DeInit
521 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
522 * the configuration information for I2S module
523 * @retval None
524 */
HAL_I2S_MspDeInit(I2S_HandleTypeDef * hi2s)525 __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
526 {
527 /* Prevent unused argument(s) compilation warning */
528 UNUSED(hi2s);
529
530 /* NOTE : This function Should not be modified, when the callback is needed,
531 the HAL_I2S_MspDeInit could be implemented in the user file
532 */
533 }
534
535 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
536 /**
537 * @brief Register a User I2S Callback
538 * To be used instead of the weak predefined callback
539 * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
540 * the configuration information for the specified I2S.
541 * @param CallbackID ID of the callback to be registered
542 * @param pCallback pointer to the Callback function
543 * @note The HAL_I2S_RegisterCallback() may be called before HAL_I2S_Init() in HAL_I2S_STATE_RESET
544 * to register callbacks for HAL_I2S_MSPINIT_CB_ID and HAL_I2S_MSPDEINIT_CB_ID
545 * @retval HAL status
546 */
HAL_I2S_RegisterCallback(I2S_HandleTypeDef * hi2s,HAL_I2S_CallbackIDTypeDef CallbackID,pI2S_CallbackTypeDef pCallback)547 HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
548 pI2S_CallbackTypeDef pCallback)
549 {
550 HAL_StatusTypeDef status = HAL_OK;
551
552 if (pCallback == NULL)
553 {
554 /* Update the error code */
555 hi2s->ErrorCode |= HAL_I2S_ERROR_INVALID_CALLBACK;
556
557 return HAL_ERROR;
558 }
559
560 if (HAL_I2S_STATE_READY == hi2s->State)
561 {
562 switch (CallbackID)
563 {
564 case HAL_I2S_TX_COMPLETE_CB_ID :
565 hi2s->TxCpltCallback = pCallback;
566 break;
567
568 case HAL_I2S_RX_COMPLETE_CB_ID :
569 hi2s->RxCpltCallback = pCallback;
570 break;
571
572 case HAL_I2S_TX_RX_COMPLETE_CB_ID :
573 hi2s->TxRxCpltCallback = pCallback;
574 break;
575
576 case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
577 hi2s->TxHalfCpltCallback = pCallback;
578 break;
579
580 case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
581 hi2s->RxHalfCpltCallback = pCallback;
582 break;
583
584
585 case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID :
586 hi2s->TxRxHalfCpltCallback = pCallback;
587 break;
588
589 case HAL_I2S_ERROR_CB_ID :
590 hi2s->ErrorCallback = pCallback;
591 break;
592
593 case HAL_I2S_MSPINIT_CB_ID :
594 hi2s->MspInitCallback = pCallback;
595 break;
596
597 case HAL_I2S_MSPDEINIT_CB_ID :
598 hi2s->MspDeInitCallback = pCallback;
599 break;
600
601 default :
602 /* Update the error code */
603 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
604
605 /* Return error status */
606 status = HAL_ERROR;
607 break;
608 }
609 }
610 else if (HAL_I2S_STATE_RESET == hi2s->State)
611 {
612 switch (CallbackID)
613 {
614 case HAL_I2S_MSPINIT_CB_ID :
615 hi2s->MspInitCallback = pCallback;
616 break;
617
618 case HAL_I2S_MSPDEINIT_CB_ID :
619 hi2s->MspDeInitCallback = pCallback;
620 break;
621
622 default :
623 /* Update the error code */
624 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
625
626 /* Return error status */
627 status = HAL_ERROR;
628 break;
629 }
630 }
631 else
632 {
633 /* Update the error code */
634 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
635
636 /* Return error status */
637 status = HAL_ERROR;
638 }
639
640 return status;
641 }
642
643 /**
644 * @brief Unregister an I2S Callback
645 * I2S callback is redirected to the weak predefined callback
646 * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
647 * the configuration information for the specified I2S.
648 * @param CallbackID ID of the callback to be unregistered
649 * @note The HAL_I2S_UnRegisterCallback() may be called before HAL_I2S_Init() in HAL_I2S_STATE_RESET
650 * to un-register callbacks for HAL_I2S_MSPINIT_CB_ID and HAL_I2S_MSPDEINIT_CB_ID
651 * @retval HAL status
652 */
HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef * hi2s,HAL_I2S_CallbackIDTypeDef CallbackID)653 HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
654 {
655 HAL_StatusTypeDef status = HAL_OK;
656
657 if (HAL_I2S_STATE_READY == hi2s->State)
658 {
659 switch (CallbackID)
660 {
661 case HAL_I2S_TX_COMPLETE_CB_ID :
662 hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
663 break;
664
665 case HAL_I2S_RX_COMPLETE_CB_ID :
666 hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
667 break;
668
669 case HAL_I2S_TX_RX_COMPLETE_CB_ID :
670 hi2s->TxRxCpltCallback = HAL_I2SEx_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
671 break;
672
673 case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
674 hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
675 break;
676
677 case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
678 hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
679 break;
680
681 case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID :
682 hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
683 break;
684
685 case HAL_I2S_ERROR_CB_ID :
686 hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
687 break;
688
689 case HAL_I2S_MSPINIT_CB_ID :
690 hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
691 break;
692
693 case HAL_I2S_MSPDEINIT_CB_ID :
694 hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
695 break;
696
697 default :
698 /* Update the error code */
699 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
700
701 /* Return error status */
702 status = HAL_ERROR;
703 break;
704 }
705 }
706 else if (HAL_I2S_STATE_RESET == hi2s->State)
707 {
708 switch (CallbackID)
709 {
710 case HAL_I2S_MSPINIT_CB_ID :
711 hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
712 break;
713
714 case HAL_I2S_MSPDEINIT_CB_ID :
715 hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
716 break;
717
718 default :
719 /* Update the error code */
720 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
721
722 /* Return error status */
723 status = HAL_ERROR;
724 break;
725 }
726 }
727 else
728 {
729 /* Update the error code */
730 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
731
732 /* Return error status */
733 status = HAL_ERROR;
734 }
735
736 return status;
737 }
738 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
739 /**
740 * @}
741 */
742
743 /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
744 * @brief Data transfers functions
745 *
746 @verbatim
747 ===============================================================================
748 ##### IO operation functions #####
749 ===============================================================================
750 [..]
751 This subsection provides a set of functions allowing to manage the I2S data
752 transfers.
753
754 (#) There are two modes of transfer:
755 (++) Blocking mode : The communication is performed in the polling mode.
756 The status of all data processing is returned by the same function
757 after finishing transfer.
758 (++) No-Blocking mode : The communication is performed using Interrupts
759 or DMA. These functions return the status of the transfer startup.
760 The end of the data processing will be indicated through the
761 dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
762 using DMA mode.
763
764 (#) Blocking mode functions are :
765 (++) HAL_I2S_Transmit()
766 (++) HAL_I2S_Receive()
767 (++) HAL_I2SEx_TransmitReceive()
768
769 (#) No-Blocking mode functions with Interrupt are :
770 (++) HAL_I2S_Transmit_IT()
771 (++) HAL_I2S_Receive_IT()
772 (++) HAL_I2SEx_TransmitReceive_IT()
773
774 (#) No-Blocking mode functions with DMA are :
775 (++) HAL_I2S_Transmit_DMA()
776 (++) HAL_I2S_Receive_DMA()
777 (++) HAL_I2SEx_TransmitReceive_DMA()
778
779 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
780 (++) HAL_I2S_TxCpltCallback()
781 (++) HAL_I2S_RxCpltCallback()
782 (++) HAL_I2SEx_TxRxCpltCallback()
783 (++) HAL_I2S_ErrorCallback()
784
785 @endverbatim
786 * @{
787 */
788
789 /**
790 * @brief Transmit an amount of data in blocking mode
791 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
792 * the configuration information for I2S module
793 * @param pData a 16-bit pointer to data buffer.
794 * @param Size number of data sample to be sent:
795 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
796 * configuration phase, the Size parameter means the number of 16-bit data length
797 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
798 * the Size parameter means the number of 16-bit data length.
799 * @param Timeout Timeout duration
800 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
801 * between Master and Slave(example: audio streaming).
802 * @retval HAL status
803 */
HAL_I2S_Transmit(I2S_HandleTypeDef * hi2s,const uint16_t * pData,uint16_t Size,uint32_t Timeout)804 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size, uint32_t Timeout)
805 {
806 #if defined (__GNUC__)
807 __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->TXDR));
808 #endif /* __GNUC__ */
809 uint32_t tickstart;
810
811 if ((pData == NULL) || (Size == 0UL))
812 {
813 return HAL_ERROR;
814 }
815
816 if (hi2s->State != HAL_I2S_STATE_READY)
817 {
818 return HAL_BUSY;
819 }
820
821 /* Process Locked */
822 __HAL_LOCK(hi2s);
823
824 /* Init tickstart for timeout management*/
825 tickstart = HAL_GetTick();
826
827 /* Set state and reset error code */
828 hi2s->State = HAL_I2S_STATE_BUSY_TX;
829 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
830 hi2s->pTxBuffPtr = (const uint16_t *)pData;
831 hi2s->TxXferSize = Size;
832 hi2s->TxXferCount = Size;
833
834 /* Initialize fields not used in handle to zero */
835 hi2s->pRxBuffPtr = NULL;
836 hi2s->RxXferSize = (uint16_t) 0UL;
837 hi2s->RxXferCount = (uint16_t) 0UL;
838
839 /* Check if the I2S is already enabled */
840 if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
841 {
842 /* Enable I2S peripheral */
843 __HAL_I2S_ENABLE(hi2s);
844 }
845
846 /* Start the transfer */
847 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
848
849
850 /* Wait until TXP flag is set */
851 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXP, SET, tickstart, Timeout) != HAL_OK)
852 {
853 /* Set the error code */
854 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
855 hi2s->State = HAL_I2S_STATE_READY;
856 __HAL_UNLOCK(hi2s);
857 return HAL_TIMEOUT;
858 }
859
860 while (hi2s->TxXferCount > 0UL)
861 {
862 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
863 {
864 /* Transmit data in 32 Bit mode */
865 hi2s->Instance->TXDR = *((const uint32_t *)hi2s->pTxBuffPtr);
866 hi2s->pTxBuffPtr += 2;
867 hi2s->TxXferCount--;
868 }
869 else
870 {
871 /* Transmit data in 16 Bit mode */
872 #if defined (__GNUC__)
873 *ptxdr_16bits = *((const uint16_t *)hi2s->pTxBuffPtr);
874 #else
875 *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((const uint16_t *)hi2s->pTxBuffPtr);
876 #endif /* __GNUC__ */
877
878 hi2s->pTxBuffPtr++;
879 hi2s->TxXferCount--;
880 }
881
882 /* Wait until TXP flag is set */
883 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXP, SET, tickstart, Timeout) != HAL_OK)
884 {
885 /* Set the error code */
886 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
887 hi2s->State = HAL_I2S_STATE_READY;
888 __HAL_UNLOCK(hi2s);
889 return HAL_TIMEOUT;
890 }
891
892 /* Check if an underrun occurs */
893 if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
894 {
895 /* Clear underrun flag */
896 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
897
898 /* Set the error code */
899 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
900 }
901 }
902
903 hi2s->State = HAL_I2S_STATE_READY;
904 __HAL_UNLOCK(hi2s);
905 return HAL_OK;
906 }
907
908 /**
909 * @brief Receive an amount of data in blocking mode
910 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
911 * the configuration information for I2S module
912 * @param pData a 16-bit pointer to data buffer.
913 * @param Size number of data sample to be sent:
914 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
915 * configuration phase, the Size parameter means the number of 16-bit data length
916 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
917 * the Size parameter means the number of 16-bit data length.
918 * @param Timeout Timeout duration
919 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
920 * between Master and Slave(example: audio streaming).
921 * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
922 * in continuous way and as the I2S is not disabled at the end of the I2S transaction.
923 * @retval HAL status
924 */
HAL_I2S_Receive(I2S_HandleTypeDef * hi2s,uint16_t * pData,uint16_t Size,uint32_t Timeout)925 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
926 {
927 #if defined (__GNUC__)
928 __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->RXDR));
929 #endif /* __GNUC__ */
930 uint32_t tickstart;
931
932 if ((pData == NULL) || (Size == 0UL))
933 {
934 return HAL_ERROR;
935 }
936
937 if (hi2s->State != HAL_I2S_STATE_READY)
938 {
939 return HAL_BUSY;
940 }
941
942 /* Process Locked */
943 __HAL_LOCK(hi2s);
944
945 /* Init tickstart for timeout management*/
946 tickstart = HAL_GetTick();
947
948 /* Set state and reset error code */
949 hi2s->State = HAL_I2S_STATE_BUSY_RX;
950 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
951 hi2s->pRxBuffPtr = pData;
952 hi2s->RxXferSize = Size;
953 hi2s->RxXferCount = Size;
954
955 /* Initialize fields not used in handle to zero */
956 hi2s->pTxBuffPtr = NULL;
957 hi2s->TxXferSize = (uint16_t) 0UL;
958 hi2s->TxXferCount = (uint16_t) 0UL;
959
960 /* Check if the I2S is already enabled */
961 if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
962 {
963 /* Enable I2S peripheral */
964 __HAL_I2S_ENABLE(hi2s);
965 }
966
967 /* Start the transfer */
968 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
969
970 /* Receive data */
971 while (hi2s->RxXferCount > 0UL)
972 {
973 /* Wait until RXP flag is set */
974 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXP, SET, tickstart, Timeout) != HAL_OK)
975 {
976 /* Set the error code */
977 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
978 hi2s->State = HAL_I2S_STATE_READY;
979 __HAL_UNLOCK(hi2s);
980 return HAL_TIMEOUT;
981 }
982
983 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
984 {
985 /* Receive data in 32 Bit mode */
986 *((uint32_t *)hi2s->pRxBuffPtr) = hi2s->Instance->RXDR;
987 hi2s->pRxBuffPtr += 2;
988 hi2s->RxXferCount--;
989 }
990 else
991 {
992 /* Receive data in 16 Bit mode */
993 #if defined (__GNUC__)
994 *((uint16_t *)hi2s->pRxBuffPtr) = *prxdr_16bits;
995 #else
996 *((uint16_t *)hi2s->pRxBuffPtr) = *((__IO uint16_t *)&hi2s->Instance->RXDR);
997 #endif /* __GNUC__ */
998 hi2s->pRxBuffPtr++;
999 hi2s->RxXferCount--;
1000 }
1001
1002 /* Check if an overrun occurs */
1003 if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
1004 {
1005 /* Clear overrun flag */
1006 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
1007
1008 /* Set the error code */
1009 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
1010 }
1011 }
1012
1013 hi2s->State = HAL_I2S_STATE_READY;
1014 __HAL_UNLOCK(hi2s);
1015 return HAL_OK;
1016 }
1017
1018 /**
1019 * @brief Full-Duplex Transmit/Receive data in blocking mode.
1020 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1021 * the configuration information for I2S module
1022 * @param pTxData a 16-bit pointer to the Transmit data buffer.
1023 * @param pRxData a 16-bit pointer to the Receive data buffer.
1024 * @param Size number of data sample to be sent:
1025 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1026 * configuration phase, the Size parameter means the number of 16-bit data length
1027 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1028 * the Size parameter means the number of 16-bit data length.
1029 * @param Timeout Timeout duration
1030 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1031 * between Master and Slave(example: audio streaming).
1032 * @retval HAL status
1033 */
1034
HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef * hi2s,const uint16_t * pTxData,uint16_t * pRxData,uint16_t Size,uint32_t Timeout)1035 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
1036 uint16_t Size, uint32_t Timeout)
1037 {
1038 uint32_t tmp_TxXferCount;
1039 uint32_t tmp_RxXferCount;
1040 uint32_t tickstart;
1041
1042 #if defined (__GNUC__)
1043 __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->TXDR));
1044 __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->RXDR));
1045 #endif /* __GNUC__ */
1046
1047 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1048 {
1049 return HAL_ERROR;
1050 }
1051
1052 if (hi2s->State != HAL_I2S_STATE_READY)
1053 {
1054 return HAL_BUSY;
1055 }
1056
1057 /* Process Locked */
1058 __HAL_LOCK(hi2s);
1059
1060 /* Init tickstart for timeout management*/
1061 tickstart = HAL_GetTick();
1062
1063 hi2s->TxXferSize = Size;
1064 hi2s->TxXferCount = Size;
1065 hi2s->pTxBuffPtr = (const uint16_t *)pTxData;
1066 hi2s->RxXferSize = Size;
1067 hi2s->RxXferCount = Size;
1068 hi2s->pRxBuffPtr = pRxData;
1069
1070 tmp_TxXferCount = hi2s->TxXferCount;
1071 tmp_RxXferCount = hi2s->RxXferCount;
1072
1073 /* Set state and reset error code */
1074 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1075 hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
1076
1077 /* Check if the I2S is already enabled */
1078 if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1079 {
1080 /* Enable I2S peripheral */
1081 __HAL_I2S_ENABLE(hi2s);
1082 }
1083
1084 /* Start the transfer */
1085 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
1086
1087 while ((tmp_TxXferCount > 0UL) || (tmp_RxXferCount > 0UL))
1088 {
1089 if ((__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXP) == SET) && (tmp_TxXferCount != 0UL))
1090 {
1091 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
1092 {
1093 /* Transmit data in 32 Bit mode */
1094 hi2s->Instance->TXDR = *((const uint32_t *)hi2s->pTxBuffPtr);
1095 hi2s->pTxBuffPtr += 2;
1096 tmp_TxXferCount--;
1097 }
1098 else
1099 {
1100 /* Transmit data in 16 Bit mode */
1101 #if defined (__GNUC__)
1102 *ptxdr_16bits = *((const uint16_t *)hi2s->pTxBuffPtr);
1103 #else
1104 *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((const uint16_t *)hi2s->pTxBuffPtr);
1105 #endif /* __GNUC__ */
1106
1107 hi2s->pTxBuffPtr++;
1108 tmp_TxXferCount--;
1109 }
1110
1111 /* Check if an underrun occurs */
1112 if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
1113 {
1114 /* Clear underrun flag */
1115 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
1116
1117 /* Set the error code */
1118 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
1119 }
1120 }
1121
1122 if ((__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXP) == SET) && (tmp_RxXferCount != 0UL))
1123 {
1124 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
1125 {
1126 /* Receive data in 32 Bit mode */
1127 *((uint32_t *)hi2s->pRxBuffPtr) = hi2s->Instance->RXDR;
1128 hi2s->pRxBuffPtr += 2;
1129 tmp_RxXferCount--;
1130 }
1131 else
1132 {
1133 /* Receive data in 16 Bit mode */
1134 #if defined (__GNUC__)
1135 *((uint16_t *)hi2s->pRxBuffPtr) = *prxdr_16bits;
1136 #else
1137 *((uint16_t *)hi2s->pRxBuffPtr) = *((__IO uint16_t *)&hi2s->Instance->RXDR);
1138 #endif /* __GNUC__ */
1139 hi2s->pRxBuffPtr++;
1140 tmp_RxXferCount--;
1141 }
1142
1143 /* Check if an overrun occurs */
1144 if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
1145 {
1146 /* Clear overrun flag */
1147 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
1148
1149 /* Set the error code */
1150 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
1151 }
1152 }
1153
1154 /* Timeout management */
1155 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1156 {
1157 /* Set the error code */
1158 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
1159 hi2s->State = HAL_I2S_STATE_READY;
1160 __HAL_UNLOCK(hi2s);
1161 return HAL_TIMEOUT;
1162 }
1163 }
1164
1165 hi2s->State = HAL_I2S_STATE_READY;
1166 __HAL_UNLOCK(hi2s);
1167 return HAL_OK;
1168 }
1169
1170 /**
1171 * @brief Transmit an amount of data in non-blocking mode with Interrupt
1172 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1173 * the configuration information for I2S module
1174 * @param pData a 16-bit pointer to data buffer.
1175 * @param Size number of data sample to be sent:
1176 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1177 * configuration phase, the Size parameter means the number of 16-bit data length
1178 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1179 * the Size parameter means the number of 16-bit data length.
1180 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1181 * between Master and Slave(example: audio streaming).
1182 * @retval HAL status
1183 */
HAL_I2S_Transmit_IT(I2S_HandleTypeDef * hi2s,const uint16_t * pData,uint16_t Size)1184 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size)
1185 {
1186 if ((pData == NULL) || (Size == 0UL))
1187 {
1188 return HAL_ERROR;
1189 }
1190
1191 if (hi2s->State != HAL_I2S_STATE_READY)
1192 {
1193 return HAL_BUSY;
1194 }
1195
1196 /* Process Locked */
1197 __HAL_LOCK(hi2s);
1198
1199 /* Set state and reset error code */
1200 hi2s->State = HAL_I2S_STATE_BUSY_TX;
1201 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1202 hi2s->pTxBuffPtr = (const uint16_t *)pData;
1203 hi2s->TxXferSize = Size;
1204 hi2s->TxXferCount = Size;
1205
1206 /* Initialize fields not used in handle to zero */
1207 hi2s->pRxBuffPtr = NULL;
1208 hi2s->RxXferSize = (uint16_t) 0UL;
1209 hi2s->RxXferCount = (uint16_t) 0UL;
1210
1211 /* Set the function for IT treatment */
1212 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
1213 {
1214 hi2s->TxISR = I2S_Transmit_32Bit_IT;
1215 }
1216 else
1217 {
1218 hi2s->TxISR = I2S_Transmit_16Bit_IT;
1219 }
1220
1221 /* Check if the I2S is already enabled */
1222 if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1223 {
1224 /* Enable I2S peripheral */
1225 __HAL_I2S_ENABLE(hi2s);
1226 }
1227
1228 /* Enable TXP and UDR interrupt */
1229 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_UDR));
1230
1231 /* Enable TIFRE interrupt if the mode is Slave */
1232 if (hi2s->Init.Mode == I2S_MODE_SLAVE_TX)
1233 {
1234 __HAL_I2S_ENABLE_IT(hi2s, I2S_IT_FRE);
1235 }
1236
1237 /* Start the transfer */
1238 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
1239
1240 __HAL_UNLOCK(hi2s);
1241 return HAL_OK;
1242 }
1243
1244 /**
1245 * @brief Receive an amount of data in non-blocking mode with Interrupt
1246 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1247 * the configuration information for I2S module
1248 * @param pData a 16-bit pointer to the Receive data buffer.
1249 * @param Size number of data sample to be sent:
1250 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1251 * configuration phase, the Size parameter means the number of 16-bit data length
1252 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1253 * the Size parameter means the number of 16-bit data length.
1254 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1255 * between Master and Slave(example: audio streaming).
1256 * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization
1257 * between Master and Slave otherwise the I2S interrupt should be optimized.
1258 * @retval HAL status
1259 */
HAL_I2S_Receive_IT(I2S_HandleTypeDef * hi2s,uint16_t * pData,uint16_t Size)1260 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
1261 {
1262 if ((pData == NULL) || (Size == 0UL))
1263 {
1264 return HAL_ERROR;
1265 }
1266
1267 if (hi2s->State != HAL_I2S_STATE_READY)
1268 {
1269 return HAL_BUSY;
1270 }
1271
1272 /* Process Locked */
1273 __HAL_LOCK(hi2s);
1274
1275 /* Set state and reset error code */
1276 hi2s->State = HAL_I2S_STATE_BUSY_RX;
1277 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1278 hi2s->pRxBuffPtr = pData;
1279 hi2s->RxXferSize = Size;
1280 hi2s->RxXferCount = Size;
1281
1282 /* Initialize fields not used in handle to zero */
1283 hi2s->pTxBuffPtr = NULL;
1284 hi2s->TxXferSize = (uint16_t) 0UL;
1285 hi2s->TxXferCount = (uint16_t) 0UL;
1286
1287 /* Set the function for IT treatment */
1288 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
1289 {
1290 hi2s->RxISR = I2S_Receive_32Bit_IT;
1291 }
1292 else
1293 {
1294 hi2s->RxISR = I2S_Receive_16Bit_IT;
1295 }
1296
1297 /* Check if the I2S is already enabled */
1298 if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1299 {
1300 /* Enable I2S peripheral */
1301 __HAL_I2S_ENABLE(hi2s);
1302 }
1303 /* Enable RXP and ERR interrupt */
1304 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_OVR));
1305
1306 /* Enable TIFRE interrupt if the mode is Slave */
1307 if (hi2s->Init.Mode == I2S_MODE_SLAVE_RX)
1308 {
1309 __HAL_I2S_ENABLE_IT(hi2s, I2S_IT_FRE);
1310 }
1311
1312 /* Start the transfer */
1313 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
1314
1315 __HAL_UNLOCK(hi2s);
1316 return HAL_OK;
1317 }
1318
1319 /**
1320 * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
1321 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1322 * the configuration information for I2S module
1323 * @param pTxData a 16-bit pointer to the Transmit data buffer.
1324 * @param pRxData a 16-bit pointer to the Receive data buffer.
1325 * @param Size number of data sample to be sent:
1326 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1327 * configuration phase, the Size parameter means the number of 16-bit data length
1328 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1329 * the Size parameter means the number of 16-bit data length.
1330 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1331 * between Master and Slave(example: audio streaming).
1332 * @retval HAL status
1333 */
HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef * hi2s,const uint16_t * pTxData,uint16_t * pRxData,uint16_t Size)1334 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
1335 uint16_t Size)
1336 {
1337 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1338 {
1339 return HAL_ERROR;
1340 }
1341
1342 if (hi2s->State != HAL_I2S_STATE_READY)
1343 {
1344 return HAL_BUSY;
1345 }
1346
1347 /* Process Locked */
1348 __HAL_LOCK(hi2s);
1349
1350 hi2s->pTxBuffPtr = (const uint16_t *)pTxData;
1351 hi2s->pRxBuffPtr = pRxData;
1352
1353 hi2s->TxXferSize = Size;
1354 hi2s->TxXferCount = Size;
1355 hi2s->RxXferSize = Size;
1356 hi2s->RxXferCount = Size;
1357
1358 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1359 hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
1360
1361
1362 /* Set the function for IT treatment */
1363 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
1364 {
1365 hi2s->TxISR = I2S_Transmit_32Bit_IT;
1366 hi2s->RxISR = I2S_Receive_32Bit_IT;
1367 }
1368 else
1369 {
1370 hi2s->TxISR = I2S_Transmit_16Bit_IT;
1371 hi2s->RxISR = I2S_Receive_16Bit_IT;
1372 }
1373
1374 /* Check if the I2S is already enabled */
1375 if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1376 {
1377 /* Enable I2S peripheral */
1378 __HAL_I2S_ENABLE(hi2s);
1379 }
1380
1381 /* Enable TXP, RXP, DXP, UDR, OVR interrupts */
1382 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_DXP | I2S_IT_UDR | I2S_IT_OVR));
1383
1384 /* Enable TIFRE interrupt if the mode is Slave */
1385 if (hi2s->Init.Mode == I2S_MODE_SLAVE_FULLDUPLEX)
1386 {
1387 __HAL_I2S_ENABLE_IT(hi2s, I2S_IT_FRE);
1388 }
1389
1390 /* Start the transfer */
1391 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
1392
1393 __HAL_UNLOCK(hi2s);
1394 return HAL_OK;
1395
1396 }
1397
1398 /**
1399 * @brief Transmit an amount of data in non-blocking mode with DMA
1400 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1401 * the configuration information for I2S module
1402 * @param pData a 16-bit pointer to the Transmit data buffer.
1403 * @param Size number of data sample to be sent:
1404 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1405 * configuration phase, the Size parameter means the number of 16-bit data length
1406 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1407 * the Size parameter means the number of 16-bit data length.
1408 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1409 * between Master and Slave(example: audio streaming).
1410 * @retval HAL status
1411 */
HAL_I2S_Transmit_DMA(I2S_HandleTypeDef * hi2s,const uint16_t * pData,uint16_t Size)1412 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size)
1413 {
1414 HAL_StatusTypeDef errorcode;
1415
1416 if ((pData == NULL) || (Size == 0UL))
1417 {
1418 return HAL_ERROR;
1419 }
1420
1421 if (hi2s->State != HAL_I2S_STATE_READY)
1422 {
1423 return HAL_BUSY;
1424 }
1425
1426 /* Process Locked */
1427 __HAL_LOCK(hi2s);
1428
1429 /* Set state and reset error code */
1430 hi2s->State = HAL_I2S_STATE_BUSY_TX;
1431 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1432 hi2s->pTxBuffPtr = (const uint16_t *)pData;
1433 hi2s->TxXferSize = Size;
1434 hi2s->TxXferCount = Size;
1435
1436 /* Init field not used in handle to zero */
1437 hi2s->pRxBuffPtr = NULL;
1438 hi2s->RxXferSize = (uint16_t)0UL;
1439 hi2s->RxXferCount = (uint16_t)0UL;
1440
1441 /* Set the I2S Tx DMA Half transfer complete callback */
1442 hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
1443
1444 /* Set the I2S Tx DMA transfer complete callback */
1445 hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
1446
1447 /* Set the DMA error callback */
1448 hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
1449
1450 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B_EXTENDED))
1451 {
1452 hi2s->TxXferCount = Size * 2U;
1453 }
1454 else
1455 {
1456 hi2s->TxXferCount = Size * 4U;
1457 }
1458
1459 /* Enable the Tx DMA Stream/Channel */
1460 if ((hi2s->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
1461 {
1462 if (hi2s->hdmatx->LinkedListQueue != NULL)
1463 {
1464 /* Set DMA data size */
1465 hi2s->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2s->TxXferCount;
1466
1467 /* Set DMA source address */
1468 hi2s->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2s->pTxBuffPtr;
1469
1470 /* Set DMA destination address */
1471 hi2s->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hi2s->Instance->TXDR;
1472
1473 errorcode = HAL_DMAEx_List_Start_IT(hi2s->hdmatx);
1474 }
1475 else
1476 {
1477 /* Update SPI error code */
1478 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1479
1480 /* Unlock the process */
1481 __HAL_UNLOCK(hi2s);
1482
1483 hi2s->State = HAL_I2S_STATE_READY;
1484 errorcode = HAL_ERROR;
1485 return errorcode;
1486 }
1487 }
1488 else
1489 {
1490 errorcode = HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR,
1491 hi2s->TxXferCount);
1492 }
1493
1494 /* Check status */
1495 if (errorcode != HAL_OK)
1496 {
1497 /* Update I2S error code */
1498 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1499 hi2s->State = HAL_I2S_STATE_READY;
1500
1501 __HAL_UNLOCK(hi2s);
1502 errorcode = HAL_ERROR;
1503 return errorcode;
1504 }
1505
1506 /* Check if the I2S Tx request is already enabled */
1507 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN))
1508 {
1509 /* Enable Tx DMA Request */
1510 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
1511 }
1512
1513 /* Check if the I2S is already enabled */
1514 if (HAL_IS_BIT_CLR(hi2s->Instance->CR1, SPI_CR1_SPE))
1515 {
1516 /* Enable I2S peripheral */
1517 __HAL_I2S_ENABLE(hi2s);
1518 }
1519
1520 /* Start the transfer */
1521 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
1522
1523 __HAL_UNLOCK(hi2s);
1524 return errorcode;
1525 }
1526
1527 /**
1528 * @brief Receive an amount of data in non-blocking mode with DMA
1529 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1530 * the configuration information for I2S module
1531 * @param pData a 16-bit pointer to the Receive data buffer.
1532 * @param Size number of data sample to be sent:
1533 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1534 * configuration phase, the Size parameter means the number of 16-bit data length
1535 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1536 * the Size parameter means the number of 16-bit data length.
1537 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1538 * between Master and Slave(example: audio streaming).
1539 * @retval HAL status
1540 */
HAL_I2S_Receive_DMA(I2S_HandleTypeDef * hi2s,uint16_t * pData,uint16_t Size)1541 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
1542 {
1543 HAL_StatusTypeDef errorcode;
1544
1545 if ((pData == NULL) || (Size == 0UL))
1546 {
1547 return HAL_ERROR;
1548 }
1549
1550 if (hi2s->State != HAL_I2S_STATE_READY)
1551 {
1552 return HAL_BUSY;
1553 }
1554
1555 /* Process Locked */
1556 __HAL_LOCK(hi2s);
1557
1558 /* Set state and reset error code */
1559 hi2s->State = HAL_I2S_STATE_BUSY_RX;
1560 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1561 hi2s->pRxBuffPtr = pData;
1562 hi2s->RxXferSize = Size;
1563 hi2s->RxXferCount = Size;
1564
1565 /* Init field not used in handle to zero */
1566 hi2s->pTxBuffPtr = NULL;
1567 hi2s->TxXferSize = (uint16_t)0UL;
1568 hi2s->TxXferCount = (uint16_t)0UL;
1569
1570
1571 /* Set the I2S Rx DMA Half transfer complete callback */
1572 hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
1573
1574 /* Set the I2S Rx DMA transfer complete callback */
1575 hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
1576
1577 /* Set the DMA error callback */
1578 hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
1579
1580 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B_EXTENDED))
1581 {
1582 hi2s->RxXferCount = Size * 2U;
1583 }
1584 else
1585 {
1586 hi2s->RxXferCount = Size * 4U;
1587 }
1588
1589 /* Enable the Rx DMA Stream/Channel */
1590 if ((hi2s->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
1591 {
1592 if (hi2s->hdmarx->LinkedListQueue != NULL)
1593 {
1594 /* Set DMA data size */
1595 hi2s->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2s->RxXferCount;
1596
1597 /* Set DMA source address */
1598 hi2s->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hi2s->Instance->RXDR;
1599
1600 /* Set DMA destination address */
1601 hi2s->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hi2s->pRxBuffPtr;
1602
1603 errorcode = HAL_DMAEx_List_Start_IT(hi2s->hdmarx);
1604 }
1605 else
1606 {
1607 /* Update SPI error code */
1608 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1609
1610 /* Unlock the process */
1611 __HAL_UNLOCK(hi2s);
1612
1613 hi2s->State = HAL_I2S_STATE_READY;
1614 errorcode = HAL_ERROR;
1615 return errorcode;
1616 }
1617 }
1618 else
1619 {
1620 errorcode = HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr,
1621 hi2s->RxXferCount);
1622 }
1623
1624 /* Check status */
1625 if (errorcode != HAL_OK)
1626 {
1627 /* Update I2S error code */
1628 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1629 hi2s->State = HAL_I2S_STATE_READY;
1630 errorcode = HAL_ERROR;
1631 __HAL_UNLOCK(hi2s);
1632 return errorcode;
1633 }
1634
1635 /* Check if the I2S Rx request is already enabled */
1636 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN))
1637 {
1638 /* Enable Rx DMA Request */
1639 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
1640 }
1641
1642 /* Check if the I2S is already enabled */
1643 if (HAL_IS_BIT_CLR(hi2s->Instance->CR1, SPI_CR1_SPE))
1644 {
1645 /* Enable I2S peripheral */
1646 __HAL_I2S_ENABLE(hi2s);
1647 }
1648
1649 /* Start the transfer */
1650 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
1651
1652 __HAL_UNLOCK(hi2s);
1653 return errorcode;
1654 }
1655
1656 /**
1657 * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA
1658 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1659 * the configuration information for I2S module
1660 * @param pTxData a 16-bit pointer to the Transmit data buffer.
1661 * @param pRxData a 16-bit pointer to the Receive data buffer.
1662 * @param Size number of data sample to be sent:
1663 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1664 * configuration phase, the Size parameter means the number of 16-bit data length
1665 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1666 * the Size parameter means the number of 16-bit data length.
1667 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1668 * between Master and Slave(example: audio streaming).
1669 * @retval HAL status
1670 */
HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef * hi2s,const uint16_t * pTxData,uint16_t * pRxData,uint16_t Size)1671 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
1672 uint16_t Size)
1673 {
1674 HAL_StatusTypeDef errorcode;
1675
1676
1677 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1678 {
1679 return HAL_ERROR;
1680 }
1681
1682 if (hi2s->State != HAL_I2S_STATE_READY)
1683 {
1684 return HAL_BUSY;
1685 }
1686
1687 /* Process Locked */
1688 __HAL_LOCK(hi2s);
1689
1690 hi2s->pTxBuffPtr = (const uint16_t *)pTxData;
1691 hi2s->pRxBuffPtr = pRxData;
1692
1693 hi2s->TxXferSize = Size;
1694 hi2s->TxXferCount = Size;
1695 hi2s->RxXferSize = Size;
1696 hi2s->RxXferCount = Size;
1697
1698 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1699 hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
1700
1701 /* Reset the Tx/Rx DMA bits */
1702 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
1703
1704 /* Set the I2S Rx DMA Half transfer complete callback */
1705 hi2s->hdmarx->XferHalfCpltCallback = I2SEx_DMATxRxHalfCplt;
1706
1707 /* Set the I2S Rx DMA transfer complete callback */
1708 hi2s->hdmarx->XferCpltCallback = I2SEx_DMATxRxCplt;
1709
1710 /* Set the I2S Rx DMA error callback */
1711 hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
1712 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B_EXTENDED))
1713 {
1714 hi2s->TxXferCount = Size * 2U;
1715 }
1716 else
1717 {
1718 hi2s->TxXferCount = Size * 4U;
1719 }
1720
1721 /* Enable the Tx DMA Stream/Channel */
1722 if ((hi2s->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
1723 {
1724 if (hi2s->hdmatx->LinkedListQueue != NULL)
1725 {
1726 /* Set DMA data size */
1727 hi2s->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2s->TxXferCount;
1728
1729 /* Set DMA source address */
1730 hi2s->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2s->pTxBuffPtr;
1731
1732 /* Set DMA destination address */
1733 hi2s->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hi2s->Instance->TXDR;
1734
1735 errorcode = HAL_DMAEx_List_Start_IT(hi2s->hdmatx);
1736 }
1737 else
1738 {
1739 /* Update SPI error code */
1740 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1741
1742 /* Unlock the process */
1743 __HAL_UNLOCK(hi2s);
1744
1745 hi2s->State = HAL_I2S_STATE_READY;
1746 errorcode = HAL_ERROR;
1747 return errorcode;
1748 }
1749 }
1750 else
1751 {
1752 errorcode = HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR,
1753 hi2s->TxXferCount);
1754 }
1755
1756 /* Check status */
1757 if (errorcode != HAL_OK)
1758 {
1759 /* Update I2S error code */
1760 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1761 hi2s->State = HAL_I2S_STATE_READY;
1762
1763 __HAL_UNLOCK(hi2s);
1764 errorcode = HAL_ERROR;
1765 return errorcode;
1766 }
1767
1768 /* Check if the I2S Tx request is already enabled */
1769 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN))
1770 {
1771 /* Enable Tx DMA Request */
1772 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
1773 }
1774
1775 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B_EXTENDED))
1776 {
1777 hi2s->RxXferCount = Size * 2U;
1778 }
1779 else
1780 {
1781 hi2s->RxXferCount = Size * 4U;
1782 }
1783
1784 /* Enable the Rx DMA Stream/Channel */
1785 if ((hi2s->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
1786 {
1787 if (hi2s->hdmarx->LinkedListQueue != NULL)
1788 {
1789 /* Set DMA data size */
1790 hi2s->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2s->RxXferCount;
1791
1792 /* Set DMA source address */
1793 hi2s->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hi2s->Instance->RXDR;
1794
1795 /* Set DMA destination address */
1796 hi2s->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hi2s->pRxBuffPtr;
1797
1798 errorcode = HAL_DMAEx_List_Start_IT(hi2s->hdmarx);
1799 }
1800 else
1801 {
1802 /* Update SPI error code */
1803 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1804
1805 /* Unlock the process */
1806 __HAL_UNLOCK(hi2s);
1807
1808 hi2s->State = HAL_I2S_STATE_READY;
1809 errorcode = HAL_ERROR;
1810 return errorcode;
1811 }
1812 }
1813 else
1814 {
1815 errorcode = HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr,
1816 hi2s->RxXferCount);
1817 }
1818
1819 /* Check status */
1820 if (errorcode != HAL_OK)
1821 {
1822 /* Update I2S error code */
1823 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1824 hi2s->State = HAL_I2S_STATE_READY;
1825 errorcode = HAL_ERROR;
1826 __HAL_UNLOCK(hi2s);
1827 return errorcode;
1828 }
1829
1830 /* Check if the I2S Rx request is already enabled */
1831 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN))
1832 {
1833 /* Enable Rx DMA Request */
1834 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
1835 }
1836
1837 /* Check if the I2S is already enabled */
1838 if (HAL_IS_BIT_CLR(hi2s->Instance->CR1, SPI_CR1_SPE))
1839 {
1840 /* Enable I2S peripheral */
1841 __HAL_I2S_ENABLE(hi2s);
1842 }
1843
1844 /* Start the transfer */
1845 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
1846
1847 __HAL_UNLOCK(hi2s);
1848 return errorcode;
1849 }
1850
1851 /**
1852 * @brief Pauses the audio DMA Stream/Channel playing from the Media.
1853 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1854 * the configuration information for I2S module
1855 * @retval HAL status
1856 */
HAL_I2S_DMAPause(I2S_HandleTypeDef * hi2s)1857 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
1858 {
1859 /* Process Locked */
1860 __HAL_LOCK(hi2s);
1861
1862 uint32_t tickstart;
1863
1864 /* Get tick */
1865 tickstart = HAL_GetTick();
1866
1867
1868 /* Check if the I2S peripheral is in master mode */
1869 if (IS_I2S_MASTER(hi2s->Init.Mode))
1870 {
1871 /* Check if there is a transfer on-going */
1872 if (HAL_IS_BIT_SET(hi2s->Instance->CR1, SPI_CR1_CSTART) == 0UL)
1873 {
1874 /* Set error code to no on going transfer */
1875 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_NO_OGT);
1876 hi2s->State = HAL_I2S_STATE_READY;
1877
1878 __HAL_UNLOCK(hi2s);
1879 return HAL_ERROR;
1880 }
1881
1882 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSUSP);
1883
1884 while (HAL_IS_BIT_SET(hi2s->Instance->CR1, SPI_CR1_CSTART) != 0UL)
1885 {
1886 if ((((HAL_GetTick() - tickstart) >= I2S_TIMEOUT) && (I2S_TIMEOUT != HAL_MAX_DELAY)) || (I2S_TIMEOUT == 0U))
1887 {
1888 /* Set the I2S State ready */
1889 hi2s->State = HAL_I2S_STATE_READY;
1890
1891 /* Process Unlocked */
1892 __HAL_UNLOCK(hi2s);
1893
1894 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
1895 hi2s->State = HAL_I2S_STATE_READY;
1896 return HAL_TIMEOUT;
1897 }
1898 }
1899
1900 /* Disable I2S peripheral */
1901 __HAL_I2S_DISABLE(hi2s);
1902
1903 hi2s->State = HAL_I2S_STATE_READY;
1904
1905 /* Process Unlocked */
1906 __HAL_UNLOCK(hi2s);
1907
1908 return HAL_OK;
1909 }
1910 else
1911 {
1912 /* Set error code to not supported */
1913 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_NOT_SUPPORTED);
1914 hi2s->State = HAL_I2S_STATE_READY;
1915
1916 /* Process Unlocked */
1917 __HAL_UNLOCK(hi2s);
1918
1919 return HAL_ERROR;
1920 }
1921 }
1922
1923 /**
1924 * @brief Resumes the audio DMA Stream/Channel playing from the Media.
1925 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1926 * the configuration information for I2S module
1927 * @retval HAL status
1928 */
HAL_I2S_DMAResume(I2S_HandleTypeDef * hi2s)1929 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
1930 {
1931 /* Process Locked */
1932 __HAL_LOCK(hi2s);
1933
1934 if (hi2s->State != HAL_I2S_STATE_READY)
1935 {
1936 hi2s->State = HAL_I2S_STATE_READY;
1937
1938 __HAL_UNLOCK(hi2s);
1939 return HAL_ERROR;
1940 }
1941
1942 /* Set state and reset error code */
1943 hi2s->State = HAL_I2S_STATE_BUSY;
1944 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1945
1946 /* Enable I2S peripheral */
1947 __HAL_I2S_ENABLE(hi2s);
1948
1949 /* Start the transfer */
1950 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
1951
1952 /* Process Unlocked */
1953 __HAL_UNLOCK(hi2s);
1954
1955 return HAL_OK;
1956 }
1957
1958 /**
1959 * @brief Stops the audio DMA Stream/Channel playing from the Media.
1960 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1961 * the configuration information for I2S module
1962 * @retval HAL status
1963 */
HAL_I2S_DMAStop(I2S_HandleTypeDef * hi2s)1964 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
1965 {
1966 HAL_StatusTypeDef errorcode = HAL_OK;
1967 /* The Lock is not implemented on this API to allow the user application
1968 to call the HAL I2S API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
1969 when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated
1970 and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
1971 */
1972
1973 /* Disable the I2S Tx/Rx DMA requests */
1974 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
1975 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
1976
1977 /* Abort the I2S DMA tx Stream/Channel */
1978 if (hi2s->hdmatx != NULL)
1979 {
1980 /* Disable the I2S DMA tx Stream/Channel */
1981 if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
1982 {
1983 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1984 errorcode = HAL_ERROR;
1985 }
1986 }
1987
1988 /* Abort the I2S DMA rx Stream/Channel */
1989 if (hi2s->hdmarx != NULL)
1990 {
1991 /* Disable the I2S DMA rx Stream/Channel */
1992 if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
1993 {
1994 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1995 errorcode = HAL_ERROR;
1996 }
1997 }
1998
1999 /* Disable I2S peripheral */
2000 __HAL_I2S_DISABLE(hi2s);
2001
2002 hi2s->State = HAL_I2S_STATE_READY;
2003
2004 return errorcode;
2005 }
2006
2007 /**
2008 * @brief Enable the SDO/SDI alternate functions inversion feature for the dedicated I2Sx.
2009 * Original SDI pin becomes SDO and original SDO pin becomes SDI (Also applicable
2010 * on half-duplex mode in case of single data line).
2011 * @param hi2s Pointer to a @ref I2S_HandleTypeDef structure that contains
2012 * the configuration information for I2S module.
2013 * @retval HAL_ERROR When IO is locked, handle is NULL or wrong state.
2014 * @retval HAL_OK IO Swap feature enabled successfully.
2015 */
HAL_I2S_EnableIOSwap(I2S_HandleTypeDef * hi2s)2016 HAL_StatusTypeDef HAL_I2S_EnableIOSwap(I2S_HandleTypeDef *hi2s)
2017 {
2018 /* Check the I2S handle allocation */
2019 if (hi2s == NULL)
2020 {
2021 return HAL_ERROR;
2022 }
2023
2024 /* Check the global state */
2025 if (hi2s->State != HAL_I2S_STATE_READY)
2026 {
2027 return HAL_ERROR;
2028 }
2029
2030 /* Check for IOLock */
2031 if (READ_BIT(hi2s->Instance->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK))
2032 {
2033 return HAL_ERROR;
2034 }
2035
2036 /* Check if the I2S is already enabled */
2037 if ((hi2s->Instance->CR1 & SPI_CR1_SPE) == SPI_CR1_SPE)
2038 {
2039 /* Disable I2S peripheral */
2040 __HAL_I2S_DISABLE(hi2s);
2041 }
2042
2043 /* Enable IO Swap feature */
2044 SET_BIT(hi2s->Instance->CFG2, SPI_CFG2_IOSWP);
2045
2046 return HAL_OK;
2047 }
2048
2049 /**
2050 * @brief Disable the SDO/SDI alternate functions inversion feature for the dedicated I2Sx.
2051 * Original SDI pin becomes SDI and original SDO pin becomes SDO (Also applicable
2052 * on half-duplex mode in case of single data line).
2053 * @param hi2s Pointer to a @ref I2S_HandleTypeDef structure that contains
2054 * the configuration information for I2S module.
2055 * @retval HAL_ERROR When IO is locked, handle is NULL or wrong state.
2056 * @retval HAL_OK IO Swap feature disabled successfully.
2057 */
HAL_I2S_DisableIOSwap(I2S_HandleTypeDef * hi2s)2058 HAL_StatusTypeDef HAL_I2S_DisableIOSwap(I2S_HandleTypeDef *hi2s)
2059 {
2060 /* Check the I2S handle allocation */
2061 if (hi2s == NULL)
2062 {
2063 return HAL_ERROR;
2064 }
2065
2066 /* Check the global state */
2067 if (hi2s->State != HAL_I2S_STATE_READY)
2068 {
2069 return HAL_ERROR;
2070 }
2071
2072 /* Check for IOLock */
2073 if (READ_BIT(hi2s->Instance->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK))
2074 {
2075 return HAL_ERROR;
2076 }
2077
2078 /* Check if the I2S is already enabled */
2079 if ((hi2s->Instance->CR1 & SPI_CR1_SPE) == SPI_CR1_SPE)
2080 {
2081 /* Disable I2S peripheral */
2082 __HAL_I2S_DISABLE(hi2s);
2083 }
2084
2085 /* Disable the IO Swap feature */
2086 CLEAR_BIT(hi2s->Instance->CFG2, SPI_CFG2_IOSWP);
2087
2088 return HAL_OK;
2089 }
2090
2091 /**
2092 * @brief Retrieve the SDO/SDI alternate functions inversion feature status for the dedicated I2Sx.
2093 * @param hi2s Pointer to a @ref I2S_HandleTypeDef structure that contains
2094 * the configuration information for I2S module.
2095 * @retval 1 when I2S IO swap feature is enabled, 0 otherwise, or when hi2s pointer is null.
2096 */
HAL_I2S_IsEnabledIOSwap(const I2S_HandleTypeDef * hi2s)2097 uint32_t HAL_I2S_IsEnabledIOSwap(const I2S_HandleTypeDef *hi2s)
2098 {
2099 /* Check the I2S handle allocation */
2100 if (hi2s == NULL)
2101 {
2102 return 0;
2103 }
2104
2105 return ((READ_BIT(hi2s->Instance->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL);
2106 }
2107
2108 /**
2109 * @brief This function handles I2S interrupt request.
2110 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2111 * the configuration information for I2S module
2112 * @retval None
2113 */
HAL_I2S_IRQHandler(I2S_HandleTypeDef * hi2s)2114 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
2115 {
2116 uint32_t i2sier = hi2s->Instance->IER;
2117 uint32_t i2ssr = hi2s->Instance->SR;
2118 uint32_t trigger = i2sier & i2ssr;
2119
2120 if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
2121 {
2122 /* I2S in mode Receiver ------------------------------------------------*/
2123 if (HAL_IS_BIT_SET(trigger, I2S_FLAG_RXP) && HAL_IS_BIT_CLR(trigger, I2S_FLAG_OVR))
2124 {
2125 hi2s->RxISR(hi2s);
2126 }
2127
2128 /* I2S Overrun error interrupt occurred -------------------------------------*/
2129 if (HAL_IS_BIT_SET(trigger, I2S_FLAG_OVR))
2130 {
2131 /* Disable RXP and ERR interrupt */
2132 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR));
2133
2134 /* Clear Overrun flag */
2135 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
2136
2137 /* Set the I2S State ready */
2138 hi2s->State = HAL_I2S_STATE_READY;
2139
2140
2141 /* Set the error code and execute error callback*/
2142 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
2143 /* Call user error callback */
2144 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2145 hi2s->ErrorCallback(hi2s);
2146 #else
2147 HAL_I2S_ErrorCallback(hi2s);
2148 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2149 }
2150 }
2151
2152 if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
2153 {
2154 /* I2S in mode Transmitter -----------------------------------------------*/
2155 if (HAL_IS_BIT_SET(trigger, I2S_FLAG_TXP) && HAL_IS_BIT_CLR(trigger, I2S_FLAG_UDR))
2156 {
2157 hi2s->TxISR(hi2s);
2158 }
2159
2160 /* I2S Underrun error interrupt occurred --------------------------------*/
2161 if (HAL_IS_BIT_SET(trigger, I2S_FLAG_UDR))
2162 {
2163 /* Disable TXP and ERR interrupt */
2164 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR));
2165
2166 /* Clear Underrun flag */
2167 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
2168
2169 /* Set the I2S State ready */
2170 hi2s->State = HAL_I2S_STATE_READY;
2171
2172 /* Set the error code and execute error callback*/
2173 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
2174 /* Call user error callback */
2175 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2176 hi2s->ErrorCallback(hi2s);
2177 #else
2178 HAL_I2S_ErrorCallback(hi2s);
2179 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2180 }
2181 }
2182 if (hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
2183 {
2184 /* I2S in mode Transmitter -----------------------------------------------*/
2185 if (HAL_IS_BIT_SET(trigger, I2S_FLAG_DXP))
2186 {
2187 hi2s->TxISR(hi2s);
2188 hi2s->RxISR(hi2s);
2189 }
2190 /* I2S in mode Receiver ------------------------------------------------*/
2191 if (HAL_IS_BIT_SET(trigger, I2S_FLAG_RXP) && HAL_IS_BIT_CLR(trigger, I2S_FLAG_DXP))
2192 {
2193 hi2s->RxISR(hi2s);
2194 }
2195 /* I2S in mode Transmitter -----------------------------------------------*/
2196 if (HAL_IS_BIT_SET(trigger, I2S_FLAG_TXP) && HAL_IS_BIT_CLR(trigger, I2S_FLAG_DXP))
2197 {
2198 hi2s->TxISR(hi2s);
2199 }
2200
2201 /* I2S Underrun error interrupt occurred --------------------------------*/
2202 if (HAL_IS_BIT_SET(trigger, I2S_FLAG_UDR))
2203 {
2204 /* Disable TXP, RXP and ERR interrupt */
2205 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_ERR));
2206
2207 /* Clear Underrun flag */
2208 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
2209
2210 /* Set the I2S State ready */
2211 hi2s->State = HAL_I2S_STATE_READY;
2212
2213 /* Set the error code and execute error callback*/
2214 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
2215 /* Call user error callback */
2216 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2217 hi2s->ErrorCallback(hi2s);
2218 #else
2219 HAL_I2S_ErrorCallback(hi2s);
2220 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2221 }
2222
2223 /* I2S Overrun error interrupt occurred -------------------------------------*/
2224 if (HAL_IS_BIT_SET(trigger, I2S_FLAG_OVR))
2225 {
2226 /* Disable TXP, RXP and ERR interrupt */
2227 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_ERR));
2228
2229 /* Clear Overrun flag */
2230 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
2231
2232 /* Set the I2S State ready */
2233 hi2s->State = HAL_I2S_STATE_READY;
2234
2235
2236 /* Set the error code and execute error callback*/
2237 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
2238
2239 /* Call user error callback */
2240 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2241 hi2s->ErrorCallback(hi2s);
2242 #else
2243 HAL_I2S_ErrorCallback(hi2s);
2244 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2245 }
2246 }
2247 }
2248
2249 /**
2250 * @brief Tx Transfer Half completed callbacks
2251 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2252 * the configuration information for I2S module
2253 * @retval None
2254 */
HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef * hi2s)2255 __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
2256 {
2257 /* Prevent unused argument(s) compilation warning */
2258 UNUSED(hi2s);
2259
2260 /* NOTE : This function Should not be modified, when the callback is needed,
2261 the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
2262 */
2263 }
2264
2265 /**
2266 * @brief Tx Transfer completed callbacks
2267 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2268 * the configuration information for I2S module
2269 * @retval None
2270 */
HAL_I2S_TxCpltCallback(I2S_HandleTypeDef * hi2s)2271 __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
2272 {
2273 /* Prevent unused argument(s) compilation warning */
2274 UNUSED(hi2s);
2275
2276 /* NOTE : This function Should not be modified, when the callback is needed,
2277 the HAL_I2S_TxCpltCallback could be implemented in the user file
2278 */
2279 }
2280
2281 /**
2282 * @brief Rx Transfer half completed callbacks
2283 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2284 * the configuration information for I2S module
2285 * @retval None
2286 */
HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef * hi2s)2287 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
2288 {
2289 /* Prevent unused argument(s) compilation warning */
2290 UNUSED(hi2s);
2291
2292 /* NOTE : This function Should not be modified, when the callback is needed,
2293 the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
2294 */
2295 }
2296
2297 /**
2298 * @brief Rx Transfer completed callbacks
2299 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2300 * the configuration information for I2S module
2301 * @retval None
2302 */
HAL_I2S_RxCpltCallback(I2S_HandleTypeDef * hi2s)2303 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
2304 {
2305 /* Prevent unused argument(s) compilation warning */
2306 UNUSED(hi2s);
2307
2308 /* NOTE : This function Should not be modified, when the callback is needed,
2309 the HAL_I2S_RxCpltCallback could be implemented in the user file
2310 */
2311 }
2312
2313 /**
2314 * @brief Rx Transfer half completed callbacks
2315 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2316 * the configuration information for I2S module
2317 * @retval None
2318 */
HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef * hi2s)2319 __weak void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
2320 {
2321 /* Prevent unused argument(s) compilation warning */
2322 UNUSED(hi2s);
2323
2324 /* NOTE : This function Should not be modified, when the callback is needed,
2325 the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
2326 */
2327 }
2328
2329 /**
2330 * @brief Rx Transfer completed callbacks
2331 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2332 * the configuration information for I2S module
2333 * @retval None
2334 */
HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef * hi2s)2335 __weak void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s)
2336 {
2337 /* Prevent unused argument(s) compilation warning */
2338 UNUSED(hi2s);
2339
2340 /* NOTE : This function Should not be modified, when the callback is needed,
2341 the HAL_I2S_RxCpltCallback could be implemented in the user file
2342 */
2343 }
2344
2345 /**
2346 * @brief I2S error callbacks
2347 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2348 * the configuration information for I2S module
2349 * @retval None
2350 */
HAL_I2S_ErrorCallback(I2S_HandleTypeDef * hi2s)2351 __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
2352 {
2353 /* Prevent unused argument(s) compilation warning */
2354 UNUSED(hi2s);
2355
2356 /* NOTE : This function Should not be modified, when the callback is needed,
2357 the HAL_I2S_ErrorCallback could be implemented in the user file
2358 */
2359 }
2360
2361 /**
2362 * @}
2363 */
2364
2365 /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
2366 * @brief Peripheral State functions
2367 *
2368 @verbatim
2369 ===============================================================================
2370 ##### Peripheral State and Errors functions #####
2371 ===============================================================================
2372 [..]
2373 This subsection permits to get in run-time the status of the peripheral
2374 and the data flow.
2375
2376 @endverbatim
2377 * @{
2378 */
2379
2380 /**
2381 * @brief Return the I2S state
2382 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2383 * the configuration information for I2S module
2384 * @retval HAL state
2385 */
HAL_I2S_GetState(const I2S_HandleTypeDef * hi2s)2386 HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s)
2387 {
2388 return hi2s->State;
2389 }
2390
2391 /**
2392 * @brief Return the I2S error code
2393 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2394 * the configuration information for I2S module
2395 * @retval I2S Error Code
2396 */
HAL_I2S_GetError(const I2S_HandleTypeDef * hi2s)2397 uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s)
2398 {
2399 return hi2s->ErrorCode;
2400 }
2401 /**
2402 * @}
2403 */
2404
2405 /**
2406 * @}
2407 */
2408
2409 /** @addtogroup I2S_Private_Functions
2410 * @{
2411 */
2412 /**
2413 * @brief DMA I2S transmit process complete callback
2414 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2415 * the configuration information for the specified DMA module.
2416 * @retval None
2417 */
I2S_DMATxCplt(DMA_HandleTypeDef * hdma)2418 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
2419 {
2420 /* Derogation MISRAC2012-Rule-11.5 */
2421 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2422
2423 /* if DMA is configured in DMA_NORMAL Mode */
2424 if (hdma->Init.Mode == DMA_NORMAL)
2425 {
2426 /* Disable Tx DMA Request */
2427 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
2428
2429 hi2s->TxXferCount = (uint16_t) 0UL;
2430 hi2s->State = HAL_I2S_STATE_READY;
2431 }
2432 /* Call user Tx complete callback */
2433 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2434 hi2s->TxCpltCallback(hi2s);
2435 #else
2436 HAL_I2S_TxCpltCallback(hi2s);
2437 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2438 }
2439
2440 /**
2441 * @brief DMA I2S transmit process half complete callback
2442 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2443 * the configuration information for the specified DMA module.
2444 * @retval None
2445 */
I2S_DMATxHalfCplt(DMA_HandleTypeDef * hdma)2446 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
2447 {
2448 /* Derogation MISRAC2012-Rule-11.5 */
2449 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2450
2451 /* Call user Tx half complete callback */
2452 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2453 hi2s->TxHalfCpltCallback(hi2s);
2454 #else
2455 HAL_I2S_TxHalfCpltCallback(hi2s);
2456 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2457 }
2458
2459 /**
2460 * @brief DMA I2S receive process complete callback
2461 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2462 * the configuration information for the specified DMA module.
2463 * @retval None
2464 */
I2S_DMARxCplt(DMA_HandleTypeDef * hdma)2465 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
2466 {
2467 /* Derogation MISRAC2012-Rule-11.5 */
2468 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2469
2470 /* if DMA is configured in DMA_NORMAL Mode */
2471 if (hdma->Init.Mode == DMA_NORMAL)
2472 {
2473 /* Disable Rx DMA Request */
2474 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
2475 hi2s->RxXferCount = (uint16_t)0UL;
2476 hi2s->State = HAL_I2S_STATE_READY;
2477 }
2478 /* Call user Rx complete callback */
2479 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2480 hi2s->RxCpltCallback(hi2s);
2481 #else
2482 HAL_I2S_RxCpltCallback(hi2s);
2483 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2484 }
2485
2486 /**
2487 * @brief DMA I2S receive process half complete callback
2488 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2489 * the configuration information for the specified DMA module.
2490 * @retval None
2491 */
I2S_DMARxHalfCplt(DMA_HandleTypeDef * hdma)2492 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
2493 {
2494 /* Derogation MISRAC2012-Rule-11.5 */
2495 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2496
2497 /* Call user Rx half complete callback */
2498 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2499 hi2s->RxHalfCpltCallback(hi2s);
2500 #else
2501 HAL_I2S_RxHalfCpltCallback(hi2s);
2502 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2503 }
2504
2505 /**
2506 * @brief DMA I2S transmit receive process complete callback
2507 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2508 * the configuration information for the specified DMA module.
2509 * @retval None
2510 */
I2SEx_DMATxRxCplt(DMA_HandleTypeDef * hdma)2511 static void I2SEx_DMATxRxCplt(DMA_HandleTypeDef *hdma)
2512 {
2513 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2514
2515 /* if DMA is configured in DMA_NORMAL Mode */
2516 if (hdma->Init.Mode == DMA_NORMAL)
2517 {
2518 /* Disable Tx DMA Request */
2519 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
2520 hi2s->TxXferCount = (uint16_t) 0UL;
2521
2522 /* Disable Rx DMA Request */
2523 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
2524 hi2s->RxXferCount = (uint16_t)0UL;
2525
2526 /* Updated HAL State */
2527 hi2s->State = HAL_I2S_STATE_READY;
2528 }
2529
2530 /* Call user TxRx complete callback */
2531 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
2532 hi2s->TxRxCpltCallback(hi2s);
2533 #else
2534 HAL_I2SEx_TxRxCpltCallback(hi2s);
2535 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2536 }
2537
2538 /**
2539 * @brief DMA I2S transmit receive process half complete callback
2540 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2541 * the configuration information for the specified DMA module.
2542 * @retval None
2543 */
I2SEx_DMATxRxHalfCplt(DMA_HandleTypeDef * hdma)2544 static void I2SEx_DMATxRxHalfCplt(DMA_HandleTypeDef *hdma)
2545 {
2546 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2547
2548 /* Call user TxRx Half complete callback */
2549 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
2550 hi2s->TxRxHalfCpltCallback(hi2s);
2551 #else
2552 HAL_I2SEx_TxRxHalfCpltCallback(hi2s);
2553 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2554 }
2555
2556 /**
2557 * @brief DMA I2S communication error callback
2558 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2559 * the configuration information for the specified DMA module.
2560 * @retval None
2561 */
I2S_DMAError(DMA_HandleTypeDef * hdma)2562 static void I2S_DMAError(DMA_HandleTypeDef *hdma)
2563 {
2564 /* Derogation MISRAC2012-Rule-11.5 */
2565 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2566
2567 /* Disable Rx and Tx DMA Request */
2568 CLEAR_BIT(hi2s->Instance->CFG1, (SPI_CFG1_RXDMAEN | SPI_CFG1_TXDMAEN));
2569 hi2s->TxXferCount = (uint16_t) 0UL;
2570 hi2s->RxXferCount = (uint16_t) 0UL;
2571
2572 hi2s->State = HAL_I2S_STATE_READY;
2573
2574 /* Set the error code and execute error callback*/
2575 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
2576 /* Call user error callback */
2577 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2578 hi2s->ErrorCallback(hi2s);
2579 #else
2580 HAL_I2S_ErrorCallback(hi2s);
2581 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2582 }
2583
2584 /**
2585 * @brief Manage the transmission 16-bit in Interrupt context
2586 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2587 * the configuration information for I2S module
2588 * @retval None
2589 */
I2S_Transmit_16Bit_IT(I2S_HandleTypeDef * hi2s)2590 static void I2S_Transmit_16Bit_IT(I2S_HandleTypeDef *hi2s)
2591 {
2592 /* Transmit data */
2593 #if defined (__GNUC__)
2594 __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->TXDR));
2595
2596 *ptxdr_16bits = *((const uint16_t *)hi2s->pTxBuffPtr);
2597 #else
2598 *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((const uint16_t *)hi2s->pTxBuffPtr);
2599 #endif /* __GNUC__ */
2600 hi2s->pTxBuffPtr++;
2601 hi2s->TxXferCount--;
2602
2603 if (hi2s->TxXferCount == 0UL)
2604 {
2605 /* Disable TXP and ERR interrupt */
2606 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR));
2607
2608 if ((hi2s->Init.Mode == I2S_MODE_SLAVE_TX) || (hi2s->Init.Mode == I2S_MODE_MASTER_TX))
2609 {
2610 hi2s->State = HAL_I2S_STATE_READY;
2611
2612 /* Call user Tx complete callback */
2613 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2614 hi2s->TxCpltCallback(hi2s);
2615 #else
2616 HAL_I2S_TxCpltCallback(hi2s);
2617 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2618 }
2619 }
2620 }
2621
2622 /**
2623 * @brief Manage the transmission 32-bit in Interrupt context
2624 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2625 * the configuration information for I2S module
2626 * @retval None
2627 */
I2S_Transmit_32Bit_IT(I2S_HandleTypeDef * hi2s)2628 static void I2S_Transmit_32Bit_IT(I2S_HandleTypeDef *hi2s)
2629 {
2630 /* Transmit data */
2631 hi2s->Instance->TXDR = *((const uint32_t *)hi2s->pTxBuffPtr);
2632 hi2s->pTxBuffPtr += 2;
2633 hi2s->TxXferCount--;
2634
2635 if (hi2s->TxXferCount == 0UL)
2636 {
2637 /* Disable TXP and ERR interrupt */
2638 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR));
2639
2640 if ((hi2s->Init.Mode == I2S_MODE_SLAVE_TX) || (hi2s->Init.Mode == I2S_MODE_MASTER_TX))
2641 {
2642 hi2s->State = HAL_I2S_STATE_READY;
2643
2644 /* Call user Tx complete callback */
2645 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2646 hi2s->TxCpltCallback(hi2s);
2647 #else
2648 HAL_I2S_TxCpltCallback(hi2s);
2649 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2650 }
2651 }
2652 }
2653
2654 /**
2655 * @brief Manage the reception 16-bit in Interrupt context
2656 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2657 * the configuration information for I2S module
2658 * @retval None
2659 */
I2S_Receive_16Bit_IT(I2S_HandleTypeDef * hi2s)2660 static void I2S_Receive_16Bit_IT(I2S_HandleTypeDef *hi2s)
2661 {
2662 /* Receive data */
2663 #if defined (__GNUC__)
2664 __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->RXDR));
2665
2666 *((uint16_t *)hi2s->pRxBuffPtr) = *prxdr_16bits;
2667 #else
2668 *((uint16_t *)hi2s->pRxBuffPtr) = *((__IO uint16_t *)&hi2s->Instance->RXDR);
2669 #endif /* __GNUC__ */
2670 hi2s->pRxBuffPtr++;
2671 hi2s->RxXferCount--;
2672
2673 if (hi2s->RxXferCount == 0UL)
2674 {
2675 if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
2676 {
2677 /* Disable TXP, RXP, DXP, ERR interrupts */
2678 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_DXP | I2S_IT_ERR));
2679 }
2680 else
2681 {
2682 /* Disable RXP and ERR interrupt */
2683 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR));
2684 }
2685
2686 hi2s->State = HAL_I2S_STATE_READY;
2687 /* Call user Rx complete callback */
2688 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2689 if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
2690 {
2691 hi2s->TxRxCpltCallback(hi2s);
2692 }
2693 else
2694 {
2695 hi2s->RxCpltCallback(hi2s);
2696 }
2697 #else
2698 if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
2699 {
2700 HAL_I2SEx_TxRxCpltCallback(hi2s);
2701 }
2702 else
2703 {
2704 HAL_I2S_RxCpltCallback(hi2s);
2705 }
2706 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2707 }
2708 }
2709
2710 /**
2711 * @brief Manage the reception 32-bit in Interrupt context
2712 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2713 * the configuration information for I2S module
2714 * @retval None
2715 */
I2S_Receive_32Bit_IT(I2S_HandleTypeDef * hi2s)2716 static void I2S_Receive_32Bit_IT(I2S_HandleTypeDef *hi2s)
2717 {
2718 /* Receive data */
2719 *((uint32_t *)hi2s->pRxBuffPtr) = hi2s->Instance->RXDR;
2720 hi2s->pRxBuffPtr += 2;
2721 hi2s->RxXferCount--;
2722
2723 if (hi2s->RxXferCount == 0UL)
2724 {
2725 if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
2726 {
2727 /* Disable TXP, RXP, DXP, ERR interrupts */
2728 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_DXP | I2S_IT_ERR));
2729 }
2730 else
2731 {
2732 /* Disable RXP and ERR interrupt */
2733 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR));
2734 }
2735
2736 hi2s->State = HAL_I2S_STATE_READY;
2737 /* Call user Rx complete callback */
2738 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2739 if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
2740 {
2741 hi2s->TxRxCpltCallback(hi2s);
2742 }
2743 else
2744 {
2745 hi2s->RxCpltCallback(hi2s);
2746 }
2747 #else
2748 if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
2749 {
2750 HAL_I2SEx_TxRxCpltCallback(hi2s);
2751 }
2752 else
2753 {
2754 HAL_I2S_RxCpltCallback(hi2s);
2755 }
2756 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2757 }
2758 }
2759
2760 /**
2761 * @brief This function handles I2S Communication Timeout.
2762 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2763 * the configuration information for I2S module
2764 * @param Flag Flag checked
2765 * @param State Value of the flag expected
2766 * @param Tickstart Tick start value
2767 * @param Timeout Duration of the timeout
2768 * @retval HAL status
2769 */
I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef * hi2s,uint32_t Flag,FlagStatus State,uint32_t Tickstart,uint32_t Timeout)2770 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
2771 uint32_t Tickstart, uint32_t Timeout)
2772 {
2773 /* Wait until flag is set to status*/
2774 while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
2775 {
2776 if (Timeout != HAL_MAX_DELAY)
2777 {
2778 if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0UL))
2779 {
2780 /* Set the I2S State ready */
2781 hi2s->State = HAL_I2S_STATE_READY;
2782
2783 /* Process Unlocked */
2784 __HAL_UNLOCK(hi2s);
2785
2786 return HAL_TIMEOUT;
2787 }
2788 }
2789 }
2790 return HAL_OK;
2791 }
2792
2793 /**
2794 * @}
2795 */
2796
2797 /**
2798 * @}
2799 */
2800
2801 /**
2802 * @}
2803 */
2804
2805 #endif /* HAL_I2S_MODULE_ENABLED */
2806
