1 /**
2 ******************************************************************************
3 * @file stm32h5xx_hal_i2c.c
4 * @author MCD Application Team
5 * @brief I2C HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Inter Integrated Circuit (I2C) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral State and Errors functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2023 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 ==============================================================================
25 ##### How to use this driver #####
26 ==============================================================================
27 [..]
28 The I2C HAL driver can be used as follows:
29
30 (#) Declare a I2C_HandleTypeDef handle structure, for example:
31 I2C_HandleTypeDef hi2c;
32
33 (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
34 (##) Enable the I2Cx interface clock
35 (##) I2C pins configuration
36 (+++) Enable the clock for the I2C GPIOs
37 (+++) Configure I2C pins as alternate function open-drain
38 (##) NVIC configuration if you need to use interrupt process
39 (+++) Configure the I2Cx interrupt priority
40 (+++) Enable the NVIC I2C IRQ Channel
41 (##) DMA Configuration if you need to use DMA process
42 (+++) Declare a DMA_HandleTypeDef handle structure for
43 the transmit or receive channel
44 (+++) Enable the DMAx interface clock using
45 (+++) Configure the DMA handle parameters
46 (+++) Configure the DMA Tx or Rx channel
47 (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
48 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
49 the DMA Tx or Rx channel
50
51 (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
52 Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
53
54 (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
55 (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
56
57 (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
58
59 (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
60
61 *** Polling mode IO operation ***
62 =================================
63 [..]
64 (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
65 (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
66 (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
67 (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
68
69 *** Polling mode IO MEM operation ***
70 =====================================
71 [..]
72 (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
73 (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
74
75
76 *** Interrupt mode IO operation ***
77 ===================================
78 [..]
79 (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
80 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
81 add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
82 (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
83 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
84 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
85 (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
86 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
87 add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
88 (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
89 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
90 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
91 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
92 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
93 (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
94 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
95 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
96 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
97 This action will inform Master to generate a Stop condition to discard the communication.
98
99
100 *** Interrupt mode or DMA mode IO sequential operation ***
101 ==========================================================
102 [..]
103 (@) These interfaces allow to manage a sequential transfer with a repeated start condition
104 when a direction change during transfer
105 [..]
106 (+) A specific option field manage the different steps of a sequential transfer
107 (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
108 (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in
109 no sequential mode
110 (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
111 and data to transfer without a final stop condition
112 (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with
113 start condition, address and data to transfer without a final stop condition,
114 an then permit a call the same master sequential interface several times
115 (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
116 or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
117 (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
118 and with new data to transfer if the direction change or manage only the new data to
119 transfer
120 if no direction change and without a final stop condition in both cases
121 (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
122 and with new data to transfer if the direction change or manage only the new data to
123 transfer
124 if no direction change and with a final stop condition in both cases
125 (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition
126 after several call of the same master sequential interface several times
127 (link with option I2C_FIRST_AND_NEXT_FRAME).
128 Usage can, transfer several bytes one by one using
129 HAL_I2C_Master_Seq_Transmit_IT
130 or HAL_I2C_Master_Seq_Receive_IT
131 or HAL_I2C_Master_Seq_Transmit_DMA
132 or HAL_I2C_Master_Seq_Receive_DMA
133 with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME.
134 Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or
135 Receive sequence permit to call the opposite interface Receive or Transmit
136 without stopping the communication and so generate a restart condition.
137 (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after
138 each call of the same master sequential
139 interface.
140 Usage can, transfer several bytes one by one with a restart with slave address between
141 each bytes using
142 HAL_I2C_Master_Seq_Transmit_IT
143 or HAL_I2C_Master_Seq_Receive_IT
144 or HAL_I2C_Master_Seq_Transmit_DMA
145 or HAL_I2C_Master_Seq_Receive_DMA
146 with option I2C_FIRST_FRAME then I2C_OTHER_FRAME.
147 Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic
148 generation of STOP condition.
149
150 (+) Different sequential I2C interfaces are listed below:
151 (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
152 HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA()
153 (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and
154 users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
155 (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
156 HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
157 (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
158 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
159 (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
160 (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
161 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
162 (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
163 HAL_I2C_DisableListen_IT()
164 (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can
165 add their own code to check the Address Match Code and the transmission direction request by master
166 (Write/Read).
167 (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can
168 add their own code by customization of function pointer HAL_I2C_ListenCpltCallback()
169 (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
170 HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA()
171 (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and
172 users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
173 (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
174 HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA()
175 (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
176 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
177 (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
178 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
179 (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
180 This action will inform Master to generate a Stop condition to discard the communication.
181
182 *** Interrupt mode IO MEM operation ***
183 =======================================
184 [..]
185 (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
186 HAL_I2C_Mem_Write_IT()
187 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
188 add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
189 (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
190 HAL_I2C_Mem_Read_IT()
191 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
192 add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
193 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
194 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
195
196 *** DMA mode IO operation ***
197 ==============================
198 [..]
199 (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
200 HAL_I2C_Master_Transmit_DMA()
201 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
202 add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
203 (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
204 HAL_I2C_Master_Receive_DMA()
205 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
206 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
207 (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
208 HAL_I2C_Slave_Transmit_DMA()
209 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
210 add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
211 (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
212 HAL_I2C_Slave_Receive_DMA()
213 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
214 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
215 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
216 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
217 (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
218 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
219 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
220 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
221 This action will inform Master to generate a Stop condition to discard the communication.
222
223 *** DMA mode IO MEM operation ***
224 =================================
225 [..]
226 (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
227 HAL_I2C_Mem_Write_DMA()
228 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
229 add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
230 (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
231 HAL_I2C_Mem_Read_DMA()
232 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
233 add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
234 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
235 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
236
237
238 *** I2C HAL driver macros list ***
239 ==================================
240 [..]
241 Below the list of most used macros in I2C HAL driver.
242
243 (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
244 (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
245 (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
246 (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
247 (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
248 (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
249 (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
250
251 *** Callback registration ***
252 =============================================
253 [..]
254 The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
255 allows the user to configure dynamically the driver callbacks.
256 Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
257 to register an interrupt callback.
258 [..]
259 Function HAL_I2C_RegisterCallback() allows to register following callbacks:
260 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
261 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
262 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
263 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
264 (+) ListenCpltCallback : callback for end of listen mode.
265 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
266 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
267 (+) ErrorCallback : callback for error detection.
268 (+) AbortCpltCallback : callback for abort completion process.
269 (+) MspInitCallback : callback for Msp Init.
270 (+) MspDeInitCallback : callback for Msp DeInit.
271 This function takes as parameters the HAL peripheral handle, the Callback ID
272 and a pointer to the user callback function.
273 [..]
274 For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
275 [..]
276 Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
277 weak function.
278 HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
279 and the Callback ID.
280 This function allows to reset following callbacks:
281 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
282 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
283 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
284 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
285 (+) ListenCpltCallback : callback for end of listen mode.
286 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
287 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
288 (+) ErrorCallback : callback for error detection.
289 (+) AbortCpltCallback : callback for abort completion process.
290 (+) MspInitCallback : callback for Msp Init.
291 (+) MspDeInitCallback : callback for Msp DeInit.
292 [..]
293 For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
294 [..]
295 By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
296 all callbacks are set to the corresponding weak functions:
297 examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
298 Exception done for MspInit and MspDeInit functions that are
299 reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
300 these callbacks are null (not registered beforehand).
301 If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
302 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
303 [..]
304 Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
305 Exception done MspInit/MspDeInit functions that can be registered/unregistered
306 in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
307 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
308 Then, the user first registers the MspInit/MspDeInit user callbacks
309 using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
310 or HAL_I2C_Init() function.
311 [..]
312 When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
313 not defined, the callback registration feature is not available and all callbacks
314 are set to the corresponding weak functions.
315
316 [..]
317 (@) You can refer to the I2C HAL driver header file for more useful macros
318
319 @endverbatim
320 */
321
322 /* Includes ------------------------------------------------------------------*/
323 #include "stm32h5xx_hal.h"
324
325 /** @addtogroup STM32H5xx_HAL_Driver
326 * @{
327 */
328
329 /** @defgroup I2C I2C
330 * @brief I2C HAL module driver
331 * @{
332 */
333
334 #ifdef HAL_I2C_MODULE_ENABLED
335
336 /* Private typedef -----------------------------------------------------------*/
337 /* Private define ------------------------------------------------------------*/
338
339 /** @defgroup I2C_Private_Define I2C Private Define
340 * @{
341 */
342 #define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */
343 #define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */
344 #define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */
345 #define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */
346 #define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */
347 #define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */
348 #define I2C_TIMEOUT_TC (25U) /*!< 25 ms */
349 #define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */
350 #define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */
351 #define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */
352
353 #define MAX_NBYTE_SIZE 255U
354 #define SLAVE_ADDR_SHIFT 7U
355 #define SLAVE_ADDR_MSK 0x06U
356
357 /* Private define for @ref PreviousState usage */
358 #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
359 (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
360 (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
361 /*!< Mask State define, keep only RX and TX bits */
362 #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
363 /*!< Default Value */
364 #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
365 (uint32_t)HAL_I2C_MODE_MASTER))
366 /*!< Master Busy TX, combinaison of State LSB and Mode enum */
367 #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
368 (uint32_t)HAL_I2C_MODE_MASTER))
369 /*!< Master Busy RX, combinaison of State LSB and Mode enum */
370 #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
371 (uint32_t)HAL_I2C_MODE_SLAVE))
372 /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
373 #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
374 (uint32_t)HAL_I2C_MODE_SLAVE))
375 /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
376 #define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
377 (uint32_t)HAL_I2C_MODE_MEM))
378 /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
379 #define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
380 (uint32_t)HAL_I2C_MODE_MEM))
381 /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
382
383
384 /* Private define to centralize the enable/disable of Interrupts */
385 #define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with
386 @ref I2C_XFER_LISTEN_IT */
387 #define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with
388 @ref I2C_XFER_LISTEN_IT */
389 #define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT
390 and @ref I2C_XFER_RX_IT */
391
392 #define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error
393 and NACK treatment */
394 #define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */
395 #define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */
396
397 /* Private define Sequential Transfer Options default/reset value */
398 #define I2C_NO_OPTION_FRAME (0xFFFF0000U)
399 /**
400 * @}
401 */
402
403 /* Private macros ------------------------------------------------------------*/
404 /** @addtogroup I2C_Private_Macro
405 * @{
406 */
407 #if defined(HAL_DMA_MODULE_ENABLED)
408 /* Macro to get remaining data to transfer on DMA side */
409 #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) (__HAL_DMA_GET_COUNTER(__HANDLE__) + HAL_DMAEx_GetFifoLevel(__HANDLE__))
410 #endif /* HAL_DMA_MODULE_ENABLED */
411 /**
412 * @}
413 */
414
415 /* Private variables ---------------------------------------------------------*/
416 /* Private function prototypes -----------------------------------------------*/
417
418 /** @defgroup I2C_Private_Functions I2C Private Functions
419 * @{
420 */
421 #if defined(HAL_DMA_MODULE_ENABLED)
422 /* Private functions to handle DMA transfer */
423 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
424 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
425 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
426 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
427 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
428 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
429
430 #endif /* HAL_DMA_MODULE_ENABLED */
431
432 /* Private functions to handle IT transfer */
433 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
434 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
435 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
436 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
437 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
438 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
439 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
440
441 /* Private functions to handle IT transfer */
442 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
443 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
444 uint32_t Tickstart);
445 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
446 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
447 uint32_t Tickstart);
448
449 /* Private functions for I2C transfer IRQ handler */
450 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
451 uint32_t ITSources);
452 static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
453 uint32_t ITSources);
454 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
455 uint32_t ITSources);
456 #if defined(HAL_DMA_MODULE_ENABLED)
457 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
458 uint32_t ITSources);
459 static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
460 uint32_t ITSources);
461 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
462 uint32_t ITSources);
463 #endif /* HAL_DMA_MODULE_ENABLED */
464
465 /* Private functions to handle flags during polling transfer */
466 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
467 uint32_t Timeout, uint32_t Tickstart);
468 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
469 uint32_t Tickstart);
470 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
471 uint32_t Tickstart);
472 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
473 uint32_t Tickstart);
474 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
475 uint32_t Tickstart);
476
477 /* Private functions to centralize the enable/disable of Interrupts */
478 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
479 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
480
481 /* Private function to treat different error callback */
482 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
483
484 /* Private function to flush TXDR register */
485 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
486
487 /* Private function to handle start, restart or stop a transfer */
488 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
489 uint32_t Request);
490
491 /* Private function to Convert Specific options */
492 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
493 /**
494 * @}
495 */
496
497 /* Exported functions --------------------------------------------------------*/
498
499 /** @defgroup I2C_Exported_Functions I2C Exported Functions
500 * @{
501 */
502
503 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
504 * @brief Initialization and Configuration functions
505 *
506 @verbatim
507 ===============================================================================
508 ##### Initialization and de-initialization functions #####
509 ===============================================================================
510 [..] This subsection provides a set of functions allowing to initialize and
511 deinitialize the I2Cx peripheral:
512
513 (+) User must Implement HAL_I2C_MspInit() function in which he configures
514 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
515
516 (+) Call the function HAL_I2C_Init() to configure the selected device with
517 the selected configuration:
518 (++) Clock Timing
519 (++) Own Address 1
520 (++) Addressing mode (Master, Slave)
521 (++) Dual Addressing mode
522 (++) Own Address 2
523 (++) Own Address 2 Mask
524 (++) General call mode
525 (++) Nostretch mode
526
527 (+) Call the function HAL_I2C_DeInit() to restore the default configuration
528 of the selected I2Cx peripheral.
529
530 @endverbatim
531 * @{
532 */
533
534 /**
535 * @brief Initializes the I2C according to the specified parameters
536 * in the I2C_InitTypeDef and initialize the associated handle.
537 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
538 * the configuration information for the specified I2C.
539 * @retval HAL status
540 */
HAL_I2C_Init(I2C_HandleTypeDef * hi2c)541 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
542 {
543 /* Check the I2C handle allocation */
544 if (hi2c == NULL)
545 {
546 return HAL_ERROR;
547 }
548
549 /* Check the parameters */
550 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
551 assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
552 assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
553 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
554 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
555 assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
556 assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
557 assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
558
559 if (hi2c->State == HAL_I2C_STATE_RESET)
560 {
561 /* Allocate lock resource and initialize it */
562 hi2c->Lock = HAL_UNLOCKED;
563
564 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
565 /* Init the I2C Callback settings */
566 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
567 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
568 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
569 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
570 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
571 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
572 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
573 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
574 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
575 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
576
577 if (hi2c->MspInitCallback == NULL)
578 {
579 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
580 }
581
582 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
583 hi2c->MspInitCallback(hi2c);
584 #else
585 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
586 HAL_I2C_MspInit(hi2c);
587 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
588 }
589
590 hi2c->State = HAL_I2C_STATE_BUSY;
591
592 /* Disable the selected I2C peripheral */
593 __HAL_I2C_DISABLE(hi2c);
594
595 /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
596 /* Configure I2Cx: Frequency range */
597 hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
598
599 /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
600 /* Disable Own Address1 before set the Own Address1 configuration */
601 hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
602
603 /* Configure I2Cx: Own Address1 and ack own address1 mode */
604 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
605 {
606 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
607 }
608 else /* I2C_ADDRESSINGMODE_10BIT */
609 {
610 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
611 }
612
613 /*---------------------------- I2Cx CR2 Configuration ----------------------*/
614 /* Configure I2Cx: Addressing Master mode */
615 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
616 {
617 SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
618 }
619 else
620 {
621 /* Clear the I2C ADD10 bit */
622 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
623 }
624 /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
625 hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
626
627 /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
628 /* Disable Own Address2 before set the Own Address2 configuration */
629 hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
630
631 /* Configure I2Cx: Dual mode and Own Address2 */
632 hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
633 (hi2c->Init.OwnAddress2Masks << 8));
634
635 /*---------------------------- I2Cx CR1 Configuration ----------------------*/
636 /* Configure I2Cx: Generalcall and NoStretch mode */
637 hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
638
639 /* Enable the selected I2C peripheral */
640 __HAL_I2C_ENABLE(hi2c);
641
642 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
643 hi2c->State = HAL_I2C_STATE_READY;
644 hi2c->PreviousState = I2C_STATE_NONE;
645 hi2c->Mode = HAL_I2C_MODE_NONE;
646
647 return HAL_OK;
648 }
649
650 /**
651 * @brief DeInitialize the I2C peripheral.
652 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
653 * the configuration information for the specified I2C.
654 * @retval HAL status
655 */
HAL_I2C_DeInit(I2C_HandleTypeDef * hi2c)656 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
657 {
658 /* Check the I2C handle allocation */
659 if (hi2c == NULL)
660 {
661 return HAL_ERROR;
662 }
663
664 /* Check the parameters */
665 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
666
667 hi2c->State = HAL_I2C_STATE_BUSY;
668
669 /* Disable the I2C Peripheral Clock */
670 __HAL_I2C_DISABLE(hi2c);
671
672 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
673 if (hi2c->MspDeInitCallback == NULL)
674 {
675 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
676 }
677
678 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
679 hi2c->MspDeInitCallback(hi2c);
680 #else
681 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
682 HAL_I2C_MspDeInit(hi2c);
683 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
684
685 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
686 hi2c->State = HAL_I2C_STATE_RESET;
687 hi2c->PreviousState = I2C_STATE_NONE;
688 hi2c->Mode = HAL_I2C_MODE_NONE;
689
690 /* Release Lock */
691 __HAL_UNLOCK(hi2c);
692
693 return HAL_OK;
694 }
695
696 /**
697 * @brief Initialize the I2C MSP.
698 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
699 * the configuration information for the specified I2C.
700 * @retval None
701 */
HAL_I2C_MspInit(I2C_HandleTypeDef * hi2c)702 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
703 {
704 /* Prevent unused argument(s) compilation warning */
705 UNUSED(hi2c);
706
707 /* NOTE : This function should not be modified, when the callback is needed,
708 the HAL_I2C_MspInit could be implemented in the user file
709 */
710 }
711
712 /**
713 * @brief DeInitialize the I2C MSP.
714 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
715 * the configuration information for the specified I2C.
716 * @retval None
717 */
HAL_I2C_MspDeInit(I2C_HandleTypeDef * hi2c)718 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
719 {
720 /* Prevent unused argument(s) compilation warning */
721 UNUSED(hi2c);
722
723 /* NOTE : This function should not be modified, when the callback is needed,
724 the HAL_I2C_MspDeInit could be implemented in the user file
725 */
726 }
727
728 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
729 /**
730 * @brief Register a User I2C Callback
731 * To be used instead of the weak predefined callback
732 * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
733 * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
734 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
735 * the configuration information for the specified I2C.
736 * @param CallbackID ID of the callback to be registered
737 * This parameter can be one of the following values:
738 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
739 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
740 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
741 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
742 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
743 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
744 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
745 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
746 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
747 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
748 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
749 * @param pCallback pointer to the Callback function
750 * @retval HAL status
751 */
HAL_I2C_RegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID,pI2C_CallbackTypeDef pCallback)752 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
753 pI2C_CallbackTypeDef pCallback)
754 {
755 HAL_StatusTypeDef status = HAL_OK;
756
757 if (pCallback == NULL)
758 {
759 /* Update the error code */
760 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
761
762 return HAL_ERROR;
763 }
764
765 if (HAL_I2C_STATE_READY == hi2c->State)
766 {
767 switch (CallbackID)
768 {
769 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
770 hi2c->MasterTxCpltCallback = pCallback;
771 break;
772
773 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
774 hi2c->MasterRxCpltCallback = pCallback;
775 break;
776
777 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
778 hi2c->SlaveTxCpltCallback = pCallback;
779 break;
780
781 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
782 hi2c->SlaveRxCpltCallback = pCallback;
783 break;
784
785 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
786 hi2c->ListenCpltCallback = pCallback;
787 break;
788
789 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
790 hi2c->MemTxCpltCallback = pCallback;
791 break;
792
793 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
794 hi2c->MemRxCpltCallback = pCallback;
795 break;
796
797 case HAL_I2C_ERROR_CB_ID :
798 hi2c->ErrorCallback = pCallback;
799 break;
800
801 case HAL_I2C_ABORT_CB_ID :
802 hi2c->AbortCpltCallback = pCallback;
803 break;
804
805 case HAL_I2C_MSPINIT_CB_ID :
806 hi2c->MspInitCallback = pCallback;
807 break;
808
809 case HAL_I2C_MSPDEINIT_CB_ID :
810 hi2c->MspDeInitCallback = pCallback;
811 break;
812
813 default :
814 /* Update the error code */
815 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
816
817 /* Return error status */
818 status = HAL_ERROR;
819 break;
820 }
821 }
822 else if (HAL_I2C_STATE_RESET == hi2c->State)
823 {
824 switch (CallbackID)
825 {
826 case HAL_I2C_MSPINIT_CB_ID :
827 hi2c->MspInitCallback = pCallback;
828 break;
829
830 case HAL_I2C_MSPDEINIT_CB_ID :
831 hi2c->MspDeInitCallback = pCallback;
832 break;
833
834 default :
835 /* Update the error code */
836 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
837
838 /* Return error status */
839 status = HAL_ERROR;
840 break;
841 }
842 }
843 else
844 {
845 /* Update the error code */
846 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
847
848 /* Return error status */
849 status = HAL_ERROR;
850 }
851
852 return status;
853 }
854
855 /**
856 * @brief Unregister an I2C Callback
857 * I2C callback is redirected to the weak predefined callback
858 * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
859 * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
860 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
861 * the configuration information for the specified I2C.
862 * @param CallbackID ID of the callback to be unregistered
863 * This parameter can be one of the following values:
864 * This parameter can be one of the following values:
865 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
866 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
867 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
868 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
869 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
870 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
871 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
872 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
873 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
874 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
875 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
876 * @retval HAL status
877 */
HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID)878 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
879 {
880 HAL_StatusTypeDef status = HAL_OK;
881
882 if (HAL_I2C_STATE_READY == hi2c->State)
883 {
884 switch (CallbackID)
885 {
886 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
887 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
888 break;
889
890 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
891 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
892 break;
893
894 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
895 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
896 break;
897
898 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
899 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
900 break;
901
902 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
903 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
904 break;
905
906 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
907 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
908 break;
909
910 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
911 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
912 break;
913
914 case HAL_I2C_ERROR_CB_ID :
915 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
916 break;
917
918 case HAL_I2C_ABORT_CB_ID :
919 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
920 break;
921
922 case HAL_I2C_MSPINIT_CB_ID :
923 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
924 break;
925
926 case HAL_I2C_MSPDEINIT_CB_ID :
927 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
928 break;
929
930 default :
931 /* Update the error code */
932 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
933
934 /* Return error status */
935 status = HAL_ERROR;
936 break;
937 }
938 }
939 else if (HAL_I2C_STATE_RESET == hi2c->State)
940 {
941 switch (CallbackID)
942 {
943 case HAL_I2C_MSPINIT_CB_ID :
944 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
945 break;
946
947 case HAL_I2C_MSPDEINIT_CB_ID :
948 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
949 break;
950
951 default :
952 /* Update the error code */
953 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
954
955 /* Return error status */
956 status = HAL_ERROR;
957 break;
958 }
959 }
960 else
961 {
962 /* Update the error code */
963 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
964
965 /* Return error status */
966 status = HAL_ERROR;
967 }
968
969 return status;
970 }
971
972 /**
973 * @brief Register the Slave Address Match I2C Callback
974 * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
975 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
976 * the configuration information for the specified I2C.
977 * @param pCallback pointer to the Address Match Callback function
978 * @retval HAL status
979 */
HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef * hi2c,pI2C_AddrCallbackTypeDef pCallback)980 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
981 {
982 HAL_StatusTypeDef status = HAL_OK;
983
984 if (pCallback == NULL)
985 {
986 /* Update the error code */
987 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
988
989 return HAL_ERROR;
990 }
991
992 if (HAL_I2C_STATE_READY == hi2c->State)
993 {
994 hi2c->AddrCallback = pCallback;
995 }
996 else
997 {
998 /* Update the error code */
999 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
1000
1001 /* Return error status */
1002 status = HAL_ERROR;
1003 }
1004
1005 return status;
1006 }
1007
1008 /**
1009 * @brief UnRegister the Slave Address Match I2C Callback
1010 * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
1011 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1012 * the configuration information for the specified I2C.
1013 * @retval HAL status
1014 */
HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef * hi2c)1015 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
1016 {
1017 HAL_StatusTypeDef status = HAL_OK;
1018
1019 if (HAL_I2C_STATE_READY == hi2c->State)
1020 {
1021 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
1022 }
1023 else
1024 {
1025 /* Update the error code */
1026 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
1027
1028 /* Return error status */
1029 status = HAL_ERROR;
1030 }
1031
1032 return status;
1033 }
1034
1035 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
1036
1037 /**
1038 * @}
1039 */
1040
1041 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
1042 * @brief Data transfers functions
1043 *
1044 @verbatim
1045 ===============================================================================
1046 ##### IO operation functions #####
1047 ===============================================================================
1048 [..]
1049 This subsection provides a set of functions allowing to manage the I2C data
1050 transfers.
1051
1052 (#) There are two modes of transfer:
1053 (++) Blocking mode : The communication is performed in the polling mode.
1054 The status of all data processing is returned by the same function
1055 after finishing transfer.
1056 (++) No-Blocking mode : The communication is performed using Interrupts
1057 or DMA. These functions return the status of the transfer startup.
1058 The end of the data processing will be indicated through the
1059 dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
1060 using DMA mode.
1061
1062 (#) Blocking mode functions are :
1063 (++) HAL_I2C_Master_Transmit()
1064 (++) HAL_I2C_Master_Receive()
1065 (++) HAL_I2C_Slave_Transmit()
1066 (++) HAL_I2C_Slave_Receive()
1067 (++) HAL_I2C_Mem_Write()
1068 (++) HAL_I2C_Mem_Read()
1069 (++) HAL_I2C_IsDeviceReady()
1070
1071 (#) No-Blocking mode functions with Interrupt are :
1072 (++) HAL_I2C_Master_Transmit_IT()
1073 (++) HAL_I2C_Master_Receive_IT()
1074 (++) HAL_I2C_Slave_Transmit_IT()
1075 (++) HAL_I2C_Slave_Receive_IT()
1076 (++) HAL_I2C_Mem_Write_IT()
1077 (++) HAL_I2C_Mem_Read_IT()
1078 (++) HAL_I2C_Master_Seq_Transmit_IT()
1079 (++) HAL_I2C_Master_Seq_Receive_IT()
1080 (++) HAL_I2C_Slave_Seq_Transmit_IT()
1081 (++) HAL_I2C_Slave_Seq_Receive_IT()
1082 (++) HAL_I2C_EnableListen_IT()
1083 (++) HAL_I2C_DisableListen_IT()
1084 (++) HAL_I2C_Master_Abort_IT()
1085
1086 (#) No-Blocking mode functions with DMA are :
1087 (++) HAL_I2C_Master_Transmit_DMA()
1088 (++) HAL_I2C_Master_Receive_DMA()
1089 (++) HAL_I2C_Slave_Transmit_DMA()
1090 (++) HAL_I2C_Slave_Receive_DMA()
1091 (++) HAL_I2C_Mem_Write_DMA()
1092 (++) HAL_I2C_Mem_Read_DMA()
1093 (++) HAL_I2C_Master_Seq_Transmit_DMA()
1094 (++) HAL_I2C_Master_Seq_Receive_DMA()
1095 (++) HAL_I2C_Slave_Seq_Transmit_DMA()
1096 (++) HAL_I2C_Slave_Seq_Receive_DMA()
1097
1098 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
1099 (++) HAL_I2C_MasterTxCpltCallback()
1100 (++) HAL_I2C_MasterRxCpltCallback()
1101 (++) HAL_I2C_SlaveTxCpltCallback()
1102 (++) HAL_I2C_SlaveRxCpltCallback()
1103 (++) HAL_I2C_MemTxCpltCallback()
1104 (++) HAL_I2C_MemRxCpltCallback()
1105 (++) HAL_I2C_AddrCallback()
1106 (++) HAL_I2C_ListenCpltCallback()
1107 (++) HAL_I2C_ErrorCallback()
1108 (++) HAL_I2C_AbortCpltCallback()
1109
1110 @endverbatim
1111 * @{
1112 */
1113
1114 /**
1115 * @brief Transmits in master mode an amount of data in blocking mode.
1116 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1117 * the configuration information for the specified I2C.
1118 * @param DevAddress Target device address: The device 7 bits address value
1119 * in datasheet must be shifted to the left before calling the interface
1120 * @param pData Pointer to data buffer
1121 * @param Size Amount of data to be sent
1122 * @param Timeout Timeout duration
1123 * @retval HAL status
1124 */
HAL_I2C_Master_Transmit(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1125 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1126 uint16_t Size, uint32_t Timeout)
1127 {
1128 uint32_t tickstart;
1129
1130 if (hi2c->State == HAL_I2C_STATE_READY)
1131 {
1132 /* Process Locked */
1133 __HAL_LOCK(hi2c);
1134
1135 /* Init tickstart for timeout management*/
1136 tickstart = HAL_GetTick();
1137
1138 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1139 {
1140 return HAL_ERROR;
1141 }
1142
1143 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1144 hi2c->Mode = HAL_I2C_MODE_MASTER;
1145 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1146
1147 /* Prepare transfer parameters */
1148 hi2c->pBuffPtr = pData;
1149 hi2c->XferCount = Size;
1150 hi2c->XferISR = NULL;
1151
1152 /* Send Slave Address */
1153 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1154 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1155 {
1156 hi2c->XferSize = MAX_NBYTE_SIZE;
1157 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1158 I2C_GENERATE_START_WRITE);
1159 }
1160 else
1161 {
1162 hi2c->XferSize = hi2c->XferCount;
1163 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1164 I2C_GENERATE_START_WRITE);
1165 }
1166
1167 while (hi2c->XferCount > 0U)
1168 {
1169 /* Wait until TXIS flag is set */
1170 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1171 {
1172 return HAL_ERROR;
1173 }
1174 /* Write data to TXDR */
1175 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1176
1177 /* Increment Buffer pointer */
1178 hi2c->pBuffPtr++;
1179
1180 hi2c->XferCount--;
1181 hi2c->XferSize--;
1182
1183 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
1184 {
1185 /* Wait until TCR flag is set */
1186 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1187 {
1188 return HAL_ERROR;
1189 }
1190
1191 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1192 {
1193 hi2c->XferSize = MAX_NBYTE_SIZE;
1194 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1195 I2C_NO_STARTSTOP);
1196 }
1197 else
1198 {
1199 hi2c->XferSize = hi2c->XferCount;
1200 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1201 I2C_NO_STARTSTOP);
1202 }
1203 }
1204 }
1205
1206 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1207 /* Wait until STOPF flag is set */
1208 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1209 {
1210 return HAL_ERROR;
1211 }
1212
1213 /* Clear STOP Flag */
1214 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1215
1216 /* Clear Configuration Register 2 */
1217 I2C_RESET_CR2(hi2c);
1218
1219 hi2c->State = HAL_I2C_STATE_READY;
1220 hi2c->Mode = HAL_I2C_MODE_NONE;
1221
1222 /* Process Unlocked */
1223 __HAL_UNLOCK(hi2c);
1224
1225 return HAL_OK;
1226 }
1227 else
1228 {
1229 return HAL_BUSY;
1230 }
1231 }
1232
1233 /**
1234 * @brief Receives in master mode an amount of data in blocking mode.
1235 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1236 * the configuration information for the specified I2C.
1237 * @param DevAddress Target device address: The device 7 bits address value
1238 * in datasheet must be shifted to the left before calling the interface
1239 * @param pData Pointer to data buffer
1240 * @param Size Amount of data to be sent
1241 * @param Timeout Timeout duration
1242 * @retval HAL status
1243 */
HAL_I2C_Master_Receive(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1244 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1245 uint16_t Size, uint32_t Timeout)
1246 {
1247 uint32_t tickstart;
1248
1249 if (hi2c->State == HAL_I2C_STATE_READY)
1250 {
1251 /* Process Locked */
1252 __HAL_LOCK(hi2c);
1253
1254 /* Init tickstart for timeout management*/
1255 tickstart = HAL_GetTick();
1256
1257 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1258 {
1259 return HAL_ERROR;
1260 }
1261
1262 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1263 hi2c->Mode = HAL_I2C_MODE_MASTER;
1264 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1265
1266 /* Prepare transfer parameters */
1267 hi2c->pBuffPtr = pData;
1268 hi2c->XferCount = Size;
1269 hi2c->XferISR = NULL;
1270
1271 /* Send Slave Address */
1272 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1273 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1274 {
1275 hi2c->XferSize = MAX_NBYTE_SIZE;
1276 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1277 I2C_GENERATE_START_READ);
1278 }
1279 else
1280 {
1281 hi2c->XferSize = hi2c->XferCount;
1282 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1283 I2C_GENERATE_START_READ);
1284 }
1285
1286 while (hi2c->XferCount > 0U)
1287 {
1288 /* Wait until RXNE flag is set */
1289 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1290 {
1291 return HAL_ERROR;
1292 }
1293
1294 /* Read data from RXDR */
1295 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1296
1297 /* Increment Buffer pointer */
1298 hi2c->pBuffPtr++;
1299
1300 hi2c->XferSize--;
1301 hi2c->XferCount--;
1302
1303 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
1304 {
1305 /* Wait until TCR flag is set */
1306 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1307 {
1308 return HAL_ERROR;
1309 }
1310
1311 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1312 {
1313 hi2c->XferSize = MAX_NBYTE_SIZE;
1314 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1315 I2C_NO_STARTSTOP);
1316 }
1317 else
1318 {
1319 hi2c->XferSize = hi2c->XferCount;
1320 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1321 I2C_NO_STARTSTOP);
1322 }
1323 }
1324 }
1325
1326 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1327 /* Wait until STOPF flag is set */
1328 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1329 {
1330 return HAL_ERROR;
1331 }
1332
1333 /* Clear STOP Flag */
1334 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1335
1336 /* Clear Configuration Register 2 */
1337 I2C_RESET_CR2(hi2c);
1338
1339 hi2c->State = HAL_I2C_STATE_READY;
1340 hi2c->Mode = HAL_I2C_MODE_NONE;
1341
1342 /* Process Unlocked */
1343 __HAL_UNLOCK(hi2c);
1344
1345 return HAL_OK;
1346 }
1347 else
1348 {
1349 return HAL_BUSY;
1350 }
1351 }
1352
1353 /**
1354 * @brief Transmits in slave mode an amount of data in blocking mode.
1355 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1356 * the configuration information for the specified I2C.
1357 * @param pData Pointer to data buffer
1358 * @param Size Amount of data to be sent
1359 * @param Timeout Timeout duration
1360 * @retval HAL status
1361 */
HAL_I2C_Slave_Transmit(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1362 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
1363 uint32_t Timeout)
1364 {
1365 uint32_t tickstart;
1366 uint16_t tmpXferCount;
1367 HAL_StatusTypeDef error;
1368
1369 if (hi2c->State == HAL_I2C_STATE_READY)
1370 {
1371 if ((pData == NULL) || (Size == 0U))
1372 {
1373 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
1374 return HAL_ERROR;
1375 }
1376 /* Process Locked */
1377 __HAL_LOCK(hi2c);
1378
1379 /* Init tickstart for timeout management*/
1380 tickstart = HAL_GetTick();
1381
1382 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1383 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1384 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1385
1386 /* Prepare transfer parameters */
1387 hi2c->pBuffPtr = pData;
1388 hi2c->XferCount = Size;
1389 hi2c->XferISR = NULL;
1390
1391 /* Enable Address Acknowledge */
1392 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1393
1394 /* Preload TX data if no stretch enable */
1395 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
1396 {
1397 /* Preload TX register */
1398 /* Write data to TXDR */
1399 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1400
1401 /* Increment Buffer pointer */
1402 hi2c->pBuffPtr++;
1403
1404 hi2c->XferCount--;
1405 }
1406
1407 /* Wait until ADDR flag is set */
1408 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1409 {
1410 /* Disable Address Acknowledge */
1411 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1412
1413 /* Flush TX register */
1414 I2C_Flush_TXDR(hi2c);
1415
1416 return HAL_ERROR;
1417 }
1418
1419 /* Clear ADDR flag */
1420 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1421
1422 /* If 10bit addressing mode is selected */
1423 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
1424 {
1425 /* Wait until ADDR flag is set */
1426 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1427 {
1428 /* Disable Address Acknowledge */
1429 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1430
1431 /* Flush TX register */
1432 I2C_Flush_TXDR(hi2c);
1433
1434 return HAL_ERROR;
1435 }
1436
1437 /* Clear ADDR flag */
1438 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1439 }
1440
1441 /* Wait until DIR flag is set Transmitter mode */
1442 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
1443 {
1444 /* Disable Address Acknowledge */
1445 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1446
1447 /* Flush TX register */
1448 I2C_Flush_TXDR(hi2c);
1449
1450 return HAL_ERROR;
1451 }
1452
1453 while (hi2c->XferCount > 0U)
1454 {
1455 /* Wait until TXIS flag is set */
1456 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1457 {
1458 /* Disable Address Acknowledge */
1459 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1460 return HAL_ERROR;
1461 }
1462
1463 /* Write data to TXDR */
1464 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1465
1466 /* Increment Buffer pointer */
1467 hi2c->pBuffPtr++;
1468
1469 hi2c->XferCount--;
1470 }
1471
1472 /* Wait until AF flag is set */
1473 error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart);
1474
1475 if (error != HAL_OK)
1476 {
1477 /* Check that I2C transfer finished */
1478 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
1479 /* Mean XferCount == 0 */
1480
1481 tmpXferCount = hi2c->XferCount;
1482 if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U))
1483 {
1484 /* Reset ErrorCode to NONE */
1485 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1486 }
1487 else
1488 {
1489 /* Disable Address Acknowledge */
1490 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1491 return HAL_ERROR;
1492 }
1493 }
1494 else
1495 {
1496 /* Flush TX register */
1497 I2C_Flush_TXDR(hi2c);
1498
1499 /* Clear AF flag */
1500 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
1501
1502 /* Wait until STOP flag is set */
1503 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1504 {
1505 /* Disable Address Acknowledge */
1506 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1507
1508 return HAL_ERROR;
1509 }
1510
1511 /* Clear STOP flag */
1512 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1513 }
1514
1515 /* Wait until BUSY flag is reset */
1516 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1517 {
1518 /* Disable Address Acknowledge */
1519 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1520 return HAL_ERROR;
1521 }
1522
1523 /* Disable Address Acknowledge */
1524 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1525
1526 hi2c->State = HAL_I2C_STATE_READY;
1527 hi2c->Mode = HAL_I2C_MODE_NONE;
1528
1529 /* Process Unlocked */
1530 __HAL_UNLOCK(hi2c);
1531
1532 return HAL_OK;
1533 }
1534 else
1535 {
1536 return HAL_BUSY;
1537 }
1538 }
1539
1540 /**
1541 * @brief Receive in slave mode an amount of data in blocking mode
1542 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1543 * the configuration information for the specified I2C.
1544 * @param pData Pointer to data buffer
1545 * @param Size Amount of data to be sent
1546 * @param Timeout Timeout duration
1547 * @retval HAL status
1548 */
HAL_I2C_Slave_Receive(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1549 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
1550 uint32_t Timeout)
1551 {
1552 uint32_t tickstart;
1553
1554 if (hi2c->State == HAL_I2C_STATE_READY)
1555 {
1556 if ((pData == NULL) || (Size == 0U))
1557 {
1558 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
1559 return HAL_ERROR;
1560 }
1561 /* Process Locked */
1562 __HAL_LOCK(hi2c);
1563
1564 /* Init tickstart for timeout management*/
1565 tickstart = HAL_GetTick();
1566
1567 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1568 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1569 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1570
1571 /* Prepare transfer parameters */
1572 hi2c->pBuffPtr = pData;
1573 hi2c->XferCount = Size;
1574 hi2c->XferSize = hi2c->XferCount;
1575 hi2c->XferISR = NULL;
1576
1577 /* Enable Address Acknowledge */
1578 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1579
1580 /* Wait until ADDR flag is set */
1581 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1582 {
1583 /* Disable Address Acknowledge */
1584 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1585 return HAL_ERROR;
1586 }
1587
1588 /* Clear ADDR flag */
1589 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1590
1591 /* Wait until DIR flag is reset Receiver mode */
1592 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
1593 {
1594 /* Disable Address Acknowledge */
1595 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1596 return HAL_ERROR;
1597 }
1598
1599 while (hi2c->XferCount > 0U)
1600 {
1601 /* Wait until RXNE flag is set */
1602 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1603 {
1604 /* Disable Address Acknowledge */
1605 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1606
1607 /* Store Last receive data if any */
1608 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
1609 {
1610 /* Read data from RXDR */
1611 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1612
1613 /* Increment Buffer pointer */
1614 hi2c->pBuffPtr++;
1615
1616 hi2c->XferCount--;
1617 hi2c->XferSize--;
1618 }
1619
1620 return HAL_ERROR;
1621 }
1622
1623 /* Read data from RXDR */
1624 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1625
1626 /* Increment Buffer pointer */
1627 hi2c->pBuffPtr++;
1628
1629 hi2c->XferCount--;
1630 hi2c->XferSize--;
1631 }
1632
1633 /* Wait until STOP flag is set */
1634 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1635 {
1636 /* Disable Address Acknowledge */
1637 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1638 return HAL_ERROR;
1639 }
1640
1641 /* Clear STOP flag */
1642 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1643
1644 /* Wait until BUSY flag is reset */
1645 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1646 {
1647 /* Disable Address Acknowledge */
1648 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1649 return HAL_ERROR;
1650 }
1651
1652 /* Disable Address Acknowledge */
1653 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1654
1655 hi2c->State = HAL_I2C_STATE_READY;
1656 hi2c->Mode = HAL_I2C_MODE_NONE;
1657
1658 /* Process Unlocked */
1659 __HAL_UNLOCK(hi2c);
1660
1661 return HAL_OK;
1662 }
1663 else
1664 {
1665 return HAL_BUSY;
1666 }
1667 }
1668
1669 /**
1670 * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
1671 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1672 * the configuration information for the specified I2C.
1673 * @param DevAddress Target device address: The device 7 bits address value
1674 * in datasheet must be shifted to the left before calling the interface
1675 * @param pData Pointer to data buffer
1676 * @param Size Amount of data to be sent
1677 * @retval HAL status
1678 */
HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1679 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1680 uint16_t Size)
1681 {
1682 uint32_t xfermode;
1683
1684 if (hi2c->State == HAL_I2C_STATE_READY)
1685 {
1686 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1687 {
1688 return HAL_BUSY;
1689 }
1690
1691 /* Process Locked */
1692 __HAL_LOCK(hi2c);
1693
1694 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1695 hi2c->Mode = HAL_I2C_MODE_MASTER;
1696 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1697
1698 /* Prepare transfer parameters */
1699 hi2c->pBuffPtr = pData;
1700 hi2c->XferCount = Size;
1701 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1702 hi2c->XferISR = I2C_Master_ISR_IT;
1703
1704 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1705 {
1706 hi2c->XferSize = MAX_NBYTE_SIZE;
1707 xfermode = I2C_RELOAD_MODE;
1708 }
1709 else
1710 {
1711 hi2c->XferSize = hi2c->XferCount;
1712 xfermode = I2C_AUTOEND_MODE;
1713 }
1714
1715 /* Send Slave Address */
1716 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1717 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
1718
1719 /* Process Unlocked */
1720 __HAL_UNLOCK(hi2c);
1721
1722 /* Note : The I2C interrupts must be enabled after unlocking current process
1723 to avoid the risk of I2C interrupt handle execution before current
1724 process unlock */
1725
1726 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1727 /* possible to enable all of these */
1728 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1729 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1730 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
1731
1732 return HAL_OK;
1733 }
1734 else
1735 {
1736 return HAL_BUSY;
1737 }
1738 }
1739
1740 /**
1741 * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
1742 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1743 * the configuration information for the specified I2C.
1744 * @param DevAddress Target device address: The device 7 bits address value
1745 * in datasheet must be shifted to the left before calling the interface
1746 * @param pData Pointer to data buffer
1747 * @param Size Amount of data to be sent
1748 * @retval HAL status
1749 */
HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1750 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1751 uint16_t Size)
1752 {
1753 uint32_t xfermode;
1754
1755 if (hi2c->State == HAL_I2C_STATE_READY)
1756 {
1757 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1758 {
1759 return HAL_BUSY;
1760 }
1761
1762 /* Process Locked */
1763 __HAL_LOCK(hi2c);
1764
1765 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1766 hi2c->Mode = HAL_I2C_MODE_MASTER;
1767 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1768
1769 /* Prepare transfer parameters */
1770 hi2c->pBuffPtr = pData;
1771 hi2c->XferCount = Size;
1772 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1773 hi2c->XferISR = I2C_Master_ISR_IT;
1774
1775 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1776 {
1777 hi2c->XferSize = MAX_NBYTE_SIZE;
1778 xfermode = I2C_RELOAD_MODE;
1779 }
1780 else
1781 {
1782 hi2c->XferSize = hi2c->XferCount;
1783 xfermode = I2C_AUTOEND_MODE;
1784 }
1785
1786 /* Send Slave Address */
1787 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1788 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
1789
1790 /* Process Unlocked */
1791 __HAL_UNLOCK(hi2c);
1792
1793 /* Note : The I2C interrupts must be enabled after unlocking current process
1794 to avoid the risk of I2C interrupt handle execution before current
1795 process unlock */
1796
1797 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1798 /* possible to enable all of these */
1799 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1800 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1801 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
1802
1803 return HAL_OK;
1804 }
1805 else
1806 {
1807 return HAL_BUSY;
1808 }
1809 }
1810
1811 /**
1812 * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
1813 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1814 * the configuration information for the specified I2C.
1815 * @param pData Pointer to data buffer
1816 * @param Size Amount of data to be sent
1817 * @retval HAL status
1818 */
HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1819 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1820 {
1821 if (hi2c->State == HAL_I2C_STATE_READY)
1822 {
1823 /* Process Locked */
1824 __HAL_LOCK(hi2c);
1825
1826 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1827 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1828 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1829
1830 /* Enable Address Acknowledge */
1831 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1832
1833 /* Prepare transfer parameters */
1834 hi2c->pBuffPtr = pData;
1835 hi2c->XferCount = Size;
1836 hi2c->XferSize = hi2c->XferCount;
1837 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1838 hi2c->XferISR = I2C_Slave_ISR_IT;
1839
1840 /* Preload TX data if no stretch enable */
1841 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
1842 {
1843 /* Preload TX register */
1844 /* Write data to TXDR */
1845 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1846
1847 /* Increment Buffer pointer */
1848 hi2c->pBuffPtr++;
1849
1850 hi2c->XferCount--;
1851 hi2c->XferSize--;
1852 }
1853
1854 /* Process Unlocked */
1855 __HAL_UNLOCK(hi2c);
1856
1857 /* Note : The I2C interrupts must be enabled after unlocking current process
1858 to avoid the risk of I2C interrupt handle execution before current
1859 process unlock */
1860
1861 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1862 /* possible to enable all of these */
1863 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1864 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1865 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
1866
1867 return HAL_OK;
1868 }
1869 else
1870 {
1871 return HAL_BUSY;
1872 }
1873 }
1874
1875 /**
1876 * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
1877 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1878 * the configuration information for the specified I2C.
1879 * @param pData Pointer to data buffer
1880 * @param Size Amount of data to be sent
1881 * @retval HAL status
1882 */
HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1883 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1884 {
1885 if (hi2c->State == HAL_I2C_STATE_READY)
1886 {
1887 /* Process Locked */
1888 __HAL_LOCK(hi2c);
1889
1890 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1891 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1892 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1893
1894 /* Enable Address Acknowledge */
1895 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1896
1897 /* Prepare transfer parameters */
1898 hi2c->pBuffPtr = pData;
1899 hi2c->XferCount = Size;
1900 hi2c->XferSize = hi2c->XferCount;
1901 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1902 hi2c->XferISR = I2C_Slave_ISR_IT;
1903
1904 /* Process Unlocked */
1905 __HAL_UNLOCK(hi2c);
1906
1907 /* Note : The I2C interrupts must be enabled after unlocking current process
1908 to avoid the risk of I2C interrupt handle execution before current
1909 process unlock */
1910
1911 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1912 /* possible to enable all of these */
1913 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1914 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1915 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
1916
1917 return HAL_OK;
1918 }
1919 else
1920 {
1921 return HAL_BUSY;
1922 }
1923 }
1924
1925 #if defined(HAL_DMA_MODULE_ENABLED)
1926 /**
1927 * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
1928 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1929 * the configuration information for the specified I2C.
1930 * @param DevAddress Target device address: The device 7 bits address value
1931 * in datasheet must be shifted to the left before calling the interface
1932 * @param pData Pointer to data buffer
1933 * @param Size Amount of data to be sent
1934 * @retval HAL status
1935 */
HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1936 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1937 uint16_t Size)
1938 {
1939 uint32_t xfermode;
1940 HAL_StatusTypeDef dmaxferstatus;
1941
1942 if (hi2c->State == HAL_I2C_STATE_READY)
1943 {
1944 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1945 {
1946 return HAL_BUSY;
1947 }
1948
1949 /* Process Locked */
1950 __HAL_LOCK(hi2c);
1951
1952 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1953 hi2c->Mode = HAL_I2C_MODE_MASTER;
1954 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1955
1956 /* Prepare transfer parameters */
1957 hi2c->pBuffPtr = pData;
1958 hi2c->XferCount = Size;
1959 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1960 hi2c->XferISR = I2C_Master_ISR_DMA;
1961
1962 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1963 {
1964 hi2c->XferSize = MAX_NBYTE_SIZE;
1965 xfermode = I2C_RELOAD_MODE;
1966 }
1967 else
1968 {
1969 hi2c->XferSize = hi2c->XferCount;
1970 xfermode = I2C_AUTOEND_MODE;
1971 }
1972
1973 if (hi2c->XferSize > 0U)
1974 {
1975 if (hi2c->hdmatx != NULL)
1976 {
1977 /* Set the I2C DMA transfer complete callback */
1978 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
1979
1980 /* Set the DMA error callback */
1981 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
1982
1983 /* Set the unused DMA callbacks to NULL */
1984 hi2c->hdmatx->XferHalfCpltCallback = NULL;
1985 hi2c->hdmatx->XferAbortCallback = NULL;
1986
1987 /* Enable the DMA channel */
1988 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
1989 {
1990 if (hi2c->hdmatx->LinkedListQueue != NULL)
1991 {
1992 /* Set DMA data size */
1993 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
1994
1995 /* Set DMA source address */
1996 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
1997
1998 /* Set DMA destination address */
1999 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
2000 = (uint32_t)&hi2c->Instance->TXDR;
2001
2002 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
2003 }
2004 else
2005 {
2006 /* Update I2C state */
2007 hi2c->State = HAL_I2C_STATE_READY;
2008 hi2c->Mode = HAL_I2C_MODE_NONE;
2009
2010 /* Update I2C error code */
2011 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2012
2013 /* Process Unlocked */
2014 __HAL_UNLOCK(hi2c);
2015
2016 return HAL_ERROR;
2017 }
2018 }
2019 else
2020 {
2021 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
2022 hi2c->XferSize);
2023 }
2024 }
2025 else
2026 {
2027 /* Update I2C state */
2028 hi2c->State = HAL_I2C_STATE_READY;
2029 hi2c->Mode = HAL_I2C_MODE_NONE;
2030
2031 /* Update I2C error code */
2032 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2033
2034 /* Process Unlocked */
2035 __HAL_UNLOCK(hi2c);
2036
2037 return HAL_ERROR;
2038 }
2039
2040 if (dmaxferstatus == HAL_OK)
2041 {
2042 /* Send Slave Address */
2043 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2044 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
2045
2046 /* Update XferCount value */
2047 hi2c->XferCount -= hi2c->XferSize;
2048
2049 /* Process Unlocked */
2050 __HAL_UNLOCK(hi2c);
2051
2052 /* Note : The I2C interrupts must be enabled after unlocking current process
2053 to avoid the risk of I2C interrupt handle execution before current
2054 process unlock */
2055 /* Enable ERR and NACK interrupts */
2056 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
2057
2058 /* Enable DMA Request */
2059 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
2060 }
2061 else
2062 {
2063 /* Update I2C state */
2064 hi2c->State = HAL_I2C_STATE_READY;
2065 hi2c->Mode = HAL_I2C_MODE_NONE;
2066
2067 /* Update I2C error code */
2068 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2069
2070 /* Process Unlocked */
2071 __HAL_UNLOCK(hi2c);
2072
2073 return HAL_ERROR;
2074 }
2075 }
2076 else
2077 {
2078 /* Update Transfer ISR function pointer */
2079 hi2c->XferISR = I2C_Master_ISR_IT;
2080
2081 /* Send Slave Address */
2082 /* Set NBYTES to write and generate START condition */
2083 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2084 I2C_GENERATE_START_WRITE);
2085
2086 /* Process Unlocked */
2087 __HAL_UNLOCK(hi2c);
2088
2089 /* Note : The I2C interrupts must be enabled after unlocking current process
2090 to avoid the risk of I2C interrupt handle execution before current
2091 process unlock */
2092 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2093 /* possible to enable all of these */
2094 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2095 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2096 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2097 }
2098
2099 return HAL_OK;
2100 }
2101 else
2102 {
2103 return HAL_BUSY;
2104 }
2105 }
2106
2107 /**
2108 * @brief Receive in master mode an amount of data in non-blocking mode with DMA
2109 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2110 * the configuration information for the specified I2C.
2111 * @param DevAddress Target device address: The device 7 bits address value
2112 * in datasheet must be shifted to the left before calling the interface
2113 * @param pData Pointer to data buffer
2114 * @param Size Amount of data to be sent
2115 * @retval HAL status
2116 */
HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)2117 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
2118 uint16_t Size)
2119 {
2120 uint32_t xfermode;
2121 HAL_StatusTypeDef dmaxferstatus;
2122
2123 if (hi2c->State == HAL_I2C_STATE_READY)
2124 {
2125 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2126 {
2127 return HAL_BUSY;
2128 }
2129
2130 /* Process Locked */
2131 __HAL_LOCK(hi2c);
2132
2133 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2134 hi2c->Mode = HAL_I2C_MODE_MASTER;
2135 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2136
2137 /* Prepare transfer parameters */
2138 hi2c->pBuffPtr = pData;
2139 hi2c->XferCount = Size;
2140 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2141 hi2c->XferISR = I2C_Master_ISR_DMA;
2142
2143 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2144 {
2145 hi2c->XferSize = MAX_NBYTE_SIZE;
2146 xfermode = I2C_RELOAD_MODE;
2147 }
2148 else
2149 {
2150 hi2c->XferSize = hi2c->XferCount;
2151 xfermode = I2C_AUTOEND_MODE;
2152 }
2153
2154 if (hi2c->XferSize > 0U)
2155 {
2156 if (hi2c->hdmarx != NULL)
2157 {
2158 /* Set the I2C DMA transfer complete callback */
2159 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
2160
2161 /* Set the DMA error callback */
2162 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2163
2164 /* Set the unused DMA callbacks to NULL */
2165 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2166 hi2c->hdmarx->XferAbortCallback = NULL;
2167
2168 /* Enable the DMA channel */
2169 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
2170 {
2171 if (hi2c->hdmarx->LinkedListQueue != NULL)
2172 {
2173 /* Set DMA data size */
2174 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
2175
2176 /* Set DMA source address */
2177 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
2178 = (uint32_t)&hi2c->Instance->RXDR;
2179
2180 /* Set DMA destination address */
2181 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
2182
2183 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
2184 }
2185 else
2186 {
2187 /* Update I2C state */
2188 hi2c->State = HAL_I2C_STATE_READY;
2189 hi2c->Mode = HAL_I2C_MODE_NONE;
2190
2191 /* Update I2C error code */
2192 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2193
2194 /* Process Unlocked */
2195 __HAL_UNLOCK(hi2c);
2196
2197 return HAL_ERROR;
2198 }
2199 }
2200 else
2201 {
2202 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
2203 hi2c->XferSize);
2204 }
2205 }
2206 else
2207 {
2208 /* Update I2C state */
2209 hi2c->State = HAL_I2C_STATE_READY;
2210 hi2c->Mode = HAL_I2C_MODE_NONE;
2211
2212 /* Update I2C error code */
2213 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2214
2215 /* Process Unlocked */
2216 __HAL_UNLOCK(hi2c);
2217
2218 return HAL_ERROR;
2219 }
2220
2221 if (dmaxferstatus == HAL_OK)
2222 {
2223 /* Send Slave Address */
2224 /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2225 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
2226
2227 /* Update XferCount value */
2228 hi2c->XferCount -= hi2c->XferSize;
2229
2230 /* Process Unlocked */
2231 __HAL_UNLOCK(hi2c);
2232
2233 /* Note : The I2C interrupts must be enabled after unlocking current process
2234 to avoid the risk of I2C interrupt handle execution before current
2235 process unlock */
2236 /* Enable ERR and NACK interrupts */
2237 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
2238
2239 /* Enable DMA Request */
2240 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2241 }
2242 else
2243 {
2244 /* Update I2C state */
2245 hi2c->State = HAL_I2C_STATE_READY;
2246 hi2c->Mode = HAL_I2C_MODE_NONE;
2247
2248 /* Update I2C error code */
2249 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2250
2251 /* Process Unlocked */
2252 __HAL_UNLOCK(hi2c);
2253
2254 return HAL_ERROR;
2255 }
2256 }
2257 else
2258 {
2259 /* Update Transfer ISR function pointer */
2260 hi2c->XferISR = I2C_Master_ISR_IT;
2261
2262 /* Send Slave Address */
2263 /* Set NBYTES to read and generate START condition */
2264 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2265 I2C_GENERATE_START_READ);
2266
2267 /* Process Unlocked */
2268 __HAL_UNLOCK(hi2c);
2269
2270 /* Note : The I2C interrupts must be enabled after unlocking current process
2271 to avoid the risk of I2C interrupt handle execution before current
2272 process unlock */
2273 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
2274 /* possible to enable all of these */
2275 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2276 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2277 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
2278 }
2279
2280 return HAL_OK;
2281 }
2282 else
2283 {
2284 return HAL_BUSY;
2285 }
2286 }
2287
2288 /**
2289 * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
2290 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2291 * the configuration information for the specified I2C.
2292 * @param pData Pointer to data buffer
2293 * @param Size Amount of data to be sent
2294 * @retval HAL status
2295 */
HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2296 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2297 {
2298 HAL_StatusTypeDef dmaxferstatus;
2299
2300 if (hi2c->State == HAL_I2C_STATE_READY)
2301 {
2302 if ((pData == NULL) || (Size == 0U))
2303 {
2304 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2305 return HAL_ERROR;
2306 }
2307 /* Process Locked */
2308 __HAL_LOCK(hi2c);
2309
2310 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2311 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2312 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2313
2314 /* Prepare transfer parameters */
2315 hi2c->pBuffPtr = pData;
2316 hi2c->XferCount = Size;
2317 hi2c->XferSize = hi2c->XferCount;
2318 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2319 hi2c->XferISR = I2C_Slave_ISR_DMA;
2320
2321 /* Preload TX data if no stretch enable */
2322 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
2323 {
2324 /* Preload TX register */
2325 /* Write data to TXDR */
2326 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
2327
2328 /* Increment Buffer pointer */
2329 hi2c->pBuffPtr++;
2330
2331 hi2c->XferCount--;
2332 hi2c->XferSize--;
2333 }
2334
2335 if (hi2c->XferCount != 0U)
2336 {
2337 if (hi2c->hdmatx != NULL)
2338 {
2339 /* Set the I2C DMA transfer complete callback */
2340 hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
2341
2342 /* Set the DMA error callback */
2343 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2344
2345 /* Set the unused DMA callbacks to NULL */
2346 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2347 hi2c->hdmatx->XferAbortCallback = NULL;
2348
2349 /* Enable the DMA channel */
2350 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
2351 {
2352 if (hi2c->hdmatx->LinkedListQueue != NULL)
2353 {
2354 /* Set DMA data size */
2355 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
2356
2357 /* Set DMA source address */
2358 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr;
2359
2360 /* Set DMA destination address */
2361 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
2362 = (uint32_t)&hi2c->Instance->TXDR;
2363
2364 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
2365 }
2366 else
2367 {
2368 /* Update I2C state */
2369 hi2c->State = HAL_I2C_STATE_LISTEN;
2370 hi2c->Mode = HAL_I2C_MODE_NONE;
2371
2372 /* Update I2C error code */
2373 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2374
2375 /* Process Unlocked */
2376 __HAL_UNLOCK(hi2c);
2377
2378 return HAL_ERROR;
2379 }
2380 }
2381 else
2382 {
2383 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx,
2384 (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
2385 hi2c->XferSize);
2386 }
2387 }
2388 else
2389 {
2390 /* Update I2C state */
2391 hi2c->State = HAL_I2C_STATE_LISTEN;
2392 hi2c->Mode = HAL_I2C_MODE_NONE;
2393
2394 /* Update I2C error code */
2395 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2396
2397 /* Process Unlocked */
2398 __HAL_UNLOCK(hi2c);
2399
2400 return HAL_ERROR;
2401 }
2402
2403 if (dmaxferstatus == HAL_OK)
2404 {
2405 /* Enable Address Acknowledge */
2406 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2407
2408 /* Process Unlocked */
2409 __HAL_UNLOCK(hi2c);
2410
2411 /* Note : The I2C interrupts must be enabled after unlocking current process
2412 to avoid the risk of I2C interrupt handle execution before current
2413 process unlock */
2414 /* Enable ERR, STOP, NACK, ADDR interrupts */
2415 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2416
2417 /* Enable DMA Request */
2418 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
2419 }
2420 else
2421 {
2422 /* Update I2C state */
2423 hi2c->State = HAL_I2C_STATE_LISTEN;
2424 hi2c->Mode = HAL_I2C_MODE_NONE;
2425
2426 /* Update I2C error code */
2427 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2428
2429 /* Process Unlocked */
2430 __HAL_UNLOCK(hi2c);
2431
2432 return HAL_ERROR;
2433 }
2434 }
2435 else
2436 {
2437 /* Enable Address Acknowledge */
2438 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2439
2440 /* Process Unlocked */
2441 __HAL_UNLOCK(hi2c);
2442
2443 /* Note : The I2C interrupts must be enabled after unlocking current process
2444 to avoid the risk of I2C interrupt handle execution before current
2445 process unlock */
2446 /* Enable ERR, STOP, NACK, ADDR interrupts */
2447 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2448 }
2449
2450 return HAL_OK;
2451 }
2452 else
2453 {
2454 return HAL_BUSY;
2455 }
2456 }
2457
2458 /**
2459 * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
2460 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2461 * the configuration information for the specified I2C.
2462 * @param pData Pointer to data buffer
2463 * @param Size Amount of data to be sent
2464 * @retval HAL status
2465 */
HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2466 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2467 {
2468 HAL_StatusTypeDef dmaxferstatus;
2469
2470 if (hi2c->State == HAL_I2C_STATE_READY)
2471 {
2472 if ((pData == NULL) || (Size == 0U))
2473 {
2474 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2475 return HAL_ERROR;
2476 }
2477 /* Process Locked */
2478 __HAL_LOCK(hi2c);
2479
2480 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2481 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2482 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2483
2484 /* Prepare transfer parameters */
2485 hi2c->pBuffPtr = pData;
2486 hi2c->XferCount = Size;
2487 hi2c->XferSize = hi2c->XferCount;
2488 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2489 hi2c->XferISR = I2C_Slave_ISR_DMA;
2490
2491 if (hi2c->hdmarx != NULL)
2492 {
2493 /* Set the I2C DMA transfer complete callback */
2494 hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
2495
2496 /* Set the DMA error callback */
2497 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2498
2499 /* Set the unused DMA callbacks to NULL */
2500 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2501 hi2c->hdmarx->XferAbortCallback = NULL;
2502
2503 /* Enable the DMA channel */
2504 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
2505 {
2506 if (hi2c->hdmarx->LinkedListQueue != NULL)
2507 {
2508 /* Set DMA data size */
2509 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
2510
2511 /* Set DMA source address */
2512 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
2513 = (uint32_t)&hi2c->Instance->RXDR;
2514
2515 /* Set DMA destination address */
2516 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
2517
2518 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
2519 }
2520 else
2521 {
2522 /* Update I2C state */
2523 hi2c->State = HAL_I2C_STATE_LISTEN;
2524 hi2c->Mode = HAL_I2C_MODE_NONE;
2525
2526 /* Update I2C error code */
2527 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2528
2529 /* Process Unlocked */
2530 __HAL_UNLOCK(hi2c);
2531
2532 return HAL_ERROR;
2533 }
2534 }
2535 else
2536 {
2537 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
2538 hi2c->XferSize);
2539 }
2540 }
2541 else
2542 {
2543 /* Update I2C state */
2544 hi2c->State = HAL_I2C_STATE_LISTEN;
2545 hi2c->Mode = HAL_I2C_MODE_NONE;
2546
2547 /* Update I2C error code */
2548 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2549
2550 /* Process Unlocked */
2551 __HAL_UNLOCK(hi2c);
2552
2553 return HAL_ERROR;
2554 }
2555
2556 if (dmaxferstatus == HAL_OK)
2557 {
2558 /* Enable Address Acknowledge */
2559 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2560
2561 /* Process Unlocked */
2562 __HAL_UNLOCK(hi2c);
2563
2564 /* Note : The I2C interrupts must be enabled after unlocking current process
2565 to avoid the risk of I2C interrupt handle execution before current
2566 process unlock */
2567 /* Enable ERR, STOP, NACK, ADDR interrupts */
2568 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2569
2570 /* Enable DMA Request */
2571 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2572 }
2573 else
2574 {
2575 /* Update I2C state */
2576 hi2c->State = HAL_I2C_STATE_LISTEN;
2577 hi2c->Mode = HAL_I2C_MODE_NONE;
2578
2579 /* Update I2C error code */
2580 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2581
2582 /* Process Unlocked */
2583 __HAL_UNLOCK(hi2c);
2584
2585 return HAL_ERROR;
2586 }
2587
2588 return HAL_OK;
2589 }
2590 else
2591 {
2592 return HAL_BUSY;
2593 }
2594 }
2595 #endif /* HAL_DMA_MODULE_ENABLED */
2596
2597 /**
2598 * @brief Write an amount of data in blocking mode to a specific memory address
2599 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2600 * the configuration information for the specified I2C.
2601 * @param DevAddress Target device address: The device 7 bits address value
2602 * in datasheet must be shifted to the left before calling the interface
2603 * @param MemAddress Internal memory address
2604 * @param MemAddSize Size of internal memory address
2605 * @param pData Pointer to data buffer
2606 * @param Size Amount of data to be sent
2607 * @param Timeout Timeout duration
2608 * @retval HAL status
2609 */
HAL_I2C_Mem_Write(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2610 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2611 uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2612 {
2613 uint32_t tickstart;
2614
2615 /* Check the parameters */
2616 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2617
2618 if (hi2c->State == HAL_I2C_STATE_READY)
2619 {
2620 if ((pData == NULL) || (Size == 0U))
2621 {
2622 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2623 return HAL_ERROR;
2624 }
2625
2626 /* Process Locked */
2627 __HAL_LOCK(hi2c);
2628
2629 /* Init tickstart for timeout management*/
2630 tickstart = HAL_GetTick();
2631
2632 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
2633 {
2634 return HAL_ERROR;
2635 }
2636
2637 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2638 hi2c->Mode = HAL_I2C_MODE_MEM;
2639 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2640
2641 /* Prepare transfer parameters */
2642 hi2c->pBuffPtr = pData;
2643 hi2c->XferCount = Size;
2644 hi2c->XferISR = NULL;
2645
2646 /* Send Slave Address and Memory Address */
2647 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2648 {
2649 /* Process Unlocked */
2650 __HAL_UNLOCK(hi2c);
2651 return HAL_ERROR;
2652 }
2653
2654 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
2655 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2656 {
2657 hi2c->XferSize = MAX_NBYTE_SIZE;
2658 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
2659 }
2660 else
2661 {
2662 hi2c->XferSize = hi2c->XferCount;
2663 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
2664 }
2665
2666 do
2667 {
2668 /* Wait until TXIS flag is set */
2669 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2670 {
2671 return HAL_ERROR;
2672 }
2673
2674 /* Write data to TXDR */
2675 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
2676
2677 /* Increment Buffer pointer */
2678 hi2c->pBuffPtr++;
2679
2680 hi2c->XferCount--;
2681 hi2c->XferSize--;
2682
2683 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
2684 {
2685 /* Wait until TCR flag is set */
2686 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
2687 {
2688 return HAL_ERROR;
2689 }
2690
2691 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2692 {
2693 hi2c->XferSize = MAX_NBYTE_SIZE;
2694 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
2695 I2C_NO_STARTSTOP);
2696 }
2697 else
2698 {
2699 hi2c->XferSize = hi2c->XferCount;
2700 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2701 I2C_NO_STARTSTOP);
2702 }
2703 }
2704
2705 } while (hi2c->XferCount > 0U);
2706
2707 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2708 /* Wait until STOPF flag is reset */
2709 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2710 {
2711 return HAL_ERROR;
2712 }
2713
2714 /* Clear STOP Flag */
2715 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2716
2717 /* Clear Configuration Register 2 */
2718 I2C_RESET_CR2(hi2c);
2719
2720 hi2c->State = HAL_I2C_STATE_READY;
2721 hi2c->Mode = HAL_I2C_MODE_NONE;
2722
2723 /* Process Unlocked */
2724 __HAL_UNLOCK(hi2c);
2725
2726 return HAL_OK;
2727 }
2728 else
2729 {
2730 return HAL_BUSY;
2731 }
2732 }
2733
2734 /**
2735 * @brief Read an amount of data in blocking mode from a specific memory address
2736 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2737 * the configuration information for the specified I2C.
2738 * @param DevAddress Target device address: The device 7 bits address value
2739 * in datasheet must be shifted to the left before calling the interface
2740 * @param MemAddress Internal memory address
2741 * @param MemAddSize Size of internal memory address
2742 * @param pData Pointer to data buffer
2743 * @param Size Amount of data to be sent
2744 * @param Timeout Timeout duration
2745 * @retval HAL status
2746 */
HAL_I2C_Mem_Read(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2747 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2748 uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2749 {
2750 uint32_t tickstart;
2751
2752 /* Check the parameters */
2753 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2754
2755 if (hi2c->State == HAL_I2C_STATE_READY)
2756 {
2757 if ((pData == NULL) || (Size == 0U))
2758 {
2759 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2760 return HAL_ERROR;
2761 }
2762
2763 /* Process Locked */
2764 __HAL_LOCK(hi2c);
2765
2766 /* Init tickstart for timeout management*/
2767 tickstart = HAL_GetTick();
2768
2769 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
2770 {
2771 return HAL_ERROR;
2772 }
2773
2774 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2775 hi2c->Mode = HAL_I2C_MODE_MEM;
2776 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2777
2778 /* Prepare transfer parameters */
2779 hi2c->pBuffPtr = pData;
2780 hi2c->XferCount = Size;
2781 hi2c->XferISR = NULL;
2782
2783 /* Send Slave Address and Memory Address */
2784 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2785 {
2786 /* Process Unlocked */
2787 __HAL_UNLOCK(hi2c);
2788 return HAL_ERROR;
2789 }
2790
2791 /* Send Slave Address */
2792 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2793 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2794 {
2795 hi2c->XferSize = MAX_NBYTE_SIZE;
2796 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
2797 I2C_GENERATE_START_READ);
2798 }
2799 else
2800 {
2801 hi2c->XferSize = hi2c->XferCount;
2802 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2803 I2C_GENERATE_START_READ);
2804 }
2805
2806 do
2807 {
2808 /* Wait until RXNE flag is set */
2809 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
2810 {
2811 return HAL_ERROR;
2812 }
2813
2814 /* Read data from RXDR */
2815 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
2816
2817 /* Increment Buffer pointer */
2818 hi2c->pBuffPtr++;
2819
2820 hi2c->XferSize--;
2821 hi2c->XferCount--;
2822
2823 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
2824 {
2825 /* Wait until TCR flag is set */
2826 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
2827 {
2828 return HAL_ERROR;
2829 }
2830
2831 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2832 {
2833 hi2c->XferSize = MAX_NBYTE_SIZE;
2834 I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
2835 I2C_NO_STARTSTOP);
2836 }
2837 else
2838 {
2839 hi2c->XferSize = hi2c->XferCount;
2840 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2841 I2C_NO_STARTSTOP);
2842 }
2843 }
2844 } while (hi2c->XferCount > 0U);
2845
2846 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2847 /* Wait until STOPF flag is reset */
2848 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2849 {
2850 return HAL_ERROR;
2851 }
2852
2853 /* Clear STOP Flag */
2854 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2855
2856 /* Clear Configuration Register 2 */
2857 I2C_RESET_CR2(hi2c);
2858
2859 hi2c->State = HAL_I2C_STATE_READY;
2860 hi2c->Mode = HAL_I2C_MODE_NONE;
2861
2862 /* Process Unlocked */
2863 __HAL_UNLOCK(hi2c);
2864
2865 return HAL_OK;
2866 }
2867 else
2868 {
2869 return HAL_BUSY;
2870 }
2871 }
2872 /**
2873 * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
2874 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2875 * the configuration information for the specified I2C.
2876 * @param DevAddress Target device address: The device 7 bits address value
2877 * in datasheet must be shifted to the left before calling the interface
2878 * @param MemAddress Internal memory address
2879 * @param MemAddSize Size of internal memory address
2880 * @param pData Pointer to data buffer
2881 * @param Size Amount of data to be sent
2882 * @retval HAL status
2883 */
HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2884 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2885 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2886 {
2887 /* Check the parameters */
2888 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2889
2890 if (hi2c->State == HAL_I2C_STATE_READY)
2891 {
2892 if ((pData == NULL) || (Size == 0U))
2893 {
2894 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2895 return HAL_ERROR;
2896 }
2897
2898 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2899 {
2900 return HAL_BUSY;
2901 }
2902
2903 /* Process Locked */
2904 __HAL_LOCK(hi2c);
2905
2906 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2907 hi2c->Mode = HAL_I2C_MODE_MEM;
2908 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2909
2910 /* Prepare transfer parameters */
2911 hi2c->XferSize = 0U;
2912 hi2c->pBuffPtr = pData;
2913 hi2c->XferCount = Size;
2914 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2915 hi2c->XferISR = I2C_Mem_ISR_IT;
2916 hi2c->Devaddress = DevAddress;
2917
2918 /* If Memory address size is 8Bit */
2919 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
2920 {
2921 /* Prefetch Memory Address */
2922 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
2923
2924 /* Reset Memaddress content */
2925 hi2c->Memaddress = 0xFFFFFFFFU;
2926 }
2927 /* If Memory address size is 16Bit */
2928 else
2929 {
2930 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
2931 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
2932
2933 /* Prepare Memaddress buffer for LSB part */
2934 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
2935 }
2936 /* Send Slave Address and Memory Address */
2937 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
2938
2939 /* Process Unlocked */
2940 __HAL_UNLOCK(hi2c);
2941
2942 /* Note : The I2C interrupts must be enabled after unlocking current process
2943 to avoid the risk of I2C interrupt handle execution before current
2944 process unlock */
2945
2946 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2947 /* possible to enable all of these */
2948 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2949 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2950 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2951
2952 return HAL_OK;
2953 }
2954 else
2955 {
2956 return HAL_BUSY;
2957 }
2958 }
2959
2960 /**
2961 * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
2962 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2963 * the configuration information for the specified I2C.
2964 * @param DevAddress Target device address: The device 7 bits address value
2965 * in datasheet must be shifted to the left before calling the interface
2966 * @param MemAddress Internal memory address
2967 * @param MemAddSize Size of internal memory address
2968 * @param pData Pointer to data buffer
2969 * @param Size Amount of data to be sent
2970 * @retval HAL status
2971 */
HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2972 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2973 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2974 {
2975 /* Check the parameters */
2976 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2977
2978 if (hi2c->State == HAL_I2C_STATE_READY)
2979 {
2980 if ((pData == NULL) || (Size == 0U))
2981 {
2982 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2983 return HAL_ERROR;
2984 }
2985
2986 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2987 {
2988 return HAL_BUSY;
2989 }
2990
2991 /* Process Locked */
2992 __HAL_LOCK(hi2c);
2993
2994 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2995 hi2c->Mode = HAL_I2C_MODE_MEM;
2996 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2997
2998 /* Prepare transfer parameters */
2999 hi2c->pBuffPtr = pData;
3000 hi2c->XferCount = Size;
3001 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3002 hi2c->XferISR = I2C_Mem_ISR_IT;
3003 hi2c->Devaddress = DevAddress;
3004
3005 /* If Memory address size is 8Bit */
3006 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
3007 {
3008 /* Prefetch Memory Address */
3009 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3010
3011 /* Reset Memaddress content */
3012 hi2c->Memaddress = 0xFFFFFFFFU;
3013 }
3014 /* If Memory address size is 16Bit */
3015 else
3016 {
3017 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
3018 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
3019
3020 /* Prepare Memaddress buffer for LSB part */
3021 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
3022 }
3023 /* Send Slave Address and Memory Address */
3024 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
3025
3026 /* Process Unlocked */
3027 __HAL_UNLOCK(hi2c);
3028
3029 /* Note : The I2C interrupts must be enabled after unlocking current process
3030 to avoid the risk of I2C interrupt handle execution before current
3031 process unlock */
3032
3033 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3034 /* possible to enable all of these */
3035 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3036 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3037 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3038
3039 return HAL_OK;
3040 }
3041 else
3042 {
3043 return HAL_BUSY;
3044 }
3045 }
3046
3047 #if defined(HAL_DMA_MODULE_ENABLED)
3048 /**
3049 * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
3050 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3051 * the configuration information for the specified I2C.
3052 * @param DevAddress Target device address: The device 7 bits address value
3053 * in datasheet must be shifted to the left before calling the interface
3054 * @param MemAddress Internal memory address
3055 * @param MemAddSize Size of internal memory address
3056 * @param pData Pointer to data buffer
3057 * @param Size Amount of data to be sent
3058 * @retval HAL status
3059 */
HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)3060 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
3061 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3062 {
3063 HAL_StatusTypeDef dmaxferstatus;
3064
3065 /* Check the parameters */
3066 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3067
3068 if (hi2c->State == HAL_I2C_STATE_READY)
3069 {
3070 if ((pData == NULL) || (Size == 0U))
3071 {
3072 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3073 return HAL_ERROR;
3074 }
3075
3076 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3077 {
3078 return HAL_BUSY;
3079 }
3080
3081 /* Process Locked */
3082 __HAL_LOCK(hi2c);
3083
3084 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3085 hi2c->Mode = HAL_I2C_MODE_MEM;
3086 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3087
3088 /* Prepare transfer parameters */
3089 hi2c->pBuffPtr = pData;
3090 hi2c->XferCount = Size;
3091 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3092 hi2c->XferISR = I2C_Mem_ISR_DMA;
3093 hi2c->Devaddress = DevAddress;
3094
3095 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3096 {
3097 hi2c->XferSize = MAX_NBYTE_SIZE;
3098 }
3099 else
3100 {
3101 hi2c->XferSize = hi2c->XferCount;
3102 }
3103
3104 /* If Memory address size is 8Bit */
3105 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
3106 {
3107 /* Prefetch Memory Address */
3108 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3109
3110 /* Reset Memaddress content */
3111 hi2c->Memaddress = 0xFFFFFFFFU;
3112 }
3113 /* If Memory address size is 16Bit */
3114 else
3115 {
3116 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
3117 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
3118
3119 /* Prepare Memaddress buffer for LSB part */
3120 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
3121 }
3122
3123 if (hi2c->hdmatx != NULL)
3124 {
3125 /* Set the I2C DMA transfer complete callback */
3126 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
3127
3128 /* Set the DMA error callback */
3129 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3130
3131 /* Set the unused DMA callbacks to NULL */
3132 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3133 hi2c->hdmatx->XferAbortCallback = NULL;
3134
3135 /* Enable the DMA channel */
3136 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
3137 {
3138 if (hi2c->hdmatx->LinkedListQueue != NULL)
3139 {
3140 /* Set DMA data size */
3141 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
3142
3143 /* Set DMA source address */
3144 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
3145
3146 /* Set DMA destination address */
3147 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
3148 = (uint32_t)&hi2c->Instance->TXDR;
3149
3150 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
3151 }
3152 else
3153 {
3154 /* Update I2C state */
3155 hi2c->State = HAL_I2C_STATE_READY;
3156 hi2c->Mode = HAL_I2C_MODE_NONE;
3157
3158 /* Update I2C error code */
3159 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3160
3161 /* Process Unlocked */
3162 __HAL_UNLOCK(hi2c);
3163
3164 return HAL_ERROR;
3165 }
3166 }
3167 else
3168 {
3169 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
3170 hi2c->XferSize);
3171 }
3172 }
3173 else
3174 {
3175 /* Update I2C state */
3176 hi2c->State = HAL_I2C_STATE_READY;
3177 hi2c->Mode = HAL_I2C_MODE_NONE;
3178
3179 /* Update I2C error code */
3180 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3181
3182 /* Process Unlocked */
3183 __HAL_UNLOCK(hi2c);
3184
3185 return HAL_ERROR;
3186 }
3187
3188 if (dmaxferstatus == HAL_OK)
3189 {
3190 /* Send Slave Address and Memory Address */
3191 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
3192
3193 /* Process Unlocked */
3194 __HAL_UNLOCK(hi2c);
3195
3196 /* Note : The I2C interrupts must be enabled after unlocking current process
3197 to avoid the risk of I2C interrupt handle execution before current
3198 process unlock */
3199 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3200 /* possible to enable all of these */
3201 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3202 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3203 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3204 }
3205 else
3206 {
3207 /* Update I2C state */
3208 hi2c->State = HAL_I2C_STATE_READY;
3209 hi2c->Mode = HAL_I2C_MODE_NONE;
3210
3211 /* Update I2C error code */
3212 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3213
3214 /* Process Unlocked */
3215 __HAL_UNLOCK(hi2c);
3216
3217 return HAL_ERROR;
3218 }
3219
3220 return HAL_OK;
3221 }
3222 else
3223 {
3224 return HAL_BUSY;
3225 }
3226 }
3227
3228 /**
3229 * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
3230 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3231 * the configuration information for the specified I2C.
3232 * @param DevAddress Target device address: The device 7 bits address value
3233 * in datasheet must be shifted to the left before calling the interface
3234 * @param MemAddress Internal memory address
3235 * @param MemAddSize Size of internal memory address
3236 * @param pData Pointer to data buffer
3237 * @param Size Amount of data to be read
3238 * @retval HAL status
3239 */
HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)3240 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
3241 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3242 {
3243 HAL_StatusTypeDef dmaxferstatus;
3244
3245 /* Check the parameters */
3246 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3247
3248 if (hi2c->State == HAL_I2C_STATE_READY)
3249 {
3250 if ((pData == NULL) || (Size == 0U))
3251 {
3252 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3253 return HAL_ERROR;
3254 }
3255
3256 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3257 {
3258 return HAL_BUSY;
3259 }
3260
3261 /* Process Locked */
3262 __HAL_LOCK(hi2c);
3263
3264 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3265 hi2c->Mode = HAL_I2C_MODE_MEM;
3266 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3267
3268 /* Prepare transfer parameters */
3269 hi2c->pBuffPtr = pData;
3270 hi2c->XferCount = Size;
3271 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3272 hi2c->XferISR = I2C_Mem_ISR_DMA;
3273 hi2c->Devaddress = DevAddress;
3274
3275 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3276 {
3277 hi2c->XferSize = MAX_NBYTE_SIZE;
3278 }
3279 else
3280 {
3281 hi2c->XferSize = hi2c->XferCount;
3282 }
3283
3284 /* If Memory address size is 8Bit */
3285 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
3286 {
3287 /* Prefetch Memory Address */
3288 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3289
3290 /* Reset Memaddress content */
3291 hi2c->Memaddress = 0xFFFFFFFFU;
3292 }
3293 /* If Memory address size is 16Bit */
3294 else
3295 {
3296 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
3297 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
3298
3299 /* Prepare Memaddress buffer for LSB part */
3300 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
3301 }
3302
3303 if (hi2c->hdmarx != NULL)
3304 {
3305 /* Set the I2C DMA transfer complete callback */
3306 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
3307
3308 /* Set the DMA error callback */
3309 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3310
3311 /* Set the unused DMA callbacks to NULL */
3312 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3313 hi2c->hdmarx->XferAbortCallback = NULL;
3314
3315 /* Enable the DMA channel */
3316 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
3317 {
3318 if (hi2c->hdmarx->LinkedListQueue != NULL)
3319 {
3320 /* Set DMA data size */
3321 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
3322
3323 /* Set DMA source address */
3324 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
3325 = (uint32_t)&hi2c->Instance->RXDR;
3326
3327 /* Set DMA destination address */
3328 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
3329
3330 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
3331 }
3332 else
3333 {
3334 /* Update I2C state */
3335 hi2c->State = HAL_I2C_STATE_READY;
3336 hi2c->Mode = HAL_I2C_MODE_NONE;
3337
3338 /* Update I2C error code */
3339 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3340
3341 /* Process Unlocked */
3342 __HAL_UNLOCK(hi2c);
3343
3344 return HAL_ERROR;
3345 }
3346 }
3347 else
3348 {
3349 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
3350 hi2c->XferSize);
3351 }
3352 }
3353 else
3354 {
3355 /* Update I2C state */
3356 hi2c->State = HAL_I2C_STATE_READY;
3357 hi2c->Mode = HAL_I2C_MODE_NONE;
3358
3359 /* Update I2C error code */
3360 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3361
3362 /* Process Unlocked */
3363 __HAL_UNLOCK(hi2c);
3364
3365 return HAL_ERROR;
3366 }
3367
3368 if (dmaxferstatus == HAL_OK)
3369 {
3370 /* Send Slave Address and Memory Address */
3371 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
3372
3373 /* Process Unlocked */
3374 __HAL_UNLOCK(hi2c);
3375
3376 /* Note : The I2C interrupts must be enabled after unlocking current process
3377 to avoid the risk of I2C interrupt handle execution before current
3378 process unlock */
3379 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3380 /* possible to enable all of these */
3381 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3382 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3383 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3384 }
3385 else
3386 {
3387 /* Update I2C state */
3388 hi2c->State = HAL_I2C_STATE_READY;
3389 hi2c->Mode = HAL_I2C_MODE_NONE;
3390
3391 /* Update I2C error code */
3392 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3393
3394 /* Process Unlocked */
3395 __HAL_UNLOCK(hi2c);
3396
3397 return HAL_ERROR;
3398 }
3399
3400 return HAL_OK;
3401 }
3402 else
3403 {
3404 return HAL_BUSY;
3405 }
3406 }
3407 #endif /* HAL_DMA_MODULE_ENABLED */
3408
3409 /**
3410 * @brief Checks if target device is ready for communication.
3411 * @note This function is used with Memory devices
3412 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3413 * the configuration information for the specified I2C.
3414 * @param DevAddress Target device address: The device 7 bits address value
3415 * in datasheet must be shifted to the left before calling the interface
3416 * @param Trials Number of trials
3417 * @param Timeout Timeout duration
3418 * @retval HAL status
3419 */
HAL_I2C_IsDeviceReady(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Trials,uint32_t Timeout)3420 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
3421 uint32_t Timeout)
3422 {
3423 uint32_t tickstart;
3424
3425 __IO uint32_t I2C_Trials = 0UL;
3426
3427 HAL_StatusTypeDef status = HAL_OK;
3428
3429 FlagStatus tmp1;
3430 FlagStatus tmp2;
3431
3432 if (hi2c->State == HAL_I2C_STATE_READY)
3433 {
3434 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3435 {
3436 return HAL_BUSY;
3437 }
3438
3439 /* Process Locked */
3440 __HAL_LOCK(hi2c);
3441
3442 hi2c->State = HAL_I2C_STATE_BUSY;
3443 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3444
3445 do
3446 {
3447 /* Generate Start */
3448 hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
3449
3450 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
3451 /* Wait until STOPF flag is set or a NACK flag is set*/
3452 tickstart = HAL_GetTick();
3453
3454 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
3455 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3456
3457 while ((tmp1 == RESET) && (tmp2 == RESET))
3458 {
3459 if (Timeout != HAL_MAX_DELAY)
3460 {
3461 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3462 {
3463 /* Update I2C state */
3464 hi2c->State = HAL_I2C_STATE_READY;
3465
3466 /* Update I2C error code */
3467 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3468
3469 /* Process Unlocked */
3470 __HAL_UNLOCK(hi2c);
3471
3472 return HAL_ERROR;
3473 }
3474 }
3475
3476 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
3477 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3478 }
3479
3480 /* Check if the NACKF flag has not been set */
3481 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
3482 {
3483 /* Wait until STOPF flag is reset */
3484 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3485 {
3486 /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */
3487 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
3488 {
3489 /* Clear STOP Flag */
3490 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3491
3492 /* Reset the error code for next trial */
3493 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3494 }
3495 else
3496 {
3497 status = HAL_ERROR;
3498 }
3499 }
3500 else
3501 {
3502 /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */
3503
3504 /* Clear STOP Flag */
3505 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3506
3507 /* Device is ready */
3508 hi2c->State = HAL_I2C_STATE_READY;
3509
3510 /* Process Unlocked */
3511 __HAL_UNLOCK(hi2c);
3512
3513 return HAL_OK;
3514 }
3515 }
3516 else
3517 {
3518 /* A non acknowledge is detected, this mean that device not respond to its address,
3519 a new trial must be performed */
3520
3521 /* Clear NACK Flag */
3522 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3523
3524 /* Wait until STOPF flag is reset */
3525 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3526 {
3527 status = HAL_ERROR;
3528 }
3529 else
3530 {
3531 /* Clear STOP Flag, auto generated with autoend*/
3532 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3533 }
3534 }
3535
3536 /* Increment Trials */
3537 I2C_Trials++;
3538
3539 if ((I2C_Trials < Trials) && (status == HAL_ERROR))
3540 {
3541 status = HAL_OK;
3542 }
3543
3544 } while (I2C_Trials < Trials);
3545
3546 /* Update I2C state */
3547 hi2c->State = HAL_I2C_STATE_READY;
3548
3549 /* Update I2C error code */
3550 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3551
3552 /* Process Unlocked */
3553 __HAL_UNLOCK(hi2c);
3554
3555 return HAL_ERROR;
3556 }
3557 else
3558 {
3559 return HAL_BUSY;
3560 }
3561 }
3562
3563 /**
3564 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
3565 * @note This interface allow to manage repeated start condition when a direction change during transfer
3566 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3567 * the configuration information for the specified I2C.
3568 * @param DevAddress Target device address: The device 7 bits address value
3569 * in datasheet must be shifted to the left before calling the interface
3570 * @param pData Pointer to data buffer
3571 * @param Size Amount of data to be sent
3572 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3573 * @retval HAL status
3574 */
HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3575 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3576 uint16_t Size, uint32_t XferOptions)
3577 {
3578 uint32_t xfermode;
3579 uint32_t xferrequest = I2C_GENERATE_START_WRITE;
3580
3581 /* Check the parameters */
3582 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3583
3584 if (hi2c->State == HAL_I2C_STATE_READY)
3585 {
3586 /* Process Locked */
3587 __HAL_LOCK(hi2c);
3588
3589 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3590 hi2c->Mode = HAL_I2C_MODE_MASTER;
3591 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3592
3593 /* Prepare transfer parameters */
3594 hi2c->pBuffPtr = pData;
3595 hi2c->XferCount = Size;
3596 hi2c->XferOptions = XferOptions;
3597 hi2c->XferISR = I2C_Master_ISR_IT;
3598
3599 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3600 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3601 {
3602 hi2c->XferSize = MAX_NBYTE_SIZE;
3603 xfermode = I2C_RELOAD_MODE;
3604 }
3605 else
3606 {
3607 hi2c->XferSize = hi2c->XferCount;
3608 xfermode = hi2c->XferOptions;
3609 }
3610
3611 /* If transfer direction not change and there is no request to start another frame,
3612 do not generate Restart Condition */
3613 /* Mean Previous state is same as current state */
3614 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
3615 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3616 {
3617 xferrequest = I2C_NO_STARTSTOP;
3618 }
3619 else
3620 {
3621 /* Convert OTHER_xxx XferOptions if any */
3622 I2C_ConvertOtherXferOptions(hi2c);
3623
3624 /* Update xfermode accordingly if no reload is necessary */
3625 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3626 {
3627 xfermode = hi2c->XferOptions;
3628 }
3629 }
3630
3631 /* Send Slave Address and set NBYTES to write */
3632 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3633
3634 /* Process Unlocked */
3635 __HAL_UNLOCK(hi2c);
3636
3637 /* Note : The I2C interrupts must be enabled after unlocking current process
3638 to avoid the risk of I2C interrupt handle execution before current
3639 process unlock */
3640 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3641 /* possible to enable all of these */
3642 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3643 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3644 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3645
3646 return HAL_OK;
3647 }
3648 else
3649 {
3650 return HAL_BUSY;
3651 }
3652 }
3653
3654 #if defined(HAL_DMA_MODULE_ENABLED)
3655 /**
3656 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
3657 * @note This interface allow to manage repeated start condition when a direction change during transfer
3658 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3659 * the configuration information for the specified I2C.
3660 * @param DevAddress Target device address: The device 7 bits address value
3661 * in datasheet must be shifted to the left before calling the interface
3662 * @param pData Pointer to data buffer
3663 * @param Size Amount of data to be sent
3664 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3665 * @retval HAL status
3666 */
HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3667 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3668 uint16_t Size, uint32_t XferOptions)
3669 {
3670 uint32_t xfermode;
3671 uint32_t xferrequest = I2C_GENERATE_START_WRITE;
3672 HAL_StatusTypeDef dmaxferstatus;
3673
3674 /* Check the parameters */
3675 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3676
3677 if (hi2c->State == HAL_I2C_STATE_READY)
3678 {
3679 /* Process Locked */
3680 __HAL_LOCK(hi2c);
3681
3682 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3683 hi2c->Mode = HAL_I2C_MODE_MASTER;
3684 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3685
3686 /* Prepare transfer parameters */
3687 hi2c->pBuffPtr = pData;
3688 hi2c->XferCount = Size;
3689 hi2c->XferOptions = XferOptions;
3690 hi2c->XferISR = I2C_Master_ISR_DMA;
3691
3692 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3693 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3694 {
3695 hi2c->XferSize = MAX_NBYTE_SIZE;
3696 xfermode = I2C_RELOAD_MODE;
3697 }
3698 else
3699 {
3700 hi2c->XferSize = hi2c->XferCount;
3701 xfermode = hi2c->XferOptions;
3702 }
3703
3704 /* If transfer direction not change and there is no request to start another frame,
3705 do not generate Restart Condition */
3706 /* Mean Previous state is same as current state */
3707 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
3708 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3709 {
3710 xferrequest = I2C_NO_STARTSTOP;
3711 }
3712 else
3713 {
3714 /* Convert OTHER_xxx XferOptions if any */
3715 I2C_ConvertOtherXferOptions(hi2c);
3716
3717 /* Update xfermode accordingly if no reload is necessary */
3718 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3719 {
3720 xfermode = hi2c->XferOptions;
3721 }
3722 }
3723
3724 if (hi2c->XferSize > 0U)
3725 {
3726 if (hi2c->hdmatx != NULL)
3727 {
3728 /* Set the I2C DMA transfer complete callback */
3729 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
3730
3731 /* Set the DMA error callback */
3732 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3733
3734 /* Set the unused DMA callbacks to NULL */
3735 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3736 hi2c->hdmatx->XferAbortCallback = NULL;
3737
3738 /* Enable the DMA channel */
3739 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
3740 {
3741 if (hi2c->hdmatx->LinkedListQueue != NULL)
3742 {
3743 /* Set DMA data size */
3744 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
3745
3746 /* Set DMA source address */
3747 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
3748
3749 /* Set DMA destination address */
3750 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
3751 = (uint32_t)&hi2c->Instance->TXDR;
3752
3753 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
3754 }
3755 else
3756 {
3757 /* Update I2C state */
3758 hi2c->State = HAL_I2C_STATE_READY;
3759 hi2c->Mode = HAL_I2C_MODE_NONE;
3760
3761 /* Update I2C error code */
3762 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3763
3764 /* Process Unlocked */
3765 __HAL_UNLOCK(hi2c);
3766
3767 return HAL_ERROR;
3768 }
3769 }
3770 else
3771 {
3772 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
3773 hi2c->XferSize);
3774 }
3775 }
3776 else
3777 {
3778 /* Update I2C state */
3779 hi2c->State = HAL_I2C_STATE_READY;
3780 hi2c->Mode = HAL_I2C_MODE_NONE;
3781
3782 /* Update I2C error code */
3783 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3784
3785 /* Process Unlocked */
3786 __HAL_UNLOCK(hi2c);
3787
3788 return HAL_ERROR;
3789 }
3790
3791 if (dmaxferstatus == HAL_OK)
3792 {
3793 /* Send Slave Address and set NBYTES to write */
3794 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3795
3796 /* Update XferCount value */
3797 hi2c->XferCount -= hi2c->XferSize;
3798
3799 /* Process Unlocked */
3800 __HAL_UNLOCK(hi2c);
3801
3802 /* Note : The I2C interrupts must be enabled after unlocking current process
3803 to avoid the risk of I2C interrupt handle execution before current
3804 process unlock */
3805 /* Enable ERR and NACK interrupts */
3806 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
3807
3808 /* Enable DMA Request */
3809 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
3810 }
3811 else
3812 {
3813 /* Update I2C state */
3814 hi2c->State = HAL_I2C_STATE_READY;
3815 hi2c->Mode = HAL_I2C_MODE_NONE;
3816
3817 /* Update I2C error code */
3818 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3819
3820 /* Process Unlocked */
3821 __HAL_UNLOCK(hi2c);
3822
3823 return HAL_ERROR;
3824 }
3825 }
3826 else
3827 {
3828 /* Update Transfer ISR function pointer */
3829 hi2c->XferISR = I2C_Master_ISR_IT;
3830
3831 /* Send Slave Address */
3832 /* Set NBYTES to write and generate START condition */
3833 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
3834 I2C_GENERATE_START_WRITE);
3835
3836 /* Process Unlocked */
3837 __HAL_UNLOCK(hi2c);
3838
3839 /* Note : The I2C interrupts must be enabled after unlocking current process
3840 to avoid the risk of I2C interrupt handle execution before current
3841 process unlock */
3842 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3843 /* possible to enable all of these */
3844 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3845 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3846 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3847 }
3848
3849 return HAL_OK;
3850 }
3851 else
3852 {
3853 return HAL_BUSY;
3854 }
3855 }
3856 #endif /* HAL_DMA_MODULE_ENABLED */
3857
3858 /**
3859 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
3860 * @note This interface allow to manage repeated start condition when a direction change during transfer
3861 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3862 * the configuration information for the specified I2C.
3863 * @param DevAddress Target device address: The device 7 bits address value
3864 * in datasheet must be shifted to the left before calling the interface
3865 * @param pData Pointer to data buffer
3866 * @param Size Amount of data to be sent
3867 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3868 * @retval HAL status
3869 */
HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3870 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3871 uint16_t Size, uint32_t XferOptions)
3872 {
3873 uint32_t xfermode;
3874 uint32_t xferrequest = I2C_GENERATE_START_READ;
3875
3876 /* Check the parameters */
3877 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3878
3879 if (hi2c->State == HAL_I2C_STATE_READY)
3880 {
3881 /* Process Locked */
3882 __HAL_LOCK(hi2c);
3883
3884 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3885 hi2c->Mode = HAL_I2C_MODE_MASTER;
3886 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3887
3888 /* Prepare transfer parameters */
3889 hi2c->pBuffPtr = pData;
3890 hi2c->XferCount = Size;
3891 hi2c->XferOptions = XferOptions;
3892 hi2c->XferISR = I2C_Master_ISR_IT;
3893
3894 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3895 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3896 {
3897 hi2c->XferSize = MAX_NBYTE_SIZE;
3898 xfermode = I2C_RELOAD_MODE;
3899 }
3900 else
3901 {
3902 hi2c->XferSize = hi2c->XferCount;
3903 xfermode = hi2c->XferOptions;
3904 }
3905
3906 /* If transfer direction not change and there is no request to start another frame,
3907 do not generate Restart Condition */
3908 /* Mean Previous state is same as current state */
3909 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
3910 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3911 {
3912 xferrequest = I2C_NO_STARTSTOP;
3913 }
3914 else
3915 {
3916 /* Convert OTHER_xxx XferOptions if any */
3917 I2C_ConvertOtherXferOptions(hi2c);
3918
3919 /* Update xfermode accordingly if no reload is necessary */
3920 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3921 {
3922 xfermode = hi2c->XferOptions;
3923 }
3924 }
3925
3926 /* Send Slave Address and set NBYTES to read */
3927 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3928
3929 /* Process Unlocked */
3930 __HAL_UNLOCK(hi2c);
3931
3932 /* Note : The I2C interrupts must be enabled after unlocking current process
3933 to avoid the risk of I2C interrupt handle execution before current
3934 process unlock */
3935 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
3936
3937 return HAL_OK;
3938 }
3939 else
3940 {
3941 return HAL_BUSY;
3942 }
3943 }
3944
3945 #if defined(HAL_DMA_MODULE_ENABLED)
3946 /**
3947 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
3948 * @note This interface allow to manage repeated start condition when a direction change during transfer
3949 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3950 * the configuration information for the specified I2C.
3951 * @param DevAddress Target device address: The device 7 bits address value
3952 * in datasheet must be shifted to the left before calling the interface
3953 * @param pData Pointer to data buffer
3954 * @param Size Amount of data to be sent
3955 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3956 * @retval HAL status
3957 */
HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3958 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3959 uint16_t Size, uint32_t XferOptions)
3960 {
3961 uint32_t xfermode;
3962 uint32_t xferrequest = I2C_GENERATE_START_READ;
3963 HAL_StatusTypeDef dmaxferstatus;
3964
3965 /* Check the parameters */
3966 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3967
3968 if (hi2c->State == HAL_I2C_STATE_READY)
3969 {
3970 /* Process Locked */
3971 __HAL_LOCK(hi2c);
3972
3973 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3974 hi2c->Mode = HAL_I2C_MODE_MASTER;
3975 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3976
3977 /* Prepare transfer parameters */
3978 hi2c->pBuffPtr = pData;
3979 hi2c->XferCount = Size;
3980 hi2c->XferOptions = XferOptions;
3981 hi2c->XferISR = I2C_Master_ISR_DMA;
3982
3983 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3984 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3985 {
3986 hi2c->XferSize = MAX_NBYTE_SIZE;
3987 xfermode = I2C_RELOAD_MODE;
3988 }
3989 else
3990 {
3991 hi2c->XferSize = hi2c->XferCount;
3992 xfermode = hi2c->XferOptions;
3993 }
3994
3995 /* If transfer direction not change and there is no request to start another frame,
3996 do not generate Restart Condition */
3997 /* Mean Previous state is same as current state */
3998 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
3999 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
4000 {
4001 xferrequest = I2C_NO_STARTSTOP;
4002 }
4003 else
4004 {
4005 /* Convert OTHER_xxx XferOptions if any */
4006 I2C_ConvertOtherXferOptions(hi2c);
4007
4008 /* Update xfermode accordingly if no reload is necessary */
4009 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
4010 {
4011 xfermode = hi2c->XferOptions;
4012 }
4013 }
4014
4015 if (hi2c->XferSize > 0U)
4016 {
4017 if (hi2c->hdmarx != NULL)
4018 {
4019 /* Set the I2C DMA transfer complete callback */
4020 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
4021
4022 /* Set the DMA error callback */
4023 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4024
4025 /* Set the unused DMA callbacks to NULL */
4026 hi2c->hdmarx->XferHalfCpltCallback = NULL;
4027 hi2c->hdmarx->XferAbortCallback = NULL;
4028
4029 /* Enable the DMA channel */
4030 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
4031 {
4032 if (hi2c->hdmarx->LinkedListQueue != NULL)
4033 {
4034 /* Set DMA data size */
4035 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
4036
4037 /* Set DMA source address */
4038 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
4039 = (uint32_t)&hi2c->Instance->RXDR;
4040
4041 /* Set DMA destination address */
4042 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
4043
4044 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
4045 }
4046 else
4047 {
4048 hi2c->State = HAL_I2C_STATE_READY;
4049 hi2c->Mode = HAL_I2C_MODE_NONE;
4050
4051 /* Update I2C error code */
4052 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4053
4054 /* Process Unlocked */
4055 __HAL_UNLOCK(hi2c);
4056
4057 return HAL_ERROR;
4058 }
4059 }
4060 else
4061 {
4062 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
4063 hi2c->XferSize);
4064 }
4065 }
4066 else
4067 {
4068 /* Update I2C state */
4069 hi2c->State = HAL_I2C_STATE_READY;
4070 hi2c->Mode = HAL_I2C_MODE_NONE;
4071
4072 /* Update I2C error code */
4073 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4074
4075 /* Process Unlocked */
4076 __HAL_UNLOCK(hi2c);
4077
4078 return HAL_ERROR;
4079 }
4080
4081 if (dmaxferstatus == HAL_OK)
4082 {
4083 /* Send Slave Address and set NBYTES to read */
4084 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
4085
4086 /* Update XferCount value */
4087 hi2c->XferCount -= hi2c->XferSize;
4088
4089 /* Process Unlocked */
4090 __HAL_UNLOCK(hi2c);
4091
4092 /* Note : The I2C interrupts must be enabled after unlocking current process
4093 to avoid the risk of I2C interrupt handle execution before current
4094 process unlock */
4095 /* Enable ERR and NACK interrupts */
4096 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
4097
4098 /* Enable DMA Request */
4099 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
4100 }
4101 else
4102 {
4103 /* Update I2C state */
4104 hi2c->State = HAL_I2C_STATE_READY;
4105 hi2c->Mode = HAL_I2C_MODE_NONE;
4106
4107 /* Update I2C error code */
4108 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4109
4110 /* Process Unlocked */
4111 __HAL_UNLOCK(hi2c);
4112
4113 return HAL_ERROR;
4114 }
4115 }
4116 else
4117 {
4118 /* Update Transfer ISR function pointer */
4119 hi2c->XferISR = I2C_Master_ISR_IT;
4120
4121 /* Send Slave Address */
4122 /* Set NBYTES to read and generate START condition */
4123 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
4124 I2C_GENERATE_START_READ);
4125
4126 /* Process Unlocked */
4127 __HAL_UNLOCK(hi2c);
4128
4129 /* Note : The I2C interrupts must be enabled after unlocking current process
4130 to avoid the risk of I2C interrupt handle execution before current
4131 process unlock */
4132 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
4133 /* possible to enable all of these */
4134 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
4135 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
4136 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
4137 }
4138
4139 return HAL_OK;
4140 }
4141 else
4142 {
4143 return HAL_BUSY;
4144 }
4145 }
4146 #endif /* HAL_DMA_MODULE_ENABLED */
4147
4148 /**
4149 * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
4150 * @note This interface allow to manage repeated start condition when a direction change during transfer
4151 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4152 * the configuration information for the specified I2C.
4153 * @param pData Pointer to data buffer
4154 * @param Size Amount of data to be sent
4155 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4156 * @retval HAL status
4157 */
HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4158 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4159 uint32_t XferOptions)
4160 {
4161 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4162 FlagStatus tmp;
4163
4164 /* Check the parameters */
4165 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4166
4167 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4168 {
4169 if ((pData == NULL) || (Size == 0U))
4170 {
4171 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4172 return HAL_ERROR;
4173 }
4174
4175 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4176 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
4177
4178 /* Process Locked */
4179 __HAL_LOCK(hi2c);
4180
4181 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4182 /* and then toggle the HAL slave RX state to TX state */
4183 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4184 {
4185 /* Disable associated Interrupts */
4186 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
4187
4188 #if defined(HAL_DMA_MODULE_ENABLED)
4189 /* Abort DMA Xfer if any */
4190 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4191 {
4192 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4193
4194 if (hi2c->hdmarx != NULL)
4195 {
4196 /* Set the I2C DMA Abort callback :
4197 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4198 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4199
4200 /* Abort DMA RX */
4201 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4202 {
4203 /* Call Directly XferAbortCallback function in case of error */
4204 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4205 }
4206 }
4207 }
4208 #endif /* HAL_DMA_MODULE_ENABLED */
4209 }
4210
4211 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4212 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4213 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4214
4215 /* Enable Address Acknowledge */
4216 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4217
4218 /* Prepare transfer parameters */
4219 hi2c->pBuffPtr = pData;
4220 hi2c->XferCount = Size;
4221 hi2c->XferSize = hi2c->XferCount;
4222 hi2c->XferOptions = XferOptions;
4223 hi2c->XferISR = I2C_Slave_ISR_IT;
4224
4225 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4226 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
4227 {
4228 /* Clear ADDR flag after prepare the transfer parameters */
4229 /* This action will generate an acknowledge to the Master */
4230 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4231 }
4232
4233 /* Process Unlocked */
4234 __HAL_UNLOCK(hi2c);
4235
4236 /* Note : The I2C interrupts must be enabled after unlocking current process
4237 to avoid the risk of I2C interrupt handle execution before current
4238 process unlock */
4239 /* REnable ADDR interrupt */
4240 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
4241
4242 return HAL_OK;
4243 }
4244 else
4245 {
4246 return HAL_ERROR;
4247 }
4248 }
4249
4250 #if defined(HAL_DMA_MODULE_ENABLED)
4251 /**
4252 * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
4253 * @note This interface allow to manage repeated start condition when a direction change during transfer
4254 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4255 * the configuration information for the specified I2C.
4256 * @param pData Pointer to data buffer
4257 * @param Size Amount of data to be sent
4258 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4259 * @retval HAL status
4260 */
HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4261 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4262 uint32_t XferOptions)
4263 {
4264 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4265 FlagStatus tmp;
4266 HAL_StatusTypeDef dmaxferstatus;
4267
4268 /* Check the parameters */
4269 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4270
4271 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4272 {
4273 if ((pData == NULL) || (Size == 0U))
4274 {
4275 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4276 return HAL_ERROR;
4277 }
4278
4279 /* Process Locked */
4280 __HAL_LOCK(hi2c);
4281
4282 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4283 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
4284
4285 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4286 /* and then toggle the HAL slave RX state to TX state */
4287 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4288 {
4289 /* Disable associated Interrupts */
4290 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
4291
4292 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4293 {
4294 /* Abort DMA Xfer if any */
4295 if (hi2c->hdmarx != NULL)
4296 {
4297 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4298
4299 /* Set the I2C DMA Abort callback :
4300 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4301 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4302
4303 /* Abort DMA RX */
4304 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4305 {
4306 /* Call Directly XferAbortCallback function in case of error */
4307 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4308 }
4309 }
4310 }
4311 }
4312 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4313 {
4314 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4315 {
4316 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4317
4318 /* Abort DMA Xfer if any */
4319 if (hi2c->hdmatx != NULL)
4320 {
4321 /* Set the I2C DMA Abort callback :
4322 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4323 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4324
4325 /* Abort DMA TX */
4326 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4327 {
4328 /* Call Directly XferAbortCallback function in case of error */
4329 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4330 }
4331 }
4332 }
4333 }
4334 else
4335 {
4336 /* Nothing to do */
4337 }
4338
4339 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4340 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4341 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4342
4343 /* Enable Address Acknowledge */
4344 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4345
4346 /* Prepare transfer parameters */
4347 hi2c->pBuffPtr = pData;
4348 hi2c->XferCount = Size;
4349 hi2c->XferSize = hi2c->XferCount;
4350 hi2c->XferOptions = XferOptions;
4351 hi2c->XferISR = I2C_Slave_ISR_DMA;
4352
4353 if (hi2c->hdmatx != NULL)
4354 {
4355 /* Set the I2C DMA transfer complete callback */
4356 hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
4357
4358 /* Set the DMA error callback */
4359 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
4360
4361 /* Set the unused DMA callbacks to NULL */
4362 hi2c->hdmatx->XferHalfCpltCallback = NULL;
4363 hi2c->hdmatx->XferAbortCallback = NULL;
4364
4365 /* Enable the DMA channel */
4366 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
4367 {
4368 if (hi2c->hdmatx->LinkedListQueue != NULL)
4369 {
4370 /* Set DMA data size */
4371 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
4372
4373 /* Set DMA source address */
4374 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
4375
4376 /* Set DMA destination address */
4377 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
4378 = (uint32_t)&hi2c->Instance->TXDR;
4379
4380 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
4381 }
4382 else
4383 {
4384 /* Update I2C state */
4385 hi2c->State = HAL_I2C_STATE_LISTEN;
4386 hi2c->Mode = HAL_I2C_MODE_NONE;
4387
4388 /* Update I2C error code */
4389 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4390
4391 /* Process Unlocked */
4392 __HAL_UNLOCK(hi2c);
4393
4394 return HAL_ERROR;
4395 }
4396 }
4397 else
4398 {
4399 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
4400 hi2c->XferSize);
4401 }
4402 }
4403 else
4404 {
4405 /* Update I2C state */
4406 hi2c->State = HAL_I2C_STATE_LISTEN;
4407 hi2c->Mode = HAL_I2C_MODE_NONE;
4408
4409 /* Update I2C error code */
4410 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4411
4412 /* Process Unlocked */
4413 __HAL_UNLOCK(hi2c);
4414
4415 return HAL_ERROR;
4416 }
4417
4418 if (dmaxferstatus == HAL_OK)
4419 {
4420 /* Update XferCount value */
4421 hi2c->XferCount -= hi2c->XferSize;
4422
4423 /* Reset XferSize */
4424 hi2c->XferSize = 0;
4425 }
4426 else
4427 {
4428 /* Update I2C state */
4429 hi2c->State = HAL_I2C_STATE_LISTEN;
4430 hi2c->Mode = HAL_I2C_MODE_NONE;
4431
4432 /* Update I2C error code */
4433 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4434
4435 /* Process Unlocked */
4436 __HAL_UNLOCK(hi2c);
4437
4438 return HAL_ERROR;
4439 }
4440
4441 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4442 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
4443 {
4444 /* Clear ADDR flag after prepare the transfer parameters */
4445 /* This action will generate an acknowledge to the Master */
4446 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4447 }
4448
4449 /* Process Unlocked */
4450 __HAL_UNLOCK(hi2c);
4451
4452 /* Enable DMA Request */
4453 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
4454
4455 /* Note : The I2C interrupts must be enabled after unlocking current process
4456 to avoid the risk of I2C interrupt handle execution before current
4457 process unlock */
4458 /* Enable ERR, STOP, NACK, ADDR interrupts */
4459 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4460
4461 return HAL_OK;
4462 }
4463 else
4464 {
4465 return HAL_ERROR;
4466 }
4467 }
4468 #endif /* HAL_DMA_MODULE_ENABLED */
4469
4470 /**
4471 * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
4472 * @note This interface allow to manage repeated start condition when a direction change during transfer
4473 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4474 * the configuration information for the specified I2C.
4475 * @param pData Pointer to data buffer
4476 * @param Size Amount of data to be sent
4477 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4478 * @retval HAL status
4479 */
HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4480 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4481 uint32_t XferOptions)
4482 {
4483 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4484 FlagStatus tmp;
4485
4486 /* Check the parameters */
4487 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4488
4489 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4490 {
4491 if ((pData == NULL) || (Size == 0U))
4492 {
4493 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4494 return HAL_ERROR;
4495 }
4496
4497 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4498 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
4499
4500 /* Process Locked */
4501 __HAL_LOCK(hi2c);
4502
4503 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4504 /* and then toggle the HAL slave TX state to RX state */
4505 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4506 {
4507 /* Disable associated Interrupts */
4508 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4509
4510 #if defined(HAL_DMA_MODULE_ENABLED)
4511 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4512 {
4513 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4514
4515 /* Abort DMA Xfer if any */
4516 if (hi2c->hdmatx != NULL)
4517 {
4518 /* Set the I2C DMA Abort callback :
4519 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4520 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4521
4522 /* Abort DMA TX */
4523 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4524 {
4525 /* Call Directly XferAbortCallback function in case of error */
4526 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4527 }
4528 }
4529 }
4530 #endif /* HAL_DMA_MODULE_ENABLED */
4531 }
4532
4533 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4534 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4535 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4536
4537 /* Enable Address Acknowledge */
4538 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4539
4540 /* Prepare transfer parameters */
4541 hi2c->pBuffPtr = pData;
4542 hi2c->XferCount = Size;
4543 hi2c->XferSize = hi2c->XferCount;
4544 hi2c->XferOptions = XferOptions;
4545 hi2c->XferISR = I2C_Slave_ISR_IT;
4546
4547 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4548 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
4549 {
4550 /* Clear ADDR flag after prepare the transfer parameters */
4551 /* This action will generate an acknowledge to the Master */
4552 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4553 }
4554
4555 /* Process Unlocked */
4556 __HAL_UNLOCK(hi2c);
4557
4558 /* Note : The I2C interrupts must be enabled after unlocking current process
4559 to avoid the risk of I2C interrupt handle execution before current
4560 process unlock */
4561 /* REnable ADDR interrupt */
4562 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
4563
4564 return HAL_OK;
4565 }
4566 else
4567 {
4568 return HAL_ERROR;
4569 }
4570 }
4571
4572 #if defined(HAL_DMA_MODULE_ENABLED)
4573 /**
4574 * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
4575 * @note This interface allow to manage repeated start condition when a direction change during transfer
4576 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4577 * the configuration information for the specified I2C.
4578 * @param pData Pointer to data buffer
4579 * @param Size Amount of data to be sent
4580 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4581 * @retval HAL status
4582 */
HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4583 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4584 uint32_t XferOptions)
4585 {
4586 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4587 FlagStatus tmp;
4588 HAL_StatusTypeDef dmaxferstatus;
4589
4590 /* Check the parameters */
4591 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4592
4593 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4594 {
4595 if ((pData == NULL) || (Size == 0U))
4596 {
4597 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4598 return HAL_ERROR;
4599 }
4600
4601 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4602 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
4603
4604 /* Process Locked */
4605 __HAL_LOCK(hi2c);
4606
4607 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4608 /* and then toggle the HAL slave TX state to RX state */
4609 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4610 {
4611 /* Disable associated Interrupts */
4612 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4613
4614 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4615 {
4616 /* Abort DMA Xfer if any */
4617 if (hi2c->hdmatx != NULL)
4618 {
4619 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4620
4621 /* Set the I2C DMA Abort callback :
4622 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4623 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4624
4625 /* Abort DMA TX */
4626 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4627 {
4628 /* Call Directly XferAbortCallback function in case of error */
4629 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4630 }
4631 }
4632 }
4633 }
4634 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4635 {
4636 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4637 {
4638 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4639
4640 /* Abort DMA Xfer if any */
4641 if (hi2c->hdmarx != NULL)
4642 {
4643 /* Set the I2C DMA Abort callback :
4644 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4645 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4646
4647 /* Abort DMA RX */
4648 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4649 {
4650 /* Call Directly XferAbortCallback function in case of error */
4651 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4652 }
4653 }
4654 }
4655 }
4656 else
4657 {
4658 /* Nothing to do */
4659 }
4660
4661 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4662 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4663 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4664
4665 /* Enable Address Acknowledge */
4666 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4667
4668 /* Prepare transfer parameters */
4669 hi2c->pBuffPtr = pData;
4670 hi2c->XferCount = Size;
4671 hi2c->XferSize = hi2c->XferCount;
4672 hi2c->XferOptions = XferOptions;
4673 hi2c->XferISR = I2C_Slave_ISR_DMA;
4674
4675 if (hi2c->hdmarx != NULL)
4676 {
4677 /* Set the I2C DMA transfer complete callback */
4678 hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
4679
4680 /* Set the DMA error callback */
4681 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4682
4683 /* Set the unused DMA callbacks to NULL */
4684 hi2c->hdmarx->XferHalfCpltCallback = NULL;
4685 hi2c->hdmarx->XferAbortCallback = NULL;
4686
4687 /* Enable the DMA channel */
4688 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
4689 {
4690 if (hi2c->hdmarx->LinkedListQueue != NULL)
4691 {
4692 /* Set DMA data size */
4693 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
4694
4695 /* Set DMA source address */
4696 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
4697 = (uint32_t)&hi2c->Instance->RXDR;
4698
4699 /* Set DMA destination address */
4700 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
4701
4702 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
4703 }
4704 else
4705 {
4706 /* Update I2C state */
4707 hi2c->State = HAL_I2C_STATE_LISTEN;
4708 hi2c->Mode = HAL_I2C_MODE_NONE;
4709
4710 /* Update I2C error code */
4711 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4712
4713 /* Process Unlocked */
4714 __HAL_UNLOCK(hi2c);
4715
4716 return HAL_ERROR;
4717 }
4718 }
4719 else
4720 {
4721 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
4722 hi2c->XferSize);
4723 }
4724 }
4725 else
4726 {
4727 /* Update I2C state */
4728 hi2c->State = HAL_I2C_STATE_LISTEN;
4729 hi2c->Mode = HAL_I2C_MODE_NONE;
4730
4731 /* Update I2C error code */
4732 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4733
4734 /* Process Unlocked */
4735 __HAL_UNLOCK(hi2c);
4736
4737 return HAL_ERROR;
4738 }
4739
4740 if (dmaxferstatus == HAL_OK)
4741 {
4742 /* Update XferCount value */
4743 hi2c->XferCount -= hi2c->XferSize;
4744
4745 /* Reset XferSize */
4746 hi2c->XferSize = 0;
4747 }
4748 else
4749 {
4750 /* Update I2C state */
4751 hi2c->State = HAL_I2C_STATE_LISTEN;
4752 hi2c->Mode = HAL_I2C_MODE_NONE;
4753
4754 /* Update I2C error code */
4755 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4756
4757 /* Process Unlocked */
4758 __HAL_UNLOCK(hi2c);
4759
4760 return HAL_ERROR;
4761 }
4762
4763 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4764 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
4765 {
4766 /* Clear ADDR flag after prepare the transfer parameters */
4767 /* This action will generate an acknowledge to the Master */
4768 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4769 }
4770
4771 /* Process Unlocked */
4772 __HAL_UNLOCK(hi2c);
4773
4774 /* Enable DMA Request */
4775 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
4776
4777 /* Note : The I2C interrupts must be enabled after unlocking current process
4778 to avoid the risk of I2C interrupt handle execution before current
4779 process unlock */
4780 /* REnable ADDR interrupt */
4781 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
4782
4783 return HAL_OK;
4784 }
4785 else
4786 {
4787 return HAL_ERROR;
4788 }
4789 }
4790 #endif /* HAL_DMA_MODULE_ENABLED */
4791
4792 /**
4793 * @brief Enable the Address listen mode with Interrupt.
4794 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4795 * the configuration information for the specified I2C.
4796 * @retval HAL status
4797 */
HAL_I2C_EnableListen_IT(I2C_HandleTypeDef * hi2c)4798 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
4799 {
4800 if (hi2c->State == HAL_I2C_STATE_READY)
4801 {
4802 hi2c->State = HAL_I2C_STATE_LISTEN;
4803 hi2c->XferISR = I2C_Slave_ISR_IT;
4804
4805 /* Enable the Address Match interrupt */
4806 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4807
4808 return HAL_OK;
4809 }
4810 else
4811 {
4812 return HAL_BUSY;
4813 }
4814 }
4815
4816 /**
4817 * @brief Disable the Address listen mode with Interrupt.
4818 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4819 * the configuration information for the specified I2C
4820 * @retval HAL status
4821 */
HAL_I2C_DisableListen_IT(I2C_HandleTypeDef * hi2c)4822 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
4823 {
4824 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4825 uint32_t tmp;
4826
4827 /* Disable Address listen mode only if a transfer is not ongoing */
4828 if (hi2c->State == HAL_I2C_STATE_LISTEN)
4829 {
4830 tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
4831 hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
4832 hi2c->State = HAL_I2C_STATE_READY;
4833 hi2c->Mode = HAL_I2C_MODE_NONE;
4834 hi2c->XferISR = NULL;
4835
4836 /* Disable the Address Match interrupt */
4837 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4838
4839 return HAL_OK;
4840 }
4841 else
4842 {
4843 return HAL_BUSY;
4844 }
4845 }
4846
4847 /**
4848 * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt.
4849 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4850 * the configuration information for the specified I2C.
4851 * @param DevAddress Target device address: The device 7 bits address value
4852 * in datasheet must be shifted to the left before calling the interface
4853 * @retval HAL status
4854 */
HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress)4855 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
4856 {
4857 HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode;
4858
4859 if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM))
4860 {
4861 /* Process Locked */
4862 __HAL_LOCK(hi2c);
4863
4864 /* Disable Interrupts and Store Previous state */
4865 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
4866 {
4867 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4868 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
4869 }
4870 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
4871 {
4872 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
4873 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
4874 }
4875 else
4876 {
4877 /* Do nothing */
4878 }
4879
4880 /* Set State at HAL_I2C_STATE_ABORT */
4881 hi2c->State = HAL_I2C_STATE_ABORT;
4882
4883 /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
4884 /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
4885 I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
4886
4887 /* Process Unlocked */
4888 __HAL_UNLOCK(hi2c);
4889
4890 /* Note : The I2C interrupts must be enabled after unlocking current process
4891 to avoid the risk of I2C interrupt handle execution before current
4892 process unlock */
4893 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
4894
4895 return HAL_OK;
4896 }
4897 else
4898 {
4899 /* Wrong usage of abort function */
4900 /* This function should be used only in case of abort monitored by master device */
4901 return HAL_ERROR;
4902 }
4903 }
4904
4905 /**
4906 * @}
4907 */
4908
4909 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
4910 * @{
4911 */
4912
4913 /**
4914 * @brief This function handles I2C event interrupt request.
4915 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4916 * the configuration information for the specified I2C.
4917 * @retval None
4918 */
HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef * hi2c)4919 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */
4920 {
4921 /* Get current IT Flags and IT sources value */
4922 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
4923 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
4924
4925 /* I2C events treatment -------------------------------------*/
4926 if (hi2c->XferISR != NULL)
4927 {
4928 hi2c->XferISR(hi2c, itflags, itsources);
4929 }
4930 }
4931
4932 /**
4933 * @brief This function handles I2C error interrupt request.
4934 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4935 * the configuration information for the specified I2C.
4936 * @retval None
4937 */
HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef * hi2c)4938 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
4939 {
4940 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
4941 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
4942 uint32_t tmperror;
4943
4944 /* I2C Bus error interrupt occurred ------------------------------------*/
4945 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
4946 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4947 {
4948 hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
4949
4950 /* Clear BERR flag */
4951 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
4952 }
4953
4954 /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
4955 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
4956 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4957 {
4958 hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
4959
4960 /* Clear OVR flag */
4961 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
4962 }
4963
4964 /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
4965 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
4966 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4967 {
4968 hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
4969
4970 /* Clear ARLO flag */
4971 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
4972 }
4973
4974 /* Store current volatile hi2c->ErrorCode, misra rule */
4975 tmperror = hi2c->ErrorCode;
4976
4977 /* Call the Error Callback in case of Error detected */
4978 if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
4979 {
4980 I2C_ITError(hi2c, tmperror);
4981 }
4982 }
4983
4984 /**
4985 * @brief Master Tx Transfer completed callback.
4986 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4987 * the configuration information for the specified I2C.
4988 * @retval None
4989 */
HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef * hi2c)4990 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
4991 {
4992 /* Prevent unused argument(s) compilation warning */
4993 UNUSED(hi2c);
4994
4995 /* NOTE : This function should not be modified, when the callback is needed,
4996 the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
4997 */
4998 }
4999
5000 /**
5001 * @brief Master Rx Transfer completed callback.
5002 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5003 * the configuration information for the specified I2C.
5004 * @retval None
5005 */
HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef * hi2c)5006 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
5007 {
5008 /* Prevent unused argument(s) compilation warning */
5009 UNUSED(hi2c);
5010
5011 /* NOTE : This function should not be modified, when the callback is needed,
5012 the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
5013 */
5014 }
5015
5016 /** @brief Slave Tx Transfer completed callback.
5017 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5018 * the configuration information for the specified I2C.
5019 * @retval None
5020 */
HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef * hi2c)5021 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
5022 {
5023 /* Prevent unused argument(s) compilation warning */
5024 UNUSED(hi2c);
5025
5026 /* NOTE : This function should not be modified, when the callback is needed,
5027 the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
5028 */
5029 }
5030
5031 /**
5032 * @brief Slave Rx Transfer completed callback.
5033 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5034 * the configuration information for the specified I2C.
5035 * @retval None
5036 */
HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef * hi2c)5037 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
5038 {
5039 /* Prevent unused argument(s) compilation warning */
5040 UNUSED(hi2c);
5041
5042 /* NOTE : This function should not be modified, when the callback is needed,
5043 the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
5044 */
5045 }
5046
5047 /**
5048 * @brief Slave Address Match callback.
5049 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5050 * the configuration information for the specified I2C.
5051 * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
5052 * @param AddrMatchCode Address Match Code
5053 * @retval None
5054 */
HAL_I2C_AddrCallback(I2C_HandleTypeDef * hi2c,uint8_t TransferDirection,uint16_t AddrMatchCode)5055 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
5056 {
5057 /* Prevent unused argument(s) compilation warning */
5058 UNUSED(hi2c);
5059 UNUSED(TransferDirection);
5060 UNUSED(AddrMatchCode);
5061
5062 /* NOTE : This function should not be modified, when the callback is needed,
5063 the HAL_I2C_AddrCallback() could be implemented in the user file
5064 */
5065 }
5066
5067 /**
5068 * @brief Listen Complete callback.
5069 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5070 * the configuration information for the specified I2C.
5071 * @retval None
5072 */
HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef * hi2c)5073 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
5074 {
5075 /* Prevent unused argument(s) compilation warning */
5076 UNUSED(hi2c);
5077
5078 /* NOTE : This function should not be modified, when the callback is needed,
5079 the HAL_I2C_ListenCpltCallback() could be implemented in the user file
5080 */
5081 }
5082
5083 /**
5084 * @brief Memory Tx Transfer completed callback.
5085 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5086 * the configuration information for the specified I2C.
5087 * @retval None
5088 */
HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef * hi2c)5089 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
5090 {
5091 /* Prevent unused argument(s) compilation warning */
5092 UNUSED(hi2c);
5093
5094 /* NOTE : This function should not be modified, when the callback is needed,
5095 the HAL_I2C_MemTxCpltCallback could be implemented in the user file
5096 */
5097 }
5098
5099 /**
5100 * @brief Memory Rx Transfer completed callback.
5101 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5102 * the configuration information for the specified I2C.
5103 * @retval None
5104 */
HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef * hi2c)5105 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
5106 {
5107 /* Prevent unused argument(s) compilation warning */
5108 UNUSED(hi2c);
5109
5110 /* NOTE : This function should not be modified, when the callback is needed,
5111 the HAL_I2C_MemRxCpltCallback could be implemented in the user file
5112 */
5113 }
5114
5115 /**
5116 * @brief I2C error callback.
5117 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5118 * the configuration information for the specified I2C.
5119 * @retval None
5120 */
HAL_I2C_ErrorCallback(I2C_HandleTypeDef * hi2c)5121 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
5122 {
5123 /* Prevent unused argument(s) compilation warning */
5124 UNUSED(hi2c);
5125
5126 /* NOTE : This function should not be modified, when the callback is needed,
5127 the HAL_I2C_ErrorCallback could be implemented in the user file
5128 */
5129 }
5130
5131 /**
5132 * @brief I2C abort callback.
5133 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5134 * the configuration information for the specified I2C.
5135 * @retval None
5136 */
HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef * hi2c)5137 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
5138 {
5139 /* Prevent unused argument(s) compilation warning */
5140 UNUSED(hi2c);
5141
5142 /* NOTE : This function should not be modified, when the callback is needed,
5143 the HAL_I2C_AbortCpltCallback could be implemented in the user file
5144 */
5145 }
5146
5147 /**
5148 * @}
5149 */
5150
5151 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
5152 * @brief Peripheral State, Mode and Error functions
5153 *
5154 @verbatim
5155 ===============================================================================
5156 ##### Peripheral State, Mode and Error functions #####
5157 ===============================================================================
5158 [..]
5159 This subsection permit to get in run-time the status of the peripheral
5160 and the data flow.
5161
5162 @endverbatim
5163 * @{
5164 */
5165
5166 /**
5167 * @brief Return the I2C handle state.
5168 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5169 * the configuration information for the specified I2C.
5170 * @retval HAL state
5171 */
HAL_I2C_GetState(const I2C_HandleTypeDef * hi2c)5172 HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c)
5173 {
5174 /* Return I2C handle state */
5175 return hi2c->State;
5176 }
5177
5178 /**
5179 * @brief Returns the I2C Master, Slave, Memory or no mode.
5180 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5181 * the configuration information for I2C module
5182 * @retval HAL mode
5183 */
HAL_I2C_GetMode(const I2C_HandleTypeDef * hi2c)5184 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c)
5185 {
5186 return hi2c->Mode;
5187 }
5188
5189 /**
5190 * @brief Return the I2C error code.
5191 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5192 * the configuration information for the specified I2C.
5193 * @retval I2C Error Code
5194 */
HAL_I2C_GetError(const I2C_HandleTypeDef * hi2c)5195 uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c)
5196 {
5197 return hi2c->ErrorCode;
5198 }
5199
5200 /**
5201 * @}
5202 */
5203
5204 /**
5205 * @}
5206 */
5207
5208 /** @addtogroup I2C_Private_Functions
5209 * @{
5210 */
5211
5212 /**
5213 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
5214 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5215 * the configuration information for the specified I2C.
5216 * @param ITFlags Interrupt flags to handle.
5217 * @param ITSources Interrupt sources enabled.
5218 * @retval HAL status
5219 */
I2C_Master_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5220 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5221 uint32_t ITSources)
5222 {
5223 uint16_t devaddress;
5224 uint32_t tmpITFlags = ITFlags;
5225
5226 /* Process Locked */
5227 __HAL_LOCK(hi2c);
5228
5229 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
5230 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5231 {
5232 /* Clear NACK Flag */
5233 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5234
5235 /* Set corresponding Error Code */
5236 /* No need to generate STOP, it is automatically done */
5237 /* Error callback will be send during stop flag treatment */
5238 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5239
5240 /* Flush TX register */
5241 I2C_Flush_TXDR(hi2c);
5242 }
5243 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
5244 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
5245 {
5246 /* Remove RXNE flag on temporary variable as read done */
5247 tmpITFlags &= ~I2C_FLAG_RXNE;
5248
5249 /* Read data from RXDR */
5250 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
5251
5252 /* Increment Buffer pointer */
5253 hi2c->pBuffPtr++;
5254
5255 hi2c->XferSize--;
5256 hi2c->XferCount--;
5257 }
5258 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
5259 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5260 {
5261 /* Write data to TXDR */
5262 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
5263
5264 /* Increment Buffer pointer */
5265 hi2c->pBuffPtr++;
5266
5267 hi2c->XferSize--;
5268 hi2c->XferCount--;
5269 }
5270 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
5271 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5272 {
5273 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
5274 {
5275 devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
5276
5277 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5278 {
5279 hi2c->XferSize = MAX_NBYTE_SIZE;
5280 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5281 }
5282 else
5283 {
5284 hi2c->XferSize = hi2c->XferCount;
5285 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
5286 {
5287 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
5288 hi2c->XferOptions, I2C_NO_STARTSTOP);
5289 }
5290 else
5291 {
5292 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
5293 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5294 }
5295 }
5296 }
5297 else
5298 {
5299 /* Call TxCpltCallback() if no stop mode is set */
5300 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5301 {
5302 /* Call I2C Master Sequential complete process */
5303 I2C_ITMasterSeqCplt(hi2c);
5304 }
5305 else
5306 {
5307 /* Wrong size Status regarding TCR flag event */
5308 /* Call the corresponding callback to inform upper layer of End of Transfer */
5309 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5310 }
5311 }
5312 }
5313 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
5314 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5315 {
5316 if (hi2c->XferCount == 0U)
5317 {
5318 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5319 {
5320 /* Generate a stop condition in case of no transfer option */
5321 if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
5322 {
5323 /* Generate Stop */
5324 hi2c->Instance->CR2 |= I2C_CR2_STOP;
5325 }
5326 else
5327 {
5328 /* Call I2C Master Sequential complete process */
5329 I2C_ITMasterSeqCplt(hi2c);
5330 }
5331 }
5332 }
5333 else
5334 {
5335 /* Wrong size Status regarding TC flag event */
5336 /* Call the corresponding callback to inform upper layer of End of Transfer */
5337 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5338 }
5339 }
5340 else
5341 {
5342 /* Nothing to do */
5343 }
5344
5345 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5346 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5347 {
5348 /* Call I2C Master complete process */
5349 I2C_ITMasterCplt(hi2c, tmpITFlags);
5350 }
5351
5352 /* Process Unlocked */
5353 __HAL_UNLOCK(hi2c);
5354
5355 return HAL_OK;
5356 }
5357
5358 /**
5359 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.
5360 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5361 * the configuration information for the specified I2C.
5362 * @param ITFlags Interrupt flags to handle.
5363 * @param ITSources Interrupt sources enabled.
5364 * @retval HAL status
5365 */
I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5366 static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5367 uint32_t ITSources)
5368 {
5369 uint32_t direction = I2C_GENERATE_START_WRITE;
5370 uint32_t tmpITFlags = ITFlags;
5371
5372 /* Process Locked */
5373 __HAL_LOCK(hi2c);
5374
5375 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
5376 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5377 {
5378 /* Clear NACK Flag */
5379 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5380
5381 /* Set corresponding Error Code */
5382 /* No need to generate STOP, it is automatically done */
5383 /* Error callback will be send during stop flag treatment */
5384 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5385
5386 /* Flush TX register */
5387 I2C_Flush_TXDR(hi2c);
5388 }
5389 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
5390 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
5391 {
5392 /* Remove RXNE flag on temporary variable as read done */
5393 tmpITFlags &= ~I2C_FLAG_RXNE;
5394
5395 /* Read data from RXDR */
5396 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
5397
5398 /* Increment Buffer pointer */
5399 hi2c->pBuffPtr++;
5400
5401 hi2c->XferSize--;
5402 hi2c->XferCount--;
5403 }
5404 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
5405 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5406 {
5407 if (hi2c->Memaddress == 0xFFFFFFFFU)
5408 {
5409 /* Write data to TXDR */
5410 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
5411
5412 /* Increment Buffer pointer */
5413 hi2c->pBuffPtr++;
5414
5415 hi2c->XferSize--;
5416 hi2c->XferCount--;
5417 }
5418 else
5419 {
5420 /* Write LSB part of Memory Address */
5421 hi2c->Instance->TXDR = hi2c->Memaddress;
5422
5423 /* Reset Memaddress content */
5424 hi2c->Memaddress = 0xFFFFFFFFU;
5425 }
5426 }
5427 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
5428 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5429 {
5430 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
5431 {
5432 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5433 {
5434 hi2c->XferSize = MAX_NBYTE_SIZE;
5435 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5436 I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5437 }
5438 else
5439 {
5440 hi2c->XferSize = hi2c->XferCount;
5441 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5442 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5443 }
5444 }
5445 else
5446 {
5447 /* Wrong size Status regarding TCR flag event */
5448 /* Call the corresponding callback to inform upper layer of End of Transfer */
5449 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5450 }
5451 }
5452 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
5453 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5454 {
5455 /* Disable Interrupt related to address step */
5456 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5457
5458 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
5459 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
5460
5461 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5462 {
5463 direction = I2C_GENERATE_START_READ;
5464 }
5465
5466 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5467 {
5468 hi2c->XferSize = MAX_NBYTE_SIZE;
5469
5470 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
5471 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5472 I2C_RELOAD_MODE, direction);
5473 }
5474 else
5475 {
5476 hi2c->XferSize = hi2c->XferCount;
5477
5478 /* Set NBYTES to write and generate RESTART */
5479 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5480 I2C_AUTOEND_MODE, direction);
5481 }
5482 }
5483 else
5484 {
5485 /* Nothing to do */
5486 }
5487
5488 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5489 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5490 {
5491 /* Call I2C Master complete process */
5492 I2C_ITMasterCplt(hi2c, tmpITFlags);
5493 }
5494
5495 /* Process Unlocked */
5496 __HAL_UNLOCK(hi2c);
5497
5498 return HAL_OK;
5499 }
5500
5501 /**
5502 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
5503 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5504 * the configuration information for the specified I2C.
5505 * @param ITFlags Interrupt flags to handle.
5506 * @param ITSources Interrupt sources enabled.
5507 * @retval HAL status
5508 */
I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5509 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5510 uint32_t ITSources)
5511 {
5512 uint32_t tmpoptions = hi2c->XferOptions;
5513 uint32_t tmpITFlags = ITFlags;
5514
5515 /* Process locked */
5516 __HAL_LOCK(hi2c);
5517
5518 /* Check if STOPF is set */
5519 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5520 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5521 {
5522 /* Call I2C Slave complete process */
5523 I2C_ITSlaveCplt(hi2c, tmpITFlags);
5524 }
5525 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
5526 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5527 {
5528 /* Check that I2C transfer finished */
5529 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
5530 /* Mean XferCount == 0*/
5531 /* So clear Flag NACKF only */
5532 if (hi2c->XferCount == 0U)
5533 {
5534 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
5535 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
5536 Warning[Pa134]: left and right operands are identical */
5537 {
5538 /* Call I2C Listen complete process */
5539 I2C_ITListenCplt(hi2c, tmpITFlags);
5540 }
5541 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
5542 {
5543 /* Clear NACK Flag */
5544 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5545
5546 /* Flush TX register */
5547 I2C_Flush_TXDR(hi2c);
5548
5549 /* Last Byte is Transmitted */
5550 /* Call I2C Slave Sequential complete process */
5551 I2C_ITSlaveSeqCplt(hi2c);
5552 }
5553 else
5554 {
5555 /* Clear NACK Flag */
5556 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5557 }
5558 }
5559 else
5560 {
5561 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
5562 /* Clear NACK Flag */
5563 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5564
5565 /* Set ErrorCode corresponding to a Non-Acknowledge */
5566 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5567
5568 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
5569 {
5570 /* Call the corresponding callback to inform upper layer of End of Transfer */
5571 I2C_ITError(hi2c, hi2c->ErrorCode);
5572 }
5573 }
5574 }
5575 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
5576 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
5577 {
5578 if (hi2c->XferCount > 0U)
5579 {
5580 /* Read data from RXDR */
5581 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
5582
5583 /* Increment Buffer pointer */
5584 hi2c->pBuffPtr++;
5585
5586 hi2c->XferSize--;
5587 hi2c->XferCount--;
5588 }
5589
5590 if ((hi2c->XferCount == 0U) && \
5591 (tmpoptions != I2C_NO_OPTION_FRAME))
5592 {
5593 /* Call I2C Slave Sequential complete process */
5594 I2C_ITSlaveSeqCplt(hi2c);
5595 }
5596 }
5597 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
5598 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
5599 {
5600 I2C_ITAddrCplt(hi2c, tmpITFlags);
5601 }
5602 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
5603 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5604 {
5605 /* Write data to TXDR only if XferCount not reach "0" */
5606 /* A TXIS flag can be set, during STOP treatment */
5607 /* Check if all Data have already been sent */
5608 /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
5609 if (hi2c->XferCount > 0U)
5610 {
5611 /* Write data to TXDR */
5612 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
5613
5614 /* Increment Buffer pointer */
5615 hi2c->pBuffPtr++;
5616
5617 hi2c->XferCount--;
5618 hi2c->XferSize--;
5619 }
5620 else
5621 {
5622 if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
5623 {
5624 /* Last Byte is Transmitted */
5625 /* Call I2C Slave Sequential complete process */
5626 I2C_ITSlaveSeqCplt(hi2c);
5627 }
5628 }
5629 }
5630 else
5631 {
5632 /* Nothing to do */
5633 }
5634
5635 /* Process Unlocked */
5636 __HAL_UNLOCK(hi2c);
5637
5638 return HAL_OK;
5639 }
5640
5641 #if defined(HAL_DMA_MODULE_ENABLED)
5642 /**
5643 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
5644 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5645 * the configuration information for the specified I2C.
5646 * @param ITFlags Interrupt flags to handle.
5647 * @param ITSources Interrupt sources enabled.
5648 * @retval HAL status
5649 */
I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5650 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5651 uint32_t ITSources)
5652 {
5653 uint16_t devaddress;
5654 uint32_t xfermode;
5655
5656 /* Process Locked */
5657 __HAL_LOCK(hi2c);
5658
5659 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5660 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5661 {
5662 /* Clear NACK Flag */
5663 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5664
5665 /* Set corresponding Error Code */
5666 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5667
5668 /* No need to generate STOP, it is automatically done */
5669 /* But enable STOP interrupt, to treat it */
5670 /* Error callback will be send during stop flag treatment */
5671 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
5672
5673 /* Flush TX register */
5674 I2C_Flush_TXDR(hi2c);
5675 }
5676 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
5677 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5678 {
5679 /* Disable TC interrupt */
5680 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
5681
5682 if (hi2c->XferCount != 0U)
5683 {
5684 /* Recover Slave address */
5685 devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
5686
5687 /* Prepare the new XferSize to transfer */
5688 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5689 {
5690 hi2c->XferSize = MAX_NBYTE_SIZE;
5691 xfermode = I2C_RELOAD_MODE;
5692 }
5693 else
5694 {
5695 hi2c->XferSize = hi2c->XferCount;
5696 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
5697 {
5698 xfermode = hi2c->XferOptions;
5699 }
5700 else
5701 {
5702 xfermode = I2C_AUTOEND_MODE;
5703 }
5704 }
5705
5706 /* Set the new XferSize in Nbytes register */
5707 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
5708
5709 /* Update XferCount value */
5710 hi2c->XferCount -= hi2c->XferSize;
5711
5712 /* Enable DMA Request */
5713 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5714 {
5715 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5716 }
5717 else
5718 {
5719 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5720 }
5721 }
5722 else
5723 {
5724 /* Call TxCpltCallback() if no stop mode is set */
5725 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5726 {
5727 /* Call I2C Master Sequential complete process */
5728 I2C_ITMasterSeqCplt(hi2c);
5729 }
5730 else
5731 {
5732 /* Wrong size Status regarding TCR flag event */
5733 /* Call the corresponding callback to inform upper layer of End of Transfer */
5734 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5735 }
5736 }
5737 }
5738 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
5739 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5740 {
5741 if (hi2c->XferCount == 0U)
5742 {
5743 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5744 {
5745 /* Generate a stop condition in case of no transfer option */
5746 if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
5747 {
5748 /* Generate Stop */
5749 hi2c->Instance->CR2 |= I2C_CR2_STOP;
5750 }
5751 else
5752 {
5753 /* Call I2C Master Sequential complete process */
5754 I2C_ITMasterSeqCplt(hi2c);
5755 }
5756 }
5757 }
5758 else
5759 {
5760 /* Wrong size Status regarding TC flag event */
5761 /* Call the corresponding callback to inform upper layer of End of Transfer */
5762 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5763 }
5764 }
5765 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5766 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5767 {
5768 /* Call I2C Master complete process */
5769 I2C_ITMasterCplt(hi2c, ITFlags);
5770 }
5771 else
5772 {
5773 /* Nothing to do */
5774 }
5775
5776 /* Process Unlocked */
5777 __HAL_UNLOCK(hi2c);
5778
5779 return HAL_OK;
5780 }
5781
5782 /**
5783 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.
5784 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5785 * the configuration information for the specified I2C.
5786 * @param ITFlags Interrupt flags to handle.
5787 * @param ITSources Interrupt sources enabled.
5788 * @retval HAL status
5789 */
I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5790 static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5791 uint32_t ITSources)
5792 {
5793 uint32_t direction = I2C_GENERATE_START_WRITE;
5794
5795 /* Process Locked */
5796 __HAL_LOCK(hi2c);
5797
5798 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5799 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5800 {
5801 /* Clear NACK Flag */
5802 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5803
5804 /* Set corresponding Error Code */
5805 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5806
5807 /* No need to generate STOP, it is automatically done */
5808 /* But enable STOP interrupt, to treat it */
5809 /* Error callback will be send during stop flag treatment */
5810 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
5811
5812 /* Flush TX register */
5813 I2C_Flush_TXDR(hi2c);
5814 }
5815 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \
5816 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5817 {
5818 /* Write LSB part of Memory Address */
5819 hi2c->Instance->TXDR = hi2c->Memaddress;
5820
5821 /* Reset Memaddress content */
5822 hi2c->Memaddress = 0xFFFFFFFFU;
5823 }
5824 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
5825 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5826 {
5827 /* Disable Interrupt related to address step */
5828 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5829
5830 /* Enable only Error interrupt */
5831 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
5832
5833 if (hi2c->XferCount != 0U)
5834 {
5835 /* Prepare the new XferSize to transfer */
5836 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5837 {
5838 hi2c->XferSize = MAX_NBYTE_SIZE;
5839 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5840 I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5841 }
5842 else
5843 {
5844 hi2c->XferSize = hi2c->XferCount;
5845 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5846 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5847 }
5848
5849 /* Update XferCount value */
5850 hi2c->XferCount -= hi2c->XferSize;
5851
5852 /* Enable DMA Request */
5853 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5854 {
5855 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5856 }
5857 else
5858 {
5859 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5860 }
5861 }
5862 else
5863 {
5864 /* Wrong size Status regarding TCR flag event */
5865 /* Call the corresponding callback to inform upper layer of End of Transfer */
5866 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5867 }
5868 }
5869 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
5870 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5871 {
5872 /* Disable Interrupt related to address step */
5873 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5874
5875 /* Enable only Error and NACK interrupt for data transfer */
5876 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
5877
5878 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5879 {
5880 direction = I2C_GENERATE_START_READ;
5881 }
5882
5883 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5884 {
5885 hi2c->XferSize = MAX_NBYTE_SIZE;
5886
5887 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
5888 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5889 I2C_RELOAD_MODE, direction);
5890 }
5891 else
5892 {
5893 hi2c->XferSize = hi2c->XferCount;
5894
5895 /* Set NBYTES to write and generate RESTART */
5896 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5897 I2C_AUTOEND_MODE, direction);
5898 }
5899
5900 /* Update XferCount value */
5901 hi2c->XferCount -= hi2c->XferSize;
5902
5903 /* Enable DMA Request */
5904 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5905 {
5906 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5907 }
5908 else
5909 {
5910 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5911 }
5912 }
5913 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5914 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5915 {
5916 /* Call I2C Master complete process */
5917 I2C_ITMasterCplt(hi2c, ITFlags);
5918 }
5919 else
5920 {
5921 /* Nothing to do */
5922 }
5923
5924 /* Process Unlocked */
5925 __HAL_UNLOCK(hi2c);
5926
5927 return HAL_OK;
5928 }
5929
5930 /**
5931 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
5932 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5933 * the configuration information for the specified I2C.
5934 * @param ITFlags Interrupt flags to handle.
5935 * @param ITSources Interrupt sources enabled.
5936 * @retval HAL status
5937 */
I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5938 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5939 uint32_t ITSources)
5940 {
5941 uint32_t tmpoptions = hi2c->XferOptions;
5942 uint32_t treatdmanack = 0U;
5943 HAL_I2C_StateTypeDef tmpstate;
5944
5945 /* Process locked */
5946 __HAL_LOCK(hi2c);
5947
5948 /* Check if STOPF is set */
5949 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5950 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5951 {
5952 /* Call I2C Slave complete process */
5953 I2C_ITSlaveCplt(hi2c, ITFlags);
5954 }
5955 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5956 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5957 {
5958 /* Check that I2C transfer finished */
5959 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
5960 /* Mean XferCount == 0 */
5961 /* So clear Flag NACKF only */
5962 if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
5963 (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
5964 {
5965 /* Split check of hdmarx, for MISRA compliance */
5966 if (hi2c->hdmarx != NULL)
5967 {
5968 if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
5969 {
5970 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
5971 {
5972 treatdmanack = 1U;
5973 }
5974 }
5975 }
5976
5977 /* Split check of hdmatx, for MISRA compliance */
5978 if (hi2c->hdmatx != NULL)
5979 {
5980 if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
5981 {
5982 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
5983 {
5984 treatdmanack = 1U;
5985 }
5986 }
5987 }
5988
5989 if (treatdmanack == 1U)
5990 {
5991 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
5992 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
5993 Warning[Pa134]: left and right operands are identical */
5994 {
5995 /* Call I2C Listen complete process */
5996 I2C_ITListenCplt(hi2c, ITFlags);
5997 }
5998 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
5999 {
6000 /* Clear NACK Flag */
6001 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6002
6003 /* Flush TX register */
6004 I2C_Flush_TXDR(hi2c);
6005
6006 /* Last Byte is Transmitted */
6007 /* Call I2C Slave Sequential complete process */
6008 I2C_ITSlaveSeqCplt(hi2c);
6009 }
6010 else
6011 {
6012 /* Clear NACK Flag */
6013 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6014 }
6015 }
6016 else
6017 {
6018 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
6019 /* Clear NACK Flag */
6020 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6021
6022 /* Set ErrorCode corresponding to a Non-Acknowledge */
6023 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6024
6025 /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
6026 tmpstate = hi2c->State;
6027
6028 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
6029 {
6030 if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
6031 {
6032 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6033 }
6034 else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6035 {
6036 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6037 }
6038 else
6039 {
6040 /* Do nothing */
6041 }
6042
6043 /* Call the corresponding callback to inform upper layer of End of Transfer */
6044 I2C_ITError(hi2c, hi2c->ErrorCode);
6045 }
6046 }
6047 }
6048 else
6049 {
6050 /* Only Clear NACK Flag, no DMA treatment is pending */
6051 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6052 }
6053 }
6054 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
6055 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
6056 {
6057 I2C_ITAddrCplt(hi2c, ITFlags);
6058 }
6059 else
6060 {
6061 /* Nothing to do */
6062 }
6063
6064 /* Process Unlocked */
6065 __HAL_UNLOCK(hi2c);
6066
6067 return HAL_OK;
6068 }
6069 #endif /* HAL_DMA_MODULE_ENABLED */
6070
6071 /**
6072 * @brief Master sends target device address followed by internal memory address for write request.
6073 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6074 * the configuration information for the specified I2C.
6075 * @param DevAddress Target device address: The device 7 bits address value
6076 * in datasheet must be shifted to the left before calling the interface
6077 * @param MemAddress Internal memory address
6078 * @param MemAddSize Size of internal memory address
6079 * @param Timeout Timeout duration
6080 * @param Tickstart Tick start value
6081 * @retval HAL status
6082 */
I2C_RequestMemoryWrite(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)6083 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
6084 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
6085 uint32_t Tickstart)
6086 {
6087 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
6088
6089 /* Wait until TXIS flag is set */
6090 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6091 {
6092 return HAL_ERROR;
6093 }
6094
6095 /* If Memory address size is 8Bit */
6096 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
6097 {
6098 /* Send Memory Address */
6099 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
6100 }
6101 /* If Memory address size is 16Bit */
6102 else
6103 {
6104 /* Send MSB of Memory Address */
6105 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
6106
6107 /* Wait until TXIS flag is set */
6108 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6109 {
6110 return HAL_ERROR;
6111 }
6112
6113 /* Send LSB of Memory Address */
6114 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
6115 }
6116
6117 /* Wait until TCR flag is set */
6118 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
6119 {
6120 return HAL_ERROR;
6121 }
6122
6123 return HAL_OK;
6124 }
6125
6126 /**
6127 * @brief Master sends target device address followed by internal memory address for read request.
6128 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6129 * the configuration information for the specified I2C.
6130 * @param DevAddress Target device address: The device 7 bits address value
6131 * in datasheet must be shifted to the left before calling the interface
6132 * @param MemAddress Internal memory address
6133 * @param MemAddSize Size of internal memory address
6134 * @param Timeout Timeout duration
6135 * @param Tickstart Tick start value
6136 * @retval HAL status
6137 */
I2C_RequestMemoryRead(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)6138 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
6139 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
6140 uint32_t Tickstart)
6141 {
6142 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
6143
6144 /* Wait until TXIS flag is set */
6145 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6146 {
6147 return HAL_ERROR;
6148 }
6149
6150 /* If Memory address size is 8Bit */
6151 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
6152 {
6153 /* Send Memory Address */
6154 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
6155 }
6156 /* If Memory address size is 16Bit */
6157 else
6158 {
6159 /* Send MSB of Memory Address */
6160 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
6161
6162 /* Wait until TXIS flag is set */
6163 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6164 {
6165 return HAL_ERROR;
6166 }
6167
6168 /* Send LSB of Memory Address */
6169 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
6170 }
6171
6172 /* Wait until TC flag is set */
6173 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
6174 {
6175 return HAL_ERROR;
6176 }
6177
6178 return HAL_OK;
6179 }
6180
6181 /**
6182 * @brief I2C Address complete process callback.
6183 * @param hi2c I2C handle.
6184 * @param ITFlags Interrupt flags to handle.
6185 * @retval None
6186 */
I2C_ITAddrCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6187 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6188 {
6189 uint8_t transferdirection;
6190 uint16_t slaveaddrcode;
6191 uint16_t ownadd1code;
6192 uint16_t ownadd2code;
6193
6194 /* Prevent unused argument(s) compilation warning */
6195 UNUSED(ITFlags);
6196
6197 /* In case of Listen state, need to inform upper layer of address match code event */
6198 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
6199 {
6200 transferdirection = I2C_GET_DIR(hi2c);
6201 slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
6202 ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);
6203 ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
6204
6205 /* If 10bits addressing mode is selected */
6206 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
6207 {
6208 if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
6209 {
6210 slaveaddrcode = ownadd1code;
6211 hi2c->AddrEventCount++;
6212 if (hi2c->AddrEventCount == 2U)
6213 {
6214 /* Reset Address Event counter */
6215 hi2c->AddrEventCount = 0U;
6216
6217 /* Clear ADDR flag */
6218 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
6219
6220 /* Process Unlocked */
6221 __HAL_UNLOCK(hi2c);
6222
6223 /* Call Slave Addr callback */
6224 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6225 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
6226 #else
6227 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
6228 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6229 }
6230 }
6231 else
6232 {
6233 slaveaddrcode = ownadd2code;
6234
6235 /* Disable ADDR Interrupts */
6236 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
6237
6238 /* Process Unlocked */
6239 __HAL_UNLOCK(hi2c);
6240
6241 /* Call Slave Addr callback */
6242 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6243 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
6244 #else
6245 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
6246 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6247 }
6248 }
6249 /* else 7 bits addressing mode is selected */
6250 else
6251 {
6252 /* Disable ADDR Interrupts */
6253 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
6254
6255 /* Process Unlocked */
6256 __HAL_UNLOCK(hi2c);
6257
6258 /* Call Slave Addr callback */
6259 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6260 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
6261 #else
6262 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
6263 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6264 }
6265 }
6266 /* Else clear address flag only */
6267 else
6268 {
6269 /* Clear ADDR flag */
6270 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
6271
6272 /* Process Unlocked */
6273 __HAL_UNLOCK(hi2c);
6274 }
6275 }
6276
6277 /**
6278 * @brief I2C Master sequential complete process.
6279 * @param hi2c I2C handle.
6280 * @retval None
6281 */
I2C_ITMasterSeqCplt(I2C_HandleTypeDef * hi2c)6282 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
6283 {
6284 /* Reset I2C handle mode */
6285 hi2c->Mode = HAL_I2C_MODE_NONE;
6286
6287 /* No Generate Stop, to permit restart mode */
6288 /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
6289 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
6290 {
6291 hi2c->State = HAL_I2C_STATE_READY;
6292 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
6293 hi2c->XferISR = NULL;
6294
6295 /* Disable Interrupts */
6296 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
6297
6298 /* Process Unlocked */
6299 __HAL_UNLOCK(hi2c);
6300
6301 /* Call the corresponding callback to inform upper layer of End of Transfer */
6302 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6303 hi2c->MasterTxCpltCallback(hi2c);
6304 #else
6305 HAL_I2C_MasterTxCpltCallback(hi2c);
6306 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6307 }
6308 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
6309 else
6310 {
6311 hi2c->State = HAL_I2C_STATE_READY;
6312 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
6313 hi2c->XferISR = NULL;
6314
6315 /* Disable Interrupts */
6316 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
6317
6318 /* Process Unlocked */
6319 __HAL_UNLOCK(hi2c);
6320
6321 /* Call the corresponding callback to inform upper layer of End of Transfer */
6322 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6323 hi2c->MasterRxCpltCallback(hi2c);
6324 #else
6325 HAL_I2C_MasterRxCpltCallback(hi2c);
6326 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6327 }
6328 }
6329
6330 /**
6331 * @brief I2C Slave sequential complete process.
6332 * @param hi2c I2C handle.
6333 * @retval None
6334 */
I2C_ITSlaveSeqCplt(I2C_HandleTypeDef * hi2c)6335 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
6336 {
6337 uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
6338
6339 /* Reset I2C handle mode */
6340 hi2c->Mode = HAL_I2C_MODE_NONE;
6341
6342 #if defined(HAL_DMA_MODULE_ENABLED)
6343 /* If a DMA is ongoing, Update handle size context */
6344 if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
6345 {
6346 /* Disable DMA Request */
6347 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6348 }
6349 else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
6350 {
6351 /* Disable DMA Request */
6352 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6353 }
6354 else
6355 {
6356 /* Do nothing */
6357 }
6358 #endif /* HAL_DMA_MODULE_ENABLED */
6359
6360 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
6361 {
6362 /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
6363 hi2c->State = HAL_I2C_STATE_LISTEN;
6364 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6365
6366 /* Disable Interrupts */
6367 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
6368
6369 /* Process Unlocked */
6370 __HAL_UNLOCK(hi2c);
6371
6372 /* Call the corresponding callback to inform upper layer of End of Transfer */
6373 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6374 hi2c->SlaveTxCpltCallback(hi2c);
6375 #else
6376 HAL_I2C_SlaveTxCpltCallback(hi2c);
6377 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6378 }
6379
6380 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
6381 {
6382 /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
6383 hi2c->State = HAL_I2C_STATE_LISTEN;
6384 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6385
6386 /* Disable Interrupts */
6387 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
6388
6389 /* Process Unlocked */
6390 __HAL_UNLOCK(hi2c);
6391
6392 /* Call the corresponding callback to inform upper layer of End of Transfer */
6393 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6394 hi2c->SlaveRxCpltCallback(hi2c);
6395 #else
6396 HAL_I2C_SlaveRxCpltCallback(hi2c);
6397 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6398 }
6399 else
6400 {
6401 /* Nothing to do */
6402 }
6403 }
6404
6405 /**
6406 * @brief I2C Master complete process.
6407 * @param hi2c I2C handle.
6408 * @param ITFlags Interrupt flags to handle.
6409 * @retval None
6410 */
I2C_ITMasterCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6411 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6412 {
6413 uint32_t tmperror;
6414 uint32_t tmpITFlags = ITFlags;
6415 __IO uint32_t tmpreg;
6416
6417 /* Clear STOP Flag */
6418 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6419
6420 /* Disable Interrupts and Store Previous state */
6421 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
6422 {
6423 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
6424 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
6425 }
6426 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6427 {
6428 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
6429 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
6430 }
6431 else
6432 {
6433 /* Do nothing */
6434 }
6435
6436 /* Clear Configuration Register 2 */
6437 I2C_RESET_CR2(hi2c);
6438
6439 /* Reset handle parameters */
6440 hi2c->XferISR = NULL;
6441 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6442
6443 if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
6444 {
6445 /* Clear NACK Flag */
6446 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6447
6448 /* Set acknowledge error code */
6449 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6450 }
6451
6452 /* Fetch Last receive data if any */
6453 if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
6454 {
6455 /* Read data from RXDR */
6456 tmpreg = (uint8_t)hi2c->Instance->RXDR;
6457 UNUSED(tmpreg);
6458 }
6459
6460 /* Flush TX register */
6461 I2C_Flush_TXDR(hi2c);
6462
6463 /* Store current volatile hi2c->ErrorCode, misra rule */
6464 tmperror = hi2c->ErrorCode;
6465
6466 /* Call the corresponding callback to inform upper layer of End of Transfer */
6467 if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
6468 {
6469 /* Call the corresponding callback to inform upper layer of End of Transfer */
6470 I2C_ITError(hi2c, hi2c->ErrorCode);
6471 }
6472 /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
6473 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
6474 {
6475 hi2c->State = HAL_I2C_STATE_READY;
6476 hi2c->PreviousState = I2C_STATE_NONE;
6477
6478 if (hi2c->Mode == HAL_I2C_MODE_MEM)
6479 {
6480 hi2c->Mode = HAL_I2C_MODE_NONE;
6481
6482 /* Process Unlocked */
6483 __HAL_UNLOCK(hi2c);
6484
6485 /* Call the corresponding callback to inform upper layer of End of Transfer */
6486 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6487 hi2c->MemTxCpltCallback(hi2c);
6488 #else
6489 HAL_I2C_MemTxCpltCallback(hi2c);
6490 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6491 }
6492 else
6493 {
6494 hi2c->Mode = HAL_I2C_MODE_NONE;
6495
6496 /* Process Unlocked */
6497 __HAL_UNLOCK(hi2c);
6498
6499 /* Call the corresponding callback to inform upper layer of End of Transfer */
6500 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6501 hi2c->MasterTxCpltCallback(hi2c);
6502 #else
6503 HAL_I2C_MasterTxCpltCallback(hi2c);
6504 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6505 }
6506 }
6507 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
6508 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6509 {
6510 hi2c->State = HAL_I2C_STATE_READY;
6511 hi2c->PreviousState = I2C_STATE_NONE;
6512
6513 if (hi2c->Mode == HAL_I2C_MODE_MEM)
6514 {
6515 hi2c->Mode = HAL_I2C_MODE_NONE;
6516
6517 /* Process Unlocked */
6518 __HAL_UNLOCK(hi2c);
6519
6520 /* Call the corresponding callback to inform upper layer of End of Transfer */
6521 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6522 hi2c->MemRxCpltCallback(hi2c);
6523 #else
6524 HAL_I2C_MemRxCpltCallback(hi2c);
6525 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6526 }
6527 else
6528 {
6529 hi2c->Mode = HAL_I2C_MODE_NONE;
6530
6531 /* Process Unlocked */
6532 __HAL_UNLOCK(hi2c);
6533
6534 /* Call the corresponding callback to inform upper layer of End of Transfer */
6535 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6536 hi2c->MasterRxCpltCallback(hi2c);
6537 #else
6538 HAL_I2C_MasterRxCpltCallback(hi2c);
6539 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6540 }
6541 }
6542 else
6543 {
6544 /* Nothing to do */
6545 }
6546 }
6547
6548 /**
6549 * @brief I2C Slave complete process.
6550 * @param hi2c I2C handle.
6551 * @param ITFlags Interrupt flags to handle.
6552 * @retval None
6553 */
I2C_ITSlaveCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6554 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6555 {
6556 uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
6557 uint32_t tmpITFlags = ITFlags;
6558 uint32_t tmpoptions = hi2c->XferOptions;
6559 HAL_I2C_StateTypeDef tmpstate = hi2c->State;
6560
6561 /* Clear STOP Flag */
6562 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6563
6564 /* Disable Interrupts and Store Previous state */
6565 if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
6566 {
6567 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
6568 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6569 }
6570 else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6571 {
6572 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
6573 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6574 }
6575 else if (tmpstate == HAL_I2C_STATE_LISTEN)
6576 {
6577 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
6578 hi2c->PreviousState = I2C_STATE_NONE;
6579 }
6580 else
6581 {
6582 /* Do nothing */
6583 }
6584
6585 /* Disable Address Acknowledge */
6586 hi2c->Instance->CR2 |= I2C_CR2_NACK;
6587
6588 /* Clear Configuration Register 2 */
6589 I2C_RESET_CR2(hi2c);
6590
6591 /* Flush TX register */
6592 I2C_Flush_TXDR(hi2c);
6593
6594 #if defined(HAL_DMA_MODULE_ENABLED)
6595 /* If a DMA is ongoing, Update handle size context */
6596 if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
6597 {
6598 /* Disable DMA Request */
6599 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6600
6601 if (hi2c->hdmatx != NULL)
6602 {
6603 hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
6604 }
6605 }
6606 else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
6607 {
6608 /* Disable DMA Request */
6609 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6610
6611 if (hi2c->hdmarx != NULL)
6612 {
6613 hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
6614 }
6615 }
6616 else
6617 {
6618 /* Do nothing */
6619 }
6620 #endif /* HAL_DMA_MODULE_ENABLED */
6621
6622 /* Store Last receive data if any */
6623 if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
6624 {
6625 /* Remove RXNE flag on temporary variable as read done */
6626 tmpITFlags &= ~I2C_FLAG_RXNE;
6627
6628 /* Read data from RXDR */
6629 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
6630
6631 /* Increment Buffer pointer */
6632 hi2c->pBuffPtr++;
6633
6634 if ((hi2c->XferSize > 0U))
6635 {
6636 hi2c->XferSize--;
6637 hi2c->XferCount--;
6638 }
6639 }
6640
6641 /* All data are not transferred, so set error code accordingly */
6642 if (hi2c->XferCount != 0U)
6643 {
6644 /* Set ErrorCode corresponding to a Non-Acknowledge */
6645 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6646 }
6647
6648 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
6649 (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET))
6650 {
6651 /* Check that I2C transfer finished */
6652 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
6653 /* Mean XferCount == 0*/
6654 /* So clear Flag NACKF only */
6655 if (hi2c->XferCount == 0U)
6656 {
6657 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
6658 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
6659 Warning[Pa134]: left and right operands are identical */
6660 {
6661 /* Call I2C Listen complete process */
6662 I2C_ITListenCplt(hi2c, tmpITFlags);
6663 }
6664 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
6665 {
6666 /* Clear NACK Flag */
6667 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6668
6669 /* Flush TX register */
6670 I2C_Flush_TXDR(hi2c);
6671
6672 /* Last Byte is Transmitted */
6673 /* Call I2C Slave Sequential complete process */
6674 I2C_ITSlaveSeqCplt(hi2c);
6675 }
6676 else
6677 {
6678 /* Clear NACK Flag */
6679 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6680 }
6681 }
6682 else
6683 {
6684 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
6685 /* Clear NACK Flag */
6686 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6687
6688 /* Set ErrorCode corresponding to a Non-Acknowledge */
6689 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6690
6691 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
6692 {
6693 /* Call the corresponding callback to inform upper layer of End of Transfer */
6694 I2C_ITError(hi2c, hi2c->ErrorCode);
6695 }
6696 }
6697 }
6698
6699 hi2c->Mode = HAL_I2C_MODE_NONE;
6700 hi2c->XferISR = NULL;
6701
6702 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
6703 {
6704 /* Call the corresponding callback to inform upper layer of End of Transfer */
6705 I2C_ITError(hi2c, hi2c->ErrorCode);
6706
6707 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6708 if (hi2c->State == HAL_I2C_STATE_LISTEN)
6709 {
6710 /* Call I2C Listen complete process */
6711 I2C_ITListenCplt(hi2c, tmpITFlags);
6712 }
6713 }
6714 else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
6715 {
6716 /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
6717 I2C_ITSlaveSeqCplt(hi2c);
6718
6719 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6720 hi2c->State = HAL_I2C_STATE_READY;
6721 hi2c->PreviousState = I2C_STATE_NONE;
6722
6723 /* Process Unlocked */
6724 __HAL_UNLOCK(hi2c);
6725
6726 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6727 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6728 hi2c->ListenCpltCallback(hi2c);
6729 #else
6730 HAL_I2C_ListenCpltCallback(hi2c);
6731 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6732 }
6733 /* Call the corresponding callback to inform upper layer of End of Transfer */
6734 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6735 {
6736 hi2c->State = HAL_I2C_STATE_READY;
6737 hi2c->PreviousState = I2C_STATE_NONE;
6738
6739 /* Process Unlocked */
6740 __HAL_UNLOCK(hi2c);
6741
6742 /* Call the corresponding callback to inform upper layer of End of Transfer */
6743 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6744 hi2c->SlaveRxCpltCallback(hi2c);
6745 #else
6746 HAL_I2C_SlaveRxCpltCallback(hi2c);
6747 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6748 }
6749 else
6750 {
6751 hi2c->State = HAL_I2C_STATE_READY;
6752 hi2c->PreviousState = I2C_STATE_NONE;
6753
6754 /* Process Unlocked */
6755 __HAL_UNLOCK(hi2c);
6756
6757 /* Call the corresponding callback to inform upper layer of End of Transfer */
6758 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6759 hi2c->SlaveTxCpltCallback(hi2c);
6760 #else
6761 HAL_I2C_SlaveTxCpltCallback(hi2c);
6762 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6763 }
6764 }
6765
6766 /**
6767 * @brief I2C Listen complete process.
6768 * @param hi2c I2C handle.
6769 * @param ITFlags Interrupt flags to handle.
6770 * @retval None
6771 */
I2C_ITListenCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6772 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6773 {
6774 /* Reset handle parameters */
6775 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6776 hi2c->PreviousState = I2C_STATE_NONE;
6777 hi2c->State = HAL_I2C_STATE_READY;
6778 hi2c->Mode = HAL_I2C_MODE_NONE;
6779 hi2c->XferISR = NULL;
6780
6781 /* Store Last receive data if any */
6782 if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
6783 {
6784 /* Read data from RXDR */
6785 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
6786
6787 /* Increment Buffer pointer */
6788 hi2c->pBuffPtr++;
6789
6790 if ((hi2c->XferSize > 0U))
6791 {
6792 hi2c->XferSize--;
6793 hi2c->XferCount--;
6794
6795 /* Set ErrorCode corresponding to a Non-Acknowledge */
6796 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6797 }
6798 }
6799
6800 /* Disable all Interrupts*/
6801 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6802
6803 /* Clear NACK Flag */
6804 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6805
6806 /* Process Unlocked */
6807 __HAL_UNLOCK(hi2c);
6808
6809 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6810 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6811 hi2c->ListenCpltCallback(hi2c);
6812 #else
6813 HAL_I2C_ListenCpltCallback(hi2c);
6814 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6815 }
6816
6817 /**
6818 * @brief I2C interrupts error process.
6819 * @param hi2c I2C handle.
6820 * @param ErrorCode Error code to handle.
6821 * @retval None
6822 */
I2C_ITError(I2C_HandleTypeDef * hi2c,uint32_t ErrorCode)6823 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
6824 {
6825 HAL_I2C_StateTypeDef tmpstate = hi2c->State;
6826
6827 #if defined(HAL_DMA_MODULE_ENABLED)
6828 uint32_t tmppreviousstate;
6829 #endif /* HAL_DMA_MODULE_ENABLED */
6830
6831 /* Reset handle parameters */
6832 hi2c->Mode = HAL_I2C_MODE_NONE;
6833 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6834 hi2c->XferCount = 0U;
6835
6836 /* Set new error code */
6837 hi2c->ErrorCode |= ErrorCode;
6838
6839 /* Disable Interrupts */
6840 if ((tmpstate == HAL_I2C_STATE_LISTEN) ||
6841 (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
6842 (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6843 {
6844 /* Disable all interrupts, except interrupts related to LISTEN state */
6845 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6846
6847 /* keep HAL_I2C_STATE_LISTEN if set */
6848 hi2c->State = HAL_I2C_STATE_LISTEN;
6849 hi2c->XferISR = I2C_Slave_ISR_IT;
6850 }
6851 else
6852 {
6853 /* Disable all interrupts */
6854 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6855
6856 /* Flush TX register */
6857 I2C_Flush_TXDR(hi2c);
6858
6859 /* If state is an abort treatment on going, don't change state */
6860 /* This change will be do later */
6861 if (hi2c->State != HAL_I2C_STATE_ABORT)
6862 {
6863 /* Set HAL_I2C_STATE_READY */
6864 hi2c->State = HAL_I2C_STATE_READY;
6865
6866 /* Check if a STOPF is detected */
6867 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
6868 {
6869 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
6870 {
6871 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6872 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6873 }
6874
6875 /* Clear STOP Flag */
6876 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6877 }
6878
6879 }
6880 hi2c->XferISR = NULL;
6881 }
6882
6883 #if defined(HAL_DMA_MODULE_ENABLED)
6884 /* Abort DMA TX transfer if any */
6885 tmppreviousstate = hi2c->PreviousState;
6886
6887 if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
6888 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
6889 {
6890 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
6891 {
6892 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6893 }
6894
6895 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
6896 {
6897 /* Set the I2C DMA Abort callback :
6898 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6899 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
6900
6901 /* Process Unlocked */
6902 __HAL_UNLOCK(hi2c);
6903
6904 /* Abort DMA TX */
6905 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
6906 {
6907 /* Call Directly XferAbortCallback function in case of error */
6908 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
6909 }
6910 }
6911 else
6912 {
6913 I2C_TreatErrorCallback(hi2c);
6914 }
6915 }
6916 /* Abort DMA RX transfer if any */
6917 else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
6918 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
6919 {
6920 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
6921 {
6922 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6923 }
6924
6925 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
6926 {
6927 /* Set the I2C DMA Abort callback :
6928 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6929 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
6930
6931 /* Process Unlocked */
6932 __HAL_UNLOCK(hi2c);
6933
6934 /* Abort DMA RX */
6935 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
6936 {
6937 /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
6938 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
6939 }
6940 }
6941 else
6942 {
6943 I2C_TreatErrorCallback(hi2c);
6944 }
6945 }
6946 else
6947 #endif /* HAL_DMA_MODULE_ENABLED */
6948 {
6949 I2C_TreatErrorCallback(hi2c);
6950 }
6951 }
6952
6953 /**
6954 * @brief I2C Error callback treatment.
6955 * @param hi2c I2C handle.
6956 * @retval None
6957 */
I2C_TreatErrorCallback(I2C_HandleTypeDef * hi2c)6958 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
6959 {
6960 if (hi2c->State == HAL_I2C_STATE_ABORT)
6961 {
6962 hi2c->State = HAL_I2C_STATE_READY;
6963 hi2c->PreviousState = I2C_STATE_NONE;
6964
6965 /* Process Unlocked */
6966 __HAL_UNLOCK(hi2c);
6967
6968 /* Call the corresponding callback to inform upper layer of End of Transfer */
6969 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6970 hi2c->AbortCpltCallback(hi2c);
6971 #else
6972 HAL_I2C_AbortCpltCallback(hi2c);
6973 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6974 }
6975 else
6976 {
6977 hi2c->PreviousState = I2C_STATE_NONE;
6978
6979 /* Process Unlocked */
6980 __HAL_UNLOCK(hi2c);
6981
6982 /* Call the corresponding callback to inform upper layer of End of Transfer */
6983 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6984 hi2c->ErrorCallback(hi2c);
6985 #else
6986 HAL_I2C_ErrorCallback(hi2c);
6987 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6988 }
6989 }
6990
6991 /**
6992 * @brief I2C Tx data register flush process.
6993 * @param hi2c I2C handle.
6994 * @retval None
6995 */
I2C_Flush_TXDR(I2C_HandleTypeDef * hi2c)6996 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
6997 {
6998 /* If a pending TXIS flag is set */
6999 /* Write a dummy data in TXDR to clear it */
7000 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
7001 {
7002 hi2c->Instance->TXDR = 0x00U;
7003 }
7004
7005 /* Flush TX register if not empty */
7006 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
7007 {
7008 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
7009 }
7010 }
7011
7012 #if defined(HAL_DMA_MODULE_ENABLED)
7013 /**
7014 * @brief DMA I2C master transmit process complete callback.
7015 * @param hdma DMA handle
7016 * @retval None
7017 */
I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef * hdma)7018 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
7019 {
7020 HAL_StatusTypeDef dmaxferstatus = HAL_OK;
7021 /* Derogation MISRAC2012-Rule-11.5 */
7022 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
7023
7024 /* Disable DMA Request */
7025 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
7026
7027 /* If last transfer, enable STOP interrupt */
7028 if (hi2c->XferCount == 0U)
7029 {
7030 /* Enable STOP interrupt */
7031 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
7032 }
7033 /* else prepare a new DMA transfer and enable TCReload interrupt */
7034 else
7035 {
7036 /* Update Buffer pointer */
7037 hi2c->pBuffPtr += hi2c->XferSize;
7038
7039 /* Set the XferSize to transfer */
7040 if (hi2c->XferCount > MAX_NBYTE_SIZE)
7041 {
7042 hi2c->XferSize = MAX_NBYTE_SIZE;
7043 }
7044 else
7045 {
7046 hi2c->XferSize = hi2c->XferCount;
7047 }
7048
7049 /* Enable the DMA channel */
7050 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
7051 {
7052 if (hi2c->hdmatx->LinkedListQueue != NULL)
7053 {
7054 /* Set DMA data size */
7055 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
7056
7057 /* Set DMA source address */
7058 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr;
7059
7060 /* Set DMA destination address */
7061 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hi2c->Instance->TXDR;
7062
7063 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
7064 }
7065 else
7066 {
7067 /* Call the corresponding callback to inform upper layer of End of Transfer */
7068 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
7069 }
7070 }
7071 else
7072 {
7073 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
7074 hi2c->XferSize);
7075 }
7076
7077 if (dmaxferstatus != HAL_OK)
7078 {
7079 /* Call the corresponding callback to inform upper layer of End of Transfer */
7080 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
7081 }
7082 else
7083 {
7084 /* Enable TC interrupts */
7085 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
7086 }
7087 }
7088 }
7089
7090
7091 /**
7092 * @brief DMA I2C slave transmit process complete callback.
7093 * @param hdma DMA handle
7094 * @retval None
7095 */
I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef * hdma)7096 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
7097 {
7098 /* Derogation MISRAC2012-Rule-11.5 */
7099 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
7100 uint32_t tmpoptions = hi2c->XferOptions;
7101
7102 if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
7103 {
7104 /* Disable DMA Request */
7105 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
7106
7107 /* Last Byte is Transmitted */
7108 /* Call I2C Slave Sequential complete process */
7109 I2C_ITSlaveSeqCplt(hi2c);
7110 }
7111 else
7112 {
7113 /* No specific action, Master fully manage the generation of STOP condition */
7114 /* Mean that this generation can arrive at any time, at the end or during DMA process */
7115 /* So STOP condition should be manage through Interrupt treatment */
7116 }
7117 }
7118
7119
7120 /**
7121 * @brief DMA I2C master receive process complete callback.
7122 * @param hdma DMA handle
7123 * @retval None
7124 */
I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef * hdma)7125 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
7126 {
7127 HAL_StatusTypeDef dmaxferstatus = HAL_OK;
7128 /* Derogation MISRAC2012-Rule-11.5 */
7129 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
7130
7131 /* Disable DMA Request */
7132 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
7133
7134 /* If last transfer, enable STOP interrupt */
7135 if (hi2c->XferCount == 0U)
7136 {
7137 /* Enable STOP interrupt */
7138 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
7139 }
7140 /* else prepare a new DMA transfer and enable TCReload interrupt */
7141 else
7142 {
7143 /* Update Buffer pointer */
7144 hi2c->pBuffPtr += hi2c->XferSize;
7145
7146 /* Set the XferSize to transfer */
7147 if (hi2c->XferCount > MAX_NBYTE_SIZE)
7148 {
7149 hi2c->XferSize = MAX_NBYTE_SIZE;
7150 }
7151 else
7152 {
7153 hi2c->XferSize = hi2c->XferCount;
7154 }
7155
7156 /* Enable the DMA channel */
7157 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
7158 {
7159 if (hi2c->hdmarx->LinkedListQueue != NULL)
7160 {
7161 /* Set DMA data size */
7162 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
7163
7164 /* Set DMA source address */
7165 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hi2c->Instance->RXDR;
7166
7167 /* Set DMA destination address */
7168 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr;
7169
7170 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
7171 }
7172 else
7173 {
7174 /* Call the corresponding callback to inform upper layer of End of Transfer */
7175 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
7176 }
7177 }
7178 else
7179 {
7180 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
7181 hi2c->XferSize);
7182 }
7183
7184 if (dmaxferstatus != HAL_OK)
7185 {
7186 /* Call the corresponding callback to inform upper layer of End of Transfer */
7187 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
7188 }
7189 else
7190 {
7191 /* Enable TC interrupts */
7192 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
7193 }
7194 }
7195 }
7196
7197
7198 /**
7199 * @brief DMA I2C slave receive process complete callback.
7200 * @param hdma DMA handle
7201 * @retval None
7202 */
I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef * hdma)7203 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
7204 {
7205 /* Derogation MISRAC2012-Rule-11.5 */
7206 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
7207 uint32_t tmpoptions = hi2c->XferOptions;
7208
7209 if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \
7210 (tmpoptions != I2C_NO_OPTION_FRAME))
7211 {
7212 /* Disable DMA Request */
7213 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
7214
7215 /* Call I2C Slave Sequential complete process */
7216 I2C_ITSlaveSeqCplt(hi2c);
7217 }
7218 else
7219 {
7220 /* No specific action, Master fully manage the generation of STOP condition */
7221 /* Mean that this generation can arrive at any time, at the end or during DMA process */
7222 /* So STOP condition should be manage through Interrupt treatment */
7223 }
7224 }
7225
7226
7227 /**
7228 * @brief DMA I2C communication error callback.
7229 * @param hdma DMA handle
7230 * @retval None
7231 */
I2C_DMAError(DMA_HandleTypeDef * hdma)7232 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
7233 {
7234 /* Derogation MISRAC2012-Rule-11.5 */
7235 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
7236
7237 /* Disable Acknowledge */
7238 hi2c->Instance->CR2 |= I2C_CR2_NACK;
7239
7240 /* Call the corresponding callback to inform upper layer of End of Transfer */
7241 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
7242 }
7243
7244
7245 /**
7246 * @brief DMA I2C communication abort callback
7247 * (To be called at end of DMA Abort procedure).
7248 * @param hdma DMA handle.
7249 * @retval None
7250 */
I2C_DMAAbort(DMA_HandleTypeDef * hdma)7251 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
7252 {
7253 /* Derogation MISRAC2012-Rule-11.5 */
7254 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
7255
7256 /* Reset AbortCpltCallback */
7257 if (hi2c->hdmatx != NULL)
7258 {
7259 hi2c->hdmatx->XferAbortCallback = NULL;
7260 }
7261 if (hi2c->hdmarx != NULL)
7262 {
7263 hi2c->hdmarx->XferAbortCallback = NULL;
7264 }
7265
7266 I2C_TreatErrorCallback(hi2c);
7267 }
7268
7269 #endif /* HAL_DMA_MODULE_ENABLED */
7270
7271 /**
7272 * @brief This function handles I2C Communication Timeout. It waits
7273 * until a flag is no longer in the specified status.
7274 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7275 * the configuration information for the specified I2C.
7276 * @param Flag Specifies the I2C flag to check.
7277 * @param Status The actual Flag status (SET or RESET).
7278 * @param Timeout Timeout duration
7279 * @param Tickstart Tick start value
7280 * @retval HAL status
7281 */
I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Flag,FlagStatus Status,uint32_t Timeout,uint32_t Tickstart)7282 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
7283 uint32_t Timeout, uint32_t Tickstart)
7284 {
7285 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
7286 {
7287 /* Check if an error is detected */
7288 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
7289 {
7290 return HAL_ERROR;
7291 }
7292
7293 /* Check for the Timeout */
7294 if (Timeout != HAL_MAX_DELAY)
7295 {
7296 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7297 {
7298 if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
7299 {
7300 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7301 hi2c->State = HAL_I2C_STATE_READY;
7302 hi2c->Mode = HAL_I2C_MODE_NONE;
7303
7304 /* Process Unlocked */
7305 __HAL_UNLOCK(hi2c);
7306 return HAL_ERROR;
7307 }
7308 }
7309 }
7310 }
7311 return HAL_OK;
7312 }
7313
7314 /**
7315 * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
7316 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7317 * the configuration information for the specified I2C.
7318 * @param Timeout Timeout duration
7319 * @param Tickstart Tick start value
7320 * @retval HAL status
7321 */
I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7322 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
7323 uint32_t Tickstart)
7324 {
7325 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
7326 {
7327 /* Check if an error is detected */
7328 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
7329 {
7330 return HAL_ERROR;
7331 }
7332
7333 /* Check for the Timeout */
7334 if (Timeout != HAL_MAX_DELAY)
7335 {
7336 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7337 {
7338 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET))
7339 {
7340 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7341 hi2c->State = HAL_I2C_STATE_READY;
7342 hi2c->Mode = HAL_I2C_MODE_NONE;
7343
7344 /* Process Unlocked */
7345 __HAL_UNLOCK(hi2c);
7346
7347 return HAL_ERROR;
7348 }
7349 }
7350 }
7351 }
7352 return HAL_OK;
7353 }
7354
7355 /**
7356 * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
7357 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7358 * the configuration information for the specified I2C.
7359 * @param Timeout Timeout duration
7360 * @param Tickstart Tick start value
7361 * @retval HAL status
7362 */
I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7363 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
7364 uint32_t Tickstart)
7365 {
7366 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
7367 {
7368 /* Check if an error is detected */
7369 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
7370 {
7371 return HAL_ERROR;
7372 }
7373
7374 /* Check for the Timeout */
7375 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7376 {
7377 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
7378 {
7379 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7380 hi2c->State = HAL_I2C_STATE_READY;
7381 hi2c->Mode = HAL_I2C_MODE_NONE;
7382
7383 /* Process Unlocked */
7384 __HAL_UNLOCK(hi2c);
7385
7386 return HAL_ERROR;
7387 }
7388 }
7389 }
7390 return HAL_OK;
7391 }
7392
7393 /**
7394 * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
7395 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7396 * the configuration information for the specified I2C.
7397 * @param Timeout Timeout duration
7398 * @param Tickstart Tick start value
7399 * @retval HAL status
7400 */
I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7401 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
7402 uint32_t Tickstart)
7403 {
7404 HAL_StatusTypeDef status = HAL_OK;
7405
7406 while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK))
7407 {
7408 /* Check if an error is detected */
7409 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
7410 {
7411 status = HAL_ERROR;
7412 }
7413
7414 /* Check if a STOPF is detected */
7415 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK))
7416 {
7417 /* Check if an RXNE is pending */
7418 /* Store Last receive data if any */
7419 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
7420 {
7421 /* Return HAL_OK */
7422 /* The Reading of data from RXDR will be done in caller function */
7423 status = HAL_OK;
7424 }
7425
7426 /* Check a no-acknowledge have been detected */
7427 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
7428 {
7429 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7430 hi2c->ErrorCode = HAL_I2C_ERROR_AF;
7431
7432 /* Clear STOP Flag */
7433 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
7434
7435 /* Clear Configuration Register 2 */
7436 I2C_RESET_CR2(hi2c);
7437
7438 hi2c->State = HAL_I2C_STATE_READY;
7439 hi2c->Mode = HAL_I2C_MODE_NONE;
7440
7441 /* Process Unlocked */
7442 __HAL_UNLOCK(hi2c);
7443
7444 status = HAL_ERROR;
7445 }
7446 else
7447 {
7448 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
7449 }
7450 }
7451
7452 /* Check for the Timeout */
7453 if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK))
7454 {
7455 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
7456 {
7457 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7458 hi2c->State = HAL_I2C_STATE_READY;
7459
7460 /* Process Unlocked */
7461 __HAL_UNLOCK(hi2c);
7462
7463 status = HAL_ERROR;
7464 }
7465 }
7466 }
7467 return status;
7468 }
7469
7470 /**
7471 * @brief This function handles errors detection during an I2C Communication.
7472 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7473 * the configuration information for the specified I2C.
7474 * @param Timeout Timeout duration
7475 * @param Tickstart Tick start value
7476 * @retval HAL status
7477 */
I2C_IsErrorOccurred(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7478 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7479 {
7480 HAL_StatusTypeDef status = HAL_OK;
7481 uint32_t itflag = hi2c->Instance->ISR;
7482 uint32_t error_code = 0;
7483 uint32_t tickstart = Tickstart;
7484 uint32_t tmp1;
7485 HAL_I2C_ModeTypeDef tmp2;
7486
7487 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
7488 {
7489 /* Clear NACKF Flag */
7490 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7491
7492 /* Wait until STOP Flag is set or timeout occurred */
7493 /* AutoEnd should be initiate after AF */
7494 while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
7495 {
7496 /* Check for the Timeout */
7497 if (Timeout != HAL_MAX_DELAY)
7498 {
7499 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7500 {
7501 tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
7502 tmp2 = hi2c->Mode;
7503
7504 /* In case of I2C still busy, try to regenerate a STOP manually */
7505 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
7506 (tmp1 != I2C_CR2_STOP) && \
7507 (tmp2 != HAL_I2C_MODE_SLAVE))
7508 {
7509 /* Generate Stop */
7510 hi2c->Instance->CR2 |= I2C_CR2_STOP;
7511
7512 /* Update Tick with new reference */
7513 tickstart = HAL_GetTick();
7514 }
7515
7516 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
7517 {
7518 /* Check for the Timeout */
7519 if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
7520 {
7521 error_code |= HAL_I2C_ERROR_TIMEOUT;
7522
7523 status = HAL_ERROR;
7524
7525 break;
7526 }
7527 }
7528 }
7529 }
7530 }
7531
7532 /* In case STOP Flag is detected, clear it */
7533 if (status == HAL_OK)
7534 {
7535 /* Clear STOP Flag */
7536 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
7537 }
7538
7539 error_code |= HAL_I2C_ERROR_AF;
7540
7541 status = HAL_ERROR;
7542 }
7543
7544 /* Refresh Content of Status register */
7545 itflag = hi2c->Instance->ISR;
7546
7547 /* Then verify if an additional errors occurs */
7548 /* Check if a Bus error occurred */
7549 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
7550 {
7551 error_code |= HAL_I2C_ERROR_BERR;
7552
7553 /* Clear BERR flag */
7554 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
7555
7556 status = HAL_ERROR;
7557 }
7558
7559 /* Check if an Over-Run/Under-Run error occurred */
7560 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
7561 {
7562 error_code |= HAL_I2C_ERROR_OVR;
7563
7564 /* Clear OVR flag */
7565 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
7566
7567 status = HAL_ERROR;
7568 }
7569
7570 /* Check if an Arbitration Loss error occurred */
7571 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
7572 {
7573 error_code |= HAL_I2C_ERROR_ARLO;
7574
7575 /* Clear ARLO flag */
7576 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
7577
7578 status = HAL_ERROR;
7579 }
7580
7581 if (status != HAL_OK)
7582 {
7583 /* Flush TX register */
7584 I2C_Flush_TXDR(hi2c);
7585
7586 /* Clear Configuration Register 2 */
7587 I2C_RESET_CR2(hi2c);
7588
7589 hi2c->ErrorCode |= error_code;
7590 hi2c->State = HAL_I2C_STATE_READY;
7591 hi2c->Mode = HAL_I2C_MODE_NONE;
7592
7593 /* Process Unlocked */
7594 __HAL_UNLOCK(hi2c);
7595 }
7596
7597 return status;
7598 }
7599
7600 /**
7601 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
7602 * @param hi2c I2C handle.
7603 * @param DevAddress Specifies the slave address to be programmed.
7604 * @param Size Specifies the number of bytes to be programmed.
7605 * This parameter must be a value between 0 and 255.
7606 * @param Mode New state of the I2C START condition generation.
7607 * This parameter can be one of the following values:
7608 * @arg @ref I2C_RELOAD_MODE Enable Reload mode .
7609 * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
7610 * @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
7611 * @param Request New state of the I2C START condition generation.
7612 * This parameter can be one of the following values:
7613 * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
7614 * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
7615 * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
7616 * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
7617 * @retval None
7618 */
I2C_TransferConfig(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t Size,uint32_t Mode,uint32_t Request)7619 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
7620 uint32_t Request)
7621 {
7622 uint32_t tmp;
7623
7624 /* Check the parameters */
7625 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
7626 assert_param(IS_TRANSFER_MODE(Mode));
7627 assert_param(IS_TRANSFER_REQUEST(Request));
7628
7629 /* Declaration of tmp to prevent undefined behavior of volatile usage */
7630 tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
7631 (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
7632 (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
7633
7634 /* update CR2 register */
7635 MODIFY_REG(hi2c->Instance->CR2, \
7636 ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
7637 (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
7638 I2C_CR2_START | I2C_CR2_STOP)), tmp);
7639 }
7640
7641 /**
7642 * @brief Manage the enabling of Interrupts.
7643 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7644 * the configuration information for the specified I2C.
7645 * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
7646 * @retval None
7647 */
I2C_Enable_IRQ(I2C_HandleTypeDef * hi2c,uint16_t InterruptRequest)7648 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
7649 {
7650 uint32_t tmpisr = 0U;
7651
7652 #if defined(HAL_DMA_MODULE_ENABLED)
7653 if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \
7654 (hi2c->XferISR != I2C_Slave_ISR_DMA) && \
7655 (hi2c->XferISR != I2C_Mem_ISR_DMA))
7656 #endif /* HAL_DMA_MODULE_ENABLED */
7657 {
7658 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7659 {
7660 /* Enable ERR, STOP, NACK and ADDR interrupts */
7661 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7662 }
7663
7664 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7665 {
7666 /* Enable ERR, TC, STOP, NACK and TXI interrupts */
7667 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
7668 }
7669
7670 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7671 {
7672 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
7673 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
7674 }
7675
7676 if (InterruptRequest == I2C_XFER_ERROR_IT)
7677 {
7678 /* Enable ERR and NACK interrupts */
7679 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7680 }
7681
7682 if (InterruptRequest == I2C_XFER_CPLT_IT)
7683 {
7684 /* Enable STOP interrupts */
7685 tmpisr |= I2C_IT_STOPI;
7686 }
7687 }
7688
7689 #if defined(HAL_DMA_MODULE_ENABLED)
7690 else
7691 {
7692 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7693 {
7694 /* Enable ERR, STOP, NACK and ADDR interrupts */
7695 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7696 }
7697
7698 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7699 {
7700 /* Enable ERR, TC, STOP, NACK and TXI interrupts */
7701 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
7702 }
7703
7704 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7705 {
7706 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
7707 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
7708 }
7709
7710 if (InterruptRequest == I2C_XFER_ERROR_IT)
7711 {
7712 /* Enable ERR and NACK interrupts */
7713 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7714 }
7715
7716 if (InterruptRequest == I2C_XFER_CPLT_IT)
7717 {
7718 /* Enable STOP interrupts */
7719 tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
7720 }
7721
7722 if (InterruptRequest == I2C_XFER_RELOAD_IT)
7723 {
7724 /* Enable TC interrupts */
7725 tmpisr |= I2C_IT_TCI;
7726 }
7727 }
7728 #endif /* HAL_DMA_MODULE_ENABLED */
7729
7730 /* Enable interrupts only at the end */
7731 /* to avoid the risk of I2C interrupt handle execution before */
7732 /* all interrupts requested done */
7733 __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
7734 }
7735
7736 /**
7737 * @brief Manage the disabling of Interrupts.
7738 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7739 * the configuration information for the specified I2C.
7740 * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
7741 * @retval None
7742 */
I2C_Disable_IRQ(I2C_HandleTypeDef * hi2c,uint16_t InterruptRequest)7743 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
7744 {
7745 uint32_t tmpisr = 0U;
7746
7747 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7748 {
7749 /* Disable TC and TXI interrupts */
7750 tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
7751
7752 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
7753 {
7754 /* Disable NACK and STOP interrupts */
7755 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7756 }
7757 }
7758
7759 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7760 {
7761 /* Disable TC and RXI interrupts */
7762 tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
7763
7764 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
7765 {
7766 /* Disable NACK and STOP interrupts */
7767 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7768 }
7769 }
7770
7771 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7772 {
7773 /* Disable ADDR, NACK and STOP interrupts */
7774 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7775 }
7776
7777 if (InterruptRequest == I2C_XFER_ERROR_IT)
7778 {
7779 /* Enable ERR and NACK interrupts */
7780 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7781 }
7782
7783 if (InterruptRequest == I2C_XFER_CPLT_IT)
7784 {
7785 /* Enable STOP interrupts */
7786 tmpisr |= I2C_IT_STOPI;
7787 }
7788
7789 if (InterruptRequest == I2C_XFER_RELOAD_IT)
7790 {
7791 /* Enable TC interrupts */
7792 tmpisr |= I2C_IT_TCI;
7793 }
7794
7795 /* Disable interrupts only at the end */
7796 /* to avoid a breaking situation like at "t" time */
7797 /* all disable interrupts request are not done */
7798 __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
7799 }
7800
7801 /**
7802 * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
7803 * @param hi2c I2C handle.
7804 * @retval None
7805 */
I2C_ConvertOtherXferOptions(I2C_HandleTypeDef * hi2c)7806 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
7807 {
7808 /* if user set XferOptions to I2C_OTHER_FRAME */
7809 /* it request implicitly to generate a restart condition */
7810 /* set XferOptions to I2C_FIRST_FRAME */
7811 if (hi2c->XferOptions == I2C_OTHER_FRAME)
7812 {
7813 hi2c->XferOptions = I2C_FIRST_FRAME;
7814 }
7815 /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
7816 /* it request implicitly to generate a restart condition */
7817 /* then generate a stop condition at the end of transfer */
7818 /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */
7819 else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
7820 {
7821 hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
7822 }
7823 else
7824 {
7825 /* Nothing to do */
7826 }
7827 }
7828
7829 /**
7830 * @}
7831 */
7832
7833 #endif /* HAL_I2C_MODULE_ENABLED */
7834 /**
7835 * @}
7836 */
7837
7838 /**
7839 * @}
7840 */
7841
