1 /**
2 ******************************************************************************
3 * @file stm32h5xx_hal_gtzc.c
4 * @author MCD Application Team
5 * @brief GTZC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of GTZC peripheral:
8 * + TZSC Initialization and Configuration functions
9 * + TZSC-MPCWM Initialization and Configuration functions
10 * + MPCBB Initialization and Configuration functions
11 * + TZSC, TZSC-MPCWM and MPCBB Lock functions
12 * + TZIC Initialization and Configuration functions
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2023 STMicroelectronics.
18 * All rights reserved.
19 *
20 * This software is licensed under terms that can be found in the LICENSE file
21 * in the root directory of this software component.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
23 *
24 ******************************************************************************
25 @verbatim
26 ==============================================================================
27 ##### GTZC main features #####
28 ==============================================================================
29 [..]
30 (+) Global TrustZone Controller (GTZC) composed of three sub-blocks:
31 (++) TZSC: TrustZone security controller
32 This sub-block defines the secure/privileged state of master and slave
33 peripherals. It also controls the secure/privileged state of subregions
34 for the watermark memory peripheral controller (MPCWM).
35 (++) MPCBB: Block-Based memory protection controller
36 This sub-block defines the secure/privileged state of all blocks
37 (512-byte pages) of the associated SRAM.
38 (++) TZIC: TrustZone illegal access controller
39 This sub-block gathers all illegal access events in the system and
40 generates a secure interrupt towards NVIC.
41
42 (+) These sub-blocks are used to configure TrustZone system security in
43 a product having bus agents with programmable-security and privileged
44 attributes (securable) such as:
45 (++) on-chip RAM with programmable secure and/or privilege blocks (pages)
46 (++) AHB and APB peripherals with programmable security and/or privilege access
47 (++) AHB master granted as secure and/or privilege
48 (++) off-chip memories with secure and/or privilege areas
49
50 [..]
51 (+) TZIC accessible only with secure privileged transactions.
52 (+) Secure and non-secure access supported for privileged and unprivileged
53 part of TZSC and MPCBB
54 (+) Set of registers to define product security settings:
55 (++) Secure and privilege blocks for internal memories
56 (++) Secure and privilege regions for external memories
57 (++) Secure and privileged access mode for securable peripherals
58
59 ==============================================================================
60 ##### How to use this driver #####
61 ==============================================================================
62 [..]
63 The GTZC HAL driver can be used as follows:
64
65 (#) Configure or get back securable peripherals attributes using
66 HAL_GTZC_TZSC_ConfigPeriphAttributes() / HAL_GTZC_TZSC_GetConfigPeriphAttributes()
67
68 (#) Configure or get back MPCWM memories attributes using
69 HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes() / HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes()
70
71 (#) Lock TZSC sub-block or get lock status using HAL_GTZC_TZSC_Lock() /
72 HAL_GTZC_TZSC_GetLock()
73
74 (#) Configure or get back MPCBB memories complete configuration using
75 HAL_GTZC_MPCBB_ConfigMem() / HAL_GTZC_MPCBB_GetConfigMem()
76
77 (#) Configure or get back MPCBB memories attributes using
78 HAL_GTZC_MPCBB_ConfigMemAttributes() / HAL_GTZC_MPCBB_GetConfigMemAttributes()
79
80 (#) Lock MPCBB configuration or get lock status using HAL_GTZC_MPCBB_Lock() /
81 HAL_GTZC_MPCBB_GetLock()
82
83 (#) Lock MPCBB super-blocks or get lock status using HAL_GTZC_MPCBB_LockConfig() /
84 HAL_GTZC_MPCBB_GetLockConfig()
85
86 (#) Illegal access detection can be configured through TZIC sub-block using
87 following functions: HAL_GTZC_TZIC_DisableIT() / HAL_GTZC_TZIC_EnableIT()
88
89 (#) Illegal access flags can be retrieved through HAL_GTZC_TZIC_GetFlag() and
90 HAL_GTZC_TZIC_ClearFlag() functions
91
92 (#) Illegal access interrupt service routines are served by HAL_GTZC_IRQHandler()
93 and user can add his own code using HAL_GTZC_TZIC_Callback()
94
95 @endverbatim
96 ******************************************************************************
97 */
98
99 /* Includes ------------------------------------------------------------------*/
100 #include "stm32h5xx_hal.h"
101
102 /** @addtogroup STM32H5xx_HAL_Driver
103 * @{
104 */
105
106 /** @defgroup GTZC GTZC
107 * @brief GTZC HAL module driver
108 * @{
109 */
110
111 #ifdef HAL_GTZC_MODULE_ENABLED
112
113 /* Private typedef -----------------------------------------------------------*/
114 /* Private constants ---------------------------------------------------------*/
115
116 /** @defgroup GTZC_Private_Constants GTZC Private Constants
117 * @{
118 */
119
120 /* Definitions for GTZC_TZSC_MPCWM */
121 #if defined (OCTOSPI1)
122 #define GTZC_TZSC_MPCWM1_MEM_SIZE 0x10000000U /* 256MB max size */
123 #endif /* defined (OCTOSPI1) */
124 #if defined (FMC_BANK1)
125 #define GTZC_TZSC_MPCWM2_MEM_SIZE 0x10000000U /* 256MB max size */
126 #endif /* defined (FMC_BANK1) */
127 #if defined (FMC_BANK3) || defined(FMC_SDRAM_BANK_1)
128 #define GTZC_TZSC_MPCWM3_MEM_SIZE 0x10000000U /* 256MB max size */
129 #endif /* defined (FMC_BANK3) || defined(FMC_SDRAM_BANK_1) */
130 #if defined(BKPSRAM_BASE)
131 #define GTZC_TZSC_MPCWM4_MEM_SIZE BKPSRAM_SIZE
132 #endif /* defined (BKPSRAM_BASE) */
133 #if defined(FMC_SDRAM_BANK_2)
134 #define GTZC_TZSC_MPCWM4_SDRAM_MEM_SIZE 0x10000000U /* 256MB max size */
135 #endif /* defined(FMC_SDRAM_BANK_2) */
136
137 /* Definitions for GTZC TZSC & TZIC Crypto peripherals */
138 #if defined(STM32H573xx) || defined(STM32H533xx)
139 #define GTZC_CRYP_CFG3_MSK 0x00190000U
140 #define GTZC_CRYP_CFG4_MSK 0x00000010U
141 #else
142 #define GTZC_CRYP_CFG3_MSK 0U
143 #define GTZC_CRYP_CFG4_MSK 0U
144 #endif /* defined(STM32H573xx) || defined(STM32H533xx) */
145
146 /* Definitions for GTZC TZSC & TZIC ALL register values */
147 #if defined(STM32H573xx) || defined(STM32H563xx)
148 #define GTZC_CFGR1_MSK 0xFFFFFFFFU
149 #define GTZC_CFGR2_MSK 0xFF0FFF07U
150 #define GTZC_CFGR3_MSK (0x05E6FF03U | GTZC_CRYP_CFG3_MSK)
151 #define GTZC_CFGR4_MSK (0x3F1F0FDFU | GTZC_CRYP_CFG4_MSK)
152 #elif defined(STM32H533xx) || defined(STM32H523xx)
153 #define GTZC_CFGR1_MSK 0xC33FFE7FU
154 #define GTZC_CFGR2_MSK 0x16089F07U
155 #define GTZC_CFGR3_MSK (0x05A6F106U | GTZC_CRYP_CFG3_MSK)
156 #define GTZC_CFGR4_MSK (0x3F1F0FDFU | GTZC_CRYP_CFG4_MSK)
157 #elif defined(STM32H562xx)
158 #define GTZC_CFGR1_MSK 0xFFFFFFFFU
159 #define GTZC_CFGR2_MSK 0xFF0FFF05U
160 #define GTZC_CFGR3_MSK 0x05A6FF03U
161 #define GTZC_CFGR4_MSK 0x3F1F0FDFU
162 #elif defined(STM32H503xx)
163 #define GTZC_CFGR1_MSK 0xC21E7E33U
164 #define GTZC_CFGR2_MSK 0x12080B19U
165 #define GTZC_CFGR3_MSK 0x04065104U
166 #define GTZC_CFGR4_MSK 0x00000000U
167 #endif /* (STM32H533xx) || defined(STM32H523xx) */
168
169 #if defined (GTZC_TZIC1)
170 #define GTZC_SEC_PRIV_MSK (GTZC_TZSC_PERIPH_PRIV | GTZC_TZSC_PERIPH_SEC)
171 #else
172 #define GTZC_SEC_PRIV_MSK GTZC_TZSC_PERIPH_PRIV
173 #endif /* defined (GTZC_TZIC1) */
174 /**
175 * @}
176 */
177
178 /* Private macros ------------------------------------------------------------*/
179
180 /** @defgroup GTZC_Private_Macros GTZC Private Macros
181 * @{
182 */
183
184 #define IS_ADDRESS_IN(mem, address)\
185 ( ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \
186 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) \
187 || ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \
188 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) )
189
190 #define IS_ADDRESS_IN_S(mem, address)\
191 ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \
192 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) )
193
194 #define IS_ADDRESS_IN_NS(mem, address)\
195 ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \
196 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) )
197
198 #define GTZC_BASE_ADDRESS(mem)\
199 ( mem ## _BASE )
200
201 #if defined(GTZC_MPCBB_CR_INVSECSTATE_Pos)
202 #define MPCBB_PARAMETERS_CHECK() \
203 ((pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_ENABLE) \
204 && (pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_DISABLE)) \
205 || ((pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED) \
206 && (pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_INVERTED))
207 #else
208 #define MPCBB_PARAMETERS_CHECK() (0U == 1U)
209 #endif /* defined(GTZC_MPCBB_CR_INVSECSTATE_Pos) */
210 /**
211 * @}
212 */
213
214 /* Private variables ---------------------------------------------------------*/
215 /* Private function prototypes -----------------------------------------------*/
216 /* Exported functions --------------------------------------------------------*/
217
218 /** @defgroup GTZC_Exported_Functions GTZC Exported Functions
219 * @{
220 */
221
222 /** @defgroup GTZC_Exported_Functions_Group1 TZSC Configuration functions
223 * @brief TZSC Configuration functions
224 *
225 @verbatim
226 ==============================================================================
227 ##### TZSC Configuration functions #####
228 ==============================================================================
229 [..]
230 This section provides functions allowing to configure TZSC
231 TZSC: TrustZone Security Controller
232 @endverbatim
233 * @{
234 */
235
236 /**
237 * @brief Configure TZSC on a single peripheral or on all peripherals.
238 * @note Secure and non-secure attributes can only be set from the secure
239 * state when the system implements the security (TZEN=1).
240 * @note Privilege and non-privilege attributes can only be set from the
241 * privilege state when TZEN=0 or TZEN=1
242 * @note Security and privilege attributes can be set independently.
243 * @note Default state is non-secure and unprivileged access allowed.
244 * @param PeriphId Peripheral identifier
245 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
246 * Use GTZC_PERIPH_ALL to select all peripherals.
247 * @param PeriphAttributes Peripheral attributes, see @ref GTZC_TZSC_PeriphAttributes.
248 * @retval HAL status.
249 */
HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId,uint32_t PeriphAttributes)250 HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId,
251 uint32_t PeriphAttributes)
252 {
253 uint32_t register_address;
254
255 /* check entry parameters */
256 if (((PeriphAttributes & ~(GTZC_SEC_PRIV_MSK)) != 0U)
257 || (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER)
258 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
259 && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
260 {
261 return HAL_ERROR;
262 }
263
264 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
265 {
266 /* special case where same attributes are applied to all peripherals */
267
268 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
269 /* secure configuration */
270 if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC)
271 {
272 SET_BIT(GTZC_TZSC1->SECCFGR1, GTZC_CFGR1_MSK);
273 SET_BIT(GTZC_TZSC1->SECCFGR2, GTZC_CFGR2_MSK);
274 SET_BIT(GTZC_TZSC1->SECCFGR3, GTZC_CFGR3_MSK);
275 }
276 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NSEC) == GTZC_TZSC_PERIPH_NSEC)
277 {
278 CLEAR_BIT(GTZC_TZSC1->SECCFGR1, GTZC_CFGR1_MSK);
279 CLEAR_BIT(GTZC_TZSC1->SECCFGR2, GTZC_CFGR2_MSK);
280 CLEAR_BIT(GTZC_TZSC1->SECCFGR3, GTZC_CFGR3_MSK);
281 }
282 else
283 {
284 /* do nothing */
285 }
286 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
287
288 /* privilege configuration */
289 if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV)
290 {
291 SET_BIT(GTZC_TZSC1->PRIVCFGR1, GTZC_CFGR1_MSK);
292 SET_BIT(GTZC_TZSC1->PRIVCFGR2, GTZC_CFGR2_MSK);
293 SET_BIT(GTZC_TZSC1->PRIVCFGR3, GTZC_CFGR3_MSK);
294 }
295 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NPRIV) == GTZC_TZSC_PERIPH_NPRIV)
296 {
297 CLEAR_BIT(GTZC_TZSC1->PRIVCFGR1, GTZC_CFGR1_MSK);
298 CLEAR_BIT(GTZC_TZSC1->PRIVCFGR2, GTZC_CFGR2_MSK);
299 CLEAR_BIT(GTZC_TZSC1->PRIVCFGR3, GTZC_CFGR3_MSK);
300 }
301 else
302 {
303 /* do nothing */
304 }
305 }
306 else
307 {
308 /* common case where only one peripheral is configured */
309
310 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
311 /* secure configuration */
312 register_address = (uint32_t) &(GTZC_TZSC1->SECCFGR1)
313 + (4U * GTZC_GET_REG_INDEX(PeriphId));
314 if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC)
315 {
316 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
317 }
318 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NSEC) == GTZC_TZSC_PERIPH_NSEC)
319 {
320 CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
321 }
322 else
323 {
324 /* do nothing */
325 }
326 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
327
328 /* privilege configuration */
329 register_address = (uint32_t) &(GTZC_TZSC1->PRIVCFGR1)
330 + (4U * GTZC_GET_REG_INDEX(PeriphId));
331 if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV)
332 {
333 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
334 }
335 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NPRIV) == GTZC_TZSC_PERIPH_NPRIV)
336 {
337 CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
338 }
339 else
340 {
341 /* do nothing */
342 }
343 }
344 return HAL_OK;
345 }
346
347 /**
348 * @brief Get TZSC configuration on a single peripheral or on all peripherals.
349 * @param PeriphId Peripheral identifier.
350 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
351 * Use GTZC_PERIPH_ALL to select all peripherals.
352 * @param PeriphAttributes Peripheral attribute pointer.
353 * This parameter can be a value of @ref GTZC_TZSC_PeriphAttributes.
354 * If PeriphId target a single peripheral, pointer on a single element.
355 * If all peripherals selected (GTZC_PERIPH_ALL), pointer to an array of
356 * GTZC_TZSC_PERIPH_NUMBER elements is to be provided.
357 * @retval HAL status.
358 */
HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,uint32_t * PeriphAttributes)359 HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,
360 uint32_t *PeriphAttributes)
361 {
362 uint32_t i;
363 uint32_t reg_value;
364 uint32_t register_address;
365
366 /* check entry parameters */
367 if ((PeriphAttributes == NULL)
368 || (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER)
369 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
370 && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
371 {
372 return HAL_ERROR;
373 }
374
375 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
376 {
377 /* get privilege configuration: read each register and deploy each bit value
378 * of corresponding index in the destination array
379 */
380 reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR1);
381 for (i = 0U; i < 32U; i++)
382 {
383 if (((reg_value & (1UL << i)) >> i) != 0U)
384 {
385 PeriphAttributes[i] = GTZC_TZSC_PERIPH_PRIV;
386 }
387 else
388 {
389 PeriphAttributes[i] = GTZC_TZSC_PERIPH_NPRIV;
390 }
391 }
392
393 reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR2);
394 for (i = 32U; i < 64U; i++)
395 {
396 if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U)
397 {
398 PeriphAttributes[i] = GTZC_TZSC_PERIPH_PRIV;
399 }
400 else
401 {
402 PeriphAttributes[i] = GTZC_TZSC_PERIPH_NPRIV;
403 }
404 }
405
406 reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR3);
407 for (i = 64U; i < GTZC_TZSC_PERIPH_NUMBER; i++)
408 {
409 if (((reg_value & (1UL << (i - 64U))) >> (i - 64U)) != 0U)
410 {
411 PeriphAttributes[i] = GTZC_TZSC_PERIPH_PRIV;
412 }
413 else
414 {
415 PeriphAttributes[i] = GTZC_TZSC_PERIPH_NPRIV;
416 }
417 }
418 #if defined (GTZC_TZIC1)
419 /* get secure configuration: read each register and deploy each bit value
420 * of corresponding index in the destination array
421 */
422 reg_value = READ_REG(GTZC_TZSC1->SECCFGR1);
423 for (i = 0U; i < 32U; i++)
424 {
425 if (((reg_value & (1UL << i)) >> i) != 0U)
426 {
427 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_SEC;
428 }
429 else
430 {
431 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NSEC;
432 }
433 }
434
435 reg_value = READ_REG(GTZC_TZSC1->SECCFGR2);
436 for (i = 32U; i < 64U; i++)
437 {
438 if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U)
439 {
440 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_SEC;
441 }
442 else
443 {
444 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NSEC;
445 }
446 }
447
448 reg_value = READ_REG(GTZC_TZSC1->SECCFGR3);
449 for (i = 64U; i < GTZC_TZSC_PERIPH_NUMBER; i++)
450 {
451 if (((reg_value & (1UL << (i - 64U))) >> (i - 64U)) != 0U)
452 {
453 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_SEC;
454 }
455 else
456 {
457 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NSEC;
458 }
459 }
460
461 #endif /* defined (GTZC_TZIC1) */
462 }
463 else
464 {
465 /* privilege configuration */
466 register_address = (uint32_t) &(GTZC_TZSC1->PRIVCFGR1)
467 + (4U * GTZC_GET_REG_INDEX(PeriphId));
468
469 if (((READ_BIT(*(__IO uint32_t *)register_address,
470 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId))
471 != 0U)
472 {
473 *PeriphAttributes = GTZC_TZSC_PERIPH_PRIV;
474 }
475 else
476 {
477 *PeriphAttributes = GTZC_TZSC_PERIPH_NPRIV;
478 }
479
480 /* common case where only one peripheral is configured */
481 #if defined (GTZC_TZIC1)
482 /* secure configuration */
483 register_address = (uint32_t) &(GTZC_TZSC1->SECCFGR1)
484 + (4U * GTZC_GET_REG_INDEX(PeriphId));
485
486 if (((READ_BIT(*(__IO uint32_t *)register_address,
487 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId))
488 != 0U)
489 {
490 *PeriphAttributes |= GTZC_TZSC_PERIPH_SEC;
491 }
492 else
493 {
494 *PeriphAttributes |= GTZC_TZSC_PERIPH_NSEC;
495 }
496 #endif /* defined (GTZC_TZIC1) */
497 }
498 return HAL_OK;
499 }
500
501 /**
502 * @}
503 */
504
505
506 /** @defgroup GTZC_Exported_Functions_Group2 MPCWM Configuration functions
507 * @brief MPCWM Configuration functions
508 *
509 @verbatim
510 ==============================================================================
511 ##### MPCWM Configuration functions #####
512 ==============================================================================
513 [..]
514 This section provides functions allowing to configure MPCWM
515 MPCWM is Memory Protection Controller WaterMark
516 @endverbatim
517 * @{
518 */
519
520 /**
521 * @brief Configure a TZSC-MPCWM area.
522 * @param MemBaseAddress WM identifier.
523 * @param pMPCWM_Desc TZSC-MPCWM descriptor pointer.
524 * The structure description is available in @ref GTZC_Exported_Types.
525 * @retval HAL status.
526 */
HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress,const MPCWM_ConfigTypeDef * pMPCWM_Desc)527 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress,
528 const MPCWM_ConfigTypeDef *pMPCWM_Desc)
529 {
530 uint32_t register_address;
531 uint32_t reg_value;
532 uint32_t size;
533 /* granularity value depends on selected memory */
534 uint32_t granularity = (MemBaseAddress == BKPSRAM_BASE) ? \
535 GTZC_TZSC_MPCWM_GRANULARITY_2 : GTZC_TZSC_MPCWM_GRANULARITY_1;
536
537 /* check entry parameters */
538 if ((pMPCWM_Desc->AreaId > GTZC_TZSC_MPCWM_ID2)
539 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
540 || (((MemBaseAddress == FMC_BANK3) || (MemBaseAddress == BKPSRAM_BASE) || \
541 (MemBaseAddress == FMC_SDRAM_BANK_1) || (MemBaseAddress == FMC_SDRAM_BANK_2))
542 #else
543 || ((MemBaseAddress == BKPSRAM_BASE)
544 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
545 && (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2))
546 || ((pMPCWM_Desc->Offset % granularity) != 0U)
547 || ((pMPCWM_Desc->Length % granularity) != 0U))
548 {
549 return HAL_ERROR;
550 }
551
552 /* check descriptor content vs. memory capacity */
553 switch (MemBaseAddress)
554 {
555 #if defined(OCTOSPI1)
556 case OCTOSPI1_BASE:
557 size = GTZC_TZSC_MPCWM1_MEM_SIZE;
558 if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
559 {
560 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM1AR);
561 }
562 else
563 {
564 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
565 * (Parameter already checked)
566 */
567 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM1BR);
568 }
569 break;
570 #endif /* (OCTOSPI1) */
571 #if defined(FMC_BANK1)
572 case FMC_BANK1:
573 size = GTZC_TZSC_MPCWM2_MEM_SIZE;
574 if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
575 {
576 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM2AR);
577 }
578 else
579 {
580 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
581 * (Parameter already checked)
582 */
583 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM2BR);
584 }
585 break;
586 #endif /* defined(FMC_BANK1) */
587 #if defined(FMC_BANK3)
588 case FMC_BANK3:
589 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1
590 * (Parameter already checked)
591 */
592 size = GTZC_TZSC_MPCWM3_MEM_SIZE;
593 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM3AR);
594 break;
595 #endif /* defined(FMC_BANK3) */
596 #if defined(FMC_SDRAM_BANK_1)
597 case FMC_SDRAM_BANK_1:
598 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1
599 * (Parameter already checked)
600 */
601 size = GTZC_TZSC_MPCWM3_MEM_SIZE;
602 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM3BR);
603 break;
604 #endif /* (FMC_SDRAM_BANK_1) */
605 #if defined(BKPSRAM_BASE)
606 case BKPSRAM_BASE:
607 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1
608 * (Parameter already checked)
609 */
610 size = GTZC_TZSC_MPCWM4_MEM_SIZE;
611 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM4AR);
612 break;
613 #endif /* (BKPSRAM_BASE) */
614 #if defined(FMC_SDRAM_BANK_2)
615 case FMC_SDRAM_BANK_2:
616 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1
617 * (Parameter already checked)
618 */
619 size = GTZC_TZSC_MPCWM4_SDRAM_MEM_SIZE ;
620 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM4BR);
621 break;
622 #endif /* (FMC_SDRAM_BANK_2) */
623 default:
624 return HAL_ERROR;
625 break;
626 }
627
628 if ((pMPCWM_Desc->Offset > size)
629 || ((pMPCWM_Desc->Offset
630 + pMPCWM_Desc->Length)
631 > size))
632 {
633 return HAL_ERROR;
634 }
635
636 /* Write watermark start and length value */
637 reg_value = ((pMPCWM_Desc->Offset / granularity)
638 << GTZC_TZSC_MPCWMR_SUBZ_START_Pos) & GTZC_TZSC_MPCWMR_SUBZ_START_Msk;
639 reg_value |= ((pMPCWM_Desc->Length / granularity)
640 << GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) & GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk;
641 MODIFY_REG(*(__IO uint32_t *)register_address, GTZC_TZSC_MPCWMR_SUBZ_START_Msk | \
642 GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk, reg_value);
643
644 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
645 /* Write watermark configuration value */
646 reg_value = (pMPCWM_Desc->Attribute << GTZC_TZSC_MPCWM_CFGR_SEC_Pos) | \
647 pMPCWM_Desc->Lock | \
648 pMPCWM_Desc->AreaStatus;
649 MODIFY_REG(*(__IO uint32_t *)(register_address - 4U), (GTZC_TZSC_MPCWM_CFGR_PRIV | GTZC_TZSC_MPCWM_CFGR_SEC | \
650 GTZC_TZSC_MPCWM_CFGR_SRLOCK | GTZC_TZSC_MPCWM_CFGR_SREN), \
651 reg_value);
652 #else
653 /* Write watermark configuration value */
654 reg_value = (pMPCWM_Desc->Attribute << (GTZC_TZSC_MPCWM_CFGR_PRIV_Pos - 1U)) | \
655 pMPCWM_Desc->Lock | \
656 pMPCWM_Desc->AreaStatus;
657 MODIFY_REG(*(__IO uint32_t *)(register_address - 4U), (GTZC_TZSC_MPCWM_CFGR_PRIV | GTZC_TZSC_MPCWM_CFGR_SRLOCK | \
658 GTZC_TZSC_MPCWM_CFGR_SREN), reg_value);
659 #endif /* (__ARM_FEATURE_CMSE) */
660
661 return HAL_OK;
662 }
663
664 /**
665 * @brief Get a TZSC-MPCWM area configuration.
666 * @param MemBaseAddress WM identifier.
667 * @param pMPCWM_Desc pointer to a TZSC-MPCWM descriptor.
668 * When the WaterMark memory supports two sub-regions A and B. pMPCWM_Desc argument must point to an array of
669 * two MPCWM_ConfigTypeDef structures.
670 * The structure description is available in @ref GTZC_Exported_Types.
671 * @retval HAL status.
672 */
HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress,MPCWM_ConfigTypeDef * pMPCWM_Desc)673 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress, MPCWM_ConfigTypeDef *pMPCWM_Desc)
674 {
675 uint32_t register_address;
676 uint32_t reg_value;
677 uint32_t granularity = (MemBaseAddress == BKPSRAM_BASE) ? \
678 GTZC_TZSC_MPCWM_GRANULARITY_2 : GTZC_TZSC_MPCWM_GRANULARITY_1;
679
680 /* firstly take care of the first area, present on all MPCWM sub-blocks */
681 switch (MemBaseAddress)
682 {
683 #if defined(OCTOSPI1)
684 case OCTOSPI1_BASE:
685 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM1AR);
686 break;
687 #endif /* (OCTOSPI1) */
688 #if defined(FMC_BANK1)
689 case FMC_BANK1:
690 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM2AR);
691 break;
692 #endif /* defined(FMC_BANK1) */
693 #if defined(FMC_BANK3)
694 case FMC_BANK3:
695 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM3AR);
696 break;
697 #endif /* defined(FMC_BANK3) */
698 #if defined(FMC_SDRAM_BANK_1)
699 case FMC_SDRAM_BANK_1:
700 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM3BR);
701 break;
702 #endif /* (FMC_SDRAM_BANK_1) */
703 #if defined(BKPSRAM_BASE)
704 case BKPSRAM_BASE:
705 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM4AR);
706 break;
707 #endif /* (BKPSRAM_BASE) */
708 #if defined(FMC_SDRAM_BANK_2)
709 case FMC_SDRAM_BANK_2:
710 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM4BR);
711 break;
712 #endif /* (FMC_SDRAM_BANK_2) */
713 default:
714 return HAL_ERROR;
715 break;
716 }
717
718 /* read register and update the descriptor for first area*/
719 reg_value = READ_REG(*(__IO uint32_t *)register_address);
720 pMPCWM_Desc[0].AreaId = GTZC_TZSC_MPCWM_ID1;
721 pMPCWM_Desc[0].Offset = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_START_Msk)
722 >> GTZC_TZSC_MPCWMR_SUBZ_START_Pos) * granularity;
723 pMPCWM_Desc[0].Length = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk)
724 >> GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) * granularity;
725
726 /* read configuration register and update the descriptor for first area*/
727 reg_value = READ_REG(*(__IO uint32_t *)(register_address - 4U));
728 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
729 pMPCWM_Desc[0].Attribute = (reg_value & (GTZC_TZSC_MPCWM_CFGR_PRIV | \
730 GTZC_TZSC_MPCWM_CFGR_SEC)) >> GTZC_TZSC_MPCWM_CFGR_SEC_Pos;
731 #else
732 pMPCWM_Desc[0].Attribute = (reg_value & GTZC_TZSC_MPCWM_CFGR_PRIV) >> (GTZC_TZSC_MPCWM_CFGR_PRIV_Pos - 1U);
733 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
734 pMPCWM_Desc[0].Lock = reg_value & GTZC_TZSC_MPCWM_CFGR_SRLOCK;
735 pMPCWM_Desc[0].AreaStatus = reg_value & GTZC_TZSC_MPCWM_CFGR_SREN;
736
737 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
738 if ((MemBaseAddress == OCTOSPI1_BASE) || (MemBaseAddress == FMC_BANK1))
739 {
740 if (MemBaseAddress == OCTOSPI1_BASE)
741 {
742 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1BR);
743 }
744 else
745 {
746 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2BR);
747 }
748
749 /* read register and update the descriptor for second area*/
750 reg_value = READ_REG(*(__IO uint32_t *)register_address);
751 pMPCWM_Desc[1].AreaId = GTZC_TZSC_MPCWM_ID2;
752 pMPCWM_Desc[1].Offset = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_START_Msk)
753 >> GTZC_TZSC_MPCWMR_SUBZ_START_Pos) * granularity;
754 pMPCWM_Desc[1].Length = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk)
755 >> GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) * granularity;
756
757 /* read configuration register and update the descriptor for second area*/
758 reg_value = READ_REG(*(__IO uint32_t *)(register_address - 4U));
759 pMPCWM_Desc[1].Attribute = (reg_value & (GTZC_TZSC_MPCWM_CFGR_PRIV | \
760 GTZC_TZSC_MPCWM_CFGR_SEC)) >> GTZC_TZSC_MPCWM_CFGR_SEC_Pos;
761 pMPCWM_Desc[1].Lock = reg_value & GTZC_TZSC_MPCWM_CFGR_SRLOCK;
762 pMPCWM_Desc[1].AreaStatus = reg_value & GTZC_TZSC_MPCWM_CFGR_SREN;
763 }
764 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
765
766 return HAL_OK;
767 }
768
769 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
770 /**
771 * @}
772 */
773
774 /** @defgroup GTZC_Exported_Functions_Group3 TZSC Lock functions
775 * @brief TZSC Lock functions
776 *
777 @verbatim
778 ==============================================================================
779 ##### TZSC Lock functions #####
780 ==============================================================================
781 [..]
782 This section provides functions allowing to manage the TZSC (TrustZone
783 Security Controller) lock. It includes lock enable, and current value read.
784 @endverbatim
785 * @{
786 */
787
788 /**
789 * @brief Lock TZSC configuration.
790 * @note This function locks the configuration of TZSC_SECCFGRx and TZSC_PRIVCFGRx
791 * registers until next reset
792 * @param TZSC_Instance TZSC sub-block instance.
793 */
HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef * TZSC_Instance)794 void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance)
795 {
796 SET_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk);
797 }
798
799 /**
800 * @brief Get TZSC configuration lock state.
801 * @param TZSC_Instance TZSC sub-block instance.
802 * @retval Lock State (GTZC_TZSC_LOCK_OFF or GTZC_TZSC_LOCK_ON)
803 */
HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef * TZSC_Instance)804 uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSC_Instance)
805 {
806 return READ_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk);
807 }
808
809 /**
810 * @}
811 */
812 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
813
814 /** @defgroup GTZC_Exported_Functions_Group4 MPCBB Configuration functions
815 * @brief MPCBB Configuration functions
816 *
817 @verbatim
818 ==============================================================================
819 ##### MPCBB Configuration functions #####
820 ==============================================================================
821 [..]
822 This section provides functions allowing to configure MPCBB
823 MPCBB is Memory Protection Controller Block Base
824 @endverbatim
825 * @{
826 */
827
828 /**
829 * @brief Set a complete MPCBB configuration on the SRAM passed as parameter.
830 * @param MemBaseAddress MPCBB identifier.
831 * @param pMPCBB_desc pointer to MPCBB descriptor.
832 * The structure description is available in @ref GTZC_Exported_Types.
833 * @retval HAL status.
834 */
HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress,const MPCBB_ConfigTypeDef * pMPCBB_desc)835 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress,
836 const MPCBB_ConfigTypeDef *pMPCBB_desc)
837 {
838 GTZC_MPCBB_TypeDef *mpcbb_ptr;
839 uint32_t mem_size;
840 uint32_t size_in_superblocks;
841 uint32_t i;
842
843 #if defined (GTZC_MPCBB3)
844 /* check entry parameters */
845 if ((!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
846 && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
847 && !(IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)))
848 || MPCBB_PARAMETERS_CHECK())
849 #else
850 if ((!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
851 && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)))
852 || MPCBB_PARAMETERS_CHECK())
853 #endif /* defined (GTZC_MPCBB3) */
854 {
855 return HAL_ERROR;
856 }
857
858 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
859 {
860 mpcbb_ptr = GTZC_MPCBB1;
861 mem_size = GTZC_MEM_SIZE(SRAM1);
862 }
863 #if defined (GTZC_MPCBB3)
864 else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
865 {
866 mpcbb_ptr = GTZC_MPCBB2;
867 mem_size = GTZC_MEM_SIZE(SRAM2);
868 }
869 else
870 {
871 mpcbb_ptr = GTZC_MPCBB3;
872 mem_size = GTZC_MEM_SIZE(SRAM3);
873 }
874 #else
875 else
876 {
877 mpcbb_ptr = GTZC_MPCBB2;
878 mem_size = GTZC_MEM_SIZE(SRAM2);
879 }
880 #endif /* defined (GTZC_MPCBB3) */
881
882 /* translate mem_size in number of super-blocks */
883 size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE);
884
885 /* write PRIVCFGR register information */
886 for (i = 0U; i < size_in_superblocks; i++)
887 {
888 WRITE_REG(mpcbb_ptr->PRIVCFGR[i],
889 pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i]);
890 }
891
892 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
893 uint32_t size_mask;
894 uint32_t reg_value;
895
896 /* write InvertSecureState and SecureRWIllegalMode properties */
897 reg_value = pMPCBB_desc->InvertSecureState;
898 reg_value |= pMPCBB_desc->SecureRWIllegalMode;
899
900 /* write SECCFGR register information */
901 for (i = 0U; i < size_in_superblocks; i++)
902 {
903 WRITE_REG(mpcbb_ptr->SECCFGR[i],
904 pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i]);
905 }
906
907 if (size_in_superblocks == 32U)
908 {
909 size_mask = 0xFFFFFFFFU;
910 }
911 else
912 {
913 size_mask = (1UL << size_in_superblocks) - 1U;
914 }
915 /* limitation: code not portable with memory > 512K */
916 MODIFY_REG(mpcbb_ptr->CFGLOCKR1, size_mask, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0]);
917
918 /* write configuration and lock register information */
919 MODIFY_REG(mpcbb_ptr->CR,
920 GTZC_MPCBB_CR_INVSECSTATE_Msk | GTZC_MPCBB_CR_SRWILADIS_Msk, reg_value);
921
922 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
923
924 return HAL_OK;
925 }
926
927 /**
928 * @brief Get a complete MPCBB configuration on the SRAM passed as parameter.
929 * @param MemBaseAddress MPCBB identifier.
930 * @param pMPCBB_desc pointer to a MPCBB descriptor.
931 * The structure description is available in @ref GTZC_Exported_Types.
932 * @retval HAL status.
933 */
HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress,MPCBB_ConfigTypeDef * pMPCBB_desc)934 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress,
935 MPCBB_ConfigTypeDef *pMPCBB_desc)
936 {
937 GTZC_MPCBB_TypeDef *mpcbb_ptr;
938 uint32_t mem_size;
939 uint32_t size_in_superblocks;
940 uint32_t i;
941
942 /* check entry parameters */
943 #if defined (GTZC_MPCBB3)
944 if (!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
945 && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
946 && !(IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)))
947 #else
948 if (!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
949 && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)))
950 #endif /* defined (GTZC_MPCBB3) */
951 {
952 return HAL_ERROR;
953 }
954
955 /* read InvertSecureState and SecureRWIllegalMode properties */
956 /* assume their Position/Mask is identical for all sub-blocks */
957 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
958 {
959 mpcbb_ptr = GTZC_MPCBB1;
960 mem_size = GTZC_MEM_SIZE(SRAM1);
961 }
962 #if defined (GTZC_MPCBB3)
963 else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
964 {
965 mpcbb_ptr = GTZC_MPCBB2;
966 mem_size = GTZC_MEM_SIZE(SRAM2);
967 }
968 else
969 {
970 mpcbb_ptr = GTZC_MPCBB3;
971 mem_size = GTZC_MEM_SIZE(SRAM3);
972 }
973 #else
974 else
975 {
976 mpcbb_ptr = GTZC_MPCBB2;
977 mem_size = GTZC_MEM_SIZE(SRAM2);
978 }
979 #endif /* */
980
981 /* translate mem_size in number of super-blocks */
982 size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE);
983
984 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
985 uint32_t reg_value;
986 uint32_t size_mask;
987
988 /* read configuration and lock register information */
989 reg_value = READ_REG(mpcbb_ptr->CR);
990 pMPCBB_desc->InvertSecureState = (reg_value & GTZC_MPCBB_CR_INVSECSTATE_Msk);
991 pMPCBB_desc->SecureRWIllegalMode = (reg_value & GTZC_MPCBB_CR_SRWILADIS_Msk);
992 if (size_in_superblocks == 32U)
993 {
994 size_mask = 0xFFFFFFFFU;
995 }
996 else
997 {
998 size_mask = (1UL << size_in_superblocks) - 1U;
999 }
1000 /* limitation: code not portable with memory > 512K */
1001 pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0] = READ_REG(mpcbb_ptr->CFGLOCKR1)
1002 & size_mask;
1003 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1004
1005 /* read SECCFGR / PRIVCFGR registers information */
1006 for (i = 0U; i < size_in_superblocks; i++)
1007 {
1008 #if defined (GTZC_TZIC1)
1009 pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i] = mpcbb_ptr->SECCFGR[i];
1010 #endif /* defined (GTZC_TZIC1) */
1011 pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i] = mpcbb_ptr->PRIVCFGR[i];
1012 }
1013
1014 return HAL_OK;
1015 }
1016
1017 /**
1018 * @brief Set a MPCBB attribute configuration on the SRAM passed as parameter
1019 * for a number of blocks.
1020 * @param MemAddress MPCBB identifier, and start block to configure
1021 * (must be 512 Bytes aligned).
1022 * @param NbBlocks Number of blocks to configure
1023 * (Block size is 512 Bytes).
1024 * @param pMemAttributes pointer to an array (containing "NbBlocks" elements),
1025 * with each element must be GTZC_MPCBB_BLOCK_NSEC or GTZC_MPCBB_BLOCK_SEC,
1026 * and GTZC_MPCBB_BLOCK_NPRIV or GTZC_MPCBB_BLOCK_PRIV.
1027 * @retval HAL status.
1028 */
HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,uint32_t NbBlocks,const uint32_t * pMemAttributes)1029 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,
1030 uint32_t NbBlocks,
1031 const uint32_t *pMemAttributes)
1032 {
1033 GTZC_MPCBB_TypeDef *mpcbb_ptr;
1034 uint32_t base_address;
1035 uint32_t end_address;
1036 uint32_t block_start;
1037 uint32_t offset_reg_start;
1038 uint32_t offset_bit_start;
1039 uint32_t i;
1040 uint32_t do_attr_change;
1041
1042 /* firstly check that MemAddress is well 512 Bytes aligned */
1043 if ((MemAddress % GTZC_MPCBB_BLOCK_SIZE) != 0U)
1044 {
1045 return HAL_ERROR;
1046 }
1047
1048 /* check entry parameters and deduce physical base address */
1049 end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U;
1050 if (((IS_ADDRESS_IN_NS(SRAM1, MemAddress))
1051 && (IS_ADDRESS_IN_NS(SRAM1, end_address))) != 0U)
1052 {
1053 mpcbb_ptr = GTZC_MPCBB1;
1054 base_address = SRAM1_BASE_NS;
1055 }
1056 #if defined (GTZC_TZIC1)
1057 else if (((IS_ADDRESS_IN_S(SRAM1, MemAddress))
1058 && (IS_ADDRESS_IN_S(SRAM1, end_address))) != 0U)
1059 {
1060 mpcbb_ptr = GTZC_MPCBB1;
1061 base_address = SRAM1_BASE_S;
1062 }
1063 #endif /* defined (GTZC_TZIC1) */
1064 else if (((IS_ADDRESS_IN_NS(SRAM2, MemAddress))
1065 && (IS_ADDRESS_IN_NS(SRAM2, end_address))) != 0U)
1066 {
1067 mpcbb_ptr = GTZC_MPCBB2;
1068 base_address = SRAM2_BASE_NS;
1069 }
1070 #if defined (GTZC_TZIC1)
1071 else if (((IS_ADDRESS_IN_S(SRAM2, MemAddress))
1072 && (IS_ADDRESS_IN_S(SRAM2, end_address))) != 0U)
1073 {
1074 mpcbb_ptr = GTZC_MPCBB2;
1075 base_address = SRAM2_BASE_S;
1076 }
1077 #endif /* defined (GTZC_TZIC1) */
1078 #if defined (GTZC_MPCBB3)
1079 else if (((IS_ADDRESS_IN_NS(SRAM3, MemAddress))
1080 && (IS_ADDRESS_IN_NS(SRAM3, end_address))) != 0U)
1081 {
1082 mpcbb_ptr = GTZC_MPCBB3;
1083 base_address = SRAM3_BASE_NS;
1084 }
1085 else if (((IS_ADDRESS_IN_S(SRAM3, MemAddress))
1086 && (IS_ADDRESS_IN_S(SRAM3, end_address))) != 0U)
1087 {
1088 mpcbb_ptr = GTZC_MPCBB3;
1089 base_address = SRAM3_BASE_S;
1090 }
1091 #endif /* defined (GTZC_MPCBB3) */
1092 else
1093 {
1094 return HAL_ERROR;
1095 }
1096
1097 /* get start coordinates of the configuration */
1098 block_start = (MemAddress - base_address) / GTZC_MPCBB_BLOCK_SIZE;
1099 offset_reg_start = block_start / 32U;
1100 offset_bit_start = block_start % 32U;
1101
1102 for (i = 0U; i < NbBlocks; i++)
1103 {
1104 /* Indicate change done for protection attributes */
1105 do_attr_change = 0U;
1106
1107 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1108 /* secure configuration */
1109 if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_SEC) == GTZC_MPCBB_BLOCK_SEC)
1110 {
1111 SET_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
1112 1UL << (offset_bit_start % 32U));
1113 do_attr_change = 1U;
1114 }
1115 else if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_NSEC) == GTZC_MPCBB_BLOCK_NSEC)
1116 {
1117 CLEAR_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
1118 1UL << (offset_bit_start % 32U));
1119 do_attr_change = 1U;
1120 }
1121 else
1122 {
1123 /* nothing to do */
1124 }
1125 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1126
1127 /* privilege configuration */
1128 if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_PRIV) == GTZC_MPCBB_BLOCK_PRIV)
1129 {
1130 SET_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
1131 1UL << (offset_bit_start % 32U));
1132 }
1133 else if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_NPRIV) == GTZC_MPCBB_BLOCK_NPRIV)
1134 {
1135 CLEAR_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
1136 1UL << (offset_bit_start % 32U));
1137 }
1138 else
1139 {
1140 /* if no change is done for security and privilege attributes: break the loop */
1141 if (do_attr_change == 0U)
1142 {
1143 break;
1144 }
1145 }
1146
1147 offset_bit_start++;
1148 if (offset_bit_start == 32U)
1149 {
1150 offset_bit_start = 0U;
1151 offset_reg_start++;
1152 }
1153 }
1154
1155 /* an unexpected value in pMemAttributes array leads to error status */
1156 if (i != NbBlocks)
1157 {
1158 return HAL_ERROR;
1159 }
1160
1161 return HAL_OK;
1162 }
1163
1164 /**
1165 * @brief Get a MPCBB attribute configuration on the SRAM passed as parameter
1166 * for a number of blocks.
1167 * @param MemAddress MPCBB identifier, and start block to get configuration
1168 * (must be 512 Bytes aligned).
1169 * @param NbBlocks Number of blocks to get configuration.
1170 * @param pMemAttributes pointer to an array (containing "NbBlocks" elements),
1171 * with each element will be GTZC_MPCBB_BLOCK_NSEC or GTZC_MPCBB_BLOCK_SEC,
1172 * and GTZC_MPCBB_BLOCK_NPRIV or GTZC_MPCBB_BLOCK_PRIV.
1173 * @retval HAL status.
1174 */
HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,uint32_t NbBlocks,uint32_t * pMemAttributes)1175 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,
1176 uint32_t NbBlocks,
1177 uint32_t *pMemAttributes)
1178 {
1179 GTZC_MPCBB_TypeDef *mpcbb_ptr;
1180 uint32_t base_address;
1181 uint32_t end_address;
1182 uint32_t block_start;
1183 uint32_t offset_reg_start;
1184 uint32_t offset_bit_start;
1185 uint32_t i;
1186
1187 /* firstly check that MemAddress is well 512 Bytes aligned */
1188 if ((MemAddress % GTZC_MPCBB_BLOCK_SIZE) != 0U)
1189 {
1190 return HAL_ERROR;
1191 }
1192
1193 /* check entry parameters and deduce physical base address */
1194 end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U;
1195 if ((IS_ADDRESS_IN_NS(SRAM1, MemAddress))
1196 && (IS_ADDRESS_IN_NS(SRAM1, end_address)))
1197 {
1198 mpcbb_ptr = GTZC_MPCBB1_NS;
1199 base_address = SRAM1_BASE_NS;
1200 }
1201 #if defined (GTZC_TZIC1)
1202 else if ((IS_ADDRESS_IN_S(SRAM1, MemAddress))
1203 && (IS_ADDRESS_IN_S(SRAM1, end_address)))
1204 {
1205 mpcbb_ptr = GTZC_MPCBB1_S;
1206 base_address = SRAM1_BASE_S;
1207 }
1208 #endif /* defined (GTZC_TZIC1) */
1209 else if ((IS_ADDRESS_IN_NS(SRAM2, MemAddress))
1210 && (IS_ADDRESS_IN_NS(SRAM2, end_address)))
1211 {
1212 mpcbb_ptr = GTZC_MPCBB2_NS;
1213 base_address = SRAM2_BASE_NS;
1214 }
1215 #if defined (GTZC_TZIC1)
1216 else if ((IS_ADDRESS_IN_S(SRAM2, MemAddress))
1217 && (IS_ADDRESS_IN_S(SRAM2, end_address)))
1218 {
1219 mpcbb_ptr = GTZC_MPCBB2_S;
1220 base_address = SRAM2_BASE_S;
1221 }
1222 #endif /* defined (GTZC_TZIC1) */
1223 #if defined (GTZC_MPCBB3)
1224 else if ((IS_ADDRESS_IN_NS(SRAM3, MemAddress))
1225 && (IS_ADDRESS_IN_NS(SRAM3, end_address)))
1226 {
1227 mpcbb_ptr = GTZC_MPCBB3_NS;
1228 base_address = SRAM3_BASE_NS;
1229 }
1230 else if ((IS_ADDRESS_IN_S(SRAM3, MemAddress))
1231 && (IS_ADDRESS_IN_S(SRAM3, end_address)))
1232 {
1233 mpcbb_ptr = GTZC_MPCBB3_S;
1234 base_address = SRAM3_BASE_S;
1235 }
1236 #endif /* defined (GTZC_MPCBB3) */
1237 else
1238 {
1239 return HAL_ERROR;
1240 }
1241
1242 /* get start coordinates of the configuration */
1243 block_start = (MemAddress - base_address) / GTZC_MPCBB_BLOCK_SIZE;
1244 offset_reg_start = block_start / 32U;
1245 offset_bit_start = block_start % 32U;
1246
1247 for (i = 0U; i < NbBlocks; i++)
1248 {
1249 #if defined (GTZC_TZIC1)
1250 pMemAttributes[i] = (READ_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
1251 1UL << (offset_bit_start % 32U))
1252 >> (offset_bit_start % 32U)) | GTZC_ATTR_SEC_MASK;
1253 #endif /* defined (GTZC_TZIC1) */
1254 pMemAttributes[i] |= ((READ_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
1255 1UL << (offset_bit_start % 32U))
1256 >> (offset_bit_start % 32U)) << 1U) | GTZC_ATTR_PRIV_MASK;
1257
1258 offset_bit_start++;
1259 if (offset_bit_start == 32U)
1260 {
1261 offset_bit_start = 0U;
1262 offset_reg_start++;
1263 }
1264 }
1265
1266 return HAL_OK;
1267 }
1268
1269 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1270 /**
1271 * @brief Lock MPCBB super-blocks on the SRAM passed as parameter.
1272 * @param MemAddress MPCBB start-address of super-block to configure
1273 * (must be 16KBytes aligned).
1274 * @param NbSuperBlocks Number of super-blocks to configure.
1275 * @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements),
1276 * with for each element:
1277 * value 0 super-block is unlocked, value 1 super-block is locked
1278 * (corresponds to GTZC_MPCBB_SUPERBLOCK_UNLOCKED and
1279 * GTZC_MPCBB_SUPERBLOCK_LOCKED values).
1280 * @retval HAL status.
1281 */
HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,uint32_t NbSuperBlocks,const uint32_t * pLockAttributes)1282 HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,
1283 uint32_t NbSuperBlocks,
1284 const uint32_t *pLockAttributes)
1285 {
1286 __IO uint32_t *reg_mpcbb;
1287 uint32_t base_address;
1288 uint32_t superblock_start;
1289 uint32_t offset_bit_start;
1290 uint32_t i;
1291
1292 /* firstly check that MemAddress is well 16KBytes aligned */
1293 if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U)
1294 {
1295 return HAL_ERROR;
1296 }
1297
1298 /* check entry parameters */
1299 if ((IS_ADDRESS_IN(SRAM1, MemAddress))
1300 && (IS_ADDRESS_IN(SRAM1, (MemAddress
1301 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1302 - 1U))))
1303 {
1304 base_address = GTZC_BASE_ADDRESS(SRAM1);
1305 /* limitation: code not portable with memory > 512K */
1306 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB1_S->CFGLOCKR1;
1307 }
1308 else if ((IS_ADDRESS_IN(SRAM2, MemAddress))
1309 && (IS_ADDRESS_IN(SRAM2, (MemAddress
1310 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1311 - 1U))))
1312 {
1313 base_address = GTZC_BASE_ADDRESS(SRAM2);
1314 /* limitation: code not portable with memory > 256K */
1315 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB2_S->CFGLOCKR1;
1316 }
1317 else if ((IS_ADDRESS_IN(SRAM3, MemAddress))
1318 && (IS_ADDRESS_IN(SRAM3, (MemAddress
1319 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1320 - 1U))))
1321 {
1322 base_address = GTZC_BASE_ADDRESS(SRAM3);
1323 /* limitation: code not portable with memory > 512K */
1324 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB3_S->CFGLOCKR1;
1325 }
1326
1327 else
1328 {
1329 return HAL_ERROR;
1330 }
1331
1332 /* get start coordinates of the configuration */
1333 superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE;
1334 offset_bit_start = superblock_start % 32U;
1335
1336 for (i = 0U; i < NbSuperBlocks; i++)
1337 {
1338 if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_LOCKED)
1339 {
1340 SET_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
1341 }
1342 else if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_UNLOCKED)
1343 {
1344 CLEAR_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
1345 }
1346 else
1347 {
1348 break;
1349 }
1350
1351 offset_bit_start++;
1352 }
1353
1354 /* an unexpected value in pLockAttributes array leads to an error status */
1355 if (i != NbSuperBlocks)
1356 {
1357 return HAL_ERROR;
1358 }
1359
1360 return HAL_OK;
1361 }
1362
1363 /**
1364 * @brief Get MPCBB super-blocks lock configuration on the SRAM passed as parameter.
1365 * @param MemAddress MPCBB start-address of super-block to get configuration
1366 * (must be 16KBytes aligned).
1367 * @param NbSuperBlocks Number of super-blocks to get configuration.
1368 * @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements),
1369 * with for each element:
1370 * value 0 super-block is unlocked, value 1 super-block is locked
1371 * (corresponds to GTZC_MPCBB_SUPERBLOCK_UNLOCKED and
1372 * GTZC_MPCBB_SUPERBLOCK_LOCKED values).
1373 * @retval HAL status.
1374 */
HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress,uint32_t NbSuperBlocks,uint32_t * pLockAttributes)1375 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress,
1376 uint32_t NbSuperBlocks,
1377 uint32_t *pLockAttributes)
1378 {
1379 uint32_t reg_mpcbb;
1380 uint32_t base_address;
1381 uint32_t superblock_start;
1382 uint32_t offset_bit_start;
1383 uint32_t i;
1384
1385 /* firstly check that MemAddress is well 16KBytes aligned */
1386 if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U)
1387 {
1388 return HAL_ERROR;
1389 }
1390
1391 /* check entry parameters */
1392 if ((IS_ADDRESS_IN(SRAM1, MemAddress))
1393 && (IS_ADDRESS_IN(SRAM1, (MemAddress
1394 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1395 - 1U))))
1396 {
1397 base_address = GTZC_BASE_ADDRESS(SRAM1);
1398 /* limitation: code not portable with memory > 512K */
1399 reg_mpcbb = GTZC_MPCBB1_S->CFGLOCKR1;
1400 }
1401 else if ((IS_ADDRESS_IN(SRAM2, MemAddress))
1402 && (IS_ADDRESS_IN(SRAM2, (MemAddress
1403 + (NbSuperBlocks
1404 * GTZC_MPCBB_SUPERBLOCK_SIZE)
1405 - 1U))))
1406 {
1407 base_address = GTZC_BASE_ADDRESS(SRAM2);
1408 /* limitation: code not portable with memory > 512K */
1409 reg_mpcbb = GTZC_MPCBB2_S->CFGLOCKR1;
1410 }
1411 else if ((IS_ADDRESS_IN(SRAM3, MemAddress))
1412 && (IS_ADDRESS_IN(SRAM3, (MemAddress
1413 + (NbSuperBlocks
1414 * GTZC_MPCBB_SUPERBLOCK_SIZE)
1415 - 1U))))
1416 {
1417 base_address = GTZC_BASE_ADDRESS(SRAM3);
1418 /* limitation: code not portable with memory > 512K */
1419 reg_mpcbb = GTZC_MPCBB3_S->CFGLOCKR1;
1420 }
1421 else
1422 {
1423 return HAL_ERROR;
1424 }
1425
1426 /* get start coordinates of the configuration */
1427 superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE;
1428 offset_bit_start = superblock_start % 32U;
1429
1430 for (i = 0U; i < NbSuperBlocks; i++)
1431 {
1432 pLockAttributes[i] = (reg_mpcbb & (1UL << (offset_bit_start % 32U)))
1433 >> (offset_bit_start % 32U);
1434 offset_bit_start++;
1435 }
1436
1437 return HAL_OK;
1438 }
1439
1440 /**
1441 * @brief Lock a MPCBB configuration on the SRAM base address passed as parameter.
1442 * @note This functions locks the control register of the MPCBB until next reset.
1443 * @param MemBaseAddress MPCBB identifier.
1444 * @retval HAL status.
1445 */
HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress)1446 HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress)
1447 {
1448 /* check entry parameters */
1449 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
1450 {
1451 SET_BIT(GTZC_MPCBB1_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1452 }
1453 else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
1454 {
1455 SET_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1456 }
1457 else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
1458 {
1459 SET_BIT(GTZC_MPCBB3_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1460 }
1461 else
1462 {
1463 return HAL_ERROR;
1464 }
1465
1466 return HAL_OK;
1467 }
1468
1469 /**
1470 * @brief Get MPCBB configuration lock state on the SRAM base address passed as parameter.
1471 * @param MemBaseAddress MPCBB identifier.
1472 * @param pLockState pointer to Lock State (GTZC_MPCBB_LOCK_OFF or GTZC_MPCBB_LOCK_ON).
1473 * @retval HAL status.
1474 */
HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress,uint32_t * pLockState)1475 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress,
1476 uint32_t *pLockState)
1477 {
1478 /* check entry parameters */
1479 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
1480 {
1481 *pLockState = READ_BIT(GTZC_MPCBB1_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1482 }
1483 else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
1484 {
1485 *pLockState = READ_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1486 }
1487 else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
1488 {
1489 *pLockState = READ_BIT(GTZC_MPCBB3_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1490 }
1491 else
1492 {
1493 return HAL_ERROR;
1494 }
1495
1496 return HAL_OK;
1497 }
1498
1499 /**
1500 * @}
1501 */
1502
1503 /** @defgroup GTZC_Exported_Functions_Group5 TZIC Configuration and Control functions
1504 * @brief TZIC Configuration and Control functions
1505 *
1506 @verbatim
1507 ==============================================================================
1508 ##### TZIC Configuration and Control functions #####
1509 ==============================================================================
1510 [..]
1511 This section provides functions allowing to configure and control TZIC
1512 TZIC is Trust Zone Interrupt Controller
1513 @endverbatim
1514 * @{
1515 */
1516
1517 /**
1518 * @brief Disable the interrupt associated to a single TZIC peripheral or on all peripherals.
1519 * @param PeriphId Peripheral identifier.
1520 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1521 * Use GTZC_PERIPH_ALL to select all peripherals.
1522 * @retval HAL status.
1523 */
HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId)1524 HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId)
1525 {
1526 uint32_t register_address;
1527
1528 /* check entry parameters */
1529 if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1530 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
1531 && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1532 {
1533 return HAL_ERROR;
1534 }
1535
1536 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1537 {
1538 /* same configuration is applied to all peripherals */
1539 WRITE_REG(GTZC_TZIC1->IER1, 0U);
1540 WRITE_REG(GTZC_TZIC1->IER2, 0U);
1541 WRITE_REG(GTZC_TZIC1->IER3, 0U);
1542 WRITE_REG(GTZC_TZIC1->IER4, 0U);
1543 }
1544 else
1545 {
1546 /* common case where only one peripheral is configured */
1547 register_address = (uint32_t) &(GTZC_TZIC1->IER1)
1548 + (4U * GTZC_GET_REG_INDEX(PeriphId));
1549 CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
1550 }
1551
1552 return HAL_OK;
1553 }
1554
1555 /**
1556 * @brief Enable the interrupt associated to a single TZIC peripheral or on all peripherals.
1557 * @param PeriphId Peripheral identifier.
1558 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1559 * Use GTZC_PERIPH_ALL to select all peripherals.
1560 * @retval HAL status.
1561 */
HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId)1562 HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId)
1563 {
1564 uint32_t register_address;
1565
1566 /* check entry parameters */
1567 if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1568 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
1569 && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1570 {
1571 return HAL_ERROR;
1572 }
1573
1574 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1575 {
1576 /* same configuration is applied to all peripherals */
1577 WRITE_REG(GTZC_TZIC1->IER1, GTZC_CFGR1_MSK);
1578 WRITE_REG(GTZC_TZIC1->IER2, GTZC_CFGR2_MSK);
1579 WRITE_REG(GTZC_TZIC1->IER3, GTZC_CFGR3_MSK);
1580 WRITE_REG(GTZC_TZIC1->IER4, GTZC_CFGR4_MSK);
1581 }
1582 else
1583 {
1584 /* common case where only one peripheral is configured */
1585 register_address = (uint32_t) &(GTZC_TZIC1->IER1)
1586 + (4U * GTZC_GET_REG_INDEX(PeriphId));
1587 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
1588 }
1589
1590 return HAL_OK;
1591 }
1592
1593 /**
1594 * @brief Get TZIC flag on a single TZIC peripheral or on all peripherals.
1595 * @param PeriphId Peripheral identifier.
1596 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1597 * Use GTZC_PERIPH_ALL to select all peripherals.
1598 * @param pFlag Pointer to the flags.
1599 * If PeriphId target a single peripheral, pointer on a single element.
1600 * If all peripherals selected (GTZC_PERIPH_ALL), pointer to an array
1601 * of GTZC_TZIC_PERIPH_NUMBER elements.
1602 * Element content is either GTZC_TZIC_NO_ILA_EVENT
1603 * or GTZC_TZSC_ILA_EVENT_PENDING.
1604 * @retval HAL status
1605 */
HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId,uint32_t * pFlag)1606 HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag)
1607 {
1608 uint32_t i;
1609 uint32_t reg_value;
1610 uint32_t register_address;
1611
1612 /* check entry parameters */
1613 if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1614 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
1615 && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1616 {
1617 return HAL_ERROR;
1618 }
1619
1620 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1621 {
1622 /* special case where it is applied to all peripherals */
1623 reg_value = READ_REG(GTZC_TZIC1->SR1);
1624 for (i = 0U; i < 32U; i++)
1625 {
1626 pFlag[i] = (reg_value & (1UL << i)) >> i;
1627 }
1628
1629 reg_value = READ_REG(GTZC_TZIC1->SR2);
1630 for (i = 32U; i < 64U; i++)
1631 {
1632 pFlag[i] = (reg_value & (1UL << (i - 32U))) >> (i - 32U);
1633 }
1634
1635 reg_value = READ_REG(GTZC_TZIC1->SR3);
1636 for (i = 64U; i < 96U; i++)
1637 {
1638 pFlag[i] = (reg_value & (1UL << (i - 64U))) >> (i - 64U);
1639 }
1640
1641 reg_value = READ_REG(GTZC_TZIC1->SR4);
1642 for (i = 96U; i < GTZC_TZIC_PERIPH_NUMBER; i++)
1643 {
1644 pFlag[i] = (reg_value & (1UL << (i - 96U))) >> (i - 96U);
1645 }
1646 }
1647 else
1648 {
1649 /* common case where only one peripheral is concerned */
1650 register_address = (uint32_t) &(GTZC_TZIC1->SR1)
1651 + (4U * GTZC_GET_REG_INDEX(PeriphId));
1652 *pFlag = READ_BIT(*(__IO uint32_t *)register_address,
1653 1UL << GTZC_GET_PERIPH_POS(PeriphId)) >> GTZC_GET_PERIPH_POS(PeriphId);
1654 }
1655
1656 return HAL_OK;
1657 }
1658
1659 /**
1660 * @brief Clear TZIC flag on a single TZIC peripheral or on all peripherals.
1661 * @param PeriphId Peripheral identifier.
1662 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1663 * Use GTZC_PERIPH_ALL to select all peripherals.
1664 * @retval HAL status.
1665 */
HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId)1666 HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId)
1667 {
1668 uint32_t register_address;
1669
1670 /* check entry parameters */
1671 if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1672 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
1673 && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1674 {
1675 return HAL_ERROR;
1676 }
1677
1678 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1679 {
1680 /* same configuration is applied to all peripherals */
1681 WRITE_REG(GTZC_TZIC1->FCR1, GTZC_CFGR1_MSK);
1682 WRITE_REG(GTZC_TZIC1->FCR2, GTZC_CFGR2_MSK);
1683 WRITE_REG(GTZC_TZIC1->FCR3, GTZC_CFGR3_MSK);
1684 WRITE_REG(GTZC_TZIC1->FCR4, GTZC_CFGR4_MSK);
1685 }
1686 else
1687 {
1688 /* common case where only one peripheral is configured */
1689 register_address = (uint32_t) &(GTZC_TZIC1->FCR1)
1690 + (4U * GTZC_GET_REG_INDEX(PeriphId));
1691 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
1692 }
1693
1694 return HAL_OK;
1695 }
1696
1697 /**
1698 * @}
1699 */
1700
1701 /** @defgroup GTZC_Exported_Functions_Group6 IRQ related functions
1702 * @brief IRQ related functions
1703 *
1704 @verbatim
1705 ==============================================================================
1706 ##### TZIC IRQ Handler and Callback functions #####
1707 ==============================================================================
1708 [..]
1709 This section provides functions allowing to treat ISR and provide user callback
1710 @endverbatim
1711 * @{
1712 */
1713
1714 /**
1715 * @brief This function handles GTZC TZIC interrupt request.
1716 * @retval None.
1717 */
HAL_GTZC_IRQHandler(void)1718 void HAL_GTZC_IRQHandler(void)
1719 {
1720 uint32_t position;
1721 uint32_t flag;
1722 uint32_t ier_itsources;
1723 uint32_t sr_flags;
1724
1725 /* Get current IT Flags and IT sources value on 1st register of TZIC1 */
1726 ier_itsources = READ_REG(GTZC_TZIC1_S->IER1);
1727 sr_flags = READ_REG(GTZC_TZIC1_S->SR1);
1728
1729 /* Get Mask interrupt and then clear them */
1730 flag = ier_itsources & sr_flags;
1731 if (flag != 0U)
1732 {
1733 WRITE_REG(GTZC_TZIC1_S->FCR1, flag);
1734
1735 /* Loop on flag to check, which ones have been raised */
1736 position = 0U;
1737 while ((flag >> position) != 0U)
1738 {
1739 if ((flag & (1UL << position)) != 0U)
1740 {
1741 HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG1 | position);
1742 }
1743
1744 /* Position bit to be updated */
1745 position++;
1746 }
1747 }
1748
1749 /* Get current IT Flags and IT sources value on 2nd register of TZIC1 */
1750 ier_itsources = READ_REG(GTZC_TZIC1_S->IER2);
1751 sr_flags = READ_REG(GTZC_TZIC1_S->SR2);
1752
1753 /* Get Mask interrupt and then clear them */
1754 flag = ier_itsources & sr_flags;
1755 if (flag != 0U)
1756 {
1757 WRITE_REG(GTZC_TZIC1_S->FCR2, flag);
1758
1759 /* Loop on flag to check, which ones have been raised */
1760 position = 0U;
1761 while ((flag >> position) != 0U)
1762 {
1763 if ((flag & (1UL << position)) != 0U)
1764 {
1765 HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG2 | position);
1766 }
1767
1768 /* Position bit to be updated */
1769 position++;
1770 }
1771 }
1772
1773 /* Get current IT Flags and IT sources value on 3rd register of TZIC1 */
1774 ier_itsources = READ_REG(GTZC_TZIC1_S->IER3);
1775 sr_flags = READ_REG(GTZC_TZIC1_S->SR3);
1776
1777 /* Get Mask interrupt and then clear them */
1778 flag = ier_itsources & sr_flags;
1779 if (flag != 0U)
1780 {
1781 WRITE_REG(GTZC_TZIC1_S->FCR3, flag);
1782
1783 /* Loop on flag to check, which ones have been raised */
1784 position = 0U;
1785 while ((flag >> position) != 0U)
1786 {
1787 if ((flag & (1UL << position)) != 0U)
1788 {
1789 HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG3 | position);
1790 }
1791
1792 /* Position bit to be updated */
1793 position++;
1794 }
1795 }
1796
1797 /* Get current IT Flags and IT sources value on 4th register of TZIC1 */
1798 ier_itsources = READ_REG(GTZC_TZIC1_S->IER4);
1799 sr_flags = READ_REG(GTZC_TZIC1_S->SR4);
1800
1801 /* Get Mask interrupt and then clear them */
1802 flag = ier_itsources & sr_flags;
1803 if (flag != 0U)
1804 {
1805 WRITE_REG(GTZC_TZIC1->FCR4, flag);
1806
1807 /* Loop on flag to check, which ones have been raised */
1808 position = 0U;
1809 while ((flag >> position) != 0U)
1810 {
1811 if ((flag & (1UL << position)) != 0U)
1812 {
1813 HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG4 | position);
1814 }
1815
1816 /* Position bit to be updated */
1817 position++;
1818 }
1819 }
1820 }
1821
1822 /**
1823 * @brief GTZC TZIC sub-block interrupt callback.
1824 * @param PeriphId Peripheral identifier triggering the illegal access.
1825 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId
1826 * @retval None.
1827 */
HAL_GTZC_TZIC_Callback(uint32_t PeriphId)1828 __weak void HAL_GTZC_TZIC_Callback(uint32_t PeriphId)
1829 {
1830 /* Prevent unused argument(s) compilation warning */
1831 UNUSED(PeriphId);
1832
1833 /* NOTE: This function should not be modified. When the callback is needed,
1834 * the HAL_GTZC_TZIC_Callback is to be implemented in the user file
1835 */
1836 }
1837
1838 /**
1839 * @}
1840 */
1841
1842 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1843
1844 /**
1845 * @}
1846 */
1847
1848 #endif /*HAL_GTZC_MODULE_ENABLED*/
1849
1850 /**
1851 * @}
1852 */
1853
1854 /**
1855 * @}
1856 */
1857
