1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_spi.c
4 * @author MCD Application Team
5 * @brief SPI LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32g4xx_ll_spi.h"
22 #include "stm32g4xx_ll_bus.h"
23 #include "stm32g4xx_ll_rcc.h"
24
25 #ifdef USE_FULL_ASSERT
26 #include "stm32_assert.h"
27 #else
28 #define assert_param(expr) ((void)0U)
29 #endif /* USE_FULL_ASSERT */
30
31 /** @addtogroup STM32G4xx_LL_Driver
32 * @{
33 */
34
35 #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4)
36
37 /** @addtogroup SPI_LL
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup SPI_LL_Private_Constants SPI Private Constants
46 * @{
47 */
48 /* SPI registers Masks */
49 #define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
50 SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
51 SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_CRCL | \
52 SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
53 SPI_CR1_BIDIMODE)
54 /**
55 * @}
56 */
57
58 /* Private macros ------------------------------------------------------------*/
59 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
60 * @{
61 */
62 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
63 || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
64 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
65 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
66
67 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
68 || ((__VALUE__) == LL_SPI_MODE_SLAVE))
69
70 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \
71 || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \
72 || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \
73 || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \
74 || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
75 || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \
76 || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
77 || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
78 || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
79 || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
80 || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
81 || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
82 || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
83
84 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
85 || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
86
87 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
88 || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
89
90 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
91 || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
92 || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
93
94 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
95 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
96 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
97 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
98 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
99 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
100 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
101 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
102
103 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
104 || ((__VALUE__) == LL_SPI_MSB_FIRST))
105
106 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
107 || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
108
109 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
110
111 /**
112 * @}
113 */
114
115 /* Private function prototypes -----------------------------------------------*/
116
117 /* Exported functions --------------------------------------------------------*/
118 /** @addtogroup SPI_LL_Exported_Functions
119 * @{
120 */
121
122 /** @addtogroup SPI_LL_EF_Init
123 * @{
124 */
125
126 /**
127 * @brief De-initialize the SPI registers to their default reset values.
128 * @param SPIx SPI Instance
129 * @retval An ErrorStatus enumeration value:
130 * - SUCCESS: SPI registers are de-initialized
131 * - ERROR: SPI registers are not de-initialized
132 */
LL_SPI_DeInit(const SPI_TypeDef * SPIx)133 ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx)
134 {
135 ErrorStatus status = ERROR;
136
137 /* Check the parameters */
138 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
139
140 #if defined(SPI1)
141 if (SPIx == SPI1)
142 {
143 /* Force reset of SPI clock */
144 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
145
146 /* Release reset of SPI clock */
147 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
148
149 status = SUCCESS;
150 }
151 #endif /* SPI1 */
152 #if defined(SPI2)
153 if (SPIx == SPI2)
154 {
155 /* Force reset of SPI clock */
156 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
157
158 /* Release reset of SPI clock */
159 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
160
161 status = SUCCESS;
162 }
163 #endif /* SPI2 */
164 #if defined(SPI3)
165 if (SPIx == SPI3)
166 {
167 /* Force reset of SPI clock */
168 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
169
170 /* Release reset of SPI clock */
171 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
172
173 status = SUCCESS;
174 }
175 #endif /* SPI3 */
176 #if defined(SPI4)
177 if (SPIx == SPI4)
178 {
179 /* Force reset of SPI clock */
180 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
181
182 /* Release reset of SPI clock */
183 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
184
185 status = SUCCESS;
186 }
187 #endif /* SPI4 */
188
189 return status;
190 }
191
192 /**
193 * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
194 * @note As some bits in SPI configuration registers can only be written when the
195 * SPI is disabled (SPI_CR1_SPE bit = 0), SPI peripheral should be in disabled state prior
196 * calling this function. Otherwise, ERROR result will be returned.
197 * @param SPIx SPI Instance
198 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
199 * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
200 */
LL_SPI_Init(SPI_TypeDef * SPIx,LL_SPI_InitTypeDef * SPI_InitStruct)201 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
202 {
203 ErrorStatus status = ERROR;
204
205 /* Check the SPI Instance SPIx*/
206 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
207
208 /* Check the SPI parameters from SPI_InitStruct*/
209 assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
210 assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
211 assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
212 assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
213 assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
214 assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
215 assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
216 assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
217 assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
218
219 if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
220 {
221 /*---------------------------- SPIx CR1 Configuration ------------------------
222 * Configure SPIx CR1 with parameters:
223 * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
224 * - Master/Slave Mode: SPI_CR1_MSTR bit
225 * - ClockPolarity: SPI_CR1_CPOL bit
226 * - ClockPhase: SPI_CR1_CPHA bit
227 * - NSS management: SPI_CR1_SSM bit
228 * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
229 * - BitOrder: SPI_CR1_LSBFIRST bit
230 * - CRCCalculation: SPI_CR1_CRCEN bit
231 */
232 MODIFY_REG(SPIx->CR1,
233 SPI_CR1_CLEAR_MASK,
234 SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
235 SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
236 SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
237 SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
238
239 /*---------------------------- SPIx CR2 Configuration ------------------------
240 * Configure SPIx CR2 with parameters:
241 * - DataWidth: DS[3:0] bits
242 * - NSS management: SSOE bit
243 */
244 MODIFY_REG(SPIx->CR2,
245 SPI_CR2_DS | SPI_CR2_SSOE,
246 SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
247
248 /* Set Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode. No DataPacking by default */
249 if (SPI_InitStruct->DataWidth < LL_SPI_DATAWIDTH_9BIT)
250 {
251 LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER);
252 }
253
254 /*---------------------------- SPIx CRCPR Configuration ----------------------
255 * Configure SPIx CRCPR with parameters:
256 * - CRCPoly: CRCPOLY[15:0] bits
257 */
258 if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
259 {
260 assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
261 LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
262 }
263 status = SUCCESS;
264 }
265
266 #if defined (SPI_I2S_SUPPORT)
267 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
268 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
269 #endif /* SPI_I2S_SUPPORT */
270 return status;
271 }
272
273 /**
274 * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
275 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
276 * whose fields will be set to default values.
277 * @retval None
278 */
LL_SPI_StructInit(LL_SPI_InitTypeDef * SPI_InitStruct)279 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
280 {
281 /* Set SPI_InitStruct fields to default values */
282 SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
283 SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
284 SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
285 SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
286 SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
287 SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
288 SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
289 SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
290 SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
291 SPI_InitStruct->CRCPoly = 7U;
292 }
293
294 /**
295 * @}
296 */
297
298 /**
299 * @}
300 */
301
302 /**
303 * @}
304 */
305
306 #if defined(SPI_I2S_SUPPORT)
307 /** @addtogroup I2S_LL
308 * @{
309 */
310
311 /* Private types -------------------------------------------------------------*/
312 /* Private variables ---------------------------------------------------------*/
313 /* Private constants ---------------------------------------------------------*/
314 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
315 * @{
316 */
317 /* I2S registers Masks */
318 #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
319 SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
320 SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
321
322 #define I2S_I2SPR_CLEAR_MASK 0x0002U
323 /**
324 * @}
325 */
326 /* Private macros ------------------------------------------------------------*/
327 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
328 * @{
329 */
330
331 #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
332 || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
333 || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
334 || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
335
336 #define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
337 || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
338
339 #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
340 || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
341 || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
342 || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
343 || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
344
345 #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
346 || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
347 || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
348 || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
349
350 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
351 || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
352
353 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
354 && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
355 || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
356
357 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
358
359 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
360 || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
361 /**
362 * @}
363 */
364
365 /* Private function prototypes -----------------------------------------------*/
366
367 /* Exported functions --------------------------------------------------------*/
368 /** @addtogroup I2S_LL_Exported_Functions
369 * @{
370 */
371
372 /** @addtogroup I2S_LL_EF_Init
373 * @{
374 */
375
376 /**
377 * @brief De-initialize the SPI/I2S registers to their default reset values.
378 * @param SPIx SPI Instance
379 * @retval An ErrorStatus enumeration value:
380 * - SUCCESS: SPI registers are de-initialized
381 * - ERROR: SPI registers are not de-initialized
382 */
LL_I2S_DeInit(const SPI_TypeDef * SPIx)383 ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx)
384 {
385 return LL_SPI_DeInit(SPIx);
386 }
387
388 /**
389 * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
390 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
391 * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
392 * @param SPIx SPI Instance
393 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
394 * @retval An ErrorStatus enumeration value:
395 * - SUCCESS: SPI registers are Initialized
396 * - ERROR: SPI registers are not Initialized
397 */
LL_I2S_Init(SPI_TypeDef * SPIx,LL_I2S_InitTypeDef * I2S_InitStruct)398 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
399 {
400 uint32_t i2sdiv = 2U;
401 uint32_t i2sodd = 0U;
402 uint32_t packetlength = 1U;
403 uint32_t tmp;
404 uint32_t sourceclock;
405 ErrorStatus status = ERROR;
406
407 /* Check the I2S parameters */
408 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
409 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
410 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
411 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
412 assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
413 assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
414 assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
415
416 if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
417 {
418 /*---------------------------- SPIx I2SCFGR Configuration --------------------
419 * Configure SPIx I2SCFGR with parameters:
420 * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
421 * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
422 * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
423 * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
424 */
425
426 /* Write to SPIx I2SCFGR */
427 MODIFY_REG(SPIx->I2SCFGR,
428 I2S_I2SCFGR_CLEAR_MASK,
429 I2S_InitStruct->Mode | I2S_InitStruct->Standard |
430 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
431 SPI_I2SCFGR_I2SMOD);
432
433 /*---------------------------- SPIx I2SPR Configuration ----------------------
434 * Configure SPIx I2SPR with parameters:
435 * - MCLKOutput: SPI_I2SPR_MCKOE bit
436 * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
437 */
438
439 /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
440 * else, default values are used: i2sodd = 0U, i2sdiv = 2U.
441 */
442 if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
443 {
444 /* Check the frame length (For the Prescaler computing)
445 * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
446 */
447 if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
448 {
449 /* Packet length is 32 bits */
450 packetlength = 2U;
451 }
452
453 /* If an external I2S clock has to be used, the specific define should be set
454 in the project configuration or in the stm32g4xx_ll_rcc.h file */
455 /* Get the I2S source clock value */
456 sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S_CLKSOURCE);
457
458 /* Compute the Real divider depending on the MCLK output state with a floating point */
459 if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
460 {
461 /* MCLK output is enabled */
462 tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
463 }
464 else
465 {
466 /* MCLK output is disabled */
467 tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
468 }
469
470 /* Remove the floating point */
471 tmp = tmp / 10U;
472
473 /* Check the parity of the divider */
474 i2sodd = (tmp & (uint16_t)0x0001U);
475
476 /* Compute the i2sdiv prescaler */
477 i2sdiv = ((tmp - i2sodd) / 2U);
478
479 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
480 i2sodd = (i2sodd << 8U);
481 }
482
483 /* Test if the divider is 1 or 0 or greater than 0xFF */
484 if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
485 {
486 /* Set the default values */
487 i2sdiv = 2U;
488 i2sodd = 0U;
489 }
490
491 /* Write to SPIx I2SPR register the computed value */
492 WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
493
494 status = SUCCESS;
495 }
496 return status;
497 }
498
499 /**
500 * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
501 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
502 * whose fields will be set to default values.
503 * @retval None
504 */
LL_I2S_StructInit(LL_I2S_InitTypeDef * I2S_InitStruct)505 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
506 {
507 /*--------------- Reset I2S init structure parameters values -----------------*/
508 I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
509 I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
510 I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
511 I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
512 I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
513 I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
514 }
515
516 /**
517 * @brief Set linear and parity prescaler.
518 * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
519 * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
520 * @param SPIx SPI Instance
521 * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
522 * @param PrescalerParity This parameter can be one of the following values:
523 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
524 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
525 * @retval None
526 */
LL_I2S_ConfigPrescaler(SPI_TypeDef * SPIx,uint32_t PrescalerLinear,uint32_t PrescalerParity)527 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
528 {
529 /* Check the I2S parameters */
530 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
531 assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
532 assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
533
534 /* Write to SPIx I2SPR */
535 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
536 }
537
538 /**
539 * @}
540 */
541
542 /**
543 * @}
544 */
545
546 /**
547 * @}
548 */
549 #endif /* SPI_I2S_SUPPORT */
550
551 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) */
552
553 /**
554 * @}
555 */
556
557 #endif /* USE_FULL_LL_DRIVER */
558
559
