1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_rcc.c
4 * @author MCD Application Team
5 * @brief RCC LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 ******************************************************************************
16 */
17 #if defined(USE_FULL_LL_DRIVER)
18
19 /* Includes ------------------------------------------------------------------*/
20 #include "stm32g4xx_ll_rcc.h"
21 #ifdef USE_FULL_ASSERT
22 #include "stm32_assert.h"
23 #else
24 #define assert_param(expr) ((void)0U)
25 #endif
26 /** @addtogroup STM32G4xx_LL_Driver
27 * @{
28 */
29
30 /** @addtogroup RCC_LL
31 * @{
32 */
33
34 /* Private types -------------------------------------------------------------*/
35 /* Private variables ---------------------------------------------------------*/
36 /* Private constants ---------------------------------------------------------*/
37 /* Private macros ------------------------------------------------------------*/
38 /** @addtogroup RCC_LL_Private_Macros
39 * @{
40 */
41 #if defined(RCC_CCIPR_USART3SEL)
42 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
43 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
44 || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
45 #else
46 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
47 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE))
48 #endif /* RCC_CCIPR_USART3SEL*/
49
50 #if defined(RCC_CCIPR_UART5SEL)
51 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
52 || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE))
53 #elif defined(RCC_CCIPR_UART4SEL)
54 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_UART4_CLKSOURCE)
55 #endif /* RCC_CCIPR_UART5SEL*/
56
57 #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE))
58
59 #if defined(RCC_CCIPR2_I2C4SEL)
60 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
61 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
62 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \
63 || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
64 #elif defined(RCC_CCIPR_I2C3SEL)
65 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
66 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
67 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
68 #else
69 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
70 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE))
71
72 #endif /* RCC_CCIPR2_I2C4SEL */
73 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE))
74
75 #if defined(SAI1)
76 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE)
77 #endif /* SAI1 */
78
79 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2S_CLKSOURCE)
80
81 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
82
83 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
84
85 #if defined(ADC345_COMMON)
86 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC12_CLKSOURCE) \
87 || ((__VALUE__) == LL_RCC_ADC345_CLKSOURCE))
88 #else
89 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC12_CLKSOURCE))
90 #endif /* ADC345_COMMON */
91
92 #if defined(QUADSPI)
93 #define IS_LL_RCC_QUADSPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_QUADSPI_CLKSOURCE))
94 #endif /* QUADSPI */
95
96 #if defined(FDCAN1)
97 #define IS_LL_RCC_FDCAN_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_FDCAN_CLKSOURCE))
98 #endif /* FDCAN1 */
99
100 /**
101 * @}
102 */
103
104 /* Private function prototypes -----------------------------------------------*/
105 /** @defgroup RCC_LL_Private_Functions RCC Private functions
106 * @{
107 */
108 static uint32_t RCC_GetSystemClockFreq(void);
109 static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
110 static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
111 static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
112 static uint32_t RCC_PLL_GetFreqDomain_SYS(void);
113 static uint32_t RCC_PLL_GetFreqDomain_ADC(void);
114 static uint32_t RCC_PLL_GetFreqDomain_48M(void);
115 /**
116 * @}
117 */
118
119
120 /* Exported functions --------------------------------------------------------*/
121 /** @addtogroup RCC_LL_Exported_Functions
122 * @{
123 */
124
125 /** @addtogroup RCC_LL_EF_Init
126 * @{
127 */
128
129 /**
130 * @brief Reset the RCC clock configuration to the default reset state.
131 * @note The default reset state of the clock configuration is given below:
132 * - HSI ON and used as system clock source
133 * - HSE and PLL OFF
134 * - AHB, APB1 and APB2 prescaler set to 1.
135 * - CSS, MCO OFF
136 * - All interrupts disabled
137 * @note This function doesn't modify the configuration of the
138 * - Peripheral clocks
139 * - LSI, LSE and RTC clocks
140 * @retval An ErrorStatus enumeration value:
141 * - SUCCESS: RCC registers are de-initialized
142 * - ERROR: not applicable
143 */
LL_RCC_DeInit(void)144 ErrorStatus LL_RCC_DeInit(void)
145 {
146 uint32_t vl_mask;
147
148 /* Set HSION bit and wait for HSI READY bit */
149 LL_RCC_HSI_Enable();
150 while (LL_RCC_HSI_IsReady() == 0U)
151 {}
152
153 /* Set HSITRIM bits to reset value*/
154 LL_RCC_HSI_SetCalibTrimming(0x40U);
155
156 /* Reset whole CFGR register but keep HSI as system clock source */
157 LL_RCC_WriteReg(CFGR, LL_RCC_SYS_CLKSOURCE_HSI);
158 while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) {};
159
160 /* Reset whole CR register but HSI in 2 steps in case HSEBYP is set */
161 LL_RCC_WriteReg(CR, RCC_CR_HSION);
162 LL_RCC_WriteReg(CR, RCC_CR_HSION);
163
164 /* Wait for PLL READY bit to be reset */
165 while (LL_RCC_PLL_IsReady() != 0U)
166 {}
167
168 /* Reset PLLCFGR register */
169 LL_RCC_WriteReg(PLLCFGR, 16U << RCC_PLLCFGR_PLLN_Pos);
170
171 /* Disable all interrupts */
172 LL_RCC_WriteReg(CIER, 0x00000000U);
173
174 /* Clear all interrupt flags */
175 vl_mask = RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | RCC_CICR_PLLRDYC | \
176 RCC_CICR_HSI48RDYC | RCC_CICR_CSSC | RCC_CICR_LSECSSC;
177
178 LL_RCC_WriteReg(CICR, vl_mask);
179
180 /* Clear reset flags */
181 LL_RCC_ClearResetFlags();
182
183 return SUCCESS;
184 }
185
186 /**
187 * @}
188 */
189
190 /** @addtogroup RCC_LL_EF_Get_Freq
191 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
192 * and different peripheral clocks available on the device.
193 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
194 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
195 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
196 * or HSI_VALUE(**) multiplied/divided by the PLL factors.
197 * @note (**) HSI_VALUE is a constant defined in this file (default value
198 * 16 MHz) but the real value may vary depending on the variations
199 * in voltage and temperature.
200 * @note (***) HSE_VALUE is a constant defined in this file (default value
201 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
202 * frequency of the crystal used. Otherwise, this function may
203 * have wrong result.
204 * @note The result of this function could be incorrect when using fractional
205 * value for HSE crystal.
206 * @note This function can be used by the user application to compute the
207 * baud-rate for the communication peripherals or configure other parameters.
208 * @{
209 */
210
211 /**
212 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
213 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
214 * must be called to update structure fields. Otherwise, any
215 * configuration based on this function will be incorrect.
216 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
217 * @retval None
218 */
LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef * RCC_Clocks)219 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
220 {
221 /* Get SYSCLK frequency */
222 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
223
224 /* HCLK clock frequency */
225 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
226
227 /* PCLK1 clock frequency */
228 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
229
230 /* PCLK2 clock frequency */
231 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
232 }
233
234 /**
235 * @brief Return USARTx clock frequency
236 * @param USARTxSource This parameter can be one of the following values:
237 * @arg @ref LL_RCC_USART1_CLKSOURCE
238 * @arg @ref LL_RCC_USART2_CLKSOURCE
239 * @arg @ref LL_RCC_USART3_CLKSOURCE
240 *
241 * @retval USART clock frequency (in Hz)
242 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
243 */
LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)244 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
245 {
246 uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
247
248 /* Check parameter */
249 assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
250
251 if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
252 {
253 /* USART1CLK clock frequency */
254 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
255 {
256 case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
257 usart_frequency = RCC_GetSystemClockFreq();
258 break;
259
260 case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
261 if (LL_RCC_HSI_IsReady() != 0U)
262 {
263 usart_frequency = HSI_VALUE;
264 }
265 break;
266
267 case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
268 if (LL_RCC_LSE_IsReady() != 0U)
269 {
270 usart_frequency = LSE_VALUE;
271 }
272 break;
273
274 case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */
275 default:
276 usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
277 break;
278 }
279 }
280 else if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
281 {
282 /* USART2CLK clock frequency */
283 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
284 {
285 case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
286 usart_frequency = RCC_GetSystemClockFreq();
287 break;
288
289 case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
290 if (LL_RCC_HSI_IsReady() != 0U)
291 {
292 usart_frequency = HSI_VALUE;
293 }
294 break;
295
296 case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
297 if (LL_RCC_LSE_IsReady() != 0U)
298 {
299 usart_frequency = LSE_VALUE;
300 }
301 break;
302
303 case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
304 default:
305 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
306 break;
307 }
308 }
309 else
310 {
311 #if defined(RCC_CCIPR_USART3SEL)
312 if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
313 {
314 /* USART3CLK clock frequency */
315 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
316 {
317 case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
318 usart_frequency = RCC_GetSystemClockFreq();
319 break;
320
321 case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */
322 if (LL_RCC_HSI_IsReady() != 0U)
323 {
324 usart_frequency = HSI_VALUE;
325 }
326 break;
327
328 case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */
329 if (LL_RCC_LSE_IsReady() != 0U)
330 {
331 usart_frequency = LSE_VALUE;
332 }
333 break;
334
335 case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */
336 default:
337 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
338 break;
339 }
340 }
341 #endif /* RCC_CCIPR_USART3SEL */
342 }
343 return usart_frequency;
344 }
345
346 #if defined(RCC_CCIPR_UART4SEL)
347 /**
348 * @brief Return UARTx clock frequency
349 * @param UARTxSource This parameter can be one of the following values:
350 * @arg @ref LL_RCC_UART4_CLKSOURCE (*)
351 * @arg @ref LL_RCC_UART5_CLKSOURCE (*)
352 *
353 * (*) value not defined in all devices.
354 * @retval UART clock frequency (in Hz)
355 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
356 */
LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)357 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
358 {
359 uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
360
361 /* Check parameter */
362 assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
363
364 if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
365 {
366 /* UART4CLK clock frequency */
367 switch (LL_RCC_GetUARTClockSource(UARTxSource))
368 {
369 case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */
370 uart_frequency = RCC_GetSystemClockFreq();
371 break;
372
373 case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */
374 if (LL_RCC_HSI_IsReady() != 0U)
375 {
376 uart_frequency = HSI_VALUE;
377 }
378 break;
379
380 case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */
381 if (LL_RCC_LSE_IsReady() != 0U)
382 {
383 uart_frequency = LSE_VALUE;
384 }
385 break;
386
387 case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */
388 default:
389 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
390 break;
391 }
392 }
393
394 #if defined(RCC_CCIPR_UART5SEL)
395 if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
396 {
397 /* UART5CLK clock frequency */
398 switch (LL_RCC_GetUARTClockSource(UARTxSource))
399 {
400 case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */
401 uart_frequency = RCC_GetSystemClockFreq();
402 break;
403
404 case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */
405 if (LL_RCC_HSI_IsReady() != 0U)
406 {
407 uart_frequency = HSI_VALUE;
408 }
409 break;
410
411 case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */
412 if (LL_RCC_LSE_IsReady() != 0U)
413 {
414 uart_frequency = LSE_VALUE;
415 }
416 break;
417
418 case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */
419 default:
420 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
421 break;
422 }
423 }
424 #endif /* RCC_CCIPR_UART5SEL */
425
426 return uart_frequency;
427 }
428 #endif /* RCC_CCIPR_UART4SEL */
429
430 /**
431 * @brief Return I2Cx clock frequency
432 * @param I2CxSource This parameter can be one of the following values:
433 * @arg @ref LL_RCC_I2C1_CLKSOURCE
434 * @arg @ref LL_RCC_I2C2_CLKSOURCE
435 * @arg @ref LL_RCC_I2C3_CLKSOURCE
436 * @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
437 *
438 * (*) value not defined in all devices.
439 * @retval I2C clock frequency (in Hz)
440 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
441 */
LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)442 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
443 {
444 uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
445
446 /* Check parameter */
447 assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
448
449 if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
450 {
451 /* I2C1 CLK clock frequency */
452 switch (LL_RCC_GetI2CClockSource(I2CxSource))
453 {
454 case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
455 i2c_frequency = RCC_GetSystemClockFreq();
456 break;
457
458 case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
459 if (LL_RCC_HSI_IsReady() != 0U)
460 {
461 i2c_frequency = HSI_VALUE;
462 }
463 break;
464
465 case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */
466 default:
467 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
468 break;
469 }
470 }
471 else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
472 {
473 /* I2C2 CLK clock frequency */
474 switch (LL_RCC_GetI2CClockSource(I2CxSource))
475 {
476 case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
477 i2c_frequency = RCC_GetSystemClockFreq();
478 break;
479
480 case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */
481 if (LL_RCC_HSI_IsReady() != 0U)
482 {
483 i2c_frequency = HSI_VALUE;
484 }
485 break;
486
487 case LL_RCC_I2C2_CLKSOURCE_PCLK1: /* I2C2 Clock is PCLK1 */
488 default:
489 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
490 break;
491 }
492 }
493 else
494 {
495 #if defined(RCC_CCIPR_I2C3SEL)
496 if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
497 {
498 /* I2C3 CLK clock frequency */
499 switch (LL_RCC_GetI2CClockSource(I2CxSource))
500 {
501 case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
502 i2c_frequency = RCC_GetSystemClockFreq();
503 break;
504
505 case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
506 if (LL_RCC_HSI_IsReady() != 0U)
507 {
508 i2c_frequency = HSI_VALUE;
509 }
510 break;
511
512 case LL_RCC_I2C3_CLKSOURCE_PCLK1: /* I2C3 Clock is PCLK1 */
513 default:
514 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
515 break;
516 }
517 }
518 #endif /* RCC_CCIPR_I2C3SEL */
519 #if defined(RCC_CCIPR2_I2C4SEL)
520 else
521 {
522 if (I2CxSource == LL_RCC_I2C4_CLKSOURCE)
523 {
524 /* I2C4 CLK clock frequency */
525 switch (LL_RCC_GetI2CClockSource(I2CxSource))
526 {
527 case LL_RCC_I2C4_CLKSOURCE_SYSCLK: /* I2C4 Clock is System Clock */
528 i2c_frequency = RCC_GetSystemClockFreq();
529 break;
530
531 case LL_RCC_I2C4_CLKSOURCE_HSI: /* I2C4 Clock is HSI Osc. */
532 if (LL_RCC_HSI_IsReady() != 0U)
533 {
534 i2c_frequency = HSI_VALUE;
535 }
536 break;
537
538 case LL_RCC_I2C4_CLKSOURCE_PCLK1: /* I2C4 Clock is PCLK1 */
539 default:
540 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
541 break;
542 }
543 }
544 }
545 #endif /*RCC_CCIPR2_I2C4SEL*/
546 }
547
548 return i2c_frequency;
549 }
550
551
552 /**
553 * @brief Return LPUARTx clock frequency
554 * @param LPUARTxSource This parameter can be one of the following values:
555 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
556 * @retval LPUART clock frequency (in Hz)
557 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
558 */
LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)559 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
560 {
561 uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
562
563 /* Check parameter */
564 assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource));
565
566 /* LPUART1CLK clock frequency */
567 switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
568 {
569 case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */
570 lpuart_frequency = RCC_GetSystemClockFreq();
571 break;
572
573 case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */
574 if (LL_RCC_HSI_IsReady() != 0U)
575 {
576 lpuart_frequency = HSI_VALUE;
577 }
578 break;
579
580 case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */
581 if (LL_RCC_LSE_IsReady() != 0U)
582 {
583 lpuart_frequency = LSE_VALUE;
584 }
585 break;
586
587 case LL_RCC_LPUART1_CLKSOURCE_PCLK1: /* LPUART1 Clock is PCLK1 */
588 default:
589 lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
590 break;
591 }
592
593 return lpuart_frequency;
594 }
595
596 /**
597 * @brief Return LPTIMx clock frequency
598 * @param LPTIMxSource This parameter can be one of the following values:
599 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
600 * @retval LPTIM clock frequency (in Hz)
601 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
602 */
LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)603 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
604 {
605 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
606
607 /* Check parameter */
608 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
609
610 if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
611 {
612 /* LPTIM1CLK clock frequency */
613 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
614 {
615 case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
616 if (LL_RCC_LSI_IsReady() != 0U)
617 {
618 lptim_frequency = LSI_VALUE;
619 }
620 break;
621
622 case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */
623 if (LL_RCC_HSI_IsReady() != 0U)
624 {
625 lptim_frequency = HSI_VALUE;
626 }
627 break;
628
629 case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
630 if (LL_RCC_LSE_IsReady() != 0U)
631 {
632 lptim_frequency = LSE_VALUE;
633 }
634 break;
635
636 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */
637 default:
638 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
639 break;
640 }
641 }
642
643 return lptim_frequency;
644 }
645
646 #if defined(SAI1)
647 /**
648 * @brief Return SAIx clock frequency
649 * @param SAIxSource This parameter can be one of the following values:
650 * @arg @ref LL_RCC_SAI1_CLKSOURCE
651 *
652 * @retval SAI clock frequency (in Hz)
653 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
654 */
LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)655 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
656 {
657 uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
658
659 /* Check parameter */
660 assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
661
662 if (SAIxSource == LL_RCC_SAI1_CLKSOURCE)
663 {
664 /* SAI1CLK clock frequency */
665 switch (LL_RCC_GetSAIClockSource(SAIxSource))
666 {
667 case LL_RCC_SAI1_CLKSOURCE_SYSCLK: /* System clock used as SAI1 clock source */
668 sai_frequency = RCC_GetSystemClockFreq();
669 break;
670
671 case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */
672 if (LL_RCC_PLL_IsReady() != 0U)
673 {
674 if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
675 {
676 sai_frequency = RCC_PLL_GetFreqDomain_48M();
677 }
678 }
679 break;
680
681 case LL_RCC_SAI1_CLKSOURCE_PIN: /* SAI1 Clock is External clock */
682 sai_frequency = EXTERNAL_CLOCK_VALUE;
683 break;
684
685 case LL_RCC_SAI1_CLKSOURCE_HSI: /* HSI clock used as SAI1 clock source */
686 default:
687 if (LL_RCC_HSI_IsReady() != 0U)
688 {
689 sai_frequency = HSI_VALUE;
690 }
691 break;
692
693 }
694 }
695
696 return sai_frequency;
697 }
698
699 #endif /* SAI1 */
700
701 #if defined(SPI_I2S_SUPPORT)
702 /**
703 * @brief Return I2Sx clock frequency
704 * @param I2SxSource This parameter can be one of the following values:
705 * @arg @ref LL_RCC_I2S_CLKSOURCE
706 * @retval I2S clock frequency (in Hz)
707 * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
708 */
LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)709 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
710 {
711 uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
712
713 /* Check parameter */
714 assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
715
716 if (I2SxSource == LL_RCC_I2S_CLKSOURCE)
717 {
718 /* I2S CLK clock frequency */
719 switch (LL_RCC_GetI2SClockSource(I2SxSource))
720 {
721 case LL_RCC_I2S_CLKSOURCE_SYSCLK: /* I2S Clock is System Clock */
722 i2s_frequency = RCC_GetSystemClockFreq();
723 break;
724
725 case LL_RCC_I2S_CLKSOURCE_PLL: /* I2S Clock is PLL"Q" */
726 if (LL_RCC_PLL_IsReady() != 0U)
727 {
728 if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
729 {
730 i2s_frequency = RCC_PLL_GetFreqDomain_48M();
731 }
732 }
733 break;
734
735 case LL_RCC_I2S_CLKSOURCE_PIN: /* I2S Clock is External clock */
736 i2s_frequency = EXTERNAL_CLOCK_VALUE;
737 break;
738
739 case LL_RCC_I2S_CLKSOURCE_HSI: /* I2S Clock is HSI */
740 default:
741 if (LL_RCC_HSI_IsReady() != 0U)
742 {
743 i2s_frequency = HSI_VALUE;
744 }
745 break;
746 }
747 }
748
749 return i2s_frequency;
750 }
751 #endif /* SPI_I2S_SUPPORT */
752
753 #if defined(FDCAN1)
754 /**
755 * @brief Return FDCAN kernel clock frequency
756 * @param FDCANxSource This parameter can be one of the following values:
757 * @arg @ref LL_RCC_FDCAN_CLKSOURCE
758 * @retval FDCAN kernel clock frequency (in Hz)
759 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
760 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
761 */
LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)762 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)
763 {
764 uint32_t fdcan_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
765
766 /* Check parameter */
767 assert_param(IS_LL_RCC_FDCAN_CLKSOURCE(FDCANxSource));
768
769 /* FDCAN kernel clock frequency */
770 switch (LL_RCC_GetFDCANClockSource(FDCANxSource))
771 {
772 case LL_RCC_FDCAN_CLKSOURCE_HSE: /* HSE clock used as FDCAN kernel clock */
773 if (LL_RCC_HSE_IsReady() != 0U)
774 {
775 fdcan_frequency = HSE_VALUE;
776 }
777 break;
778
779 case LL_RCC_FDCAN_CLKSOURCE_PLL: /* PLL clock used as FDCAN kernel clock */
780 if (LL_RCC_PLL_IsReady() != 0U)
781 {
782 if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
783 {
784 fdcan_frequency = RCC_PLL_GetFreqDomain_48M();
785 }
786 }
787 break;
788
789 case LL_RCC_FDCAN_CLKSOURCE_PCLK1: /* PCLK1 clock used as FDCAN kernel clock */
790 fdcan_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
791 break;
792
793 default:
794 fdcan_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
795 break;
796 }
797 return fdcan_frequency;
798 }
799 #endif /* FDCAN1 */
800
801 /**
802 * @brief Return RNGx clock frequency
803 * @param RNGxSource This parameter can be one of the following values:
804 * @arg @ref LL_RCC_RNG_CLKSOURCE
805 * @retval RNG clock frequency (in Hz)
806 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready
807 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
808 */
LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)809 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
810 {
811 uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
812
813 /* Check parameter */
814 assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
815
816 /* RNGCLK clock frequency */
817 switch (LL_RCC_GetRNGClockSource(RNGxSource))
818 {
819 case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */
820 if (LL_RCC_PLL_IsReady() != 0U)
821 {
822 if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
823 {
824 rng_frequency = RCC_PLL_GetFreqDomain_48M();
825 }
826 }
827 break;
828
829 case LL_RCC_RNG_CLKSOURCE_HSI48: /* HSI48 used as RNG clock source */
830 if (LL_RCC_HSI48_IsReady() != 0U)
831 {
832 rng_frequency = HSI48_VALUE;
833 }
834 break;
835
836 default:
837 rng_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
838 break;
839
840 }
841
842 return rng_frequency;
843 }
844
845 /**
846 * @brief Return USBx clock frequency
847 * @param USBxSource This parameter can be one of the following values:
848 * @arg @ref LL_RCC_USB_CLKSOURCE
849 * @retval USB clock frequency (in Hz)
850 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready
851 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
852 */
LL_RCC_GetUSBClockFreq(uint32_t USBxSource)853 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
854 {
855 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
856
857 /* Check parameter */
858 assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
859
860 /* USBCLK clock frequency */
861 switch (LL_RCC_GetUSBClockSource(USBxSource))
862 {
863 case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
864 if (LL_RCC_PLL_IsReady() != 0U)
865 {
866 if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
867 {
868 usb_frequency = RCC_PLL_GetFreqDomain_48M();
869 }
870 }
871 break;
872
873 case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 used as USB clock source */
874 if (LL_RCC_HSI48_IsReady() != 0U)
875 {
876 usb_frequency = HSI48_VALUE;
877 }
878 break;
879
880 default:
881 usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
882 break;
883 }
884
885 return usb_frequency;
886 }
887
888 /**
889 * @brief Return ADCx clock frequency
890 * @param ADCxSource This parameter can be one of the following values:
891 * @arg @ref LL_RCC_ADC12_CLKSOURCE
892 * @arg @ref LL_RCC_ADC345_CLKSOURCE (*)
893 *
894 * (*) value not defined in all devices.
895 * @retval ADC clock frequency (in Hz)
896 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
897 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
898 */
LL_RCC_GetADCClockFreq(uint32_t ADCxSource)899 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
900 {
901 uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
902
903 /* Check parameter */
904 assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
905
906 if (ADCxSource == LL_RCC_ADC12_CLKSOURCE)
907 {
908 /* ADC12CLK clock frequency */
909 switch (LL_RCC_GetADCClockSource(ADCxSource))
910 {
911 case LL_RCC_ADC12_CLKSOURCE_PLL: /* PLL clock used as ADC12 clock source */
912 if (LL_RCC_PLL_IsReady() != 0U)
913 {
914 if (LL_RCC_PLL_IsEnabledDomain_ADC() != 0U)
915 {
916 adc_frequency = RCC_PLL_GetFreqDomain_ADC();
917 }
918 }
919 break;
920
921 case LL_RCC_ADC12_CLKSOURCE_SYSCLK: /* System clock used as ADC12 clock source */
922 adc_frequency = RCC_GetSystemClockFreq();
923 break;
924
925 case LL_RCC_ADC12_CLKSOURCE_NONE: /* No clock used as ADC12 clock source */
926 default:
927 adc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
928 break;
929 }
930 }
931 #if defined(ADC345_COMMON)
932 else
933 {
934 /* ADC345CLK clock frequency */
935 switch (LL_RCC_GetADCClockSource(ADCxSource))
936 {
937 case LL_RCC_ADC345_CLKSOURCE_PLL: /* PLL clock used as ADC345 clock source */
938 if (LL_RCC_PLL_IsReady() != 0U)
939 {
940 if (LL_RCC_PLL_IsEnabledDomain_ADC() != 0U)
941 {
942 adc_frequency = RCC_PLL_GetFreqDomain_ADC();
943 }
944 }
945 break;
946
947 case LL_RCC_ADC345_CLKSOURCE_SYSCLK: /* System clock used as ADC345 clock source */
948 adc_frequency = RCC_GetSystemClockFreq();
949 break;
950
951 case LL_RCC_ADC345_CLKSOURCE_NONE: /* No clock used as ADC345 clock source */
952 default:
953 adc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
954 break;
955 }
956 }
957 #endif /* ADC345_COMMON */
958
959 return adc_frequency;
960 }
961
962 #if defined(QUADSPI)
963 /**
964 * @brief Return QUADSPI clock frequency
965 * @param QUADSPIxSource This parameter can be one of the following values:
966 * @arg @ref LL_RCC_QUADSPI_CLKSOURCE
967 * @retval QUADSPI clock frequency (in Hz)
968 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that no clock is configured
969 */
LL_RCC_GetQUADSPIClockFreq(uint32_t QUADSPIxSource)970 uint32_t LL_RCC_GetQUADSPIClockFreq(uint32_t QUADSPIxSource)
971 {
972 uint32_t quadspi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
973
974 /* Check parameter */
975 assert_param(IS_LL_RCC_QUADSPI_CLKSOURCE(QUADSPIxSource));
976
977 /* QUADSPI clock frequency */
978 switch (LL_RCC_GetQUADSPIClockSource(QUADSPIxSource))
979 {
980 case LL_RCC_QUADSPI_CLKSOURCE_SYSCLK: /* SYSCLK used as QUADSPI source */
981 quadspi_frequency = RCC_GetSystemClockFreq();
982 break;
983
984 case LL_RCC_QUADSPI_CLKSOURCE_HSI: /* HSI clock used as QUADSPI source */
985 if (LL_RCC_HSI_IsReady() != 0U)
986 {
987 quadspi_frequency = HSI_VALUE;
988 }
989 break;
990
991 case LL_RCC_QUADSPI_CLKSOURCE_PLL: /* PLL clock used as QUADSPI source */
992 if (LL_RCC_PLL_IsReady() != 0U)
993 {
994 if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
995 {
996 quadspi_frequency = RCC_PLL_GetFreqDomain_48M();
997 }
998 }
999 break;
1000
1001 default:
1002 /* Nothing to do: quadspi frequency already initilalized to LL_RCC_PERIPH_FREQUENCY_NO */
1003 break;
1004 }
1005
1006 return quadspi_frequency;
1007 }
1008 #endif /* QUADSPI */
1009
1010 /**
1011 * @}
1012 */
1013
1014 /**
1015 * @}
1016 */
1017
1018 /** @addtogroup RCC_LL_Private_Functions
1019 * @{
1020 */
1021
1022 /**
1023 * @brief Return SYSTEM clock frequency
1024 * @retval SYSTEM clock frequency (in Hz)
1025 */
RCC_GetSystemClockFreq(void)1026 static uint32_t RCC_GetSystemClockFreq(void)
1027 {
1028 uint32_t frequency;
1029
1030 /* Get SYSCLK source -------------------------------------------------------*/
1031 switch (LL_RCC_GetSysClkSource())
1032 {
1033 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
1034 frequency = HSI_VALUE;
1035 break;
1036
1037 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
1038 frequency = HSE_VALUE;
1039 break;
1040
1041 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
1042 frequency = RCC_PLL_GetFreqDomain_SYS();
1043 break;
1044
1045 default:
1046 frequency = HSI_VALUE;
1047 break;
1048 }
1049
1050 return frequency;
1051 }
1052
1053 /**
1054 * @brief Return HCLK clock frequency
1055 * @param SYSCLK_Frequency SYSCLK clock frequency
1056 * @retval HCLK clock frequency (in Hz)
1057 */
RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)1058 static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
1059 {
1060 /* HCLK clock frequency */
1061 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
1062 }
1063
1064 /**
1065 * @brief Return PCLK1 clock frequency
1066 * @param HCLK_Frequency HCLK clock frequency
1067 * @retval PCLK1 clock frequency (in Hz)
1068 */
RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)1069 static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
1070 {
1071 /* PCLK1 clock frequency */
1072 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
1073 }
1074
1075 /**
1076 * @brief Return PCLK2 clock frequency
1077 * @param HCLK_Frequency HCLK clock frequency
1078 * @retval PCLK2 clock frequency (in Hz)
1079 */
RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)1080 static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
1081 {
1082 /* PCLK2 clock frequency */
1083 return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
1084 }
1085
1086 /**
1087 * @brief Return PLL clock frequency used for system domain
1088 * @retval PLL clock frequency (in Hz)
1089 */
RCC_PLL_GetFreqDomain_SYS(void)1090 static uint32_t RCC_PLL_GetFreqDomain_SYS(void)
1091 {
1092 uint32_t pllinputfreq, pllsource;
1093
1094 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1095 SYSCLK = PLL_VCO / PLLR
1096 */
1097 pllsource = LL_RCC_PLL_GetMainSource();
1098
1099 switch (pllsource)
1100 {
1101 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1102 pllinputfreq = HSI_VALUE;
1103 break;
1104
1105 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1106 pllinputfreq = HSE_VALUE;
1107 break;
1108
1109 default:
1110 pllinputfreq = HSI_VALUE;
1111 break;
1112 }
1113 return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1114 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1115 }
1116
1117 /**
1118 * @brief Return PLL clock frequency used for ADC domain
1119 * @retval PLL clock frequency (in Hz)
1120 */
RCC_PLL_GetFreqDomain_ADC(void)1121 static uint32_t RCC_PLL_GetFreqDomain_ADC(void)
1122 {
1123 uint32_t pllinputfreq, pllsource;
1124
1125 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1126 ADC Domain clock = PLL_VCO / PLLP
1127 */
1128 pllsource = LL_RCC_PLL_GetMainSource();
1129
1130 switch (pllsource)
1131 {
1132 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1133 pllinputfreq = HSI_VALUE;
1134 break;
1135
1136 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1137 pllinputfreq = HSE_VALUE;
1138 break;
1139
1140 default:
1141 pllinputfreq = HSI_VALUE;
1142 break;
1143 }
1144 return __LL_RCC_CALC_PLLCLK_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1145 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
1146 }
1147
1148 /**
1149 * @brief Return PLL clock frequency used for 48 MHz domain
1150 * @retval PLL clock frequency (in Hz)
1151 */
RCC_PLL_GetFreqDomain_48M(void)1152 static uint32_t RCC_PLL_GetFreqDomain_48M(void)
1153 {
1154 uint32_t pllinputfreq, pllsource;
1155
1156 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1157 48M Domain clock = PLL_VCO / PLLQ
1158 */
1159 pllsource = LL_RCC_PLL_GetMainSource();
1160
1161 switch (pllsource)
1162 {
1163 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1164 pllinputfreq = HSI_VALUE;
1165 break;
1166
1167 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1168 pllinputfreq = HSE_VALUE;
1169 break;
1170
1171 default:
1172 pllinputfreq = HSI_VALUE;
1173 break;
1174 }
1175 return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1176 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
1177 }
1178
1179 /**
1180 * @}
1181 */
1182
1183 /**
1184 * @}
1185 */
1186
1187 /**
1188 * @}
1189 */
1190
1191 #endif /* USE_FULL_LL_DRIVER */
1192
1193
