1 /**
2 ******************************************************************************
3 * @file stm32g4xx_hal_tim_ex.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer Extended peripheral:
8 * + Time Hall Sensor Interface Initialization
9 * + Time Hall Sensor Interface Start
10 * + Time Complementary signal break and dead time configuration
11 * + Time Master and Slave synchronization configuration
12 * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
13 * + Time OCRef clear configuration
14 * + Timer remapping capabilities configuration
15 * + Timer encoder index configuration
16 ******************************************************************************
17 * @attention
18 *
19 * Copyright (c) 2019 STMicroelectronics.
20 * All rights reserved.
21 *
22 * This software is licensed under terms that can be found in the LICENSE file
23 * in the root directory of this software component.
24 * If no LICENSE file comes with this software, it is provided AS-IS.
25 *
26 ******************************************************************************
27 @verbatim
28 ==============================================================================
29 ##### TIMER Extended features #####
30 ==============================================================================
31 [..]
32 The Timer Extended features include:
33 (#) Complementary outputs with programmable dead-time for :
34 (++) Output Compare
35 (++) PWM generation (Edge and Center-aligned Mode)
36 (++) One-pulse mode output
37 (#) Synchronization circuit to control the timer with external signals and to
38 interconnect several timers together.
39 (#) Break input to put the timer output signals in reset state or in a known state.
40 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
41 positioning purposes
42 (#) In case of Pulse on compare, configure pulse length and delay
43 (#) Encoder index configuration
44
45 ##### How to use this driver #####
46 ==============================================================================
47 [..]
48 (#) Initialize the TIM low level resources by implementing the following functions
49 depending on the selected feature:
50 (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
51
52 (#) Initialize the TIM low level resources :
53 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
54 (##) TIM pins configuration
55 (+++) Enable the clock for the TIM GPIOs using the following function:
56 __HAL_RCC_GPIOx_CLK_ENABLE();
57 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
58
59 (#) The external Clock can be configured, if needed (the default clock is the
60 internal clock from the APBx), using the following function:
61 HAL_TIM_ConfigClockSource, the clock configuration should be done before
62 any start function.
63
64 (#) Configure the TIM in the desired functioning mode using one of the
65 initialization function of this driver:
66 (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
67 Timer Hall Sensor Interface and the commutation event with the corresponding
68 Interrupt and DMA request if needed (Note that One Timer is used to interface
69 with the Hall sensor Interface and another Timer should be used to use
70 the commutation event).
71 (#) In case of Pulse On Compare:
72 (++) HAL_TIMEx_OC_ConfigPulseOnCompare(): to configure pulse width and prescaler
73
74
75 (#) Activate the TIM peripheral using one of the start functions:
76 (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
77 HAL_TIMEx_OCN_Start_IT()
78 (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
79 HAL_TIMEx_PWMN_Start_IT()
80 (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
81 (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(),
82 HAL_TIMEx_HallSensor_Start_IT().
83
84 @endverbatim
85 ******************************************************************************
86 */
87
88 /* Includes ------------------------------------------------------------------*/
89 #include "stm32g4xx_hal.h"
90
91 /** @addtogroup STM32G4xx_HAL_Driver
92 * @{
93 */
94
95 /** @defgroup TIMEx TIMEx
96 * @brief TIM Extended HAL module driver
97 * @{
98 */
99
100 #ifdef HAL_TIM_MODULE_ENABLED
101
102 /* Private typedef -----------------------------------------------------------*/
103 /* Private define ------------------------------------------------------------*/
104 /* Private constants ---------------------------------------------------------*/
105 /** @defgroup TIMEx_Private_Constants TIM Extended Private Constants
106 * @{
107 */
108 /* Timeout for break input rearm */
109 #define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */
110 /**
111 * @}
112 */
113 /* End of private constants --------------------------------------------------*/
114
115 /* Private macros ------------------------------------------------------------*/
116 /* Private variables ---------------------------------------------------------*/
117 /* Private function prototypes -----------------------------------------------*/
118 static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
119 static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
120 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
121
122 /* Exported functions --------------------------------------------------------*/
123 /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
124 * @{
125 */
126
127 /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
128 * @brief Timer Hall Sensor functions
129 *
130 @verbatim
131 ==============================================================================
132 ##### Timer Hall Sensor functions #####
133 ==============================================================================
134 [..]
135 This section provides functions allowing to:
136 (+) Initialize and configure TIM HAL Sensor.
137 (+) De-initialize TIM HAL Sensor.
138 (+) Start the Hall Sensor Interface.
139 (+) Stop the Hall Sensor Interface.
140 (+) Start the Hall Sensor Interface and enable interrupts.
141 (+) Stop the Hall Sensor Interface and disable interrupts.
142 (+) Start the Hall Sensor Interface and enable DMA transfers.
143 (+) Stop the Hall Sensor Interface and disable DMA transfers.
144
145 @endverbatim
146 * @{
147 */
148 /**
149 * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
150 * @note When the timer instance is initialized in Hall Sensor Interface mode,
151 * timer channels 1 and channel 2 are reserved and cannot be used for
152 * other purpose.
153 * @param htim TIM Hall Sensor Interface handle
154 * @param sConfig TIM Hall Sensor configuration structure
155 * @retval HAL status
156 */
HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef * htim,const TIM_HallSensor_InitTypeDef * sConfig)157 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig)
158 {
159 TIM_OC_InitTypeDef OC_Config;
160
161 /* Check the TIM handle allocation */
162 if (htim == NULL)
163 {
164 return HAL_ERROR;
165 }
166
167 /* Check the parameters */
168 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
169 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
170 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
171 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
172 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
173 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
174 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
175 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
176
177 if (htim->State == HAL_TIM_STATE_RESET)
178 {
179 /* Allocate lock resource and initialize it */
180 htim->Lock = HAL_UNLOCKED;
181
182 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
183 /* Reset interrupt callbacks to legacy week callbacks */
184 TIM_ResetCallback(htim);
185
186 if (htim->HallSensor_MspInitCallback == NULL)
187 {
188 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
189 }
190 /* Init the low level hardware : GPIO, CLOCK, NVIC */
191 htim->HallSensor_MspInitCallback(htim);
192 #else
193 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
194 HAL_TIMEx_HallSensor_MspInit(htim);
195 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
196 }
197
198 /* Set the TIM state */
199 htim->State = HAL_TIM_STATE_BUSY;
200
201 /* Configure the Time base in the Encoder Mode */
202 TIM_Base_SetConfig(htim->Instance, &htim->Init);
203
204 /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
205 TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
206
207 /* Reset the IC1PSC Bits */
208 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
209 /* Set the IC1PSC value */
210 htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
211
212 /* Enable the Hall sensor interface (XOR function of the three inputs) */
213 htim->Instance->CR2 |= TIM_CR2_TI1S;
214
215 /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
216 htim->Instance->SMCR &= ~TIM_SMCR_TS;
217 htim->Instance->SMCR |= TIM_TS_TI1F_ED;
218
219 /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
220 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
221 htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
222
223 /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
224 OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
225 OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
226 OC_Config.OCMode = TIM_OCMODE_PWM2;
227 OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
228 OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
229 OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
230 OC_Config.Pulse = sConfig->Commutation_Delay;
231
232 TIM_OC2_SetConfig(htim->Instance, &OC_Config);
233
234 /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
235 register to 101 */
236 htim->Instance->CR2 &= ~TIM_CR2_MMS;
237 htim->Instance->CR2 |= TIM_TRGO_OC2REF;
238
239 /* Initialize the DMA burst operation state */
240 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
241
242 /* Initialize the TIM channels state */
243 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
244 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
245 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
246 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
247
248 /* Initialize the TIM state*/
249 htim->State = HAL_TIM_STATE_READY;
250
251 return HAL_OK;
252 }
253
254 /**
255 * @brief DeInitializes the TIM Hall Sensor interface
256 * @param htim TIM Hall Sensor Interface handle
257 * @retval HAL status
258 */
HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef * htim)259 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
260 {
261 /* Check the parameters */
262 assert_param(IS_TIM_INSTANCE(htim->Instance));
263
264 htim->State = HAL_TIM_STATE_BUSY;
265
266 /* Disable the TIM Peripheral Clock */
267 __HAL_TIM_DISABLE(htim);
268
269 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
270 if (htim->HallSensor_MspDeInitCallback == NULL)
271 {
272 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
273 }
274 /* DeInit the low level hardware */
275 htim->HallSensor_MspDeInitCallback(htim);
276 #else
277 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
278 HAL_TIMEx_HallSensor_MspDeInit(htim);
279 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
280
281 /* Change the DMA burst operation state */
282 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
283
284 /* Change the TIM channels state */
285 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
286 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
287 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
288 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
289
290 /* Change TIM state */
291 htim->State = HAL_TIM_STATE_RESET;
292
293 /* Release Lock */
294 __HAL_UNLOCK(htim);
295
296 return HAL_OK;
297 }
298
299 /**
300 * @brief Initializes the TIM Hall Sensor MSP.
301 * @param htim TIM Hall Sensor Interface handle
302 * @retval None
303 */
HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef * htim)304 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
305 {
306 /* Prevent unused argument(s) compilation warning */
307 UNUSED(htim);
308
309 /* NOTE : This function should not be modified, when the callback is needed,
310 the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
311 */
312 }
313
314 /**
315 * @brief DeInitializes TIM Hall Sensor MSP.
316 * @param htim TIM Hall Sensor Interface handle
317 * @retval None
318 */
HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef * htim)319 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
320 {
321 /* Prevent unused argument(s) compilation warning */
322 UNUSED(htim);
323
324 /* NOTE : This function should not be modified, when the callback is needed,
325 the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
326 */
327 }
328
329 /**
330 * @brief Starts the TIM Hall Sensor Interface.
331 * @param htim TIM Hall Sensor Interface handle
332 * @retval HAL status
333 */
HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef * htim)334 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
335 {
336 uint32_t tmpsmcr;
337 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
338 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
339 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
340 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
341
342 /* Check the parameters */
343 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
344
345 /* Check the TIM channels state */
346 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
347 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
348 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
349 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
350 {
351 return HAL_ERROR;
352 }
353
354 /* Set the TIM channels state */
355 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
356 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
357 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
358 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
359
360 /* Enable the Input Capture channel 1
361 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
362 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
363 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
364
365 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
366 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
367 {
368 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
369 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
370 {
371 __HAL_TIM_ENABLE(htim);
372 }
373 }
374 else
375 {
376 __HAL_TIM_ENABLE(htim);
377 }
378
379 /* Return function status */
380 return HAL_OK;
381 }
382
383 /**
384 * @brief Stops the TIM Hall sensor Interface.
385 * @param htim TIM Hall Sensor Interface handle
386 * @retval HAL status
387 */
HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef * htim)388 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
389 {
390 /* Check the parameters */
391 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
392
393 /* Disable the Input Capture channels 1, 2 and 3
394 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
395 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
396 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
397
398 /* Disable the Peripheral */
399 __HAL_TIM_DISABLE(htim);
400
401 /* Set the TIM channels state */
402 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
403 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
404 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
405 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
406
407 /* Return function status */
408 return HAL_OK;
409 }
410
411 /**
412 * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
413 * @param htim TIM Hall Sensor Interface handle
414 * @retval HAL status
415 */
HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef * htim)416 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
417 {
418 uint32_t tmpsmcr;
419 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
420 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
421 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
422 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
423
424 /* Check the parameters */
425 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
426
427 /* Check the TIM channels state */
428 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
429 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
430 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
431 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
432 {
433 return HAL_ERROR;
434 }
435
436 /* Set the TIM channels state */
437 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
438 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
439 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
440 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
441
442 /* Enable the capture compare Interrupts 1 event */
443 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
444
445 /* Enable the Input Capture channel 1
446 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
447 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
448 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
449
450 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
451 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
452 {
453 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
454 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
455 {
456 __HAL_TIM_ENABLE(htim);
457 }
458 }
459 else
460 {
461 __HAL_TIM_ENABLE(htim);
462 }
463
464 /* Return function status */
465 return HAL_OK;
466 }
467
468 /**
469 * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
470 * @param htim TIM Hall Sensor Interface handle
471 * @retval HAL status
472 */
HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef * htim)473 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
474 {
475 /* Check the parameters */
476 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
477
478 /* Disable the Input Capture channel 1
479 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
480 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
481 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
482
483 /* Disable the capture compare Interrupts event */
484 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
485
486 /* Disable the Peripheral */
487 __HAL_TIM_DISABLE(htim);
488
489 /* Set the TIM channels state */
490 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
491 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
492 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
493 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
494
495 /* Return function status */
496 return HAL_OK;
497 }
498
499 /**
500 * @brief Starts the TIM Hall Sensor Interface in DMA mode.
501 * @param htim TIM Hall Sensor Interface handle
502 * @param pData The destination Buffer address.
503 * @param Length The length of data to be transferred from TIM peripheral to memory.
504 * @retval HAL status
505 */
HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef * htim,uint32_t * pData,uint16_t Length)506 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
507 {
508 uint32_t tmpsmcr;
509 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
510 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
511
512 /* Check the parameters */
513 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
514
515 /* Set the TIM channel state */
516 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
517 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
518 {
519 return HAL_BUSY;
520 }
521 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
522 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
523 {
524 if ((pData == NULL) || (Length == 0U))
525 {
526 return HAL_ERROR;
527 }
528 else
529 {
530 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
531 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
532 }
533 }
534 else
535 {
536 return HAL_ERROR;
537 }
538
539 /* Enable the Input Capture channel 1
540 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
541 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
542 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
543
544 /* Set the DMA Input Capture 1 Callbacks */
545 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
546 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
547 /* Set the DMA error callback */
548 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
549
550 /* Enable the DMA channel for Capture 1*/
551 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
552 {
553 /* Return error status */
554 return HAL_ERROR;
555 }
556 /* Enable the capture compare 1 Interrupt */
557 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
558
559 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
560 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
561 {
562 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
563 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
564 {
565 __HAL_TIM_ENABLE(htim);
566 }
567 }
568 else
569 {
570 __HAL_TIM_ENABLE(htim);
571 }
572
573 /* Return function status */
574 return HAL_OK;
575 }
576
577 /**
578 * @brief Stops the TIM Hall Sensor Interface in DMA mode.
579 * @param htim TIM Hall Sensor Interface handle
580 * @retval HAL status
581 */
HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef * htim)582 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
583 {
584 /* Check the parameters */
585 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
586
587 /* Disable the Input Capture channel 1
588 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
589 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
590 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
591
592
593 /* Disable the capture compare Interrupts 1 event */
594 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
595
596 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
597
598 /* Disable the Peripheral */
599 __HAL_TIM_DISABLE(htim);
600
601 /* Set the TIM channel state */
602 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
603 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
604
605 /* Return function status */
606 return HAL_OK;
607 }
608
609 /**
610 * @}
611 */
612
613 /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
614 * @brief Timer Complementary Output Compare functions
615 *
616 @verbatim
617 ==============================================================================
618 ##### Timer Complementary Output Compare functions #####
619 ==============================================================================
620 [..]
621 This section provides functions allowing to:
622 (+) Start the Complementary Output Compare/PWM.
623 (+) Stop the Complementary Output Compare/PWM.
624 (+) Start the Complementary Output Compare/PWM and enable interrupts.
625 (+) Stop the Complementary Output Compare/PWM and disable interrupts.
626 (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
627 (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
628
629 @endverbatim
630 * @{
631 */
632
633 /**
634 * @brief Starts the TIM Output Compare signal generation on the complementary
635 * output.
636 * @param htim TIM Output Compare handle
637 * @param Channel TIM Channel to be enabled
638 * This parameter can be one of the following values:
639 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
640 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
641 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
642 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
643 * @retval HAL status
644 */
HAL_TIMEx_OCN_Start(TIM_HandleTypeDef * htim,uint32_t Channel)645 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
646 {
647 uint32_t tmpsmcr;
648
649 /* Check the parameters */
650 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
651
652 /* Check the TIM complementary channel state */
653 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
654 {
655 return HAL_ERROR;
656 }
657
658 /* Set the TIM complementary channel state */
659 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
660
661 /* Enable the Capture compare channel N */
662 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
663
664 /* Enable the Main Output */
665 __HAL_TIM_MOE_ENABLE(htim);
666
667 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
668 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
669 {
670 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
671 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
672 {
673 __HAL_TIM_ENABLE(htim);
674 }
675 }
676 else
677 {
678 __HAL_TIM_ENABLE(htim);
679 }
680
681 /* Return function status */
682 return HAL_OK;
683 }
684
685 /**
686 * @brief Stops the TIM Output Compare signal generation on the complementary
687 * output.
688 * @param htim TIM handle
689 * @param Channel TIM Channel to be disabled
690 * This parameter can be one of the following values:
691 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
692 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
693 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
694 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
695 * @retval HAL status
696 */
HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)697 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
698 {
699 /* Check the parameters */
700 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
701
702 /* Disable the Capture compare channel N */
703 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
704
705 /* Disable the Main Output */
706 __HAL_TIM_MOE_DISABLE(htim);
707
708 /* Disable the Peripheral */
709 __HAL_TIM_DISABLE(htim);
710
711 /* Set the TIM complementary channel state */
712 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
713
714 /* Return function status */
715 return HAL_OK;
716 }
717
718 /**
719 * @brief Starts the TIM Output Compare signal generation in interrupt mode
720 * on the complementary output.
721 * @param htim TIM OC handle
722 * @param Channel TIM Channel to be enabled
723 * This parameter can be one of the following values:
724 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
725 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
726 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
727 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
728 * @retval HAL status
729 */
HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)730 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
731 {
732 HAL_StatusTypeDef status = HAL_OK;
733 uint32_t tmpsmcr;
734
735 /* Check the parameters */
736 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
737
738 /* Check the TIM complementary channel state */
739 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
740 {
741 return HAL_ERROR;
742 }
743
744 /* Set the TIM complementary channel state */
745 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
746
747 switch (Channel)
748 {
749 case TIM_CHANNEL_1:
750 {
751 /* Enable the TIM Output Compare interrupt */
752 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
753 break;
754 }
755
756 case TIM_CHANNEL_2:
757 {
758 /* Enable the TIM Output Compare interrupt */
759 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
760 break;
761 }
762
763 case TIM_CHANNEL_3:
764 {
765 /* Enable the TIM Output Compare interrupt */
766 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
767 break;
768 }
769
770
771 case TIM_CHANNEL_4:
772 {
773 /* Enable the TIM Output Compare interrupt */
774 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
775 break;
776 }
777
778 default:
779 status = HAL_ERROR;
780 break;
781 }
782
783 if (status == HAL_OK)
784 {
785 /* Enable the TIM Break interrupt */
786 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
787
788 /* Enable the Capture compare channel N */
789 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
790
791 /* Enable the Main Output */
792 __HAL_TIM_MOE_ENABLE(htim);
793
794 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
795 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
796 {
797 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
798 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
799 {
800 __HAL_TIM_ENABLE(htim);
801 }
802 }
803 else
804 {
805 __HAL_TIM_ENABLE(htim);
806 }
807 }
808
809 /* Return function status */
810 return status;
811 }
812
813 /**
814 * @brief Stops the TIM Output Compare signal generation in interrupt mode
815 * on the complementary output.
816 * @param htim TIM Output Compare handle
817 * @param Channel TIM Channel to be disabled
818 * This parameter can be one of the following values:
819 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
820 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
821 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
822 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
823 * @retval HAL status
824 */
HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)825 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
826 {
827 HAL_StatusTypeDef status = HAL_OK;
828 uint32_t tmpccer;
829
830 /* Check the parameters */
831 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
832
833 switch (Channel)
834 {
835 case TIM_CHANNEL_1:
836 {
837 /* Disable the TIM Output Compare interrupt */
838 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
839 break;
840 }
841
842 case TIM_CHANNEL_2:
843 {
844 /* Disable the TIM Output Compare interrupt */
845 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
846 break;
847 }
848
849 case TIM_CHANNEL_3:
850 {
851 /* Disable the TIM Output Compare interrupt */
852 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
853 break;
854 }
855
856 case TIM_CHANNEL_4:
857 {
858 /* Disable the TIM Output Compare interrupt */
859 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
860 break;
861 }
862
863 default:
864 status = HAL_ERROR;
865 break;
866 }
867
868 if (status == HAL_OK)
869 {
870 /* Disable the Capture compare channel N */
871 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
872
873 /* Disable the TIM Break interrupt (only if no more channel is active) */
874 tmpccer = htim->Instance->CCER;
875 if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
876 {
877 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
878 }
879
880 /* Disable the Main Output */
881 __HAL_TIM_MOE_DISABLE(htim);
882
883 /* Disable the Peripheral */
884 __HAL_TIM_DISABLE(htim);
885
886 /* Set the TIM complementary channel state */
887 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
888 }
889
890 /* Return function status */
891 return status;
892 }
893
894 /**
895 * @brief Starts the TIM Output Compare signal generation in DMA mode
896 * on the complementary output.
897 * @param htim TIM Output Compare handle
898 * @param Channel TIM Channel to be enabled
899 * This parameter can be one of the following values:
900 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
901 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
902 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
903 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
904 * @param pData The source Buffer address.
905 * @param Length The length of data to be transferred from memory to TIM peripheral
906 * @retval HAL status
907 */
HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)908 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
909 uint16_t Length)
910 {
911 HAL_StatusTypeDef status = HAL_OK;
912 uint32_t tmpsmcr;
913
914 /* Check the parameters */
915 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
916
917 /* Set the TIM complementary channel state */
918 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
919 {
920 return HAL_BUSY;
921 }
922 else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
923 {
924 if ((pData == NULL) || (Length == 0U))
925 {
926 return HAL_ERROR;
927 }
928 else
929 {
930 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
931 }
932 }
933 else
934 {
935 return HAL_ERROR;
936 }
937
938 switch (Channel)
939 {
940 case TIM_CHANNEL_1:
941 {
942 /* Set the DMA compare callbacks */
943 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
944 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
945
946 /* Set the DMA error callback */
947 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
948
949 /* Enable the DMA channel */
950 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
951 Length) != HAL_OK)
952 {
953 /* Return error status */
954 return HAL_ERROR;
955 }
956 /* Enable the TIM Output Compare DMA request */
957 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
958 break;
959 }
960
961 case TIM_CHANNEL_2:
962 {
963 /* Set the DMA compare callbacks */
964 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
965 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
966
967 /* Set the DMA error callback */
968 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
969
970 /* Enable the DMA channel */
971 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
972 Length) != HAL_OK)
973 {
974 /* Return error status */
975 return HAL_ERROR;
976 }
977 /* Enable the TIM Output Compare DMA request */
978 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
979 break;
980 }
981
982 case TIM_CHANNEL_3:
983 {
984 /* Set the DMA compare callbacks */
985 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
986 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
987
988 /* Set the DMA error callback */
989 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
990
991 /* Enable the DMA channel */
992 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
993 Length) != HAL_OK)
994 {
995 /* Return error status */
996 return HAL_ERROR;
997 }
998 /* Enable the TIM Output Compare DMA request */
999 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1000 break;
1001 }
1002
1003 case TIM_CHANNEL_4:
1004 {
1005 /* Set the DMA compare callbacks */
1006 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1007 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1008
1009 /* Set the DMA error callback */
1010 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ;
1011
1012 /* Enable the DMA channel */
1013 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1014 Length) != HAL_OK)
1015 {
1016 /* Return error status */
1017 return HAL_ERROR;
1018 }
1019 /* Enable the TIM Output Compare DMA request */
1020 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1021 break;
1022 }
1023
1024 default:
1025 status = HAL_ERROR;
1026 break;
1027 }
1028
1029 if (status == HAL_OK)
1030 {
1031 /* Enable the Capture compare channel N */
1032 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1033
1034 /* Enable the Main Output */
1035 __HAL_TIM_MOE_ENABLE(htim);
1036
1037 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1038 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1039 {
1040 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1041 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1042 {
1043 __HAL_TIM_ENABLE(htim);
1044 }
1045 }
1046 else
1047 {
1048 __HAL_TIM_ENABLE(htim);
1049 }
1050 }
1051
1052 /* Return function status */
1053 return status;
1054 }
1055
1056 /**
1057 * @brief Stops the TIM Output Compare signal generation in DMA mode
1058 * on the complementary output.
1059 * @param htim TIM Output Compare handle
1060 * @param Channel TIM Channel to be disabled
1061 * This parameter can be one of the following values:
1062 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1063 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1064 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1065 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1066 * @retval HAL status
1067 */
HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1068 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1069 {
1070 HAL_StatusTypeDef status = HAL_OK;
1071
1072 /* Check the parameters */
1073 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1074
1075 switch (Channel)
1076 {
1077 case TIM_CHANNEL_1:
1078 {
1079 /* Disable the TIM Output Compare DMA request */
1080 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1081 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1082 break;
1083 }
1084
1085 case TIM_CHANNEL_2:
1086 {
1087 /* Disable the TIM Output Compare DMA request */
1088 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1089 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1090 break;
1091 }
1092
1093 case TIM_CHANNEL_3:
1094 {
1095 /* Disable the TIM Output Compare DMA request */
1096 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1097 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1098 break;
1099 }
1100
1101 case TIM_CHANNEL_4:
1102 {
1103 /* Disable the TIM Output Compare interrupt */
1104 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1105 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1106 break;
1107 }
1108
1109 default:
1110 status = HAL_ERROR;
1111 break;
1112 }
1113
1114 if (status == HAL_OK)
1115 {
1116 /* Disable the Capture compare channel N */
1117 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1118
1119 /* Disable the Main Output */
1120 __HAL_TIM_MOE_DISABLE(htim);
1121
1122 /* Disable the Peripheral */
1123 __HAL_TIM_DISABLE(htim);
1124
1125 /* Set the TIM complementary channel state */
1126 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1127 }
1128
1129 /* Return function status */
1130 return status;
1131 }
1132
1133 /**
1134 * @}
1135 */
1136
1137 /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
1138 * @brief Timer Complementary PWM functions
1139 *
1140 @verbatim
1141 ==============================================================================
1142 ##### Timer Complementary PWM functions #####
1143 ==============================================================================
1144 [..]
1145 This section provides functions allowing to:
1146 (+) Start the Complementary PWM.
1147 (+) Stop the Complementary PWM.
1148 (+) Start the Complementary PWM and enable interrupts.
1149 (+) Stop the Complementary PWM and disable interrupts.
1150 (+) Start the Complementary PWM and enable DMA transfers.
1151 (+) Stop the Complementary PWM and disable DMA transfers.
1152 @endverbatim
1153 * @{
1154 */
1155
1156 /**
1157 * @brief Starts the PWM signal generation on the complementary output.
1158 * @param htim TIM handle
1159 * @param Channel TIM Channel to be enabled
1160 * This parameter can be one of the following values:
1161 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1162 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1163 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1164 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1165 * @retval HAL status
1166 */
HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1167 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1168 {
1169 uint32_t tmpsmcr;
1170
1171 /* Check the parameters */
1172 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1173
1174 /* Check the TIM complementary channel state */
1175 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1176 {
1177 return HAL_ERROR;
1178 }
1179
1180 /* Set the TIM complementary channel state */
1181 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1182
1183 /* Enable the complementary PWM output */
1184 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1185
1186 /* Enable the Main Output */
1187 __HAL_TIM_MOE_ENABLE(htim);
1188
1189 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1190 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1191 {
1192 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1193 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1194 {
1195 __HAL_TIM_ENABLE(htim);
1196 }
1197 }
1198 else
1199 {
1200 __HAL_TIM_ENABLE(htim);
1201 }
1202
1203 /* Return function status */
1204 return HAL_OK;
1205 }
1206
1207 /**
1208 * @brief Stops the PWM signal generation on the complementary output.
1209 * @param htim TIM handle
1210 * @param Channel TIM Channel to be disabled
1211 * This parameter can be one of the following values:
1212 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1213 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1214 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1215 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1216 * @retval HAL status
1217 */
HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1218 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1219 {
1220 /* Check the parameters */
1221 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1222
1223 /* Disable the complementary PWM output */
1224 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1225
1226 /* Disable the Main Output */
1227 __HAL_TIM_MOE_DISABLE(htim);
1228
1229 /* Disable the Peripheral */
1230 __HAL_TIM_DISABLE(htim);
1231
1232 /* Set the TIM complementary channel state */
1233 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1234
1235 /* Return function status */
1236 return HAL_OK;
1237 }
1238
1239 /**
1240 * @brief Starts the PWM signal generation in interrupt mode on the
1241 * complementary output.
1242 * @param htim TIM handle
1243 * @param Channel TIM Channel to be disabled
1244 * This parameter can be one of the following values:
1245 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1246 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1247 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1248 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1249 * @retval HAL status
1250 */
HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1251 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1252 {
1253 HAL_StatusTypeDef status = HAL_OK;
1254 uint32_t tmpsmcr;
1255
1256 /* Check the parameters */
1257 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1258
1259 /* Check the TIM complementary channel state */
1260 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1261 {
1262 return HAL_ERROR;
1263 }
1264
1265 /* Set the TIM complementary channel state */
1266 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1267
1268 switch (Channel)
1269 {
1270 case TIM_CHANNEL_1:
1271 {
1272 /* Enable the TIM Capture/Compare 1 interrupt */
1273 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1274 break;
1275 }
1276
1277 case TIM_CHANNEL_2:
1278 {
1279 /* Enable the TIM Capture/Compare 2 interrupt */
1280 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1281 break;
1282 }
1283
1284 case TIM_CHANNEL_3:
1285 {
1286 /* Enable the TIM Capture/Compare 3 interrupt */
1287 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1288 break;
1289 }
1290
1291 case TIM_CHANNEL_4:
1292 {
1293 /* Enable the TIM Capture/Compare 4 interrupt */
1294 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1295 break;
1296 }
1297
1298 default:
1299 status = HAL_ERROR;
1300 break;
1301 }
1302
1303 if (status == HAL_OK)
1304 {
1305 /* Enable the TIM Break interrupt */
1306 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
1307
1308 /* Enable the complementary PWM output */
1309 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1310
1311 /* Enable the Main Output */
1312 __HAL_TIM_MOE_ENABLE(htim);
1313
1314 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1315 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1316 {
1317 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1318 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1319 {
1320 __HAL_TIM_ENABLE(htim);
1321 }
1322 }
1323 else
1324 {
1325 __HAL_TIM_ENABLE(htim);
1326 }
1327 }
1328
1329 /* Return function status */
1330 return status;
1331 }
1332
1333 /**
1334 * @brief Stops the PWM signal generation in interrupt mode on the
1335 * complementary output.
1336 * @param htim TIM handle
1337 * @param Channel TIM Channel to be disabled
1338 * This parameter can be one of the following values:
1339 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1340 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1341 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1342 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1343 * @retval HAL status
1344 */
HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1345 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1346 {
1347 HAL_StatusTypeDef status = HAL_OK;
1348 uint32_t tmpccer;
1349
1350 /* Check the parameters */
1351 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1352
1353 switch (Channel)
1354 {
1355 case TIM_CHANNEL_1:
1356 {
1357 /* Disable the TIM Capture/Compare 1 interrupt */
1358 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1359 break;
1360 }
1361
1362 case TIM_CHANNEL_2:
1363 {
1364 /* Disable the TIM Capture/Compare 2 interrupt */
1365 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1366 break;
1367 }
1368
1369 case TIM_CHANNEL_3:
1370 {
1371 /* Disable the TIM Capture/Compare 3 interrupt */
1372 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1373 break;
1374 }
1375
1376 case TIM_CHANNEL_4:
1377 {
1378 /* Disable the TIM Capture/Compare 4 interrupt */
1379 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1380 break;
1381 }
1382
1383 default:
1384 status = HAL_ERROR;
1385 break;
1386 }
1387
1388 if (status == HAL_OK)
1389 {
1390 /* Disable the complementary PWM output */
1391 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1392
1393 /* Disable the TIM Break interrupt (only if no more channel is active) */
1394 tmpccer = htim->Instance->CCER;
1395 if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
1396 {
1397 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
1398 }
1399
1400 /* Disable the Main Output */
1401 __HAL_TIM_MOE_DISABLE(htim);
1402
1403 /* Disable the Peripheral */
1404 __HAL_TIM_DISABLE(htim);
1405
1406 /* Set the TIM complementary channel state */
1407 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1408 }
1409
1410 /* Return function status */
1411 return status;
1412 }
1413
1414 /**
1415 * @brief Starts the TIM PWM signal generation in DMA mode on the
1416 * complementary output
1417 * @param htim TIM handle
1418 * @param Channel TIM Channel to be enabled
1419 * This parameter can be one of the following values:
1420 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1421 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1422 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1423 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1424 * @param pData The source Buffer address.
1425 * @param Length The length of data to be transferred from memory to TIM peripheral
1426 * @retval HAL status
1427 */
HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1428 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1429 uint16_t Length)
1430 {
1431 HAL_StatusTypeDef status = HAL_OK;
1432 uint32_t tmpsmcr;
1433
1434 /* Check the parameters */
1435 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1436
1437 /* Set the TIM complementary channel state */
1438 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1439 {
1440 return HAL_BUSY;
1441 }
1442 else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1443 {
1444 if ((pData == NULL) || (Length == 0U))
1445 {
1446 return HAL_ERROR;
1447 }
1448 else
1449 {
1450 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1451 }
1452 }
1453 else
1454 {
1455 return HAL_ERROR;
1456 }
1457
1458 switch (Channel)
1459 {
1460 case TIM_CHANNEL_1:
1461 {
1462 /* Set the DMA compare callbacks */
1463 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1464 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1465
1466 /* Set the DMA error callback */
1467 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
1468
1469 /* Enable the DMA channel */
1470 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1471 Length) != HAL_OK)
1472 {
1473 /* Return error status */
1474 return HAL_ERROR;
1475 }
1476 /* Enable the TIM Capture/Compare 1 DMA request */
1477 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1478 break;
1479 }
1480
1481 case TIM_CHANNEL_2:
1482 {
1483 /* Set the DMA compare callbacks */
1484 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1485 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1486
1487 /* Set the DMA error callback */
1488 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
1489
1490 /* Enable the DMA channel */
1491 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1492 Length) != HAL_OK)
1493 {
1494 /* Return error status */
1495 return HAL_ERROR;
1496 }
1497 /* Enable the TIM Capture/Compare 2 DMA request */
1498 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1499 break;
1500 }
1501
1502 case TIM_CHANNEL_3:
1503 {
1504 /* Set the DMA compare callbacks */
1505 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1506 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1507
1508 /* Set the DMA error callback */
1509 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
1510
1511 /* Enable the DMA channel */
1512 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1513 Length) != HAL_OK)
1514 {
1515 /* Return error status */
1516 return HAL_ERROR;
1517 }
1518 /* Enable the TIM Capture/Compare 3 DMA request */
1519 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1520 break;
1521 }
1522
1523 case TIM_CHANNEL_4:
1524 {
1525 /* Set the DMA compare callbacks */
1526 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1527 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1528
1529 /* Set the DMA error callback */
1530 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ;
1531
1532 /* Enable the DMA channel */
1533 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1534 Length) != HAL_OK)
1535 {
1536 /* Return error status */
1537 return HAL_ERROR;
1538 }
1539 /* Enable the TIM Capture/Compare 4 DMA request */
1540 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1541 break;
1542 }
1543
1544 default:
1545 status = HAL_ERROR;
1546 break;
1547 }
1548
1549 if (status == HAL_OK)
1550 {
1551 /* Enable the complementary PWM output */
1552 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1553
1554 /* Enable the Main Output */
1555 __HAL_TIM_MOE_ENABLE(htim);
1556
1557 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1558 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1559 {
1560 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1561 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1562 {
1563 __HAL_TIM_ENABLE(htim);
1564 }
1565 }
1566 else
1567 {
1568 __HAL_TIM_ENABLE(htim);
1569 }
1570 }
1571
1572 /* Return function status */
1573 return status;
1574 }
1575
1576 /**
1577 * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
1578 * output
1579 * @param htim TIM handle
1580 * @param Channel TIM Channel to be disabled
1581 * This parameter can be one of the following values:
1582 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1583 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1584 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1585 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1586 * @retval HAL status
1587 */
HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1588 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1589 {
1590 HAL_StatusTypeDef status = HAL_OK;
1591
1592 /* Check the parameters */
1593 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1594
1595 switch (Channel)
1596 {
1597 case TIM_CHANNEL_1:
1598 {
1599 /* Disable the TIM Capture/Compare 1 DMA request */
1600 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1601 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1602 break;
1603 }
1604
1605 case TIM_CHANNEL_2:
1606 {
1607 /* Disable the TIM Capture/Compare 2 DMA request */
1608 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1609 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1610 break;
1611 }
1612
1613 case TIM_CHANNEL_3:
1614 {
1615 /* Disable the TIM Capture/Compare 3 DMA request */
1616 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1617 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1618 break;
1619 }
1620
1621 case TIM_CHANNEL_4:
1622 {
1623 /* Disable the TIM Capture/Compare 4 DMA request */
1624 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1625 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1626 break;
1627 }
1628
1629 default:
1630 status = HAL_ERROR;
1631 break;
1632 }
1633
1634 if (status == HAL_OK)
1635 {
1636 /* Disable the complementary PWM output */
1637 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1638
1639 /* Disable the Main Output */
1640 __HAL_TIM_MOE_DISABLE(htim);
1641
1642 /* Disable the Peripheral */
1643 __HAL_TIM_DISABLE(htim);
1644
1645 /* Set the TIM complementary channel state */
1646 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1647 }
1648
1649 /* Return function status */
1650 return status;
1651 }
1652
1653 /**
1654 * @}
1655 */
1656
1657 /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
1658 * @brief Timer Complementary One Pulse functions
1659 *
1660 @verbatim
1661 ==============================================================================
1662 ##### Timer Complementary One Pulse functions #####
1663 ==============================================================================
1664 [..]
1665 This section provides functions allowing to:
1666 (+) Start the Complementary One Pulse generation.
1667 (+) Stop the Complementary One Pulse.
1668 (+) Start the Complementary One Pulse and enable interrupts.
1669 (+) Stop the Complementary One Pulse and disable interrupts.
1670
1671 @endverbatim
1672 * @{
1673 */
1674
1675 /**
1676 * @brief Starts the TIM One Pulse signal generation on the complementary
1677 * output.
1678 * @note OutputChannel must match the pulse output channel chosen when calling
1679 * @ref HAL_TIM_OnePulse_ConfigChannel().
1680 * @param htim TIM One Pulse handle
1681 * @param OutputChannel pulse output channel to enable
1682 * This parameter can be one of the following values:
1683 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1684 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1685 * @retval HAL status
1686 */
HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1687 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1688 {
1689 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1690 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
1691 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
1692 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
1693 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
1694
1695 /* Check the parameters */
1696 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1697
1698 /* Check the TIM channels state */
1699 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1700 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
1701 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1702 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
1703 {
1704 return HAL_ERROR;
1705 }
1706
1707 /* Set the TIM channels state */
1708 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1709 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1710 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1711 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1712
1713 /* Enable the complementary One Pulse output channel and the Input Capture channel */
1714 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
1715 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
1716
1717 /* Enable the Main Output */
1718 __HAL_TIM_MOE_ENABLE(htim);
1719
1720 /* Return function status */
1721 return HAL_OK;
1722 }
1723
1724 /**
1725 * @brief Stops the TIM One Pulse signal generation on the complementary
1726 * output.
1727 * @note OutputChannel must match the pulse output channel chosen when calling
1728 * @ref HAL_TIM_OnePulse_ConfigChannel().
1729 * @param htim TIM One Pulse handle
1730 * @param OutputChannel pulse output channel to disable
1731 * This parameter can be one of the following values:
1732 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1733 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1734 * @retval HAL status
1735 */
HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1736 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1737 {
1738 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1739
1740 /* Check the parameters */
1741 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1742
1743 /* Disable the complementary One Pulse output channel and the Input Capture channel */
1744 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
1745 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
1746
1747 /* Disable the Main Output */
1748 __HAL_TIM_MOE_DISABLE(htim);
1749
1750 /* Disable the Peripheral */
1751 __HAL_TIM_DISABLE(htim);
1752
1753 /* Set the TIM channels state */
1754 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1755 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1756 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1757 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1758
1759 /* Return function status */
1760 return HAL_OK;
1761 }
1762
1763 /**
1764 * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
1765 * complementary channel.
1766 * @note OutputChannel must match the pulse output channel chosen when calling
1767 * @ref HAL_TIM_OnePulse_ConfigChannel().
1768 * @param htim TIM One Pulse handle
1769 * @param OutputChannel pulse output channel to enable
1770 * This parameter can be one of the following values:
1771 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1772 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1773 * @retval HAL status
1774 */
HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1775 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1776 {
1777 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1778 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
1779 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
1780 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
1781 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
1782
1783 /* Check the parameters */
1784 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1785
1786 /* Check the TIM channels state */
1787 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1788 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
1789 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1790 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
1791 {
1792 return HAL_ERROR;
1793 }
1794
1795 /* Set the TIM channels state */
1796 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1797 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1798 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1799 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1800
1801 /* Enable the TIM Capture/Compare 1 interrupt */
1802 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1803
1804 /* Enable the TIM Capture/Compare 2 interrupt */
1805 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1806
1807 /* Enable the complementary One Pulse output channel and the Input Capture channel */
1808 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
1809 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
1810
1811 /* Enable the Main Output */
1812 __HAL_TIM_MOE_ENABLE(htim);
1813
1814 /* Return function status */
1815 return HAL_OK;
1816 }
1817
1818 /**
1819 * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
1820 * complementary channel.
1821 * @note OutputChannel must match the pulse output channel chosen when calling
1822 * @ref HAL_TIM_OnePulse_ConfigChannel().
1823 * @param htim TIM One Pulse handle
1824 * @param OutputChannel pulse output channel to disable
1825 * This parameter can be one of the following values:
1826 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1827 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1828 * @retval HAL status
1829 */
HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1830 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1831 {
1832 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1833
1834 /* Check the parameters */
1835 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1836
1837 /* Disable the TIM Capture/Compare 1 interrupt */
1838 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1839
1840 /* Disable the TIM Capture/Compare 2 interrupt */
1841 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1842
1843 /* Disable the complementary One Pulse output channel and the Input Capture channel */
1844 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
1845 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
1846
1847 /* Disable the Main Output */
1848 __HAL_TIM_MOE_DISABLE(htim);
1849
1850 /* Disable the Peripheral */
1851 __HAL_TIM_DISABLE(htim);
1852
1853 /* Set the TIM channels state */
1854 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1855 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1856 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1857 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1858
1859 /* Return function status */
1860 return HAL_OK;
1861 }
1862
1863 /**
1864 * @}
1865 */
1866
1867 /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
1868 * @brief Peripheral Control functions
1869 *
1870 @verbatim
1871 ==============================================================================
1872 ##### Peripheral Control functions #####
1873 ==============================================================================
1874 [..]
1875 This section provides functions allowing to:
1876 (+) Configure the commutation event in case of use of the Hall sensor interface.
1877 (+) Configure Output channels for OC and PWM mode.
1878
1879 (+) Configure Complementary channels, break features and dead time.
1880 (+) Configure Master synchronization.
1881 (+) Configure timer remapping capabilities.
1882 (+) Select timer input source.
1883 (+) Enable or disable channel grouping.
1884 (+) Configure Pulse on compare.
1885 (+) Configure Encoder index.
1886
1887 @endverbatim
1888 * @{
1889 */
1890
1891 /**
1892 * @brief Configure the TIM commutation event sequence.
1893 * @note This function is mandatory to use the commutation event in order to
1894 * update the configuration at each commutation detection on the TRGI input of the Timer,
1895 * the typical use of this feature is with the use of another Timer(interface Timer)
1896 * configured in Hall sensor interface, this interface Timer will generate the
1897 * commutation at its TRGO output (connected to Timer used in this function) each time
1898 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1899 * @param htim TIM handle
1900 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
1901 * This parameter can be one of the following values:
1902 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1903 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1904 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1905 * @arg TIM_TS_ITR3: Internal trigger 3 selected
1906 * @arg TIM_TS_ITR4: Internal trigger 4 selected (*)
1907 * @arg TIM_TS_ITR5: Internal trigger 5 selected
1908 * @arg TIM_TS_ITR6: Internal trigger 6 selected
1909 * @arg TIM_TS_ITR7: Internal trigger 7 selected
1910 * @arg TIM_TS_ITR8: Internal trigger 8 selected
1911 * @arg TIM_TS_ITR9: Internal trigger 9 selected (*)
1912 * @arg TIM_TS_ITR10: Internal trigger 10 selected
1913 * @arg TIM_TS_ITR11: Internal trigger 11 selected
1914 * @arg TIM_TS_NONE: No trigger is needed
1915 *
1916 * (*) Value not defined in all devices.
1917 *
1918 * @param CommutationSource the Commutation Event source
1919 * This parameter can be one of the following values:
1920 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1921 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1922 * @retval HAL status
1923 */
HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)1924 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
1925 uint32_t CommutationSource)
1926 {
1927 /* Check the parameters */
1928 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
1929 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
1930
1931 __HAL_LOCK(htim);
1932
1933 #if defined(TIM5) && defined(TIM20)
1934 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1935 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
1936 (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
1937 (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
1938 (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR9) ||
1939 (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11))
1940 #elif defined(TIM5)
1941 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1942 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
1943 (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
1944 (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
1945 (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11))
1946 #elif defined(TIM20)
1947 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1948 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
1949 (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) ||
1950 (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) ||
1951 (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR11))
1952 #else
1953 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1954 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
1955 (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) ||
1956 (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) ||
1957 (InputTrigger == TIM_TS_ITR11))
1958 #endif /* TIM5 && TIM20 */
1959 {
1960 /* Select the Input trigger */
1961 htim->Instance->SMCR &= ~TIM_SMCR_TS;
1962 htim->Instance->SMCR |= InputTrigger;
1963 }
1964
1965 /* Select the Capture Compare preload feature */
1966 htim->Instance->CR2 |= TIM_CR2_CCPC;
1967 /* Select the Commutation event source */
1968 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
1969 htim->Instance->CR2 |= CommutationSource;
1970
1971 /* Disable Commutation Interrupt */
1972 __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
1973
1974 /* Disable Commutation DMA request */
1975 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
1976
1977 __HAL_UNLOCK(htim);
1978
1979 return HAL_OK;
1980 }
1981
1982 /**
1983 * @brief Configure the TIM commutation event sequence with interrupt.
1984 * @note This function is mandatory to use the commutation event in order to
1985 * update the configuration at each commutation detection on the TRGI input of the Timer,
1986 * the typical use of this feature is with the use of another Timer(interface Timer)
1987 * configured in Hall sensor interface, this interface Timer will generate the
1988 * commutation at its TRGO output (connected to Timer used in this function) each time
1989 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1990 * @param htim TIM handle
1991 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
1992 * This parameter can be one of the following values:
1993 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1994 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1995 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1996 * @arg TIM_TS_ITR3: Internal trigger 3 selected
1997 * @arg TIM_TS_ITR4: Internal trigger 4 selected (*)
1998 * @arg TIM_TS_ITR5: Internal trigger 5 selected
1999 * @arg TIM_TS_ITR6: Internal trigger 6 selected
2000 * @arg TIM_TS_ITR7: Internal trigger 7 selected
2001 * @arg TIM_TS_ITR8: Internal trigger 8 selected
2002 * @arg TIM_TS_ITR9: Internal trigger 9 selected (*)
2003 * @arg TIM_TS_ITR10: Internal trigger 10 selected
2004 * @arg TIM_TS_ITR11: Internal trigger 11 selected
2005 * @arg TIM_TS_NONE: No trigger is needed
2006 *
2007 * (*) Value not defined in all devices.
2008 *
2009 * @param CommutationSource the Commutation Event source
2010 * This parameter can be one of the following values:
2011 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
2012 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
2013 * @retval HAL status
2014 */
HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)2015 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
2016 uint32_t CommutationSource)
2017 {
2018 /* Check the parameters */
2019 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
2020 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
2021
2022 __HAL_LOCK(htim);
2023
2024 #if defined(TIM5) && defined(TIM20)
2025 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
2026 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
2027 (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
2028 (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
2029 (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR9) ||
2030 (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11))
2031 #elif defined(TIM5)
2032 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
2033 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
2034 (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
2035 (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
2036 (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11))
2037 #elif defined(TIM20)
2038 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
2039 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
2040 (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) ||
2041 (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) ||
2042 (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR11))
2043 #else
2044 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
2045 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
2046 (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) ||
2047 (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) ||
2048 (InputTrigger == TIM_TS_ITR11))
2049 #endif /* TIM5 && TIM20 */
2050 {
2051 /* Select the Input trigger */
2052 htim->Instance->SMCR &= ~TIM_SMCR_TS;
2053 htim->Instance->SMCR |= InputTrigger;
2054 }
2055
2056 /* Select the Capture Compare preload feature */
2057 htim->Instance->CR2 |= TIM_CR2_CCPC;
2058 /* Select the Commutation event source */
2059 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
2060 htim->Instance->CR2 |= CommutationSource;
2061
2062 /* Disable Commutation DMA request */
2063 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
2064
2065 /* Enable the Commutation Interrupt */
2066 __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
2067
2068 __HAL_UNLOCK(htim);
2069
2070 return HAL_OK;
2071 }
2072
2073 /**
2074 * @brief Configure the TIM commutation event sequence with DMA.
2075 * @note This function is mandatory to use the commutation event in order to
2076 * update the configuration at each commutation detection on the TRGI input of the Timer,
2077 * the typical use of this feature is with the use of another Timer(interface Timer)
2078 * configured in Hall sensor interface, this interface Timer will generate the
2079 * commutation at its TRGO output (connected to Timer used in this function) each time
2080 * the TI1 of the Interface Timer detect a commutation at its input TI1.
2081 * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set
2082 * @param htim TIM handle
2083 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
2084 * This parameter can be one of the following values:
2085 * @arg TIM_TS_ITR0: Internal trigger 0 selected
2086 * @arg TIM_TS_ITR1: Internal trigger 1 selected
2087 * @arg TIM_TS_ITR2: Internal trigger 2 selected
2088 * @arg TIM_TS_ITR3: Internal trigger 3 selected
2089 * @arg TIM_TS_ITR4: Internal trigger 4 selected (*)
2090 * @arg TIM_TS_ITR5: Internal trigger 5 selected
2091 * @arg TIM_TS_ITR6: Internal trigger 6 selected
2092 * @arg TIM_TS_ITR7: Internal trigger 7 selected
2093 * @arg TIM_TS_ITR8: Internal trigger 8 selected
2094 * @arg TIM_TS_ITR9: Internal trigger 9 selected (*)
2095 * @arg TIM_TS_ITR10: Internal trigger 10 selected
2096 * @arg TIM_TS_ITR11: Internal trigger 11 selected
2097 * @arg TIM_TS_NONE: No trigger is needed
2098 *
2099 * (*) Value not defined in all devices.
2100 *
2101 * @param CommutationSource the Commutation Event source
2102 * This parameter can be one of the following values:
2103 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
2104 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
2105 * @retval HAL status
2106 */
HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)2107 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
2108 uint32_t CommutationSource)
2109 {
2110 /* Check the parameters */
2111 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
2112 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
2113
2114 __HAL_LOCK(htim);
2115
2116 #if defined(TIM5) && defined(TIM20)
2117 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
2118 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
2119 (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
2120 (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
2121 (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR9) ||
2122 (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11))
2123 #elif defined(TIM5)
2124 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
2125 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
2126 (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) ||
2127 (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) ||
2128 (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11))
2129 #elif defined(TIM20)
2130 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
2131 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
2132 (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) ||
2133 (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) ||
2134 (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR11))
2135 #else
2136 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
2137 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
2138 (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) ||
2139 (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) ||
2140 (InputTrigger == TIM_TS_ITR11))
2141 #endif /* TIM5 && TIM20 */
2142 {
2143 /* Select the Input trigger */
2144 htim->Instance->SMCR &= ~TIM_SMCR_TS;
2145 htim->Instance->SMCR |= InputTrigger;
2146 }
2147
2148 /* Select the Capture Compare preload feature */
2149 htim->Instance->CR2 |= TIM_CR2_CCPC;
2150 /* Select the Commutation event source */
2151 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
2152 htim->Instance->CR2 |= CommutationSource;
2153
2154 /* Enable the Commutation DMA Request */
2155 /* Set the DMA Commutation Callback */
2156 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
2157 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
2158 /* Set the DMA error callback */
2159 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
2160
2161 /* Disable Commutation Interrupt */
2162 __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
2163
2164 /* Enable the Commutation DMA Request */
2165 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
2166
2167 __HAL_UNLOCK(htim);
2168
2169 return HAL_OK;
2170 }
2171
2172 /**
2173 * @brief Configures the TIM in master mode.
2174 * @param htim TIM handle.
2175 * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
2176 * contains the selected trigger output (TRGO) and the Master/Slave
2177 * mode.
2178 * @retval HAL status
2179 */
HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef * htim,const TIM_MasterConfigTypeDef * sMasterConfig)2180 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
2181 const TIM_MasterConfigTypeDef *sMasterConfig)
2182 {
2183 uint32_t tmpcr2;
2184 uint32_t tmpsmcr;
2185
2186 /* Check the parameters */
2187 assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
2188 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
2189 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
2190
2191 /* Check input state */
2192 __HAL_LOCK(htim);
2193
2194 /* Change the handler state */
2195 htim->State = HAL_TIM_STATE_BUSY;
2196
2197 /* Get the TIMx CR2 register value */
2198 tmpcr2 = htim->Instance->CR2;
2199
2200 /* Get the TIMx SMCR register value */
2201 tmpsmcr = htim->Instance->SMCR;
2202
2203 /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
2204 if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
2205 {
2206 /* Check the parameters */
2207 assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
2208
2209 /* Clear the MMS2 bits */
2210 tmpcr2 &= ~TIM_CR2_MMS2;
2211 /* Select the TRGO2 source*/
2212 tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
2213 }
2214
2215 /* Reset the MMS Bits */
2216 tmpcr2 &= ~TIM_CR2_MMS;
2217 /* Select the TRGO source */
2218 tmpcr2 |= sMasterConfig->MasterOutputTrigger;
2219
2220 /* Update TIMx CR2 */
2221 htim->Instance->CR2 = tmpcr2;
2222
2223 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2224 {
2225 /* Reset the MSM Bit */
2226 tmpsmcr &= ~TIM_SMCR_MSM;
2227 /* Set master mode */
2228 tmpsmcr |= sMasterConfig->MasterSlaveMode;
2229
2230 /* Update TIMx SMCR */
2231 htim->Instance->SMCR = tmpsmcr;
2232 }
2233
2234 /* Change the htim state */
2235 htim->State = HAL_TIM_STATE_READY;
2236
2237 __HAL_UNLOCK(htim);
2238
2239 return HAL_OK;
2240 }
2241
2242 /**
2243 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
2244 * and the AOE(automatic output enable).
2245 * @param htim TIM handle
2246 * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
2247 * contains the BDTR Register configuration information for the TIM peripheral.
2248 * @note Interrupts can be generated when an active level is detected on the
2249 * break input, the break 2 input or the system break input. Break
2250 * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
2251 * @retval HAL status
2252 */
HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef * htim,const TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)2253 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
2254 const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
2255 {
2256 /* Keep this variable initialized to 0 as it is used to configure BDTR register */
2257 uint32_t tmpbdtr = 0U;
2258
2259 /* Check the parameters */
2260 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2261 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
2262 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
2263 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
2264 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
2265 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
2266 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
2267 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
2268 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
2269 assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
2270
2271 /* Check input state */
2272 __HAL_LOCK(htim);
2273
2274 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
2275 the OSSI State, the dead time value and the Automatic Output Enable Bit */
2276
2277 /* Set the BDTR bits */
2278 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
2279 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
2280 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
2281 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
2282 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
2283 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
2284 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
2285 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
2286 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
2287
2288 if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
2289 {
2290 /* Check the parameters */
2291 assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
2292 assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
2293 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
2294 assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
2295
2296 /* Set the BREAK2 input related BDTR bits */
2297 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
2298 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
2299 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
2300 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
2301 }
2302
2303 /* Set TIMx_BDTR */
2304 htim->Instance->BDTR = tmpbdtr;
2305
2306 __HAL_UNLOCK(htim);
2307
2308 return HAL_OK;
2309 }
2310
2311 /**
2312 * @brief Configures the break input source.
2313 * @param htim TIM handle.
2314 * @param BreakInput Break input to configure
2315 * This parameter can be one of the following values:
2316 * @arg TIM_BREAKINPUT_BRK: Timer break input
2317 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
2318 * @param sBreakInputConfig Break input source configuration
2319 * @retval HAL status
2320 */
HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef * htim,uint32_t BreakInput,const TIMEx_BreakInputConfigTypeDef * sBreakInputConfig)2321 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
2322 uint32_t BreakInput,
2323 const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
2324 {
2325 HAL_StatusTypeDef status = HAL_OK;
2326 uint32_t tmporx;
2327 uint32_t bkin_enable_mask;
2328 uint32_t bkin_polarity_mask;
2329 uint32_t bkin_enable_bitpos;
2330 uint32_t bkin_polarity_bitpos;
2331
2332 /* Check the parameters */
2333 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2334 assert_param(IS_TIM_BREAKINPUT(BreakInput));
2335 assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
2336 assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
2337 assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
2338
2339 /* Check input state */
2340 __HAL_LOCK(htim);
2341
2342 switch (sBreakInputConfig->Source)
2343 {
2344 case TIM_BREAKINPUTSOURCE_BKIN:
2345 {
2346 bkin_enable_mask = TIM1_AF1_BKINE;
2347 bkin_enable_bitpos = TIM1_AF1_BKINE_Pos;
2348 bkin_polarity_mask = TIM1_AF1_BKINP;
2349 bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos;
2350 break;
2351 }
2352 case TIM_BREAKINPUTSOURCE_COMP1:
2353 {
2354 bkin_enable_mask = TIM1_AF1_BKCMP1E;
2355 bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos;
2356 bkin_polarity_mask = TIM1_AF1_BKCMP1P;
2357 bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos;
2358 break;
2359 }
2360 #if defined (COMP2)
2361 case TIM_BREAKINPUTSOURCE_COMP2:
2362 {
2363 bkin_enable_mask = TIM1_AF1_BKCMP2E;
2364 bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos;
2365 bkin_polarity_mask = TIM1_AF1_BKCMP2P;
2366 bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos;
2367 break;
2368 }
2369 #endif /* COMP2 */
2370 case TIM_BREAKINPUTSOURCE_COMP3:
2371 {
2372 bkin_enable_mask = TIM1_AF1_BKCMP3E;
2373 bkin_enable_bitpos = TIM1_AF1_BKCMP3E_Pos;
2374 bkin_polarity_mask = TIM1_AF1_BKCMP3P;
2375 bkin_polarity_bitpos = TIM1_AF1_BKCMP3P_Pos;
2376 break;
2377 }
2378 #if defined (COMP4)
2379 case TIM_BREAKINPUTSOURCE_COMP4:
2380 {
2381 bkin_enable_mask = TIM1_AF1_BKCMP4E;
2382 bkin_enable_bitpos = TIM1_AF1_BKCMP4E_Pos;
2383 bkin_polarity_mask = TIM1_AF1_BKCMP4P;
2384 bkin_polarity_bitpos = TIM1_AF1_BKCMP4P_Pos;
2385 break;
2386 }
2387 #endif /* COMP4 */
2388 #if defined (COMP5)
2389 case TIM_BREAKINPUTSOURCE_COMP5:
2390 {
2391 bkin_enable_mask = TIM1_AF1_BKCMP5E;
2392 bkin_enable_bitpos = TIM1_AF1_BKCMP5E_Pos;
2393 /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its default value 0 */
2394 bkin_polarity_mask = 0U;
2395 bkin_polarity_bitpos = 0U;
2396 break;
2397 }
2398 #endif /* COMP5 */
2399 #if defined (COMP6)
2400 case TIM_BREAKINPUTSOURCE_COMP6:
2401 {
2402 bkin_enable_mask = TIM1_AF1_BKCMP6E;
2403 bkin_enable_bitpos = TIM1_AF1_BKCMP6E_Pos;
2404 /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its default value 0 */
2405 bkin_polarity_mask = 0U;
2406 bkin_polarity_bitpos = 0U;
2407 break;
2408 }
2409 #endif /* COMP7 */
2410 #if defined (COMP7)
2411 case TIM_BREAKINPUTSOURCE_COMP7:
2412 {
2413 bkin_enable_mask = TIM1_AF1_BKCMP7E;
2414 bkin_enable_bitpos = TIM1_AF1_BKCMP7E_Pos;
2415 /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its default value 0 */
2416 bkin_polarity_mask = 0U;
2417 bkin_polarity_bitpos = 0U;
2418 break;
2419 }
2420 #endif /* COMP7 */
2421
2422 default:
2423 {
2424 bkin_enable_mask = 0U;
2425 bkin_polarity_mask = 0U;
2426 bkin_enable_bitpos = 0U;
2427 bkin_polarity_bitpos = 0U;
2428 break;
2429 }
2430 }
2431
2432 switch (BreakInput)
2433 {
2434 case TIM_BREAKINPUT_BRK:
2435 {
2436 /* Get the TIMx_AF1 register value */
2437 tmporx = htim->Instance->AF1;
2438
2439 /* Enable the break input */
2440 tmporx &= ~bkin_enable_mask;
2441 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
2442
2443 /* Set the break input polarity */
2444 tmporx &= ~bkin_polarity_mask;
2445 tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
2446
2447 /* Set TIMx_AF1 */
2448 htim->Instance->AF1 = tmporx;
2449 break;
2450 }
2451 case TIM_BREAKINPUT_BRK2:
2452 {
2453 /* Get the TIMx_AF2 register value */
2454 tmporx = htim->Instance->AF2;
2455
2456 /* Enable the break input */
2457 tmporx &= ~bkin_enable_mask;
2458 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
2459
2460 /* Set the break input polarity */
2461 tmporx &= ~bkin_polarity_mask;
2462 tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
2463
2464 /* Set TIMx_AF2 */
2465 htim->Instance->AF2 = tmporx;
2466 break;
2467 }
2468 default:
2469 status = HAL_ERROR;
2470 break;
2471 }
2472
2473 __HAL_UNLOCK(htim);
2474
2475 return status;
2476 }
2477
2478 /**
2479 * @brief Configures the TIMx Remapping input capabilities.
2480 * @param htim TIM handle.
2481 * @param Remap specifies the TIM remapping source.
2482 * For TIM1, the parameter can take one of the following values:
2483 * @arg TIM_TIM1_ETR_GPIO TIM1 ETR is connected to GPIO
2484 * @arg TIM_TIM1_ETR_COMP1 TIM1 ETR is connected to COMP1 output
2485 * @arg TIM_TIM1_ETR_COMP2 TIM1 ETR is connected to COMP2 output
2486 * @arg TIM_TIM1_ETR_COMP3 TIM1 ETR is connected to COMP3 output
2487 * @arg TIM_TIM1_ETR_COMP4 TIM1 ETR is connected to COMP4 output
2488 * @arg TIM_TIM1_ETR_COMP5 TIM1 ETR is connected to COMP5 output (*)
2489 * @arg TIM_TIM1_ETR_COMP6 TIM1 ETR is connected to COMP6 output (*)
2490 * @arg TIM_TIM1_ETR_COMP7 TIM1 ETR is connected to COMP7 output (*)
2491 * @arg TIM_TIM1_ETR_ADC1_AWD1 TIM1 ETR is connected to ADC1 AWD1
2492 * @arg TIM_TIM1_ETR_ADC1_AWD2 TIM1 ETR is connected to ADC1 AWD2
2493 * @arg TIM_TIM1_ETR_ADC1_AWD3 TIM1 ETR is connected to ADC1 AWD3
2494 * @arg TIM_TIM1_ETR_ADC4_AWD1 TIM1 ETR is connected to ADC4 AWD1 (*)
2495 * @arg TIM_TIM1_ETR_ADC4_AWD2 TIM1 ETR is connected to ADC4 AWD2 (*)
2496 * @arg TIM_TIM1_ETR_ADC4_AWD3 TIM1 ETR is connected to ADC4 AWD3 (*)
2497 *
2498 * For TIM2, the parameter can take one of the following values:
2499 * @arg TIM_TIM2_ETR_GPIO TIM2 ETR is connected to GPIO
2500 * @arg TIM_TIM2_ETR_COMP1 TIM2 ETR is connected to COMP1 output
2501 * @arg TIM_TIM2_ETR_COMP2 TIM2 ETR is connected to COMP2 output
2502 * @arg TIM_TIM2_ETR_COMP3 TIM2 ETR is connected to COMP3 output
2503 * @arg TIM_TIM2_ETR_COMP4 TIM2 ETR is connected to COMP4 output
2504 * @arg TIM_TIM2_ETR_COMP5 TIM2 ETR is connected to COMP5 output (*)
2505 * @arg TIM_TIM2_ETR_COMP6 TIM2 ETR is connected to COMP6 output (*)
2506 * @arg TIM_TIM2_ETR_COMP7 TIM2 ETR is connected to COMP7 output (*)
2507 * @arg TIM_TIM2_ETR_TIM3_ETR TIM2 ETR is connected to TIM3 ETR pin
2508 * @arg TIM_TIM2_ETR_TIM4_ETR TIM2 ETR is connected to TIM4 ETR pin
2509 * @arg TIM_TIM2_ETR_TIM5_ETR TIM2 ETR is connected to TIM5 ETR pin (*)
2510 * @arg TIM_TIM2_ETR_LSE
2511 *
2512 * For TIM3, the parameter can take one of the following values:
2513 * @arg TIM_TIM3_ETR_GPIO TIM3 ETR is connected to GPIO
2514 * @arg TIM_TIM3_ETR_COMP1 TIM3 ETR is connected to COMP1 output
2515 * @arg TIM_TIM3_ETR_COMP2 TIM3 ETR is connected to COMP2 output
2516 * @arg TIM_TIM3_ETR_COMP3 TIM3 ETR is connected to COMP3 output
2517 * @arg TIM_TIM3_ETR_COMP4 TIM3 ETR is connected to COMP4 output
2518 * @arg TIM_TIM3_ETR_COMP5 TIM3 ETR is connected to COMP5 output (*)
2519 * @arg TIM_TIM3_ETR_COMP6 TIM3 ETR is connected to COMP6 output (*)
2520 * @arg TIM_TIM3_ETR_COMP7 TIM3 ETR is connected to COMP7 output (*)
2521 * @arg TIM_TIM3_ETR_TIM2_ETR TIM3 ETR is connected to TIM2 ETR pin
2522 * @arg TIM_TIM3_ETR_TIM4_ETR TIM3 ETR is connected to TIM4 ETR pin
2523 * @arg TIM_TIM3_ETR_ADC2_AWD1 TIM3 ETR is connected to ADC2 AWD1
2524 * @arg TIM_TIM3_ETR_ADC2_AWD2 TIM3 ETR is connected to ADC2 AWD2
2525 * @arg TIM_TIM3_ETR_ADC2_AWD3 TIM3 ETR is connected to ADC2 AWD3
2526 *
2527 * For TIM4, the parameter can take one of the following values:
2528 * @arg TIM_TIM4_ETR_GPIO TIM4 ETR is connected to GPIO
2529 * @arg TIM_TIM4_ETR_COMP1 TIM4 ETR is connected to COMP1 output
2530 * @arg TIM_TIM4_ETR_COMP2 TIM4 ETR is connected to COMP2 output
2531 * @arg TIM_TIM4_ETR_COMP3 TIM4 ETR is connected to COMP3 output
2532 * @arg TIM_TIM4_ETR_COMP4 TIM4 ETR is connected to COMP4 output
2533 * @arg TIM_TIM4_ETR_COMP5 TIM4 ETR is connected to COMP5 output (*)
2534 * @arg TIM_TIM4_ETR_COMP6 TIM4 ETR is connected to COMP6 output (*)
2535 * @arg TIM_TIM4_ETR_COMP7 TIM4 ETR is connected to COMP7 output (*)
2536 * @arg TIM_TIM4_ETR_TIM3_ETR TIM4 ETR is connected to TIM3 ETR pin
2537 * @arg TIM_TIM4_ETR_TIM5_ETR TIM4 ETR is connected to TIM5 ETR pin (*)
2538 *
2539 * For TIM5, the parameter can take one of the following values: (**)
2540 * @arg TIM_TIM5_ETR_GPIO TIM5 ETR is connected to GPIO (*)
2541 * @arg TIM_TIM5_ETR_COMP1 TIM5 ETR is connected to COMP1 output (*)
2542 * @arg TIM_TIM5_ETR_COMP2 TIM5 ETR is connected to COMP2 output (*)
2543 * @arg TIM_TIM5_ETR_COMP3 TIM5 ETR is connected to COMP3 output (*)
2544 * @arg TIM_TIM5_ETR_COMP4 TIM5 ETR is connected to COMP4 output (*)
2545 * @arg TIM_TIM5_ETR_COMP5 TIM5 ETR is connected to COMP5 output (*)
2546 * @arg TIM_TIM5_ETR_COMP6 TIM5 ETR is connected to COMP6 output (*)
2547 * @arg TIM_TIM5_ETR_COMP7 TIM5 ETR is connected to COMP7 output (*)
2548 * @arg TIM_TIM5_ETR_TIM2_ETR TIM5 ETR is connected to TIM2 ETR pin (*)
2549 * @arg TIM_TIM5_ETR_TIM3_ETR TIM5 ETR is connected to TIM3 ETR pin (*)
2550 *
2551 * For TIM8, the parameter can take one of the following values:
2552 * @arg TIM_TIM8_ETR_GPIO TIM8 ETR is connected to GPIO
2553 * @arg TIM_TIM8_ETR_COMP1 TIM8 ETR is connected to COMP1 output
2554 * @arg TIM_TIM8_ETR_COMP2 TIM8 ETR is connected to COMP2 output
2555 * @arg TIM_TIM8_ETR_COMP3 TIM8 ETR is connected to COMP3 output
2556 * @arg TIM_TIM8_ETR_COMP4 TIM8 ETR is connected to COMP4 output
2557 * @arg TIM_TIM8_ETR_COMP5 TIM8 ETR is connected to COMP5 output (*)
2558 * @arg TIM_TIM8_ETR_COMP6 TIM8 ETR is connected to COMP6 output (*)
2559 * @arg TIM_TIM8_ETR_COMP7 TIM8 ETR is connected to COMP7 output (*)
2560 * @arg TIM_TIM8_ETR_ADC2_AWD1 TIM8 ETR is connected to ADC2 AWD1
2561 * @arg TIM_TIM8_ETR_ADC2_AWD2 TIM8 ETR is connected to ADC2 AWD2
2562 * @arg TIM_TIM8_ETR_ADC2_AWD3 TIM8 ETR is connected to ADC2 AWD3
2563 * @arg TIM_TIM8_ETR_ADC3_AWD1 TIM8 ETR is connected to ADC3 AWD1 (*)
2564 * @arg TIM_TIM8_ETR_ADC3_AWD2 TIM8 ETR is connected to ADC3 AWD2 (*)
2565 * @arg TIM_TIM8_ETR_ADC3_AWD3 TIM8 ETR is connected to ADC3 AWD3 (*)
2566 *
2567 * For TIM20, the parameter can take one of the following values: (**)
2568 * @arg TIM_TIM20_ETR_GPIO TIM20 ETR is connected to GPIO
2569 * @arg TIM_TIM20_ETR_COMP1 TIM20 ETR is connected to COMP1 output (*)
2570 * @arg TIM_TIM20_ETR_COMP2 TIM20 ETR is connected to COMP2 output (*)
2571 * @arg TIM_TIM20_ETR_COMP3 TIM20 ETR is connected to COMP3 output (*)
2572 * @arg TIM_TIM20_ETR_COMP4 TIM20 ETR is connected to COMP4 output (*)
2573 * @arg TIM_TIM20_ETR_COMP5 TIM20 ETR is connected to COMP5 output (*)
2574 * @arg TIM_TIM20_ETR_COMP6 TIM20 ETR is connected to COMP6 output (*)
2575 * @arg TIM_TIM20_ETR_COMP7 TIM20 ETR is connected to COMP7 output (*)
2576 * @arg TIM_TIM20_ETR_ADC3_AWD1 TIM20 ETR is connected to ADC3 AWD1 (*)
2577 * @arg TIM_TIM20_ETR_ADC3_AWD2 TIM20 ETR is connected to ADC3 AWD2 (*)
2578 * @arg TIM_TIM20_ETR_ADC3_AWD3 TIM20 ETR is connected to ADC3 AWD3 (*)
2579 * @arg TIM_TIM20_ETR_ADC5_AWD1 TIM20 ETR is connected to ADC5 AWD1 (*)
2580 * @arg TIM_TIM20_ETR_ADC5_AWD2 TIM20 ETR is connected to ADC5 AWD2 (*)
2581 * @arg TIM_TIM20_ETR_ADC5_AWD3 TIM20 ETR is connected to ADC5 AWD3 (*)
2582 *
2583 * (*) Value not defined in all devices. \n
2584 * (**) Register not available in all devices.
2585 *
2586 * @retval HAL status
2587 */
HAL_TIMEx_RemapConfig(TIM_HandleTypeDef * htim,uint32_t Remap)2588 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
2589 {
2590 /* Check parameters */
2591 assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
2592 assert_param(IS_TIM_REMAP(Remap));
2593
2594 __HAL_LOCK(htim);
2595
2596 MODIFY_REG(htim->Instance->AF1, TIM1_AF1_ETRSEL_Msk, Remap);
2597
2598 __HAL_UNLOCK(htim);
2599
2600 return HAL_OK;
2601 }
2602
2603 /**
2604 * @brief Select the timer input source
2605 * @param htim TIM handle.
2606 * @param Channel specifies the TIM Channel
2607 * This parameter can be one of the following values:
2608 * @arg TIM_CHANNEL_1: TI1 input channel
2609 * @arg TIM_CHANNEL_2: TI2 input channel
2610 * @arg TIM_CHANNEL_3: TI3 input channel
2611 * @arg TIM_CHANNEL_4: TI4 input channel
2612 * @param TISelection specifies the timer input source
2613 * For TIM1 this parameter can be one of the following values:
2614 * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO
2615 * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output
2616 * @arg TIM_TIM1_TI1_COMP2: TIM1 TI1 is connected to COMP2 output
2617 * @arg TIM_TIM1_TI1_COMP3: TIM1 TI1 is connected to COMP3 output
2618 * @arg TIM_TIM1_TI1_COMP4: TIM1 TI1 is connected to COMP4 output
2619 *
2620 * For TIM2 this parameter can be one of the following values:
2621 * @arg TIM_TIM2_TI1_GPIO: TIM2 TI1 is connected to GPIO
2622 * @arg TIM_TIM2_TI1_COMP1: TIM2 TI1 is connected to COMP1 output
2623 * @arg TIM_TIM2_TI1_COMP2: TIM2 TI1 is connected to COMP2 output
2624 * @arg TIM_TIM2_TI1_COMP3: TIM2 TI1 is connected to COMP3 output
2625 * @arg TIM_TIM2_TI1_COMP4: TIM2 TI1 is connected to COMP4 output
2626 * @arg TIM_TIM2_TI1_COMP5: TIM2 TI1 is connected to COMP5 output (*)
2627 *
2628 * @arg TIM_TIM2_TI2_GPIO: TIM1 TI2 is connected to GPIO
2629 * @arg TIM_TIM2_TI2_COMP1: TIM2 TI2 is connected to COMP1 output
2630 * @arg TIM_TIM2_TI2_COMP2: TIM2 TI2 is connected to COMP2 output
2631 * @arg TIM_TIM2_TI2_COMP3: TIM2 TI2 is connected to COMP3 output
2632 * @arg TIM_TIM2_TI2_COMP4: TIM2 TI2 is connected to COMP4 output
2633 * @arg TIM_TIM2_TI2_COMP6: TIM2 TI2 is connected to COMP6 output (*)
2634 *
2635 * @arg TIM_TIM2_TI3_GPIO: TIM2 TI3 is connected to GPIO
2636 * @arg TIM_TIM2_TI3_COMP4: TIM2 TI3 is connected to COMP4 output
2637 *
2638 * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO
2639 * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output
2640 * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output
2641 *
2642 * For TIM3 this parameter can be one of the following values:
2643 * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO
2644 * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output
2645 * @arg TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output
2646 * @arg TIM_TIM3_TI1_COMP3: TIM3 TI1 is connected to COMP3 output
2647 * @arg TIM_TIM3_TI1_COMP4: TIM3 TI1 is connected to COMP4 output
2648 * @arg TIM_TIM3_TI1_COMP5: TIM3 TI1 is connected to COMP5 output (*)
2649 * @arg TIM_TIM3_TI1_COMP6: TIM3 TI1 is connected to COMP6 output (*)
2650 * @arg TIM_TIM3_TI1_COMP7: TIM3 TI1 is connected to COMP7 output (*)
2651 *
2652 * @arg TIM_TIM3_TI2_GPIO: TIM3 TI2 is connected to GPIO
2653 * @arg TIM_TIM3_TI2_COMP1: TIM3 TI2 is connected to COMP1 output
2654 * @arg TIM_TIM3_TI2_COMP2: TIM3 TI2 is connected to COMP2 output
2655 * @arg TIM_TIM3_TI2_COMP3: TIM3 TI2 is connected to COMP3 output
2656 * @arg TIM_TIM3_TI2_COMP4: TIM3 TI2 is connected to COMP4 output
2657 * @arg TIM_TIM3_TI2_COMP5: TIM3 TI2 is connected to COMP5 output (*)
2658 * @arg TIM_TIM3_TI2_COMP6: TIM3 TI2 is connected to COMP6 output (*)
2659 * @arg TIM_TIM3_TI2_COMP7: TIM3 TI2 is connected to COMP7 output (*)
2660 *
2661 * @arg TIM_TIM3_TI3_GPIO: TIM3 TI3 is connected to GPIO
2662 * @arg TIM_TIM3_TI3_COMP3: TIM3 TI3 is connected to COMP3 output
2663 *
2664 * For TIM4 this parameter can be one of the following values:
2665 * @arg TIM_TIM4_TI1_GPIO: TIM4 TI1 is connected to GPIO
2666 * @arg TIM_TIM4_TI1_COMP1: TIM4 TI1 is connected to COMP1 output
2667 * @arg TIM_TIM4_TI1_COMP2: TIM4 TI1 is connected to COMP2 output
2668 * @arg TIM_TIM4_TI1_COMP3: TIM4 TI1 is connected to COMP3 output
2669 * @arg TIM_TIM4_TI1_COMP4: TIM4 TI1 is connected to COMP4 output
2670 * @arg TIM_TIM4_TI1_COMP5: TIM4 TI1 is connected to COMP5 output (*)
2671 * @arg TIM_TIM4_TI1_COMP6: TIM4 TI1 is connected to COMP6 output (*)
2672 * @arg TIM_TIM4_TI1_COMP7: TIM4 TI1 is connected to COMP7 output (*)
2673 *
2674 * @arg TIM_TIM4_TI2_GPIO: TIM4 TI2 is connected to GPIO
2675 * @arg TIM_TIM4_TI2_COMP1: TIM4 TI2 is connected to COMP1 output
2676 * @arg TIM_TIM4_TI2_COMP2: TIM4 TI2 is connected to COMP2 output
2677 * @arg TIM_TIM4_TI2_COMP3: TIM4 TI2 is connected to COMP3 output
2678 * @arg TIM_TIM4_TI2_COMP4: TIM4 TI2 is connected to COMP4 output
2679 * @arg TIM_TIM4_TI2_COMP5: TIM4 TI2 is connected to COMP5 output (*)
2680 * @arg TIM_TIM4_TI2_COMP6: TIM4 TI2 is connected to COMP6 output (*)
2681 * @arg TIM_TIM4_TI2_COMP7: TIM4 TI2 is connected to COMP7 output (*)
2682 *
2683 * @arg TIM_TIM4_TI3_GPIO: TIM4 TI3 is connected to GPIO
2684 * @arg TIM_TIM4_TI3_COMP5: TIM4 TI3 is connected to COMP5 output (*)
2685 *
2686 * @arg TIM_TIM4_TI4_GPIO: TIM4 TI4 is connected to GPIO
2687 * @arg TIM_TIM4_TI4_COMP6: TIM4 TI4 is connected to COMP6 output (*)
2688 *
2689 * For TIM5 this parameter can be one of the following values: (**)
2690 * @arg TIM_TIM5_TI1_GPIO: TIM5 TI1 is connected to GPIO
2691 * @arg TIM_TIM5_TI1_LSI: TIM5 TI1 is connected to LSI clock (*)
2692 * @arg TIM_TIM5_TI1_LSE: TIM5 TI1 is connected to LSE clock (*)
2693 * @arg TIM_TIM5_TI1_RTC_WK: TIM5 TI1 is connected to RTC Wakeup (*)
2694 * @arg TIM_TIM5_TI1_COMP1: TIM5 TI1 is connected to COMP1 output (*)
2695 * @arg TIM_TIM5_TI1_COMP2: TIM5 TI1 is connected to COMP2 output (*)
2696 * @arg TIM_TIM5_TI1_COMP3: TIM5 TI1 is connected to COMP3 output (*)
2697 * @arg TIM_TIM5_TI1_COMP4: TIM5 TI1 is connected to COMP4 output (*)
2698 * @arg TIM_TIM5_TI1_COMP5: TIM5 TI1 is connected to COMP5 output (*)
2699 * @arg TIM_TIM5_TI1_COMP6: TIM5 TI1 is connected to COMP6 output (*)
2700 * @arg TIM_TIM5_TI1_COMP7: TIM5 TI1 is connected to COMP7 output (*)
2701 *
2702 * @arg TIM_TIM5_TI2_GPIO: TIM5 TI2 is connected to GPIO
2703 * @arg TIM_TIM5_TI2_COMP1: TIM5 TI2 is connected to COMP1 output
2704 * @arg TIM_TIM5_TI2_COMP2: TIM5 TI2 is connected to COMP2 output
2705 * @arg TIM_TIM5_TI2_COMP3: TIM5 TI2 is connected to COMP3 output
2706 * @arg TIM_TIM5_TI2_COMP4: TIM5 TI2 is connected to COMP4 output
2707 * @arg TIM_TIM5_TI2_COMP5: TIM5 TI2 is connected to COMP5 output (*)
2708 * @arg TIM_TIM5_TI2_COMP6: TIM5 TI2 is connected to COMP6 output (*)
2709 * @arg TIM_TIM5_TI2_COMP7: TIM5 TI2 is connected to COMP7 output (*)
2710 *
2711 * For TIM8 this parameter can be one of the following values:
2712 * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO
2713 * @arg TIM_TIM8_TI1_COMP1: TIM8 TI1 is connected to COMP1 output
2714 * @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output
2715 * @arg TIM_TIM8_TI1_COMP3: TIM8 TI1 is connected to COMP3 output
2716 * @arg TIM_TIM8_TI1_COMP4: TIM8 TI1 is connected to COMP4 output
2717 *
2718 * For TIM15 this parameter can be one of the following values:
2719 * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO
2720 * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE clock
2721 * @arg TIM_TIM15_TI1_COMP1: TIM15 TI1 is connected to COMP1 output
2722 * @arg TIM_TIM15_TI1_COMP2: TIM15 TI1 is connected to COMP2 output
2723 * @arg TIM_TIM15_TI1_COMP5: TIM15 TI1 is connected to COMP5 output (*)
2724 * @arg TIM_TIM15_TI1_COMP7: TIM15 TI1 is connected to COMP7 output (*)
2725 *
2726 * @arg TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO
2727 * @arg TIM_TIM15_TI2_COMP2: TIM15 TI2 is connected to COMP2 output
2728 * @arg TIM_TIM15_TI2_COMP3: TIM15 TI2 is connected to COMP3 output
2729 * @arg TIM_TIM15_TI2_COMP6: TIM15 TI2 is connected to COMP6 output (*)
2730 * @arg TIM_TIM15_TI2_COMP7: TIM15 TI2 is connected to COMP7 output (*)
2731 *
2732 * For TIM16 this parameter can be one of the following values:
2733 * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
2734 * @arg TIM_TIM16_TI1_COMP6: TIM16 TI1 is connected to COMP6 output (*)
2735 * @arg TIM_TIM16_TI1_MCO: TIM15 TI1 is connected to MCO output
2736 * @arg TIM_TIM16_TI1_HSE_32: TIM15 TI1 is connected to HSE div 32
2737 * @arg TIM_TIM16_TI1_RTC_WK: TIM15 TI1 is connected to RTC wakeup
2738 * @arg TIM_TIM16_TI1_LSE: TIM15 TI1 is connected to LSE clock
2739 * @arg TIM_TIM16_TI1_LSI: TIM15 TI1 is connected to LSI clock
2740 *
2741 * For TIM17 this parameter can be one of the following values:
2742 * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO
2743 * @arg TIM_TIM17_TI1_COMP5: TIM17 TI1 is connected to COMP5 output (*)
2744 * @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO output
2745 * @arg TIM_TIM17_TI1_HSE_32: TIM17 TI1 is connected to HSE div 32
2746 * @arg TIM_TIM17_TI1_RTC_WK: TIM17 TI1 is connected to RTC wakeup
2747 * @arg TIM_TIM17_TI1_LSE: TIM17 TI1 is connected to LSE clock
2748 * @arg TIM_TIM17_TI1_LSI: TIM17 TI1 is connected to LSI clock
2749
2750 * For TIM20 this parameter can be one of the following values: (**)
2751 * @arg TIM_TIM20_TI1_GPIO: TIM20 TI1 is connected to GPIO
2752 * @arg TIM_TIM20_TI1_COMP1: TIM20 TI1 is connected to COMP1 output (*)
2753 * @arg TIM_TIM20_TI1_COMP2: TIM20 TI1 is connected to COMP2 output (*)
2754 * @arg TIM_TIM20_TI1_COMP3: TIM20 TI1 is connected to COMP3 output (*)
2755 * @arg TIM_TIM20_TI1_COMP4: TIM20 TI1 is connected to COMP4 output (*)
2756 *
2757 * (*) Value not defined in all devices. \n
2758 * (**) Register not available in all devices.
2759 *
2760 * @retval HAL status
2761 */
HAL_TIMEx_TISelection(TIM_HandleTypeDef * htim,uint32_t TISelection,uint32_t Channel)2762 HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
2763 {
2764 HAL_StatusTypeDef status = HAL_OK;
2765
2766 /* Check parameters */
2767 assert_param(IS_TIM_TISEL_TIX_INSTANCE(htim->Instance, Channel));
2768 assert_param(IS_TIM_TISEL(TISelection));
2769
2770 __HAL_LOCK(htim);
2771
2772 switch (Channel)
2773 {
2774 case TIM_CHANNEL_1:
2775 MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection);
2776
2777 /* If required, set OR bit to request HSE/32 clock */
2778 if (IS_TIM_HSE32_INSTANCE(htim->Instance))
2779 {
2780 SET_BIT(htim->Instance->OR, TIM_OR_HSE32EN);
2781 }
2782 else
2783 {
2784 CLEAR_BIT(htim->Instance->OR, TIM_OR_HSE32EN);
2785 }
2786 break;
2787 case TIM_CHANNEL_2:
2788 MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection);
2789 break;
2790 case TIM_CHANNEL_3:
2791 MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI3SEL, TISelection);
2792 break;
2793 case TIM_CHANNEL_4:
2794 MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI4SEL, TISelection);
2795 break;
2796 default:
2797 status = HAL_ERROR;
2798 break;
2799 }
2800
2801 __HAL_UNLOCK(htim);
2802
2803 return status;
2804 }
2805
2806 /**
2807 * @brief Group channel 5 and channel 1, 2 or 3
2808 * @param htim TIM handle.
2809 * @param Channels specifies the reference signal(s) the OC5REF is combined with.
2810 * This parameter can be any combination of the following values:
2811 * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
2812 * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
2813 * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
2814 * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
2815 * @retval HAL status
2816 */
HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef * htim,uint32_t Channels)2817 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
2818 {
2819 /* Check parameters */
2820 assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
2821 assert_param(IS_TIM_GROUPCH5(Channels));
2822
2823 /* Process Locked */
2824 __HAL_LOCK(htim);
2825
2826 htim->State = HAL_TIM_STATE_BUSY;
2827
2828 /* Clear GC5Cx bit fields */
2829 htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
2830
2831 /* Set GC5Cx bit fields */
2832 htim->Instance->CCR5 |= Channels;
2833
2834 /* Change the htim state */
2835 htim->State = HAL_TIM_STATE_READY;
2836
2837 __HAL_UNLOCK(htim);
2838
2839 return HAL_OK;
2840 }
2841
2842 /**
2843 * @brief Disarm the designated break input (when it operates in bidirectional mode).
2844 * @param htim TIM handle.
2845 * @param BreakInput Break input to disarm
2846 * This parameter can be one of the following values:
2847 * @arg TIM_BREAKINPUT_BRK: Timer break input
2848 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
2849 * @note The break input can be disarmed only when it is configured in
2850 * bidirectional mode and when when MOE is reset.
2851 * @note Purpose is to be able to have the input voltage back to high-state,
2852 * whatever the time constant on the output .
2853 * @retval HAL status
2854 */
HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef * htim,uint32_t BreakInput)2855 HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput)
2856 {
2857 HAL_StatusTypeDef status = HAL_OK;
2858 uint32_t tmpbdtr;
2859
2860 /* Check the parameters */
2861 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2862 assert_param(IS_TIM_BREAKINPUT(BreakInput));
2863
2864 switch (BreakInput)
2865 {
2866 case TIM_BREAKINPUT_BRK:
2867 {
2868 /* Check initial conditions */
2869 tmpbdtr = READ_REG(htim->Instance->BDTR);
2870 if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) &&
2871 (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
2872 {
2873 /* Break input BRK is disarmed */
2874 SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM);
2875 }
2876 break;
2877 }
2878 case TIM_BREAKINPUT_BRK2:
2879 {
2880 /* Check initial conditions */
2881 tmpbdtr = READ_REG(htim->Instance->BDTR);
2882 if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) &&
2883 (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
2884 {
2885 /* Break input BRK is disarmed */
2886 SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM);
2887 }
2888 break;
2889 }
2890 default:
2891 status = HAL_ERROR;
2892 break;
2893 }
2894
2895 return status;
2896 }
2897
2898 /**
2899 * @brief Arm the designated break input (when it operates in bidirectional mode).
2900 * @param htim TIM handle.
2901 * @param BreakInput Break input to arm
2902 * This parameter can be one of the following values:
2903 * @arg TIM_BREAKINPUT_BRK: Timer break input
2904 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
2905 * @note Arming is possible at anytime, even if fault is present.
2906 * @note Break input is automatically armed as soon as MOE bit is set.
2907 * @retval HAL status
2908 */
HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef * htim,uint32_t BreakInput)2909 HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput)
2910 {
2911 HAL_StatusTypeDef status = HAL_OK;
2912 uint32_t tickstart;
2913
2914 /* Check the parameters */
2915 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2916 assert_param(IS_TIM_BREAKINPUT(BreakInput));
2917
2918 switch (BreakInput)
2919 {
2920 case TIM_BREAKINPUT_BRK:
2921 {
2922 /* Check initial conditions */
2923 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID)
2924 {
2925 /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
2926 /* Init tickstart for timeout management */
2927 tickstart = HAL_GetTick();
2928 while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
2929 {
2930 if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
2931 {
2932 /* New check to avoid false timeout detection in case of preemption */
2933 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
2934 {
2935 return HAL_TIMEOUT;
2936 }
2937 }
2938 }
2939 }
2940 break;
2941 }
2942
2943 case TIM_BREAKINPUT_BRK2:
2944 {
2945 /* Check initial conditions */
2946 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID)
2947 {
2948 /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
2949 /* Init tickstart for timeout management */
2950 tickstart = HAL_GetTick();
2951 while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
2952 {
2953 if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
2954 {
2955 /* New check to avoid false timeout detection in case of preemption */
2956 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
2957 {
2958 return HAL_TIMEOUT;
2959 }
2960 }
2961 }
2962 }
2963 break;
2964 }
2965 default:
2966 status = HAL_ERROR;
2967 break;
2968 }
2969
2970 return status;
2971 }
2972
2973 /**
2974 * @brief Enable dithering
2975 * @param htim TIM handle
2976 * @note Main usage is PWM mode
2977 * @note This function must be called when timer is stopped or disabled (CEN =0)
2978 * @note If dithering is activated, pay attention to ARR, CCRx, CNT interpretation:
2979 * - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers)
2980 * - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers
2981 * - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers
2982 * - ARR and CCRx values are limited to 0xFFEF in dithering mode for 16b timers
2983 * (corresponds to 4094 for the integer part and 15 for the dithered part).
2984 * @note Macros @ref __HAL_TIM_CALC_PERIOD_DITHER() __HAL_TIM_CALC_DELAY_DITHER() __HAL_TIM_CALC_PULSE_DITHER()
2985 * can be used to calculate period (ARR) and delay (CCRx) value.
2986 * @note Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
2987 * @note Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
2988 * So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD()
2989 * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period .
2990 * @retval HAL status
2991 */
HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef * htim)2992 HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim)
2993 {
2994 /* Check the parameters */
2995 assert_param(IS_TIM_INSTANCE(htim->Instance));
2996
2997 SET_BIT(htim->Instance->CR1, TIM_CR1_DITHEN);
2998 return HAL_OK;
2999 }
3000
3001 /**
3002 * @brief Disable dithering
3003 * @param htim TIM handle
3004 * @note This function must be called when timer is stopped or disabled (CEN =0)
3005 * @note If dithering is activated, pay attention to ARR, CCRx, CNT interpretation:
3006 * - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers)
3007 * - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers
3008 * - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers
3009 * - ARR and CCRx values are limited to 0xFFEF in dithering mode
3010 * (corresponds to 4094 for the integer part and 15 for the dithered part).
3011 * @note Disabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
3012 * So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD()
3013 * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period .
3014 * @retval HAL status
3015 */
HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef * htim)3016 HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim)
3017 {
3018 /* Check the parameters */
3019 assert_param(IS_TIM_INSTANCE(htim->Instance));
3020
3021 CLEAR_BIT(htim->Instance->CR1, TIM_CR1_DITHEN);
3022 return HAL_OK;
3023 }
3024
3025 /**
3026 * @brief Initializes the pulse on compare pulse width and pulse prescaler
3027 * @param htim TIM Output Compare handle
3028 * @param PulseWidthPrescaler Pulse width prescaler
3029 * This parameter can be a number between Min_Data = 0x0 and Max_Data = 0x7
3030 * @param PulseWidth Pulse width
3031 * This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
3032 * @retval HAL status
3033 */
HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef * htim,uint32_t PulseWidthPrescaler,uint32_t PulseWidth)3034 HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim,
3035 uint32_t PulseWidthPrescaler,
3036 uint32_t PulseWidth)
3037 {
3038 uint32_t tmpecr;
3039
3040 /* Check the parameters */
3041 assert_param(IS_TIM_PULSEONCOMPARE_INSTANCE(htim->Instance));
3042 assert_param(IS_TIM_PULSEONCOMPARE_WIDTH(PulseWidth));
3043 assert_param(IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(PulseWidthPrescaler));
3044
3045 /* Process Locked */
3046 __HAL_LOCK(htim);
3047
3048 /* Set the TIM state */
3049 htim->State = HAL_TIM_STATE_BUSY;
3050
3051 /* Get the TIMx ECR register value */
3052 tmpecr = htim->Instance->ECR;
3053 /* Reset the Pulse width prescaler and the Pulse width */
3054 tmpecr &= ~(TIM_ECR_PWPRSC | TIM_ECR_PW);
3055 /* Set the Pulse width prescaler and Pulse width*/
3056 tmpecr |= PulseWidthPrescaler << TIM_ECR_PWPRSC_Pos;
3057 tmpecr |= PulseWidth << TIM_ECR_PW_Pos;
3058 /* Write to TIMx ECR */
3059 htim->Instance->ECR = tmpecr;
3060
3061 /* Change the TIM state */
3062 htim->State = HAL_TIM_STATE_READY;
3063
3064 /* Release Lock */
3065 __HAL_UNLOCK(htim);
3066
3067 return HAL_OK;
3068 }
3069
3070 /**
3071 * @brief Configure preload source of Slave Mode Selection bitfield (SMS in SMCR register)
3072 * @param htim TIM handle
3073 * @param Source Source of slave mode selection preload
3074 * This parameter can be one of the following values:
3075 * @arg TIM_SMS_PRELOAD_SOURCE_UPDATE: Timer update event is used as source of Slave Mode Selection preload
3076 * @arg TIM_SMS_PRELOAD_SOURCE_INDEX: Timer index event is used as source of Slave Mode Selection preload
3077 * @retval HAL status
3078 */
HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef * htim,uint32_t Source)3079 HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim, uint32_t Source)
3080 {
3081 /* Check the parameters */
3082 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
3083 assert_param(IS_TIM_SLAVE_PRELOAD_SOURCE(Source));
3084
3085 MODIFY_REG(htim->Instance->SMCR, TIM_SMCR_SMSPS, Source);
3086 return HAL_OK;
3087 }
3088
3089 /**
3090 * @brief Enable preload of Slave Mode Selection bitfield (SMS in SMCR register)
3091 * @param htim TIM handle
3092 * @retval HAL status
3093 */
HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef * htim)3094 HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim)
3095 {
3096 /* Check the parameters */
3097 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
3098
3099 SET_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE);
3100 return HAL_OK;
3101 }
3102
3103 /**
3104 * @brief Disable preload of Slave Mode Selection bitfield (SMS in SMCR register)
3105 * @param htim TIM handle
3106 * @retval HAL status
3107 */
HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef * htim)3108 HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim)
3109 {
3110 /* Check the parameters */
3111 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
3112
3113 CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE);
3114 return HAL_OK;
3115 }
3116
3117 /**
3118 * @brief Enable deadtime preload
3119 * @param htim TIM handle
3120 * @retval HAL status
3121 */
HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef * htim)3122 HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim)
3123 {
3124 /* Check the parameters */
3125 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
3126
3127 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE);
3128 return HAL_OK;
3129 }
3130
3131 /**
3132 * @brief Disable deadtime preload
3133 * @param htim TIM handle
3134 * @retval HAL status
3135 */
HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef * htim)3136 HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim)
3137 {
3138 /* Check the parameters */
3139 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
3140
3141 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE);
3142 return HAL_OK;
3143 }
3144
3145 /**
3146 * @brief Configure deadtime
3147 * @param htim TIM handle
3148 * @param Deadtime Deadtime value
3149 * @note This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
3150 * @retval HAL status
3151 */
HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef * htim,uint32_t Deadtime)3152 HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim, uint32_t Deadtime)
3153 {
3154 /* Check the parameters */
3155 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
3156 assert_param(IS_TIM_DEADTIME(Deadtime));
3157
3158 MODIFY_REG(htim->Instance->BDTR, TIM_BDTR_DTG, Deadtime);
3159 return HAL_OK;
3160 }
3161
3162 /**
3163 * @brief Configure asymmetrical deadtime
3164 * @param htim TIM handle
3165 * @param FallingDeadtime Falling edge deadtime value
3166 * @note This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
3167 * @retval HAL status
3168 */
HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef * htim,uint32_t FallingDeadtime)3169 HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef *htim, uint32_t FallingDeadtime)
3170 {
3171 /* Check the parameters */
3172 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
3173 assert_param(IS_TIM_DEADTIME(FallingDeadtime));
3174
3175 MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime);
3176 return HAL_OK;
3177 }
3178
3179 /**
3180 * @brief Enable asymmetrical deadtime
3181 * @param htim TIM handle
3182 * @retval HAL status
3183 */
HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef * htim)3184 HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim)
3185 {
3186 /* Check the parameters */
3187 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
3188
3189 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE);
3190 return HAL_OK;
3191 }
3192
3193 /**
3194 * @brief Disable asymmetrical deadtime
3195 * @param htim TIM handle
3196 * @retval HAL status
3197 */
HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef * htim)3198 HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef *htim)
3199 {
3200 /* Check the parameters */
3201 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
3202
3203 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE);
3204 return HAL_OK;
3205 }
3206
3207 /**
3208 * @brief Configures the encoder index.
3209 * @note warning in case of encoder mode clock plus direction
3210 * @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 or @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
3211 * Direction must be set to @ref TIM_ENCODERINDEX_DIRECTION_UP_DOWN
3212 * @param htim TIM handle.
3213 * @param sEncoderIndexConfig Encoder index configuration
3214 * @retval HAL status
3215 */
HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef * htim,TIMEx_EncoderIndexConfigTypeDef * sEncoderIndexConfig)3216 HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim,
3217 TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig)
3218 {
3219 /* Check the parameters */
3220 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3221 assert_param(IS_TIM_ENCODERINDEX_POLARITY(sEncoderIndexConfig->Polarity));
3222 assert_param(IS_TIM_ENCODERINDEX_PRESCALER(sEncoderIndexConfig->Prescaler));
3223 assert_param(IS_TIM_ENCODERINDEX_FILTER(sEncoderIndexConfig->Filter));
3224 assert_param(IS_FUNCTIONAL_STATE(sEncoderIndexConfig->FirstIndexEnable));
3225 assert_param(IS_TIM_ENCODERINDEX_POSITION(sEncoderIndexConfig->Position));
3226 assert_param(IS_TIM_ENCODERINDEX_DIRECTION(sEncoderIndexConfig->Direction));
3227
3228 /* Process Locked */
3229 __HAL_LOCK(htim);
3230
3231 /* Configures the TIMx External Trigger (ETR) which is used as Index input */
3232 TIM_ETR_SetConfig(htim->Instance,
3233 sEncoderIndexConfig->Prescaler,
3234 sEncoderIndexConfig->Polarity,
3235 sEncoderIndexConfig->Filter);
3236
3237 /* Configures the encoder index */
3238 MODIFY_REG(htim->Instance->ECR,
3239 TIM_ECR_IDIR_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk,
3240 (sEncoderIndexConfig->Direction |
3241 ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) |
3242 sEncoderIndexConfig->Position |
3243 TIM_ECR_IE));
3244
3245 __HAL_UNLOCK(htim);
3246
3247 return HAL_OK;
3248 }
3249
3250 /**
3251 * @brief Enable encoder index
3252 * @param htim TIM handle
3253 * @retval HAL status
3254 */
HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef * htim)3255 HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim)
3256 {
3257 /* Check the parameters */
3258 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3259
3260 SET_BIT(htim->Instance->ECR, TIM_ECR_IE);
3261 return HAL_OK;
3262 }
3263
3264 /**
3265 * @brief Disable encoder index
3266 * @param htim TIM handle
3267 * @retval HAL status
3268 */
HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef * htim)3269 HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim)
3270 {
3271 /* Check the parameters */
3272 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3273
3274 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_IE);
3275 return HAL_OK;
3276 }
3277
3278 /**
3279 * @brief Enable encoder first index
3280 * @param htim TIM handle
3281 * @retval HAL status
3282 */
HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef * htim)3283 HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim)
3284 {
3285 /* Check the parameters */
3286 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3287
3288 SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX);
3289 return HAL_OK;
3290 }
3291
3292 /**
3293 * @brief Disable encoder first index
3294 * @param htim TIM handle
3295 * @retval HAL status
3296 */
HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef * htim)3297 HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim)
3298 {
3299 /* Check the parameters */
3300 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3301
3302 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX);
3303 return HAL_OK;
3304 }
3305
3306 /**
3307 * @}
3308 */
3309
3310 /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
3311 * @brief Extended Callbacks functions
3312 *
3313 @verbatim
3314 ==============================================================================
3315 ##### Extended Callbacks functions #####
3316 ==============================================================================
3317 [..]
3318 This section provides Extended TIM callback functions:
3319 (+) Timer Commutation callback
3320 (+) Timer Break callback
3321
3322 @endverbatim
3323 * @{
3324 */
3325
3326 /**
3327 * @brief Commutation callback in non-blocking mode
3328 * @param htim TIM handle
3329 * @retval None
3330 */
HAL_TIMEx_CommutCallback(TIM_HandleTypeDef * htim)3331 __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
3332 {
3333 /* Prevent unused argument(s) compilation warning */
3334 UNUSED(htim);
3335
3336 /* NOTE : This function should not be modified, when the callback is needed,
3337 the HAL_TIMEx_CommutCallback could be implemented in the user file
3338 */
3339 }
3340 /**
3341 * @brief Commutation half complete callback in non-blocking mode
3342 * @param htim TIM handle
3343 * @retval None
3344 */
HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef * htim)3345 __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
3346 {
3347 /* Prevent unused argument(s) compilation warning */
3348 UNUSED(htim);
3349
3350 /* NOTE : This function should not be modified, when the callback is needed,
3351 the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
3352 */
3353 }
3354
3355 /**
3356 * @brief Break detection callback in non-blocking mode
3357 * @param htim TIM handle
3358 * @retval None
3359 */
HAL_TIMEx_BreakCallback(TIM_HandleTypeDef * htim)3360 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
3361 {
3362 /* Prevent unused argument(s) compilation warning */
3363 UNUSED(htim);
3364
3365 /* NOTE : This function should not be modified, when the callback is needed,
3366 the HAL_TIMEx_BreakCallback could be implemented in the user file
3367 */
3368 }
3369
3370 /**
3371 * @brief Break2 detection callback in non blocking mode
3372 * @param htim: TIM handle
3373 * @retval None
3374 */
HAL_TIMEx_Break2Callback(TIM_HandleTypeDef * htim)3375 __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
3376 {
3377 /* Prevent unused argument(s) compilation warning */
3378 UNUSED(htim);
3379
3380 /* NOTE : This function Should not be modified, when the callback is needed,
3381 the HAL_TIMEx_Break2Callback could be implemented in the user file
3382 */
3383 }
3384
3385 /**
3386 * @brief Encoder index callback in non-blocking mode
3387 * @param htim TIM handle
3388 * @retval None
3389 */
HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef * htim)3390 __weak void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim)
3391 {
3392 /* Prevent unused argument(s) compilation warning */
3393 UNUSED(htim);
3394
3395 /* NOTE : This function should not be modified, when the callback is needed,
3396 the HAL_TIMEx_EncoderIndexCallback could be implemented in the user file
3397 */
3398 }
3399
3400 /**
3401 * @brief Direction change callback in non-blocking mode
3402 * @param htim TIM handle
3403 * @retval None
3404 */
HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef * htim)3405 __weak void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim)
3406 {
3407 /* Prevent unused argument(s) compilation warning */
3408 UNUSED(htim);
3409
3410 /* NOTE : This function should not be modified, when the callback is needed,
3411 the HAL_TIMEx_DirectionChangeCallback could be implemented in the user file
3412 */
3413 }
3414
3415 /**
3416 * @brief Index error callback in non-blocking mode
3417 * @param htim TIM handle
3418 * @retval None
3419 */
HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef * htim)3420 __weak void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim)
3421 {
3422 /* Prevent unused argument(s) compilation warning */
3423 UNUSED(htim);
3424
3425 /* NOTE : This function should not be modified, when the callback is needed,
3426 the HAL_TIMEx_IndexErrorCallback could be implemented in the user file
3427 */
3428 }
3429
3430 /**
3431 * @brief Transition error callback in non-blocking mode
3432 * @param htim TIM handle
3433 * @retval None
3434 */
HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef * htim)3435 __weak void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim)
3436 {
3437 /* Prevent unused argument(s) compilation warning */
3438 UNUSED(htim);
3439
3440 /* NOTE : This function should not be modified, when the callback is needed,
3441 the HAL_TIMEx_TransitionErrorCallback could be implemented in the user file
3442 */
3443 }
3444
3445 /**
3446 * @}
3447 */
3448
3449 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
3450 * @brief Extended Peripheral State functions
3451 *
3452 @verbatim
3453 ==============================================================================
3454 ##### Extended Peripheral State functions #####
3455 ==============================================================================
3456 [..]
3457 This subsection permits to get in run-time the status of the peripheral
3458 and the data flow.
3459
3460 @endverbatim
3461 * @{
3462 */
3463
3464 /**
3465 * @brief Return the TIM Hall Sensor interface handle state.
3466 * @param htim TIM Hall Sensor handle
3467 * @retval HAL state
3468 */
HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef * htim)3469 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim)
3470 {
3471 return htim->State;
3472 }
3473
3474 /**
3475 * @brief Return actual state of the TIM complementary channel.
3476 * @param htim TIM handle
3477 * @param ChannelN TIM Complementary channel
3478 * This parameter can be one of the following values:
3479 * @arg TIM_CHANNEL_1: TIM Channel 1
3480 * @arg TIM_CHANNEL_2: TIM Channel 2
3481 * @arg TIM_CHANNEL_3: TIM Channel 3
3482 * @arg TIM_CHANNEL_4: TIM Channel 4
3483 * @retval TIM Complementary channel state
3484 */
HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef * htim,uint32_t ChannelN)3485 HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN)
3486 {
3487 HAL_TIM_ChannelStateTypeDef channel_state;
3488
3489 /* Check the parameters */
3490 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
3491
3492 channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
3493
3494 return channel_state;
3495 }
3496 /**
3497 * @}
3498 */
3499
3500 /**
3501 * @}
3502 */
3503
3504 /* Private functions ---------------------------------------------------------*/
3505 /** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
3506 * @{
3507 */
3508
3509 /**
3510 * @brief TIM DMA Commutation callback.
3511 * @param hdma pointer to DMA handle.
3512 * @retval None
3513 */
TIMEx_DMACommutationCplt(DMA_HandleTypeDef * hdma)3514 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
3515 {
3516 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3517
3518 /* Change the htim state */
3519 htim->State = HAL_TIM_STATE_READY;
3520
3521 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3522 htim->CommutationCallback(htim);
3523 #else
3524 HAL_TIMEx_CommutCallback(htim);
3525 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3526 }
3527
3528 /**
3529 * @brief TIM DMA Commutation half complete callback.
3530 * @param hdma pointer to DMA handle.
3531 * @retval None
3532 */
TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef * hdma)3533 void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
3534 {
3535 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3536
3537 /* Change the htim state */
3538 htim->State = HAL_TIM_STATE_READY;
3539
3540 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3541 htim->CommutationHalfCpltCallback(htim);
3542 #else
3543 HAL_TIMEx_CommutHalfCpltCallback(htim);
3544 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3545 }
3546
3547
3548 /**
3549 * @brief TIM DMA Delay Pulse complete callback (complementary channel).
3550 * @param hdma pointer to DMA handle.
3551 * @retval None
3552 */
TIM_DMADelayPulseNCplt(DMA_HandleTypeDef * hdma)3553 static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
3554 {
3555 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3556
3557 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
3558 {
3559 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3560
3561 if (hdma->Init.Mode == DMA_NORMAL)
3562 {
3563 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3564 }
3565 }
3566 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
3567 {
3568 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3569
3570 if (hdma->Init.Mode == DMA_NORMAL)
3571 {
3572 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3573 }
3574 }
3575 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
3576 {
3577 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3578
3579 if (hdma->Init.Mode == DMA_NORMAL)
3580 {
3581 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
3582 }
3583 }
3584 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
3585 {
3586 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3587
3588 if (hdma->Init.Mode == DMA_NORMAL)
3589 {
3590 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
3591 }
3592 }
3593 else
3594 {
3595 /* nothing to do */
3596 }
3597
3598 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3599 htim->PWM_PulseFinishedCallback(htim);
3600 #else
3601 HAL_TIM_PWM_PulseFinishedCallback(htim);
3602 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3603
3604 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3605 }
3606
3607 /**
3608 * @brief TIM DMA error callback (complementary channel)
3609 * @param hdma pointer to DMA handle.
3610 * @retval None
3611 */
TIM_DMAErrorCCxN(DMA_HandleTypeDef * hdma)3612 static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
3613 {
3614 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3615
3616 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
3617 {
3618 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3619 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3620 }
3621 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
3622 {
3623 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3624 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3625 }
3626 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
3627 {
3628 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3629 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
3630 }
3631 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
3632 {
3633 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3634 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
3635 }
3636 else
3637 {
3638 /* nothing to do */
3639 }
3640
3641 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3642 htim->ErrorCallback(htim);
3643 #else
3644 HAL_TIM_ErrorCallback(htim);
3645 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3646
3647 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3648 }
3649
3650 /**
3651 * @brief Enables or disables the TIM Capture Compare Channel xN.
3652 * @param TIMx to select the TIM peripheral
3653 * @param Channel specifies the TIM Channel
3654 * This parameter can be one of the following values:
3655 * @arg TIM_CHANNEL_1: TIM Channel 1
3656 * @arg TIM_CHANNEL_2: TIM Channel 2
3657 * @arg TIM_CHANNEL_3: TIM Channel 3
3658 * @arg TIM_CHANNEL_4: TIM Channel 4
3659 * @param ChannelNState specifies the TIM Channel CCxNE bit new state.
3660 * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
3661 * @retval None
3662 */
TIM_CCxNChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelNState)3663 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
3664 {
3665 uint32_t tmp;
3666
3667 tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */
3668
3669 /* Reset the CCxNE Bit */
3670 TIMx->CCER &= ~tmp;
3671
3672 /* Set or reset the CCxNE Bit */
3673 TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */
3674 }
3675 /**
3676 * @}
3677 */
3678
3679 #endif /* HAL_TIM_MODULE_ENABLED */
3680 /**
3681 * @}
3682 */
3683
3684 /**
3685 * @}
3686 */
3687
