1 /**
2 ******************************************************************************
3 * @file stm32g4xx_hal_pwr_ex.c
4 * @author MCD Application Team
5 * @brief Extended PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller (PWR) peripheral:
8 * + Extended Initialization and de-initialization functions
9 * + Extended Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2019 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file
18 * in the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 *
21 ******************************************************************************
22 */
23
24 /* Includes ------------------------------------------------------------------*/
25 #include "stm32g4xx_hal.h"
26
27 /** @addtogroup STM32G4xx_HAL_Driver
28 * @{
29 */
30
31 /** @defgroup PWREx PWREx
32 * @brief PWR Extended HAL module driver
33 * @{
34 */
35
36 #ifdef HAL_PWR_MODULE_ENABLED
37
38 /* Private typedef -----------------------------------------------------------*/
39 /* Private define ------------------------------------------------------------*/
40
41
42 #if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G414xx) || defined (STM32G474xx) || defined (STM32G483xx) || defined (STM32G484xx)
43 #define PWR_PORTF_AVAILABLE_PINS 0x0000FFFFU /* PF0..PF15 */
44 #define PWR_PORTG_AVAILABLE_PINS 0x000007FFU /* PG0..PG10 */
45 #elif defined (STM32G411xB) || defined (STM32G411xC) || defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB) || defined (STM32G491xx) || defined (STM32G4A1xx)
46 #define PWR_PORTF_AVAILABLE_PINS 0x00000607U /* PF0..PF2 and PF9 and PF10 */
47 #define PWR_PORTG_AVAILABLE_PINS 0x00000400U /* PG10 */
48 #endif /* STM32G471xx || STM32G473xx || STM32G414xx || STM32G474xx || STM32G483xx || STM32G484xx */
49
50 /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
51 * @{
52 */
53
54 /** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask
55 * @{
56 */
57 #define PVM_MODE_IT 0x00010000U /*!< Mask for interruption yielded by PVM threshold crossing */
58 #define PVM_MODE_EVT 0x00020000U /*!< Mask for event yielded by PVM threshold crossing */
59 #define PVM_RISING_EDGE 0x00000001U /*!< Mask for rising edge set as PVM trigger */
60 #define PVM_FALLING_EDGE 0x00000002U /*!< Mask for falling edge set as PVM trigger */
61 /**
62 * @}
63 */
64
65 /** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value
66 * @{
67 */
68 #define PWR_FLAG_SETTING_DELAY_US 50UL /*!< Time out value for REGLPF and VOSF flags setting */
69 /**
70 * @}
71 */
72
73
74
75 /**
76 * @}
77 */
78
79
80
81 /* Private macro -------------------------------------------------------------*/
82 /* Private variables ---------------------------------------------------------*/
83 /* Private function prototypes -----------------------------------------------*/
84 /* Exported functions --------------------------------------------------------*/
85
86 /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
87 * @{
88 */
89
90 /** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
91 * @brief Extended Peripheral Control functions
92 *
93 @verbatim
94 ===============================================================================
95 ##### Extended Peripheral Initialization and de-initialization functions #####
96 ===============================================================================
97 [..]
98
99 @endverbatim
100 * @{
101 */
102
103
104 /**
105 * @brief Return Voltage Scaling Range.
106 * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2
107 * or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable)
108 */
HAL_PWREx_GetVoltageRange(void)109 uint32_t HAL_PWREx_GetVoltageRange(void)
110 {
111 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
112 {
113 return PWR_REGULATOR_VOLTAGE_SCALE2;
114 }
115 else if (READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == PWR_CR5_R1MODE)
116 {
117 /* PWR_CR5_R1MODE bit set means that Range 1 Boost is disabled */
118 return PWR_REGULATOR_VOLTAGE_SCALE1;
119 }
120 else
121 {
122 return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST;
123 }
124 }
125
126
127
128 /**
129 * @brief Configure the main internal regulator output voltage.
130 * @param VoltageScaling: specifies the regulator output voltage to achieve
131 * a tradeoff between performance and power consumption.
132 * This parameter can be one of the following values:
133 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when available, Regulator voltage output range 1 boost mode,
134 * typical output voltage at 1.28 V,
135 * system frequency up to 170 MHz.
136 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
137 * typical output voltage at 1.2 V,
138 * system frequency up to 150 MHz.
139 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
140 * typical output voltage at 1.0 V,
141 * system frequency up to 26 MHz.
142 * @note When moving from Range 1 to Range 2, the system frequency must be decreased to
143 * a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API.
144 * When moving from Range 2 to Range 1, the system frequency can be increased to
145 * a value up to 150 MHz after calling HAL_PWREx_ControlVoltageScaling() API.
146 * When moving from Range 1 to Boost Mode Range 1, the system frequency can be increased to
147 * a value up to 170 MHz after calling HAL_PWREx_ControlVoltageScaling() API.
148 * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be
149 * cleared before returning the status. If the flag is not cleared within
150 * 50 microseconds, HAL_TIMEOUT status is reported.
151 * @retval HAL Status
152 */
HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)153 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
154 {
155 uint32_t wait_loop_index;
156
157 assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
158
159 if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST)
160 {
161 /* If current range is range 2 */
162 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
163 {
164 /* Make sure Range 1 Boost is enabled */
165 CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
166
167 /* Set Range 1 */
168 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
169
170 /* Wait until VOSF is cleared */
171 wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
172 while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
173 {
174 wait_loop_index--;
175 }
176 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
177 {
178 return HAL_TIMEOUT;
179 }
180 }
181 /* If current range is range 1 normal or boost mode */
182 else
183 {
184 /* Enable Range 1 Boost (no issue if bit already reset) */
185 CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
186 }
187 }
188 else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
189 {
190 /* If current range is range 2 */
191 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
192 {
193 /* Make sure Range 1 Boost is disabled */
194 SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
195
196 /* Set Range 1 */
197 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
198
199 /* Wait until VOSF is cleared */
200 wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
201 while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
202 {
203 wait_loop_index--;
204 }
205 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
206 {
207 return HAL_TIMEOUT;
208 }
209 }
210 /* If current range is range 1 normal or boost mode */
211 else
212 {
213 /* Disable Range 1 Boost (no issue if bit already set) */
214 SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
215 }
216 }
217 else
218 {
219 /* Set Range 2 */
220 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
221 /* No need to wait for VOSF to be cleared for this transition */
222 /* PWR_CR5_R1MODE bit setting has no effect in Range 2 */
223 }
224
225 return HAL_OK;
226 }
227
228
229 /**
230 * @brief Enable battery charging.
231 * When VDD is present, charge the external battery on VBAT through an internal resistor.
232 * @param ResistorSelection: specifies the resistor impedance.
233 * This parameter can be one of the following values:
234 * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor
235 * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor
236 * @retval None
237 */
HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)238 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)
239 {
240 assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection));
241
242 /* Specify resistor selection */
243 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection);
244
245 /* Enable battery charging */
246 SET_BIT(PWR->CR4, PWR_CR4_VBE);
247 }
248
249
250 /**
251 * @brief Disable battery charging.
252 * @retval None
253 */
HAL_PWREx_DisableBatteryCharging(void)254 void HAL_PWREx_DisableBatteryCharging(void)
255 {
256 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
257 }
258
259
260 /**
261 * @brief Enable Internal Wake-up Line.
262 * @retval None
263 */
HAL_PWREx_EnableInternalWakeUpLine(void)264 void HAL_PWREx_EnableInternalWakeUpLine(void)
265 {
266 SET_BIT(PWR->CR3, PWR_CR3_EIWF);
267 }
268
269
270 /**
271 * @brief Disable Internal Wake-up Line.
272 * @retval None
273 */
HAL_PWREx_DisableInternalWakeUpLine(void)274 void HAL_PWREx_DisableInternalWakeUpLine(void)
275 {
276 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
277 }
278
279
280
281 /**
282 * @brief Enable GPIO pull-up state in Standby and Shutdown modes.
283 * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in
284 * pull-up state in Standby and Shutdown modes.
285 * @note This state is effective in Standby and Shutdown modes only if APC bit
286 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
287 * @note The configuration is lost when exiting the Shutdown mode due to the
288 * power-on reset, maintained when exiting the Standby mode.
289 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
290 * PDy bit of PWR_PDCRx register is cleared unless it is reserved.
291 * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input
292 * parameter at the same time are set.
293 * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_G
294 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
295 * @param GPIONumber: Specify the I/O pins numbers.
296 * This parameter can be one of the following values:
297 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
298 * I/O pins are available) or the logical OR of several of them to set
299 * several bits for a given port in a single API call.
300 * @retval HAL Status
301 */
HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)302 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
303 {
304 HAL_StatusTypeDef status = HAL_OK;
305
306 assert_param(IS_PWR_GPIO(GPIO));
307 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
308
309 switch (GPIO)
310 {
311 case PWR_GPIO_A:
312 SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
313 CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
314 break;
315 case PWR_GPIO_B:
316 SET_BIT(PWR->PUCRB, GPIONumber);
317 CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
318 break;
319 case PWR_GPIO_C:
320 SET_BIT(PWR->PUCRC, GPIONumber);
321 CLEAR_BIT(PWR->PDCRC, GPIONumber);
322 break;
323 case PWR_GPIO_D:
324 SET_BIT(PWR->PUCRD, GPIONumber);
325 CLEAR_BIT(PWR->PDCRD, GPIONumber);
326 break;
327 case PWR_GPIO_E:
328 SET_BIT(PWR->PUCRE, GPIONumber);
329 CLEAR_BIT(PWR->PDCRE, GPIONumber);
330 break;
331 case PWR_GPIO_F:
332 SET_BIT(PWR->PUCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
333 CLEAR_BIT(PWR->PDCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
334 break;
335 case PWR_GPIO_G:
336 SET_BIT(PWR->PUCRG, (GPIONumber & PWR_PORTG_AVAILABLE_PINS));
337 CLEAR_BIT(PWR->PDCRG, ((GPIONumber & PWR_PORTG_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_10))));
338 break;
339 default:
340 status = HAL_ERROR;
341 break;
342 }
343
344 return status;
345 }
346
347
348 /**
349 * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.
350 * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O
351 * in pull-up state in Standby and Shutdown modes.
352 * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input
353 * parameter at the same time are reset.
354 * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_G
355 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
356 * @param GPIONumber: Specify the I/O pins numbers.
357 * This parameter can be one of the following values:
358 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
359 * I/O pins are available) or the logical OR of several of them to reset
360 * several bits for a given port in a single API call.
361 * @retval HAL Status
362 */
HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)363 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
364 {
365 HAL_StatusTypeDef status = HAL_OK;
366
367 assert_param(IS_PWR_GPIO(GPIO));
368 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
369
370 switch (GPIO)
371 {
372 case PWR_GPIO_A:
373 CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
374 break;
375 case PWR_GPIO_B:
376 CLEAR_BIT(PWR->PUCRB, GPIONumber);
377 break;
378 case PWR_GPIO_C:
379 CLEAR_BIT(PWR->PUCRC, GPIONumber);
380 break;
381 case PWR_GPIO_D:
382 CLEAR_BIT(PWR->PUCRD, GPIONumber);
383 break;
384 case PWR_GPIO_E:
385 CLEAR_BIT(PWR->PUCRE, GPIONumber);
386 break;
387 case PWR_GPIO_F:
388 CLEAR_BIT(PWR->PUCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
389 break;
390 case PWR_GPIO_G:
391 CLEAR_BIT(PWR->PUCRG, (GPIONumber & PWR_PORTG_AVAILABLE_PINS));
392 break;
393 default:
394 status = HAL_ERROR;
395 break;
396 }
397
398 return status;
399 }
400
401
402
403 /**
404 * @brief Enable GPIO pull-down state in Standby and Shutdown modes.
405 * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in
406 * pull-down state in Standby and Shutdown modes.
407 * @note This state is effective in Standby and Shutdown modes only if APC bit
408 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
409 * @note The configuration is lost when exiting the Shutdown mode due to the
410 * power-on reset, maintained when exiting the Standby mode.
411 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
412 * PUy bit of PWR_PUCRx register is cleared unless it is reserved.
413 * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input
414 * parameter at the same time are set.
415 * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_G
416 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
417 * @param GPIONumber: Specify the I/O pins numbers.
418 * This parameter can be one of the following values:
419 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
420 * I/O pins are available) or the logical OR of several of them to set
421 * several bits for a given port in a single API call.
422 * @retval HAL Status
423 */
HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)424 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
425 {
426 HAL_StatusTypeDef status = HAL_OK;
427
428 assert_param(IS_PWR_GPIO(GPIO));
429 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
430
431 switch (GPIO)
432 {
433 case PWR_GPIO_A:
434 SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
435 CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
436 break;
437 case PWR_GPIO_B:
438 SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
439 CLEAR_BIT(PWR->PUCRB, GPIONumber);
440 break;
441 case PWR_GPIO_C:
442 SET_BIT(PWR->PDCRC, GPIONumber);
443 CLEAR_BIT(PWR->PUCRC, GPIONumber);
444 break;
445 case PWR_GPIO_D:
446 SET_BIT(PWR->PDCRD, GPIONumber);
447 CLEAR_BIT(PWR->PUCRD, GPIONumber);
448 break;
449 case PWR_GPIO_E:
450 SET_BIT(PWR->PDCRE, GPIONumber);
451 CLEAR_BIT(PWR->PUCRE, GPIONumber);
452 break;
453 case PWR_GPIO_F:
454 SET_BIT(PWR->PDCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
455 CLEAR_BIT(PWR->PUCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
456 break;
457 case PWR_GPIO_G:
458 SET_BIT(PWR->PDCRG, ((GPIONumber & PWR_PORTG_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_10))));
459 CLEAR_BIT(PWR->PUCRG, (GPIONumber & PWR_PORTG_AVAILABLE_PINS));
460 break;
461 default:
462 status = HAL_ERROR;
463 break;
464 }
465
466 return status;
467 }
468
469
470 /**
471 * @brief Disable GPIO pull-down state in Standby and Shutdown modes.
472 * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O
473 * in pull-down state in Standby and Shutdown modes.
474 * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input
475 * parameter at the same time are reset.
476 * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_G
477 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
478 * @param GPIONumber: Specify the I/O pins numbers.
479 * This parameter can be one of the following values:
480 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
481 * I/O pins are available) or the logical OR of several of them to reset
482 * several bits for a given port in a single API call.
483 * @retval HAL Status
484 */
HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)485 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
486 {
487 HAL_StatusTypeDef status = HAL_OK;
488
489 assert_param(IS_PWR_GPIO(GPIO));
490 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
491
492 switch (GPIO)
493 {
494 case PWR_GPIO_A:
495 CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
496 break;
497 case PWR_GPIO_B:
498 CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
499 break;
500 case PWR_GPIO_C:
501 CLEAR_BIT(PWR->PDCRC, GPIONumber);
502 break;
503 case PWR_GPIO_D:
504 CLEAR_BIT(PWR->PDCRD, GPIONumber);
505 break;
506 case PWR_GPIO_E:
507 CLEAR_BIT(PWR->PDCRE, GPIONumber);
508 break;
509 case PWR_GPIO_F:
510 CLEAR_BIT(PWR->PDCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS));
511 break;
512 case PWR_GPIO_G:
513 CLEAR_BIT(PWR->PDCRG, ((GPIONumber & PWR_PORTG_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_10))));
514 break;
515 default:
516 status = HAL_ERROR;
517 break;
518 }
519
520 return status;
521 }
522
523
524
525 /**
526 * @brief Enable pull-up and pull-down configuration.
527 * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in
528 * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.
529 * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding
530 * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher).
531 * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there
532 * is no conflict when setting PUy or PDy bit.
533 * @retval None
534 */
HAL_PWREx_EnablePullUpPullDownConfig(void)535 void HAL_PWREx_EnablePullUpPullDownConfig(void)
536 {
537 SET_BIT(PWR->CR3, PWR_CR3_APC);
538 }
539
540
541 /**
542 * @brief Disable pull-up and pull-down configuration.
543 * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in
544 * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.
545 * @retval None
546 */
HAL_PWREx_DisablePullUpPullDownConfig(void)547 void HAL_PWREx_DisablePullUpPullDownConfig(void)
548 {
549 CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
550 }
551
552
553 #if defined (SRAM2_BASE)
554 /**
555 * @brief Enable SRAM2 content retention in Standby mode.
556 * @note When RRS bit is set, SRAM2 is powered by the low-power regulator in
557 * Standby mode and its content is kept.
558 * @retval None
559 */
HAL_PWREx_EnableSRAM2ContentRetention(void)560 void HAL_PWREx_EnableSRAM2ContentRetention(void)
561 {
562 SET_BIT(PWR->CR3, PWR_CR3_RRS);
563 }
564
565
566 /**
567 * @brief Disable SRAM2 content retention in Standby mode.
568 * @note When RRS bit is reset, SRAM2 is powered off in Standby mode
569 * and its content is lost.
570 * @retval None
571 */
HAL_PWREx_DisableSRAM2ContentRetention(void)572 void HAL_PWREx_DisableSRAM2ContentRetention(void)
573 {
574 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
575 }
576 #endif /* SRAM2_BASE */
577
578
579
580 #if defined(PWR_CR2_PVME1)
581 /**
582 * @brief Enable the Power Voltage Monitoring 1: VDDA versus FASTCOMP minimum voltage.
583 * @retval None
584 */
HAL_PWREx_EnablePVM1(void)585 void HAL_PWREx_EnablePVM1(void)
586 {
587 SET_BIT(PWR->CR2, PWR_PVM_1);
588 }
589
590 /**
591 * @brief Disable the Power Voltage Monitoring 1: VDDA versus FASTCOMP minimum voltage.
592 * @retval None
593 */
HAL_PWREx_DisablePVM1(void)594 void HAL_PWREx_DisablePVM1(void)
595 {
596 CLEAR_BIT(PWR->CR2, PWR_PVM_1);
597 }
598 #endif /* PWR_CR2_PVME1 */
599
600
601 #if defined(PWR_CR2_PVME2)
602 /**
603 * @brief Enable the Power Voltage Monitoring 2: VDDA versus FASTDAC minimum voltage.
604 * @retval None
605 */
HAL_PWREx_EnablePVM2(void)606 void HAL_PWREx_EnablePVM2(void)
607 {
608 SET_BIT(PWR->CR2, PWR_PVM_2);
609 }
610
611 /**
612 * @brief Disable the Power Voltage Monitoring 2: VDDA versus FASTDAC minimum voltage.
613 * @retval None
614 */
HAL_PWREx_DisablePVM2(void)615 void HAL_PWREx_DisablePVM2(void)
616 {
617 CLEAR_BIT(PWR->CR2, PWR_PVM_2);
618 }
619 #endif /* PWR_CR2_PVME2 */
620
621
622 /**
623 * @brief Enable the Power Voltage Monitoring 3: VDDA versus ADC minimum voltage 1.62V.
624 * @retval None
625 */
HAL_PWREx_EnablePVM3(void)626 void HAL_PWREx_EnablePVM3(void)
627 {
628 SET_BIT(PWR->CR2, PWR_PVM_3);
629 }
630
631 /**
632 * @brief Disable the Power Voltage Monitoring 3: VDDA versus ADC minimum voltage 1.62V.
633 * @retval None
634 */
HAL_PWREx_DisablePVM3(void)635 void HAL_PWREx_DisablePVM3(void)
636 {
637 CLEAR_BIT(PWR->CR2, PWR_PVM_3);
638 }
639
640
641 /**
642 * @brief Enable the Power Voltage Monitoring 4: VDDA versus OPAMP/DAC minimum voltage 1.8V.
643 * @retval None
644 */
HAL_PWREx_EnablePVM4(void)645 void HAL_PWREx_EnablePVM4(void)
646 {
647 SET_BIT(PWR->CR2, PWR_PVM_4);
648 }
649
650 /**
651 * @brief Disable the Power Voltage Monitoring 4: VDDA versus OPAMP/DAC minimum voltage 1.8V.
652 * @retval None
653 */
HAL_PWREx_DisablePVM4(void)654 void HAL_PWREx_DisablePVM4(void)
655 {
656 CLEAR_BIT(PWR->CR2, PWR_PVM_4);
657 }
658
659
660
661
662 /**
663 * @brief Configure the Peripheral Voltage Monitoring (PVM).
664 * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the
665 * PVM configuration information.
666 * @note The API configures a single PVM according to the information contained
667 * in the input structure. To configure several PVMs, the API must be singly
668 * called for each PVM used.
669 * @note Refer to the electrical characteristics of your device datasheet for
670 * more details about the voltage thresholds corresponding to each
671 * detection level and to each monitored supply.
672 * @retval HAL status
673 */
HAL_PWREx_ConfigPVM(PWR_PVMTypeDef * sConfigPVM)674 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
675 {
676 HAL_StatusTypeDef status = HAL_OK;
677
678 /* Check the parameters */
679 assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType));
680 assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode));
681
682
683 /* Configure EXTI 35 to 38 interrupts if so required:
684 scan through PVMType to detect which PVMx is set and
685 configure the corresponding EXTI line accordingly. */
686 switch (sConfigPVM->PVMType)
687 {
688 #if defined(PWR_CR2_PVME1)
689 case PWR_PVM_1:
690 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
691 __HAL_PWR_PVM1_EXTI_DISABLE_EVENT();
692 __HAL_PWR_PVM1_EXTI_DISABLE_IT();
693 __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();
694 __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();
695
696 /* Configure interrupt mode */
697 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
698 {
699 __HAL_PWR_PVM1_EXTI_ENABLE_IT();
700 }
701
702 /* Configure event mode */
703 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
704 {
705 __HAL_PWR_PVM1_EXTI_ENABLE_EVENT();
706 }
707
708 /* Configure the edge */
709 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
710 {
711 __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();
712 }
713
714 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
715 {
716 __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();
717 }
718 break;
719 #endif /* PWR_CR2_PVME1 */
720
721 #if defined(PWR_CR2_PVME2)
722 case PWR_PVM_2:
723 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
724 __HAL_PWR_PVM2_EXTI_DISABLE_EVENT();
725 __HAL_PWR_PVM2_EXTI_DISABLE_IT();
726 __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();
727 __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();
728
729 /* Configure interrupt mode */
730 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
731 {
732 __HAL_PWR_PVM2_EXTI_ENABLE_IT();
733 }
734
735 /* Configure event mode */
736 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
737 {
738 __HAL_PWR_PVM2_EXTI_ENABLE_EVENT();
739 }
740
741 /* Configure the edge */
742 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
743 {
744 __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();
745 }
746
747 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
748 {
749 __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();
750 }
751 break;
752 #endif /* PWR_CR2_PVME2 */
753
754 case PWR_PVM_3:
755 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
756 __HAL_PWR_PVM3_EXTI_DISABLE_EVENT();
757 __HAL_PWR_PVM3_EXTI_DISABLE_IT();
758 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();
759 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();
760
761 /* Configure interrupt mode */
762 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
763 {
764 __HAL_PWR_PVM3_EXTI_ENABLE_IT();
765 }
766
767 /* Configure event mode */
768 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
769 {
770 __HAL_PWR_PVM3_EXTI_ENABLE_EVENT();
771 }
772
773 /* Configure the edge */
774 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
775 {
776 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();
777 }
778
779 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
780 {
781 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();
782 }
783 break;
784
785 case PWR_PVM_4:
786 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
787 __HAL_PWR_PVM4_EXTI_DISABLE_EVENT();
788 __HAL_PWR_PVM4_EXTI_DISABLE_IT();
789 __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();
790 __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();
791
792 /* Configure interrupt mode */
793 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
794 {
795 __HAL_PWR_PVM4_EXTI_ENABLE_IT();
796 }
797
798 /* Configure event mode */
799 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
800 {
801 __HAL_PWR_PVM4_EXTI_ENABLE_EVENT();
802 }
803
804 /* Configure the edge */
805 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
806 {
807 __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();
808 }
809
810 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
811 {
812 __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();
813 }
814 break;
815
816 default:
817 status = HAL_ERROR;
818 break;
819 }
820
821 return status;
822 }
823
824
825 /**
826 * @brief Enter Low-power Run mode
827 * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode.
828 * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
829 * Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register.
830 * Additionally, the clock frequency must be reduced below 2 MHz.
831 * Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must
832 * be done before calling HAL_PWREx_EnableLowPowerRunMode() API.
833 * @retval None
834 */
HAL_PWREx_EnableLowPowerRunMode(void)835 void HAL_PWREx_EnableLowPowerRunMode(void)
836 {
837 /* Set Regulator parameter */
838 SET_BIT(PWR->CR1, PWR_CR1_LPR);
839 }
840
841
842 /**
843 * @brief Exit Low-power Run mode.
844 * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that
845 * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode
846 * returns HAL_TIMEOUT status). The system clock frequency can then be
847 * increased above 2 MHz.
848 * @retval HAL Status
849 */
HAL_PWREx_DisableLowPowerRunMode(void)850 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
851 {
852 uint32_t wait_loop_index;
853
854 /* Clear LPR bit */
855 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
856
857 /* Wait until REGLPF is reset */
858 wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000U));
859 while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U))
860 {
861 wait_loop_index--;
862 }
863 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
864 {
865 return HAL_TIMEOUT;
866 }
867
868 return HAL_OK;
869 }
870
871
872 /**
873 * @brief Enter Stop 0 mode.
874 * @note In Stop 0 mode, main and low voltage regulators are ON.
875 * @note In Stop 0 mode, all I/O pins keep the same state as in Run mode.
876 * @note All clocks in the VCORE domain are stopped; the PLL, the HSI
877 * and the HSE oscillators are disabled. Some peripherals with the wakeup capability
878 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
879 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
880 * only to the peripheral requesting it.
881 * SRAM1, SRAM2 and register contents are preserved.
882 * The BOR is available.
883 * @note When exiting Stop 0 mode by issuing an interrupt or a wakeup event,
884 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
885 * is set; the HSI oscillator is selected if STOPWUCK is cleared.
886 * @note By keeping the internal regulator ON during Stop 0 mode, the consumption
887 * is higher although the startup time is reduced.
888 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
889 * This parameter can be one of the following values:
890 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
891 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
892 * @retval None
893 */
HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)894 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)
895 {
896 /* Check the parameters */
897 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
898
899 /* Stop 0 mode with Main Regulator */
900 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0);
901
902 /* Set SLEEPDEEP bit of Cortex System Control Register */
903 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
904
905 /* Select Stop mode entry --------------------------------------------------*/
906 if(STOPEntry == PWR_STOPENTRY_WFI)
907 {
908 /* Request Wait For Interrupt */
909 __WFI();
910 }
911 else
912 {
913 /* Request Wait For Event */
914 __SEV();
915 __WFE();
916 __WFE();
917 }
918
919 /* Reset SLEEPDEEP bit of Cortex System Control Register */
920 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
921 }
922
923
924 /**
925 * @brief Enter Stop 1 mode.
926 * @note In Stop 1 mode, only low power voltage regulator is ON.
927 * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode.
928 * @note All clocks in the VCORE domain are stopped; the PLL, the HSI
929 * and the HSE oscillators are disabled. Some peripherals with the wakeup capability
930 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
931 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
932 * only to the peripheral requesting it.
933 * SRAM1, SRAM2 and register contents are preserved.
934 * The BOR is available.
935 * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event,
936 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
937 * is set.
938 * @note Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode.
939 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
940 * This parameter can be one of the following values:
941 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
942 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
943 * @retval None
944 */
HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)945 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)
946 {
947 /* Check the parameters */
948 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
949
950 /* Stop 1 mode with Low-Power Regulator */
951 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1);
952
953 /* Set SLEEPDEEP bit of Cortex System Control Register */
954 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
955
956 /* Select Stop mode entry --------------------------------------------------*/
957 if(STOPEntry == PWR_STOPENTRY_WFI)
958 {
959 /* Request Wait For Interrupt */
960 __WFI();
961 }
962 else
963 {
964 /* Request Wait For Event */
965 __SEV();
966 __WFE();
967 __WFE();
968 }
969
970 /* Reset SLEEPDEEP bit of Cortex System Control Register */
971 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
972 }
973
974
975
976
977 /**
978 * @brief Enter Shutdown mode.
979 * @note In Shutdown mode, the PLL, the HSI, the LSI and the HSE oscillators are switched
980 * off. The voltage regulator is disabled and Vcore domain is powered off.
981 * SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain.
982 * The BOR is not available.
983 * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
984 * @retval None
985 */
HAL_PWREx_EnterSHUTDOWNMode(void)986 void HAL_PWREx_EnterSHUTDOWNMode(void)
987 {
988
989 /* Set Shutdown mode */
990 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN);
991
992 /* Set SLEEPDEEP bit of Cortex System Control Register */
993 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
994
995 /* This option is used to ensure that store operations are completed */
996 #if defined ( __CC_ARM)
997 __force_stores();
998 #endif
999 /* Request Wait For Interrupt */
1000 __WFI();
1001 }
1002
1003
1004
1005
1006 /**
1007 * @brief This function handles the PWR PVD/PVMx interrupt request.
1008 * @note This API should be called under the PVD_PVM_IRQHandler().
1009 * @retval None
1010 */
HAL_PWREx_PVD_PVM_IRQHandler(void)1011 void HAL_PWREx_PVD_PVM_IRQHandler(void)
1012 {
1013 /* Check PWR exti flag */
1014 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != 0U)
1015 {
1016 /* PWR PVD interrupt user callback */
1017 HAL_PWR_PVDCallback();
1018
1019 /* Clear PVD exti pending bit */
1020 __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
1021 }
1022 /* Next, successively check PVMx exti flags */
1023 #if defined(PWR_CR2_PVME1)
1024 if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != 0U)
1025 {
1026 /* PWR PVM1 interrupt user callback */
1027 HAL_PWREx_PVM1Callback();
1028
1029 /* Clear PVM1 exti pending bit */
1030 __HAL_PWR_PVM1_EXTI_CLEAR_FLAG();
1031 }
1032 #endif /* PWR_CR2_PVME1 */
1033 #if defined(PWR_CR2_PVME2)
1034 if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != 0U)
1035 {
1036 /* PWR PVM2 interrupt user callback */
1037 HAL_PWREx_PVM2Callback();
1038
1039 /* Clear PVM2 exti pending bit */
1040 __HAL_PWR_PVM2_EXTI_CLEAR_FLAG();
1041 }
1042 #endif /* PWR_CR2_PVME2 */
1043 if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != 0U)
1044 {
1045 /* PWR PVM3 interrupt user callback */
1046 HAL_PWREx_PVM3Callback();
1047
1048 /* Clear PVM3 exti pending bit */
1049 __HAL_PWR_PVM3_EXTI_CLEAR_FLAG();
1050 }
1051 if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != 0U)
1052 {
1053 /* PWR PVM4 interrupt user callback */
1054 HAL_PWREx_PVM4Callback();
1055
1056 /* Clear PVM4 exti pending bit */
1057 __HAL_PWR_PVM4_EXTI_CLEAR_FLAG();
1058 }
1059 }
1060
1061
1062 #if defined(PWR_CR2_PVME1)
1063 /**
1064 * @brief PWR PVM1 interrupt callback
1065 * @retval None
1066 */
HAL_PWREx_PVM1Callback(void)1067 __weak void HAL_PWREx_PVM1Callback(void)
1068 {
1069 /* NOTE : This function should not be modified; when the callback is needed,
1070 HAL_PWREx_PVM1Callback() API can be implemented in the user file
1071 */
1072 }
1073 #endif /* PWR_CR2_PVME1 */
1074
1075 #if defined(PWR_CR2_PVME2)
1076 /**
1077 * @brief PWR PVM2 interrupt callback
1078 * @retval None
1079 */
HAL_PWREx_PVM2Callback(void)1080 __weak void HAL_PWREx_PVM2Callback(void)
1081 {
1082 /* NOTE : This function should not be modified; when the callback is needed,
1083 HAL_PWREx_PVM2Callback() API can be implemented in the user file
1084 */
1085 }
1086 #endif /* PWR_CR2_PVME2 */
1087
1088 /**
1089 * @brief PWR PVM3 interrupt callback
1090 * @retval None
1091 */
HAL_PWREx_PVM3Callback(void)1092 __weak void HAL_PWREx_PVM3Callback(void)
1093 {
1094 /* NOTE : This function should not be modified; when the callback is needed,
1095 HAL_PWREx_PVM3Callback() API can be implemented in the user file
1096 */
1097 }
1098
1099 /**
1100 * @brief PWR PVM4 interrupt callback
1101 * @retval None
1102 */
HAL_PWREx_PVM4Callback(void)1103 __weak void HAL_PWREx_PVM4Callback(void)
1104 {
1105 /* NOTE : This function should not be modified; when the callback is needed,
1106 HAL_PWREx_PVM4Callback() API can be implemented in the user file
1107 */
1108 }
1109
1110 #if defined(PWR_CR3_UCPD_STDBY)
1111 /**
1112 * @brief Enable UCPD configuration memorization in Standby.
1113 * @retval None
1114 */
HAL_PWREx_EnableUCPDStandbyMode(void)1115 void HAL_PWREx_EnableUCPDStandbyMode(void)
1116 {
1117 /* Memorize UCPD configuration when entering standby mode */
1118 SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
1119 }
1120
1121 /**
1122 * @brief Disable UCPD configuration memorization in Standby.
1123 * @note This function must be called on exiting the Standby mode and before any UCPD
1124 * configuration update.
1125 * @retval None
1126 */
HAL_PWREx_DisableUCPDStandbyMode(void)1127 void HAL_PWREx_DisableUCPDStandbyMode(void)
1128 {
1129 /* Write 0 immediately after Standby exit when using UCPD,
1130 and before writing any UCPD registers */
1131 CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
1132 }
1133 #endif /* PWR_CR3_UCPD_STDBY */
1134
1135 #if defined(PWR_CR3_UCPD_DBDIS)
1136 /**
1137 * @brief Enable the USB Type-C dead battery pull-down behavior
1138 * on UCPDx_CC1 and UCPDx_CC2 pins
1139 * @retval None
1140 */
HAL_PWREx_EnableUCPDDeadBattery(void)1141 void HAL_PWREx_EnableUCPDDeadBattery(void)
1142 {
1143 /* Write 0 to enable the USB Type-C dead battery pull-down behavior */
1144 CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
1145 }
1146
1147 /**
1148 * @brief Disable the USB Type-C dead battery pull-down behavior
1149 * on UCPDx_CC1 and UCPDx_CC2 pins
1150 * @note After exiting reset, the USB Type-C dead battery behavior will be enabled,
1151 * which may have a pull-down effect on CC1 and CC2 pins.
1152 * It is recommended to disable it in all cases, either to stop this pull-down
1153 * or to hand over control to the UCPD (which should therefore be
1154 * initialized before doing the disable).
1155 * @retval None
1156 */
HAL_PWREx_DisableUCPDDeadBattery(void)1157 void HAL_PWREx_DisableUCPDDeadBattery(void)
1158 {
1159 /* Write 1 to disable the USB Type-C dead battery pull-down behavior */
1160 SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
1161 }
1162 #endif /* PWR_CR3_UCPD_DBDIS */
1163
1164
1165
1166 /**
1167 * @}
1168 */
1169
1170 /**
1171 * @}
1172 */
1173
1174 #endif /* HAL_PWR_MODULE_ENABLED */
1175 /**
1176 * @}
1177 */
1178
1179 /**
1180 * @}
1181 */
1182
1183
