1 /**
2 ******************************************************************************
3 * @file stm32g0xx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2018 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32g0xx_ll_tim.h"
22 #include "stm32g0xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32G0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7)
35
36 /** @addtogroup TIM_LL
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /** @addtogroup TIM_LL_Private_Macros
45 * @{
46 */
47 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
48 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
49 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
50 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
51 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
52
53 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
54 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
55 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
56
57 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
58 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
59 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
60 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
61 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
62 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
63 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
64 || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
65 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
66 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
67 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
68 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
69 || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \
70 || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2))
71
72 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
73 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
74
75 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
76 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
77
78 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
79 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
80
81 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
82 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
83 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
84
85 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
86 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
87 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
88 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
89
90 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
91 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
92 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
93 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
94 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
95 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
96 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
97 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
98 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
99 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
100 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
101 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
102 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
103 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
104 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
105 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
106
107 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
108 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
109 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
110
111 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
112 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
113 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
114
115 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
116 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
117
118 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
119 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
120
121 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
122 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
123
124 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
125 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
126 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
127 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
128
129 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
130 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
131
132 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
133 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
134
135 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
136 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
137 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
138 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
139 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
140 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
141 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
142 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
143 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
144 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
145 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
146 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
147 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
148 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
149 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
150 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
151
152 #define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \
153 || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))
154
155 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
156 || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
157
158 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
159 || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
160
161 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
162 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
163 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
164 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
165 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
166 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
167 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
168 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
169 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
170 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
171 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
172 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
173 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
174 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
175 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
176 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
177
178 #define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \
179 || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))
180
181 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
182 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
183 /**
184 * @}
185 */
186
187
188 /* Private function prototypes -----------------------------------------------*/
189 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
190 * @{
191 */
192 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
193 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
194 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
195 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
196 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
197 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
198 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
199 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
200 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
201 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
202 /**
203 * @}
204 */
205
206 /* Exported functions --------------------------------------------------------*/
207 /** @addtogroup TIM_LL_Exported_Functions
208 * @{
209 */
210
211 /** @addtogroup TIM_LL_EF_Init
212 * @{
213 */
214
215 /**
216 * @brief Set TIMx registers to their reset values.
217 * @param TIMx Timer instance
218 * @retval An ErrorStatus enumeration value:
219 * - SUCCESS: TIMx registers are de-initialized
220 * - ERROR: invalid TIMx instance
221 */
LL_TIM_DeInit(const TIM_TypeDef * TIMx)222 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)
223 {
224 ErrorStatus result = SUCCESS;
225
226 /* Check the parameters */
227 assert_param(IS_TIM_INSTANCE(TIMx));
228
229 if (TIMx == TIM1)
230 {
231 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
232 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
233 }
234 #if defined(TIM2)
235 else if (TIMx == TIM2)
236 {
237 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
238 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
239 }
240 #endif /* TIM2 */
241 #if defined(TIM3)
242 else if (TIMx == TIM3)
243 {
244 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
245 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
246 }
247 #endif /* TIM3 */
248 #if defined(TIM4)
249 else if (TIMx == TIM4)
250 {
251 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
252 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
253 }
254 #endif /* TIM4 */
255 #if defined(TIM6)
256 else if (TIMx == TIM6)
257 {
258 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
259 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
260 }
261 #endif /* TIM6 */
262 #if defined(TIM7)
263 else if (TIMx == TIM7)
264 {
265 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
266 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
267 }
268 #endif /* TIM7 */
269 else if (TIMx == TIM14)
270 {
271 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM14);
272 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM14);
273 }
274 #if defined(TIM15)
275 else if (TIMx == TIM15)
276 {
277 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
278 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
279 }
280 #endif /* TIM15 */
281 else if (TIMx == TIM16)
282 {
283 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
284 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
285 }
286 #if defined(TIM17)
287 else if (TIMx == TIM17)
288 {
289 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
290 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
291 }
292 #endif /* TIM17 */
293 else
294 {
295 result = ERROR;
296 }
297
298 return result;
299 }
300
301 /**
302 * @brief Set the fields of the time base unit configuration data structure
303 * to their default values.
304 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
305 * @retval None
306 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)307 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
308 {
309 /* Set the default configuration */
310 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
311 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
312 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
313 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
314 TIM_InitStruct->RepetitionCounter = 0x00000000U;
315 }
316
317 /**
318 * @brief Configure the TIMx time base unit.
319 * @param TIMx Timer Instance
320 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
321 * (TIMx time base unit configuration data structure)
322 * @retval An ErrorStatus enumeration value:
323 * - SUCCESS: TIMx registers are de-initialized
324 * - ERROR: not applicable
325 */
LL_TIM_Init(TIM_TypeDef * TIMx,const LL_TIM_InitTypeDef * TIM_InitStruct)326 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
327 {
328 uint32_t tmpcr1;
329
330 /* Check the parameters */
331 assert_param(IS_TIM_INSTANCE(TIMx));
332 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
333 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
334
335 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
336
337 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
338 {
339 /* Select the Counter Mode */
340 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
341 }
342
343 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
344 {
345 /* Set the clock division */
346 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
347 }
348
349 /* Write to TIMx CR1 */
350 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
351
352 /* Set the Autoreload value */
353 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
354
355 /* Set the Prescaler value */
356 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
357
358 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
359 {
360 /* Set the Repetition Counter value */
361 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
362 }
363
364 /* Generate an update event to reload the Prescaler
365 and the repetition counter value (if applicable) immediately */
366 LL_TIM_GenerateEvent_UPDATE(TIMx);
367
368 return SUCCESS;
369 }
370
371 /**
372 * @brief Set the fields of the TIMx output channel configuration data
373 * structure to their default values.
374 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
375 * (the output channel configuration data structure)
376 * @retval None
377 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)378 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
379 {
380 /* Set the default configuration */
381 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
382 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
383 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
384 TIM_OC_InitStruct->CompareValue = 0x00000000U;
385 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
386 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
387 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
388 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
389 }
390
391 /**
392 * @brief Configure the TIMx output channel.
393 * @param TIMx Timer Instance
394 * @param Channel This parameter can be one of the following values:
395 * @arg @ref LL_TIM_CHANNEL_CH1
396 * @arg @ref LL_TIM_CHANNEL_CH2
397 * @arg @ref LL_TIM_CHANNEL_CH3
398 * @arg @ref LL_TIM_CHANNEL_CH4
399 * @arg @ref LL_TIM_CHANNEL_CH5
400 * @arg @ref LL_TIM_CHANNEL_CH6
401 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
402 * data structure)
403 * @retval An ErrorStatus enumeration value:
404 * - SUCCESS: TIMx output channel is initialized
405 * - ERROR: TIMx output channel is not initialized
406 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)407 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
408 {
409 ErrorStatus result = ERROR;
410
411 switch (Channel)
412 {
413 case LL_TIM_CHANNEL_CH1:
414 result = OC1Config(TIMx, TIM_OC_InitStruct);
415 break;
416 case LL_TIM_CHANNEL_CH2:
417 result = OC2Config(TIMx, TIM_OC_InitStruct);
418 break;
419 case LL_TIM_CHANNEL_CH3:
420 result = OC3Config(TIMx, TIM_OC_InitStruct);
421 break;
422 case LL_TIM_CHANNEL_CH4:
423 result = OC4Config(TIMx, TIM_OC_InitStruct);
424 break;
425 case LL_TIM_CHANNEL_CH5:
426 result = OC5Config(TIMx, TIM_OC_InitStruct);
427 break;
428 case LL_TIM_CHANNEL_CH6:
429 result = OC6Config(TIMx, TIM_OC_InitStruct);
430 break;
431 default:
432 break;
433 }
434
435 return result;
436 }
437
438 /**
439 * @brief Set the fields of the TIMx input channel configuration data
440 * structure to their default values.
441 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
442 * data structure)
443 * @retval None
444 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)445 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
446 {
447 /* Set the default configuration */
448 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
449 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
450 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
451 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
452 }
453
454 /**
455 * @brief Configure the TIMx input channel.
456 * @param TIMx Timer Instance
457 * @param Channel This parameter can be one of the following values:
458 * @arg @ref LL_TIM_CHANNEL_CH1
459 * @arg @ref LL_TIM_CHANNEL_CH2
460 * @arg @ref LL_TIM_CHANNEL_CH3
461 * @arg @ref LL_TIM_CHANNEL_CH4
462 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
463 * structure)
464 * @retval An ErrorStatus enumeration value:
465 * - SUCCESS: TIMx output channel is initialized
466 * - ERROR: TIMx output channel is not initialized
467 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)468 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
469 {
470 ErrorStatus result = ERROR;
471
472 switch (Channel)
473 {
474 case LL_TIM_CHANNEL_CH1:
475 result = IC1Config(TIMx, TIM_IC_InitStruct);
476 break;
477 case LL_TIM_CHANNEL_CH2:
478 result = IC2Config(TIMx, TIM_IC_InitStruct);
479 break;
480 case LL_TIM_CHANNEL_CH3:
481 result = IC3Config(TIMx, TIM_IC_InitStruct);
482 break;
483 case LL_TIM_CHANNEL_CH4:
484 result = IC4Config(TIMx, TIM_IC_InitStruct);
485 break;
486 default:
487 break;
488 }
489
490 return result;
491 }
492
493 /**
494 * @brief Fills each TIM_EncoderInitStruct field with its default value
495 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
496 * configuration data structure)
497 * @retval None
498 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)499 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
500 {
501 /* Set the default configuration */
502 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
503 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
504 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
505 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
506 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
507 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
508 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
509 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
510 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
511 }
512
513 /**
514 * @brief Configure the encoder interface of the timer instance.
515 * @param TIMx Timer Instance
516 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
517 * configuration data structure)
518 * @retval An ErrorStatus enumeration value:
519 * - SUCCESS: TIMx registers are de-initialized
520 * - ERROR: not applicable
521 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,const LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)522 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
523 {
524 uint32_t tmpccmr1;
525 uint32_t tmpccer;
526
527 /* Check the parameters */
528 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
529 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
530 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
531 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
532 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
533 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
534 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
535 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
536 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
537 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
538
539 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
540 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
541
542 /* Get the TIMx CCMR1 register value */
543 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
544
545 /* Get the TIMx CCER register value */
546 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
547
548 /* Configure TI1 */
549 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
550 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
551 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
552 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
553
554 /* Configure TI2 */
555 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
556 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
557 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
558 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
559
560 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
561 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
562 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
563 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
564 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
565
566 /* Set encoder mode */
567 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
568
569 /* Write to TIMx CCMR1 */
570 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
571
572 /* Write to TIMx CCER */
573 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
574
575 return SUCCESS;
576 }
577
578 /**
579 * @brief Set the fields of the TIMx Hall sensor interface configuration data
580 * structure to their default values.
581 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
582 * configuration data structure)
583 * @retval None
584 */
LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)585 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
586 {
587 /* Set the default configuration */
588 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
589 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
590 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
591 TIM_HallSensorInitStruct->CommutationDelay = 0U;
592 }
593
594 /**
595 * @brief Configure the Hall sensor interface of the timer instance.
596 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
597 * to the TI1 input channel
598 * @note TIMx slave mode controller is configured in reset mode.
599 Selected internal trigger is TI1F_ED.
600 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
601 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
602 * between 2 changes on the inputs. It gives information about motor speed.
603 * @note Channel 2 is configured in output PWM 2 mode.
604 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
605 * @note OC2REF is selected as trigger output on TRGO.
606 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
607 * when TIMx operates in Hall sensor interface mode.
608 * @param TIMx Timer Instance
609 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
610 * interface configuration data structure)
611 * @retval An ErrorStatus enumeration value:
612 * - SUCCESS: TIMx registers are de-initialized
613 * - ERROR: not applicable
614 */
LL_TIM_HALLSENSOR_Init(TIM_TypeDef * TIMx,const LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)615 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
616 {
617 uint32_t tmpcr2;
618 uint32_t tmpccmr1;
619 uint32_t tmpccer;
620 uint32_t tmpsmcr;
621
622 /* Check the parameters */
623 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
624 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
625 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
626 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
627
628 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
629 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
630
631 /* Get the TIMx CR2 register value */
632 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
633
634 /* Get the TIMx CCMR1 register value */
635 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
636
637 /* Get the TIMx CCER register value */
638 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
639
640 /* Get the TIMx SMCR register value */
641 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
642
643 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
644 tmpcr2 |= TIM_CR2_TI1S;
645
646 /* OC2REF signal is used as trigger output (TRGO) */
647 tmpcr2 |= LL_TIM_TRGO_OC2REF;
648
649 /* Configure the slave mode controller */
650 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
651 tmpsmcr |= LL_TIM_TS_TI1F_ED;
652 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
653
654 /* Configure input channel 1 */
655 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
656 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
657 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
658 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
659
660 /* Configure input channel 2 */
661 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
662 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
663
664 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
665 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
666 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
667 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
668
669 /* Write to TIMx CR2 */
670 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
671
672 /* Write to TIMx SMCR */
673 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
674
675 /* Write to TIMx CCMR1 */
676 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
677
678 /* Write to TIMx CCER */
679 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
680
681 /* Write to TIMx CCR2 */
682 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
683
684 return SUCCESS;
685 }
686
687 /**
688 * @brief Set the fields of the Break and Dead Time configuration data structure
689 * to their default values.
690 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
691 * data structure)
692 * @retval None
693 */
LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)694 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
695 {
696 /* Set the default configuration */
697 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
698 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
699 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
700 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
701 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
702 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
703 TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
704 TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT;
705 TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
706 TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
707 TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
708 TIM_BDTRInitStruct->Break2AFMode = LL_TIM_BREAK2_AFMODE_INPUT;
709 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
710 }
711
712 /**
713 * @brief Configure the Break and Dead Time feature of the timer instance.
714 * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
715 * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
716 * can be necessary to configure all of them during the first write access to
717 * the TIMx_BDTR register.
718 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
719 * a timer instance provides a break input.
720 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
721 * a timer instance provides a second break input.
722 * @param TIMx Timer Instance
723 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
724 * data structure)
725 * @retval An ErrorStatus enumeration value:
726 * - SUCCESS: Break and Dead Time is initialized
727 * - ERROR: not applicable
728 */
LL_TIM_BDTR_Init(TIM_TypeDef * TIMx,const LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)729 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
730 {
731 uint32_t tmpbdtr = 0;
732
733 /* Check the parameters */
734 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
735 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
736 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
737 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
738 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
739 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
740 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
741 assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
742 assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
743
744 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
745 the OSSI State, the dead time value and the Automatic Output Enable Bit */
746
747 /* Set the BDTR bits */
748 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
749 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
750 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
751 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
752 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
753 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
754 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
755 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
756 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
757
758 if (IS_TIM_BKIN2_INSTANCE(TIMx))
759 {
760 assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
761 assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
762 assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
763 assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode));
764
765 /* Set the BREAK2 input related BDTR bit-fields */
766 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
767 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
768 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
769 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode);
770 }
771
772 /* Set TIMx_BDTR */
773 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
774
775 return SUCCESS;
776 }
777 /**
778 * @}
779 */
780
781 /**
782 * @}
783 */
784
785 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
786 * @brief Private functions
787 * @{
788 */
789 /**
790 * @brief Configure the TIMx output channel 1.
791 * @param TIMx Timer Instance
792 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
793 * @retval An ErrorStatus enumeration value:
794 * - SUCCESS: TIMx registers are de-initialized
795 * - ERROR: not applicable
796 */
OC1Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)797 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
798 {
799 uint32_t tmpccmr1;
800 uint32_t tmpccer;
801 uint32_t tmpcr2;
802
803 /* Check the parameters */
804 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
805 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
806 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
807 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
808
809 /* Disable the Channel 1: Reset the CC1E Bit */
810 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
811
812 /* Get the TIMx CCER register value */
813 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
814
815 /* Get the TIMx CR2 register value */
816 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
817
818 /* Get the TIMx CCMR1 register value */
819 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
820
821 /* Reset Capture/Compare selection Bits */
822 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
823
824 /* Set the Output Compare Mode */
825 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
826
827 /* Set the Output Compare Polarity */
828 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
829
830 /* Set the Output State */
831 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
832
833 if (IS_TIM_BREAK_INSTANCE(TIMx))
834 {
835 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
836 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
837 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
838 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
839
840 /* Set the complementary output Polarity */
841 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
842
843 /* Set the complementary output State */
844 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
845
846 /* Set the Output Idle state */
847 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
848
849 /* Set the complementary output Idle state */
850 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
851 }
852
853 /* Write to TIMx CR2 */
854 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
855
856 /* Write to TIMx CCMR1 */
857 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
858
859 /* Set the Capture Compare Register value */
860 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
861
862 /* Write to TIMx CCER */
863 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
864
865 return SUCCESS;
866 }
867
868 /**
869 * @brief Configure the TIMx output channel 2.
870 * @param TIMx Timer Instance
871 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
872 * @retval An ErrorStatus enumeration value:
873 * - SUCCESS: TIMx registers are de-initialized
874 * - ERROR: not applicable
875 */
OC2Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)876 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
877 {
878 uint32_t tmpccmr1;
879 uint32_t tmpccer;
880 uint32_t tmpcr2;
881
882 /* Check the parameters */
883 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
884 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
885 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
886 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
887
888 /* Disable the Channel 2: Reset the CC2E Bit */
889 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
890
891 /* Get the TIMx CCER register value */
892 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
893
894 /* Get the TIMx CR2 register value */
895 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
896
897 /* Get the TIMx CCMR1 register value */
898 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
899
900 /* Reset Capture/Compare selection Bits */
901 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
902
903 /* Select the Output Compare Mode */
904 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
905
906 /* Set the Output Compare Polarity */
907 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
908
909 /* Set the Output State */
910 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
911
912 if (IS_TIM_BREAK_INSTANCE(TIMx))
913 {
914 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
915 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
916 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
917 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
918
919 /* Set the complementary output Polarity */
920 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
921
922 /* Set the complementary output State */
923 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
924
925 /* Set the Output Idle state */
926 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
927
928 /* Set the complementary output Idle state */
929 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
930 }
931
932 /* Write to TIMx CR2 */
933 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
934
935 /* Write to TIMx CCMR1 */
936 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
937
938 /* Set the Capture Compare Register value */
939 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
940
941 /* Write to TIMx CCER */
942 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
943
944 return SUCCESS;
945 }
946
947 /**
948 * @brief Configure the TIMx output channel 3.
949 * @param TIMx Timer Instance
950 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
951 * @retval An ErrorStatus enumeration value:
952 * - SUCCESS: TIMx registers are de-initialized
953 * - ERROR: not applicable
954 */
OC3Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)955 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
956 {
957 uint32_t tmpccmr2;
958 uint32_t tmpccer;
959 uint32_t tmpcr2;
960
961 /* Check the parameters */
962 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
963 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
964 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
965 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
966
967 /* Disable the Channel 3: Reset the CC3E Bit */
968 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
969
970 /* Get the TIMx CCER register value */
971 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
972
973 /* Get the TIMx CR2 register value */
974 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
975
976 /* Get the TIMx CCMR2 register value */
977 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
978
979 /* Reset Capture/Compare selection Bits */
980 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
981
982 /* Select the Output Compare Mode */
983 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
984
985 /* Set the Output Compare Polarity */
986 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
987
988 /* Set the Output State */
989 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
990
991 if (IS_TIM_BREAK_INSTANCE(TIMx))
992 {
993 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
994 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
995 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
996 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
997
998 /* Set the complementary output Polarity */
999 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
1000
1001 /* Set the complementary output State */
1002 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
1003
1004 /* Set the Output Idle state */
1005 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
1006
1007 /* Set the complementary output Idle state */
1008 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
1009 }
1010
1011 /* Write to TIMx CR2 */
1012 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1013
1014 /* Write to TIMx CCMR2 */
1015 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1016
1017 /* Set the Capture Compare Register value */
1018 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
1019
1020 /* Write to TIMx CCER */
1021 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1022
1023 return SUCCESS;
1024 }
1025
1026 /**
1027 * @brief Configure the TIMx output channel 4.
1028 * @param TIMx Timer Instance
1029 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
1030 * @retval An ErrorStatus enumeration value:
1031 * - SUCCESS: TIMx registers are de-initialized
1032 * - ERROR: not applicable
1033 */
OC4Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1034 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1035 {
1036 uint32_t tmpccmr2;
1037 uint32_t tmpccer;
1038 uint32_t tmpcr2;
1039
1040 /* Check the parameters */
1041 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1042 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1043 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1044 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1045
1046 /* Disable the Channel 4: Reset the CC4E Bit */
1047 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1048
1049 /* Get the TIMx CCER register value */
1050 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1051
1052 /* Get the TIMx CR2 register value */
1053 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1054
1055 /* Get the TIMx CCMR2 register value */
1056 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1057
1058 /* Reset Capture/Compare selection Bits */
1059 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1060
1061 /* Select the Output Compare Mode */
1062 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1063
1064 /* Set the Output Compare Polarity */
1065 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1066
1067 /* Set the Output State */
1068 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1069
1070 if (IS_TIM_BREAK_INSTANCE(TIMx))
1071 {
1072 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1073
1074 /* Set the Output Idle state */
1075 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1076 }
1077
1078 /* Write to TIMx CR2 */
1079 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1080
1081 /* Write to TIMx CCMR2 */
1082 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1083
1084 /* Set the Capture Compare Register value */
1085 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1086
1087 /* Write to TIMx CCER */
1088 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1089
1090 return SUCCESS;
1091 }
1092
1093 /**
1094 * @brief Configure the TIMx output channel 5.
1095 * @param TIMx Timer Instance
1096 * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
1097 * @retval An ErrorStatus enumeration value:
1098 * - SUCCESS: TIMx registers are de-initialized
1099 * - ERROR: not applicable
1100 */
OC5Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1101 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1102 {
1103 uint32_t tmpccmr3;
1104 uint32_t tmpccer;
1105
1106 /* Check the parameters */
1107 assert_param(IS_TIM_CC5_INSTANCE(TIMx));
1108 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1109 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1110 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1111 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1112 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1113
1114 /* Disable the Channel 5: Reset the CC5E Bit */
1115 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1116
1117 /* Get the TIMx CCER register value */
1118 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1119
1120 /* Get the TIMx CCMR3 register value */
1121 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1122
1123 /* Select the Output Compare Mode */
1124 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1125
1126 /* Set the Output Compare Polarity */
1127 MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1128
1129 /* Set the Output State */
1130 MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1131
1132 if (IS_TIM_BREAK_INSTANCE(TIMx))
1133 {
1134 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1135 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1136
1137 /* Set the Output Idle state */
1138 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1139
1140 }
1141
1142 /* Write to TIMx CCMR3 */
1143 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1144
1145 /* Set the Capture Compare Register value */
1146 LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1147
1148 /* Write to TIMx CCER */
1149 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1150
1151 return SUCCESS;
1152 }
1153
1154 /**
1155 * @brief Configure the TIMx output channel 6.
1156 * @param TIMx Timer Instance
1157 * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1158 * @retval An ErrorStatus enumeration value:
1159 * - SUCCESS: TIMx registers are de-initialized
1160 * - ERROR: not applicable
1161 */
OC6Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1162 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1163 {
1164 uint32_t tmpccmr3;
1165 uint32_t tmpccer;
1166
1167 /* Check the parameters */
1168 assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1169 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1170 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1171 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1172 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1173 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1174
1175 /* Disable the Channel 5: Reset the CC6E Bit */
1176 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1177
1178 /* Get the TIMx CCER register value */
1179 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1180
1181 /* Get the TIMx CCMR3 register value */
1182 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1183
1184 /* Select the Output Compare Mode */
1185 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1186
1187 /* Set the Output Compare Polarity */
1188 MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1189
1190 /* Set the Output State */
1191 MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1192
1193 if (IS_TIM_BREAK_INSTANCE(TIMx))
1194 {
1195 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1196 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1197
1198 /* Set the Output Idle state */
1199 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1200 }
1201
1202 /* Write to TIMx CCMR3 */
1203 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1204
1205 /* Set the Capture Compare Register value */
1206 LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1207
1208 /* Write to TIMx CCER */
1209 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1210
1211 return SUCCESS;
1212 }
1213
1214 /**
1215 * @brief Configure the TIMx input channel 1.
1216 * @param TIMx Timer Instance
1217 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1218 * @retval An ErrorStatus enumeration value:
1219 * - SUCCESS: TIMx registers are de-initialized
1220 * - ERROR: not applicable
1221 */
IC1Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1222 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1223 {
1224 /* Check the parameters */
1225 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1226 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1227 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1228 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1229 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1230
1231 /* Disable the Channel 1: Reset the CC1E Bit */
1232 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1233
1234 /* Select the Input and set the filter and the prescaler value */
1235 MODIFY_REG(TIMx->CCMR1,
1236 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1237 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1238
1239 /* Select the Polarity and set the CC1E Bit */
1240 MODIFY_REG(TIMx->CCER,
1241 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1242 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1243
1244 return SUCCESS;
1245 }
1246
1247 /**
1248 * @brief Configure the TIMx input channel 2.
1249 * @param TIMx Timer Instance
1250 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1251 * @retval An ErrorStatus enumeration value:
1252 * - SUCCESS: TIMx registers are de-initialized
1253 * - ERROR: not applicable
1254 */
IC2Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1255 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1256 {
1257 /* Check the parameters */
1258 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1259 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1260 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1261 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1262 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1263
1264 /* Disable the Channel 2: Reset the CC2E Bit */
1265 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1266
1267 /* Select the Input and set the filter and the prescaler value */
1268 MODIFY_REG(TIMx->CCMR1,
1269 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1270 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1271
1272 /* Select the Polarity and set the CC2E Bit */
1273 MODIFY_REG(TIMx->CCER,
1274 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1275 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1276
1277 return SUCCESS;
1278 }
1279
1280 /**
1281 * @brief Configure the TIMx input channel 3.
1282 * @param TIMx Timer Instance
1283 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1284 * @retval An ErrorStatus enumeration value:
1285 * - SUCCESS: TIMx registers are de-initialized
1286 * - ERROR: not applicable
1287 */
IC3Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1288 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1289 {
1290 /* Check the parameters */
1291 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1292 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1293 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1294 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1295 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1296
1297 /* Disable the Channel 3: Reset the CC3E Bit */
1298 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1299
1300 /* Select the Input and set the filter and the prescaler value */
1301 MODIFY_REG(TIMx->CCMR2,
1302 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1303 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1304
1305 /* Select the Polarity and set the CC3E Bit */
1306 MODIFY_REG(TIMx->CCER,
1307 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1308 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1309
1310 return SUCCESS;
1311 }
1312
1313 /**
1314 * @brief Configure the TIMx input channel 4.
1315 * @param TIMx Timer Instance
1316 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1317 * @retval An ErrorStatus enumeration value:
1318 * - SUCCESS: TIMx registers are de-initialized
1319 * - ERROR: not applicable
1320 */
IC4Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1321 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1322 {
1323 /* Check the parameters */
1324 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1325 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1326 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1327 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1328 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1329
1330 /* Disable the Channel 4: Reset the CC4E Bit */
1331 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1332
1333 /* Select the Input and set the filter and the prescaler value */
1334 MODIFY_REG(TIMx->CCMR2,
1335 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1336 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1337
1338 /* Select the Polarity and set the CC4E Bit */
1339 MODIFY_REG(TIMx->CCER,
1340 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1341 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1342
1343 return SUCCESS;
1344 }
1345
1346
1347 /**
1348 * @}
1349 */
1350
1351 /**
1352 * @}
1353 */
1354
1355 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM14 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */
1356
1357 /**
1358 * @}
1359 */
1360
1361 #endif /* USE_FULL_LL_DRIVER */
1362
1363
