1 /**
2 ******************************************************************************
3 * @file stm32g0xx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2018 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32g0xx_ll_tim.h"
22 #include "stm32g0xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32G0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7)
35
36 /** @addtogroup TIM_LL
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /** @addtogroup TIM_LL_Private_Macros
45 * @{
46 */
47 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
48 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
49 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
50 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
51 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
52
53 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
54 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
55 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
56
57 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
58 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
59 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
60 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
61 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
62 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
63 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
64 || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
65 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
66 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
67 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
68 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
69 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
70 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
71
72 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
73 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
74
75 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
76 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
77
78 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
79 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
80
81 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
82 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
83 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
84
85 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
86 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
87 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
88 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
89
90 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
91 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
92 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
93 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
94 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
95 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
96 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
97 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
98 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
99 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
100 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
101 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
102 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
103 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
104 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
105 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
106
107 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
108 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
109 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
110
111 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
112 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
113 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
114
115 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
116 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
117
118 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
119 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
120
121 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
122 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
123
124 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
125 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
126 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
127 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
128
129 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
130 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
131
132 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
133 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
134
135 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
136 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
137 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
138 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
139 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
140 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
141 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
142 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
143 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
144 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
145 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
146 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
147 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
148 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
149 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
150 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
151
152 #define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \
153 || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))
154
155 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
156 || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
157
158 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
159 || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
160
161 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
162 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
163 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
164 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
165 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
166 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
167 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
168 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
169 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
170 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
171 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
172 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
173 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
174 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
175 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
176 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
177
178 #define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \
179 || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))
180
181 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
182 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
183 /**
184 * @}
185 */
186
187
188 /* Private function prototypes -----------------------------------------------*/
189 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
190 * @{
191 */
192 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
193 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
194 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
195 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
196 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
197 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
198 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
199 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
200 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
201 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
202 /**
203 * @}
204 */
205
206 /* Exported functions --------------------------------------------------------*/
207 /** @addtogroup TIM_LL_Exported_Functions
208 * @{
209 */
210
211 /** @addtogroup TIM_LL_EF_Init
212 * @{
213 */
214
215 /**
216 * @brief Set TIMx registers to their reset values.
217 * @param TIMx Timer instance
218 * @retval An ErrorStatus enumeration value:
219 * - SUCCESS: TIMx registers are de-initialized
220 * - ERROR: invalid TIMx instance
221 */
LL_TIM_DeInit(TIM_TypeDef * TIMx)222 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
223 {
224 ErrorStatus result = SUCCESS;
225
226 /* Check the parameters */
227 assert_param(IS_TIM_INSTANCE(TIMx));
228
229 if (TIMx == TIM1)
230 {
231 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
232 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
233 }
234 #if defined(TIM2)
235 else if (TIMx == TIM2)
236 {
237 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
238 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
239 }
240 #endif /* TIM2 */
241 #if defined(TIM3)
242 else if (TIMx == TIM3)
243 {
244 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
245 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
246 }
247 #endif /* TIM3 */
248 #if defined(TIM4)
249 else if (TIMx == TIM4)
250 {
251 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
252 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
253 }
254 #endif /* TIM4 */
255 #if defined(TIM6)
256 else if (TIMx == TIM6)
257 {
258 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
259 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
260 }
261 #endif /* TIM6 */
262 #if defined(TIM7)
263 else if (TIMx == TIM7)
264 {
265 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
266 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
267 }
268 #endif /* TIM7 */
269 else if (TIMx == TIM14)
270 {
271 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM14);
272 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM14);
273 }
274 #if defined(TIM15)
275 else if (TIMx == TIM15)
276 {
277 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
278 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
279 }
280 #endif /* TIM15 */
281 else if (TIMx == TIM16)
282 {
283 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
284 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
285 }
286 #if defined(TIM17)
287 else if (TIMx == TIM17)
288 {
289 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
290 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
291 }
292 #endif /* TIM17 */
293 else
294 {
295 result = ERROR;
296 }
297
298 return result;
299 }
300
301 /**
302 * @brief Set the fields of the time base unit configuration data structure
303 * to their default values.
304 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
305 * @retval None
306 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)307 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
308 {
309 /* Set the default configuration */
310 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
311 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
312 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
313 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
314 TIM_InitStruct->RepetitionCounter = 0x00000000U;
315 }
316
317 /**
318 * @brief Configure the TIMx time base unit.
319 * @param TIMx Timer Instance
320 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
321 * (TIMx time base unit configuration data structure)
322 * @retval An ErrorStatus enumeration value:
323 * - SUCCESS: TIMx registers are de-initialized
324 * - ERROR: not applicable
325 */
LL_TIM_Init(TIM_TypeDef * TIMx,const LL_TIM_InitTypeDef * TIM_InitStruct)326 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
327 {
328 uint32_t tmpcr1;
329
330 /* Check the parameters */
331 assert_param(IS_TIM_INSTANCE(TIMx));
332 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
333 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
334
335 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
336
337 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
338 {
339 /* Select the Counter Mode */
340 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
341 }
342
343 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
344 {
345 /* Set the clock division */
346 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
347 }
348
349 /* Write to TIMx CR1 */
350 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
351
352 /* Set the Autoreload value */
353 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
354
355 /* Set the Prescaler value */
356 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
357
358 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
359 {
360 /* Set the Repetition Counter value */
361 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
362 }
363
364 /* Generate an update event to reload the Prescaler
365 and the repetition counter value (if applicable) immediately */
366 LL_TIM_GenerateEvent_UPDATE(TIMx);
367
368 return SUCCESS;
369 }
370
371 /**
372 * @brief Set the fields of the TIMx output channel configuration data
373 * structure to their default values.
374 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
375 * (the output channel configuration data structure)
376 * @retval None
377 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)378 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
379 {
380 /* Set the default configuration */
381 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
382 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
383 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
384 TIM_OC_InitStruct->CompareValue = 0x00000000U;
385 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
386 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
387 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
388 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
389 }
390
391 /**
392 * @brief Configure the TIMx output channel.
393 * @param TIMx Timer Instance
394 * @param Channel This parameter can be one of the following values:
395 * @arg @ref LL_TIM_CHANNEL_CH1
396 * @arg @ref LL_TIM_CHANNEL_CH2
397 * @arg @ref LL_TIM_CHANNEL_CH3
398 * @arg @ref LL_TIM_CHANNEL_CH4
399 * @arg @ref LL_TIM_CHANNEL_CH5
400 * @arg @ref LL_TIM_CHANNEL_CH6
401 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
402 * data structure)
403 * @retval An ErrorStatus enumeration value:
404 * - SUCCESS: TIMx output channel is initialized
405 * - ERROR: TIMx output channel is not initialized
406 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)407 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
408 {
409 ErrorStatus result = ERROR;
410
411 switch (Channel)
412 {
413 case LL_TIM_CHANNEL_CH1:
414 result = OC1Config(TIMx, TIM_OC_InitStruct);
415 break;
416 case LL_TIM_CHANNEL_CH2:
417 result = OC2Config(TIMx, TIM_OC_InitStruct);
418 break;
419 case LL_TIM_CHANNEL_CH3:
420 result = OC3Config(TIMx, TIM_OC_InitStruct);
421 break;
422 case LL_TIM_CHANNEL_CH4:
423 result = OC4Config(TIMx, TIM_OC_InitStruct);
424 break;
425 case LL_TIM_CHANNEL_CH5:
426 result = OC5Config(TIMx, TIM_OC_InitStruct);
427 break;
428 case LL_TIM_CHANNEL_CH6:
429 result = OC6Config(TIMx, TIM_OC_InitStruct);
430 break;
431 default:
432 break;
433 }
434
435 return result;
436 }
437
438 /**
439 * @brief Set the fields of the TIMx input channel configuration data
440 * structure to their default values.
441 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
442 * data structure)
443 * @retval None
444 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)445 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
446 {
447 /* Set the default configuration */
448 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
449 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
450 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
451 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
452 }
453
454 /**
455 * @brief Configure the TIMx input channel.
456 * @param TIMx Timer Instance
457 * @param Channel This parameter can be one of the following values:
458 * @arg @ref LL_TIM_CHANNEL_CH1
459 * @arg @ref LL_TIM_CHANNEL_CH2
460 * @arg @ref LL_TIM_CHANNEL_CH3
461 * @arg @ref LL_TIM_CHANNEL_CH4
462 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
463 * structure)
464 * @retval An ErrorStatus enumeration value:
465 * - SUCCESS: TIMx output channel is initialized
466 * - ERROR: TIMx output channel is not initialized
467 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)468 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
469 {
470 ErrorStatus result = ERROR;
471
472 switch (Channel)
473 {
474 case LL_TIM_CHANNEL_CH1:
475 result = IC1Config(TIMx, TIM_IC_InitStruct);
476 break;
477 case LL_TIM_CHANNEL_CH2:
478 result = IC2Config(TIMx, TIM_IC_InitStruct);
479 break;
480 case LL_TIM_CHANNEL_CH3:
481 result = IC3Config(TIMx, TIM_IC_InitStruct);
482 break;
483 case LL_TIM_CHANNEL_CH4:
484 result = IC4Config(TIMx, TIM_IC_InitStruct);
485 break;
486 default:
487 break;
488 }
489
490 return result;
491 }
492
493 /**
494 * @brief Fills each TIM_EncoderInitStruct field with its default value
495 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
496 * configuration data structure)
497 * @retval None
498 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)499 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
500 {
501 /* Set the default configuration */
502 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
503 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
504 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
505 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
506 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
507 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
508 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
509 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
510 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
511 }
512
513 /**
514 * @brief Configure the encoder interface of the timer instance.
515 * @param TIMx Timer Instance
516 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
517 * configuration data structure)
518 * @retval An ErrorStatus enumeration value:
519 * - SUCCESS: TIMx registers are de-initialized
520 * - ERROR: not applicable
521 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,const LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)522 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
523 {
524 uint32_t tmpccmr1;
525 uint32_t tmpccer;
526
527 /* Check the parameters */
528 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
529 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
530 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
531 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
532 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
533 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
534 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
535 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
536 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
537 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
538
539 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
540 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
541
542 /* Get the TIMx CCMR1 register value */
543 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
544
545 /* Get the TIMx CCER register value */
546 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
547
548 /* Configure TI1 */
549 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
550 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
551 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
552 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
553
554 /* Configure TI2 */
555 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
556 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
557 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
558 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
559
560 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
561 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
562 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
563 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
564 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
565
566 /* Set encoder mode */
567 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
568
569 /* Write to TIMx CCMR1 */
570 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
571
572 /* Write to TIMx CCER */
573 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
574
575 return SUCCESS;
576 }
577
578 /**
579 * @brief Set the fields of the TIMx Hall sensor interface configuration data
580 * structure to their default values.
581 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
582 * configuration data structure)
583 * @retval None
584 */
LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)585 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
586 {
587 /* Set the default configuration */
588 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
589 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
590 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
591 TIM_HallSensorInitStruct->CommutationDelay = 0U;
592 }
593
594 /**
595 * @brief Configure the Hall sensor interface of the timer instance.
596 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
597 * to the TI1 input channel
598 * @note TIMx slave mode controller is configured in reset mode.
599 Selected internal trigger is TI1F_ED.
600 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
601 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
602 * between 2 changes on the inputs. It gives information about motor speed.
603 * @note Channel 2 is configured in output PWM 2 mode.
604 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
605 * @note OC2REF is selected as trigger output on TRGO.
606 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
607 * when TIMx operates in Hall sensor interface mode.
608 * @param TIMx Timer Instance
609 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
610 * interface configuration data structure)
611 * @retval An ErrorStatus enumeration value:
612 * - SUCCESS: TIMx registers are de-initialized
613 * - ERROR: not applicable
614 */
LL_TIM_HALLSENSOR_Init(TIM_TypeDef * TIMx,const LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)615 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
616 {
617 uint32_t tmpcr2;
618 uint32_t tmpccmr1;
619 uint32_t tmpccer;
620 uint32_t tmpsmcr;
621
622 /* Check the parameters */
623 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
624 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
625 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
626 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
627
628 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
629 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
630
631 /* Get the TIMx CR2 register value */
632 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
633
634 /* Get the TIMx CCMR1 register value */
635 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
636
637 /* Get the TIMx CCER register value */
638 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
639
640 /* Get the TIMx SMCR register value */
641 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
642
643 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
644 tmpcr2 |= TIM_CR2_TI1S;
645
646 /* OC2REF signal is used as trigger output (TRGO) */
647 tmpcr2 |= LL_TIM_TRGO_OC2REF;
648
649 /* Configure the slave mode controller */
650 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
651 tmpsmcr |= LL_TIM_TS_TI1F_ED;
652 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
653
654 /* Configure input channel 1 */
655 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
656 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
657 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
658 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
659
660 /* Configure input channel 2 */
661 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
662 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
663
664 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
665 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
666 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
667 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
668
669 /* Write to TIMx CR2 */
670 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
671
672 /* Write to TIMx SMCR */
673 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
674
675 /* Write to TIMx CCMR1 */
676 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
677
678 /* Write to TIMx CCER */
679 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
680
681 /* Write to TIMx CCR2 */
682 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
683
684 return SUCCESS;
685 }
686
687 /**
688 * @brief Set the fields of the Break and Dead Time configuration data structure
689 * to their default values.
690 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
691 * data structure)
692 * @retval None
693 */
LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)694 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
695 {
696 /* Set the default configuration */
697 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
698 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
699 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
700 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
701 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
702 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
703 TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
704 TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT;
705 TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
706 TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
707 TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
708 TIM_BDTRInitStruct->Break2AFMode = LL_TIM_BREAK2_AFMODE_INPUT;
709 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
710 }
711
712 /**
713 * @brief Configure the Break and Dead Time feature of the timer instance.
714 * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
715 * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
716 * can be necessary to configure all of them during the first write access to
717 * the TIMx_BDTR register.
718 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
719 * a timer instance provides a break input.
720 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
721 * a timer instance provides a second break input.
722 * @param TIMx Timer Instance
723 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
724 * data structure)
725 * @retval An ErrorStatus enumeration value:
726 * - SUCCESS: Break and Dead Time is initialized
727 * - ERROR: not applicable
728 */
LL_TIM_BDTR_Init(TIM_TypeDef * TIMx,const LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)729 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
730 {
731 uint32_t tmpbdtr = 0;
732
733 /* Check the parameters */
734 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
735 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
736 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
737 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
738 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
739 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
740 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
741
742 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
743 the OSSI State, the dead time value and the Automatic Output Enable Bit */
744
745 /* Set the BDTR bits */
746 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
747 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
748 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
749 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
750 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
751 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
752 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
753 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
754 if (IS_TIM_ADVANCED_INSTANCE(TIMx))
755 {
756 assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
757 assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
758 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
759 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
760 }
761
762 if (IS_TIM_BKIN2_INSTANCE(TIMx))
763 {
764 assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
765 assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
766 assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
767 assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode));
768
769 /* Set the BREAK2 input related BDTR bit-fields */
770 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
771 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
772 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
773 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode);
774 }
775
776 /* Set TIMx_BDTR */
777 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
778
779 return SUCCESS;
780 }
781 /**
782 * @}
783 */
784
785 /**
786 * @}
787 */
788
789 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
790 * @brief Private functions
791 * @{
792 */
793 /**
794 * @brief Configure the TIMx output channel 1.
795 * @param TIMx Timer Instance
796 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
797 * @retval An ErrorStatus enumeration value:
798 * - SUCCESS: TIMx registers are de-initialized
799 * - ERROR: not applicable
800 */
OC1Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)801 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
802 {
803 uint32_t tmpccmr1;
804 uint32_t tmpccer;
805 uint32_t tmpcr2;
806
807 /* Check the parameters */
808 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
809 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
810 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
811 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
812 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
813 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
814
815 /* Disable the Channel 1: Reset the CC1E Bit */
816 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
817
818 /* Get the TIMx CCER register value */
819 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
820
821 /* Get the TIMx CR2 register value */
822 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
823
824 /* Get the TIMx CCMR1 register value */
825 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
826
827 /* Reset Capture/Compare selection Bits */
828 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
829
830 /* Set the Output Compare Mode */
831 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
832
833 /* Set the Output Compare Polarity */
834 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
835
836 /* Set the Output State */
837 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
838
839 if (IS_TIM_BREAK_INSTANCE(TIMx))
840 {
841 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
842 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
843
844 /* Set the complementary output Polarity */
845 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
846
847 /* Set the complementary output State */
848 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
849
850 /* Set the Output Idle state */
851 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
852
853 /* Set the complementary output Idle state */
854 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
855 }
856
857 /* Write to TIMx CR2 */
858 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
859
860 /* Write to TIMx CCMR1 */
861 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
862
863 /* Set the Capture Compare Register value */
864 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
865
866 /* Write to TIMx CCER */
867 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
868
869 return SUCCESS;
870 }
871
872 /**
873 * @brief Configure the TIMx output channel 2.
874 * @param TIMx Timer Instance
875 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
876 * @retval An ErrorStatus enumeration value:
877 * - SUCCESS: TIMx registers are de-initialized
878 * - ERROR: not applicable
879 */
OC2Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)880 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
881 {
882 uint32_t tmpccmr1;
883 uint32_t tmpccer;
884 uint32_t tmpcr2;
885
886 /* Check the parameters */
887 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
888 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
889 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
890 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
891 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
892 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
893
894 /* Disable the Channel 2: Reset the CC2E Bit */
895 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
896
897 /* Get the TIMx CCER register value */
898 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
899
900 /* Get the TIMx CR2 register value */
901 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
902
903 /* Get the TIMx CCMR1 register value */
904 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
905
906 /* Reset Capture/Compare selection Bits */
907 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
908
909 /* Select the Output Compare Mode */
910 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
911
912 /* Set the Output Compare Polarity */
913 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
914
915 /* Set the Output State */
916 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
917
918 if (IS_TIM_BREAK_INSTANCE(TIMx))
919 {
920 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
921 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
922
923 /* Set the complementary output Polarity */
924 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
925
926 /* Set the complementary output State */
927 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
928
929 /* Set the Output Idle state */
930 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
931
932 /* Set the complementary output Idle state */
933 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
934 }
935
936 /* Write to TIMx CR2 */
937 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
938
939 /* Write to TIMx CCMR1 */
940 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
941
942 /* Set the Capture Compare Register value */
943 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
944
945 /* Write to TIMx CCER */
946 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
947
948 return SUCCESS;
949 }
950
951 /**
952 * @brief Configure the TIMx output channel 3.
953 * @param TIMx Timer Instance
954 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
955 * @retval An ErrorStatus enumeration value:
956 * - SUCCESS: TIMx registers are de-initialized
957 * - ERROR: not applicable
958 */
OC3Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)959 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
960 {
961 uint32_t tmpccmr2;
962 uint32_t tmpccer;
963 uint32_t tmpcr2;
964
965 /* Check the parameters */
966 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
967 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
968 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
969 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
970 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
971 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
972
973 /* Disable the Channel 3: Reset the CC3E Bit */
974 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
975
976 /* Get the TIMx CCER register value */
977 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
978
979 /* Get the TIMx CR2 register value */
980 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
981
982 /* Get the TIMx CCMR2 register value */
983 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
984
985 /* Reset Capture/Compare selection Bits */
986 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
987
988 /* Select the Output Compare Mode */
989 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
990
991 /* Set the Output Compare Polarity */
992 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
993
994 /* Set the Output State */
995 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
996
997 if (IS_TIM_BREAK_INSTANCE(TIMx))
998 {
999 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1000 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1001
1002 /* Set the complementary output Polarity */
1003 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
1004
1005 /* Set the complementary output State */
1006 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
1007
1008 /* Set the Output Idle state */
1009 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
1010
1011 /* Set the complementary output Idle state */
1012 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
1013 }
1014
1015 /* Write to TIMx CR2 */
1016 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1017
1018 /* Write to TIMx CCMR2 */
1019 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1020
1021 /* Set the Capture Compare Register value */
1022 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
1023
1024 /* Write to TIMx CCER */
1025 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1026
1027 return SUCCESS;
1028 }
1029
1030 /**
1031 * @brief Configure the TIMx output channel 4.
1032 * @param TIMx Timer Instance
1033 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
1034 * @retval An ErrorStatus enumeration value:
1035 * - SUCCESS: TIMx registers are de-initialized
1036 * - ERROR: not applicable
1037 */
OC4Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1038 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1039 {
1040 uint32_t tmpccmr2;
1041 uint32_t tmpccer;
1042 uint32_t tmpcr2;
1043
1044 /* Check the parameters */
1045 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1046 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1047 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1048 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1049 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1050 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1051
1052 /* Disable the Channel 4: Reset the CC4E Bit */
1053 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1054
1055 /* Get the TIMx CCER register value */
1056 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1057
1058 /* Get the TIMx CR2 register value */
1059 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1060
1061 /* Get the TIMx CCMR2 register value */
1062 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1063
1064 /* Reset Capture/Compare selection Bits */
1065 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1066
1067 /* Select the Output Compare Mode */
1068 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1069
1070 /* Set the Output Compare Polarity */
1071 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1072
1073 /* Set the Output State */
1074 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1075
1076 if (IS_TIM_BREAK_INSTANCE(TIMx))
1077 {
1078 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1079 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1080
1081 /* Set the Output Idle state */
1082 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1083 }
1084
1085 /* Write to TIMx CR2 */
1086 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1087
1088 /* Write to TIMx CCMR2 */
1089 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1090
1091 /* Set the Capture Compare Register value */
1092 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1093
1094 /* Write to TIMx CCER */
1095 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1096
1097 return SUCCESS;
1098 }
1099
1100 /**
1101 * @brief Configure the TIMx output channel 5.
1102 * @param TIMx Timer Instance
1103 * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
1104 * @retval An ErrorStatus enumeration value:
1105 * - SUCCESS: TIMx registers are de-initialized
1106 * - ERROR: not applicable
1107 */
OC5Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1108 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1109 {
1110 uint32_t tmpccmr3;
1111 uint32_t tmpccer;
1112
1113 /* Check the parameters */
1114 assert_param(IS_TIM_CC5_INSTANCE(TIMx));
1115 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1116 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1117 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1118 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1119 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1120
1121 /* Disable the Channel 5: Reset the CC5E Bit */
1122 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1123
1124 /* Get the TIMx CCER register value */
1125 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1126
1127 /* Get the TIMx CCMR3 register value */
1128 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1129
1130 /* Select the Output Compare Mode */
1131 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1132
1133 /* Set the Output Compare Polarity */
1134 MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1135
1136 /* Set the Output State */
1137 MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1138
1139 if (IS_TIM_BREAK_INSTANCE(TIMx))
1140 {
1141 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1142 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1143
1144 /* Set the Output Idle state */
1145 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1146
1147 }
1148
1149 /* Write to TIMx CCMR3 */
1150 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1151
1152 /* Set the Capture Compare Register value */
1153 LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1154
1155 /* Write to TIMx CCER */
1156 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1157
1158 return SUCCESS;
1159 }
1160
1161 /**
1162 * @brief Configure the TIMx output channel 6.
1163 * @param TIMx Timer Instance
1164 * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1165 * @retval An ErrorStatus enumeration value:
1166 * - SUCCESS: TIMx registers are de-initialized
1167 * - ERROR: not applicable
1168 */
OC6Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1169 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1170 {
1171 uint32_t tmpccmr3;
1172 uint32_t tmpccer;
1173
1174 /* Check the parameters */
1175 assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1176 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1177 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1178 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1179 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1180 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1181
1182 /* Disable the Channel 5: Reset the CC6E Bit */
1183 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1184
1185 /* Get the TIMx CCER register value */
1186 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1187
1188 /* Get the TIMx CCMR3 register value */
1189 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1190
1191 /* Select the Output Compare Mode */
1192 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1193
1194 /* Set the Output Compare Polarity */
1195 MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1196
1197 /* Set the Output State */
1198 MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1199
1200 if (IS_TIM_BREAK_INSTANCE(TIMx))
1201 {
1202 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1203 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1204
1205 /* Set the Output Idle state */
1206 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1207 }
1208
1209 /* Write to TIMx CCMR3 */
1210 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1211
1212 /* Set the Capture Compare Register value */
1213 LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1214
1215 /* Write to TIMx CCER */
1216 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1217
1218 return SUCCESS;
1219 }
1220
1221 /**
1222 * @brief Configure the TIMx input channel 1.
1223 * @param TIMx Timer Instance
1224 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1225 * @retval An ErrorStatus enumeration value:
1226 * - SUCCESS: TIMx registers are de-initialized
1227 * - ERROR: not applicable
1228 */
IC1Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1229 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1230 {
1231 /* Check the parameters */
1232 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1233 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1234 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1235 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1236 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1237
1238 /* Disable the Channel 1: Reset the CC1E Bit */
1239 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1240
1241 /* Select the Input and set the filter and the prescaler value */
1242 MODIFY_REG(TIMx->CCMR1,
1243 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1244 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1245
1246 /* Select the Polarity and set the CC1E Bit */
1247 MODIFY_REG(TIMx->CCER,
1248 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1249 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1250
1251 return SUCCESS;
1252 }
1253
1254 /**
1255 * @brief Configure the TIMx input channel 2.
1256 * @param TIMx Timer Instance
1257 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1258 * @retval An ErrorStatus enumeration value:
1259 * - SUCCESS: TIMx registers are de-initialized
1260 * - ERROR: not applicable
1261 */
IC2Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1262 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1263 {
1264 /* Check the parameters */
1265 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1266 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1267 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1268 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1269 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1270
1271 /* Disable the Channel 2: Reset the CC2E Bit */
1272 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1273
1274 /* Select the Input and set the filter and the prescaler value */
1275 MODIFY_REG(TIMx->CCMR1,
1276 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1277 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1278
1279 /* Select the Polarity and set the CC2E Bit */
1280 MODIFY_REG(TIMx->CCER,
1281 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1282 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1283
1284 return SUCCESS;
1285 }
1286
1287 /**
1288 * @brief Configure the TIMx input channel 3.
1289 * @param TIMx Timer Instance
1290 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1291 * @retval An ErrorStatus enumeration value:
1292 * - SUCCESS: TIMx registers are de-initialized
1293 * - ERROR: not applicable
1294 */
IC3Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1295 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1296 {
1297 /* Check the parameters */
1298 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1299 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1300 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1301 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1302 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1303
1304 /* Disable the Channel 3: Reset the CC3E Bit */
1305 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1306
1307 /* Select the Input and set the filter and the prescaler value */
1308 MODIFY_REG(TIMx->CCMR2,
1309 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1310 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1311
1312 /* Select the Polarity and set the CC3E Bit */
1313 MODIFY_REG(TIMx->CCER,
1314 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1315 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1316
1317 return SUCCESS;
1318 }
1319
1320 /**
1321 * @brief Configure the TIMx input channel 4.
1322 * @param TIMx Timer Instance
1323 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1324 * @retval An ErrorStatus enumeration value:
1325 * - SUCCESS: TIMx registers are de-initialized
1326 * - ERROR: not applicable
1327 */
IC4Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1328 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1329 {
1330 /* Check the parameters */
1331 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1332 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1333 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1334 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1335 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1336
1337 /* Disable the Channel 4: Reset the CC4E Bit */
1338 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1339
1340 /* Select the Input and set the filter and the prescaler value */
1341 MODIFY_REG(TIMx->CCMR2,
1342 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1343 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1344
1345 /* Select the Polarity and set the CC2E Bit */
1346 MODIFY_REG(TIMx->CCER,
1347 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1348 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1349
1350 return SUCCESS;
1351 }
1352
1353
1354 /**
1355 * @}
1356 */
1357
1358 /**
1359 * @}
1360 */
1361
1362 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM14 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */
1363
1364 /**
1365 * @}
1366 */
1367
1368 #endif /* USE_FULL_LL_DRIVER */
1369
1370
