1 /**
2 ******************************************************************************
3 * @file stm32g0xx_ll_spi.c
4 * @author MCD Application Team
5 * @brief SPI LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2018 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32g0xx_ll_spi.h"
22 #include "stm32g0xx_ll_bus.h"
23 #include "stm32g0xx_ll_rcc.h"
24
25 #ifdef USE_FULL_ASSERT
26 #include "stm32_assert.h"
27 #else
28 #define assert_param(expr) ((void)0U)
29 #endif /* USE_FULL_ASSERT */
30
31 /** @addtogroup STM32G0xx_LL_Driver
32 * @{
33 */
34
35 #if defined (SPI1) || defined (SPI2) || defined (SPI3)
36
37 /** @addtogroup SPI_LL
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup SPI_LL_Private_Constants SPI Private Constants
46 * @{
47 */
48 /* SPI registers Masks */
49 #define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
50 SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
51 SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_CRCL | \
52 SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
53 SPI_CR1_BIDIMODE)
54 /**
55 * @}
56 */
57
58 /* Private macros ------------------------------------------------------------*/
59 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
60 * @{
61 */
62 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
63 || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
64 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
65 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
66
67 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
68 || ((__VALUE__) == LL_SPI_MODE_SLAVE))
69
70 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \
71 || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \
72 || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \
73 || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \
74 || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
75 || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \
76 || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
77 || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
78 || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
79 || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
80 || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
81 || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
82 || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
83
84 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
85 || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
86
87 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
88 || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
89
90 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
91 || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
92 || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
93
94 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
95 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
96 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
97 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
98 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
99 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
100 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
101 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
102
103 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
104 || ((__VALUE__) == LL_SPI_MSB_FIRST))
105
106 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
107 || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
108
109 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
110
111 /**
112 * @}
113 */
114
115 /* Private function prototypes -----------------------------------------------*/
116
117 /* Exported functions --------------------------------------------------------*/
118 /** @addtogroup SPI_LL_Exported_Functions
119 * @{
120 */
121
122 /** @addtogroup SPI_LL_EF_Init
123 * @{
124 */
125
126 /**
127 * @brief De-initialize the SPI registers to their default reset values.
128 * @param SPIx SPI Instance
129 * @retval An ErrorStatus enumeration value:
130 * - SUCCESS: SPI registers are de-initialized
131 * - ERROR: SPI registers are not de-initialized
132 */
LL_SPI_DeInit(SPI_TypeDef * SPIx)133 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
134 {
135 ErrorStatus status = ERROR;
136
137 /* Check the parameters */
138 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
139
140 #if defined(SPI1)
141 if (SPIx == SPI1)
142 {
143 /* Force reset of SPI clock */
144 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
145
146 /* Release reset of SPI clock */
147 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
148
149 status = SUCCESS;
150 }
151 #endif /* SPI1 */
152 #if defined(SPI2)
153 if (SPIx == SPI2)
154 {
155 /* Force reset of SPI clock */
156 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
157
158 /* Release reset of SPI clock */
159 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
160
161 status = SUCCESS;
162 }
163 #endif /* SPI2 */
164 #if defined(SPI3)
165 if (SPIx == SPI3)
166 {
167 /* Force reset of SPI clock */
168 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
169
170 /* Release reset of SPI clock */
171 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
172
173 status = SUCCESS;
174 }
175 #endif /* SPI3 */
176
177 return status;
178 }
179
180 /**
181 * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
182 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
183 * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
184 * @param SPIx SPI Instance
185 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
186 * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
187 */
LL_SPI_Init(SPI_TypeDef * SPIx,LL_SPI_InitTypeDef * SPI_InitStruct)188 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
189 {
190 ErrorStatus status = ERROR;
191
192 /* Check the SPI Instance SPIx*/
193 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
194
195 /* Check the SPI parameters from SPI_InitStruct*/
196 assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
197 assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
198 assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
199 assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
200 assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
201 assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
202 assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
203 assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
204 assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
205
206 if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
207 {
208 /*---------------------------- SPIx CR1 Configuration ------------------------
209 * Configure SPIx CR1 with parameters:
210 * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
211 * - Master/Slave Mode: SPI_CR1_MSTR bit
212 * - ClockPolarity: SPI_CR1_CPOL bit
213 * - ClockPhase: SPI_CR1_CPHA bit
214 * - NSS management: SPI_CR1_SSM bit
215 * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
216 * - BitOrder: SPI_CR1_LSBFIRST bit
217 * - CRCCalculation: SPI_CR1_CRCEN bit
218 */
219 MODIFY_REG(SPIx->CR1,
220 SPI_CR1_CLEAR_MASK,
221 SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
222 SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
223 SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
224 SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
225
226 /*---------------------------- SPIx CR2 Configuration ------------------------
227 * Configure SPIx CR2 with parameters:
228 * - DataWidth: DS[3:0] bits
229 * - NSS management: SSOE bit
230 */
231 MODIFY_REG(SPIx->CR2,
232 SPI_CR2_DS | SPI_CR2_SSOE,
233 SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
234
235 /* Set Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode. No DataPacking by default */
236 if (SPI_InitStruct->DataWidth < LL_SPI_DATAWIDTH_9BIT)
237 {
238 LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER);
239 }
240
241 /*---------------------------- SPIx CRCPR Configuration ----------------------
242 * Configure SPIx CRCPR with parameters:
243 * - CRCPoly: CRCPOLY[15:0] bits
244 */
245 if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
246 {
247 assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
248 LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
249 }
250 status = SUCCESS;
251 }
252
253 #if defined (SPI_I2S_SUPPORT)
254 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
255 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
256 #endif /* SPI_I2S_SUPPORT */
257 return status;
258 }
259
260 /**
261 * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
262 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
263 * whose fields will be set to default values.
264 * @retval None
265 */
LL_SPI_StructInit(LL_SPI_InitTypeDef * SPI_InitStruct)266 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
267 {
268 /* Set SPI_InitStruct fields to default values */
269 SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
270 SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
271 SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
272 SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
273 SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
274 SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
275 SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
276 SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
277 SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
278 SPI_InitStruct->CRCPoly = 7U;
279 }
280
281 /**
282 * @}
283 */
284
285 /**
286 * @}
287 */
288
289 /**
290 * @}
291 */
292
293 #if defined(SPI_I2S_SUPPORT)
294 /** @addtogroup I2S_LL
295 * @{
296 */
297
298 /* Private types -------------------------------------------------------------*/
299 /* Private variables ---------------------------------------------------------*/
300 /* Private constants ---------------------------------------------------------*/
301 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
302 * @{
303 */
304 /* I2S registers Masks */
305 #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
306 SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
307 SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
308
309 #define I2S_I2SPR_CLEAR_MASK 0x0002U
310 /**
311 * @}
312 */
313 /* Private macros ------------------------------------------------------------*/
314 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
315 * @{
316 */
317
318 #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
319 || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
320 || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
321 || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
322
323 #define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
324 || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
325
326 #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
327 || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
328 || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
329 || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
330 || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
331
332 #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
333 || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
334 || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
335 || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
336
337 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
338 || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
339
340 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
341 && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
342 || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
343
344 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
345
346 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
347 || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
348 /**
349 * @}
350 */
351
352 /* Private function prototypes -----------------------------------------------*/
353
354 /* Exported functions --------------------------------------------------------*/
355 /** @addtogroup I2S_LL_Exported_Functions
356 * @{
357 */
358
359 /** @addtogroup I2S_LL_EF_Init
360 * @{
361 */
362
363 /**
364 * @brief De-initialize the SPI/I2S registers to their default reset values.
365 * @param SPIx SPI Instance
366 * @retval An ErrorStatus enumeration value:
367 * - SUCCESS: SPI registers are de-initialized
368 * - ERROR: SPI registers are not de-initialized
369 */
LL_I2S_DeInit(SPI_TypeDef * SPIx)370 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
371 {
372 return LL_SPI_DeInit(SPIx);
373 }
374
375 /**
376 * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
377 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
378 * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
379 * @param SPIx SPI Instance
380 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
381 * @retval An ErrorStatus enumeration value:
382 * - SUCCESS: SPI registers are Initialized
383 * - ERROR: SPI registers are not Initialized
384 */
LL_I2S_Init(SPI_TypeDef * SPIx,LL_I2S_InitTypeDef * I2S_InitStruct)385 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
386 {
387 uint32_t i2sdiv = 2U;
388 uint32_t i2sodd = 0U;
389 uint32_t packetlength = 1U;
390 uint32_t tmp;
391 LL_RCC_ClocksTypeDef rcc_clocks;
392 uint32_t sourceclock;
393 ErrorStatus status = ERROR;
394
395 /* Check the I2S parameters */
396 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
397 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
398 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
399 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
400 assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
401 assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
402 assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
403
404 if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
405 {
406 /*---------------------------- SPIx I2SCFGR Configuration --------------------
407 * Configure SPIx I2SCFGR with parameters:
408 * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
409 * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
410 * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
411 * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
412 */
413
414 /* Write to SPIx I2SCFGR */
415 MODIFY_REG(SPIx->I2SCFGR,
416 I2S_I2SCFGR_CLEAR_MASK,
417 I2S_InitStruct->Mode | I2S_InitStruct->Standard |
418 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
419 SPI_I2SCFGR_I2SMOD);
420
421 /*---------------------------- SPIx I2SPR Configuration ----------------------
422 * Configure SPIx I2SPR with parameters:
423 * - MCLKOutput: SPI_I2SPR_MCKOE bit
424 * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
425 */
426
427 /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
428 * else, default values are used: i2sodd = 0U, i2sdiv = 2U.
429 */
430 if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
431 {
432 /* Check the frame length (For the Prescaler computing)
433 * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
434 */
435 if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
436 {
437 /* Packet length is 32 bits */
438 packetlength = 2U;
439 }
440
441 /* I2S Clock source is System clock: Get System Clock frequency */
442 LL_RCC_GetSystemClocksFreq(&rcc_clocks);
443
444 /* Get the source clock value: based on System Clock value */
445 sourceclock = rcc_clocks.SYSCLK_Frequency;
446
447 /* Compute the Real divider depending on the MCLK output state with a floating point */
448 if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
449 {
450 /* MCLK output is enabled */
451 tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
452 }
453 else
454 {
455 /* MCLK output is disabled */
456 tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
457 }
458
459 /* Remove the floating point */
460 tmp = tmp / 10U;
461
462 /* Check the parity of the divider */
463 i2sodd = (tmp & (uint16_t)0x0001U);
464
465 /* Compute the i2sdiv prescaler */
466 i2sdiv = ((tmp - i2sodd) / 2U);
467
468 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
469 i2sodd = (i2sodd << 8U);
470 }
471
472 /* Test if the divider is 1 or 0 or greater than 0xFF */
473 if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
474 {
475 /* Set the default values */
476 i2sdiv = 2U;
477 i2sodd = 0U;
478 }
479
480 /* Write to SPIx I2SPR register the computed value */
481 WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
482
483 status = SUCCESS;
484 }
485 return status;
486 }
487
488 /**
489 * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
490 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
491 * whose fields will be set to default values.
492 * @retval None
493 */
LL_I2S_StructInit(LL_I2S_InitTypeDef * I2S_InitStruct)494 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
495 {
496 /*--------------- Reset I2S init structure parameters values -----------------*/
497 I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
498 I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
499 I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
500 I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
501 I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
502 I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
503 }
504
505 /**
506 * @brief Set linear and parity prescaler.
507 * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
508 * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
509 * @param SPIx SPI Instance
510 * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
511 * @param PrescalerParity This parameter can be one of the following values:
512 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
513 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
514 * @retval None
515 */
LL_I2S_ConfigPrescaler(SPI_TypeDef * SPIx,uint32_t PrescalerLinear,uint32_t PrescalerParity)516 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
517 {
518 /* Check the I2S parameters */
519 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
520 assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
521 assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
522
523 /* Write to SPIx I2SPR */
524 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
525 }
526
527 /**
528 * @}
529 */
530
531 /**
532 * @}
533 */
534
535 /**
536 * @}
537 */
538 #endif /* SPI_I2S_SUPPORT */
539
540 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
541
542 /**
543 * @}
544 */
545
546 #endif /* USE_FULL_LL_DRIVER */
547
548
