1 /**
2 ******************************************************************************
3 * @file stm32g0xx_ll_adc.c
4 * @author MCD Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2018 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32g0xx_ll_adc.h"
22 #include "stm32g0xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32G0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1)
35
36 /** @addtogroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @addtogroup ADC_LL_Private_Constants
44 * @{
45 */
46
47 /* Definitions of ADC hardware constraints delays */
48 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
49 /* not timeout values: */
50 /* Timeout values for ADC operations are dependent to device clock */
51 /* configuration (system clock versus ADC clock), */
52 /* and therefore must be defined in user application. */
53 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
54 /* values definition. */
55 /* Note: ADC timeout values are defined here in CPU cycles to be independent */
56 /* of device clock setting. */
57 /* In user application, ADC timeout values should be defined with */
58 /* temporal values, in function of device clock settings. */
59 /* Highest ratio CPU clock frequency vs ADC clock frequency: */
60 /* - ADC clock from synchronous clock with AHB prescaler 512, */
61 /* APB prescaler 16, ADC prescaler 4. */
62 /* - ADC clock from asynchronous clock (HSI) with prescaler 1, */
63 /* with highest ratio CPU clock frequency vs HSI clock frequency: */
64 /* CPU clock frequency max 56MHz, HSI frequency 16MHz: ratio 4. */
65 /* Unit: CPU cycles. */
66 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
67 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
68 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
69 /* Note: CCRDY handshake requires 1APB + 2 ADC + 3 APB cycles */
70 /* after the channel configuration has been changed. */
71 /* Driver timeout is approximated to 6 CPU cycles. */
72 #define ADC_TIMEOUT_CCRDY_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 6UL)
73
74 /**
75 * @}
76 */
77
78 /* Private macros ------------------------------------------------------------*/
79
80 /** @addtogroup ADC_LL_Private_Macros
81 * @{
82 */
83
84 /* Check of parameters for configuration of ADC hierarchical scope: */
85 /* common to several ADC instances. */
86 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
87 (((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
88 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
89 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
90 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
91 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
92 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
93 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
94 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
95 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
96 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
97 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
98 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
99 )
100
101 #define IS_LL_ADC_CLOCK_FREQ_MODE(__CLOCK_FREQ_MODE__) \
102 (((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_HIGH) \
103 || ((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_LOW) \
104 )
105
106 /* Check of parameters for configuration of ADC hierarchical scope: */
107 /* ADC instance. */
108 #define IS_LL_ADC_CLOCK(__CLOCK__) \
109 (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
110 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
111 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
112 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC) \
113 )
114
115 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
116 (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
117 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
118 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
119 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
120 )
121
122 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
123 (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
124 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
125 )
126
127 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
128 (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
129 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
130 || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF) \
131 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF) \
132 )
133
134 /* Check of parameters for configuration of ADC hierarchical scope: */
135 /* ADC group regular */
136 #if defined(TIM15) && defined(TIM6) && defined(TIM2)
137 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
138 (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
139 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
140 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 ) \
141 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
142 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
143 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
144 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
145 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
146 )
147 #elif defined(TIM15) && defined(TIM6)
148 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
149 (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
150 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
151 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 ) \
152 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
153 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
154 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
155 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
156 )
157 #elif defined(TIM2)
158 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
159 (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
160 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
161 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 ) \
162 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
163 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
164 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
165 )
166 #else
167 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
168 (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
169 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
170 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 ) \
171 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
172 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
173 )
174 #endif /* TIM15 && TIM6 && TIM2 */
175
176 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
177 (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
178 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
179 )
180
181 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
182 (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
183 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
184 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
185 )
186
187 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
188 (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
189 || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
190 )
191
192 #define IS_LL_ADC_REG_SEQ_MODE(__REG_SEQ_MODE__) \
193 (((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_FIXED) \
194 || ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_CONFIGURABLE) \
195 )
196
197 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
198 (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
199 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
200 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
201 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
202 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
203 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
204 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
205 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
206 )
207
208 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
209 (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
210 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
211 )
212
213 /**
214 * @}
215 */
216
217
218 /* Private function prototypes -----------------------------------------------*/
219
220 /* Exported functions --------------------------------------------------------*/
221 /** @addtogroup ADC_LL_Exported_Functions
222 * @{
223 */
224
225 /** @addtogroup ADC_LL_EF_Init
226 * @{
227 */
228
229 /**
230 * @brief De-initialize registers of all ADC instances belonging to
231 * the same ADC common instance to their default reset values.
232 * @note This function is performing a hard reset, using high level
233 * clock source RCC ADC reset.
234 * @param ADCxy_COMMON ADC common instance
235 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
236 * @retval An ErrorStatus enumeration value:
237 * - SUCCESS: ADC common registers are de-initialized
238 * - ERROR: not applicable
239 */
LL_ADC_CommonDeInit(ADC_Common_TypeDef * ADCxy_COMMON)240 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
241 {
242 /* Check the parameters */
243 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
244
245 /* Prevent unused argument(s) compilation warning if no assert_param check */
246 (void)(ADCxy_COMMON);
247
248 /* Force reset of ADC clock (core clock) */
249 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC);
250
251 /* Release reset of ADC clock (core clock) */
252 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC);
253
254 return SUCCESS;
255 }
256
257 /**
258 * @brief Initialize some features of ADC common parameters
259 * (all ADC instances belonging to the same ADC common instance)
260 * and multimode (for devices with several ADC instances available).
261 * @note The setting of ADC common parameters is conditioned to
262 * ADC instances state:
263 * All ADC instances belonging to the same ADC common instance
264 * must be disabled.
265 * @param ADCxy_COMMON ADC common instance
266 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
267 * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
268 * @retval An ErrorStatus enumeration value:
269 * - SUCCESS: ADC common registers are initialized
270 * - ERROR: ADC common registers are not initialized
271 */
LL_ADC_CommonInit(ADC_Common_TypeDef * ADCxy_COMMON,LL_ADC_CommonInitTypeDef * pADC_CommonInitStruct)272 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
273 {
274 ErrorStatus status = SUCCESS;
275
276 /* Check the parameters */
277 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
278 assert_param(IS_LL_ADC_COMMON_CLOCK(pADC_CommonInitStruct->CommonClock));
279
280 /* Note: Hardware constraint (refer to description of functions */
281 /* "LL_ADC_SetCommonXXX()": */
282 /* On this STM32 series, setting of these features is conditioned to */
283 /* ADC state: */
284 /* All ADC instances of the ADC common group must be disabled. */
285 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
286 {
287 /* Configuration of ADC hierarchical scope: */
288 /* - common to several ADC */
289 /* (all ADC instances belonging to the same ADC common instance) */
290 /* - Set ADC clock (conversion clock) */
291 LL_ADC_SetCommonClock(ADCxy_COMMON, pADC_CommonInitStruct->CommonClock);
292 }
293 else
294 {
295 /* Initialization error: One or several ADC instances belonging to */
296 /* the same ADC common instance are not disabled. */
297 status = ERROR;
298 }
299
300 return status;
301 }
302
303 /**
304 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
305 * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
306 * whose fields will be set to default values.
307 * @retval None
308 */
LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef * pADC_CommonInitStruct)309 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
310 {
311 /* Set pADC_CommonInitStruct fields to default values */
312 /* Set fields of ADC common */
313 /* (all ADC instances belonging to the same ADC common instance) */
314 pADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2;
315
316 }
317
318 /**
319 * @brief De-initialize registers of the selected ADC instance
320 * to their default reset values.
321 * @note To reset all ADC instances quickly (perform a hard reset),
322 * use function @ref LL_ADC_CommonDeInit().
323 * @note If this functions returns error status, it means that ADC instance
324 * is in an unknown state.
325 * In this case, perform a hard reset using high level
326 * clock source RCC ADC reset.
327 * Refer to function @ref LL_ADC_CommonDeInit().
328 * @param ADCx ADC instance
329 * @retval An ErrorStatus enumeration value:
330 * - SUCCESS: ADC registers are de-initialized
331 * - ERROR: ADC registers are not de-initialized
332 */
LL_ADC_DeInit(ADC_TypeDef * ADCx)333 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
334 {
335 ErrorStatus status = SUCCESS;
336
337 __IO uint32_t timeout_cpu_cycles = 0UL;
338
339 /* Check the parameters */
340 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
341
342 /* Disable ADC instance if not already disabled. */
343 if (LL_ADC_IsEnabled(ADCx) == 1UL)
344 {
345 /* Set ADC group regular trigger source to SW start to ensure to not */
346 /* have an external trigger event occurring during the conversion stop */
347 /* ADC disable process. */
348 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
349
350 /* Stop potential ADC conversion on going on ADC group regular. */
351 if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
352 {
353 if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL)
354 {
355 LL_ADC_REG_StopConversion(ADCx);
356 }
357 }
358
359 /* Wait for ADC conversions are effectively stopped */
360 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
361 while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1UL)
362 {
363 timeout_cpu_cycles--;
364 if (timeout_cpu_cycles == 0UL)
365 {
366 /* Time-out error */
367 status = ERROR;
368 break;
369 }
370 }
371
372 /* Disable the ADC instance */
373 LL_ADC_Disable(ADCx);
374
375 /* Wait for ADC instance is effectively disabled */
376 timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
377 while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
378 {
379 timeout_cpu_cycles--;
380 if (timeout_cpu_cycles == 0UL)
381 {
382 /* Time-out error */
383 status = ERROR;
384 break;
385 }
386 }
387 }
388
389 /* Check whether ADC state is compliant with expected state */
390 if (READ_BIT(ADCx->CR,
391 (ADC_CR_ADSTP | ADC_CR_ADSTART
392 | ADC_CR_ADDIS | ADC_CR_ADEN)
393 )
394 == 0UL)
395 {
396 /* ========== Reset ADC registers ========== */
397 /* Reset register IER */
398 CLEAR_BIT(ADCx->IER,
399 (LL_ADC_IT_ADRDY
400 | LL_ADC_IT_EOC
401 | LL_ADC_IT_EOS
402 | LL_ADC_IT_OVR
403 | LL_ADC_IT_EOSMP
404 | LL_ADC_IT_AWD1
405 | LL_ADC_IT_AWD2
406 | LL_ADC_IT_AWD3
407 | LL_ADC_IT_EOCAL
408 | LL_ADC_IT_CCRDY
409 )
410 );
411
412 /* Reset register ISR */
413 SET_BIT(ADCx->ISR,
414 (LL_ADC_FLAG_ADRDY
415 | LL_ADC_FLAG_EOC
416 | LL_ADC_FLAG_EOS
417 | LL_ADC_FLAG_OVR
418 | LL_ADC_FLAG_EOSMP
419 | LL_ADC_FLAG_AWD1
420 | LL_ADC_FLAG_AWD2
421 | LL_ADC_FLAG_AWD3
422 | LL_ADC_FLAG_EOCAL
423 | LL_ADC_FLAG_CCRDY
424 )
425 );
426
427 /* Reset register CR */
428 /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
429 /* "read-set": no direct reset applicable. */
430 CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN);
431
432 /* Reset register CFGR1 */
433 CLEAR_BIT(ADCx->CFGR1,
434 (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN
435 | ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD
436 | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES
437 | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN)
438 );
439
440 /* Reset register CFGR2 */
441 /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
442 /* already done above. */
443 CLEAR_BIT(ADCx->CFGR2,
444 (ADC_CFGR2_CKMODE
445 | ADC_CFGR2_TOVS | ADC_CFGR2_OVSS | ADC_CFGR2_OVSR
446 | ADC_CFGR2_OVSE)
447 );
448
449 /* Reset register SMPR */
450 CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP1 | ADC_SMPR_SMP2 | ADC_SMPR_SMPSEL);
451
452 /* Reset register AWD1TR */
453 MODIFY_REG(ADCx->AWD1TR, ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1, ADC_AWD1TR_HT1);
454
455 /* Reset register AWD2TR */
456 MODIFY_REG(ADCx->AWD2TR, ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2, ADC_AWD2TR_HT2);
457
458 /* Reset register AWD3TR */
459 MODIFY_REG(ADCx->AWD3TR, ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3, ADC_AWD3TR_HT3);
460
461 /* Reset register CHSELR */
462 CLEAR_BIT(ADCx->CHSELR,
463 (ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
464 | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
465 | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8
466 | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4
467 | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0)
468 );
469
470 /* Wait for ADC channel configuration ready */
471 timeout_cpu_cycles = ADC_TIMEOUT_CCRDY_CPU_CYCLES;
472 while (LL_ADC_IsActiveFlag_CCRDY(ADCx) == 0UL)
473 {
474 timeout_cpu_cycles--;
475 if (timeout_cpu_cycles == 0UL)
476 {
477 /* Time-out error */
478 status = ERROR;
479 break;
480 }
481 }
482
483 /* Clear flag ADC channel configuration ready */
484 LL_ADC_ClearFlag_CCRDY(ADCx);
485
486 /* Reset register DR */
487 /* bits in access mode read only, no direct reset applicable */
488
489 /* Reset register CALFACT */
490 CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT);
491
492 }
493 else
494 {
495 /* ADC instance is in an unknown state */
496 /* Need to performing a hard reset of ADC instance, using high level */
497 /* clock source RCC ADC reset. */
498 /* Caution: On this STM32 series, if several ADC instances are available */
499 /* on the selected device, RCC ADC reset will reset */
500 /* all ADC instances belonging to the common ADC instance. */
501 status = ERROR;
502 }
503
504 return status;
505 }
506
507 /**
508 * @brief Initialize some features of ADC instance.
509 * @note These parameters have an impact on ADC scope: ADC instance.
510 * Refer to corresponding unitary functions into
511 * @ref ADC_LL_EF_Configuration_ADC_Instance .
512 * @note The setting of these parameters by function @ref LL_ADC_Init()
513 * is conditioned to ADC state:
514 * ADC instance must be disabled.
515 * This condition is applied to all ADC features, for efficiency
516 * and compatibility over all STM32 families. However, the different
517 * features can be set under different ADC state conditions
518 * (setting possible with ADC enabled without conversion on going,
519 * ADC enabled with conversion on going, ...)
520 * Each feature can be updated afterwards with a unitary function
521 * and potentially with ADC in a different state than disabled,
522 * refer to description of each function for setting
523 * conditioned to ADC state.
524 * @note After using this function, some other features must be configured
525 * using LL unitary functions.
526 * The minimum configuration remaining to be done is:
527 * - Set ADC group regular sequencer:
528 * Depending on the sequencer mode (refer to
529 * function @ref LL_ADC_REG_SetSequencerConfigurable() ):
530 * - map channel on the selected sequencer rank.
531 * Refer to function @ref LL_ADC_REG_SetSequencerRanks();
532 * - map channel on rank corresponding to channel number.
533 * Refer to function @ref LL_ADC_REG_SetSequencerChannels();
534 * - Set ADC channel sampling time
535 * Refer to function LL_ADC_SetSamplingTimeCommonChannels();
536 * Refer to function LL_ADC_SetChannelSamplingTime();
537 * @param ADCx ADC instance
538 * @param pADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
539 * @retval An ErrorStatus enumeration value:
540 * - SUCCESS: ADC registers are initialized
541 * - ERROR: ADC registers are not initialized
542 */
LL_ADC_Init(ADC_TypeDef * ADCx,LL_ADC_InitTypeDef * pADC_InitStruct)543 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *pADC_InitStruct)
544 {
545 ErrorStatus status = SUCCESS;
546
547 /* Check the parameters */
548 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
549
550 assert_param(IS_LL_ADC_CLOCK(pADC_InitStruct->Clock));
551 assert_param(IS_LL_ADC_RESOLUTION(pADC_InitStruct->Resolution));
552 assert_param(IS_LL_ADC_DATA_ALIGN(pADC_InitStruct->DataAlignment));
553 assert_param(IS_LL_ADC_LOW_POWER(pADC_InitStruct->LowPowerMode));
554
555 /* Note: Hardware constraint (refer to description of this function): */
556 /* ADC instance must be disabled. */
557 if (LL_ADC_IsEnabled(ADCx) == 0UL)
558 {
559 /* Configuration of ADC hierarchical scope: */
560 /* - ADC instance */
561 /* - Set ADC data resolution */
562 /* - Set ADC conversion data alignment */
563 /* - Set ADC low power mode */
564 MODIFY_REG(ADCx->CFGR1,
565 ADC_CFGR1_RES
566 | ADC_CFGR1_ALIGN
567 | ADC_CFGR1_WAIT
568 | ADC_CFGR1_AUTOFF
569 ,
570 pADC_InitStruct->Resolution
571 | pADC_InitStruct->DataAlignment
572 | pADC_InitStruct->LowPowerMode
573 );
574
575 MODIFY_REG(ADCx->CFGR2,
576 ADC_CFGR2_CKMODE
577 ,
578 pADC_InitStruct->Clock
579 );
580 }
581 else
582 {
583 /* Initialization error: ADC instance is not disabled. */
584 status = ERROR;
585 }
586
587 return status;
588 }
589
590 /**
591 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
592 * @param pADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
593 * whose fields will be set to default values.
594 * @retval None
595 */
LL_ADC_StructInit(LL_ADC_InitTypeDef * pADC_InitStruct)596 void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct)
597 {
598 /* Set pADC_InitStruct fields to default values */
599 /* Set fields of ADC instance */
600 pADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
601 pADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
602 pADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
603 pADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
604
605 }
606
607 /**
608 * @brief Initialize some features of ADC group regular.
609 * @note These parameters have an impact on ADC scope: ADC group regular.
610 * Refer to corresponding unitary functions into
611 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
612 * (functions with prefix "REG").
613 * @note The setting of these parameters by function @ref LL_ADC_Init()
614 * is conditioned to ADC state:
615 * ADC instance must be disabled.
616 * This condition is applied to all ADC features, for efficiency
617 * and compatibility over all STM32 families. However, the different
618 * features can be set under different ADC state conditions
619 * (setting possible with ADC enabled without conversion on going,
620 * ADC enabled with conversion on going, ...)
621 * Each feature can be updated afterwards with a unitary function
622 * and potentially with ADC in a different state than disabled,
623 * refer to description of each function for setting
624 * conditioned to ADC state.
625 * @note Before using this function, ADC group regular sequencer
626 * must be configured: refer to function
627 * @ref LL_ADC_REG_SetSequencerConfigurable().
628 * @note After using this function, other features must be configured
629 * using LL unitary functions.
630 * The minimum configuration remaining to be done is:
631 * - Set ADC group regular sequencer:
632 * Depending on the sequencer mode (refer to
633 * function @ref LL_ADC_REG_SetSequencerConfigurable() ):
634 * - map channel on the selected sequencer rank.
635 * Refer to function @ref LL_ADC_REG_SetSequencerRanks();
636 * - map channel on rank corresponding to channel number.
637 * Refer to function @ref LL_ADC_REG_SetSequencerChannels();
638 * - Set ADC channel sampling time
639 * Refer to function LL_ADC_SetSamplingTimeCommonChannels();
640 * Refer to function LL_ADC_SetChannelSamplingTime();
641 * @param ADCx ADC instance
642 * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
643 * @retval An ErrorStatus enumeration value:
644 * - SUCCESS: ADC registers are initialized
645 * - ERROR: ADC registers are not initialized
646 */
LL_ADC_REG_Init(ADC_TypeDef * ADCx,LL_ADC_REG_InitTypeDef * pADC_RegInitStruct)647 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
648 {
649 ErrorStatus status = SUCCESS;
650
651 /* Check the parameters */
652 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
653 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(pADC_RegInitStruct->TriggerSource));
654 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(pADC_RegInitStruct->ContinuousMode));
655 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(pADC_RegInitStruct->DMATransfer));
656 assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(pADC_RegInitStruct->Overrun));
657
658 if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
659 {
660 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct->SequencerLength));
661 }
662
663 if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
664 || (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
665 )
666 {
667 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(pADC_RegInitStruct->SequencerDiscont));
668
669 /* ADC group regular continuous mode and discontinuous mode */
670 /* can not be enabled simultenaeously */
671 assert_param((pADC_RegInitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
672 || (pADC_RegInitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
673 }
674
675 /* Note: Hardware constraint (refer to description of this function): */
676 /* ADC instance must be disabled. */
677 if (LL_ADC_IsEnabled(ADCx) == 0UL)
678 {
679 /* Configuration of ADC hierarchical scope: */
680 /* - ADC group regular */
681 /* - Set ADC group regular trigger source */
682 /* - Set ADC group regular sequencer length */
683 /* - Set ADC group regular sequencer discontinuous mode */
684 /* - Set ADC group regular continuous mode */
685 /* - Set ADC group regular conversion data transfer: no transfer or */
686 /* transfer by DMA, and DMA requests mode */
687 /* - Set ADC group regular overrun behavior */
688 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
689 /* setting of trigger source to SW start. */
690 if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
691 || (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
692 )
693 {
694 /* Case of sequencer mode fixed
695 or sequencer length >= 2 ranks with sequencer mode fully configurable:
696 discontinuous mode configured */
697 MODIFY_REG(ADCx->CFGR1,
698 ADC_CFGR1_EXTSEL
699 | ADC_CFGR1_EXTEN
700 | ADC_CFGR1_DISCEN
701 | ADC_CFGR1_CONT
702 | ADC_CFGR1_DMAEN
703 | ADC_CFGR1_DMACFG
704 | ADC_CFGR1_OVRMOD
705 ,
706 pADC_RegInitStruct->TriggerSource
707 | pADC_RegInitStruct->SequencerDiscont
708 | pADC_RegInitStruct->ContinuousMode
709 | pADC_RegInitStruct->DMATransfer
710 | pADC_RegInitStruct->Overrun
711 );
712 }
713 else
714 {
715 /* Case of sequencer mode fully configurable
716 and sequencer length 1 rank (sequencer disabled):
717 discontinuous mode discarded (fixed to disable) */
718 MODIFY_REG(ADCx->CFGR1,
719 ADC_CFGR1_EXTSEL
720 | ADC_CFGR1_EXTEN
721 | ADC_CFGR1_DISCEN
722 | ADC_CFGR1_CONT
723 | ADC_CFGR1_DMAEN
724 | ADC_CFGR1_DMACFG
725 | ADC_CFGR1_OVRMOD
726 ,
727 pADC_RegInitStruct->TriggerSource
728 | LL_ADC_REG_SEQ_DISCONT_DISABLE
729 | pADC_RegInitStruct->ContinuousMode
730 | pADC_RegInitStruct->DMATransfer
731 | pADC_RegInitStruct->Overrun
732 );
733 }
734
735 /* Set ADC group regular sequencer length */
736 if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
737 {
738 LL_ADC_REG_SetSequencerLength(ADCx, pADC_RegInitStruct->SequencerLength);
739 }
740 }
741 else
742 {
743 /* Initialization error: ADC instance is not disabled. */
744 status = ERROR;
745 }
746 return status;
747 }
748
749 /**
750 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
751 * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
752 * whose fields will be set to default values.
753 * @retval None
754 */
LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef * pADC_RegInitStruct)755 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
756 {
757 /* Set pADC_RegInitStruct fields to default values */
758 /* Set fields of ADC group regular */
759 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
760 /* setting of trigger source to SW start. */
761 pADC_RegInitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
762 pADC_RegInitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
763 pADC_RegInitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
764 pADC_RegInitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
765 pADC_RegInitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
766 pADC_RegInitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
767 }
768
769 /**
770 * @}
771 */
772
773 /**
774 * @}
775 */
776
777 /**
778 * @}
779 */
780
781 #endif /* ADC1 */
782
783 /**
784 * @}
785 */
786
787 #endif /* USE_FULL_LL_DRIVER */
788
