1 /**
2 ******************************************************************************
3 * @file stm32g0xx_hal_i2c.c
4 * @author MCD Application Team
5 * @brief I2C HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Inter Integrated Circuit (I2C) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral State and Errors functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2018 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 ==============================================================================
25 ##### How to use this driver #####
26 ==============================================================================
27 [..]
28 The I2C HAL driver can be used as follows:
29
30 (#) Declare a I2C_HandleTypeDef handle structure, for example:
31 I2C_HandleTypeDef hi2c;
32
33 (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
34 (##) Enable the I2Cx interface clock
35 (##) I2C pins configuration
36 (+++) Enable the clock for the I2C GPIOs
37 (+++) Configure I2C pins as alternate function open-drain
38 (##) NVIC configuration if you need to use interrupt process
39 (+++) Configure the I2Cx interrupt priority
40 (+++) Enable the NVIC I2C IRQ Channel
41 (##) DMA Configuration if you need to use DMA process
42 (+++) Declare a DMA_HandleTypeDef handle structure for
43 the transmit or receive channel
44 (+++) Enable the DMAx interface clock using
45 (+++) Configure the DMA handle parameters
46 (+++) Configure the DMA Tx or Rx channel
47 (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
48 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
49 the DMA Tx or Rx channel
50
51 (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
52 Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
53
54 (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
55 (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
56
57 (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
58
59 (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
60
61 *** Polling mode IO operation ***
62 =================================
63 [..]
64 (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
65 (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
66 (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
67 (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
68
69 *** Polling mode IO MEM operation ***
70 =====================================
71 [..]
72 (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
73 (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
74
75
76 *** Interrupt mode IO operation ***
77 ===================================
78 [..]
79 (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
80 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
81 add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
82 (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
83 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
84 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
85 (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
86 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
87 add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
88 (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
89 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
90 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
91 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
92 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
93 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
94 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
95 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
96 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
97 This action will inform Master to generate a Stop condition to discard the communication.
98
99
100 *** Interrupt mode or DMA mode IO sequential operation ***
101 ==========================================================
102 [..]
103 (@) These interfaces allow to manage a sequential transfer with a repeated start condition
104 when a direction change during transfer
105 [..]
106 (+) A specific option field manage the different steps of a sequential transfer
107 (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
108 (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in
109 no sequential mode
110 (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
111 and data to transfer without a final stop condition
112 (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with
113 start condition, address and data to transfer without a final stop condition,
114 an then permit a call the same master sequential interface several times
115 (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
116 or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
117 (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
118 and with new data to transfer if the direction change or manage only the new data to
119 transfer
120 if no direction change and without a final stop condition in both cases
121 (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
122 and with new data to transfer if the direction change or manage only the new data to
123 transfer
124 if no direction change and with a final stop condition in both cases
125 (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition
126 after several call of the same master sequential interface several times
127 (link with option I2C_FIRST_AND_NEXT_FRAME).
128 Usage can, transfer several bytes one by one using
129 HAL_I2C_Master_Seq_Transmit_IT
130 or HAL_I2C_Master_Seq_Receive_IT
131 or HAL_I2C_Master_Seq_Transmit_DMA
132 or HAL_I2C_Master_Seq_Receive_DMA
133 with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME.
134 Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or
135 Receive sequence permit to call the opposite interface Receive or Transmit
136 without stopping the communication and so generate a restart condition.
137 (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after
138 each call of the same master sequential
139 interface.
140 Usage can, transfer several bytes one by one with a restart with slave address between
141 each bytes using
142 HAL_I2C_Master_Seq_Transmit_IT
143 or HAL_I2C_Master_Seq_Receive_IT
144 or HAL_I2C_Master_Seq_Transmit_DMA
145 or HAL_I2C_Master_Seq_Receive_DMA
146 with option I2C_FIRST_FRAME then I2C_OTHER_FRAME.
147 Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic
148 generation of STOP condition.
149
150 (+) Different sequential I2C interfaces are listed below:
151 (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
152 HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA()
153 (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and
154 users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
155 (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
156 HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
157 (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
158 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
159 (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
160 (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
161 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
162 (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
163 HAL_I2C_DisableListen_IT()
164 (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can
165 add their own code to check the Address Match Code and the transmission direction request by master
166 (Write/Read).
167 (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can
168 add their own code by customization of function pointer HAL_I2C_ListenCpltCallback()
169 (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
170 HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA()
171 (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and
172 users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
173 (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
174 HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA()
175 (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
176 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
177 (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
178 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
179 (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
180 This action will inform Master to generate a Stop condition to discard the communication.
181
182 *** Interrupt mode IO MEM operation ***
183 =======================================
184 [..]
185 (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
186 HAL_I2C_Mem_Write_IT()
187 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
188 add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
189 (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
190 HAL_I2C_Mem_Read_IT()
191 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
192 add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
193 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
194 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
195
196 *** DMA mode IO operation ***
197 ==============================
198 [..]
199 (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
200 HAL_I2C_Master_Transmit_DMA()
201 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
202 add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
203 (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
204 HAL_I2C_Master_Receive_DMA()
205 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
206 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
207 (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
208 HAL_I2C_Slave_Transmit_DMA()
209 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
210 add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
211 (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
212 HAL_I2C_Slave_Receive_DMA()
213 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
214 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
215 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
216 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
217 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
218 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
219 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
220 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
221 This action will inform Master to generate a Stop condition to discard the communication.
222
223 *** DMA mode IO MEM operation ***
224 =================================
225 [..]
226 (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
227 HAL_I2C_Mem_Write_DMA()
228 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
229 add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
230 (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
231 HAL_I2C_Mem_Read_DMA()
232 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
233 add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
234 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
235 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
236
237
238 *** I2C HAL driver macros list ***
239 ==================================
240 [..]
241 Below the list of most used macros in I2C HAL driver.
242
243 (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
244 (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
245 (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
246 (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
247 (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
248 (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
249 (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
250
251 *** Callback registration ***
252 =============================================
253 [..]
254 The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
255 allows the user to configure dynamically the driver callbacks.
256 Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
257 to register an interrupt callback.
258 [..]
259 Function HAL_I2C_RegisterCallback() allows to register following callbacks:
260 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
261 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
262 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
263 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
264 (+) ListenCpltCallback : callback for end of listen mode.
265 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
266 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
267 (+) ErrorCallback : callback for error detection.
268 (+) AbortCpltCallback : callback for abort completion process.
269 (+) MspInitCallback : callback for Msp Init.
270 (+) MspDeInitCallback : callback for Msp DeInit.
271 This function takes as parameters the HAL peripheral handle, the Callback ID
272 and a pointer to the user callback function.
273 [..]
274 For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
275 [..]
276 Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
277 weak function.
278 HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
279 and the Callback ID.
280 This function allows to reset following callbacks:
281 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
282 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
283 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
284 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
285 (+) ListenCpltCallback : callback for end of listen mode.
286 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
287 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
288 (+) ErrorCallback : callback for error detection.
289 (+) AbortCpltCallback : callback for abort completion process.
290 (+) MspInitCallback : callback for Msp Init.
291 (+) MspDeInitCallback : callback for Msp DeInit.
292 [..]
293 For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
294 [..]
295 By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
296 all callbacks are set to the corresponding weak functions:
297 examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
298 Exception done for MspInit and MspDeInit functions that are
299 reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
300 these callbacks are null (not registered beforehand).
301 If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
302 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
303 [..]
304 Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
305 Exception done MspInit/MspDeInit functions that can be registered/unregistered
306 in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
307 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
308 Then, the user first registers the MspInit/MspDeInit user callbacks
309 using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
310 or HAL_I2C_Init() function.
311 [..]
312 When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
313 not defined, the callback registration feature is not available and all callbacks
314 are set to the corresponding weak functions.
315
316 [..]
317 (@) You can refer to the I2C HAL driver header file for more useful macros
318
319 @endverbatim
320 */
321
322 /* Includes ------------------------------------------------------------------*/
323 #include "stm32g0xx_hal.h"
324
325 /** @addtogroup STM32G0xx_HAL_Driver
326 * @{
327 */
328
329 /** @defgroup I2C I2C
330 * @brief I2C HAL module driver
331 * @{
332 */
333
334 #ifdef HAL_I2C_MODULE_ENABLED
335
336 /* Private typedef -----------------------------------------------------------*/
337 /* Private define ------------------------------------------------------------*/
338
339 /** @defgroup I2C_Private_Define I2C Private Define
340 * @{
341 */
342 #define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */
343 #define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */
344 #define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */
345 #define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */
346 #define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */
347 #define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */
348 #define I2C_TIMEOUT_TC (25U) /*!< 25 ms */
349 #define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */
350 #define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */
351 #define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */
352
353 #define MAX_NBYTE_SIZE 255U
354 #define SLAVE_ADDR_SHIFT 7U
355 #define SLAVE_ADDR_MSK 0x06U
356
357 /* Private define for @ref PreviousState usage */
358 #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
359 (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
360 (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
361 /*!< Mask State define, keep only RX and TX bits */
362 #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
363 /*!< Default Value */
364 #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
365 (uint32_t)HAL_I2C_MODE_MASTER))
366 /*!< Master Busy TX, combinaison of State LSB and Mode enum */
367 #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
368 (uint32_t)HAL_I2C_MODE_MASTER))
369 /*!< Master Busy RX, combinaison of State LSB and Mode enum */
370 #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
371 (uint32_t)HAL_I2C_MODE_SLAVE))
372 /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
373 #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
374 (uint32_t)HAL_I2C_MODE_SLAVE))
375 /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
376 #define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
377 (uint32_t)HAL_I2C_MODE_MEM))
378 /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
379 #define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
380 (uint32_t)HAL_I2C_MODE_MEM))
381 /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
382
383
384 /* Private define to centralize the enable/disable of Interrupts */
385 #define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with
386 @ref I2C_XFER_LISTEN_IT */
387 #define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with
388 @ref I2C_XFER_LISTEN_IT */
389 #define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT
390 and @ref I2C_XFER_RX_IT */
391
392 #define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error
393 and NACK treatment */
394 #define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */
395 #define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */
396
397 /* Private define Sequential Transfer Options default/reset value */
398 #define I2C_NO_OPTION_FRAME (0xFFFF0000U)
399 /**
400 * @}
401 */
402
403 /* Private macros ------------------------------------------------------------*/
404 /** @addtogroup I2C_Private_Macro
405 * @{
406 */
407 /* Macro to get remaining data to transfer on DMA side */
408 #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__)
409 /**
410 * @}
411 */
412
413 /* Private variables ---------------------------------------------------------*/
414 /* Private function prototypes -----------------------------------------------*/
415
416 /** @defgroup I2C_Private_Functions I2C Private Functions
417 * @{
418 */
419 /* Private functions to handle DMA transfer */
420 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
421 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
422 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
423 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
424 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
425 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
426
427
428 /* Private functions to handle IT transfer */
429 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
430 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
431 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
432 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
433 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
434 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
435 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
436
437 /* Private functions to handle IT transfer */
438 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
439 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
440 uint32_t Tickstart);
441 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
442 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
443 uint32_t Tickstart);
444
445 /* Private functions for I2C transfer IRQ handler */
446 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
447 uint32_t ITSources);
448 static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
449 uint32_t ITSources);
450 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
451 uint32_t ITSources);
452 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
453 uint32_t ITSources);
454 static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
455 uint32_t ITSources);
456 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
457 uint32_t ITSources);
458
459 /* Private functions to handle flags during polling transfer */
460 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
461 uint32_t Timeout, uint32_t Tickstart);
462 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
463 uint32_t Tickstart);
464 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
465 uint32_t Tickstart);
466 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
467 uint32_t Tickstart);
468 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
469 uint32_t Tickstart);
470
471 /* Private functions to centralize the enable/disable of Interrupts */
472 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
473 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
474
475 /* Private function to treat different error callback */
476 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
477
478 /* Private function to flush TXDR register */
479 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
480
481 /* Private function to handle start, restart or stop a transfer */
482 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
483 uint32_t Request);
484
485 /* Private function to Convert Specific options */
486 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
487 /**
488 * @}
489 */
490
491 /* Exported functions --------------------------------------------------------*/
492
493 /** @defgroup I2C_Exported_Functions I2C Exported Functions
494 * @{
495 */
496
497 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
498 * @brief Initialization and Configuration functions
499 *
500 @verbatim
501 ===============================================================================
502 ##### Initialization and de-initialization functions #####
503 ===============================================================================
504 [..] This subsection provides a set of functions allowing to initialize and
505 deinitialize the I2Cx peripheral:
506
507 (+) User must Implement HAL_I2C_MspInit() function in which he configures
508 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
509
510 (+) Call the function HAL_I2C_Init() to configure the selected device with
511 the selected configuration:
512 (++) Clock Timing
513 (++) Own Address 1
514 (++) Addressing mode (Master, Slave)
515 (++) Dual Addressing mode
516 (++) Own Address 2
517 (++) Own Address 2 Mask
518 (++) General call mode
519 (++) Nostretch mode
520
521 (+) Call the function HAL_I2C_DeInit() to restore the default configuration
522 of the selected I2Cx peripheral.
523
524 @endverbatim
525 * @{
526 */
527
528 /**
529 * @brief Initializes the I2C according to the specified parameters
530 * in the I2C_InitTypeDef and initialize the associated handle.
531 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
532 * the configuration information for the specified I2C.
533 * @retval HAL status
534 */
HAL_I2C_Init(I2C_HandleTypeDef * hi2c)535 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
536 {
537 /* Check the I2C handle allocation */
538 if (hi2c == NULL)
539 {
540 return HAL_ERROR;
541 }
542
543 /* Check the parameters */
544 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
545 assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
546 assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
547 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
548 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
549 assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
550 assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
551 assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
552
553 if (hi2c->State == HAL_I2C_STATE_RESET)
554 {
555 /* Allocate lock resource and initialize it */
556 hi2c->Lock = HAL_UNLOCKED;
557
558 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
559 /* Init the I2C Callback settings */
560 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
561 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
562 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
563 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
564 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
565 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
566 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
567 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
568 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
569 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
570
571 if (hi2c->MspInitCallback == NULL)
572 {
573 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
574 }
575
576 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
577 hi2c->MspInitCallback(hi2c);
578 #else
579 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
580 HAL_I2C_MspInit(hi2c);
581 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
582 }
583
584 hi2c->State = HAL_I2C_STATE_BUSY;
585
586 /* Disable the selected I2C peripheral */
587 __HAL_I2C_DISABLE(hi2c);
588
589 /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
590 /* Configure I2Cx: Frequency range */
591 hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
592
593 /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
594 /* Disable Own Address1 before set the Own Address1 configuration */
595 hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
596
597 /* Configure I2Cx: Own Address1 and ack own address1 mode */
598 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
599 {
600 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
601 }
602 else /* I2C_ADDRESSINGMODE_10BIT */
603 {
604 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
605 }
606
607 /*---------------------------- I2Cx CR2 Configuration ----------------------*/
608 /* Configure I2Cx: Addressing Master mode */
609 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
610 {
611 SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
612 }
613 else
614 {
615 /* Clear the I2C ADD10 bit */
616 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
617 }
618 /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
619 hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
620
621 /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
622 /* Disable Own Address2 before set the Own Address2 configuration */
623 hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
624
625 /* Configure I2Cx: Dual mode and Own Address2 */
626 hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
627 (hi2c->Init.OwnAddress2Masks << 8));
628
629 /*---------------------------- I2Cx CR1 Configuration ----------------------*/
630 /* Configure I2Cx: Generalcall and NoStretch mode */
631 hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
632
633 /* Enable the selected I2C peripheral */
634 __HAL_I2C_ENABLE(hi2c);
635
636 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
637 hi2c->State = HAL_I2C_STATE_READY;
638 hi2c->PreviousState = I2C_STATE_NONE;
639 hi2c->Mode = HAL_I2C_MODE_NONE;
640
641 return HAL_OK;
642 }
643
644 /**
645 * @brief DeInitialize the I2C peripheral.
646 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
647 * the configuration information for the specified I2C.
648 * @retval HAL status
649 */
HAL_I2C_DeInit(I2C_HandleTypeDef * hi2c)650 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
651 {
652 /* Check the I2C handle allocation */
653 if (hi2c == NULL)
654 {
655 return HAL_ERROR;
656 }
657
658 /* Check the parameters */
659 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
660
661 hi2c->State = HAL_I2C_STATE_BUSY;
662
663 /* Disable the I2C Peripheral Clock */
664 __HAL_I2C_DISABLE(hi2c);
665
666 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
667 if (hi2c->MspDeInitCallback == NULL)
668 {
669 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
670 }
671
672 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
673 hi2c->MspDeInitCallback(hi2c);
674 #else
675 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
676 HAL_I2C_MspDeInit(hi2c);
677 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
678
679 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
680 hi2c->State = HAL_I2C_STATE_RESET;
681 hi2c->PreviousState = I2C_STATE_NONE;
682 hi2c->Mode = HAL_I2C_MODE_NONE;
683
684 /* Release Lock */
685 __HAL_UNLOCK(hi2c);
686
687 return HAL_OK;
688 }
689
690 /**
691 * @brief Initialize the I2C MSP.
692 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
693 * the configuration information for the specified I2C.
694 * @retval None
695 */
HAL_I2C_MspInit(I2C_HandleTypeDef * hi2c)696 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
697 {
698 /* Prevent unused argument(s) compilation warning */
699 UNUSED(hi2c);
700
701 /* NOTE : This function should not be modified, when the callback is needed,
702 the HAL_I2C_MspInit could be implemented in the user file
703 */
704 }
705
706 /**
707 * @brief DeInitialize the I2C MSP.
708 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
709 * the configuration information for the specified I2C.
710 * @retval None
711 */
HAL_I2C_MspDeInit(I2C_HandleTypeDef * hi2c)712 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
713 {
714 /* Prevent unused argument(s) compilation warning */
715 UNUSED(hi2c);
716
717 /* NOTE : This function should not be modified, when the callback is needed,
718 the HAL_I2C_MspDeInit could be implemented in the user file
719 */
720 }
721
722 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
723 /**
724 * @brief Register a User I2C Callback
725 * To be used instead of the weak predefined callback
726 * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
727 * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
728 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
729 * the configuration information for the specified I2C.
730 * @param CallbackID ID of the callback to be registered
731 * This parameter can be one of the following values:
732 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
733 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
734 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
735 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
736 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
737 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
738 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
739 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
740 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
741 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
742 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
743 * @param pCallback pointer to the Callback function
744 * @retval HAL status
745 */
HAL_I2C_RegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID,pI2C_CallbackTypeDef pCallback)746 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
747 pI2C_CallbackTypeDef pCallback)
748 {
749 HAL_StatusTypeDef status = HAL_OK;
750
751 if (pCallback == NULL)
752 {
753 /* Update the error code */
754 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
755
756 return HAL_ERROR;
757 }
758
759 if (HAL_I2C_STATE_READY == hi2c->State)
760 {
761 switch (CallbackID)
762 {
763 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
764 hi2c->MasterTxCpltCallback = pCallback;
765 break;
766
767 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
768 hi2c->MasterRxCpltCallback = pCallback;
769 break;
770
771 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
772 hi2c->SlaveTxCpltCallback = pCallback;
773 break;
774
775 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
776 hi2c->SlaveRxCpltCallback = pCallback;
777 break;
778
779 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
780 hi2c->ListenCpltCallback = pCallback;
781 break;
782
783 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
784 hi2c->MemTxCpltCallback = pCallback;
785 break;
786
787 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
788 hi2c->MemRxCpltCallback = pCallback;
789 break;
790
791 case HAL_I2C_ERROR_CB_ID :
792 hi2c->ErrorCallback = pCallback;
793 break;
794
795 case HAL_I2C_ABORT_CB_ID :
796 hi2c->AbortCpltCallback = pCallback;
797 break;
798
799 case HAL_I2C_MSPINIT_CB_ID :
800 hi2c->MspInitCallback = pCallback;
801 break;
802
803 case HAL_I2C_MSPDEINIT_CB_ID :
804 hi2c->MspDeInitCallback = pCallback;
805 break;
806
807 default :
808 /* Update the error code */
809 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
810
811 /* Return error status */
812 status = HAL_ERROR;
813 break;
814 }
815 }
816 else if (HAL_I2C_STATE_RESET == hi2c->State)
817 {
818 switch (CallbackID)
819 {
820 case HAL_I2C_MSPINIT_CB_ID :
821 hi2c->MspInitCallback = pCallback;
822 break;
823
824 case HAL_I2C_MSPDEINIT_CB_ID :
825 hi2c->MspDeInitCallback = pCallback;
826 break;
827
828 default :
829 /* Update the error code */
830 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
831
832 /* Return error status */
833 status = HAL_ERROR;
834 break;
835 }
836 }
837 else
838 {
839 /* Update the error code */
840 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
841
842 /* Return error status */
843 status = HAL_ERROR;
844 }
845
846 return status;
847 }
848
849 /**
850 * @brief Unregister an I2C Callback
851 * I2C callback is redirected to the weak predefined callback
852 * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
853 * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
854 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
855 * the configuration information for the specified I2C.
856 * @param CallbackID ID of the callback to be unregistered
857 * This parameter can be one of the following values:
858 * This parameter can be one of the following values:
859 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
860 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
861 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
862 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
863 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
864 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
865 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
866 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
867 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
868 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
869 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
870 * @retval HAL status
871 */
HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID)872 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
873 {
874 HAL_StatusTypeDef status = HAL_OK;
875
876 if (HAL_I2C_STATE_READY == hi2c->State)
877 {
878 switch (CallbackID)
879 {
880 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
881 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
882 break;
883
884 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
885 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
886 break;
887
888 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
889 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
890 break;
891
892 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
893 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
894 break;
895
896 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
897 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
898 break;
899
900 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
901 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
902 break;
903
904 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
905 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
906 break;
907
908 case HAL_I2C_ERROR_CB_ID :
909 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
910 break;
911
912 case HAL_I2C_ABORT_CB_ID :
913 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
914 break;
915
916 case HAL_I2C_MSPINIT_CB_ID :
917 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
918 break;
919
920 case HAL_I2C_MSPDEINIT_CB_ID :
921 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
922 break;
923
924 default :
925 /* Update the error code */
926 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
927
928 /* Return error status */
929 status = HAL_ERROR;
930 break;
931 }
932 }
933 else if (HAL_I2C_STATE_RESET == hi2c->State)
934 {
935 switch (CallbackID)
936 {
937 case HAL_I2C_MSPINIT_CB_ID :
938 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
939 break;
940
941 case HAL_I2C_MSPDEINIT_CB_ID :
942 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
943 break;
944
945 default :
946 /* Update the error code */
947 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
948
949 /* Return error status */
950 status = HAL_ERROR;
951 break;
952 }
953 }
954 else
955 {
956 /* Update the error code */
957 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
958
959 /* Return error status */
960 status = HAL_ERROR;
961 }
962
963 return status;
964 }
965
966 /**
967 * @brief Register the Slave Address Match I2C Callback
968 * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
969 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
970 * the configuration information for the specified I2C.
971 * @param pCallback pointer to the Address Match Callback function
972 * @retval HAL status
973 */
HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef * hi2c,pI2C_AddrCallbackTypeDef pCallback)974 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
975 {
976 HAL_StatusTypeDef status = HAL_OK;
977
978 if (pCallback == NULL)
979 {
980 /* Update the error code */
981 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
982
983 return HAL_ERROR;
984 }
985
986 if (HAL_I2C_STATE_READY == hi2c->State)
987 {
988 hi2c->AddrCallback = pCallback;
989 }
990 else
991 {
992 /* Update the error code */
993 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
994
995 /* Return error status */
996 status = HAL_ERROR;
997 }
998
999 return status;
1000 }
1001
1002 /**
1003 * @brief UnRegister the Slave Address Match I2C Callback
1004 * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
1005 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1006 * the configuration information for the specified I2C.
1007 * @retval HAL status
1008 */
HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef * hi2c)1009 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
1010 {
1011 HAL_StatusTypeDef status = HAL_OK;
1012
1013 if (HAL_I2C_STATE_READY == hi2c->State)
1014 {
1015 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
1016 }
1017 else
1018 {
1019 /* Update the error code */
1020 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
1021
1022 /* Return error status */
1023 status = HAL_ERROR;
1024 }
1025
1026 return status;
1027 }
1028
1029 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
1030
1031 /**
1032 * @}
1033 */
1034
1035 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
1036 * @brief Data transfers functions
1037 *
1038 @verbatim
1039 ===============================================================================
1040 ##### IO operation functions #####
1041 ===============================================================================
1042 [..]
1043 This subsection provides a set of functions allowing to manage the I2C data
1044 transfers.
1045
1046 (#) There are two modes of transfer:
1047 (++) Blocking mode : The communication is performed in the polling mode.
1048 The status of all data processing is returned by the same function
1049 after finishing transfer.
1050 (++) No-Blocking mode : The communication is performed using Interrupts
1051 or DMA. These functions return the status of the transfer startup.
1052 The end of the data processing will be indicated through the
1053 dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
1054 using DMA mode.
1055
1056 (#) Blocking mode functions are :
1057 (++) HAL_I2C_Master_Transmit()
1058 (++) HAL_I2C_Master_Receive()
1059 (++) HAL_I2C_Slave_Transmit()
1060 (++) HAL_I2C_Slave_Receive()
1061 (++) HAL_I2C_Mem_Write()
1062 (++) HAL_I2C_Mem_Read()
1063 (++) HAL_I2C_IsDeviceReady()
1064
1065 (#) No-Blocking mode functions with Interrupt are :
1066 (++) HAL_I2C_Master_Transmit_IT()
1067 (++) HAL_I2C_Master_Receive_IT()
1068 (++) HAL_I2C_Slave_Transmit_IT()
1069 (++) HAL_I2C_Slave_Receive_IT()
1070 (++) HAL_I2C_Mem_Write_IT()
1071 (++) HAL_I2C_Mem_Read_IT()
1072 (++) HAL_I2C_Master_Seq_Transmit_IT()
1073 (++) HAL_I2C_Master_Seq_Receive_IT()
1074 (++) HAL_I2C_Slave_Seq_Transmit_IT()
1075 (++) HAL_I2C_Slave_Seq_Receive_IT()
1076 (++) HAL_I2C_EnableListen_IT()
1077 (++) HAL_I2C_DisableListen_IT()
1078 (++) HAL_I2C_Master_Abort_IT()
1079
1080 (#) No-Blocking mode functions with DMA are :
1081 (++) HAL_I2C_Master_Transmit_DMA()
1082 (++) HAL_I2C_Master_Receive_DMA()
1083 (++) HAL_I2C_Slave_Transmit_DMA()
1084 (++) HAL_I2C_Slave_Receive_DMA()
1085 (++) HAL_I2C_Mem_Write_DMA()
1086 (++) HAL_I2C_Mem_Read_DMA()
1087 (++) HAL_I2C_Master_Seq_Transmit_DMA()
1088 (++) HAL_I2C_Master_Seq_Receive_DMA()
1089 (++) HAL_I2C_Slave_Seq_Transmit_DMA()
1090 (++) HAL_I2C_Slave_Seq_Receive_DMA()
1091
1092 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
1093 (++) HAL_I2C_MasterTxCpltCallback()
1094 (++) HAL_I2C_MasterRxCpltCallback()
1095 (++) HAL_I2C_SlaveTxCpltCallback()
1096 (++) HAL_I2C_SlaveRxCpltCallback()
1097 (++) HAL_I2C_MemTxCpltCallback()
1098 (++) HAL_I2C_MemRxCpltCallback()
1099 (++) HAL_I2C_AddrCallback()
1100 (++) HAL_I2C_ListenCpltCallback()
1101 (++) HAL_I2C_ErrorCallback()
1102 (++) HAL_I2C_AbortCpltCallback()
1103
1104 @endverbatim
1105 * @{
1106 */
1107
1108 /**
1109 * @brief Transmits in master mode an amount of data in blocking mode.
1110 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1111 * the configuration information for the specified I2C.
1112 * @param DevAddress Target device address: The device 7 bits address value
1113 * in datasheet must be shifted to the left before calling the interface
1114 * @param pData Pointer to data buffer
1115 * @param Size Amount of data to be sent
1116 * @param Timeout Timeout duration
1117 * @retval HAL status
1118 */
HAL_I2C_Master_Transmit(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1119 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1120 uint16_t Size, uint32_t Timeout)
1121 {
1122 uint32_t tickstart;
1123 uint32_t xfermode;
1124
1125 if (hi2c->State == HAL_I2C_STATE_READY)
1126 {
1127 /* Process Locked */
1128 __HAL_LOCK(hi2c);
1129
1130 /* Init tickstart for timeout management*/
1131 tickstart = HAL_GetTick();
1132
1133 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1134 {
1135 return HAL_ERROR;
1136 }
1137
1138 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1139 hi2c->Mode = HAL_I2C_MODE_MASTER;
1140 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1141
1142 /* Prepare transfer parameters */
1143 hi2c->pBuffPtr = pData;
1144 hi2c->XferCount = Size;
1145 hi2c->XferISR = NULL;
1146
1147 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1148 {
1149 hi2c->XferSize = MAX_NBYTE_SIZE;
1150 xfermode = I2C_RELOAD_MODE;
1151 }
1152 else
1153 {
1154 hi2c->XferSize = hi2c->XferCount;
1155 xfermode = I2C_AUTOEND_MODE;
1156 }
1157
1158 if (hi2c->XferSize > 0U)
1159 {
1160 /* Preload TX register */
1161 /* Write data to TXDR */
1162 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1163
1164 /* Increment Buffer pointer */
1165 hi2c->pBuffPtr++;
1166
1167 hi2c->XferCount--;
1168 hi2c->XferSize--;
1169
1170 /* Send Slave Address */
1171 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1172 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode,
1173 I2C_GENERATE_START_WRITE);
1174 }
1175 else
1176 {
1177 /* Send Slave Address */
1178 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1179 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
1180 I2C_GENERATE_START_WRITE);
1181 }
1182
1183 while (hi2c->XferCount > 0U)
1184 {
1185 /* Wait until TXIS flag is set */
1186 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1187 {
1188 return HAL_ERROR;
1189 }
1190 /* Write data to TXDR */
1191 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1192
1193 /* Increment Buffer pointer */
1194 hi2c->pBuffPtr++;
1195
1196 hi2c->XferCount--;
1197 hi2c->XferSize--;
1198
1199 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
1200 {
1201 /* Wait until TCR flag is set */
1202 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1203 {
1204 return HAL_ERROR;
1205 }
1206
1207 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1208 {
1209 hi2c->XferSize = MAX_NBYTE_SIZE;
1210 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1211 I2C_NO_STARTSTOP);
1212 }
1213 else
1214 {
1215 hi2c->XferSize = hi2c->XferCount;
1216 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1217 I2C_NO_STARTSTOP);
1218 }
1219 }
1220 }
1221
1222 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1223 /* Wait until STOPF flag is set */
1224 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1225 {
1226 return HAL_ERROR;
1227 }
1228
1229 /* Clear STOP Flag */
1230 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1231
1232 /* Clear Configuration Register 2 */
1233 I2C_RESET_CR2(hi2c);
1234
1235 hi2c->State = HAL_I2C_STATE_READY;
1236 hi2c->Mode = HAL_I2C_MODE_NONE;
1237
1238 /* Process Unlocked */
1239 __HAL_UNLOCK(hi2c);
1240
1241 return HAL_OK;
1242 }
1243 else
1244 {
1245 return HAL_BUSY;
1246 }
1247 }
1248
1249 /**
1250 * @brief Receives in master mode an amount of data in blocking mode.
1251 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1252 * the configuration information for the specified I2C.
1253 * @param DevAddress Target device address: The device 7 bits address value
1254 * in datasheet must be shifted to the left before calling the interface
1255 * @param pData Pointer to data buffer
1256 * @param Size Amount of data to be sent
1257 * @param Timeout Timeout duration
1258 * @retval HAL status
1259 */
HAL_I2C_Master_Receive(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1260 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1261 uint16_t Size, uint32_t Timeout)
1262 {
1263 uint32_t tickstart;
1264
1265 if (hi2c->State == HAL_I2C_STATE_READY)
1266 {
1267 /* Process Locked */
1268 __HAL_LOCK(hi2c);
1269
1270 /* Init tickstart for timeout management*/
1271 tickstart = HAL_GetTick();
1272
1273 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1274 {
1275 return HAL_ERROR;
1276 }
1277
1278 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1279 hi2c->Mode = HAL_I2C_MODE_MASTER;
1280 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1281
1282 /* Prepare transfer parameters */
1283 hi2c->pBuffPtr = pData;
1284 hi2c->XferCount = Size;
1285 hi2c->XferISR = NULL;
1286
1287 /* Send Slave Address */
1288 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1289 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1290 {
1291 hi2c->XferSize = MAX_NBYTE_SIZE;
1292 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1293 I2C_GENERATE_START_READ);
1294 }
1295 else
1296 {
1297 hi2c->XferSize = hi2c->XferCount;
1298 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1299 I2C_GENERATE_START_READ);
1300 }
1301
1302 while (hi2c->XferCount > 0U)
1303 {
1304 /* Wait until RXNE flag is set */
1305 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1306 {
1307 return HAL_ERROR;
1308 }
1309
1310 /* Read data from RXDR */
1311 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1312
1313 /* Increment Buffer pointer */
1314 hi2c->pBuffPtr++;
1315
1316 hi2c->XferSize--;
1317 hi2c->XferCount--;
1318
1319 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
1320 {
1321 /* Wait until TCR flag is set */
1322 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1323 {
1324 return HAL_ERROR;
1325 }
1326
1327 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1328 {
1329 hi2c->XferSize = MAX_NBYTE_SIZE;
1330 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1331 I2C_NO_STARTSTOP);
1332 }
1333 else
1334 {
1335 hi2c->XferSize = hi2c->XferCount;
1336 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1337 I2C_NO_STARTSTOP);
1338 }
1339 }
1340 }
1341
1342 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1343 /* Wait until STOPF flag is set */
1344 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1345 {
1346 return HAL_ERROR;
1347 }
1348
1349 /* Clear STOP Flag */
1350 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1351
1352 /* Clear Configuration Register 2 */
1353 I2C_RESET_CR2(hi2c);
1354
1355 hi2c->State = HAL_I2C_STATE_READY;
1356 hi2c->Mode = HAL_I2C_MODE_NONE;
1357
1358 /* Process Unlocked */
1359 __HAL_UNLOCK(hi2c);
1360
1361 return HAL_OK;
1362 }
1363 else
1364 {
1365 return HAL_BUSY;
1366 }
1367 }
1368
1369 /**
1370 * @brief Transmits in slave mode an amount of data in blocking mode.
1371 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1372 * the configuration information for the specified I2C.
1373 * @param pData Pointer to data buffer
1374 * @param Size Amount of data to be sent
1375 * @param Timeout Timeout duration
1376 * @retval HAL status
1377 */
HAL_I2C_Slave_Transmit(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1378 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
1379 uint32_t Timeout)
1380 {
1381 uint32_t tickstart;
1382 uint16_t tmpXferCount;
1383 HAL_StatusTypeDef error;
1384
1385 if (hi2c->State == HAL_I2C_STATE_READY)
1386 {
1387 if ((pData == NULL) || (Size == 0U))
1388 {
1389 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
1390 return HAL_ERROR;
1391 }
1392 /* Process Locked */
1393 __HAL_LOCK(hi2c);
1394
1395 /* Init tickstart for timeout management*/
1396 tickstart = HAL_GetTick();
1397
1398 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1399 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1400 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1401
1402 /* Prepare transfer parameters */
1403 hi2c->pBuffPtr = pData;
1404 hi2c->XferCount = Size;
1405 hi2c->XferISR = NULL;
1406
1407 /* Enable Address Acknowledge */
1408 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1409
1410 /* Wait until ADDR flag is set */
1411 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1412 {
1413 /* Disable Address Acknowledge */
1414 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1415 return HAL_ERROR;
1416 }
1417
1418 /* Preload TX data if no stretch enable */
1419 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
1420 {
1421 /* Preload TX register */
1422 /* Write data to TXDR */
1423 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1424
1425 /* Increment Buffer pointer */
1426 hi2c->pBuffPtr++;
1427
1428 hi2c->XferCount--;
1429 }
1430
1431 /* Clear ADDR flag */
1432 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1433
1434 /* If 10bit addressing mode is selected */
1435 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
1436 {
1437 /* Wait until ADDR flag is set */
1438 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1439 {
1440 /* Disable Address Acknowledge */
1441 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1442 return HAL_ERROR;
1443 }
1444
1445 /* Clear ADDR flag */
1446 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1447 }
1448
1449 /* Wait until DIR flag is set Transmitter mode */
1450 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
1451 {
1452 /* Disable Address Acknowledge */
1453 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1454 return HAL_ERROR;
1455 }
1456
1457 while (hi2c->XferCount > 0U)
1458 {
1459 /* Wait until TXIS flag is set */
1460 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1461 {
1462 /* Disable Address Acknowledge */
1463 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1464 return HAL_ERROR;
1465 }
1466
1467 /* Write data to TXDR */
1468 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1469
1470 /* Increment Buffer pointer */
1471 hi2c->pBuffPtr++;
1472
1473 hi2c->XferCount--;
1474 }
1475
1476 /* Wait until AF flag is set */
1477 error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart);
1478
1479 if (error != HAL_OK)
1480 {
1481 /* Check that I2C transfer finished */
1482 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
1483 /* Mean XferCount == 0 */
1484
1485 tmpXferCount = hi2c->XferCount;
1486 if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U))
1487 {
1488 /* Reset ErrorCode to NONE */
1489 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1490 }
1491 else
1492 {
1493 /* Disable Address Acknowledge */
1494 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1495 return HAL_ERROR;
1496 }
1497 }
1498 else
1499 {
1500 /* Flush TX register */
1501 I2C_Flush_TXDR(hi2c);
1502
1503 /* Clear AF flag */
1504 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
1505
1506 /* Wait until STOP flag is set */
1507 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1508 {
1509 /* Disable Address Acknowledge */
1510 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1511
1512 return HAL_ERROR;
1513 }
1514
1515 /* Clear STOP flag */
1516 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1517 }
1518
1519 /* Wait until BUSY flag is reset */
1520 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1521 {
1522 /* Disable Address Acknowledge */
1523 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1524 return HAL_ERROR;
1525 }
1526
1527 /* Disable Address Acknowledge */
1528 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1529
1530 hi2c->State = HAL_I2C_STATE_READY;
1531 hi2c->Mode = HAL_I2C_MODE_NONE;
1532
1533 /* Process Unlocked */
1534 __HAL_UNLOCK(hi2c);
1535
1536 return HAL_OK;
1537 }
1538 else
1539 {
1540 return HAL_BUSY;
1541 }
1542 }
1543
1544 /**
1545 * @brief Receive in slave mode an amount of data in blocking mode
1546 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1547 * the configuration information for the specified I2C.
1548 * @param pData Pointer to data buffer
1549 * @param Size Amount of data to be sent
1550 * @param Timeout Timeout duration
1551 * @retval HAL status
1552 */
HAL_I2C_Slave_Receive(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1553 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
1554 uint32_t Timeout)
1555 {
1556 uint32_t tickstart;
1557
1558 if (hi2c->State == HAL_I2C_STATE_READY)
1559 {
1560 if ((pData == NULL) || (Size == 0U))
1561 {
1562 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
1563 return HAL_ERROR;
1564 }
1565 /* Process Locked */
1566 __HAL_LOCK(hi2c);
1567
1568 /* Init tickstart for timeout management*/
1569 tickstart = HAL_GetTick();
1570
1571 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1572 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1573 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1574
1575 /* Prepare transfer parameters */
1576 hi2c->pBuffPtr = pData;
1577 hi2c->XferCount = Size;
1578 hi2c->XferSize = hi2c->XferCount;
1579 hi2c->XferISR = NULL;
1580
1581 /* Enable Address Acknowledge */
1582 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1583
1584 /* Wait until ADDR flag is set */
1585 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1586 {
1587 /* Disable Address Acknowledge */
1588 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1589 return HAL_ERROR;
1590 }
1591
1592 /* Clear ADDR flag */
1593 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1594
1595 /* Wait until DIR flag is reset Receiver mode */
1596 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
1597 {
1598 /* Disable Address Acknowledge */
1599 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1600 return HAL_ERROR;
1601 }
1602
1603 while (hi2c->XferCount > 0U)
1604 {
1605 /* Wait until RXNE flag is set */
1606 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1607 {
1608 /* Disable Address Acknowledge */
1609 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1610
1611 /* Store Last receive data if any */
1612 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
1613 {
1614 /* Read data from RXDR */
1615 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1616
1617 /* Increment Buffer pointer */
1618 hi2c->pBuffPtr++;
1619
1620 hi2c->XferCount--;
1621 hi2c->XferSize--;
1622 }
1623
1624 return HAL_ERROR;
1625 }
1626
1627 /* Read data from RXDR */
1628 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1629
1630 /* Increment Buffer pointer */
1631 hi2c->pBuffPtr++;
1632
1633 hi2c->XferCount--;
1634 hi2c->XferSize--;
1635 }
1636
1637 /* Wait until STOP flag is set */
1638 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1639 {
1640 /* Disable Address Acknowledge */
1641 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1642 return HAL_ERROR;
1643 }
1644
1645 /* Clear STOP flag */
1646 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1647
1648 /* Wait until BUSY flag is reset */
1649 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1650 {
1651 /* Disable Address Acknowledge */
1652 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1653 return HAL_ERROR;
1654 }
1655
1656 /* Disable Address Acknowledge */
1657 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1658
1659 hi2c->State = HAL_I2C_STATE_READY;
1660 hi2c->Mode = HAL_I2C_MODE_NONE;
1661
1662 /* Process Unlocked */
1663 __HAL_UNLOCK(hi2c);
1664
1665 return HAL_OK;
1666 }
1667 else
1668 {
1669 return HAL_BUSY;
1670 }
1671 }
1672
1673 /**
1674 * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
1675 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1676 * the configuration information for the specified I2C.
1677 * @param DevAddress Target device address: The device 7 bits address value
1678 * in datasheet must be shifted to the left before calling the interface
1679 * @param pData Pointer to data buffer
1680 * @param Size Amount of data to be sent
1681 * @retval HAL status
1682 */
HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1683 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1684 uint16_t Size)
1685 {
1686 uint32_t xfermode;
1687
1688 if (hi2c->State == HAL_I2C_STATE_READY)
1689 {
1690 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1691 {
1692 return HAL_BUSY;
1693 }
1694
1695 /* Process Locked */
1696 __HAL_LOCK(hi2c);
1697
1698 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1699 hi2c->Mode = HAL_I2C_MODE_MASTER;
1700 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1701
1702 /* Prepare transfer parameters */
1703 hi2c->pBuffPtr = pData;
1704 hi2c->XferCount = Size;
1705 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1706 hi2c->XferISR = I2C_Master_ISR_IT;
1707
1708 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1709 {
1710 hi2c->XferSize = MAX_NBYTE_SIZE;
1711 xfermode = I2C_RELOAD_MODE;
1712 }
1713 else
1714 {
1715 hi2c->XferSize = hi2c->XferCount;
1716 xfermode = I2C_AUTOEND_MODE;
1717 }
1718
1719 /* Send Slave Address */
1720 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1721 if (hi2c->XferSize > 0U)
1722 {
1723 /* Preload TX register */
1724 /* Write data to TXDR */
1725 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1726
1727 /* Increment Buffer pointer */
1728 hi2c->pBuffPtr++;
1729
1730 hi2c->XferCount--;
1731 hi2c->XferSize--;
1732
1733 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode,
1734 I2C_GENERATE_START_WRITE);
1735 }
1736 else
1737 {
1738 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
1739 I2C_GENERATE_START_WRITE);
1740 }
1741
1742 /* Process Unlocked */
1743 __HAL_UNLOCK(hi2c);
1744
1745 /* Note : The I2C interrupts must be enabled after unlocking current process
1746 to avoid the risk of I2C interrupt handle execution before current
1747 process unlock */
1748
1749 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1750 /* possible to enable all of these */
1751 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1752 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1753 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
1754
1755 return HAL_OK;
1756 }
1757 else
1758 {
1759 return HAL_BUSY;
1760 }
1761 }
1762
1763 /**
1764 * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
1765 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1766 * the configuration information for the specified I2C.
1767 * @param DevAddress Target device address: The device 7 bits address value
1768 * in datasheet must be shifted to the left before calling the interface
1769 * @param pData Pointer to data buffer
1770 * @param Size Amount of data to be sent
1771 * @retval HAL status
1772 */
HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1773 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1774 uint16_t Size)
1775 {
1776 uint32_t xfermode;
1777
1778 if (hi2c->State == HAL_I2C_STATE_READY)
1779 {
1780 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1781 {
1782 return HAL_BUSY;
1783 }
1784
1785 /* Process Locked */
1786 __HAL_LOCK(hi2c);
1787
1788 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1789 hi2c->Mode = HAL_I2C_MODE_MASTER;
1790 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1791
1792 /* Prepare transfer parameters */
1793 hi2c->pBuffPtr = pData;
1794 hi2c->XferCount = Size;
1795 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1796 hi2c->XferISR = I2C_Master_ISR_IT;
1797
1798 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1799 {
1800 hi2c->XferSize = MAX_NBYTE_SIZE;
1801 xfermode = I2C_RELOAD_MODE;
1802 }
1803 else
1804 {
1805 hi2c->XferSize = hi2c->XferCount;
1806 xfermode = I2C_AUTOEND_MODE;
1807 }
1808
1809 /* Send Slave Address */
1810 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1811 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
1812
1813 /* Process Unlocked */
1814 __HAL_UNLOCK(hi2c);
1815
1816 /* Note : The I2C interrupts must be enabled after unlocking current process
1817 to avoid the risk of I2C interrupt handle execution before current
1818 process unlock */
1819
1820 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1821 /* possible to enable all of these */
1822 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1823 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1824 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
1825
1826 return HAL_OK;
1827 }
1828 else
1829 {
1830 return HAL_BUSY;
1831 }
1832 }
1833
1834 /**
1835 * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
1836 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1837 * the configuration information for the specified I2C.
1838 * @param pData Pointer to data buffer
1839 * @param Size Amount of data to be sent
1840 * @retval HAL status
1841 */
HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1842 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1843 {
1844 if (hi2c->State == HAL_I2C_STATE_READY)
1845 {
1846 /* Process Locked */
1847 __HAL_LOCK(hi2c);
1848
1849 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1850 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1851 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1852
1853 /* Enable Address Acknowledge */
1854 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1855
1856 /* Prepare transfer parameters */
1857 hi2c->pBuffPtr = pData;
1858 hi2c->XferCount = Size;
1859 hi2c->XferSize = hi2c->XferCount;
1860 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1861 hi2c->XferISR = I2C_Slave_ISR_IT;
1862
1863 /* Preload TX data if no stretch enable */
1864 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
1865 {
1866 /* Preload TX register */
1867 /* Write data to TXDR */
1868 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1869
1870 /* Increment Buffer pointer */
1871 hi2c->pBuffPtr++;
1872
1873 hi2c->XferCount--;
1874 hi2c->XferSize--;
1875 }
1876
1877 /* Process Unlocked */
1878 __HAL_UNLOCK(hi2c);
1879
1880 /* Note : The I2C interrupts must be enabled after unlocking current process
1881 to avoid the risk of I2C interrupt handle execution before current
1882 process unlock */
1883
1884 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1885 /* possible to enable all of these */
1886 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1887 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1888 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
1889
1890 return HAL_OK;
1891 }
1892 else
1893 {
1894 return HAL_BUSY;
1895 }
1896 }
1897
1898 /**
1899 * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
1900 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1901 * the configuration information for the specified I2C.
1902 * @param pData Pointer to data buffer
1903 * @param Size Amount of data to be sent
1904 * @retval HAL status
1905 */
HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1906 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1907 {
1908 if (hi2c->State == HAL_I2C_STATE_READY)
1909 {
1910 /* Process Locked */
1911 __HAL_LOCK(hi2c);
1912
1913 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1914 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1915 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1916
1917 /* Enable Address Acknowledge */
1918 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1919
1920 /* Prepare transfer parameters */
1921 hi2c->pBuffPtr = pData;
1922 hi2c->XferCount = Size;
1923 hi2c->XferSize = hi2c->XferCount;
1924 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1925 hi2c->XferISR = I2C_Slave_ISR_IT;
1926
1927 /* Process Unlocked */
1928 __HAL_UNLOCK(hi2c);
1929
1930 /* Note : The I2C interrupts must be enabled after unlocking current process
1931 to avoid the risk of I2C interrupt handle execution before current
1932 process unlock */
1933
1934 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1935 /* possible to enable all of these */
1936 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1937 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1938 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
1939
1940 return HAL_OK;
1941 }
1942 else
1943 {
1944 return HAL_BUSY;
1945 }
1946 }
1947
1948 /**
1949 * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
1950 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1951 * the configuration information for the specified I2C.
1952 * @param DevAddress Target device address: The device 7 bits address value
1953 * in datasheet must be shifted to the left before calling the interface
1954 * @param pData Pointer to data buffer
1955 * @param Size Amount of data to be sent
1956 * @retval HAL status
1957 */
HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1958 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1959 uint16_t Size)
1960 {
1961 uint32_t xfermode;
1962 HAL_StatusTypeDef dmaxferstatus;
1963 uint32_t sizetoxfer = 0U;
1964
1965 if (hi2c->State == HAL_I2C_STATE_READY)
1966 {
1967 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1968 {
1969 return HAL_BUSY;
1970 }
1971
1972 /* Process Locked */
1973 __HAL_LOCK(hi2c);
1974
1975 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1976 hi2c->Mode = HAL_I2C_MODE_MASTER;
1977 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1978
1979 /* Prepare transfer parameters */
1980 hi2c->pBuffPtr = pData;
1981 hi2c->XferCount = Size;
1982 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1983 hi2c->XferISR = I2C_Master_ISR_DMA;
1984
1985 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1986 {
1987 hi2c->XferSize = MAX_NBYTE_SIZE;
1988 xfermode = I2C_RELOAD_MODE;
1989 }
1990 else
1991 {
1992 hi2c->XferSize = hi2c->XferCount;
1993 xfermode = I2C_AUTOEND_MODE;
1994 }
1995
1996 if (hi2c->XferSize > 0U)
1997 {
1998 /* Preload TX register */
1999 /* Write data to TXDR */
2000 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
2001
2002 /* Increment Buffer pointer */
2003 hi2c->pBuffPtr++;
2004
2005 sizetoxfer = hi2c->XferSize;
2006 hi2c->XferCount--;
2007 hi2c->XferSize--;
2008 }
2009
2010 if (hi2c->XferSize > 0U)
2011 {
2012 if (hi2c->hdmatx != NULL)
2013 {
2014 /* Set the I2C DMA transfer complete callback */
2015 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
2016
2017 /* Set the DMA error callback */
2018 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2019
2020 /* Set the unused DMA callbacks to NULL */
2021 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2022 hi2c->hdmatx->XferAbortCallback = NULL;
2023
2024 /* Enable the DMA channel */
2025 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr,
2026 (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
2027 }
2028 else
2029 {
2030 /* Update I2C state */
2031 hi2c->State = HAL_I2C_STATE_READY;
2032 hi2c->Mode = HAL_I2C_MODE_NONE;
2033
2034 /* Update I2C error code */
2035 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2036
2037 /* Process Unlocked */
2038 __HAL_UNLOCK(hi2c);
2039
2040 return HAL_ERROR;
2041 }
2042
2043 if (dmaxferstatus == HAL_OK)
2044 {
2045 /* Send Slave Address */
2046 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2047 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U),
2048 xfermode, I2C_GENERATE_START_WRITE);
2049
2050 /* Update XferCount value */
2051 hi2c->XferCount -= hi2c->XferSize;
2052
2053 /* Process Unlocked */
2054 __HAL_UNLOCK(hi2c);
2055
2056 /* Note : The I2C interrupts must be enabled after unlocking current process
2057 to avoid the risk of I2C interrupt handle execution before current
2058 process unlock */
2059 /* Enable ERR and NACK interrupts */
2060 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
2061
2062 /* Enable DMA Request */
2063 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
2064 }
2065 else
2066 {
2067 /* Update I2C state */
2068 hi2c->State = HAL_I2C_STATE_READY;
2069 hi2c->Mode = HAL_I2C_MODE_NONE;
2070
2071 /* Update I2C error code */
2072 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2073
2074 /* Process Unlocked */
2075 __HAL_UNLOCK(hi2c);
2076
2077 return HAL_ERROR;
2078 }
2079 }
2080 else
2081 {
2082 /* Update Transfer ISR function pointer */
2083 hi2c->XferISR = I2C_Master_ISR_IT;
2084
2085 /* Send Slave Address */
2086 /* Set NBYTES to write and generate START condition */
2087 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, I2C_AUTOEND_MODE,
2088 I2C_GENERATE_START_WRITE);
2089
2090 /* Process Unlocked */
2091 __HAL_UNLOCK(hi2c);
2092
2093 /* Note : The I2C interrupts must be enabled after unlocking current process
2094 to avoid the risk of I2C interrupt handle execution before current
2095 process unlock */
2096 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2097 /* possible to enable all of these */
2098 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2099 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2100 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2101 }
2102
2103 return HAL_OK;
2104 }
2105 else
2106 {
2107 return HAL_BUSY;
2108 }
2109 }
2110
2111 /**
2112 * @brief Receive in master mode an amount of data in non-blocking mode with DMA
2113 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2114 * the configuration information for the specified I2C.
2115 * @param DevAddress Target device address: The device 7 bits address value
2116 * in datasheet must be shifted to the left before calling the interface
2117 * @param pData Pointer to data buffer
2118 * @param Size Amount of data to be sent
2119 * @retval HAL status
2120 */
HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)2121 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
2122 uint16_t Size)
2123 {
2124 uint32_t xfermode;
2125 HAL_StatusTypeDef dmaxferstatus;
2126
2127 if (hi2c->State == HAL_I2C_STATE_READY)
2128 {
2129 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2130 {
2131 return HAL_BUSY;
2132 }
2133
2134 /* Process Locked */
2135 __HAL_LOCK(hi2c);
2136
2137 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2138 hi2c->Mode = HAL_I2C_MODE_MASTER;
2139 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2140
2141 /* Prepare transfer parameters */
2142 hi2c->pBuffPtr = pData;
2143 hi2c->XferCount = Size;
2144 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2145 hi2c->XferISR = I2C_Master_ISR_DMA;
2146
2147 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2148 {
2149 hi2c->XferSize = MAX_NBYTE_SIZE;
2150 xfermode = I2C_RELOAD_MODE;
2151 }
2152 else
2153 {
2154 hi2c->XferSize = hi2c->XferCount;
2155 xfermode = I2C_AUTOEND_MODE;
2156 }
2157
2158 if (hi2c->XferSize > 0U)
2159 {
2160 if (hi2c->hdmarx != NULL)
2161 {
2162 /* Set the I2C DMA transfer complete callback */
2163 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
2164
2165 /* Set the DMA error callback */
2166 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2167
2168 /* Set the unused DMA callbacks to NULL */
2169 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2170 hi2c->hdmarx->XferAbortCallback = NULL;
2171
2172 /* Enable the DMA channel */
2173 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
2174 hi2c->XferSize);
2175 }
2176 else
2177 {
2178 /* Update I2C state */
2179 hi2c->State = HAL_I2C_STATE_READY;
2180 hi2c->Mode = HAL_I2C_MODE_NONE;
2181
2182 /* Update I2C error code */
2183 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2184
2185 /* Process Unlocked */
2186 __HAL_UNLOCK(hi2c);
2187
2188 return HAL_ERROR;
2189 }
2190
2191 if (dmaxferstatus == HAL_OK)
2192 {
2193 /* Send Slave Address */
2194 /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2195 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
2196
2197 /* Update XferCount value */
2198 hi2c->XferCount -= hi2c->XferSize;
2199
2200 /* Process Unlocked */
2201 __HAL_UNLOCK(hi2c);
2202
2203 /* Note : The I2C interrupts must be enabled after unlocking current process
2204 to avoid the risk of I2C interrupt handle execution before current
2205 process unlock */
2206 /* Enable ERR and NACK interrupts */
2207 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
2208
2209 /* Enable DMA Request */
2210 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2211 }
2212 else
2213 {
2214 /* Update I2C state */
2215 hi2c->State = HAL_I2C_STATE_READY;
2216 hi2c->Mode = HAL_I2C_MODE_NONE;
2217
2218 /* Update I2C error code */
2219 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2220
2221 /* Process Unlocked */
2222 __HAL_UNLOCK(hi2c);
2223
2224 return HAL_ERROR;
2225 }
2226 }
2227 else
2228 {
2229 /* Update Transfer ISR function pointer */
2230 hi2c->XferISR = I2C_Master_ISR_IT;
2231
2232 /* Send Slave Address */
2233 /* Set NBYTES to read and generate START condition */
2234 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2235 I2C_GENERATE_START_READ);
2236
2237 /* Process Unlocked */
2238 __HAL_UNLOCK(hi2c);
2239
2240 /* Note : The I2C interrupts must be enabled after unlocking current process
2241 to avoid the risk of I2C interrupt handle execution before current
2242 process unlock */
2243 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
2244 /* possible to enable all of these */
2245 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2246 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2247 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
2248 }
2249
2250 return HAL_OK;
2251 }
2252 else
2253 {
2254 return HAL_BUSY;
2255 }
2256 }
2257
2258 /**
2259 * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
2260 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2261 * the configuration information for the specified I2C.
2262 * @param pData Pointer to data buffer
2263 * @param Size Amount of data to be sent
2264 * @retval HAL status
2265 */
HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2266 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2267 {
2268 HAL_StatusTypeDef dmaxferstatus;
2269
2270 if (hi2c->State == HAL_I2C_STATE_READY)
2271 {
2272 if ((pData == NULL) || (Size == 0U))
2273 {
2274 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2275 return HAL_ERROR;
2276 }
2277 /* Process Locked */
2278 __HAL_LOCK(hi2c);
2279
2280 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2281 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2282 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2283
2284 /* Prepare transfer parameters */
2285 hi2c->pBuffPtr = pData;
2286 hi2c->XferCount = Size;
2287 hi2c->XferSize = hi2c->XferCount;
2288 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2289 hi2c->XferISR = I2C_Slave_ISR_DMA;
2290
2291 /* Preload TX data if no stretch enable */
2292 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
2293 {
2294 /* Preload TX register */
2295 /* Write data to TXDR */
2296 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
2297
2298 /* Increment Buffer pointer */
2299 hi2c->pBuffPtr++;
2300
2301 hi2c->XferCount--;
2302 hi2c->XferSize--;
2303 }
2304
2305 if (hi2c->XferCount != 0U)
2306 {
2307 if (hi2c->hdmatx != NULL)
2308 {
2309 /* Set the I2C DMA transfer complete callback */
2310 hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
2311
2312 /* Set the DMA error callback */
2313 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2314
2315 /* Set the unused DMA callbacks to NULL */
2316 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2317 hi2c->hdmatx->XferAbortCallback = NULL;
2318
2319 /* Enable the DMA channel */
2320 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx,
2321 (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
2322 hi2c->XferSize);
2323 }
2324 else
2325 {
2326 /* Update I2C state */
2327 hi2c->State = HAL_I2C_STATE_LISTEN;
2328 hi2c->Mode = HAL_I2C_MODE_NONE;
2329
2330 /* Update I2C error code */
2331 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2332
2333 /* Process Unlocked */
2334 __HAL_UNLOCK(hi2c);
2335
2336 return HAL_ERROR;
2337 }
2338
2339 if (dmaxferstatus == HAL_OK)
2340 {
2341 /* Enable Address Acknowledge */
2342 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2343
2344 /* Process Unlocked */
2345 __HAL_UNLOCK(hi2c);
2346
2347 /* Note : The I2C interrupts must be enabled after unlocking current process
2348 to avoid the risk of I2C interrupt handle execution before current
2349 process unlock */
2350 /* Enable ERR, STOP, NACK, ADDR interrupts */
2351 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2352
2353 /* Enable DMA Request */
2354 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
2355 }
2356 else
2357 {
2358 /* Update I2C state */
2359 hi2c->State = HAL_I2C_STATE_LISTEN;
2360 hi2c->Mode = HAL_I2C_MODE_NONE;
2361
2362 /* Update I2C error code */
2363 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2364
2365 /* Process Unlocked */
2366 __HAL_UNLOCK(hi2c);
2367
2368 return HAL_ERROR;
2369 }
2370 }
2371 else
2372 {
2373 /* Enable Address Acknowledge */
2374 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2375
2376 /* Process Unlocked */
2377 __HAL_UNLOCK(hi2c);
2378
2379 /* Note : The I2C interrupts must be enabled after unlocking current process
2380 to avoid the risk of I2C interrupt handle execution before current
2381 process unlock */
2382 /* Enable ERR, STOP, NACK, ADDR interrupts */
2383 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2384 }
2385
2386 return HAL_OK;
2387 }
2388 else
2389 {
2390 return HAL_BUSY;
2391 }
2392 }
2393
2394 /**
2395 * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
2396 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2397 * the configuration information for the specified I2C.
2398 * @param pData Pointer to data buffer
2399 * @param Size Amount of data to be sent
2400 * @retval HAL status
2401 */
HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2402 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2403 {
2404 HAL_StatusTypeDef dmaxferstatus;
2405
2406 if (hi2c->State == HAL_I2C_STATE_READY)
2407 {
2408 if ((pData == NULL) || (Size == 0U))
2409 {
2410 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2411 return HAL_ERROR;
2412 }
2413 /* Process Locked */
2414 __HAL_LOCK(hi2c);
2415
2416 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2417 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2418 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2419
2420 /* Prepare transfer parameters */
2421 hi2c->pBuffPtr = pData;
2422 hi2c->XferCount = Size;
2423 hi2c->XferSize = hi2c->XferCount;
2424 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2425 hi2c->XferISR = I2C_Slave_ISR_DMA;
2426
2427 if (hi2c->hdmarx != NULL)
2428 {
2429 /* Set the I2C DMA transfer complete callback */
2430 hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
2431
2432 /* Set the DMA error callback */
2433 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2434
2435 /* Set the unused DMA callbacks to NULL */
2436 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2437 hi2c->hdmarx->XferAbortCallback = NULL;
2438
2439 /* Enable the DMA channel */
2440 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
2441 hi2c->XferSize);
2442 }
2443 else
2444 {
2445 /* Update I2C state */
2446 hi2c->State = HAL_I2C_STATE_LISTEN;
2447 hi2c->Mode = HAL_I2C_MODE_NONE;
2448
2449 /* Update I2C error code */
2450 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2451
2452 /* Process Unlocked */
2453 __HAL_UNLOCK(hi2c);
2454
2455 return HAL_ERROR;
2456 }
2457
2458 if (dmaxferstatus == HAL_OK)
2459 {
2460 /* Enable Address Acknowledge */
2461 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2462
2463 /* Process Unlocked */
2464 __HAL_UNLOCK(hi2c);
2465
2466 /* Note : The I2C interrupts must be enabled after unlocking current process
2467 to avoid the risk of I2C interrupt handle execution before current
2468 process unlock */
2469 /* Enable ERR, STOP, NACK, ADDR interrupts */
2470 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2471
2472 /* Enable DMA Request */
2473 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2474 }
2475 else
2476 {
2477 /* Update I2C state */
2478 hi2c->State = HAL_I2C_STATE_LISTEN;
2479 hi2c->Mode = HAL_I2C_MODE_NONE;
2480
2481 /* Update I2C error code */
2482 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2483
2484 /* Process Unlocked */
2485 __HAL_UNLOCK(hi2c);
2486
2487 return HAL_ERROR;
2488 }
2489
2490 return HAL_OK;
2491 }
2492 else
2493 {
2494 return HAL_BUSY;
2495 }
2496 }
2497
2498 /**
2499 * @brief Write an amount of data in blocking mode to a specific memory address
2500 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2501 * the configuration information for the specified I2C.
2502 * @param DevAddress Target device address: The device 7 bits address value
2503 * in datasheet must be shifted to the left before calling the interface
2504 * @param MemAddress Internal memory address
2505 * @param MemAddSize Size of internal memory address
2506 * @param pData Pointer to data buffer
2507 * @param Size Amount of data to be sent
2508 * @param Timeout Timeout duration
2509 * @retval HAL status
2510 */
HAL_I2C_Mem_Write(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2511 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2512 uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2513 {
2514 uint32_t tickstart;
2515
2516 /* Check the parameters */
2517 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2518
2519 if (hi2c->State == HAL_I2C_STATE_READY)
2520 {
2521 if ((pData == NULL) || (Size == 0U))
2522 {
2523 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2524 return HAL_ERROR;
2525 }
2526
2527 /* Process Locked */
2528 __HAL_LOCK(hi2c);
2529
2530 /* Init tickstart for timeout management*/
2531 tickstart = HAL_GetTick();
2532
2533 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
2534 {
2535 return HAL_ERROR;
2536 }
2537
2538 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2539 hi2c->Mode = HAL_I2C_MODE_MEM;
2540 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2541
2542 /* Prepare transfer parameters */
2543 hi2c->pBuffPtr = pData;
2544 hi2c->XferCount = Size;
2545 hi2c->XferISR = NULL;
2546
2547 /* Send Slave Address and Memory Address */
2548 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2549 {
2550 /* Process Unlocked */
2551 __HAL_UNLOCK(hi2c);
2552 return HAL_ERROR;
2553 }
2554
2555 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
2556 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2557 {
2558 hi2c->XferSize = MAX_NBYTE_SIZE;
2559 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
2560 }
2561 else
2562 {
2563 hi2c->XferSize = hi2c->XferCount;
2564 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
2565 }
2566
2567 do
2568 {
2569 /* Wait until TXIS flag is set */
2570 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2571 {
2572 return HAL_ERROR;
2573 }
2574
2575 /* Write data to TXDR */
2576 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
2577
2578 /* Increment Buffer pointer */
2579 hi2c->pBuffPtr++;
2580
2581 hi2c->XferCount--;
2582 hi2c->XferSize--;
2583
2584 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
2585 {
2586 /* Wait until TCR flag is set */
2587 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
2588 {
2589 return HAL_ERROR;
2590 }
2591
2592 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2593 {
2594 hi2c->XferSize = MAX_NBYTE_SIZE;
2595 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
2596 I2C_NO_STARTSTOP);
2597 }
2598 else
2599 {
2600 hi2c->XferSize = hi2c->XferCount;
2601 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2602 I2C_NO_STARTSTOP);
2603 }
2604 }
2605
2606 } while (hi2c->XferCount > 0U);
2607
2608 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2609 /* Wait until STOPF flag is reset */
2610 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2611 {
2612 return HAL_ERROR;
2613 }
2614
2615 /* Clear STOP Flag */
2616 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2617
2618 /* Clear Configuration Register 2 */
2619 I2C_RESET_CR2(hi2c);
2620
2621 hi2c->State = HAL_I2C_STATE_READY;
2622 hi2c->Mode = HAL_I2C_MODE_NONE;
2623
2624 /* Process Unlocked */
2625 __HAL_UNLOCK(hi2c);
2626
2627 return HAL_OK;
2628 }
2629 else
2630 {
2631 return HAL_BUSY;
2632 }
2633 }
2634
2635 /**
2636 * @brief Read an amount of data in blocking mode from a specific memory address
2637 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2638 * the configuration information for the specified I2C.
2639 * @param DevAddress Target device address: The device 7 bits address value
2640 * in datasheet must be shifted to the left before calling the interface
2641 * @param MemAddress Internal memory address
2642 * @param MemAddSize Size of internal memory address
2643 * @param pData Pointer to data buffer
2644 * @param Size Amount of data to be sent
2645 * @param Timeout Timeout duration
2646 * @retval HAL status
2647 */
HAL_I2C_Mem_Read(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2648 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2649 uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2650 {
2651 uint32_t tickstart;
2652
2653 /* Check the parameters */
2654 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2655
2656 if (hi2c->State == HAL_I2C_STATE_READY)
2657 {
2658 if ((pData == NULL) || (Size == 0U))
2659 {
2660 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2661 return HAL_ERROR;
2662 }
2663
2664 /* Process Locked */
2665 __HAL_LOCK(hi2c);
2666
2667 /* Init tickstart for timeout management*/
2668 tickstart = HAL_GetTick();
2669
2670 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
2671 {
2672 return HAL_ERROR;
2673 }
2674
2675 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2676 hi2c->Mode = HAL_I2C_MODE_MEM;
2677 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2678
2679 /* Prepare transfer parameters */
2680 hi2c->pBuffPtr = pData;
2681 hi2c->XferCount = Size;
2682 hi2c->XferISR = NULL;
2683
2684 /* Send Slave Address and Memory Address */
2685 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2686 {
2687 /* Process Unlocked */
2688 __HAL_UNLOCK(hi2c);
2689 return HAL_ERROR;
2690 }
2691
2692 /* Send Slave Address */
2693 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2694 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2695 {
2696 hi2c->XferSize = MAX_NBYTE_SIZE;
2697 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
2698 I2C_GENERATE_START_READ);
2699 }
2700 else
2701 {
2702 hi2c->XferSize = hi2c->XferCount;
2703 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2704 I2C_GENERATE_START_READ);
2705 }
2706
2707 do
2708 {
2709 /* Wait until RXNE flag is set */
2710 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
2711 {
2712 return HAL_ERROR;
2713 }
2714
2715 /* Read data from RXDR */
2716 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
2717
2718 /* Increment Buffer pointer */
2719 hi2c->pBuffPtr++;
2720
2721 hi2c->XferSize--;
2722 hi2c->XferCount--;
2723
2724 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
2725 {
2726 /* Wait until TCR flag is set */
2727 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
2728 {
2729 return HAL_ERROR;
2730 }
2731
2732 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2733 {
2734 hi2c->XferSize = MAX_NBYTE_SIZE;
2735 I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
2736 I2C_NO_STARTSTOP);
2737 }
2738 else
2739 {
2740 hi2c->XferSize = hi2c->XferCount;
2741 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2742 I2C_NO_STARTSTOP);
2743 }
2744 }
2745 } while (hi2c->XferCount > 0U);
2746
2747 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2748 /* Wait until STOPF flag is reset */
2749 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2750 {
2751 return HAL_ERROR;
2752 }
2753
2754 /* Clear STOP Flag */
2755 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2756
2757 /* Clear Configuration Register 2 */
2758 I2C_RESET_CR2(hi2c);
2759
2760 hi2c->State = HAL_I2C_STATE_READY;
2761 hi2c->Mode = HAL_I2C_MODE_NONE;
2762
2763 /* Process Unlocked */
2764 __HAL_UNLOCK(hi2c);
2765
2766 return HAL_OK;
2767 }
2768 else
2769 {
2770 return HAL_BUSY;
2771 }
2772 }
2773 /**
2774 * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
2775 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2776 * the configuration information for the specified I2C.
2777 * @param DevAddress Target device address: The device 7 bits address value
2778 * in datasheet must be shifted to the left before calling the interface
2779 * @param MemAddress Internal memory address
2780 * @param MemAddSize Size of internal memory address
2781 * @param pData Pointer to data buffer
2782 * @param Size Amount of data to be sent
2783 * @retval HAL status
2784 */
HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2785 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2786 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2787 {
2788 /* Check the parameters */
2789 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2790
2791 if (hi2c->State == HAL_I2C_STATE_READY)
2792 {
2793 if ((pData == NULL) || (Size == 0U))
2794 {
2795 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2796 return HAL_ERROR;
2797 }
2798
2799 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2800 {
2801 return HAL_BUSY;
2802 }
2803
2804 /* Process Locked */
2805 __HAL_LOCK(hi2c);
2806
2807 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2808 hi2c->Mode = HAL_I2C_MODE_MEM;
2809 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2810
2811 /* Prepare transfer parameters */
2812 hi2c->XferSize = 0U;
2813 hi2c->pBuffPtr = pData;
2814 hi2c->XferCount = Size;
2815 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2816 hi2c->XferISR = I2C_Mem_ISR_IT;
2817 hi2c->Devaddress = DevAddress;
2818
2819 /* If Memory address size is 8Bit */
2820 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
2821 {
2822 /* Prefetch Memory Address */
2823 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
2824
2825 /* Reset Memaddress content */
2826 hi2c->Memaddress = 0xFFFFFFFFU;
2827 }
2828 /* If Memory address size is 16Bit */
2829 else
2830 {
2831 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
2832 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
2833
2834 /* Prepare Memaddress buffer for LSB part */
2835 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
2836 }
2837 /* Send Slave Address and Memory Address */
2838 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
2839
2840 /* Process Unlocked */
2841 __HAL_UNLOCK(hi2c);
2842
2843 /* Note : The I2C interrupts must be enabled after unlocking current process
2844 to avoid the risk of I2C interrupt handle execution before current
2845 process unlock */
2846
2847 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2848 /* possible to enable all of these */
2849 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2850 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2851 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2852
2853 return HAL_OK;
2854 }
2855 else
2856 {
2857 return HAL_BUSY;
2858 }
2859 }
2860
2861 /**
2862 * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
2863 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2864 * the configuration information for the specified I2C.
2865 * @param DevAddress Target device address: The device 7 bits address value
2866 * in datasheet must be shifted to the left before calling the interface
2867 * @param MemAddress Internal memory address
2868 * @param MemAddSize Size of internal memory address
2869 * @param pData Pointer to data buffer
2870 * @param Size Amount of data to be sent
2871 * @retval HAL status
2872 */
HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2873 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2874 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2875 {
2876 /* Check the parameters */
2877 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2878
2879 if (hi2c->State == HAL_I2C_STATE_READY)
2880 {
2881 if ((pData == NULL) || (Size == 0U))
2882 {
2883 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2884 return HAL_ERROR;
2885 }
2886
2887 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2888 {
2889 return HAL_BUSY;
2890 }
2891
2892 /* Process Locked */
2893 __HAL_LOCK(hi2c);
2894
2895 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2896 hi2c->Mode = HAL_I2C_MODE_MEM;
2897 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2898
2899 /* Prepare transfer parameters */
2900 hi2c->pBuffPtr = pData;
2901 hi2c->XferCount = Size;
2902 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2903 hi2c->XferISR = I2C_Mem_ISR_IT;
2904 hi2c->Devaddress = DevAddress;
2905
2906 /* If Memory address size is 8Bit */
2907 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
2908 {
2909 /* Prefetch Memory Address */
2910 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
2911
2912 /* Reset Memaddress content */
2913 hi2c->Memaddress = 0xFFFFFFFFU;
2914 }
2915 /* If Memory address size is 16Bit */
2916 else
2917 {
2918 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
2919 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
2920
2921 /* Prepare Memaddress buffer for LSB part */
2922 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
2923 }
2924 /* Send Slave Address and Memory Address */
2925 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
2926
2927 /* Process Unlocked */
2928 __HAL_UNLOCK(hi2c);
2929
2930 /* Note : The I2C interrupts must be enabled after unlocking current process
2931 to avoid the risk of I2C interrupt handle execution before current
2932 process unlock */
2933
2934 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2935 /* possible to enable all of these */
2936 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2937 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2938 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2939
2940 return HAL_OK;
2941 }
2942 else
2943 {
2944 return HAL_BUSY;
2945 }
2946 }
2947
2948 /**
2949 * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
2950 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2951 * the configuration information for the specified I2C.
2952 * @param DevAddress Target device address: The device 7 bits address value
2953 * in datasheet must be shifted to the left before calling the interface
2954 * @param MemAddress Internal memory address
2955 * @param MemAddSize Size of internal memory address
2956 * @param pData Pointer to data buffer
2957 * @param Size Amount of data to be sent
2958 * @retval HAL status
2959 */
HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2960 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2961 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2962 {
2963 HAL_StatusTypeDef dmaxferstatus;
2964
2965 /* Check the parameters */
2966 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2967
2968 if (hi2c->State == HAL_I2C_STATE_READY)
2969 {
2970 if ((pData == NULL) || (Size == 0U))
2971 {
2972 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2973 return HAL_ERROR;
2974 }
2975
2976 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2977 {
2978 return HAL_BUSY;
2979 }
2980
2981 /* Process Locked */
2982 __HAL_LOCK(hi2c);
2983
2984 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2985 hi2c->Mode = HAL_I2C_MODE_MEM;
2986 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2987
2988 /* Prepare transfer parameters */
2989 hi2c->pBuffPtr = pData;
2990 hi2c->XferCount = Size;
2991 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2992 hi2c->XferISR = I2C_Mem_ISR_DMA;
2993 hi2c->Devaddress = DevAddress;
2994
2995 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2996 {
2997 hi2c->XferSize = MAX_NBYTE_SIZE;
2998 }
2999 else
3000 {
3001 hi2c->XferSize = hi2c->XferCount;
3002 }
3003
3004 /* If Memory address size is 8Bit */
3005 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
3006 {
3007 /* Prefetch Memory Address */
3008 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3009
3010 /* Reset Memaddress content */
3011 hi2c->Memaddress = 0xFFFFFFFFU;
3012 }
3013 /* If Memory address size is 16Bit */
3014 else
3015 {
3016 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
3017 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
3018
3019 /* Prepare Memaddress buffer for LSB part */
3020 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
3021 }
3022
3023 if (hi2c->hdmatx != NULL)
3024 {
3025 /* Set the I2C DMA transfer complete callback */
3026 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
3027
3028 /* Set the DMA error callback */
3029 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3030
3031 /* Set the unused DMA callbacks to NULL */
3032 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3033 hi2c->hdmatx->XferAbortCallback = NULL;
3034
3035 /* Enable the DMA channel */
3036 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
3037 hi2c->XferSize);
3038 }
3039 else
3040 {
3041 /* Update I2C state */
3042 hi2c->State = HAL_I2C_STATE_READY;
3043 hi2c->Mode = HAL_I2C_MODE_NONE;
3044
3045 /* Update I2C error code */
3046 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3047
3048 /* Process Unlocked */
3049 __HAL_UNLOCK(hi2c);
3050
3051 return HAL_ERROR;
3052 }
3053
3054 if (dmaxferstatus == HAL_OK)
3055 {
3056 /* Send Slave Address and Memory Address */
3057 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
3058
3059 /* Process Unlocked */
3060 __HAL_UNLOCK(hi2c);
3061
3062 /* Note : The I2C interrupts must be enabled after unlocking current process
3063 to avoid the risk of I2C interrupt handle execution before current
3064 process unlock */
3065 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3066 /* possible to enable all of these */
3067 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3068 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3069 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3070 }
3071 else
3072 {
3073 /* Update I2C state */
3074 hi2c->State = HAL_I2C_STATE_READY;
3075 hi2c->Mode = HAL_I2C_MODE_NONE;
3076
3077 /* Update I2C error code */
3078 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3079
3080 /* Process Unlocked */
3081 __HAL_UNLOCK(hi2c);
3082
3083 return HAL_ERROR;
3084 }
3085
3086 return HAL_OK;
3087 }
3088 else
3089 {
3090 return HAL_BUSY;
3091 }
3092 }
3093
3094 /**
3095 * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
3096 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3097 * the configuration information for the specified I2C.
3098 * @param DevAddress Target device address: The device 7 bits address value
3099 * in datasheet must be shifted to the left before calling the interface
3100 * @param MemAddress Internal memory address
3101 * @param MemAddSize Size of internal memory address
3102 * @param pData Pointer to data buffer
3103 * @param Size Amount of data to be read
3104 * @retval HAL status
3105 */
HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)3106 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
3107 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3108 {
3109 HAL_StatusTypeDef dmaxferstatus;
3110
3111 /* Check the parameters */
3112 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3113
3114 if (hi2c->State == HAL_I2C_STATE_READY)
3115 {
3116 if ((pData == NULL) || (Size == 0U))
3117 {
3118 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3119 return HAL_ERROR;
3120 }
3121
3122 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3123 {
3124 return HAL_BUSY;
3125 }
3126
3127 /* Process Locked */
3128 __HAL_LOCK(hi2c);
3129
3130 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3131 hi2c->Mode = HAL_I2C_MODE_MEM;
3132 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3133
3134 /* Prepare transfer parameters */
3135 hi2c->pBuffPtr = pData;
3136 hi2c->XferCount = Size;
3137 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3138 hi2c->XferISR = I2C_Mem_ISR_DMA;
3139 hi2c->Devaddress = DevAddress;
3140
3141 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3142 {
3143 hi2c->XferSize = MAX_NBYTE_SIZE;
3144 }
3145 else
3146 {
3147 hi2c->XferSize = hi2c->XferCount;
3148 }
3149
3150 /* If Memory address size is 8Bit */
3151 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
3152 {
3153 /* Prefetch Memory Address */
3154 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3155
3156 /* Reset Memaddress content */
3157 hi2c->Memaddress = 0xFFFFFFFFU;
3158 }
3159 /* If Memory address size is 16Bit */
3160 else
3161 {
3162 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
3163 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
3164
3165 /* Prepare Memaddress buffer for LSB part */
3166 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
3167 }
3168
3169 if (hi2c->hdmarx != NULL)
3170 {
3171 /* Set the I2C DMA transfer complete callback */
3172 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
3173
3174 /* Set the DMA error callback */
3175 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3176
3177 /* Set the unused DMA callbacks to NULL */
3178 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3179 hi2c->hdmarx->XferAbortCallback = NULL;
3180
3181 /* Enable the DMA channel */
3182 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
3183 hi2c->XferSize);
3184 }
3185 else
3186 {
3187 /* Update I2C state */
3188 hi2c->State = HAL_I2C_STATE_READY;
3189 hi2c->Mode = HAL_I2C_MODE_NONE;
3190
3191 /* Update I2C error code */
3192 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3193
3194 /* Process Unlocked */
3195 __HAL_UNLOCK(hi2c);
3196
3197 return HAL_ERROR;
3198 }
3199
3200 if (dmaxferstatus == HAL_OK)
3201 {
3202 /* Send Slave Address and Memory Address */
3203 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
3204
3205 /* Process Unlocked */
3206 __HAL_UNLOCK(hi2c);
3207
3208 /* Note : The I2C interrupts must be enabled after unlocking current process
3209 to avoid the risk of I2C interrupt handle execution before current
3210 process unlock */
3211 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3212 /* possible to enable all of these */
3213 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3214 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3215 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3216 }
3217 else
3218 {
3219 /* Update I2C state */
3220 hi2c->State = HAL_I2C_STATE_READY;
3221 hi2c->Mode = HAL_I2C_MODE_NONE;
3222
3223 /* Update I2C error code */
3224 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3225
3226 /* Process Unlocked */
3227 __HAL_UNLOCK(hi2c);
3228
3229 return HAL_ERROR;
3230 }
3231
3232 return HAL_OK;
3233 }
3234 else
3235 {
3236 return HAL_BUSY;
3237 }
3238 }
3239
3240 /**
3241 * @brief Checks if target device is ready for communication.
3242 * @note This function is used with Memory devices
3243 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3244 * the configuration information for the specified I2C.
3245 * @param DevAddress Target device address: The device 7 bits address value
3246 * in datasheet must be shifted to the left before calling the interface
3247 * @param Trials Number of trials
3248 * @param Timeout Timeout duration
3249 * @retval HAL status
3250 */
HAL_I2C_IsDeviceReady(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Trials,uint32_t Timeout)3251 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
3252 uint32_t Timeout)
3253 {
3254 uint32_t tickstart;
3255
3256 __IO uint32_t I2C_Trials = 0UL;
3257
3258 FlagStatus tmp1;
3259 FlagStatus tmp2;
3260
3261 if (hi2c->State == HAL_I2C_STATE_READY)
3262 {
3263 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3264 {
3265 return HAL_BUSY;
3266 }
3267
3268 /* Process Locked */
3269 __HAL_LOCK(hi2c);
3270
3271 hi2c->State = HAL_I2C_STATE_BUSY;
3272 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3273
3274 do
3275 {
3276 /* Generate Start */
3277 hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
3278
3279 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
3280 /* Wait until STOPF flag is set or a NACK flag is set*/
3281 tickstart = HAL_GetTick();
3282
3283 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
3284 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3285
3286 while ((tmp1 == RESET) && (tmp2 == RESET))
3287 {
3288 if (Timeout != HAL_MAX_DELAY)
3289 {
3290 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3291 {
3292 /* Update I2C state */
3293 hi2c->State = HAL_I2C_STATE_READY;
3294
3295 /* Update I2C error code */
3296 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3297
3298 /* Process Unlocked */
3299 __HAL_UNLOCK(hi2c);
3300
3301 return HAL_ERROR;
3302 }
3303 }
3304
3305 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
3306 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3307 }
3308
3309 /* Check if the NACKF flag has not been set */
3310 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
3311 {
3312 /* Wait until STOPF flag is reset */
3313 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3314 {
3315 return HAL_ERROR;
3316 }
3317
3318 /* Clear STOP Flag */
3319 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3320
3321 /* Device is ready */
3322 hi2c->State = HAL_I2C_STATE_READY;
3323
3324 /* Process Unlocked */
3325 __HAL_UNLOCK(hi2c);
3326
3327 return HAL_OK;
3328 }
3329 else
3330 {
3331 /* Wait until STOPF flag is reset */
3332 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3333 {
3334 return HAL_ERROR;
3335 }
3336
3337 /* Clear NACK Flag */
3338 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3339
3340 /* Clear STOP Flag, auto generated with autoend*/
3341 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3342 }
3343
3344 /* Increment Trials */
3345 I2C_Trials++;
3346 } while (I2C_Trials < Trials);
3347
3348 /* Update I2C state */
3349 hi2c->State = HAL_I2C_STATE_READY;
3350
3351 /* Update I2C error code */
3352 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3353
3354 /* Process Unlocked */
3355 __HAL_UNLOCK(hi2c);
3356
3357 return HAL_ERROR;
3358 }
3359 else
3360 {
3361 return HAL_BUSY;
3362 }
3363 }
3364
3365 /**
3366 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
3367 * @note This interface allow to manage repeated start condition when a direction change during transfer
3368 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3369 * the configuration information for the specified I2C.
3370 * @param DevAddress Target device address: The device 7 bits address value
3371 * in datasheet must be shifted to the left before calling the interface
3372 * @param pData Pointer to data buffer
3373 * @param Size Amount of data to be sent
3374 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3375 * @retval HAL status
3376 */
HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3377 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3378 uint16_t Size, uint32_t XferOptions)
3379 {
3380 uint32_t xfermode;
3381 uint32_t xferrequest = I2C_GENERATE_START_WRITE;
3382 uint32_t sizetoxfer = 0U;
3383
3384 /* Check the parameters */
3385 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3386
3387 if (hi2c->State == HAL_I2C_STATE_READY)
3388 {
3389 /* Process Locked */
3390 __HAL_LOCK(hi2c);
3391
3392 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3393 hi2c->Mode = HAL_I2C_MODE_MASTER;
3394 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3395
3396 /* Prepare transfer parameters */
3397 hi2c->pBuffPtr = pData;
3398 hi2c->XferCount = Size;
3399 hi2c->XferOptions = XferOptions;
3400 hi2c->XferISR = I2C_Master_ISR_IT;
3401
3402 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3403 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3404 {
3405 hi2c->XferSize = MAX_NBYTE_SIZE;
3406 xfermode = I2C_RELOAD_MODE;
3407 }
3408 else
3409 {
3410 hi2c->XferSize = hi2c->XferCount;
3411 xfermode = hi2c->XferOptions;
3412 }
3413
3414 if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \
3415 (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
3416 {
3417 /* Preload TX register */
3418 /* Write data to TXDR */
3419 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
3420
3421 /* Increment Buffer pointer */
3422 hi2c->pBuffPtr++;
3423
3424 sizetoxfer = hi2c->XferSize;
3425 hi2c->XferCount--;
3426 hi2c->XferSize--;
3427 }
3428
3429 /* If transfer direction not change and there is no request to start another frame,
3430 do not generate Restart Condition */
3431 /* Mean Previous state is same as current state */
3432 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
3433 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3434 {
3435 xferrequest = I2C_NO_STARTSTOP;
3436 }
3437 else
3438 {
3439 /* Convert OTHER_xxx XferOptions if any */
3440 I2C_ConvertOtherXferOptions(hi2c);
3441
3442 /* Update xfermode accordingly if no reload is necessary */
3443 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3444 {
3445 xfermode = hi2c->XferOptions;
3446 }
3447 }
3448
3449 /* Send Slave Address and set NBYTES to write */
3450 if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
3451 {
3452 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
3453 }
3454 else
3455 {
3456 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3457 }
3458
3459 /* Process Unlocked */
3460 __HAL_UNLOCK(hi2c);
3461
3462 /* Note : The I2C interrupts must be enabled after unlocking current process
3463 to avoid the risk of I2C interrupt handle execution before current
3464 process unlock */
3465 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3466 /* possible to enable all of these */
3467 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3468 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3469 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3470
3471 return HAL_OK;
3472 }
3473 else
3474 {
3475 return HAL_BUSY;
3476 }
3477 }
3478
3479 /**
3480 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
3481 * @note This interface allow to manage repeated start condition when a direction change during transfer
3482 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3483 * the configuration information for the specified I2C.
3484 * @param DevAddress Target device address: The device 7 bits address value
3485 * in datasheet must be shifted to the left before calling the interface
3486 * @param pData Pointer to data buffer
3487 * @param Size Amount of data to be sent
3488 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3489 * @retval HAL status
3490 */
HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3491 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3492 uint16_t Size, uint32_t XferOptions)
3493 {
3494 uint32_t xfermode;
3495 uint32_t xferrequest = I2C_GENERATE_START_WRITE;
3496 HAL_StatusTypeDef dmaxferstatus;
3497 uint32_t sizetoxfer = 0U;
3498
3499 /* Check the parameters */
3500 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3501
3502 if (hi2c->State == HAL_I2C_STATE_READY)
3503 {
3504 /* Process Locked */
3505 __HAL_LOCK(hi2c);
3506
3507 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3508 hi2c->Mode = HAL_I2C_MODE_MASTER;
3509 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3510
3511 /* Prepare transfer parameters */
3512 hi2c->pBuffPtr = pData;
3513 hi2c->XferCount = Size;
3514 hi2c->XferOptions = XferOptions;
3515 hi2c->XferISR = I2C_Master_ISR_DMA;
3516
3517 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3518 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3519 {
3520 hi2c->XferSize = MAX_NBYTE_SIZE;
3521 xfermode = I2C_RELOAD_MODE;
3522 }
3523 else
3524 {
3525 hi2c->XferSize = hi2c->XferCount;
3526 xfermode = hi2c->XferOptions;
3527 }
3528
3529 if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \
3530 (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
3531 {
3532 /* Preload TX register */
3533 /* Write data to TXDR */
3534 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
3535
3536 /* Increment Buffer pointer */
3537 hi2c->pBuffPtr++;
3538
3539 sizetoxfer = hi2c->XferSize;
3540 hi2c->XferCount--;
3541 hi2c->XferSize--;
3542 }
3543
3544 /* If transfer direction not change and there is no request to start another frame,
3545 do not generate Restart Condition */
3546 /* Mean Previous state is same as current state */
3547 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
3548 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3549 {
3550 xferrequest = I2C_NO_STARTSTOP;
3551 }
3552 else
3553 {
3554 /* Convert OTHER_xxx XferOptions if any */
3555 I2C_ConvertOtherXferOptions(hi2c);
3556
3557 /* Update xfermode accordingly if no reload is necessary */
3558 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3559 {
3560 xfermode = hi2c->XferOptions;
3561 }
3562 }
3563
3564 if (hi2c->XferSize > 0U)
3565 {
3566 if (hi2c->hdmatx != NULL)
3567 {
3568 /* Set the I2C DMA transfer complete callback */
3569 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
3570
3571 /* Set the DMA error callback */
3572 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3573
3574 /* Set the unused DMA callbacks to NULL */
3575 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3576 hi2c->hdmatx->XferAbortCallback = NULL;
3577
3578 /* Enable the DMA channel */
3579 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr,
3580 (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
3581 }
3582 else
3583 {
3584 /* Update I2C state */
3585 hi2c->State = HAL_I2C_STATE_READY;
3586 hi2c->Mode = HAL_I2C_MODE_NONE;
3587
3588 /* Update I2C error code */
3589 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3590
3591 /* Process Unlocked */
3592 __HAL_UNLOCK(hi2c);
3593
3594 return HAL_ERROR;
3595 }
3596
3597 if (dmaxferstatus == HAL_OK)
3598 {
3599 /* Send Slave Address and set NBYTES to write */
3600 if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
3601 {
3602 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
3603 }
3604 else
3605 {
3606 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3607 }
3608
3609 /* Update XferCount value */
3610 hi2c->XferCount -= hi2c->XferSize;
3611
3612 /* Process Unlocked */
3613 __HAL_UNLOCK(hi2c);
3614
3615 /* Note : The I2C interrupts must be enabled after unlocking current process
3616 to avoid the risk of I2C interrupt handle execution before current
3617 process unlock */
3618 /* Enable ERR and NACK interrupts */
3619 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
3620
3621 /* Enable DMA Request */
3622 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
3623 }
3624 else
3625 {
3626 /* Update I2C state */
3627 hi2c->State = HAL_I2C_STATE_READY;
3628 hi2c->Mode = HAL_I2C_MODE_NONE;
3629
3630 /* Update I2C error code */
3631 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3632
3633 /* Process Unlocked */
3634 __HAL_UNLOCK(hi2c);
3635
3636 return HAL_ERROR;
3637 }
3638 }
3639 else
3640 {
3641 /* Update Transfer ISR function pointer */
3642 hi2c->XferISR = I2C_Master_ISR_IT;
3643
3644 /* Send Slave Address */
3645 /* Set NBYTES to write and generate START condition */
3646 if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
3647 {
3648 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
3649 }
3650 else
3651 {
3652 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3653 }
3654
3655 /* Process Unlocked */
3656 __HAL_UNLOCK(hi2c);
3657
3658 /* Note : The I2C interrupts must be enabled after unlocking current process
3659 to avoid the risk of I2C interrupt handle execution before current
3660 process unlock */
3661 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3662 /* possible to enable all of these */
3663 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3664 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3665 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3666 }
3667
3668 return HAL_OK;
3669 }
3670 else
3671 {
3672 return HAL_BUSY;
3673 }
3674 }
3675
3676 /**
3677 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
3678 * @note This interface allow to manage repeated start condition when a direction change during transfer
3679 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3680 * the configuration information for the specified I2C.
3681 * @param DevAddress Target device address: The device 7 bits address value
3682 * in datasheet must be shifted to the left before calling the interface
3683 * @param pData Pointer to data buffer
3684 * @param Size Amount of data to be sent
3685 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3686 * @retval HAL status
3687 */
HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3688 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3689 uint16_t Size, uint32_t XferOptions)
3690 {
3691 uint32_t xfermode;
3692 uint32_t xferrequest = I2C_GENERATE_START_READ;
3693
3694 /* Check the parameters */
3695 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3696
3697 if (hi2c->State == HAL_I2C_STATE_READY)
3698 {
3699 /* Process Locked */
3700 __HAL_LOCK(hi2c);
3701
3702 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3703 hi2c->Mode = HAL_I2C_MODE_MASTER;
3704 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3705
3706 /* Prepare transfer parameters */
3707 hi2c->pBuffPtr = pData;
3708 hi2c->XferCount = Size;
3709 hi2c->XferOptions = XferOptions;
3710 hi2c->XferISR = I2C_Master_ISR_IT;
3711
3712 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3713 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3714 {
3715 hi2c->XferSize = MAX_NBYTE_SIZE;
3716 xfermode = I2C_RELOAD_MODE;
3717 }
3718 else
3719 {
3720 hi2c->XferSize = hi2c->XferCount;
3721 xfermode = hi2c->XferOptions;
3722 }
3723
3724 /* If transfer direction not change and there is no request to start another frame,
3725 do not generate Restart Condition */
3726 /* Mean Previous state is same as current state */
3727 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
3728 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3729 {
3730 xferrequest = I2C_NO_STARTSTOP;
3731 }
3732 else
3733 {
3734 /* Convert OTHER_xxx XferOptions if any */
3735 I2C_ConvertOtherXferOptions(hi2c);
3736
3737 /* Update xfermode accordingly if no reload is necessary */
3738 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3739 {
3740 xfermode = hi2c->XferOptions;
3741 }
3742 }
3743
3744 /* Send Slave Address and set NBYTES to read */
3745 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3746
3747 /* Process Unlocked */
3748 __HAL_UNLOCK(hi2c);
3749
3750 /* Note : The I2C interrupts must be enabled after unlocking current process
3751 to avoid the risk of I2C interrupt handle execution before current
3752 process unlock */
3753 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
3754
3755 return HAL_OK;
3756 }
3757 else
3758 {
3759 return HAL_BUSY;
3760 }
3761 }
3762
3763 /**
3764 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
3765 * @note This interface allow to manage repeated start condition when a direction change during transfer
3766 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3767 * the configuration information for the specified I2C.
3768 * @param DevAddress Target device address: The device 7 bits address value
3769 * in datasheet must be shifted to the left before calling the interface
3770 * @param pData Pointer to data buffer
3771 * @param Size Amount of data to be sent
3772 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3773 * @retval HAL status
3774 */
HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3775 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3776 uint16_t Size, uint32_t XferOptions)
3777 {
3778 uint32_t xfermode;
3779 uint32_t xferrequest = I2C_GENERATE_START_READ;
3780 HAL_StatusTypeDef dmaxferstatus;
3781
3782 /* Check the parameters */
3783 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3784
3785 if (hi2c->State == HAL_I2C_STATE_READY)
3786 {
3787 /* Process Locked */
3788 __HAL_LOCK(hi2c);
3789
3790 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3791 hi2c->Mode = HAL_I2C_MODE_MASTER;
3792 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3793
3794 /* Prepare transfer parameters */
3795 hi2c->pBuffPtr = pData;
3796 hi2c->XferCount = Size;
3797 hi2c->XferOptions = XferOptions;
3798 hi2c->XferISR = I2C_Master_ISR_DMA;
3799
3800 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3801 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3802 {
3803 hi2c->XferSize = MAX_NBYTE_SIZE;
3804 xfermode = I2C_RELOAD_MODE;
3805 }
3806 else
3807 {
3808 hi2c->XferSize = hi2c->XferCount;
3809 xfermode = hi2c->XferOptions;
3810 }
3811
3812 /* If transfer direction not change and there is no request to start another frame,
3813 do not generate Restart Condition */
3814 /* Mean Previous state is same as current state */
3815 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
3816 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3817 {
3818 xferrequest = I2C_NO_STARTSTOP;
3819 }
3820 else
3821 {
3822 /* Convert OTHER_xxx XferOptions if any */
3823 I2C_ConvertOtherXferOptions(hi2c);
3824
3825 /* Update xfermode accordingly if no reload is necessary */
3826 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3827 {
3828 xfermode = hi2c->XferOptions;
3829 }
3830 }
3831
3832 if (hi2c->XferSize > 0U)
3833 {
3834 if (hi2c->hdmarx != NULL)
3835 {
3836 /* Set the I2C DMA transfer complete callback */
3837 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
3838
3839 /* Set the DMA error callback */
3840 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3841
3842 /* Set the unused DMA callbacks to NULL */
3843 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3844 hi2c->hdmarx->XferAbortCallback = NULL;
3845
3846 /* Enable the DMA channel */
3847 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
3848 hi2c->XferSize);
3849 }
3850 else
3851 {
3852 /* Update I2C state */
3853 hi2c->State = HAL_I2C_STATE_READY;
3854 hi2c->Mode = HAL_I2C_MODE_NONE;
3855
3856 /* Update I2C error code */
3857 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3858
3859 /* Process Unlocked */
3860 __HAL_UNLOCK(hi2c);
3861
3862 return HAL_ERROR;
3863 }
3864
3865 if (dmaxferstatus == HAL_OK)
3866 {
3867 /* Send Slave Address and set NBYTES to read */
3868 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3869
3870 /* Update XferCount value */
3871 hi2c->XferCount -= hi2c->XferSize;
3872
3873 /* Process Unlocked */
3874 __HAL_UNLOCK(hi2c);
3875
3876 /* Note : The I2C interrupts must be enabled after unlocking current process
3877 to avoid the risk of I2C interrupt handle execution before current
3878 process unlock */
3879 /* Enable ERR and NACK interrupts */
3880 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
3881
3882 /* Enable DMA Request */
3883 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
3884 }
3885 else
3886 {
3887 /* Update I2C state */
3888 hi2c->State = HAL_I2C_STATE_READY;
3889 hi2c->Mode = HAL_I2C_MODE_NONE;
3890
3891 /* Update I2C error code */
3892 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3893
3894 /* Process Unlocked */
3895 __HAL_UNLOCK(hi2c);
3896
3897 return HAL_ERROR;
3898 }
3899 }
3900 else
3901 {
3902 /* Update Transfer ISR function pointer */
3903 hi2c->XferISR = I2C_Master_ISR_IT;
3904
3905 /* Send Slave Address */
3906 /* Set NBYTES to read and generate START condition */
3907 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
3908 I2C_GENERATE_START_READ);
3909
3910 /* Process Unlocked */
3911 __HAL_UNLOCK(hi2c);
3912
3913 /* Note : The I2C interrupts must be enabled after unlocking current process
3914 to avoid the risk of I2C interrupt handle execution before current
3915 process unlock */
3916 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
3917 /* possible to enable all of these */
3918 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3919 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3920 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
3921 }
3922
3923 return HAL_OK;
3924 }
3925 else
3926 {
3927 return HAL_BUSY;
3928 }
3929 }
3930
3931 /**
3932 * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
3933 * @note This interface allow to manage repeated start condition when a direction change during transfer
3934 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3935 * the configuration information for the specified I2C.
3936 * @param pData Pointer to data buffer
3937 * @param Size Amount of data to be sent
3938 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3939 * @retval HAL status
3940 */
HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3941 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
3942 uint32_t XferOptions)
3943 {
3944 /* Declaration of tmp to prevent undefined behavior of volatile usage */
3945 FlagStatus tmp;
3946
3947 /* Check the parameters */
3948 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3949
3950 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
3951 {
3952 if ((pData == NULL) || (Size == 0U))
3953 {
3954 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3955 return HAL_ERROR;
3956 }
3957
3958 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
3959 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
3960
3961 /* Process Locked */
3962 __HAL_LOCK(hi2c);
3963
3964 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
3965 /* and then toggle the HAL slave RX state to TX state */
3966 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
3967 {
3968 /* Disable associated Interrupts */
3969 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
3970
3971 /* Abort DMA Xfer if any */
3972 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
3973 {
3974 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
3975
3976 if (hi2c->hdmarx != NULL)
3977 {
3978 /* Set the I2C DMA Abort callback :
3979 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
3980 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
3981
3982 /* Abort DMA RX */
3983 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
3984 {
3985 /* Call Directly XferAbortCallback function in case of error */
3986 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
3987 }
3988 }
3989 }
3990 }
3991
3992 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
3993 hi2c->Mode = HAL_I2C_MODE_SLAVE;
3994 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3995
3996 /* Enable Address Acknowledge */
3997 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
3998
3999 /* Prepare transfer parameters */
4000 hi2c->pBuffPtr = pData;
4001 hi2c->XferCount = Size;
4002 hi2c->XferSize = hi2c->XferCount;
4003 hi2c->XferOptions = XferOptions;
4004 hi2c->XferISR = I2C_Slave_ISR_IT;
4005
4006 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4007 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
4008 {
4009 /* Clear ADDR flag after prepare the transfer parameters */
4010 /* This action will generate an acknowledge to the Master */
4011 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4012 }
4013
4014 /* Process Unlocked */
4015 __HAL_UNLOCK(hi2c);
4016
4017 /* Note : The I2C interrupts must be enabled after unlocking current process
4018 to avoid the risk of I2C interrupt handle execution before current
4019 process unlock */
4020 /* REnable ADDR interrupt */
4021 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
4022
4023 return HAL_OK;
4024 }
4025 else
4026 {
4027 return HAL_ERROR;
4028 }
4029 }
4030
4031 /**
4032 * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
4033 * @note This interface allow to manage repeated start condition when a direction change during transfer
4034 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4035 * the configuration information for the specified I2C.
4036 * @param pData Pointer to data buffer
4037 * @param Size Amount of data to be sent
4038 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4039 * @retval HAL status
4040 */
HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4041 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4042 uint32_t XferOptions)
4043 {
4044 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4045 FlagStatus tmp;
4046 HAL_StatusTypeDef dmaxferstatus;
4047
4048 /* Check the parameters */
4049 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4050
4051 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4052 {
4053 if ((pData == NULL) || (Size == 0U))
4054 {
4055 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4056 return HAL_ERROR;
4057 }
4058
4059 /* Process Locked */
4060 __HAL_LOCK(hi2c);
4061
4062 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4063 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
4064
4065 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4066 /* and then toggle the HAL slave RX state to TX state */
4067 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4068 {
4069 /* Disable associated Interrupts */
4070 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
4071
4072 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4073 {
4074 /* Abort DMA Xfer if any */
4075 if (hi2c->hdmarx != NULL)
4076 {
4077 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4078
4079 /* Set the I2C DMA Abort callback :
4080 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4081 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4082
4083 /* Abort DMA RX */
4084 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4085 {
4086 /* Call Directly XferAbortCallback function in case of error */
4087 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4088 }
4089 }
4090 }
4091 }
4092 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4093 {
4094 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4095 {
4096 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4097
4098 /* Abort DMA Xfer if any */
4099 if (hi2c->hdmatx != NULL)
4100 {
4101 /* Set the I2C DMA Abort callback :
4102 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4103 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4104
4105 /* Abort DMA TX */
4106 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4107 {
4108 /* Call Directly XferAbortCallback function in case of error */
4109 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4110 }
4111 }
4112 }
4113 }
4114 else
4115 {
4116 /* Nothing to do */
4117 }
4118
4119 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4120 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4121 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4122
4123 /* Enable Address Acknowledge */
4124 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4125
4126 /* Prepare transfer parameters */
4127 hi2c->pBuffPtr = pData;
4128 hi2c->XferCount = Size;
4129 hi2c->XferSize = hi2c->XferCount;
4130 hi2c->XferOptions = XferOptions;
4131 hi2c->XferISR = I2C_Slave_ISR_DMA;
4132
4133 if (hi2c->hdmatx != NULL)
4134 {
4135 /* Set the I2C DMA transfer complete callback */
4136 hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
4137
4138 /* Set the DMA error callback */
4139 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
4140
4141 /* Set the unused DMA callbacks to NULL */
4142 hi2c->hdmatx->XferHalfCpltCallback = NULL;
4143 hi2c->hdmatx->XferAbortCallback = NULL;
4144
4145 /* Enable the DMA channel */
4146 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
4147 hi2c->XferSize);
4148 }
4149 else
4150 {
4151 /* Update I2C state */
4152 hi2c->State = HAL_I2C_STATE_LISTEN;
4153 hi2c->Mode = HAL_I2C_MODE_NONE;
4154
4155 /* Update I2C error code */
4156 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4157
4158 /* Process Unlocked */
4159 __HAL_UNLOCK(hi2c);
4160
4161 return HAL_ERROR;
4162 }
4163
4164 if (dmaxferstatus == HAL_OK)
4165 {
4166 /* Update XferCount value */
4167 hi2c->XferCount -= hi2c->XferSize;
4168
4169 /* Reset XferSize */
4170 hi2c->XferSize = 0;
4171 }
4172 else
4173 {
4174 /* Update I2C state */
4175 hi2c->State = HAL_I2C_STATE_LISTEN;
4176 hi2c->Mode = HAL_I2C_MODE_NONE;
4177
4178 /* Update I2C error code */
4179 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4180
4181 /* Process Unlocked */
4182 __HAL_UNLOCK(hi2c);
4183
4184 return HAL_ERROR;
4185 }
4186
4187 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4188 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
4189 {
4190 /* Clear ADDR flag after prepare the transfer parameters */
4191 /* This action will generate an acknowledge to the Master */
4192 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4193 }
4194
4195 /* Process Unlocked */
4196 __HAL_UNLOCK(hi2c);
4197
4198 /* Enable DMA Request */
4199 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
4200
4201 /* Note : The I2C interrupts must be enabled after unlocking current process
4202 to avoid the risk of I2C interrupt handle execution before current
4203 process unlock */
4204 /* Enable ERR, STOP, NACK, ADDR interrupts */
4205 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4206
4207 return HAL_OK;
4208 }
4209 else
4210 {
4211 return HAL_ERROR;
4212 }
4213 }
4214
4215 /**
4216 * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
4217 * @note This interface allow to manage repeated start condition when a direction change during transfer
4218 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4219 * the configuration information for the specified I2C.
4220 * @param pData Pointer to data buffer
4221 * @param Size Amount of data to be sent
4222 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4223 * @retval HAL status
4224 */
HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4225 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4226 uint32_t XferOptions)
4227 {
4228 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4229 FlagStatus tmp;
4230
4231 /* Check the parameters */
4232 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4233
4234 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4235 {
4236 if ((pData == NULL) || (Size == 0U))
4237 {
4238 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4239 return HAL_ERROR;
4240 }
4241
4242 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4243 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
4244
4245 /* Process Locked */
4246 __HAL_LOCK(hi2c);
4247
4248 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4249 /* and then toggle the HAL slave TX state to RX state */
4250 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4251 {
4252 /* Disable associated Interrupts */
4253 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4254
4255 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4256 {
4257 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4258
4259 /* Abort DMA Xfer if any */
4260 if (hi2c->hdmatx != NULL)
4261 {
4262 /* Set the I2C DMA Abort callback :
4263 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4264 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4265
4266 /* Abort DMA TX */
4267 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4268 {
4269 /* Call Directly XferAbortCallback function in case of error */
4270 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4271 }
4272 }
4273 }
4274 }
4275
4276 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4277 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4278 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4279
4280 /* Enable Address Acknowledge */
4281 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4282
4283 /* Prepare transfer parameters */
4284 hi2c->pBuffPtr = pData;
4285 hi2c->XferCount = Size;
4286 hi2c->XferSize = hi2c->XferCount;
4287 hi2c->XferOptions = XferOptions;
4288 hi2c->XferISR = I2C_Slave_ISR_IT;
4289
4290 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4291 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
4292 {
4293 /* Clear ADDR flag after prepare the transfer parameters */
4294 /* This action will generate an acknowledge to the Master */
4295 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4296 }
4297
4298 /* Process Unlocked */
4299 __HAL_UNLOCK(hi2c);
4300
4301 /* Note : The I2C interrupts must be enabled after unlocking current process
4302 to avoid the risk of I2C interrupt handle execution before current
4303 process unlock */
4304 /* REnable ADDR interrupt */
4305 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
4306
4307 return HAL_OK;
4308 }
4309 else
4310 {
4311 return HAL_ERROR;
4312 }
4313 }
4314
4315 /**
4316 * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
4317 * @note This interface allow to manage repeated start condition when a direction change during transfer
4318 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4319 * the configuration information for the specified I2C.
4320 * @param pData Pointer to data buffer
4321 * @param Size Amount of data to be sent
4322 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4323 * @retval HAL status
4324 */
HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4325 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4326 uint32_t XferOptions)
4327 {
4328 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4329 FlagStatus tmp;
4330 HAL_StatusTypeDef dmaxferstatus;
4331
4332 /* Check the parameters */
4333 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4334
4335 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4336 {
4337 if ((pData == NULL) || (Size == 0U))
4338 {
4339 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4340 return HAL_ERROR;
4341 }
4342
4343 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4344 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
4345
4346 /* Process Locked */
4347 __HAL_LOCK(hi2c);
4348
4349 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4350 /* and then toggle the HAL slave TX state to RX state */
4351 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4352 {
4353 /* Disable associated Interrupts */
4354 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4355
4356 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4357 {
4358 /* Abort DMA Xfer if any */
4359 if (hi2c->hdmatx != NULL)
4360 {
4361 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4362
4363 /* Set the I2C DMA Abort callback :
4364 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4365 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4366
4367 /* Abort DMA TX */
4368 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4369 {
4370 /* Call Directly XferAbortCallback function in case of error */
4371 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4372 }
4373 }
4374 }
4375 }
4376 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4377 {
4378 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4379 {
4380 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4381
4382 /* Abort DMA Xfer if any */
4383 if (hi2c->hdmarx != NULL)
4384 {
4385 /* Set the I2C DMA Abort callback :
4386 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4387 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4388
4389 /* Abort DMA RX */
4390 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4391 {
4392 /* Call Directly XferAbortCallback function in case of error */
4393 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4394 }
4395 }
4396 }
4397 }
4398 else
4399 {
4400 /* Nothing to do */
4401 }
4402
4403 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4404 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4405 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4406
4407 /* Enable Address Acknowledge */
4408 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4409
4410 /* Prepare transfer parameters */
4411 hi2c->pBuffPtr = pData;
4412 hi2c->XferCount = Size;
4413 hi2c->XferSize = hi2c->XferCount;
4414 hi2c->XferOptions = XferOptions;
4415 hi2c->XferISR = I2C_Slave_ISR_DMA;
4416
4417 if (hi2c->hdmarx != NULL)
4418 {
4419 /* Set the I2C DMA transfer complete callback */
4420 hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
4421
4422 /* Set the DMA error callback */
4423 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4424
4425 /* Set the unused DMA callbacks to NULL */
4426 hi2c->hdmarx->XferHalfCpltCallback = NULL;
4427 hi2c->hdmarx->XferAbortCallback = NULL;
4428
4429 /* Enable the DMA channel */
4430 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR,
4431 (uint32_t)pData, hi2c->XferSize);
4432 }
4433 else
4434 {
4435 /* Update I2C state */
4436 hi2c->State = HAL_I2C_STATE_LISTEN;
4437 hi2c->Mode = HAL_I2C_MODE_NONE;
4438
4439 /* Update I2C error code */
4440 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4441
4442 /* Process Unlocked */
4443 __HAL_UNLOCK(hi2c);
4444
4445 return HAL_ERROR;
4446 }
4447
4448 if (dmaxferstatus == HAL_OK)
4449 {
4450 /* Update XferCount value */
4451 hi2c->XferCount -= hi2c->XferSize;
4452
4453 /* Reset XferSize */
4454 hi2c->XferSize = 0;
4455 }
4456 else
4457 {
4458 /* Update I2C state */
4459 hi2c->State = HAL_I2C_STATE_LISTEN;
4460 hi2c->Mode = HAL_I2C_MODE_NONE;
4461
4462 /* Update I2C error code */
4463 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4464
4465 /* Process Unlocked */
4466 __HAL_UNLOCK(hi2c);
4467
4468 return HAL_ERROR;
4469 }
4470
4471 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4472 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
4473 {
4474 /* Clear ADDR flag after prepare the transfer parameters */
4475 /* This action will generate an acknowledge to the Master */
4476 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4477 }
4478
4479 /* Process Unlocked */
4480 __HAL_UNLOCK(hi2c);
4481
4482 /* Enable DMA Request */
4483 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
4484
4485 /* Note : The I2C interrupts must be enabled after unlocking current process
4486 to avoid the risk of I2C interrupt handle execution before current
4487 process unlock */
4488 /* REnable ADDR interrupt */
4489 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
4490
4491 return HAL_OK;
4492 }
4493 else
4494 {
4495 return HAL_ERROR;
4496 }
4497 }
4498
4499 /**
4500 * @brief Enable the Address listen mode with Interrupt.
4501 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4502 * the configuration information for the specified I2C.
4503 * @retval HAL status
4504 */
HAL_I2C_EnableListen_IT(I2C_HandleTypeDef * hi2c)4505 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
4506 {
4507 if (hi2c->State == HAL_I2C_STATE_READY)
4508 {
4509 hi2c->State = HAL_I2C_STATE_LISTEN;
4510 hi2c->XferISR = I2C_Slave_ISR_IT;
4511
4512 /* Enable the Address Match interrupt */
4513 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4514
4515 return HAL_OK;
4516 }
4517 else
4518 {
4519 return HAL_BUSY;
4520 }
4521 }
4522
4523 /**
4524 * @brief Disable the Address listen mode with Interrupt.
4525 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4526 * the configuration information for the specified I2C
4527 * @retval HAL status
4528 */
HAL_I2C_DisableListen_IT(I2C_HandleTypeDef * hi2c)4529 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
4530 {
4531 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4532 uint32_t tmp;
4533
4534 /* Disable Address listen mode only if a transfer is not ongoing */
4535 if (hi2c->State == HAL_I2C_STATE_LISTEN)
4536 {
4537 tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
4538 hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
4539 hi2c->State = HAL_I2C_STATE_READY;
4540 hi2c->Mode = HAL_I2C_MODE_NONE;
4541 hi2c->XferISR = NULL;
4542
4543 /* Disable the Address Match interrupt */
4544 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4545
4546 return HAL_OK;
4547 }
4548 else
4549 {
4550 return HAL_BUSY;
4551 }
4552 }
4553
4554 /**
4555 * @brief Abort a master I2C IT or DMA process communication with Interrupt.
4556 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4557 * the configuration information for the specified I2C.
4558 * @param DevAddress Target device address: The device 7 bits address value
4559 * in datasheet must be shifted to the left before calling the interface
4560 * @retval HAL status
4561 */
HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress)4562 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
4563 {
4564 if (hi2c->Mode == HAL_I2C_MODE_MASTER)
4565 {
4566 /* Process Locked */
4567 __HAL_LOCK(hi2c);
4568
4569 /* Disable Interrupts and Store Previous state */
4570 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
4571 {
4572 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4573 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
4574 }
4575 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
4576 {
4577 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
4578 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
4579 }
4580 else
4581 {
4582 /* Do nothing */
4583 }
4584
4585 /* Set State at HAL_I2C_STATE_ABORT */
4586 hi2c->State = HAL_I2C_STATE_ABORT;
4587
4588 /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
4589 /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
4590 I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
4591
4592 /* Process Unlocked */
4593 __HAL_UNLOCK(hi2c);
4594
4595 /* Note : The I2C interrupts must be enabled after unlocking current process
4596 to avoid the risk of I2C interrupt handle execution before current
4597 process unlock */
4598 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
4599
4600 return HAL_OK;
4601 }
4602 else
4603 {
4604 /* Wrong usage of abort function */
4605 /* This function should be used only in case of abort monitored by master device */
4606 return HAL_ERROR;
4607 }
4608 }
4609
4610 /**
4611 * @}
4612 */
4613
4614 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
4615 * @{
4616 */
4617
4618 /**
4619 * @brief This function handles I2C event interrupt request.
4620 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4621 * the configuration information for the specified I2C.
4622 * @retval None
4623 */
HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef * hi2c)4624 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */
4625 {
4626 /* Get current IT Flags and IT sources value */
4627 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
4628 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
4629
4630 /* I2C events treatment -------------------------------------*/
4631 if (hi2c->XferISR != NULL)
4632 {
4633 hi2c->XferISR(hi2c, itflags, itsources);
4634 }
4635 }
4636
4637 /**
4638 * @brief This function handles I2C error interrupt request.
4639 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4640 * the configuration information for the specified I2C.
4641 * @retval None
4642 */
HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef * hi2c)4643 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
4644 {
4645 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
4646 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
4647 uint32_t tmperror;
4648
4649 /* I2C Bus error interrupt occurred ------------------------------------*/
4650 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
4651 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4652 {
4653 hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
4654
4655 /* Clear BERR flag */
4656 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
4657 }
4658
4659 /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
4660 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
4661 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4662 {
4663 hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
4664
4665 /* Clear OVR flag */
4666 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
4667 }
4668
4669 /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
4670 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
4671 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4672 {
4673 hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
4674
4675 /* Clear ARLO flag */
4676 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
4677 }
4678
4679 /* Store current volatile hi2c->ErrorCode, misra rule */
4680 tmperror = hi2c->ErrorCode;
4681
4682 /* Call the Error Callback in case of Error detected */
4683 if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
4684 {
4685 I2C_ITError(hi2c, tmperror);
4686 }
4687 }
4688
4689 /**
4690 * @brief Master Tx Transfer completed callback.
4691 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4692 * the configuration information for the specified I2C.
4693 * @retval None
4694 */
HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef * hi2c)4695 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
4696 {
4697 /* Prevent unused argument(s) compilation warning */
4698 UNUSED(hi2c);
4699
4700 /* NOTE : This function should not be modified, when the callback is needed,
4701 the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
4702 */
4703 }
4704
4705 /**
4706 * @brief Master Rx Transfer completed callback.
4707 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4708 * the configuration information for the specified I2C.
4709 * @retval None
4710 */
HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef * hi2c)4711 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
4712 {
4713 /* Prevent unused argument(s) compilation warning */
4714 UNUSED(hi2c);
4715
4716 /* NOTE : This function should not be modified, when the callback is needed,
4717 the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
4718 */
4719 }
4720
4721 /** @brief Slave Tx Transfer completed callback.
4722 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4723 * the configuration information for the specified I2C.
4724 * @retval None
4725 */
HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef * hi2c)4726 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
4727 {
4728 /* Prevent unused argument(s) compilation warning */
4729 UNUSED(hi2c);
4730
4731 /* NOTE : This function should not be modified, when the callback is needed,
4732 the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
4733 */
4734 }
4735
4736 /**
4737 * @brief Slave Rx Transfer completed callback.
4738 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4739 * the configuration information for the specified I2C.
4740 * @retval None
4741 */
HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef * hi2c)4742 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
4743 {
4744 /* Prevent unused argument(s) compilation warning */
4745 UNUSED(hi2c);
4746
4747 /* NOTE : This function should not be modified, when the callback is needed,
4748 the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
4749 */
4750 }
4751
4752 /**
4753 * @brief Slave Address Match callback.
4754 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4755 * the configuration information for the specified I2C.
4756 * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
4757 * @param AddrMatchCode Address Match Code
4758 * @retval None
4759 */
HAL_I2C_AddrCallback(I2C_HandleTypeDef * hi2c,uint8_t TransferDirection,uint16_t AddrMatchCode)4760 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
4761 {
4762 /* Prevent unused argument(s) compilation warning */
4763 UNUSED(hi2c);
4764 UNUSED(TransferDirection);
4765 UNUSED(AddrMatchCode);
4766
4767 /* NOTE : This function should not be modified, when the callback is needed,
4768 the HAL_I2C_AddrCallback() could be implemented in the user file
4769 */
4770 }
4771
4772 /**
4773 * @brief Listen Complete callback.
4774 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4775 * the configuration information for the specified I2C.
4776 * @retval None
4777 */
HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef * hi2c)4778 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
4779 {
4780 /* Prevent unused argument(s) compilation warning */
4781 UNUSED(hi2c);
4782
4783 /* NOTE : This function should not be modified, when the callback is needed,
4784 the HAL_I2C_ListenCpltCallback() could be implemented in the user file
4785 */
4786 }
4787
4788 /**
4789 * @brief Memory Tx Transfer completed callback.
4790 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4791 * the configuration information for the specified I2C.
4792 * @retval None
4793 */
HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef * hi2c)4794 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
4795 {
4796 /* Prevent unused argument(s) compilation warning */
4797 UNUSED(hi2c);
4798
4799 /* NOTE : This function should not be modified, when the callback is needed,
4800 the HAL_I2C_MemTxCpltCallback could be implemented in the user file
4801 */
4802 }
4803
4804 /**
4805 * @brief Memory Rx Transfer completed callback.
4806 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4807 * the configuration information for the specified I2C.
4808 * @retval None
4809 */
HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef * hi2c)4810 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
4811 {
4812 /* Prevent unused argument(s) compilation warning */
4813 UNUSED(hi2c);
4814
4815 /* NOTE : This function should not be modified, when the callback is needed,
4816 the HAL_I2C_MemRxCpltCallback could be implemented in the user file
4817 */
4818 }
4819
4820 /**
4821 * @brief I2C error callback.
4822 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4823 * the configuration information for the specified I2C.
4824 * @retval None
4825 */
HAL_I2C_ErrorCallback(I2C_HandleTypeDef * hi2c)4826 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
4827 {
4828 /* Prevent unused argument(s) compilation warning */
4829 UNUSED(hi2c);
4830
4831 /* NOTE : This function should not be modified, when the callback is needed,
4832 the HAL_I2C_ErrorCallback could be implemented in the user file
4833 */
4834 }
4835
4836 /**
4837 * @brief I2C abort callback.
4838 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4839 * the configuration information for the specified I2C.
4840 * @retval None
4841 */
HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef * hi2c)4842 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
4843 {
4844 /* Prevent unused argument(s) compilation warning */
4845 UNUSED(hi2c);
4846
4847 /* NOTE : This function should not be modified, when the callback is needed,
4848 the HAL_I2C_AbortCpltCallback could be implemented in the user file
4849 */
4850 }
4851
4852 /**
4853 * @}
4854 */
4855
4856 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
4857 * @brief Peripheral State, Mode and Error functions
4858 *
4859 @verbatim
4860 ===============================================================================
4861 ##### Peripheral State, Mode and Error functions #####
4862 ===============================================================================
4863 [..]
4864 This subsection permit to get in run-time the status of the peripheral
4865 and the data flow.
4866
4867 @endverbatim
4868 * @{
4869 */
4870
4871 /**
4872 * @brief Return the I2C handle state.
4873 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4874 * the configuration information for the specified I2C.
4875 * @retval HAL state
4876 */
HAL_I2C_GetState(const I2C_HandleTypeDef * hi2c)4877 HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c)
4878 {
4879 /* Return I2C handle state */
4880 return hi2c->State;
4881 }
4882
4883 /**
4884 * @brief Returns the I2C Master, Slave, Memory or no mode.
4885 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4886 * the configuration information for I2C module
4887 * @retval HAL mode
4888 */
HAL_I2C_GetMode(const I2C_HandleTypeDef * hi2c)4889 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c)
4890 {
4891 return hi2c->Mode;
4892 }
4893
4894 /**
4895 * @brief Return the I2C error code.
4896 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4897 * the configuration information for the specified I2C.
4898 * @retval I2C Error Code
4899 */
HAL_I2C_GetError(const I2C_HandleTypeDef * hi2c)4900 uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c)
4901 {
4902 return hi2c->ErrorCode;
4903 }
4904
4905 /**
4906 * @}
4907 */
4908
4909 /**
4910 * @}
4911 */
4912
4913 /** @addtogroup I2C_Private_Functions
4914 * @{
4915 */
4916
4917 /**
4918 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
4919 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4920 * the configuration information for the specified I2C.
4921 * @param ITFlags Interrupt flags to handle.
4922 * @param ITSources Interrupt sources enabled.
4923 * @retval HAL status
4924 */
I2C_Master_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)4925 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
4926 uint32_t ITSources)
4927 {
4928 uint16_t devaddress;
4929 uint32_t tmpITFlags = ITFlags;
4930
4931 /* Process Locked */
4932 __HAL_LOCK(hi2c);
4933
4934 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
4935 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
4936 {
4937 /* Clear NACK Flag */
4938 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4939
4940 /* Set corresponding Error Code */
4941 /* No need to generate STOP, it is automatically done */
4942 /* Error callback will be send during stop flag treatment */
4943 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
4944
4945 /* Flush TX register */
4946 I2C_Flush_TXDR(hi2c);
4947 }
4948 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
4949 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
4950 {
4951 /* Remove RXNE flag on temporary variable as read done */
4952 tmpITFlags &= ~I2C_FLAG_RXNE;
4953
4954 /* Read data from RXDR */
4955 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
4956
4957 /* Increment Buffer pointer */
4958 hi2c->pBuffPtr++;
4959
4960 hi2c->XferSize--;
4961 hi2c->XferCount--;
4962 }
4963 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) == RESET) && \
4964 ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
4965 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)))
4966 {
4967 /* Write data to TXDR */
4968 if (hi2c->XferCount != 0U)
4969 {
4970 /* Write data to TXDR */
4971 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
4972
4973 /* Increment Buffer pointer */
4974 hi2c->pBuffPtr++;
4975
4976 hi2c->XferSize--;
4977 hi2c->XferCount--;
4978 }
4979 }
4980 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
4981 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
4982 {
4983 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
4984 {
4985 devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
4986
4987 if (hi2c->XferCount > MAX_NBYTE_SIZE)
4988 {
4989 hi2c->XferSize = MAX_NBYTE_SIZE;
4990 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
4991 }
4992 else
4993 {
4994 hi2c->XferSize = hi2c->XferCount;
4995 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
4996 {
4997 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
4998 hi2c->XferOptions, I2C_NO_STARTSTOP);
4999 }
5000 else
5001 {
5002 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
5003 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5004 }
5005 }
5006 }
5007 else
5008 {
5009 /* Call TxCpltCallback() if no stop mode is set */
5010 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5011 {
5012 /* Call I2C Master Sequential complete process */
5013 I2C_ITMasterSeqCplt(hi2c);
5014 }
5015 else
5016 {
5017 /* Wrong size Status regarding TCR flag event */
5018 /* Call the corresponding callback to inform upper layer of End of Transfer */
5019 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5020 }
5021 }
5022 }
5023 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
5024 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5025 {
5026 if (hi2c->XferCount == 0U)
5027 {
5028 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5029 {
5030 /* Generate a stop condition in case of no transfer option */
5031 if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
5032 {
5033 /* Generate Stop */
5034 hi2c->Instance->CR2 |= I2C_CR2_STOP;
5035 }
5036 else
5037 {
5038 /* Call I2C Master Sequential complete process */
5039 I2C_ITMasterSeqCplt(hi2c);
5040 }
5041 }
5042 }
5043 else
5044 {
5045 /* Wrong size Status regarding TC flag event */
5046 /* Call the corresponding callback to inform upper layer of End of Transfer */
5047 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5048 }
5049 }
5050 else
5051 {
5052 /* Nothing to do */
5053 }
5054
5055 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5056 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5057 {
5058 /* Call I2C Master complete process */
5059 I2C_ITMasterCplt(hi2c, tmpITFlags);
5060 }
5061
5062 /* Process Unlocked */
5063 __HAL_UNLOCK(hi2c);
5064
5065 return HAL_OK;
5066 }
5067
5068 /**
5069 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.
5070 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5071 * the configuration information for the specified I2C.
5072 * @param ITFlags Interrupt flags to handle.
5073 * @param ITSources Interrupt sources enabled.
5074 * @retval HAL status
5075 */
I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5076 static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5077 uint32_t ITSources)
5078 {
5079 uint32_t direction = I2C_GENERATE_START_WRITE;
5080 uint32_t tmpITFlags = ITFlags;
5081
5082 /* Process Locked */
5083 __HAL_LOCK(hi2c);
5084
5085 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
5086 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5087 {
5088 /* Clear NACK Flag */
5089 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5090
5091 /* Set corresponding Error Code */
5092 /* No need to generate STOP, it is automatically done */
5093 /* Error callback will be send during stop flag treatment */
5094 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5095
5096 /* Flush TX register */
5097 I2C_Flush_TXDR(hi2c);
5098 }
5099 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
5100 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
5101 {
5102 /* Remove RXNE flag on temporary variable as read done */
5103 tmpITFlags &= ~I2C_FLAG_RXNE;
5104
5105 /* Read data from RXDR */
5106 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
5107
5108 /* Increment Buffer pointer */
5109 hi2c->pBuffPtr++;
5110
5111 hi2c->XferSize--;
5112 hi2c->XferCount--;
5113 }
5114 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
5115 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5116 {
5117 if (hi2c->Memaddress == 0xFFFFFFFFU)
5118 {
5119 /* Write data to TXDR */
5120 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
5121
5122 /* Increment Buffer pointer */
5123 hi2c->pBuffPtr++;
5124
5125 hi2c->XferSize--;
5126 hi2c->XferCount--;
5127 }
5128 else
5129 {
5130 /* Write LSB part of Memory Address */
5131 hi2c->Instance->TXDR = hi2c->Memaddress;
5132
5133 /* Reset Memaddress content */
5134 hi2c->Memaddress = 0xFFFFFFFFU;
5135 }
5136 }
5137 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
5138 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5139 {
5140 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
5141 {
5142 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5143 {
5144 hi2c->XferSize = MAX_NBYTE_SIZE;
5145 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5146 I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5147 }
5148 else
5149 {
5150 hi2c->XferSize = hi2c->XferCount;
5151 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5152 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5153 }
5154 }
5155 else
5156 {
5157 /* Wrong size Status regarding TCR flag event */
5158 /* Call the corresponding callback to inform upper layer of End of Transfer */
5159 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5160 }
5161 }
5162 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
5163 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5164 {
5165 /* Disable Interrupt related to address step */
5166 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5167
5168 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
5169 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
5170
5171 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5172 {
5173 direction = I2C_GENERATE_START_READ;
5174 }
5175
5176 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5177 {
5178 hi2c->XferSize = MAX_NBYTE_SIZE;
5179
5180 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
5181 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5182 I2C_RELOAD_MODE, direction);
5183 }
5184 else
5185 {
5186 hi2c->XferSize = hi2c->XferCount;
5187
5188 /* Set NBYTES to write and generate RESTART */
5189 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5190 I2C_AUTOEND_MODE, direction);
5191 }
5192 }
5193 else
5194 {
5195 /* Nothing to do */
5196 }
5197
5198 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5199 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5200 {
5201 /* Call I2C Master complete process */
5202 I2C_ITMasterCplt(hi2c, tmpITFlags);
5203 }
5204
5205 /* Process Unlocked */
5206 __HAL_UNLOCK(hi2c);
5207
5208 return HAL_OK;
5209 }
5210
5211 /**
5212 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
5213 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5214 * the configuration information for the specified I2C.
5215 * @param ITFlags Interrupt flags to handle.
5216 * @param ITSources Interrupt sources enabled.
5217 * @retval HAL status
5218 */
I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5219 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5220 uint32_t ITSources)
5221 {
5222 uint32_t tmpoptions = hi2c->XferOptions;
5223 uint32_t tmpITFlags = ITFlags;
5224
5225 /* Process locked */
5226 __HAL_LOCK(hi2c);
5227
5228 /* Check if STOPF is set */
5229 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5230 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5231 {
5232 /* Call I2C Slave complete process */
5233 I2C_ITSlaveCplt(hi2c, tmpITFlags);
5234 }
5235 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
5236 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5237 {
5238 /* Check that I2C transfer finished */
5239 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
5240 /* Mean XferCount == 0*/
5241 /* So clear Flag NACKF only */
5242 if (hi2c->XferCount == 0U)
5243 {
5244 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
5245 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
5246 Warning[Pa134]: left and right operands are identical */
5247 {
5248 /* Call I2C Listen complete process */
5249 I2C_ITListenCplt(hi2c, tmpITFlags);
5250 }
5251 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
5252 {
5253 /* Clear NACK Flag */
5254 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5255
5256 /* Flush TX register */
5257 I2C_Flush_TXDR(hi2c);
5258
5259 /* Last Byte is Transmitted */
5260 /* Call I2C Slave Sequential complete process */
5261 I2C_ITSlaveSeqCplt(hi2c);
5262 }
5263 else
5264 {
5265 /* Clear NACK Flag */
5266 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5267 }
5268 }
5269 else
5270 {
5271 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
5272 /* Clear NACK Flag */
5273 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5274
5275 /* Set ErrorCode corresponding to a Non-Acknowledge */
5276 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5277
5278 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
5279 {
5280 /* Call the corresponding callback to inform upper layer of End of Transfer */
5281 I2C_ITError(hi2c, hi2c->ErrorCode);
5282 }
5283 }
5284 }
5285 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
5286 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
5287 {
5288 if (hi2c->XferCount > 0U)
5289 {
5290 /* Read data from RXDR */
5291 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
5292
5293 /* Increment Buffer pointer */
5294 hi2c->pBuffPtr++;
5295
5296 hi2c->XferSize--;
5297 hi2c->XferCount--;
5298 }
5299
5300 if ((hi2c->XferCount == 0U) && \
5301 (tmpoptions != I2C_NO_OPTION_FRAME))
5302 {
5303 /* Call I2C Slave Sequential complete process */
5304 I2C_ITSlaveSeqCplt(hi2c);
5305 }
5306 }
5307 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
5308 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
5309 {
5310 I2C_ITAddrCplt(hi2c, tmpITFlags);
5311 }
5312 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
5313 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5314 {
5315 /* Write data to TXDR only if XferCount not reach "0" */
5316 /* A TXIS flag can be set, during STOP treatment */
5317 /* Check if all Data have already been sent */
5318 /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
5319 if (hi2c->XferCount > 0U)
5320 {
5321 /* Write data to TXDR */
5322 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
5323
5324 /* Increment Buffer pointer */
5325 hi2c->pBuffPtr++;
5326
5327 hi2c->XferCount--;
5328 hi2c->XferSize--;
5329 }
5330 else
5331 {
5332 if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
5333 {
5334 /* Last Byte is Transmitted */
5335 /* Call I2C Slave Sequential complete process */
5336 I2C_ITSlaveSeqCplt(hi2c);
5337 }
5338 }
5339 }
5340 else
5341 {
5342 /* Nothing to do */
5343 }
5344
5345 /* Process Unlocked */
5346 __HAL_UNLOCK(hi2c);
5347
5348 return HAL_OK;
5349 }
5350
5351 /**
5352 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
5353 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5354 * the configuration information for the specified I2C.
5355 * @param ITFlags Interrupt flags to handle.
5356 * @param ITSources Interrupt sources enabled.
5357 * @retval HAL status
5358 */
I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5359 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5360 uint32_t ITSources)
5361 {
5362 uint16_t devaddress;
5363 uint32_t xfermode;
5364
5365 /* Process Locked */
5366 __HAL_LOCK(hi2c);
5367
5368 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5369 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5370 {
5371 /* Clear NACK Flag */
5372 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5373
5374 /* Set corresponding Error Code */
5375 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5376
5377 /* No need to generate STOP, it is automatically done */
5378 /* But enable STOP interrupt, to treat it */
5379 /* Error callback will be send during stop flag treatment */
5380 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
5381
5382 /* Flush TX register */
5383 I2C_Flush_TXDR(hi2c);
5384 }
5385 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
5386 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5387 {
5388 /* Disable TC interrupt */
5389 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
5390
5391 if (hi2c->XferCount != 0U)
5392 {
5393 /* Recover Slave address */
5394 devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
5395
5396 /* Prepare the new XferSize to transfer */
5397 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5398 {
5399 hi2c->XferSize = MAX_NBYTE_SIZE;
5400 xfermode = I2C_RELOAD_MODE;
5401 }
5402 else
5403 {
5404 hi2c->XferSize = hi2c->XferCount;
5405 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
5406 {
5407 xfermode = hi2c->XferOptions;
5408 }
5409 else
5410 {
5411 xfermode = I2C_AUTOEND_MODE;
5412 }
5413 }
5414
5415 /* Set the new XferSize in Nbytes register */
5416 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
5417
5418 /* Update XferCount value */
5419 hi2c->XferCount -= hi2c->XferSize;
5420
5421 /* Enable DMA Request */
5422 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5423 {
5424 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5425 }
5426 else
5427 {
5428 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5429 }
5430 }
5431 else
5432 {
5433 /* Call TxCpltCallback() if no stop mode is set */
5434 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5435 {
5436 /* Call I2C Master Sequential complete process */
5437 I2C_ITMasterSeqCplt(hi2c);
5438 }
5439 else
5440 {
5441 /* Wrong size Status regarding TCR flag event */
5442 /* Call the corresponding callback to inform upper layer of End of Transfer */
5443 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5444 }
5445 }
5446 }
5447 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
5448 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5449 {
5450 if (hi2c->XferCount == 0U)
5451 {
5452 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5453 {
5454 /* Generate a stop condition in case of no transfer option */
5455 if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
5456 {
5457 /* Generate Stop */
5458 hi2c->Instance->CR2 |= I2C_CR2_STOP;
5459 }
5460 else
5461 {
5462 /* Call I2C Master Sequential complete process */
5463 I2C_ITMasterSeqCplt(hi2c);
5464 }
5465 }
5466 }
5467 else
5468 {
5469 /* Wrong size Status regarding TC flag event */
5470 /* Call the corresponding callback to inform upper layer of End of Transfer */
5471 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5472 }
5473 }
5474 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5475 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5476 {
5477 /* Call I2C Master complete process */
5478 I2C_ITMasterCplt(hi2c, ITFlags);
5479 }
5480 else
5481 {
5482 /* Nothing to do */
5483 }
5484
5485 /* Process Unlocked */
5486 __HAL_UNLOCK(hi2c);
5487
5488 return HAL_OK;
5489 }
5490
5491 /**
5492 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.
5493 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5494 * the configuration information for the specified I2C.
5495 * @param ITFlags Interrupt flags to handle.
5496 * @param ITSources Interrupt sources enabled.
5497 * @retval HAL status
5498 */
I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5499 static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5500 uint32_t ITSources)
5501 {
5502 uint32_t direction = I2C_GENERATE_START_WRITE;
5503
5504 /* Process Locked */
5505 __HAL_LOCK(hi2c);
5506
5507 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5508 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5509 {
5510 /* Clear NACK Flag */
5511 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5512
5513 /* Set corresponding Error Code */
5514 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5515
5516 /* No need to generate STOP, it is automatically done */
5517 /* But enable STOP interrupt, to treat it */
5518 /* Error callback will be send during stop flag treatment */
5519 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
5520
5521 /* Flush TX register */
5522 I2C_Flush_TXDR(hi2c);
5523 }
5524 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \
5525 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5526 {
5527 /* Write LSB part of Memory Address */
5528 hi2c->Instance->TXDR = hi2c->Memaddress;
5529
5530 /* Reset Memaddress content */
5531 hi2c->Memaddress = 0xFFFFFFFFU;
5532 }
5533 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
5534 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5535 {
5536 /* Disable Interrupt related to address step */
5537 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5538
5539 /* Enable only Error interrupt */
5540 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
5541
5542 if (hi2c->XferCount != 0U)
5543 {
5544 /* Prepare the new XferSize to transfer */
5545 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5546 {
5547 hi2c->XferSize = MAX_NBYTE_SIZE;
5548 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5549 I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5550 }
5551 else
5552 {
5553 hi2c->XferSize = hi2c->XferCount;
5554 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5555 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5556 }
5557
5558 /* Update XferCount value */
5559 hi2c->XferCount -= hi2c->XferSize;
5560
5561 /* Enable DMA Request */
5562 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5563 {
5564 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5565 }
5566 else
5567 {
5568 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5569 }
5570 }
5571 else
5572 {
5573 /* Wrong size Status regarding TCR flag event */
5574 /* Call the corresponding callback to inform upper layer of End of Transfer */
5575 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5576 }
5577 }
5578 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
5579 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5580 {
5581 /* Disable Interrupt related to address step */
5582 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5583
5584 /* Enable only Error and NACK interrupt for data transfer */
5585 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
5586
5587 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5588 {
5589 direction = I2C_GENERATE_START_READ;
5590 }
5591
5592 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5593 {
5594 hi2c->XferSize = MAX_NBYTE_SIZE;
5595
5596 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
5597 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5598 I2C_RELOAD_MODE, direction);
5599 }
5600 else
5601 {
5602 hi2c->XferSize = hi2c->XferCount;
5603
5604 /* Set NBYTES to write and generate RESTART */
5605 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5606 I2C_AUTOEND_MODE, direction);
5607 }
5608
5609 /* Update XferCount value */
5610 hi2c->XferCount -= hi2c->XferSize;
5611
5612 /* Enable DMA Request */
5613 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5614 {
5615 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5616 }
5617 else
5618 {
5619 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5620 }
5621 }
5622 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5623 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5624 {
5625 /* Call I2C Master complete process */
5626 I2C_ITMasterCplt(hi2c, ITFlags);
5627 }
5628 else
5629 {
5630 /* Nothing to do */
5631 }
5632
5633 /* Process Unlocked */
5634 __HAL_UNLOCK(hi2c);
5635
5636 return HAL_OK;
5637 }
5638
5639 /**
5640 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
5641 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5642 * the configuration information for the specified I2C.
5643 * @param ITFlags Interrupt flags to handle.
5644 * @param ITSources Interrupt sources enabled.
5645 * @retval HAL status
5646 */
I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5647 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5648 uint32_t ITSources)
5649 {
5650 uint32_t tmpoptions = hi2c->XferOptions;
5651 uint32_t treatdmanack = 0U;
5652 HAL_I2C_StateTypeDef tmpstate;
5653
5654 /* Process locked */
5655 __HAL_LOCK(hi2c);
5656
5657 /* Check if STOPF is set */
5658 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5659 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5660 {
5661 /* Call I2C Slave complete process */
5662 I2C_ITSlaveCplt(hi2c, ITFlags);
5663 }
5664 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5665 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5666 {
5667 /* Check that I2C transfer finished */
5668 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
5669 /* Mean XferCount == 0 */
5670 /* So clear Flag NACKF only */
5671 if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
5672 (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
5673 {
5674 /* Split check of hdmarx, for MISRA compliance */
5675 if (hi2c->hdmarx != NULL)
5676 {
5677 if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
5678 {
5679 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
5680 {
5681 treatdmanack = 1U;
5682 }
5683 }
5684 }
5685
5686 /* Split check of hdmatx, for MISRA compliance */
5687 if (hi2c->hdmatx != NULL)
5688 {
5689 if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
5690 {
5691 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
5692 {
5693 treatdmanack = 1U;
5694 }
5695 }
5696 }
5697
5698 if (treatdmanack == 1U)
5699 {
5700 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
5701 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
5702 Warning[Pa134]: left and right operands are identical */
5703 {
5704 /* Call I2C Listen complete process */
5705 I2C_ITListenCplt(hi2c, ITFlags);
5706 }
5707 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
5708 {
5709 /* Clear NACK Flag */
5710 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5711
5712 /* Flush TX register */
5713 I2C_Flush_TXDR(hi2c);
5714
5715 /* Last Byte is Transmitted */
5716 /* Call I2C Slave Sequential complete process */
5717 I2C_ITSlaveSeqCplt(hi2c);
5718 }
5719 else
5720 {
5721 /* Clear NACK Flag */
5722 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5723 }
5724 }
5725 else
5726 {
5727 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
5728 /* Clear NACK Flag */
5729 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5730
5731 /* Set ErrorCode corresponding to a Non-Acknowledge */
5732 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5733
5734 /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
5735 tmpstate = hi2c->State;
5736
5737 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
5738 {
5739 if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
5740 {
5741 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
5742 }
5743 else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
5744 {
5745 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
5746 }
5747 else
5748 {
5749 /* Do nothing */
5750 }
5751
5752 /* Call the corresponding callback to inform upper layer of End of Transfer */
5753 I2C_ITError(hi2c, hi2c->ErrorCode);
5754 }
5755 }
5756 }
5757 else
5758 {
5759 /* Only Clear NACK Flag, no DMA treatment is pending */
5760 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5761 }
5762 }
5763 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
5764 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
5765 {
5766 I2C_ITAddrCplt(hi2c, ITFlags);
5767 }
5768 else
5769 {
5770 /* Nothing to do */
5771 }
5772
5773 /* Process Unlocked */
5774 __HAL_UNLOCK(hi2c);
5775
5776 return HAL_OK;
5777 }
5778
5779 /**
5780 * @brief Master sends target device address followed by internal memory address for write request.
5781 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5782 * the configuration information for the specified I2C.
5783 * @param DevAddress Target device address: The device 7 bits address value
5784 * in datasheet must be shifted to the left before calling the interface
5785 * @param MemAddress Internal memory address
5786 * @param MemAddSize Size of internal memory address
5787 * @param Timeout Timeout duration
5788 * @param Tickstart Tick start value
5789 * @retval HAL status
5790 */
I2C_RequestMemoryWrite(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)5791 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
5792 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
5793 uint32_t Tickstart)
5794 {
5795 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
5796
5797 /* Wait until TXIS flag is set */
5798 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5799 {
5800 return HAL_ERROR;
5801 }
5802
5803 /* If Memory address size is 8Bit */
5804 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
5805 {
5806 /* Send Memory Address */
5807 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5808 }
5809 /* If Memory address size is 16Bit */
5810 else
5811 {
5812 /* Send MSB of Memory Address */
5813 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
5814
5815 /* Wait until TXIS flag is set */
5816 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5817 {
5818 return HAL_ERROR;
5819 }
5820
5821 /* Send LSB of Memory Address */
5822 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5823 }
5824
5825 /* Wait until TCR flag is set */
5826 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
5827 {
5828 return HAL_ERROR;
5829 }
5830
5831 return HAL_OK;
5832 }
5833
5834 /**
5835 * @brief Master sends target device address followed by internal memory address for read request.
5836 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5837 * the configuration information for the specified I2C.
5838 * @param DevAddress Target device address: The device 7 bits address value
5839 * in datasheet must be shifted to the left before calling the interface
5840 * @param MemAddress Internal memory address
5841 * @param MemAddSize Size of internal memory address
5842 * @param Timeout Timeout duration
5843 * @param Tickstart Tick start value
5844 * @retval HAL status
5845 */
I2C_RequestMemoryRead(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)5846 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
5847 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
5848 uint32_t Tickstart)
5849 {
5850 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
5851
5852 /* Wait until TXIS flag is set */
5853 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5854 {
5855 return HAL_ERROR;
5856 }
5857
5858 /* If Memory address size is 8Bit */
5859 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
5860 {
5861 /* Send Memory Address */
5862 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5863 }
5864 /* If Memory address size is 16Bit */
5865 else
5866 {
5867 /* Send MSB of Memory Address */
5868 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
5869
5870 /* Wait until TXIS flag is set */
5871 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5872 {
5873 return HAL_ERROR;
5874 }
5875
5876 /* Send LSB of Memory Address */
5877 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5878 }
5879
5880 /* Wait until TC flag is set */
5881 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
5882 {
5883 return HAL_ERROR;
5884 }
5885
5886 return HAL_OK;
5887 }
5888
5889 /**
5890 * @brief I2C Address complete process callback.
5891 * @param hi2c I2C handle.
5892 * @param ITFlags Interrupt flags to handle.
5893 * @retval None
5894 */
I2C_ITAddrCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)5895 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
5896 {
5897 uint8_t transferdirection;
5898 uint16_t slaveaddrcode;
5899 uint16_t ownadd1code;
5900 uint16_t ownadd2code;
5901
5902 /* Prevent unused argument(s) compilation warning */
5903 UNUSED(ITFlags);
5904
5905 /* In case of Listen state, need to inform upper layer of address match code event */
5906 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
5907 {
5908 transferdirection = I2C_GET_DIR(hi2c);
5909 slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
5910 ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);
5911 ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
5912
5913 /* If 10bits addressing mode is selected */
5914 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
5915 {
5916 if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
5917 {
5918 slaveaddrcode = ownadd1code;
5919 hi2c->AddrEventCount++;
5920 if (hi2c->AddrEventCount == 2U)
5921 {
5922 /* Reset Address Event counter */
5923 hi2c->AddrEventCount = 0U;
5924
5925 /* Clear ADDR flag */
5926 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
5927
5928 /* Process Unlocked */
5929 __HAL_UNLOCK(hi2c);
5930
5931 /* Call Slave Addr callback */
5932 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5933 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
5934 #else
5935 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
5936 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5937 }
5938 }
5939 else
5940 {
5941 slaveaddrcode = ownadd2code;
5942
5943 /* Disable ADDR Interrupts */
5944 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
5945
5946 /* Process Unlocked */
5947 __HAL_UNLOCK(hi2c);
5948
5949 /* Call Slave Addr callback */
5950 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5951 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
5952 #else
5953 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
5954 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5955 }
5956 }
5957 /* else 7 bits addressing mode is selected */
5958 else
5959 {
5960 /* Disable ADDR Interrupts */
5961 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
5962
5963 /* Process Unlocked */
5964 __HAL_UNLOCK(hi2c);
5965
5966 /* Call Slave Addr callback */
5967 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5968 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
5969 #else
5970 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
5971 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5972 }
5973 }
5974 /* Else clear address flag only */
5975 else
5976 {
5977 /* Clear ADDR flag */
5978 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
5979
5980 /* Process Unlocked */
5981 __HAL_UNLOCK(hi2c);
5982 }
5983 }
5984
5985 /**
5986 * @brief I2C Master sequential complete process.
5987 * @param hi2c I2C handle.
5988 * @retval None
5989 */
I2C_ITMasterSeqCplt(I2C_HandleTypeDef * hi2c)5990 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
5991 {
5992 /* Reset I2C handle mode */
5993 hi2c->Mode = HAL_I2C_MODE_NONE;
5994
5995 /* No Generate Stop, to permit restart mode */
5996 /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
5997 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5998 {
5999 hi2c->State = HAL_I2C_STATE_READY;
6000 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
6001 hi2c->XferISR = NULL;
6002
6003 /* Disable Interrupts */
6004 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
6005
6006 /* Process Unlocked */
6007 __HAL_UNLOCK(hi2c);
6008
6009 /* Call the corresponding callback to inform upper layer of End of Transfer */
6010 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6011 hi2c->MasterTxCpltCallback(hi2c);
6012 #else
6013 HAL_I2C_MasterTxCpltCallback(hi2c);
6014 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6015 }
6016 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
6017 else
6018 {
6019 hi2c->State = HAL_I2C_STATE_READY;
6020 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
6021 hi2c->XferISR = NULL;
6022
6023 /* Disable Interrupts */
6024 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
6025
6026 /* Process Unlocked */
6027 __HAL_UNLOCK(hi2c);
6028
6029 /* Call the corresponding callback to inform upper layer of End of Transfer */
6030 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6031 hi2c->MasterRxCpltCallback(hi2c);
6032 #else
6033 HAL_I2C_MasterRxCpltCallback(hi2c);
6034 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6035 }
6036 }
6037
6038 /**
6039 * @brief I2C Slave sequential complete process.
6040 * @param hi2c I2C handle.
6041 * @retval None
6042 */
I2C_ITSlaveSeqCplt(I2C_HandleTypeDef * hi2c)6043 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
6044 {
6045 uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
6046
6047 /* Reset I2C handle mode */
6048 hi2c->Mode = HAL_I2C_MODE_NONE;
6049
6050 /* If a DMA is ongoing, Update handle size context */
6051 if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
6052 {
6053 /* Disable DMA Request */
6054 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6055 }
6056 else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
6057 {
6058 /* Disable DMA Request */
6059 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6060 }
6061 else
6062 {
6063 /* Do nothing */
6064 }
6065
6066 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
6067 {
6068 /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
6069 hi2c->State = HAL_I2C_STATE_LISTEN;
6070 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6071
6072 /* Disable Interrupts */
6073 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
6074
6075 /* Process Unlocked */
6076 __HAL_UNLOCK(hi2c);
6077
6078 /* Call the corresponding callback to inform upper layer of End of Transfer */
6079 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6080 hi2c->SlaveTxCpltCallback(hi2c);
6081 #else
6082 HAL_I2C_SlaveTxCpltCallback(hi2c);
6083 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6084 }
6085
6086 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
6087 {
6088 /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
6089 hi2c->State = HAL_I2C_STATE_LISTEN;
6090 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6091
6092 /* Disable Interrupts */
6093 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
6094
6095 /* Process Unlocked */
6096 __HAL_UNLOCK(hi2c);
6097
6098 /* Call the corresponding callback to inform upper layer of End of Transfer */
6099 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6100 hi2c->SlaveRxCpltCallback(hi2c);
6101 #else
6102 HAL_I2C_SlaveRxCpltCallback(hi2c);
6103 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6104 }
6105 else
6106 {
6107 /* Nothing to do */
6108 }
6109 }
6110
6111 /**
6112 * @brief I2C Master complete process.
6113 * @param hi2c I2C handle.
6114 * @param ITFlags Interrupt flags to handle.
6115 * @retval None
6116 */
I2C_ITMasterCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6117 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6118 {
6119 uint32_t tmperror;
6120 uint32_t tmpITFlags = ITFlags;
6121 __IO uint32_t tmpreg;
6122
6123 /* Clear STOP Flag */
6124 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6125
6126 /* Disable Interrupts and Store Previous state */
6127 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
6128 {
6129 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
6130 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
6131 }
6132 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6133 {
6134 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
6135 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
6136 }
6137 else
6138 {
6139 /* Do nothing */
6140 }
6141
6142 /* Clear Configuration Register 2 */
6143 I2C_RESET_CR2(hi2c);
6144
6145 /* Reset handle parameters */
6146 hi2c->XferISR = NULL;
6147 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6148
6149 if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
6150 {
6151 /* Clear NACK Flag */
6152 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6153
6154 /* Set acknowledge error code */
6155 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6156 }
6157
6158 /* Fetch Last receive data if any */
6159 if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
6160 {
6161 /* Read data from RXDR */
6162 tmpreg = (uint8_t)hi2c->Instance->RXDR;
6163 UNUSED(tmpreg);
6164 }
6165
6166 /* Flush TX register */
6167 I2C_Flush_TXDR(hi2c);
6168
6169 /* Store current volatile hi2c->ErrorCode, misra rule */
6170 tmperror = hi2c->ErrorCode;
6171
6172 /* Call the corresponding callback to inform upper layer of End of Transfer */
6173 if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
6174 {
6175 /* Call the corresponding callback to inform upper layer of End of Transfer */
6176 I2C_ITError(hi2c, hi2c->ErrorCode);
6177 }
6178 /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
6179 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
6180 {
6181 hi2c->State = HAL_I2C_STATE_READY;
6182 hi2c->PreviousState = I2C_STATE_NONE;
6183
6184 if (hi2c->Mode == HAL_I2C_MODE_MEM)
6185 {
6186 hi2c->Mode = HAL_I2C_MODE_NONE;
6187
6188 /* Process Unlocked */
6189 __HAL_UNLOCK(hi2c);
6190
6191 /* Call the corresponding callback to inform upper layer of End of Transfer */
6192 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6193 hi2c->MemTxCpltCallback(hi2c);
6194 #else
6195 HAL_I2C_MemTxCpltCallback(hi2c);
6196 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6197 }
6198 else
6199 {
6200 hi2c->Mode = HAL_I2C_MODE_NONE;
6201
6202 /* Process Unlocked */
6203 __HAL_UNLOCK(hi2c);
6204
6205 /* Call the corresponding callback to inform upper layer of End of Transfer */
6206 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6207 hi2c->MasterTxCpltCallback(hi2c);
6208 #else
6209 HAL_I2C_MasterTxCpltCallback(hi2c);
6210 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6211 }
6212 }
6213 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
6214 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6215 {
6216 hi2c->State = HAL_I2C_STATE_READY;
6217 hi2c->PreviousState = I2C_STATE_NONE;
6218
6219 if (hi2c->Mode == HAL_I2C_MODE_MEM)
6220 {
6221 hi2c->Mode = HAL_I2C_MODE_NONE;
6222
6223 /* Process Unlocked */
6224 __HAL_UNLOCK(hi2c);
6225
6226 /* Call the corresponding callback to inform upper layer of End of Transfer */
6227 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6228 hi2c->MemRxCpltCallback(hi2c);
6229 #else
6230 HAL_I2C_MemRxCpltCallback(hi2c);
6231 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6232 }
6233 else
6234 {
6235 hi2c->Mode = HAL_I2C_MODE_NONE;
6236
6237 /* Process Unlocked */
6238 __HAL_UNLOCK(hi2c);
6239
6240 /* Call the corresponding callback to inform upper layer of End of Transfer */
6241 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6242 hi2c->MasterRxCpltCallback(hi2c);
6243 #else
6244 HAL_I2C_MasterRxCpltCallback(hi2c);
6245 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6246 }
6247 }
6248 else
6249 {
6250 /* Nothing to do */
6251 }
6252 }
6253
6254 /**
6255 * @brief I2C Slave complete process.
6256 * @param hi2c I2C handle.
6257 * @param ITFlags Interrupt flags to handle.
6258 * @retval None
6259 */
I2C_ITSlaveCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6260 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6261 {
6262 uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
6263 uint32_t tmpITFlags = ITFlags;
6264 uint32_t tmpoptions = hi2c->XferOptions;
6265 HAL_I2C_StateTypeDef tmpstate = hi2c->State;
6266
6267 /* Clear STOP Flag */
6268 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6269
6270 /* Disable Interrupts and Store Previous state */
6271 if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
6272 {
6273 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
6274 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6275 }
6276 else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6277 {
6278 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
6279 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6280 }
6281 else if (tmpstate == HAL_I2C_STATE_LISTEN)
6282 {
6283 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
6284 hi2c->PreviousState = I2C_STATE_NONE;
6285 }
6286 else
6287 {
6288 /* Do nothing */
6289 }
6290
6291 /* Disable Address Acknowledge */
6292 hi2c->Instance->CR2 |= I2C_CR2_NACK;
6293
6294 /* Clear Configuration Register 2 */
6295 I2C_RESET_CR2(hi2c);
6296
6297 /* Flush TX register */
6298 I2C_Flush_TXDR(hi2c);
6299
6300 /* If a DMA is ongoing, Update handle size context */
6301 if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
6302 {
6303 /* Disable DMA Request */
6304 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6305
6306 if (hi2c->hdmatx != NULL)
6307 {
6308 hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
6309 }
6310 }
6311 else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
6312 {
6313 /* Disable DMA Request */
6314 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6315
6316 if (hi2c->hdmarx != NULL)
6317 {
6318 hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
6319 }
6320 }
6321 else
6322 {
6323 /* Do nothing */
6324 }
6325
6326 /* Store Last receive data if any */
6327 if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
6328 {
6329 /* Remove RXNE flag on temporary variable as read done */
6330 tmpITFlags &= ~I2C_FLAG_RXNE;
6331
6332 /* Read data from RXDR */
6333 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
6334
6335 /* Increment Buffer pointer */
6336 hi2c->pBuffPtr++;
6337
6338 if ((hi2c->XferSize > 0U))
6339 {
6340 hi2c->XferSize--;
6341 hi2c->XferCount--;
6342 }
6343 }
6344
6345 /* All data are not transferred, so set error code accordingly */
6346 if (hi2c->XferCount != 0U)
6347 {
6348 /* Set ErrorCode corresponding to a Non-Acknowledge */
6349 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6350 }
6351
6352 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
6353 (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET))
6354 {
6355 /* Check that I2C transfer finished */
6356 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
6357 /* Mean XferCount == 0*/
6358 /* So clear Flag NACKF only */
6359 if (hi2c->XferCount == 0U)
6360 {
6361 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
6362 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
6363 Warning[Pa134]: left and right operands are identical */
6364 {
6365 /* Call I2C Listen complete process */
6366 I2C_ITListenCplt(hi2c, tmpITFlags);
6367 }
6368 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
6369 {
6370 /* Clear NACK Flag */
6371 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6372
6373 /* Flush TX register */
6374 I2C_Flush_TXDR(hi2c);
6375
6376 /* Last Byte is Transmitted */
6377 /* Call I2C Slave Sequential complete process */
6378 I2C_ITSlaveSeqCplt(hi2c);
6379 }
6380 else
6381 {
6382 /* Clear NACK Flag */
6383 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6384 }
6385 }
6386 else
6387 {
6388 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
6389 /* Clear NACK Flag */
6390 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6391
6392 /* Set ErrorCode corresponding to a Non-Acknowledge */
6393 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6394
6395 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
6396 {
6397 /* Call the corresponding callback to inform upper layer of End of Transfer */
6398 I2C_ITError(hi2c, hi2c->ErrorCode);
6399 }
6400 }
6401 }
6402
6403 hi2c->Mode = HAL_I2C_MODE_NONE;
6404 hi2c->XferISR = NULL;
6405
6406 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
6407 {
6408 /* Call the corresponding callback to inform upper layer of End of Transfer */
6409 I2C_ITError(hi2c, hi2c->ErrorCode);
6410
6411 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6412 if (hi2c->State == HAL_I2C_STATE_LISTEN)
6413 {
6414 /* Call I2C Listen complete process */
6415 I2C_ITListenCplt(hi2c, tmpITFlags);
6416 }
6417 }
6418 else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
6419 {
6420 /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
6421 I2C_ITSlaveSeqCplt(hi2c);
6422
6423 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6424 hi2c->State = HAL_I2C_STATE_READY;
6425 hi2c->PreviousState = I2C_STATE_NONE;
6426
6427 /* Process Unlocked */
6428 __HAL_UNLOCK(hi2c);
6429
6430 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6431 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6432 hi2c->ListenCpltCallback(hi2c);
6433 #else
6434 HAL_I2C_ListenCpltCallback(hi2c);
6435 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6436 }
6437 /* Call the corresponding callback to inform upper layer of End of Transfer */
6438 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6439 {
6440 hi2c->State = HAL_I2C_STATE_READY;
6441 hi2c->PreviousState = I2C_STATE_NONE;
6442
6443 /* Process Unlocked */
6444 __HAL_UNLOCK(hi2c);
6445
6446 /* Call the corresponding callback to inform upper layer of End of Transfer */
6447 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6448 hi2c->SlaveRxCpltCallback(hi2c);
6449 #else
6450 HAL_I2C_SlaveRxCpltCallback(hi2c);
6451 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6452 }
6453 else
6454 {
6455 hi2c->State = HAL_I2C_STATE_READY;
6456 hi2c->PreviousState = I2C_STATE_NONE;
6457
6458 /* Process Unlocked */
6459 __HAL_UNLOCK(hi2c);
6460
6461 /* Call the corresponding callback to inform upper layer of End of Transfer */
6462 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6463 hi2c->SlaveTxCpltCallback(hi2c);
6464 #else
6465 HAL_I2C_SlaveTxCpltCallback(hi2c);
6466 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6467 }
6468 }
6469
6470 /**
6471 * @brief I2C Listen complete process.
6472 * @param hi2c I2C handle.
6473 * @param ITFlags Interrupt flags to handle.
6474 * @retval None
6475 */
I2C_ITListenCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6476 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6477 {
6478 /* Reset handle parameters */
6479 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6480 hi2c->PreviousState = I2C_STATE_NONE;
6481 hi2c->State = HAL_I2C_STATE_READY;
6482 hi2c->Mode = HAL_I2C_MODE_NONE;
6483 hi2c->XferISR = NULL;
6484
6485 /* Store Last receive data if any */
6486 if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
6487 {
6488 /* Read data from RXDR */
6489 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
6490
6491 /* Increment Buffer pointer */
6492 hi2c->pBuffPtr++;
6493
6494 if ((hi2c->XferSize > 0U))
6495 {
6496 hi2c->XferSize--;
6497 hi2c->XferCount--;
6498
6499 /* Set ErrorCode corresponding to a Non-Acknowledge */
6500 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6501 }
6502 }
6503
6504 /* Disable all Interrupts*/
6505 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6506
6507 /* Clear NACK Flag */
6508 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6509
6510 /* Process Unlocked */
6511 __HAL_UNLOCK(hi2c);
6512
6513 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6514 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6515 hi2c->ListenCpltCallback(hi2c);
6516 #else
6517 HAL_I2C_ListenCpltCallback(hi2c);
6518 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6519 }
6520
6521 /**
6522 * @brief I2C interrupts error process.
6523 * @param hi2c I2C handle.
6524 * @param ErrorCode Error code to handle.
6525 * @retval None
6526 */
I2C_ITError(I2C_HandleTypeDef * hi2c,uint32_t ErrorCode)6527 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
6528 {
6529 HAL_I2C_StateTypeDef tmpstate = hi2c->State;
6530
6531 uint32_t tmppreviousstate;
6532
6533 /* Reset handle parameters */
6534 hi2c->Mode = HAL_I2C_MODE_NONE;
6535 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6536 hi2c->XferCount = 0U;
6537
6538 /* Set new error code */
6539 hi2c->ErrorCode |= ErrorCode;
6540
6541 /* Disable Interrupts */
6542 if ((tmpstate == HAL_I2C_STATE_LISTEN) ||
6543 (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
6544 (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6545 {
6546 /* Disable all interrupts, except interrupts related to LISTEN state */
6547 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6548
6549 /* keep HAL_I2C_STATE_LISTEN if set */
6550 hi2c->State = HAL_I2C_STATE_LISTEN;
6551 hi2c->XferISR = I2C_Slave_ISR_IT;
6552 }
6553 else
6554 {
6555 /* Disable all interrupts */
6556 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6557
6558 /* Flush TX register */
6559 I2C_Flush_TXDR(hi2c);
6560
6561 /* If state is an abort treatment on going, don't change state */
6562 /* This change will be do later */
6563 if (hi2c->State != HAL_I2C_STATE_ABORT)
6564 {
6565 /* Set HAL_I2C_STATE_READY */
6566 hi2c->State = HAL_I2C_STATE_READY;
6567
6568 /* Check if a STOPF is detected */
6569 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
6570 {
6571 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
6572 {
6573 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6574 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6575 }
6576
6577 /* Clear STOP Flag */
6578 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6579 }
6580
6581 }
6582 hi2c->XferISR = NULL;
6583 }
6584
6585 /* Abort DMA TX transfer if any */
6586 tmppreviousstate = hi2c->PreviousState;
6587
6588 if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
6589 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
6590 {
6591 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
6592 {
6593 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6594 }
6595
6596 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
6597 {
6598 /* Set the I2C DMA Abort callback :
6599 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6600 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
6601
6602 /* Process Unlocked */
6603 __HAL_UNLOCK(hi2c);
6604
6605 /* Abort DMA TX */
6606 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
6607 {
6608 /* Call Directly XferAbortCallback function in case of error */
6609 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
6610 }
6611 }
6612 else
6613 {
6614 I2C_TreatErrorCallback(hi2c);
6615 }
6616 }
6617 /* Abort DMA RX transfer if any */
6618 else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
6619 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
6620 {
6621 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
6622 {
6623 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6624 }
6625
6626 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
6627 {
6628 /* Set the I2C DMA Abort callback :
6629 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6630 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
6631
6632 /* Process Unlocked */
6633 __HAL_UNLOCK(hi2c);
6634
6635 /* Abort DMA RX */
6636 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
6637 {
6638 /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
6639 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
6640 }
6641 }
6642 else
6643 {
6644 I2C_TreatErrorCallback(hi2c);
6645 }
6646 }
6647 else
6648 {
6649 I2C_TreatErrorCallback(hi2c);
6650 }
6651 }
6652
6653 /**
6654 * @brief I2C Error callback treatment.
6655 * @param hi2c I2C handle.
6656 * @retval None
6657 */
I2C_TreatErrorCallback(I2C_HandleTypeDef * hi2c)6658 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
6659 {
6660 if (hi2c->State == HAL_I2C_STATE_ABORT)
6661 {
6662 hi2c->State = HAL_I2C_STATE_READY;
6663 hi2c->PreviousState = I2C_STATE_NONE;
6664
6665 /* Process Unlocked */
6666 __HAL_UNLOCK(hi2c);
6667
6668 /* Call the corresponding callback to inform upper layer of End of Transfer */
6669 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6670 hi2c->AbortCpltCallback(hi2c);
6671 #else
6672 HAL_I2C_AbortCpltCallback(hi2c);
6673 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6674 }
6675 else
6676 {
6677 hi2c->PreviousState = I2C_STATE_NONE;
6678
6679 /* Process Unlocked */
6680 __HAL_UNLOCK(hi2c);
6681
6682 /* Call the corresponding callback to inform upper layer of End of Transfer */
6683 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6684 hi2c->ErrorCallback(hi2c);
6685 #else
6686 HAL_I2C_ErrorCallback(hi2c);
6687 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6688 }
6689 }
6690
6691 /**
6692 * @brief I2C Tx data register flush process.
6693 * @param hi2c I2C handle.
6694 * @retval None
6695 */
I2C_Flush_TXDR(I2C_HandleTypeDef * hi2c)6696 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
6697 {
6698 /* If a pending TXIS flag is set */
6699 /* Write a dummy data in TXDR to clear it */
6700 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
6701 {
6702 hi2c->Instance->TXDR = 0x00U;
6703 }
6704
6705 /* Flush TX register if not empty */
6706 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
6707 {
6708 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
6709 }
6710 }
6711
6712 /**
6713 * @brief DMA I2C master transmit process complete callback.
6714 * @param hdma DMA handle
6715 * @retval None
6716 */
I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef * hdma)6717 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
6718 {
6719 /* Derogation MISRAC2012-Rule-11.5 */
6720 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6721
6722 /* Disable DMA Request */
6723 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6724
6725 /* If last transfer, enable STOP interrupt */
6726 if (hi2c->XferCount == 0U)
6727 {
6728 /* Enable STOP interrupt */
6729 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
6730 }
6731 /* else prepare a new DMA transfer and enable TCReload interrupt */
6732 else
6733 {
6734 /* Update Buffer pointer */
6735 hi2c->pBuffPtr += hi2c->XferSize;
6736
6737 /* Set the XferSize to transfer */
6738 if (hi2c->XferCount > MAX_NBYTE_SIZE)
6739 {
6740 hi2c->XferSize = MAX_NBYTE_SIZE;
6741 }
6742 else
6743 {
6744 hi2c->XferSize = hi2c->XferCount;
6745 }
6746
6747 /* Enable the DMA channel */
6748 if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
6749 hi2c->XferSize) != HAL_OK)
6750 {
6751 /* Call the corresponding callback to inform upper layer of End of Transfer */
6752 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6753 }
6754 else
6755 {
6756 /* Enable TC interrupts */
6757 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
6758 }
6759 }
6760 }
6761
6762
6763 /**
6764 * @brief DMA I2C slave transmit process complete callback.
6765 * @param hdma DMA handle
6766 * @retval None
6767 */
I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef * hdma)6768 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
6769 {
6770 /* Derogation MISRAC2012-Rule-11.5 */
6771 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6772 uint32_t tmpoptions = hi2c->XferOptions;
6773
6774 if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
6775 {
6776 /* Disable DMA Request */
6777 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6778
6779 /* Last Byte is Transmitted */
6780 /* Call I2C Slave Sequential complete process */
6781 I2C_ITSlaveSeqCplt(hi2c);
6782 }
6783 else
6784 {
6785 /* No specific action, Master fully manage the generation of STOP condition */
6786 /* Mean that this generation can arrive at any time, at the end or during DMA process */
6787 /* So STOP condition should be manage through Interrupt treatment */
6788 }
6789 }
6790
6791
6792 /**
6793 * @brief DMA I2C master receive process complete callback.
6794 * @param hdma DMA handle
6795 * @retval None
6796 */
I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef * hdma)6797 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
6798 {
6799 /* Derogation MISRAC2012-Rule-11.5 */
6800 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6801
6802 /* Disable DMA Request */
6803 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6804
6805 /* If last transfer, enable STOP interrupt */
6806 if (hi2c->XferCount == 0U)
6807 {
6808 /* Enable STOP interrupt */
6809 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
6810 }
6811 /* else prepare a new DMA transfer and enable TCReload interrupt */
6812 else
6813 {
6814 /* Update Buffer pointer */
6815 hi2c->pBuffPtr += hi2c->XferSize;
6816
6817 /* Set the XferSize to transfer */
6818 if (hi2c->XferCount > MAX_NBYTE_SIZE)
6819 {
6820 hi2c->XferSize = MAX_NBYTE_SIZE;
6821 }
6822 else
6823 {
6824 hi2c->XferSize = hi2c->XferCount;
6825 }
6826
6827 /* Enable the DMA channel */
6828 if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
6829 hi2c->XferSize) != HAL_OK)
6830 {
6831 /* Call the corresponding callback to inform upper layer of End of Transfer */
6832 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6833 }
6834 else
6835 {
6836 /* Enable TC interrupts */
6837 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
6838 }
6839 }
6840 }
6841
6842
6843 /**
6844 * @brief DMA I2C slave receive process complete callback.
6845 * @param hdma DMA handle
6846 * @retval None
6847 */
I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef * hdma)6848 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
6849 {
6850 /* Derogation MISRAC2012-Rule-11.5 */
6851 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6852 uint32_t tmpoptions = hi2c->XferOptions;
6853
6854 if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \
6855 (tmpoptions != I2C_NO_OPTION_FRAME))
6856 {
6857 /* Disable DMA Request */
6858 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6859
6860 /* Call I2C Slave Sequential complete process */
6861 I2C_ITSlaveSeqCplt(hi2c);
6862 }
6863 else
6864 {
6865 /* No specific action, Master fully manage the generation of STOP condition */
6866 /* Mean that this generation can arrive at any time, at the end or during DMA process */
6867 /* So STOP condition should be manage through Interrupt treatment */
6868 }
6869 }
6870
6871
6872 /**
6873 * @brief DMA I2C communication error callback.
6874 * @param hdma DMA handle
6875 * @retval None
6876 */
I2C_DMAError(DMA_HandleTypeDef * hdma)6877 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
6878 {
6879 /* Derogation MISRAC2012-Rule-11.5 */
6880 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6881
6882 /* Disable Acknowledge */
6883 hi2c->Instance->CR2 |= I2C_CR2_NACK;
6884
6885 /* Call the corresponding callback to inform upper layer of End of Transfer */
6886 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6887 }
6888
6889
6890 /**
6891 * @brief DMA I2C communication abort callback
6892 * (To be called at end of DMA Abort procedure).
6893 * @param hdma DMA handle.
6894 * @retval None
6895 */
I2C_DMAAbort(DMA_HandleTypeDef * hdma)6896 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
6897 {
6898 /* Derogation MISRAC2012-Rule-11.5 */
6899 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6900
6901 /* Reset AbortCpltCallback */
6902 if (hi2c->hdmatx != NULL)
6903 {
6904 hi2c->hdmatx->XferAbortCallback = NULL;
6905 }
6906 if (hi2c->hdmarx != NULL)
6907 {
6908 hi2c->hdmarx->XferAbortCallback = NULL;
6909 }
6910
6911 I2C_TreatErrorCallback(hi2c);
6912 }
6913
6914
6915 /**
6916 * @brief This function handles I2C Communication Timeout. It waits
6917 * until a flag is no longer in the specified status.
6918 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6919 * the configuration information for the specified I2C.
6920 * @param Flag Specifies the I2C flag to check.
6921 * @param Status The actual Flag status (SET or RESET).
6922 * @param Timeout Timeout duration
6923 * @param Tickstart Tick start value
6924 * @retval HAL status
6925 */
I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Flag,FlagStatus Status,uint32_t Timeout,uint32_t Tickstart)6926 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
6927 uint32_t Timeout, uint32_t Tickstart)
6928 {
6929 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
6930 {
6931 /* Check if an error is detected */
6932 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
6933 {
6934 return HAL_ERROR;
6935 }
6936
6937 /* Check for the Timeout */
6938 if (Timeout != HAL_MAX_DELAY)
6939 {
6940 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6941 {
6942 if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
6943 {
6944 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6945 hi2c->State = HAL_I2C_STATE_READY;
6946 hi2c->Mode = HAL_I2C_MODE_NONE;
6947
6948 /* Process Unlocked */
6949 __HAL_UNLOCK(hi2c);
6950 return HAL_ERROR;
6951 }
6952 }
6953 }
6954 }
6955 return HAL_OK;
6956 }
6957
6958 /**
6959 * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
6960 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6961 * the configuration information for the specified I2C.
6962 * @param Timeout Timeout duration
6963 * @param Tickstart Tick start value
6964 * @retval HAL status
6965 */
I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)6966 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
6967 uint32_t Tickstart)
6968 {
6969 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
6970 {
6971 /* Check if an error is detected */
6972 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
6973 {
6974 return HAL_ERROR;
6975 }
6976
6977 /* Check for the Timeout */
6978 if (Timeout != HAL_MAX_DELAY)
6979 {
6980 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6981 {
6982 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET))
6983 {
6984 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6985 hi2c->State = HAL_I2C_STATE_READY;
6986 hi2c->Mode = HAL_I2C_MODE_NONE;
6987
6988 /* Process Unlocked */
6989 __HAL_UNLOCK(hi2c);
6990
6991 return HAL_ERROR;
6992 }
6993 }
6994 }
6995 }
6996 return HAL_OK;
6997 }
6998
6999 /**
7000 * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
7001 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7002 * the configuration information for the specified I2C.
7003 * @param Timeout Timeout duration
7004 * @param Tickstart Tick start value
7005 * @retval HAL status
7006 */
I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7007 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
7008 uint32_t Tickstart)
7009 {
7010 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
7011 {
7012 /* Check if an error is detected */
7013 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
7014 {
7015 return HAL_ERROR;
7016 }
7017
7018 /* Check for the Timeout */
7019 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7020 {
7021 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
7022 {
7023 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7024 hi2c->State = HAL_I2C_STATE_READY;
7025 hi2c->Mode = HAL_I2C_MODE_NONE;
7026
7027 /* Process Unlocked */
7028 __HAL_UNLOCK(hi2c);
7029
7030 return HAL_ERROR;
7031 }
7032 }
7033 }
7034 return HAL_OK;
7035 }
7036
7037 /**
7038 * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
7039 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7040 * the configuration information for the specified I2C.
7041 * @param Timeout Timeout duration
7042 * @param Tickstart Tick start value
7043 * @retval HAL status
7044 */
I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7045 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
7046 uint32_t Tickstart)
7047 {
7048 HAL_StatusTypeDef status = HAL_OK;
7049
7050 while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK))
7051 {
7052 /* Check if an error is detected */
7053 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
7054 {
7055 status = HAL_ERROR;
7056 }
7057
7058 /* Check if a STOPF is detected */
7059 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK))
7060 {
7061 /* Check if an RXNE is pending */
7062 /* Store Last receive data if any */
7063 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
7064 {
7065 /* Return HAL_OK */
7066 /* The Reading of data from RXDR will be done in caller function */
7067 status = HAL_OK;
7068 }
7069
7070 /* Check a no-acknowledge have been detected */
7071 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
7072 {
7073 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7074 hi2c->ErrorCode = HAL_I2C_ERROR_AF;
7075
7076 /* Clear STOP Flag */
7077 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
7078
7079 /* Clear Configuration Register 2 */
7080 I2C_RESET_CR2(hi2c);
7081
7082 hi2c->State = HAL_I2C_STATE_READY;
7083 hi2c->Mode = HAL_I2C_MODE_NONE;
7084
7085 /* Process Unlocked */
7086 __HAL_UNLOCK(hi2c);
7087
7088 status = HAL_ERROR;
7089 }
7090 else
7091 {
7092 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
7093 }
7094 }
7095
7096 /* Check for the Timeout */
7097 if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK))
7098 {
7099 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
7100 {
7101 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7102 hi2c->State = HAL_I2C_STATE_READY;
7103
7104 /* Process Unlocked */
7105 __HAL_UNLOCK(hi2c);
7106
7107 status = HAL_ERROR;
7108 }
7109 }
7110 }
7111 return status;
7112 }
7113
7114 /**
7115 * @brief This function handles errors detection during an I2C Communication.
7116 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7117 * the configuration information for the specified I2C.
7118 * @param Timeout Timeout duration
7119 * @param Tickstart Tick start value
7120 * @retval HAL status
7121 */
I2C_IsErrorOccurred(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7122 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7123 {
7124 HAL_StatusTypeDef status = HAL_OK;
7125 uint32_t itflag = hi2c->Instance->ISR;
7126 uint32_t error_code = 0;
7127 uint32_t tickstart = Tickstart;
7128 uint32_t tmp1;
7129 HAL_I2C_ModeTypeDef tmp2;
7130
7131 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
7132 {
7133 /* Clear NACKF Flag */
7134 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7135
7136 /* Wait until STOP Flag is set or timeout occurred */
7137 /* AutoEnd should be initiate after AF */
7138 while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
7139 {
7140 /* Check for the Timeout */
7141 if (Timeout != HAL_MAX_DELAY)
7142 {
7143 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7144 {
7145 tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
7146 tmp2 = hi2c->Mode;
7147
7148 /* In case of I2C still busy, try to regenerate a STOP manually */
7149 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
7150 (tmp1 != I2C_CR2_STOP) && \
7151 (tmp2 != HAL_I2C_MODE_SLAVE))
7152 {
7153 /* Generate Stop */
7154 hi2c->Instance->CR2 |= I2C_CR2_STOP;
7155
7156 /* Update Tick with new reference */
7157 tickstart = HAL_GetTick();
7158 }
7159
7160 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
7161 {
7162 /* Check for the Timeout */
7163 if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
7164 {
7165 error_code |= HAL_I2C_ERROR_TIMEOUT;
7166
7167 status = HAL_ERROR;
7168
7169 break;
7170 }
7171 }
7172 }
7173 }
7174 }
7175
7176 /* In case STOP Flag is detected, clear it */
7177 if (status == HAL_OK)
7178 {
7179 /* Clear STOP Flag */
7180 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
7181 }
7182
7183 error_code |= HAL_I2C_ERROR_AF;
7184
7185 status = HAL_ERROR;
7186 }
7187
7188 /* Refresh Content of Status register */
7189 itflag = hi2c->Instance->ISR;
7190
7191 /* Then verify if an additional errors occurs */
7192 /* Check if a Bus error occurred */
7193 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
7194 {
7195 error_code |= HAL_I2C_ERROR_BERR;
7196
7197 /* Clear BERR flag */
7198 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
7199
7200 status = HAL_ERROR;
7201 }
7202
7203 /* Check if an Over-Run/Under-Run error occurred */
7204 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
7205 {
7206 error_code |= HAL_I2C_ERROR_OVR;
7207
7208 /* Clear OVR flag */
7209 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
7210
7211 status = HAL_ERROR;
7212 }
7213
7214 /* Check if an Arbitration Loss error occurred */
7215 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
7216 {
7217 error_code |= HAL_I2C_ERROR_ARLO;
7218
7219 /* Clear ARLO flag */
7220 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
7221
7222 status = HAL_ERROR;
7223 }
7224
7225 if (status != HAL_OK)
7226 {
7227 /* Flush TX register */
7228 I2C_Flush_TXDR(hi2c);
7229
7230 /* Clear Configuration Register 2 */
7231 I2C_RESET_CR2(hi2c);
7232
7233 hi2c->ErrorCode |= error_code;
7234 hi2c->State = HAL_I2C_STATE_READY;
7235 hi2c->Mode = HAL_I2C_MODE_NONE;
7236
7237 /* Process Unlocked */
7238 __HAL_UNLOCK(hi2c);
7239 }
7240
7241 return status;
7242 }
7243
7244 /**
7245 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
7246 * @param hi2c I2C handle.
7247 * @param DevAddress Specifies the slave address to be programmed.
7248 * @param Size Specifies the number of bytes to be programmed.
7249 * This parameter must be a value between 0 and 255.
7250 * @param Mode New state of the I2C START condition generation.
7251 * This parameter can be one of the following values:
7252 * @arg @ref I2C_RELOAD_MODE Enable Reload mode .
7253 * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
7254 * @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
7255 * @param Request New state of the I2C START condition generation.
7256 * This parameter can be one of the following values:
7257 * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
7258 * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
7259 * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
7260 * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
7261 * @retval None
7262 */
I2C_TransferConfig(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t Size,uint32_t Mode,uint32_t Request)7263 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
7264 uint32_t Request)
7265 {
7266 /* Check the parameters */
7267 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
7268 assert_param(IS_TRANSFER_MODE(Mode));
7269 assert_param(IS_TRANSFER_REQUEST(Request));
7270
7271 /* Declaration of tmp to prevent undefined behavior of volatile usage */
7272 uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
7273 (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
7274 (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
7275
7276 /* update CR2 register */
7277 MODIFY_REG(hi2c->Instance->CR2, \
7278 ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
7279 (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
7280 I2C_CR2_START | I2C_CR2_STOP)), tmp);
7281 }
7282
7283 /**
7284 * @brief Manage the enabling of Interrupts.
7285 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7286 * the configuration information for the specified I2C.
7287 * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
7288 * @retval None
7289 */
I2C_Enable_IRQ(I2C_HandleTypeDef * hi2c,uint16_t InterruptRequest)7290 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
7291 {
7292 uint32_t tmpisr = 0U;
7293
7294 if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \
7295 (hi2c->XferISR != I2C_Slave_ISR_DMA) && \
7296 (hi2c->XferISR != I2C_Mem_ISR_DMA))
7297 {
7298 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7299 {
7300 /* Enable ERR, STOP, NACK and ADDR interrupts */
7301 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7302 }
7303
7304 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7305 {
7306 /* Enable ERR, TC, STOP, NACK and TXI interrupts */
7307 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
7308 }
7309
7310 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7311 {
7312 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
7313 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
7314 }
7315
7316 if (InterruptRequest == I2C_XFER_ERROR_IT)
7317 {
7318 /* Enable ERR and NACK interrupts */
7319 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7320 }
7321
7322 if (InterruptRequest == I2C_XFER_CPLT_IT)
7323 {
7324 /* Enable STOP interrupts */
7325 tmpisr |= I2C_IT_STOPI;
7326 }
7327 }
7328
7329 else
7330 {
7331 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7332 {
7333 /* Enable ERR, STOP, NACK and ADDR interrupts */
7334 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7335 }
7336
7337 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7338 {
7339 /* Enable ERR, TC, STOP, NACK and TXI interrupts */
7340 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
7341 }
7342
7343 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7344 {
7345 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
7346 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
7347 }
7348
7349 if (InterruptRequest == I2C_XFER_ERROR_IT)
7350 {
7351 /* Enable ERR and NACK interrupts */
7352 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7353 }
7354
7355 if (InterruptRequest == I2C_XFER_CPLT_IT)
7356 {
7357 /* Enable STOP interrupts */
7358 tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
7359 }
7360
7361 if (InterruptRequest == I2C_XFER_RELOAD_IT)
7362 {
7363 /* Enable TC interrupts */
7364 tmpisr |= I2C_IT_TCI;
7365 }
7366 }
7367
7368 /* Enable interrupts only at the end */
7369 /* to avoid the risk of I2C interrupt handle execution before */
7370 /* all interrupts requested done */
7371 __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
7372 }
7373
7374 /**
7375 * @brief Manage the disabling of Interrupts.
7376 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7377 * the configuration information for the specified I2C.
7378 * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
7379 * @retval None
7380 */
I2C_Disable_IRQ(I2C_HandleTypeDef * hi2c,uint16_t InterruptRequest)7381 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
7382 {
7383 uint32_t tmpisr = 0U;
7384
7385 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7386 {
7387 /* Disable TC and TXI interrupts */
7388 tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
7389
7390 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
7391 {
7392 /* Disable NACK and STOP interrupts */
7393 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7394 }
7395 }
7396
7397 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7398 {
7399 /* Disable TC and RXI interrupts */
7400 tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
7401
7402 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
7403 {
7404 /* Disable NACK and STOP interrupts */
7405 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7406 }
7407 }
7408
7409 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7410 {
7411 /* Disable ADDR, NACK and STOP interrupts */
7412 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7413 }
7414
7415 if (InterruptRequest == I2C_XFER_ERROR_IT)
7416 {
7417 /* Enable ERR and NACK interrupts */
7418 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7419 }
7420
7421 if (InterruptRequest == I2C_XFER_CPLT_IT)
7422 {
7423 /* Enable STOP interrupts */
7424 tmpisr |= I2C_IT_STOPI;
7425 }
7426
7427 if (InterruptRequest == I2C_XFER_RELOAD_IT)
7428 {
7429 /* Enable TC interrupts */
7430 tmpisr |= I2C_IT_TCI;
7431 }
7432
7433 /* Disable interrupts only at the end */
7434 /* to avoid a breaking situation like at "t" time */
7435 /* all disable interrupts request are not done */
7436 __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
7437 }
7438
7439 /**
7440 * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
7441 * @param hi2c I2C handle.
7442 * @retval None
7443 */
I2C_ConvertOtherXferOptions(I2C_HandleTypeDef * hi2c)7444 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
7445 {
7446 /* if user set XferOptions to I2C_OTHER_FRAME */
7447 /* it request implicitly to generate a restart condition */
7448 /* set XferOptions to I2C_FIRST_FRAME */
7449 if (hi2c->XferOptions == I2C_OTHER_FRAME)
7450 {
7451 hi2c->XferOptions = I2C_FIRST_FRAME;
7452 }
7453 /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
7454 /* it request implicitly to generate a restart condition */
7455 /* then generate a stop condition at the end of transfer */
7456 /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */
7457 else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
7458 {
7459 hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
7460 }
7461 else
7462 {
7463 /* Nothing to do */
7464 }
7465 }
7466
7467 /**
7468 * @}
7469 */
7470
7471 #endif /* HAL_I2C_MODULE_ENABLED */
7472 /**
7473 * @}
7474 */
7475
7476 /**
7477 * @}
7478 */
7479
