1 /**
2 ******************************************************************************
3 * @file stm32g0xx_hal_adc.c
4 * @author MCD Application Team
5 * @brief This file provides firmware functions to manage the following
6 * functionalities of the Analog to Digital Converter (ADC)
7 * peripheral:
8 * + Initialization and de-initialization functions
9 * + Peripheral Control functions
10 * + Peripheral State functions
11 * Other functions (extended functions) are available in file
12 * "stm32g0xx_hal_adc_ex.c".
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2018 STMicroelectronics.
18 * All rights reserved.
19 *
20 * This software is licensed under terms that can be found in the LICENSE file
21 * in the root directory of this software component.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
23 *
24 ******************************************************************************
25 @verbatim
26 ==============================================================================
27 ##### ADC peripheral features #####
28 ==============================================================================
29 [..]
30 (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
31
32 (+) Interrupt generation at the end of regular conversion and in case of
33 analog watchdog or overrun events.
34
35 (+) Single and continuous conversion modes.
36
37 (+) Scan mode for conversion of several channels sequentially.
38
39 (+) Data alignment with in-built data coherency.
40
41 (+) Programmable sampling time (common to group of channels)
42
43 (+) External trigger (timer or EXTI) with configurable polarity
44
45 (+) DMA request generation for transfer of conversions data of regular group.
46
47 (+) ADC calibration
48
49 (+) ADC conversion of regular group.
50
51 (+) ADC supply requirements: 1.62 V to 3.6 V.
52
53 (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
54 Vdda or to an external voltage reference).
55
56
57 ##### How to use this driver #####
58 ==============================================================================
59 [..]
60
61 *** Configuration of top level parameters related to ADC ***
62 ============================================================
63 [..]
64
65 (#) Enable the ADC interface
66 (++) As prerequisite, ADC clock must be configured at RCC top level.
67 Caution: On STM32G0, ADC clock frequency max is 35MHz (refer
68 to device datasheet).
69 Therefore, ADC clock source from RCC and ADC clock
70 prescaler must be configured to remain below
71 this maximum frequency.
72
73 (++) Two clock settings are mandatory:
74 (+++) ADC clock (core clock, also possibly conversion clock).
75
76 (+++) ADC clock (conversions clock).
77 Four possible clock sources: synchronous clock from APB clock (same as ADC core clock)
78 or asynchronous clock from RCC level: SYSCLK, HSI16, PLLPCLK.
79
80 (+++) Example:
81 Into HAL_ADC_MspInit() (recommended code location) or with
82 other device clock parameters configuration:
83 (+++) __HAL_RCC_ADC_CLK_ENABLE(); (mandatory: core clock)
84
85 (++) ADC clock source and clock prescaler are configured at ADC level with
86 parameter "ClockPrescaler" using function HAL_ADC_Init().
87
88 (#) ADC pins configuration
89 (++) Enable the clock for the ADC GPIOs
90 using macro __HAL_RCC_GPIOx_CLK_ENABLE()
91 (++) Configure these ADC pins in analog mode
92 using function HAL_GPIO_Init()
93
94 (#) Optionally, in case of usage of ADC with interruptions:
95 (++) Configure the NVIC for ADC
96 using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
97 (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
98 into the function of corresponding ADC interruption vector
99 ADCx_IRQHandler().
100
101 (#) Optionally, in case of usage of DMA:
102 (++) Configure the DMA (DMA channel, mode normal or circular, ...)
103 using function HAL_DMA_Init().
104 (++) Configure the NVIC for DMA
105 using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
106 (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
107 into the function of corresponding DMA interruption vector
108 DMAx_Channelx_IRQHandler().
109
110 *** Configuration of ADC, group regular, channels parameters ***
111 ================================================================
112 [..]
113
114 (#) Configure the ADC parameters (resolution, data alignment, ...)
115 and regular group parameters (conversion trigger, sequencer, ...)
116 using function HAL_ADC_Init().
117
118 (#) Configure the channels for regular group parameters (channel number,
119 channel rank into sequencer, ..., into regular group)
120 using function HAL_ADC_ConfigChannel().
121
122 (#) Optionally, configure the analog watchdog parameters (channels
123 monitored, thresholds, ...)
124 using function HAL_ADC_AnalogWDGConfig().
125
126 *** Execution of ADC conversions ***
127 ====================================
128 [..]
129
130 (#) Optionally, perform an automatic ADC calibration to improve the
131 conversion accuracy
132 using function HAL_ADCEx_Calibration_Start().
133
134 (#) ADC driver can be used among three modes: polling, interruption,
135 transfer by DMA.
136
137 (++) ADC conversion by polling:
138 (+++) Activate the ADC peripheral and start conversions
139 using function HAL_ADC_Start()
140 (+++) Wait for ADC conversion completion
141 using function HAL_ADC_PollForConversion()
142 (+++) Retrieve conversion results
143 using function HAL_ADC_GetValue()
144 (+++) Stop conversion and disable the ADC peripheral
145 using function HAL_ADC_Stop()
146
147 (++) ADC conversion by interruption:
148 (+++) Activate the ADC peripheral and start conversions
149 using function HAL_ADC_Start_IT()
150 (+++) Wait for ADC conversion completion by call of function
151 HAL_ADC_ConvCpltCallback()
152 (this function must be implemented in user program)
153 (+++) Retrieve conversion results
154 using function HAL_ADC_GetValue()
155 (+++) Stop conversion and disable the ADC peripheral
156 using function HAL_ADC_Stop_IT()
157
158 (++) ADC conversion with transfer by DMA:
159 (+++) Activate the ADC peripheral and start conversions
160 using function HAL_ADC_Start_DMA()
161 (+++) Wait for ADC conversion completion by call of function
162 HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
163 (these functions must be implemented in user program)
164 (+++) Conversion results are automatically transferred by DMA into
165 destination variable address.
166 (+++) Stop conversion and disable the ADC peripheral
167 using function HAL_ADC_Stop_DMA()
168
169 [..]
170
171 (@) Callback functions must be implemented in user program:
172 (+@) HAL_ADC_ErrorCallback()
173 (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
174 (+@) HAL_ADC_ConvCpltCallback()
175 (+@) HAL_ADC_ConvHalfCpltCallback
176
177 *** Deinitialization of ADC ***
178 ============================================================
179 [..]
180
181 (#) Disable the ADC interface
182 (++) ADC clock can be hard reset and disabled at RCC top level.
183 (++) Hard reset of ADC peripherals
184 using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
185 (++) ADC clock disable
186 using the equivalent macro/functions as configuration step.
187 (+++) Example:
188 Into HAL_ADC_MspDeInit() (recommended code location) or with
189 other device clock parameters configuration:
190 (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
191 (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock)
192 (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
193
194 (#) ADC pins configuration
195 (++) Disable the clock for the ADC GPIOs
196 using macro __HAL_RCC_GPIOx_CLK_DISABLE()
197
198 (#) Optionally, in case of usage of ADC with interruptions:
199 (++) Disable the NVIC for ADC
200 using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
201
202 (#) Optionally, in case of usage of DMA:
203 (++) Deinitialize the DMA
204 using function HAL_DMA_Init().
205 (++) Disable the NVIC for DMA
206 using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
207
208 [..]
209
210 *** Callback registration ***
211 =============================================
212 [..]
213
214 The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
215 allows the user to configure dynamically the driver callbacks.
216 Use Functions HAL_ADC_RegisterCallback()
217 to register an interrupt callback.
218 [..]
219
220 Function HAL_ADC_RegisterCallback() allows to register following callbacks:
221 (+) ConvCpltCallback : ADC conversion complete callback
222 (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
223 (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
224 (+) ErrorCallback : ADC error callback
225 (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
226 (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
227 (+) EndOfSamplingCallback : ADC end of sampling callback
228 (+) MspInitCallback : ADC Msp Init callback
229 (+) MspDeInitCallback : ADC Msp DeInit callback
230 This function takes as parameters the HAL peripheral handle, the Callback ID
231 and a pointer to the user callback function.
232 [..]
233
234 Use function HAL_ADC_UnRegisterCallback to reset a callback to the default
235 weak function.
236 [..]
237
238 HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
239 and the Callback ID.
240 This function allows to reset following callbacks:
241 (+) ConvCpltCallback : ADC conversion complete callback
242 (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
243 (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
244 (+) ErrorCallback : ADC error callback
245 (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
246 (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
247 (+) EndOfSamplingCallback : ADC end of sampling callback
248 (+) MspInitCallback : ADC Msp Init callback
249 (+) MspDeInitCallback : ADC Msp DeInit callback
250 [..]
251
252 By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET
253 all callbacks are set to the corresponding weak functions:
254 examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback().
255 Exception done for MspInit and MspDeInit functions that are
256 reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when
257 these callbacks are null (not registered beforehand).
258 [..]
259
260 If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit()
261 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
262 [..]
263
264 Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only.
265 Exception done MspInit/MspDeInit functions that can be registered/unregistered
266 in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state,
267 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
268 [..]
269
270 Then, the user first registers the MspInit/MspDeInit user callbacks
271 using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit()
272 or HAL_ADC_Init() function.
273 [..]
274
275 When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
276 not defined, the callback registration feature is not available and all callbacks
277 are set to the corresponding weak functions.
278
279 @endverbatim
280 ******************************************************************************
281 */
282
283 /* Includes ------------------------------------------------------------------*/
284 #include "stm32g0xx_hal.h"
285
286 /** @addtogroup STM32G0xx_HAL_Driver
287 * @{
288 */
289
290 /** @defgroup ADC ADC
291 * @brief ADC HAL module driver
292 * @{
293 */
294
295 #ifdef HAL_ADC_MODULE_ENABLED
296
297 /* Private typedef -----------------------------------------------------------*/
298 /* Private define ------------------------------------------------------------*/
299
300 /** @defgroup ADC_Private_Constants ADC Private Constants
301 * @{
302 */
303
304 /* Fixed timeout values for ADC calibration, enable settling time, disable */
305 /* settling time. */
306 /* Values defined to be higher than worst cases: low clock frequency, */
307 /* maximum prescaler. */
308 /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
309 /* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits. */
310 /* Unit: ms */
311 #define ADC_ENABLE_TIMEOUT (2UL)
312 #define ADC_DISABLE_TIMEOUT (2UL)
313 #define ADC_STOP_CONVERSION_TIMEOUT (2UL)
314 #define ADC_CHANNEL_CONF_RDY_TIMEOUT (1UL)
315
316 /* Register CHSELR bits corresponding to ranks 2 to 8 . */
317 #define ADC_CHSELR_SQ2_TO_SQ8 (ADC_CHSELR_SQ2 | ADC_CHSELR_SQ3 | ADC_CHSELR_SQ4 | \
318 ADC_CHSELR_SQ5 | ADC_CHSELR_SQ6 | ADC_CHSELR_SQ7 | ADC_CHSELR_SQ8)
319
320 /**
321 * @}
322 */
323
324 /* Private macro -------------------------------------------------------------*/
325 /* Private variables ---------------------------------------------------------*/
326 /* Private function prototypes -----------------------------------------------*/
327 /** @defgroup ADC_Private_Functions ADC Private Functions
328 * @{
329 */
330 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
331 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
332 static void ADC_DMAError(DMA_HandleTypeDef *hdma);
333 /**
334 * @}
335 */
336
337 /* Exported functions ---------------------------------------------------------*/
338
339 /** @defgroup ADC_Exported_Functions ADC Exported Functions
340 * @{
341 */
342
343 /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
344 * @brief ADC Initialization and Configuration functions
345 *
346 @verbatim
347 ===============================================================================
348 ##### Initialization and de-initialization functions #####
349 ===============================================================================
350 [..] This section provides functions allowing to:
351 (+) Initialize and configure the ADC.
352 (+) De-initialize the ADC.
353 @endverbatim
354 * @{
355 */
356
357 /**
358 * @brief Initialize the ADC peripheral and regular group according to
359 * parameters specified in structure "ADC_InitTypeDef".
360 * @note As prerequisite, ADC clock must be configured at RCC top level
361 * (refer to description of RCC configuration for ADC
362 * in header of this file).
363 * @note Possibility to update parameters on the fly:
364 * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
365 * coming from ADC state reset. Following calls to this function can
366 * be used to reconfigure some parameters of ADC_InitTypeDef
367 * structure on the fly, without modifying MSP configuration. If ADC
368 * MSP has to be modified again, HAL_ADC_DeInit() must be called
369 * before HAL_ADC_Init().
370 * The setting of these parameters is conditioned to ADC state.
371 * For parameters constraints, see comments of structure
372 * "ADC_InitTypeDef".
373 * @note This function configures the ADC within 2 scopes: scope of entire
374 * ADC and scope of regular group. For parameters details, see comments
375 * of structure "ADC_InitTypeDef".
376 * @param hadc ADC handle
377 * @retval HAL status
378 */
HAL_ADC_Init(ADC_HandleTypeDef * hadc)379 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
380 {
381 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
382 uint32_t tmp_cfgr1 = 0UL;
383 uint32_t tmp_cfgr2 = 0UL;
384 uint32_t tmp_adc_reg_is_conversion_on_going;
385 __IO uint32_t wait_loop_index = 0UL;
386
387 /* Check ADC handle */
388 if (hadc == NULL)
389 {
390 return HAL_ERROR;
391 }
392
393 /* Check the parameters */
394 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
395 assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
396 assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
397 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
398 assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
399 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
400 assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
401 assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
402 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
403 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
404 assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
405 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
406 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff));
407 assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon1));
408 assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon2));
409 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
410 if (hadc->Init.OversamplingMode == ENABLE)
411 {
412 assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
413 assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
414 assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
415 }
416 assert_param(IS_ADC_TRIGGER_FREQ(hadc->Init.TriggerFrequencyMode));
417
418 if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
419 {
420 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
421
422 if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
423 {
424 assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
425 }
426 }
427
428 /* ADC group regular discontinuous mode can be enabled only if */
429 /* continuous mode is disabled. */
430 assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
431
432 /* Actions performed only if ADC is coming from state reset: */
433 /* - Initialization of ADC MSP */
434 if (hadc->State == HAL_ADC_STATE_RESET)
435 {
436 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
437 /* Init the ADC Callback settings */
438 hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */
439 hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
440 hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
441 hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
442 hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */
443 hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */
444 hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */
445
446 if (hadc->MspInitCallback == NULL)
447 {
448 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
449 }
450
451 /* Init the low level hardware */
452 hadc->MspInitCallback(hadc);
453 #else
454 /* Init the low level hardware */
455 HAL_ADC_MspInit(hadc);
456 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
457
458 /* Set ADC error code to none */
459 ADC_CLEAR_ERRORCODE(hadc);
460
461 /* Initialize Lock */
462 hadc->Lock = HAL_UNLOCKED;
463 }
464
465 if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
466 {
467 /* Enable ADC internal voltage regulator */
468 LL_ADC_EnableInternalRegulator(hadc->Instance);
469
470 /* Delay for ADC stabilization time */
471 /* Wait loop initialization and execution */
472 /* Note: Variable divided by 2 to compensate partially */
473 /* CPU processing cycles, scaling in us split to not */
474 /* exceed 32 bits register capacity and handle low frequency. */
475 wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
476 while (wait_loop_index != 0UL)
477 {
478 wait_loop_index--;
479 }
480 }
481
482 /* Verification that ADC voltage regulator is correctly enabled, whether */
483 /* or not ADC is coming from state reset (if any potential problem of */
484 /* clocking, voltage regulator would not be enabled). */
485 if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
486 {
487 /* Update ADC state machine to error */
488 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
489
490 /* Set ADC error code to ADC peripheral internal error */
491 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
492
493 tmp_hal_status = HAL_ERROR;
494 }
495
496 /* Configuration of ADC parameters if previous preliminary actions are */
497 /* correctly completed and if there is no conversion on going on regular */
498 /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
499 /* called to update a parameter on the fly). */
500 tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
501
502 if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
503 && (tmp_adc_reg_is_conversion_on_going == 0UL)
504 )
505 {
506 /* Set ADC state */
507 ADC_STATE_CLR_SET(hadc->State,
508 HAL_ADC_STATE_REG_BUSY,
509 HAL_ADC_STATE_BUSY_INTERNAL);
510
511 /* Configuration of common ADC parameters */
512
513 /* Parameters update conditioned to ADC state: */
514 /* Parameters that can be updated only when ADC is disabled: */
515 /* - Internal voltage regulator (no parameter in HAL ADC init structure) */
516 /* - Clock configuration */
517 /* - ADC resolution */
518 /* - Oversampling */
519 /* - discontinuous mode */
520 /* - LowPowerAutoWait mode */
521 /* - LowPowerAutoPowerOff mode */
522 /* - continuous conversion mode */
523 /* - overrun */
524 /* - external trigger to start conversion */
525 /* - external trigger polarity */
526 /* - data alignment */
527 /* - resolution */
528 /* - scan direction */
529 /* - DMA continuous request */
530 /* - Trigger frequency mode */
531 /* Note: If low power mode AutoPowerOff is enabled, ADC enable */
532 /* and disable phases are performed automatically by hardware */
533 /* (in this case, flag ADC_FLAG_RDY is not set). */
534 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
535 {
536 /* Some parameters of this register are not reset, since they are set */
537 /* by other functions and must be kept in case of usage of this */
538 /* function on the fly (update of a parameter of ADC_InitTypeDef */
539 /* without needing to reconfigure all other ADC groups/channels */
540 /* parameters): */
541 /* - internal measurement paths (VrefInt, ...) */
542 /* (set into HAL_ADC_ConfigChannel() ) */
543
544 tmp_cfgr1 |= (hadc->Init.Resolution |
545 ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
546 ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) |
547 ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
548 ADC_CFGR1_OVERRUN(hadc->Init.Overrun) |
549 hadc->Init.DataAlign |
550 ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) |
551 ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
552
553 /* Update setting of discontinuous mode only if continuous mode is disabled */
554 if (hadc->Init.DiscontinuousConvMode == ENABLE)
555 {
556 if (hadc->Init.ContinuousConvMode == DISABLE)
557 {
558 /* Enable the selected ADC group regular discontinuous mode */
559 tmp_cfgr1 |= ADC_CFGR1_DISCEN;
560 }
561 else
562 {
563 /* ADC regular group discontinuous was intended to be enabled, */
564 /* but ADC regular group modes continuous and sequencer discontinuous */
565 /* cannot be enabled simultaneously. */
566
567 /* Update ADC state machine to error */
568 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
569
570 /* Set ADC error code to ADC peripheral internal error */
571 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
572 }
573 }
574
575 /* Enable external trigger if trigger selection is different of software */
576 /* start. */
577 /* Note: This configuration keeps the hardware feature of parameter */
578 /* ExternalTrigConvEdge "trigger edge none" equivalent to */
579 /* software start. */
580 if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
581 {
582 tmp_cfgr1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) |
583 hadc->Init.ExternalTrigConvEdge);
584 }
585
586 /* Update ADC configuration register with previous settings */
587 MODIFY_REG(hadc->Instance->CFGR1,
588 ADC_CFGR1_RES |
589 ADC_CFGR1_DISCEN |
590 ADC_CFGR1_CHSELRMOD |
591 ADC_CFGR1_AUTOFF |
592 ADC_CFGR1_WAIT |
593 ADC_CFGR1_CONT |
594 ADC_CFGR1_OVRMOD |
595 ADC_CFGR1_EXTSEL |
596 ADC_CFGR1_EXTEN |
597 ADC_CFGR1_ALIGN |
598 ADC_CFGR1_SCANDIR |
599 ADC_CFGR1_DMACFG,
600 tmp_cfgr1);
601
602 tmp_cfgr2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
603 hadc->Init.TriggerFrequencyMode
604 );
605
606 if (hadc->Init.OversamplingMode == ENABLE)
607 {
608 tmp_cfgr2 |= (ADC_CFGR2_OVSE |
609 (hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
610 hadc->Init.Oversampling.Ratio |
611 hadc->Init.Oversampling.RightBitShift |
612 hadc->Init.Oversampling.TriggeredMode
613 );
614 }
615
616 MODIFY_REG(hadc->Instance->CFGR2,
617 ADC_CFGR2_CKMODE |
618 ADC_CFGR2_LFTRIG |
619 ADC_CFGR2_OVSE |
620 ADC_CFGR2_OVSR |
621 ADC_CFGR2_OVSS |
622 ADC_CFGR2_TOVS,
623 tmp_cfgr2);
624
625 /* Configuration of ADC clock mode: asynchronous clock source */
626 /* with selectable prescaler. */
627 if (((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV1) &&
628 ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV2) &&
629 ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV4))
630 {
631 MODIFY_REG(ADC1_COMMON->CCR,
632 ADC_CCR_PRESC,
633 hadc->Init.ClockPrescaler & ADC_CCR_PRESC);
634 }
635 }
636
637 /* Channel sampling time configuration */
638 LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1, hadc->Init.SamplingTimeCommon1);
639 LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_2, hadc->Init.SamplingTimeCommon2);
640
641 /* Configuration of regular group sequencer: */
642 /* - if scan mode is disabled, regular channels sequence length is set to */
643 /* 0x00: 1 channel converted (channel on regular rank 1) */
644 /* Parameter "NbrOfConversion" is discarded. */
645 /* Note: Scan mode is not present by hardware on this device, but */
646 /* emulated by software for alignment over all STM32 devices. */
647 /* - if scan mode is enabled, regular channels sequence length is set to */
648 /* parameter "NbrOfConversion". */
649 /* Channels must be configured into each rank using function */
650 /* "HAL_ADC_ConfigChannel()". */
651 if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
652 {
653 /* Set sequencer scan length by clearing ranks above rank 1 */
654 /* and do not modify rank 1 value. */
655 SET_BIT(hadc->Instance->CHSELR,
656 ADC_CHSELR_SQ2_TO_SQ8);
657 }
658 else if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
659 {
660 /* Set ADC group regular sequencer: */
661 /* - Set ADC group regular sequencer to value memorized */
662 /* in HAL ADC handle */
663 /* Note: This value maybe be initialized at a unknown value, */
664 /* therefore after the first call of "HAL_ADC_Init()", */
665 /* each rank corresponding to parameter "NbrOfConversion" */
666 /* must be set using "HAL_ADC_ConfigChannel()". */
667 /* - Set sequencer scan length by clearing ranks above maximum rank */
668 /* and do not modify other ranks value. */
669 MODIFY_REG(hadc->Instance->CHSELR,
670 ADC_CHSELR_SQ_ALL,
671 (ADC_CHSELR_SQ2_TO_SQ8 << (((hadc->Init.NbrOfConversion - 1UL) * ADC_REGULAR_RANK_2) & 0x1FUL))
672 | (hadc->ADCGroupRegularSequencerRanks)
673 );
674 }
675 else
676 {
677 /* Nothing to do */
678 }
679
680 /* Check back that ADC registers have effectively been configured to */
681 /* ensure of no potential problem of ADC core peripheral clocking. */
682 if (LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1)
683 == hadc->Init.SamplingTimeCommon1)
684 {
685 /* Set ADC error code to none */
686 ADC_CLEAR_ERRORCODE(hadc);
687
688 /* Set the ADC state */
689 ADC_STATE_CLR_SET(hadc->State,
690 HAL_ADC_STATE_BUSY_INTERNAL,
691 HAL_ADC_STATE_READY);
692 }
693 else
694 {
695 /* Update ADC state machine to error */
696 ADC_STATE_CLR_SET(hadc->State,
697 HAL_ADC_STATE_BUSY_INTERNAL,
698 HAL_ADC_STATE_ERROR_INTERNAL);
699
700 /* Set ADC error code to ADC peripheral internal error */
701 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
702
703 tmp_hal_status = HAL_ERROR;
704 }
705
706 }
707 else
708 {
709 /* Update ADC state machine to error */
710 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
711
712 tmp_hal_status = HAL_ERROR;
713 }
714
715 return tmp_hal_status;
716 }
717
718 /**
719 * @brief Deinitialize the ADC peripheral registers to their default reset
720 * values, with deinitialization of the ADC MSP.
721 * @note For devices with several ADCs: reset of ADC common registers is done
722 * only if all ADCs sharing the same common group are disabled.
723 * (function "HAL_ADC_MspDeInit()" is also called under the same conditions:
724 * all ADC instances use the same core clock at RCC level, disabling
725 * the core clock reset all ADC instances).
726 * If this is not the case, reset of these common parameters reset is
727 * bypassed without error reporting: it can be the intended behavior in
728 * case of reset of a single ADC while the other ADCs sharing the same
729 * common group is still running.
730 * @param hadc ADC handle
731 * @retval HAL status
732 */
HAL_ADC_DeInit(ADC_HandleTypeDef * hadc)733 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
734 {
735 HAL_StatusTypeDef tmp_hal_status;
736
737 /* Check ADC handle */
738 if (hadc == NULL)
739 {
740 return HAL_ERROR;
741 }
742
743 /* Check the parameters */
744 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
745
746 /* Set ADC state */
747 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
748
749 /* Stop potential conversion on going, on regular group */
750 tmp_hal_status = ADC_ConversionStop(hadc);
751
752 /* Disable ADC peripheral if conversions are effectively stopped */
753 if (tmp_hal_status == HAL_OK)
754 {
755 /* Disable the ADC peripheral */
756 tmp_hal_status = ADC_Disable(hadc);
757
758 /* Check if ADC is effectively disabled */
759 if (tmp_hal_status == HAL_OK)
760 {
761 /* Change ADC state */
762 hadc->State = HAL_ADC_STATE_READY;
763 }
764
765 /* Disable ADC internal voltage regulator */
766 LL_ADC_DisableInternalRegulator(hadc->Instance);
767 }
768
769 /* Note: HAL ADC deInit is done independently of ADC conversion stop */
770 /* and disable return status. In case of status fail, attempt to */
771 /* perform deinitialization anyway and it is up user code in */
772 /* in HAL_ADC_MspDeInit() to reset the ADC peripheral using */
773 /* system RCC hard reset. */
774
775 /* ========== Reset ADC registers ========== */
776 /* Reset register IER */
777 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 |
778 ADC_IT_AWD1 | ADC_IT_OVR |
779 ADC_IT_EOS | ADC_IT_EOC |
780 ADC_IT_EOSMP | ADC_IT_RDY));
781
782 /* Reset register ISR */
783 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 |
784 ADC_FLAG_AWD1 | ADC_FLAG_OVR |
785 ADC_FLAG_EOS | ADC_FLAG_EOC |
786 ADC_FLAG_EOSMP | ADC_FLAG_RDY));
787
788 /* Reset register CR */
789 /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
790 /* "read-set": no direct reset applicable. */
791
792 /* Reset register CFGR1 */
793 hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN |
794 ADC_CFGR1_CHSELRMOD | ADC_CFGR1_AUTOFF |
795 ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD |
796 ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES |
797 ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN);
798
799 /* Reset register SMPR */
800 hadc->Instance->SMPR &= ~ADC_SMPR_SMP1;
801
802 /* Reset register CHSELR */
803 hadc->Instance->CHSELR &= ~(ADC_CHSELR_SQ_ALL);
804
805 /* Reset register DR */
806 /* bits in access mode read only, no direct reset applicable */
807
808 /* Reset registers AWDxTR */
809 hadc->Instance->AWD1TR &= ~(ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1);
810 hadc->Instance->AWD2TR &= ~(ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2);
811 hadc->Instance->AWD3TR &= ~(ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3);
812
813 /* Reset register CFGR2 */
814 /* Note: CFGR2 reset done at the end of de-initialization due to */
815 /* clock source reset */
816 /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
817 /* already done above. */
818 hadc->Instance->CFGR2 &= ~ADC_CFGR2_CKMODE;
819
820 /* Reset register CCR */
821 ADC1_COMMON->CCR &= ~(ADC_CCR_VBATEN | ADC_CCR_TSEN | ADC_CCR_VREFEN | ADC_CCR_PRESC);
822
823 /* ========== Hard reset ADC peripheral ========== */
824 /* Performs a global reset of the entire ADC peripheral: ADC state is */
825 /* forced to a similar state after device power-on. */
826 /* Note: A possible implementation is to add RCC bus reset of ADC */
827 /* (for example, using macro */
828 /* __HAL_RCC_ADC..._FORCE_RESET()/..._RELEASE_RESET()/..._CLK_DISABLE()) */
829 /* in function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */
830 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
831 if (hadc->MspDeInitCallback == NULL)
832 {
833 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
834 }
835
836 /* DeInit the low level hardware */
837 hadc->MspDeInitCallback(hadc);
838 #else
839 /* DeInit the low level hardware */
840 HAL_ADC_MspDeInit(hadc);
841 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
842
843 /* Reset HAL ADC handle variable */
844 hadc->ADCGroupRegularSequencerRanks = 0x00000000UL;
845
846 /* Set ADC error code to none */
847 ADC_CLEAR_ERRORCODE(hadc);
848
849 /* Set ADC state */
850 hadc->State = HAL_ADC_STATE_RESET;
851
852 __HAL_UNLOCK(hadc);
853
854 return tmp_hal_status;
855 }
856
857 /**
858 * @brief Initialize the ADC MSP.
859 * @param hadc ADC handle
860 * @retval None
861 */
HAL_ADC_MspInit(ADC_HandleTypeDef * hadc)862 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
863 {
864 /* Prevent unused argument(s) compilation warning */
865 UNUSED(hadc);
866
867 /* NOTE : This function should not be modified. When the callback is needed,
868 function HAL_ADC_MspInit must be implemented in the user file.
869 */
870 }
871
872 /**
873 * @brief DeInitialize the ADC MSP.
874 * @param hadc ADC handle
875 * @note All ADC instances use the same core clock at RCC level, disabling
876 * the core clock reset all ADC instances).
877 * @retval None
878 */
HAL_ADC_MspDeInit(ADC_HandleTypeDef * hadc)879 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
880 {
881 /* Prevent unused argument(s) compilation warning */
882 UNUSED(hadc);
883
884 /* NOTE : This function should not be modified. When the callback is needed,
885 function HAL_ADC_MspDeInit must be implemented in the user file.
886 */
887 }
888
889 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
890 /**
891 * @brief Register a User ADC Callback
892 * To be used instead of the weak predefined callback
893 * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
894 * the configuration information for the specified ADC.
895 * @param CallbackID ID of the callback to be registered
896 * This parameter can be one of the following values:
897 * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
898 * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
899 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
900 * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
901 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
902 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
903 * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
904 * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
905 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
906 * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
907 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
908 * @param pCallback pointer to the Callback function
909 * @retval HAL status
910 */
HAL_ADC_RegisterCallback(ADC_HandleTypeDef * hadc,HAL_ADC_CallbackIDTypeDef CallbackID,pADC_CallbackTypeDef pCallback)911 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
912 pADC_CallbackTypeDef pCallback)
913 {
914 HAL_StatusTypeDef status = HAL_OK;
915
916 if (pCallback == NULL)
917 {
918 /* Update the error code */
919 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
920
921 return HAL_ERROR;
922 }
923
924 if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
925 {
926 switch (CallbackID)
927 {
928 case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
929 hadc->ConvCpltCallback = pCallback;
930 break;
931
932 case HAL_ADC_CONVERSION_HALF_CB_ID :
933 hadc->ConvHalfCpltCallback = pCallback;
934 break;
935
936 case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
937 hadc->LevelOutOfWindowCallback = pCallback;
938 break;
939
940 case HAL_ADC_ERROR_CB_ID :
941 hadc->ErrorCallback = pCallback;
942 break;
943
944 case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
945 hadc->LevelOutOfWindow2Callback = pCallback;
946 break;
947
948 case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
949 hadc->LevelOutOfWindow3Callback = pCallback;
950 break;
951
952 case HAL_ADC_END_OF_SAMPLING_CB_ID :
953 hadc->EndOfSamplingCallback = pCallback;
954 break;
955
956 case HAL_ADC_MSPINIT_CB_ID :
957 hadc->MspInitCallback = pCallback;
958 break;
959
960 case HAL_ADC_MSPDEINIT_CB_ID :
961 hadc->MspDeInitCallback = pCallback;
962 break;
963
964 default :
965 /* Update the error code */
966 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
967
968 /* Return error status */
969 status = HAL_ERROR;
970 break;
971 }
972 }
973 else if (HAL_ADC_STATE_RESET == hadc->State)
974 {
975 switch (CallbackID)
976 {
977 case HAL_ADC_MSPINIT_CB_ID :
978 hadc->MspInitCallback = pCallback;
979 break;
980
981 case HAL_ADC_MSPDEINIT_CB_ID :
982 hadc->MspDeInitCallback = pCallback;
983 break;
984
985 default :
986 /* Update the error code */
987 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
988
989 /* Return error status */
990 status = HAL_ERROR;
991 break;
992 }
993 }
994 else
995 {
996 /* Update the error code */
997 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
998
999 /* Return error status */
1000 status = HAL_ERROR;
1001 }
1002
1003 return status;
1004 }
1005
1006 /**
1007 * @brief Unregister a ADC Callback
1008 * ADC callback is redirected to the weak predefined callback
1009 * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
1010 * the configuration information for the specified ADC.
1011 * @param CallbackID ID of the callback to be unregistered
1012 * This parameter can be one of the following values:
1013 * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
1014 * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
1015 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
1016 * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
1017 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
1018 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
1019 * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
1020 * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
1021 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
1022 * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
1023 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
1024 * @retval HAL status
1025 */
HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef * hadc,HAL_ADC_CallbackIDTypeDef CallbackID)1026 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
1027 {
1028 HAL_StatusTypeDef status = HAL_OK;
1029
1030 if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
1031 {
1032 switch (CallbackID)
1033 {
1034 case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
1035 hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
1036 break;
1037
1038 case HAL_ADC_CONVERSION_HALF_CB_ID :
1039 hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
1040 break;
1041
1042 case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
1043 hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
1044 break;
1045
1046 case HAL_ADC_ERROR_CB_ID :
1047 hadc->ErrorCallback = HAL_ADC_ErrorCallback;
1048 break;
1049
1050 case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
1051 hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback;
1052 break;
1053
1054 case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
1055 hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback;
1056 break;
1057
1058 case HAL_ADC_END_OF_SAMPLING_CB_ID :
1059 hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback;
1060 break;
1061
1062 case HAL_ADC_MSPINIT_CB_ID :
1063 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
1064 break;
1065
1066 case HAL_ADC_MSPDEINIT_CB_ID :
1067 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
1068 break;
1069
1070 default :
1071 /* Update the error code */
1072 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1073
1074 /* Return error status */
1075 status = HAL_ERROR;
1076 break;
1077 }
1078 }
1079 else if (HAL_ADC_STATE_RESET == hadc->State)
1080 {
1081 switch (CallbackID)
1082 {
1083 case HAL_ADC_MSPINIT_CB_ID :
1084 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
1085 break;
1086
1087 case HAL_ADC_MSPDEINIT_CB_ID :
1088 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
1089 break;
1090
1091 default :
1092 /* Update the error code */
1093 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1094
1095 /* Return error status */
1096 status = HAL_ERROR;
1097 break;
1098 }
1099 }
1100 else
1101 {
1102 /* Update the error code */
1103 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1104
1105 /* Return error status */
1106 status = HAL_ERROR;
1107 }
1108
1109 return status;
1110 }
1111
1112 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1113
1114 /**
1115 * @}
1116 */
1117
1118 /** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
1119 * @brief ADC IO operation functions
1120 *
1121 @verbatim
1122 ===============================================================================
1123 ##### IO operation functions #####
1124 ===============================================================================
1125 [..] This section provides functions allowing to:
1126 (+) Start conversion of regular group.
1127 (+) Stop conversion of regular group.
1128 (+) Poll for conversion complete on regular group.
1129 (+) Poll for conversion event.
1130 (+) Get result of regular channel conversion.
1131 (+) Start conversion of regular group and enable interruptions.
1132 (+) Stop conversion of regular group and disable interruptions.
1133 (+) Handle ADC interrupt request
1134 (+) Start conversion of regular group and enable DMA transfer.
1135 (+) Stop conversion of regular group and disable ADC DMA transfer.
1136 @endverbatim
1137 * @{
1138 */
1139
1140 /**
1141 * @brief Enable ADC, start conversion of regular group.
1142 * @note Interruptions enabled in this function: None.
1143 * @param hadc ADC handle
1144 * @retval HAL status
1145 */
HAL_ADC_Start(ADC_HandleTypeDef * hadc)1146 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
1147 {
1148 HAL_StatusTypeDef tmp_hal_status;
1149
1150 /* Check the parameters */
1151 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1152
1153 /* Perform ADC enable and conversion start if no conversion is on going */
1154 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
1155 {
1156 __HAL_LOCK(hadc);
1157
1158 /* Enable the ADC peripheral */
1159 tmp_hal_status = ADC_Enable(hadc);
1160
1161 /* Start conversion if ADC is effectively enabled */
1162 if (tmp_hal_status == HAL_OK)
1163 {
1164 /* Set ADC state */
1165 /* - Clear state bitfield related to regular group conversion results */
1166 /* - Set state bitfield related to regular operation */
1167 ADC_STATE_CLR_SET(hadc->State,
1168 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
1169 HAL_ADC_STATE_REG_BUSY);
1170
1171 /* Set ADC error code */
1172 /* Reset all ADC error code fields */
1173 ADC_CLEAR_ERRORCODE(hadc);
1174
1175 /* Clear ADC group regular conversion flag and overrun flag */
1176 /* (To ensure of no unknown state from potential previous ADC operations) */
1177 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
1178
1179 /* Process unlocked */
1180 /* Unlock before starting ADC conversions: in case of potential */
1181 /* interruption, to let the process to ADC IRQ Handler. */
1182 __HAL_UNLOCK(hadc);
1183
1184 /* Enable conversion of regular group. */
1185 /* If software start has been selected, conversion starts immediately. */
1186 /* If external trigger has been selected, conversion will start at next */
1187 /* trigger event. */
1188 /* Start ADC group regular conversion */
1189 LL_ADC_REG_StartConversion(hadc->Instance);
1190 }
1191 else
1192 {
1193 __HAL_UNLOCK(hadc);
1194 }
1195 }
1196 else
1197 {
1198 tmp_hal_status = HAL_BUSY;
1199 }
1200
1201 return tmp_hal_status;
1202 }
1203
1204 /**
1205 * @brief Stop ADC conversion of regular group (and injected channels in
1206 * case of auto_injection mode), disable ADC peripheral.
1207 * @note: ADC peripheral disable is forcing stop of potential
1208 * conversion on injected group. If injected group is under use, it
1209 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
1210 * @param hadc ADC handle
1211 * @retval HAL status.
1212 */
HAL_ADC_Stop(ADC_HandleTypeDef * hadc)1213 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
1214 {
1215 HAL_StatusTypeDef tmp_hal_status;
1216
1217 /* Check the parameters */
1218 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1219
1220 __HAL_LOCK(hadc);
1221
1222 /* 1. Stop potential conversion on going, on ADC group regular */
1223 tmp_hal_status = ADC_ConversionStop(hadc);
1224
1225 /* Disable ADC peripheral if conversions are effectively stopped */
1226 if (tmp_hal_status == HAL_OK)
1227 {
1228 /* 2. Disable the ADC peripheral */
1229 tmp_hal_status = ADC_Disable(hadc);
1230
1231 /* Check if ADC is effectively disabled */
1232 if (tmp_hal_status == HAL_OK)
1233 {
1234 /* Set ADC state */
1235 ADC_STATE_CLR_SET(hadc->State,
1236 HAL_ADC_STATE_REG_BUSY,
1237 HAL_ADC_STATE_READY);
1238 }
1239 }
1240
1241 __HAL_UNLOCK(hadc);
1242
1243 return tmp_hal_status;
1244 }
1245
1246 /**
1247 * @brief Wait for regular group conversion to be completed.
1248 * @note ADC conversion flags EOS (end of sequence) and EOC (end of
1249 * conversion) are cleared by this function, with an exception:
1250 * if low power feature "LowPowerAutoWait" is enabled, flags are
1251 * not cleared to not interfere with this feature until data register
1252 * is read using function HAL_ADC_GetValue().
1253 * @note This function cannot be used in a particular setup: ADC configured
1254 * in DMA mode and polling for end of each conversion (ADC init
1255 * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
1256 * In this case, DMA resets the flag EOC and polling cannot be
1257 * performed on each conversion. Nevertheless, polling can still
1258 * be performed on the complete sequence (ADC init
1259 * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
1260 * @param hadc ADC handle
1261 * @param Timeout Timeout value in millisecond.
1262 * @retval HAL status
1263 */
HAL_ADC_PollForConversion(ADC_HandleTypeDef * hadc,uint32_t Timeout)1264 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
1265 {
1266 uint32_t tickstart;
1267 uint32_t tmp_flag_end;
1268
1269 /* Check the parameters */
1270 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1271
1272 /* If end of conversion selected to end of sequence conversions */
1273 if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
1274 {
1275 tmp_flag_end = ADC_FLAG_EOS;
1276 }
1277 /* If end of conversion selected to end of unitary conversion */
1278 else /* ADC_EOC_SINGLE_CONV */
1279 {
1280 /* Verification that ADC configuration is compliant with polling for */
1281 /* each conversion: */
1282 /* Particular case is ADC configured in DMA mode and ADC sequencer with */
1283 /* several ranks and polling for end of each conversion. */
1284 /* For code simplicity sake, this particular case is generalized to */
1285 /* ADC configured in DMA mode and and polling for end of each conversion. */
1286 if ((hadc->Instance->CFGR1 & ADC_CFGR1_DMAEN) != 0UL)
1287 {
1288 /* Update ADC state machine to error */
1289 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1290
1291 return HAL_ERROR;
1292 }
1293 else
1294 {
1295 tmp_flag_end = (ADC_FLAG_EOC);
1296 }
1297 }
1298
1299 /* Get tick count */
1300 tickstart = HAL_GetTick();
1301
1302 /* Wait until End of unitary conversion or sequence conversions flag is raised */
1303 while ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
1304 {
1305 /* Check if timeout is disabled (set to infinite wait) */
1306 if (Timeout != HAL_MAX_DELAY)
1307 {
1308 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
1309 {
1310 /* New check to avoid false timeout detection in case of preemption */
1311 if ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
1312 {
1313 /* Update ADC state machine to timeout */
1314 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
1315
1316 __HAL_UNLOCK(hadc);
1317
1318 return HAL_TIMEOUT;
1319 }
1320 }
1321 }
1322 }
1323
1324 /* Update ADC state machine */
1325 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
1326
1327 /* Determine whether any further conversion upcoming on group regular */
1328 /* by external trigger, continuous mode or scan sequence on going. */
1329 if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
1330 && (hadc->Init.ContinuousConvMode == DISABLE)
1331 )
1332 {
1333 /* Check whether end of sequence is reached */
1334 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
1335 {
1336 /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
1337 /* ADSTART==0 (no conversion on going) */
1338 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
1339 {
1340 /* Disable ADC end of single conversion interrupt on group regular */
1341 /* Note: Overrun interrupt was enabled with EOC interrupt in */
1342 /* HAL_Start_IT(), but is not disabled here because can be used */
1343 /* by overrun IRQ process below. */
1344 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
1345
1346 /* Set ADC state */
1347 ADC_STATE_CLR_SET(hadc->State,
1348 HAL_ADC_STATE_REG_BUSY,
1349 HAL_ADC_STATE_READY);
1350 }
1351 else
1352 {
1353 /* Change ADC state to error state */
1354 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1355
1356 /* Set ADC error code to ADC peripheral internal error */
1357 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
1358 }
1359 }
1360 }
1361
1362 /* Clear end of conversion flag of regular group if low power feature */
1363 /* "LowPowerAutoWait " is disabled, to not interfere with this feature */
1364 /* until data register is read using function HAL_ADC_GetValue(). */
1365 if (hadc->Init.LowPowerAutoWait == DISABLE)
1366 {
1367 /* Clear regular group conversion flag */
1368 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
1369 }
1370
1371 /* Return function status */
1372 return HAL_OK;
1373 }
1374
1375 /**
1376 * @brief Poll for ADC event.
1377 * @param hadc ADC handle
1378 * @param EventType the ADC event type.
1379 * This parameter can be one of the following values:
1380 * @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event
1381 * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on
1382 * all STM32 series)
1383 * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on
1384 * all STM32 series)
1385 * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on
1386 * all STM32 series)
1387 * @arg @ref ADC_OVR_EVENT ADC Overrun event
1388 * @param Timeout Timeout value in millisecond.
1389 * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
1390 * Indeed, the latter is reset only if hadc->Init.Overrun field is set
1391 * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten
1392 * by a new converted data as soon as OVR is cleared.
1393 * To reset OVR flag once the preserved data is retrieved, the user can resort
1394 * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1395 * @retval HAL status
1396 */
HAL_ADC_PollForEvent(ADC_HandleTypeDef * hadc,uint32_t EventType,uint32_t Timeout)1397 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
1398 {
1399 uint32_t tickstart;
1400
1401 /* Check the parameters */
1402 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1403 assert_param(IS_ADC_EVENT_TYPE(EventType));
1404
1405 /* Get tick count */
1406 tickstart = HAL_GetTick();
1407
1408 /* Check selected event flag */
1409 while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
1410 {
1411 /* Check if timeout is disabled (set to infinite wait) */
1412 if (Timeout != HAL_MAX_DELAY)
1413 {
1414 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
1415 {
1416 /* New check to avoid false timeout detection in case of preemption */
1417 if (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
1418 {
1419 /* Update ADC state machine to timeout */
1420 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
1421
1422 __HAL_UNLOCK(hadc);
1423
1424 return HAL_TIMEOUT;
1425 }
1426 }
1427 }
1428 }
1429
1430 switch (EventType)
1431 {
1432 /* End Of Sampling event */
1433 case ADC_EOSMP_EVENT:
1434 /* Set ADC state */
1435 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
1436
1437 /* Clear the End Of Sampling flag */
1438 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
1439
1440 break;
1441
1442 /* Analog watchdog (level out of window) event */
1443 /* Note: In case of several analog watchdog enabled, if needed to know */
1444 /* which one triggered and on which ADCx, test ADC state of analog watchdog */
1445 /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */
1446 /* For example: */
1447 /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */
1448 /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) " */
1449 /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) " */
1450
1451 /* Check analog watchdog 1 flag */
1452 case ADC_AWD_EVENT:
1453 /* Set ADC state */
1454 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
1455
1456 /* Clear ADC analog watchdog flag */
1457 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
1458
1459 break;
1460
1461 /* Check analog watchdog 2 flag */
1462 case ADC_AWD2_EVENT:
1463 /* Set ADC state */
1464 SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
1465
1466 /* Clear ADC analog watchdog flag */
1467 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
1468
1469 break;
1470
1471 /* Check analog watchdog 3 flag */
1472 case ADC_AWD3_EVENT:
1473 /* Set ADC state */
1474 SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
1475
1476 /* Clear ADC analog watchdog flag */
1477 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
1478
1479 break;
1480
1481 /* Overrun event */
1482 default: /* Case ADC_OVR_EVENT */
1483 /* If overrun is set to overwrite previous data, overrun event is not */
1484 /* considered as an error. */
1485 /* (cf ref manual "Managing conversions without using the DMA and without */
1486 /* overrun ") */
1487 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
1488 {
1489 /* Set ADC state */
1490 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
1491
1492 /* Set ADC error code to overrun */
1493 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
1494 }
1495 else
1496 {
1497 /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
1498 otherwise, data register is potentially overwritten by new converted data as soon
1499 as OVR is cleared. */
1500 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1501 }
1502 break;
1503 }
1504
1505 /* Return function status */
1506 return HAL_OK;
1507 }
1508
1509 /**
1510 * @brief Enable ADC, start conversion of regular group with interruption.
1511 * @note Interruptions enabled in this function according to initialization
1512 * setting : EOC (end of conversion), EOS (end of sequence),
1513 * OVR overrun.
1514 * Each of these interruptions has its dedicated callback function.
1515 * @note To guarantee a proper reset of all interruptions once all the needed
1516 * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
1517 * a correct stop of the IT-based conversions.
1518 * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling
1519 * interruption. If required (e.g. in case of oversampling with trigger
1520 * mode), the user must:
1521 * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
1522 * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)
1523 * before calling HAL_ADC_Start_IT().
1524 * @param hadc ADC handle
1525 * @retval HAL status
1526 */
HAL_ADC_Start_IT(ADC_HandleTypeDef * hadc)1527 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
1528 {
1529 HAL_StatusTypeDef tmp_hal_status;
1530
1531 /* Check the parameters */
1532 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1533
1534 /* Perform ADC enable and conversion start if no conversion is on going */
1535 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
1536 {
1537 __HAL_LOCK(hadc);
1538
1539 /* Enable the ADC peripheral */
1540 tmp_hal_status = ADC_Enable(hadc);
1541
1542 /* Start conversion if ADC is effectively enabled */
1543 if (tmp_hal_status == HAL_OK)
1544 {
1545 /* Set ADC state */
1546 /* - Clear state bitfield related to regular group conversion results */
1547 /* - Set state bitfield related to regular operation */
1548 ADC_STATE_CLR_SET(hadc->State,
1549 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
1550 HAL_ADC_STATE_REG_BUSY);
1551
1552
1553 /* Set ADC error code */
1554 /* Reset all ADC error code fields */
1555 ADC_CLEAR_ERRORCODE(hadc);
1556
1557 /* Clear ADC group regular conversion flag and overrun flag */
1558 /* (To ensure of no unknown state from potential previous ADC operations) */
1559 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
1560
1561 /* Process unlocked */
1562 /* Unlock before starting ADC conversions: in case of potential */
1563 /* interruption, to let the process to ADC IRQ Handler. */
1564 __HAL_UNLOCK(hadc);
1565
1566 /* Disable all interruptions before enabling the desired ones */
1567 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
1568
1569 /* Enable ADC end of conversion interrupt */
1570 switch (hadc->Init.EOCSelection)
1571 {
1572 case ADC_EOC_SEQ_CONV:
1573 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
1574 break;
1575 /* case ADC_EOC_SINGLE_CONV */
1576 default:
1577 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
1578 break;
1579 }
1580
1581 /* Enable ADC overrun interrupt */
1582 /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
1583 ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
1584 behavior and no CPU time is lost for a non-processed interruption */
1585 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
1586 {
1587 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
1588 }
1589
1590 /* Enable conversion of regular group. */
1591 /* If software start has been selected, conversion starts immediately. */
1592 /* If external trigger has been selected, conversion will start at next */
1593 /* trigger event. */
1594 /* Start ADC group regular conversion */
1595 LL_ADC_REG_StartConversion(hadc->Instance);
1596 }
1597 else
1598 {
1599 __HAL_UNLOCK(hadc);
1600 }
1601
1602 }
1603 else
1604 {
1605 tmp_hal_status = HAL_BUSY;
1606 }
1607
1608 return tmp_hal_status;
1609 }
1610
1611 /**
1612 * @brief Stop ADC conversion of regular group (and injected group in
1613 * case of auto_injection mode), disable interrution of
1614 * end-of-conversion, disable ADC peripheral.
1615 * @param hadc ADC handle
1616 * @retval HAL status.
1617 */
HAL_ADC_Stop_IT(ADC_HandleTypeDef * hadc)1618 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
1619 {
1620 HAL_StatusTypeDef tmp_hal_status;
1621
1622 /* Check the parameters */
1623 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1624
1625 __HAL_LOCK(hadc);
1626
1627 /* 1. Stop potential conversion on going, on ADC group regular */
1628 tmp_hal_status = ADC_ConversionStop(hadc);
1629
1630 /* Disable ADC peripheral if conversions are effectively stopped */
1631 if (tmp_hal_status == HAL_OK)
1632 {
1633 /* Disable ADC end of conversion interrupt for regular group */
1634 /* Disable ADC overrun interrupt */
1635 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
1636
1637 /* 2. Disable the ADC peripheral */
1638 tmp_hal_status = ADC_Disable(hadc);
1639
1640 /* Check if ADC is effectively disabled */
1641 if (tmp_hal_status == HAL_OK)
1642 {
1643 /* Set ADC state */
1644 ADC_STATE_CLR_SET(hadc->State,
1645 HAL_ADC_STATE_REG_BUSY,
1646 HAL_ADC_STATE_READY);
1647 }
1648 }
1649
1650 __HAL_UNLOCK(hadc);
1651
1652 return tmp_hal_status;
1653 }
1654
1655 /**
1656 * @brief Enable ADC, start conversion of regular group and transfer result through DMA.
1657 * @note Interruptions enabled in this function:
1658 * overrun (if applicable), DMA half transfer, DMA transfer complete.
1659 * Each of these interruptions has its dedicated callback function.
1660 * @param hadc ADC handle
1661 * @param pData Destination Buffer address.
1662 * @param Length Number of data to be transferred from ADC peripheral to memory
1663 * @retval HAL status.
1664 */
HAL_ADC_Start_DMA(ADC_HandleTypeDef * hadc,uint32_t * pData,uint32_t Length)1665 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
1666 {
1667 HAL_StatusTypeDef tmp_hal_status;
1668
1669 /* Check the parameters */
1670 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1671
1672 /* Perform ADC enable and conversion start if no conversion is on going */
1673 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
1674 {
1675 __HAL_LOCK(hadc);
1676
1677 /* Specific case for first call occurrence of this function (DMA transfer */
1678 /* not activated and ADC disabled), DMA transfer must be activated */
1679 /* with ADC disabled. */
1680 if ((hadc->Instance->CFGR1 & ADC_CFGR1_DMAEN) == 0UL)
1681 {
1682 if (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
1683 {
1684 /* Disable ADC */
1685 LL_ADC_Disable(hadc->Instance);
1686 }
1687
1688 /* Enable ADC DMA mode */
1689 hadc->Instance->CFGR1 |= ADC_CFGR1_DMAEN;
1690 }
1691
1692 /* Enable the ADC peripheral */
1693 tmp_hal_status = ADC_Enable(hadc);
1694
1695 /* Start conversion if ADC is effectively enabled */
1696 if (tmp_hal_status == HAL_OK)
1697 {
1698 /* Set ADC state */
1699 /* - Clear state bitfield related to regular group conversion results */
1700 /* - Set state bitfield related to regular operation */
1701 ADC_STATE_CLR_SET(hadc->State,
1702 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
1703 HAL_ADC_STATE_REG_BUSY);
1704
1705 /* Set ADC error code */
1706 /* Reset all ADC error code fields */
1707 ADC_CLEAR_ERRORCODE(hadc);
1708
1709 /* Set the DMA transfer complete callback */
1710 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
1711
1712 /* Set the DMA half transfer complete callback */
1713 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
1714
1715 /* Set the DMA error callback */
1716 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
1717
1718
1719 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
1720 /* start (in case of SW start): */
1721
1722 /* Clear regular group conversion flag and overrun flag */
1723 /* (To ensure of no unknown state from potential previous ADC */
1724 /* operations) */
1725 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
1726
1727 /* Process unlocked */
1728 /* Unlock before starting ADC conversions: in case of potential */
1729 /* interruption, to let the process to ADC IRQ Handler. */
1730 __HAL_UNLOCK(hadc);
1731
1732 /* Enable ADC overrun interrupt */
1733 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
1734
1735 /* Start the DMA channel */
1736 tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
1737
1738 /* Enable conversion of regular group. */
1739 /* If software start has been selected, conversion starts immediately. */
1740 /* If external trigger has been selected, conversion will start at next */
1741 /* trigger event. */
1742 /* Start ADC group regular conversion */
1743 LL_ADC_REG_StartConversion(hadc->Instance);
1744 }
1745 }
1746 else
1747 {
1748 tmp_hal_status = HAL_BUSY;
1749 }
1750
1751 return tmp_hal_status;
1752 }
1753
1754 /**
1755 * @brief Stop ADC conversion of regular group (and injected group in
1756 * case of auto_injection mode), disable ADC DMA transfer, disable
1757 * ADC peripheral.
1758 * @param hadc ADC handle
1759 * @retval HAL status.
1760 */
HAL_ADC_Stop_DMA(ADC_HandleTypeDef * hadc)1761 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
1762 {
1763 HAL_StatusTypeDef tmp_hal_status;
1764
1765 /* Check the parameters */
1766 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1767
1768 __HAL_LOCK(hadc);
1769
1770 /* 1. Stop potential ADC group regular conversion on going */
1771 tmp_hal_status = ADC_ConversionStop(hadc);
1772
1773 /* Disable ADC peripheral if conversions are effectively stopped */
1774 if (tmp_hal_status == HAL_OK)
1775 {
1776 /* Disable the DMA channel (in case of DMA in circular mode or stop */
1777 /* while DMA transfer is on going) */
1778 if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
1779 {
1780 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
1781
1782 /* Check if DMA channel effectively disabled */
1783 if (tmp_hal_status != HAL_OK)
1784 {
1785 /* Update ADC state machine to error */
1786 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
1787 }
1788 }
1789
1790 /* Disable ADC overrun interrupt */
1791 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
1792
1793 /* 2. Disable the ADC peripheral */
1794 /* Update "tmp_hal_status" only if DMA channel disabling passed, */
1795 /* to keep in memory a potential failing status. */
1796 if (tmp_hal_status == HAL_OK)
1797 {
1798 tmp_hal_status = ADC_Disable(hadc);
1799 }
1800 else
1801 {
1802 (void)ADC_Disable(hadc);
1803 }
1804
1805 /* Check if ADC is effectively disabled */
1806 if (tmp_hal_status == HAL_OK)
1807 {
1808 /* Set ADC state */
1809 ADC_STATE_CLR_SET(hadc->State,
1810 HAL_ADC_STATE_REG_BUSY,
1811 HAL_ADC_STATE_READY);
1812 }
1813
1814 /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */
1815 CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN);
1816 }
1817
1818 __HAL_UNLOCK(hadc);
1819
1820 return tmp_hal_status;
1821 }
1822
1823 /**
1824 * @brief Get ADC regular group conversion result.
1825 * @note Reading register DR automatically clears ADC flag EOC
1826 * (ADC group regular end of unitary conversion).
1827 * @note This function does not clear ADC flag EOS
1828 * (ADC group regular end of sequence conversion).
1829 * Occurrence of flag EOS rising:
1830 * - If sequencer is composed of 1 rank, flag EOS is equivalent
1831 * to flag EOC.
1832 * - If sequencer is composed of several ranks, during the scan
1833 * sequence flag EOC only is raised, at the end of the scan sequence
1834 * both flags EOC and EOS are raised.
1835 * To clear this flag, either use function:
1836 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
1837 * model polling: @ref HAL_ADC_PollForConversion()
1838 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
1839 * @param hadc ADC handle
1840 * @retval ADC group regular conversion data
1841 */
HAL_ADC_GetValue(const ADC_HandleTypeDef * hadc)1842 uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc)
1843 {
1844 /* Check the parameters */
1845 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1846
1847 /* Note: EOC flag is not cleared here by software because automatically */
1848 /* cleared by hardware when reading register DR. */
1849
1850 /* Return ADC converted value */
1851 return hadc->Instance->DR;
1852 }
1853
1854 /**
1855 * @brief Handle ADC interrupt request.
1856 * @param hadc ADC handle
1857 * @retval None
1858 */
HAL_ADC_IRQHandler(ADC_HandleTypeDef * hadc)1859 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
1860 {
1861 uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */
1862 uint32_t tmp_isr = hadc->Instance->ISR;
1863 uint32_t tmp_ier = hadc->Instance->IER;
1864
1865 /* Check the parameters */
1866 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1867 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
1868
1869 /* ========== Check End of Sampling flag for ADC group regular ========== */
1870 if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
1871 {
1872 /* Update state machine on end of sampling status if not in error state */
1873 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
1874 {
1875 /* Set ADC state */
1876 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
1877 }
1878
1879 /* End Of Sampling callback */
1880 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1881 hadc->EndOfSamplingCallback(hadc);
1882 #else
1883 HAL_ADCEx_EndOfSamplingCallback(hadc);
1884 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1885
1886 /* Clear regular group conversion flag */
1887 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
1888 }
1889
1890 /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */
1891 if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
1892 (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
1893 {
1894 /* Update state machine on conversion status if not in error state */
1895 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
1896 {
1897 /* Set ADC state */
1898 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
1899 }
1900
1901 /* Determine whether any further conversion upcoming on group regular */
1902 /* by external trigger, continuous mode or scan sequence on going */
1903 /* to disable interruption. */
1904 if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
1905 && (hadc->Init.ContinuousConvMode == DISABLE)
1906 )
1907 {
1908 /* If End of Sequence is reached, disable interrupts */
1909 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
1910 {
1911 /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
1912 /* ADSTART==0 (no conversion on going) */
1913 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
1914 {
1915 /* Disable ADC end of single conversion interrupt on group regular */
1916 /* Note: Overrun interrupt was enabled with EOC interrupt in */
1917 /* HAL_Start_IT(), but is not disabled here because can be used */
1918 /* by overrun IRQ process below. */
1919 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
1920
1921 /* Set ADC state */
1922 ADC_STATE_CLR_SET(hadc->State,
1923 HAL_ADC_STATE_REG_BUSY,
1924 HAL_ADC_STATE_READY);
1925 }
1926 else
1927 {
1928 /* Change ADC state to error state */
1929 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1930
1931 /* Set ADC error code to ADC peripheral internal error */
1932 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
1933 }
1934 }
1935 }
1936
1937 /* Conversion complete callback */
1938 /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */
1939 /* to determine if conversion has been triggered from EOC or EOS, */
1940 /* possibility to use: */
1941 /* " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
1942 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1943 hadc->ConvCpltCallback(hadc);
1944 #else
1945 HAL_ADC_ConvCpltCallback(hadc);
1946 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1947
1948 /* Clear regular group conversion flag */
1949 /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
1950 /* conversion flags clear induces the release of the preserved data.*/
1951 /* Therefore, if the preserved data value is needed, it must be */
1952 /* read preliminarily into HAL_ADC_ConvCpltCallback(). */
1953 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
1954 }
1955
1956 /* ========== Check Analog watchdog 1 flag ========== */
1957 if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
1958 {
1959 /* Set ADC state */
1960 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
1961
1962 /* Level out of window 1 callback */
1963 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1964 hadc->LevelOutOfWindowCallback(hadc);
1965 #else
1966 HAL_ADC_LevelOutOfWindowCallback(hadc);
1967 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1968
1969 /* Clear ADC analog watchdog flag */
1970 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
1971 }
1972
1973 /* ========== Check analog watchdog 2 flag ========== */
1974 if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
1975 {
1976 /* Set ADC state */
1977 SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
1978
1979 /* Level out of window 2 callback */
1980 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1981 hadc->LevelOutOfWindow2Callback(hadc);
1982 #else
1983 HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
1984 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1985
1986 /* Clear ADC analog watchdog flag */
1987 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
1988 }
1989
1990 /* ========== Check analog watchdog 3 flag ========== */
1991 if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
1992 {
1993 /* Set ADC state */
1994 SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
1995
1996 /* Level out of window 3 callback */
1997 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1998 hadc->LevelOutOfWindow3Callback(hadc);
1999 #else
2000 HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
2001 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2002
2003 /* Clear ADC analog watchdog flag */
2004 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
2005 }
2006
2007 /* ========== Check Overrun flag ========== */
2008 if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
2009 {
2010 /* If overrun is set to overwrite previous data (default setting), */
2011 /* overrun event is not considered as an error. */
2012 /* (cf ref manual "Managing conversions without using the DMA and without */
2013 /* overrun ") */
2014 /* Exception for usage with DMA overrun event always considered as an */
2015 /* error. */
2016 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
2017 {
2018 overrun_error = 1UL;
2019 }
2020 else
2021 {
2022 /* Check DMA configuration */
2023 if (LL_ADC_REG_GetDMATransfer(hadc->Instance) != LL_ADC_REG_DMA_TRANSFER_NONE)
2024 {
2025 overrun_error = 1UL;
2026 }
2027 }
2028
2029 if (overrun_error == 1UL)
2030 {
2031 /* Change ADC state to error state */
2032 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
2033
2034 /* Set ADC error code to overrun */
2035 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
2036
2037 /* Error callback */
2038 /* Note: In case of overrun, ADC conversion data is preserved until */
2039 /* flag OVR is reset. */
2040 /* Therefore, old ADC conversion data can be retrieved in */
2041 /* function "HAL_ADC_ErrorCallback()". */
2042 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2043 hadc->ErrorCallback(hadc);
2044 #else
2045 HAL_ADC_ErrorCallback(hadc);
2046 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2047 }
2048
2049 /* Clear ADC overrun flag */
2050 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
2051 }
2052
2053 /* ========== Check channel configuration ready flag ========== */
2054 if (((tmp_isr & ADC_FLAG_CCRDY) == ADC_FLAG_CCRDY) && ((tmp_ier & ADC_IT_CCRDY) == ADC_IT_CCRDY))
2055 {
2056 /* Channel configuration ready callback */
2057 HAL_ADCEx_ChannelConfigReadyCallback(hadc);
2058
2059 /* Clear ADC analog watchdog flag */
2060 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_CCRDY);
2061 }
2062 }
2063
2064 /**
2065 * @brief Conversion complete callback in non-blocking mode.
2066 * @param hadc ADC handle
2067 * @retval None
2068 */
HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef * hadc)2069 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
2070 {
2071 /* Prevent unused argument(s) compilation warning */
2072 UNUSED(hadc);
2073
2074 /* NOTE : This function should not be modified. When the callback is needed,
2075 function HAL_ADC_ConvCpltCallback must be implemented in the user file.
2076 */
2077 }
2078
2079 /**
2080 * @brief Conversion DMA half-transfer callback in non-blocking mode.
2081 * @param hadc ADC handle
2082 * @retval None
2083 */
HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef * hadc)2084 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
2085 {
2086 /* Prevent unused argument(s) compilation warning */
2087 UNUSED(hadc);
2088
2089 /* NOTE : This function should not be modified. When the callback is needed,
2090 function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
2091 */
2092 }
2093
2094 /**
2095 * @brief Analog watchdog 1 callback in non-blocking mode.
2096 * @param hadc ADC handle
2097 * @retval None
2098 */
HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef * hadc)2099 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
2100 {
2101 /* Prevent unused argument(s) compilation warning */
2102 UNUSED(hadc);
2103
2104 /* NOTE : This function should not be modified. When the callback is needed,
2105 function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
2106 */
2107 }
2108
2109 /**
2110 * @brief ADC error callback in non-blocking mode
2111 * (ADC conversion with interruption or transfer by DMA).
2112 * @note In case of error due to overrun when using ADC with DMA transfer
2113 * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
2114 * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
2115 * - If needed, restart a new ADC conversion using function
2116 * "HAL_ADC_Start_DMA()"
2117 * (this function is also clearing overrun flag)
2118 * @param hadc ADC handle
2119 * @retval None
2120 */
HAL_ADC_ErrorCallback(ADC_HandleTypeDef * hadc)2121 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
2122 {
2123 /* Prevent unused argument(s) compilation warning */
2124 UNUSED(hadc);
2125
2126 /* NOTE : This function should not be modified. When the callback is needed,
2127 function HAL_ADC_ErrorCallback must be implemented in the user file.
2128 */
2129 }
2130
2131 /**
2132 * @}
2133 */
2134
2135 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
2136 * @brief Peripheral Control functions
2137 *
2138 @verbatim
2139 ===============================================================================
2140 ##### Peripheral Control functions #####
2141 ===============================================================================
2142 [..] This section provides functions allowing to:
2143 (+) Configure channels on regular group
2144 (+) Configure the analog watchdog
2145
2146 @endverbatim
2147 * @{
2148 */
2149
2150 /**
2151 * @brief Configure a channel to be assigned to ADC group regular.
2152 * @note In case of usage of internal measurement channels:
2153 * Vbat/VrefInt/TempSensor.
2154 * These internal paths can be disabled using function
2155 * HAL_ADC_DeInit().
2156 * @note Possibility to update parameters on the fly:
2157 * This function initializes channel into ADC group regular,
2158 * following calls to this function can be used to reconfigure
2159 * some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
2160 * without resetting the ADC.
2161 * The setting of these parameters is conditioned to ADC state:
2162 * Refer to comments of structure "ADC_ChannelConfTypeDef".
2163 * @param hadc ADC handle
2164 * @param pConfig Structure of ADC channel assigned to ADC group regular.
2165 * @retval HAL status
2166 */
HAL_ADC_ConfigChannel(ADC_HandleTypeDef * hadc,const ADC_ChannelConfTypeDef * pConfig)2167 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig)
2168 {
2169 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
2170 uint32_t tmp_config_internal_channel;
2171 __IO uint32_t wait_loop_index = 0UL;
2172
2173 /* Check the parameters */
2174 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2175 assert_param(IS_ADC_CHANNEL(pConfig->Channel));
2176 assert_param(IS_ADC_SAMPLING_TIME_COMMON(pConfig->SamplingTime));
2177
2178 if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
2179 (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD))
2180 {
2181 assert_param(IS_ADC_REGULAR_RANK_SEQ_FIXED(pConfig->Rank));
2182 }
2183 else
2184 {
2185 assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
2186
2187 assert_param(IS_ADC_REGULAR_RANK(pConfig->Rank));
2188 }
2189
2190 __HAL_LOCK(hadc);
2191
2192 /* Parameters update conditioned to ADC state: */
2193 /* Parameters that can be updated when ADC is disabled or enabled without */
2194 /* conversion on going on regular group: */
2195 /* - Channel number */
2196 /* - Channel sampling time */
2197 /* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */
2198 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
2199 {
2200 /* Configure channel: depending on rank setting, add it or remove it from */
2201 /* ADC sequencer. */
2202 /* If sequencer set to not fully configurable with channel rank set to */
2203 /* none, remove the channel from the sequencer. */
2204 /* Otherwise (sequencer set to fully configurable or to to not fully */
2205 /* configurable with channel rank to be set), configure the selected */
2206 /* channel. */
2207 if (pConfig->Rank != ADC_RANK_NONE)
2208 {
2209 /* Regular sequence configuration */
2210 /* Note: ADC channel configuration requires few ADC clock cycles */
2211 /* to be ready. Processing of ADC settings in this function */
2212 /* induce that a specific wait time is not necessary. */
2213 /* For more details on ADC channel configuration ready, */
2214 /* refer to function "LL_ADC_IsActiveFlag_CCRDY()". */
2215 if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
2216 (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD))
2217 {
2218 /* Sequencer set to not fully configurable: */
2219 /* Set the channel by enabling the corresponding bitfield. */
2220 LL_ADC_REG_SetSequencerChAdd(hadc->Instance, pConfig->Channel);
2221 }
2222 else
2223 {
2224 /* Sequencer set to fully configurable: */
2225 /* Set the channel by entering it into the selected rank. */
2226
2227 /* Memorize the channel set into variable in HAL ADC handle */
2228 MODIFY_REG(hadc->ADCGroupRegularSequencerRanks,
2229 ADC_CHSELR_SQ1 << (pConfig->Rank & 0x1FUL),
2230 __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel) << (pConfig->Rank & 0x1FUL));
2231
2232 /* If the selected rank is below ADC group regular sequencer length, */
2233 /* apply the configuration in ADC register. */
2234 /* Note: Otherwise, configuration is not applied. */
2235 /* To apply it, parameter'NbrOfConversion' must be increased. */
2236 if (((pConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion)
2237 {
2238 LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel);
2239 }
2240 }
2241
2242 /* Set sampling time of the selected ADC channel */
2243 LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime);
2244
2245 /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
2246 /* internal measurement paths enable: If internal channel selected, */
2247 /* enable dedicated internal buffers and path. */
2248 /* Note: these internal measurement paths can be disabled using */
2249 /* HAL_ADC_DeInit() or removing the channel from sequencer with */
2250 /* channel configuration parameter "Rank". */
2251 if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
2252 {
2253 tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
2254
2255 /* If the requested internal measurement path has already been enabled, */
2256 /* bypass the configuration processing. */
2257 if ((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
2258 ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
2259 {
2260 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2261 LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
2262
2263 /* Delay for temperature sensor stabilization time */
2264 /* Wait loop initialization and execution */
2265 /* Note: Variable divided by 2 to compensate partially */
2266 /* CPU processing cycles, scaling in us split to not */
2267 /* exceed 32 bits register capacity and handle low frequency. */
2268 wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
2269 while (wait_loop_index != 0UL)
2270 {
2271 wait_loop_index--;
2272 }
2273 }
2274 else if ((pConfig->Channel == ADC_CHANNEL_VBAT)
2275 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
2276 {
2277 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2278 LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
2279 }
2280 else if ((pConfig->Channel == ADC_CHANNEL_VREFINT) &&
2281 ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
2282 {
2283 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2284 LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
2285 }
2286 else
2287 {
2288 /* nothing to do */
2289 }
2290 }
2291 }
2292 else
2293 {
2294 /* Regular sequencer configuration */
2295 /* Note: Case of sequencer set to fully configurable: */
2296 /* Sequencer rank cannot be disabled, only affected to */
2297 /* another channel. */
2298 /* To remove a rank, use parameter 'NbrOfConversion". */
2299 if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
2300 (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD))
2301 {
2302 /* Sequencer set to not fully configurable: */
2303 /* Reset the channel by disabling the corresponding bitfield. */
2304 LL_ADC_REG_SetSequencerChRem(hadc->Instance, pConfig->Channel);
2305 }
2306
2307 /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */
2308 /* If internal channel selected, enable dedicated internal buffers and */
2309 /* paths. */
2310 if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
2311 {
2312 tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
2313
2314 if (pConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
2315 {
2316 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2317 ~LL_ADC_PATH_INTERNAL_TEMPSENSOR & tmp_config_internal_channel);
2318 }
2319 else if (pConfig->Channel == ADC_CHANNEL_VBAT)
2320 {
2321 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2322 ~LL_ADC_PATH_INTERNAL_VBAT & tmp_config_internal_channel);
2323 }
2324 else if (pConfig->Channel == ADC_CHANNEL_VREFINT)
2325 {
2326 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2327 ~LL_ADC_PATH_INTERNAL_VREFINT & tmp_config_internal_channel);
2328 }
2329 else
2330 {
2331 /* nothing to do */
2332 }
2333 }
2334 }
2335 }
2336
2337 /* If a conversion is on going on regular group, no update on regular */
2338 /* channel could be done on neither of the channel configuration structure */
2339 /* parameters. */
2340 else
2341 {
2342 /* Update ADC state machine to error */
2343 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
2344
2345 tmp_hal_status = HAL_ERROR;
2346 }
2347
2348 __HAL_UNLOCK(hadc);
2349
2350 return tmp_hal_status;
2351 }
2352
2353 /**
2354 * @brief Configure the analog watchdog.
2355 * @note Possibility to update parameters on the fly:
2356 * This function initializes the selected analog watchdog, successive
2357 * calls to this function can be used to reconfigure some parameters
2358 * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
2359 * the ADC.
2360 * The setting of these parameters is conditioned to ADC state.
2361 * For parameters constraints, see comments of structure
2362 * "ADC_AnalogWDGConfTypeDef".
2363 * @note On this STM32 series, analog watchdog thresholds can be modified
2364 * while ADC conversion is on going.
2365 * In this case, some constraints must be taken into account:
2366 * the programmed threshold values are effective from the next
2367 * ADC EOC (end of unitary conversion).
2368 * Considering that registers write delay may happen due to
2369 * bus activity, this might cause an uncertainty on the
2370 * effective timing of the new programmed threshold values.
2371 * @param hadc ADC handle
2372 * @param pAnalogWDGConfig Structure of ADC analog watchdog configuration
2373 * @retval HAL status
2374 */
HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef * hadc,const ADC_AnalogWDGConfTypeDef * pAnalogWDGConfig)2375 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig)
2376 {
2377 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
2378 uint32_t tmp_awd_high_threshold_shifted;
2379 uint32_t tmp_awd_low_threshold_shifted;
2380 uint32_t backup_setting_adc_enable_state = 0UL;
2381
2382 /* Check the parameters */
2383 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2384 assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(pAnalogWDGConfig->WatchdogNumber));
2385 assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(pAnalogWDGConfig->WatchdogMode));
2386 assert_param(IS_FUNCTIONAL_STATE(pAnalogWDGConfig->ITMode));
2387
2388 if (pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)
2389 {
2390 assert_param(IS_ADC_CHANNEL(pAnalogWDGConfig->Channel));
2391 }
2392
2393 /* Verify thresholds range */
2394 if (hadc->Init.OversamplingMode == ENABLE)
2395 {
2396 /* Case of oversampling enabled: depending on ratio and shift configuration,
2397 analog watchdog thresholds can be higher than ADC resolution.
2398 Verify if thresholds are within maximum thresholds range. */
2399 assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->HighThreshold));
2400 assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->LowThreshold));
2401 }
2402 else
2403 {
2404 /* Verify if thresholds are within the selected ADC resolution */
2405 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->HighThreshold));
2406 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->LowThreshold));
2407 }
2408
2409 __HAL_LOCK(hadc);
2410
2411 /* Parameters update conditioned to ADC state: */
2412 /* Parameters that can be updated when ADC is disabled or enabled without */
2413 /* conversion on going on ADC group regular: */
2414 /* - Analog watchdog channels */
2415 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
2416 {
2417 /* Analog watchdog configuration */
2418 if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
2419 {
2420 /* Constraint of ADC on this STM32 series: ADC must be disable
2421 to modify bitfields of register ADC_CFGR1 */
2422 if (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
2423 {
2424 backup_setting_adc_enable_state = 1UL;
2425 tmp_hal_status = ADC_Disable(hadc);
2426 }
2427
2428 /* Configuration of analog watchdog: */
2429 /* - Set the analog watchdog enable mode: one or overall group of */
2430 /* channels. */
2431 switch (pAnalogWDGConfig->WatchdogMode)
2432 {
2433 case ADC_ANALOGWATCHDOG_SINGLE_REG:
2434 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
2435 __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
2436 LL_ADC_GROUP_REGULAR));
2437 break;
2438
2439 case ADC_ANALOGWATCHDOG_ALL_REG:
2440 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG);
2441 break;
2442
2443 default: /* ADC_ANALOGWATCHDOG_NONE */
2444 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE);
2445 break;
2446 }
2447
2448 if (backup_setting_adc_enable_state == 1UL)
2449 {
2450 if (tmp_hal_status == HAL_OK)
2451 {
2452 tmp_hal_status = ADC_Enable(hadc);
2453 }
2454 }
2455
2456 /* Update state, clear previous result related to AWD1 */
2457 CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
2458
2459 /* Clear flag ADC analog watchdog */
2460 /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
2461 /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
2462 /* (in case left enabled by previous ADC operations). */
2463 LL_ADC_ClearFlag_AWD1(hadc->Instance);
2464
2465 /* Configure ADC analog watchdog interrupt */
2466 if (pAnalogWDGConfig->ITMode == ENABLE)
2467 {
2468 LL_ADC_EnableIT_AWD1(hadc->Instance);
2469 }
2470 else
2471 {
2472 LL_ADC_DisableIT_AWD1(hadc->Instance);
2473 }
2474 }
2475 /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
2476 else
2477 {
2478 switch (pAnalogWDGConfig->WatchdogMode)
2479 {
2480 case ADC_ANALOGWATCHDOG_SINGLE_REG:
2481 /* Update AWD by bitfield to keep the possibility to monitor */
2482 /* several channels by successive calls of this function. */
2483 if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
2484 {
2485 SET_BIT(hadc->Instance->AWD2CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel)));
2486 }
2487 else
2488 {
2489 SET_BIT(hadc->Instance->AWD3CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel)));
2490 }
2491 break;
2492
2493 case ADC_ANALOGWATCHDOG_ALL_REG:
2494 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance,
2495 pAnalogWDGConfig->WatchdogNumber,
2496 LL_ADC_AWD_ALL_CHANNELS_REG);
2497 break;
2498
2499 default: /* ADC_ANALOGWATCHDOG_NONE */
2500 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
2501 break;
2502 }
2503
2504 if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
2505 {
2506 /* Update state, clear previous result related to AWD2 */
2507 CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
2508
2509 /* Clear flag ADC analog watchdog */
2510 /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
2511 /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
2512 /* (in case left enabled by previous ADC operations). */
2513 LL_ADC_ClearFlag_AWD2(hadc->Instance);
2514
2515 /* Configure ADC analog watchdog interrupt */
2516 if (pAnalogWDGConfig->ITMode == ENABLE)
2517 {
2518 LL_ADC_EnableIT_AWD2(hadc->Instance);
2519 }
2520 else
2521 {
2522 LL_ADC_DisableIT_AWD2(hadc->Instance);
2523 }
2524 }
2525 /* (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
2526 else
2527 {
2528 /* Update state, clear previous result related to AWD3 */
2529 CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
2530
2531 /* Clear flag ADC analog watchdog */
2532 /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
2533 /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
2534 /* (in case left enabled by previous ADC operations). */
2535 LL_ADC_ClearFlag_AWD3(hadc->Instance);
2536
2537 /* Configure ADC analog watchdog interrupt */
2538 if (pAnalogWDGConfig->ITMode == ENABLE)
2539 {
2540 LL_ADC_EnableIT_AWD3(hadc->Instance);
2541 }
2542 else
2543 {
2544 LL_ADC_DisableIT_AWD3(hadc->Instance);
2545 }
2546 }
2547 }
2548
2549 }
2550
2551 /* Analog watchdog thresholds configuration */
2552 if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
2553 {
2554 /* Shift the offset with respect to the selected ADC resolution: */
2555 /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
2556 /* are set to 0. */
2557 tmp_awd_high_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold);
2558 tmp_awd_low_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold);
2559 }
2560 /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
2561 else
2562 {
2563 /* No need to shift the offset with respect to the selected ADC resolution: */
2564 /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
2565 /* are set to 0. */
2566 tmp_awd_high_threshold_shifted = pAnalogWDGConfig->HighThreshold;
2567 tmp_awd_low_threshold_shifted = pAnalogWDGConfig->LowThreshold;
2568 }
2569
2570 /* Set ADC analog watchdog thresholds value of both thresholds high and low */
2571 LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, tmp_awd_high_threshold_shifted,
2572 tmp_awd_low_threshold_shifted);
2573
2574 __HAL_UNLOCK(hadc);
2575
2576 return tmp_hal_status;
2577 }
2578
2579
2580 /**
2581 * @}
2582 */
2583
2584 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
2585 * @brief ADC Peripheral State functions
2586 *
2587 @verbatim
2588 ===============================================================================
2589 ##### Peripheral state and errors functions #####
2590 ===============================================================================
2591 [..]
2592 This subsection provides functions to get in run-time the status of the
2593 peripheral.
2594 (+) Check the ADC state
2595 (+) Check the ADC error code
2596
2597 @endverbatim
2598 * @{
2599 */
2600
2601 /**
2602 * @brief Return the ADC handle state.
2603 * @note ADC state machine is managed by bitfields, ADC status must be
2604 * compared with states bits.
2605 * For example:
2606 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
2607 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
2608 * @param hadc ADC handle
2609 * @retval ADC handle state (bitfield on 32 bits)
2610 */
HAL_ADC_GetState(const ADC_HandleTypeDef * hadc)2611 uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc)
2612 {
2613 /* Check the parameters */
2614 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2615
2616 /* Return ADC handle state */
2617 return hadc->State;
2618 }
2619
2620 /**
2621 * @brief Return the ADC error code.
2622 * @param hadc ADC handle
2623 * @retval ADC error code (bitfield on 32 bits)
2624 */
HAL_ADC_GetError(const ADC_HandleTypeDef * hadc)2625 uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc)
2626 {
2627 /* Check the parameters */
2628 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2629
2630 return hadc->ErrorCode;
2631 }
2632
2633 /**
2634 * @}
2635 */
2636
2637 /**
2638 * @}
2639 */
2640
2641 /** @defgroup ADC_Private_Functions ADC Private Functions
2642 * @{
2643 */
2644
2645 /**
2646 * @brief Stop ADC conversion.
2647 * @note Prerequisite condition to use this function: ADC conversions must be
2648 * stopped to disable the ADC.
2649 * @param hadc ADC handle
2650 * @retval HAL status.
2651 */
ADC_ConversionStop(ADC_HandleTypeDef * hadc)2652 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc)
2653 {
2654 uint32_t tickstart;
2655
2656 /* Check the parameters */
2657 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2658
2659 /* Verification if ADC is not already stopped on regular group to bypass */
2660 /* this function if not needed. */
2661 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
2662 {
2663 /* Stop potential conversion on going on regular group */
2664 /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
2665 if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
2666 {
2667 /* Stop ADC group regular conversion */
2668 LL_ADC_REG_StopConversion(hadc->Instance);
2669 }
2670
2671 /* Wait for conversion effectively stopped */
2672 /* Get tick count */
2673 tickstart = HAL_GetTick();
2674
2675 while ((hadc->Instance->CR & ADC_CR_ADSTART) != 0UL)
2676 {
2677 if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
2678 {
2679 /* New check to avoid false timeout detection in case of preemption */
2680 if ((hadc->Instance->CR & ADC_CR_ADSTART) != 0UL)
2681 {
2682 /* Update ADC state machine to error */
2683 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
2684
2685 /* Set ADC error code to ADC peripheral internal error */
2686 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
2687
2688 return HAL_ERROR;
2689 }
2690 }
2691 }
2692
2693 }
2694
2695 /* Return HAL status */
2696 return HAL_OK;
2697 }
2698
2699 /**
2700 * @brief Enable the selected ADC.
2701 * @note Prerequisite condition to use this function: ADC must be disabled
2702 * and voltage regulator must be enabled (done into HAL_ADC_Init()).
2703 * @param hadc ADC handle
2704 * @retval HAL status.
2705 */
ADC_Enable(ADC_HandleTypeDef * hadc)2706 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
2707 {
2708 uint32_t tickstart;
2709 __IO uint32_t wait_loop_index = 0UL;
2710
2711 /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
2712 /* enabling phase not yet completed: flag ADC ready not yet set). */
2713 /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
2714 /* causes: ADC clock not running, ...). */
2715 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
2716 {
2717 /* Check if conditions to enable the ADC are fulfilled */
2718 if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
2719 {
2720 /* Update ADC state machine to error */
2721 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
2722
2723 /* Set ADC error code to ADC peripheral internal error */
2724 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
2725
2726 return HAL_ERROR;
2727 }
2728
2729 /* Enable the ADC peripheral */
2730 LL_ADC_Enable(hadc->Instance);
2731
2732 if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2733 != 0UL)
2734 {
2735 /* Delay for temperature sensor buffer stabilization time */
2736 /* Wait loop initialization and execution */
2737 /* Note: Variable divided by 2 to compensate partially */
2738 /* CPU processing cycles, scaling in us split to not */
2739 /* exceed 32 bits register capacity and handle low frequency. */
2740 wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US / 10UL)
2741 * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
2742 while (wait_loop_index != 0UL)
2743 {
2744 wait_loop_index--;
2745 }
2746 }
2747
2748 /* If low power mode AutoPowerOff is enabled, power-on/off phases are */
2749 /* performed automatically by hardware and flag ADC ready is not set. */
2750 if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
2751 {
2752 /* Wait for ADC effectively enabled */
2753 tickstart = HAL_GetTick();
2754
2755 while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
2756 {
2757 /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
2758 has been cleared (after a calibration), ADEN bit is reset by the
2759 calibration logic.
2760 The workaround is to continue setting ADEN until ADRDY is becomes 1.
2761 Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
2762 4 ADC clock cycle duration */
2763 /* Note: Test of ADC enabled required due to hardware constraint to */
2764 /* not enable ADC if already enabled. */
2765 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
2766 {
2767 LL_ADC_Enable(hadc->Instance);
2768 }
2769
2770 if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
2771 {
2772 /* New check to avoid false timeout detection in case of preemption */
2773 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
2774 {
2775 /* Update ADC state machine to error */
2776 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
2777
2778 /* Set ADC error code to ADC peripheral internal error */
2779 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
2780
2781 return HAL_ERROR;
2782 }
2783 }
2784 }
2785 }
2786 }
2787
2788 /* Return HAL status */
2789 return HAL_OK;
2790 }
2791
2792 /**
2793 * @brief Disable the selected ADC.
2794 * @note Prerequisite condition to use this function: ADC conversions must be
2795 * stopped.
2796 * @param hadc ADC handle
2797 * @retval HAL status.
2798 */
ADC_Disable(ADC_HandleTypeDef * hadc)2799 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
2800 {
2801 uint32_t tickstart;
2802 const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
2803
2804 /* Verification if ADC is not already disabled: */
2805 /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
2806 /* disabled. */
2807 if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
2808 && (tmp_adc_is_disable_on_going == 0UL)
2809 )
2810 {
2811 /* Check if conditions to disable the ADC are fulfilled */
2812 if ((hadc->Instance->CR & (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
2813 {
2814 /* Disable the ADC peripheral */
2815 LL_ADC_Disable(hadc->Instance);
2816 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
2817 }
2818 else
2819 {
2820 /* Update ADC state machine to error */
2821 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
2822
2823 /* Set ADC error code to ADC peripheral internal error */
2824 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
2825
2826 return HAL_ERROR;
2827 }
2828
2829 /* Wait for ADC effectively disabled */
2830 /* Get tick count */
2831 tickstart = HAL_GetTick();
2832
2833 while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
2834 {
2835 if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
2836 {
2837 /* New check to avoid false timeout detection in case of preemption */
2838 if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
2839 {
2840 /* Update ADC state machine to error */
2841 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
2842
2843 /* Set ADC error code to ADC peripheral internal error */
2844 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
2845
2846 return HAL_ERROR;
2847 }
2848 }
2849 }
2850 }
2851
2852 /* Return HAL status */
2853 return HAL_OK;
2854 }
2855
2856 /**
2857 * @brief DMA transfer complete callback.
2858 * @param hdma pointer to DMA handle.
2859 * @retval None
2860 */
ADC_DMAConvCplt(DMA_HandleTypeDef * hdma)2861 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
2862 {
2863 /* Retrieve ADC handle corresponding to current DMA handle */
2864 ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2865
2866 /* Update state machine on conversion status if not in error state */
2867 if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL)
2868 {
2869 /* Set ADC state */
2870 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
2871
2872 /* Determine whether any further conversion upcoming on group regular */
2873 /* by external trigger, continuous mode or scan sequence on going */
2874 /* to disable interruption. */
2875 if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
2876 && (hadc->Init.ContinuousConvMode == DISABLE)
2877 )
2878 {
2879 /* If End of Sequence is reached, disable interrupts */
2880 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
2881 {
2882 /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
2883 /* ADSTART==0 (no conversion on going) */
2884 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
2885 {
2886 /* Disable ADC end of single conversion interrupt on group regular */
2887 /* Note: Overrun interrupt was enabled with EOC interrupt in */
2888 /* HAL_Start_IT(), but is not disabled here because can be used */
2889 /* by overrun IRQ process below. */
2890 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
2891
2892 /* Set ADC state */
2893 ADC_STATE_CLR_SET(hadc->State,
2894 HAL_ADC_STATE_REG_BUSY,
2895 HAL_ADC_STATE_READY);
2896 }
2897 else
2898 {
2899 /* Change ADC state to error state */
2900 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
2901
2902 /* Set ADC error code to ADC peripheral internal error */
2903 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
2904 }
2905 }
2906 }
2907
2908 /* Conversion complete callback */
2909 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2910 hadc->ConvCpltCallback(hadc);
2911 #else
2912 HAL_ADC_ConvCpltCallback(hadc);
2913 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2914 }
2915 else /* DMA and-or internal error occurred */
2916 {
2917 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
2918 {
2919 /* Call HAL ADC Error Callback function */
2920 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2921 hadc->ErrorCallback(hadc);
2922 #else
2923 HAL_ADC_ErrorCallback(hadc);
2924 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2925 }
2926 else
2927 {
2928 /* Call ADC DMA error callback */
2929 hadc->DMA_Handle->XferErrorCallback(hdma);
2930 }
2931 }
2932 }
2933
2934 /**
2935 * @brief DMA half transfer complete callback.
2936 * @param hdma pointer to DMA handle.
2937 * @retval None
2938 */
ADC_DMAHalfConvCplt(DMA_HandleTypeDef * hdma)2939 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
2940 {
2941 /* Retrieve ADC handle corresponding to current DMA handle */
2942 ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2943
2944 /* Half conversion callback */
2945 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2946 hadc->ConvHalfCpltCallback(hadc);
2947 #else
2948 HAL_ADC_ConvHalfCpltCallback(hadc);
2949 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2950 }
2951
2952 /**
2953 * @brief DMA error callback.
2954 * @param hdma pointer to DMA handle.
2955 * @retval None
2956 */
ADC_DMAError(DMA_HandleTypeDef * hdma)2957 static void ADC_DMAError(DMA_HandleTypeDef *hdma)
2958 {
2959 /* Retrieve ADC handle corresponding to current DMA handle */
2960 ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2961
2962 /* Set ADC state */
2963 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
2964
2965 /* Set ADC error code to DMA error */
2966 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
2967
2968 /* Error callback */
2969 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2970 hadc->ErrorCallback(hadc);
2971 #else
2972 HAL_ADC_ErrorCallback(hadc);
2973 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2974 }
2975
2976 /**
2977 * @}
2978 */
2979
2980 #endif /* HAL_ADC_MODULE_ENABLED */
2981 /**
2982 * @}
2983 */
2984
2985 /**
2986 * @}
2987 */
2988
