1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_rcc.c
4 * @author MCD Application Team
5 * @brief RCC LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 ******************************************************************************
16 */
17 #if defined(USE_FULL_LL_DRIVER)
18
19 /* Includes ------------------------------------------------------------------*/
20 #include "stm32f7xx_ll_rcc.h"
21 #ifdef USE_FULL_ASSERT
22 #include "stm32_assert.h"
23 #else
24 #define assert_param(expr) ((void)0U)
25 #endif
26
27 /** @addtogroup STM32F7xx_LL_Driver
28 * @{
29 */
30
31 #if defined(RCC)
32
33 /** @addtogroup RCC_LL
34 * @{
35 */
36
37 /* Private types -------------------------------------------------------------*/
38 /* Private variables ---------------------------------------------------------*/
39 /* Private constants ---------------------------------------------------------*/
40 /* Private macros ------------------------------------------------------------*/
41 /** @addtogroup RCC_LL_Private_Macros
42 * @{
43 */
44 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
45 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
46 || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE) \
47 || ((__VALUE__) == LL_RCC_USART6_CLKSOURCE))
48
49 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
50 || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE) \
51 || ((__VALUE__) == LL_RCC_UART7_CLKSOURCE) \
52 || ((__VALUE__) == LL_RCC_UART8_CLKSOURCE))
53
54 #if defined(I2C4)
55 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
56 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
57 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \
58 || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
59 #else
60 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
61 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
62 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
63 #endif /* I2C4 */
64
65 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE))
66
67 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
68 || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
69
70 #if defined(SDMMC2)
71 #define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE) \
72 || ((__VALUE__) == LL_RCC_SDMMC2_CLKSOURCE))
73 #else
74 #define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE))
75 #endif /* SDMMC2 */
76
77 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
78
79 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
80
81 #if defined(DFSDM1_Channel0)
82 #define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
83
84 #define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE))
85 #endif /* DFSDM1_Channel0 */
86
87 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE))
88
89 #if defined(CEC)
90 #define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
91 #endif /* CEC */
92
93 #if defined(DSI)
94 #define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DSI_CLKSOURCE))
95 #endif /* DSI */
96
97 #if defined(LTDC)
98 #define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE))
99 #endif /* LTDC */
100
101 #if defined(SPDIFRX)
102 #define IS_LL_RCC_SPDIFRX_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPDIFRX1_CLKSOURCE))
103 #endif /* SPDIFRX */
104
105 /**
106 * @}
107 */
108
109 /* Private function prototypes -----------------------------------------------*/
110 /** @defgroup RCC_LL_Private_Functions RCC Private functions
111 * @{
112 */
113 uint32_t RCC_GetSystemClockFreq(void);
114 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
115 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
116 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
117 uint32_t RCC_PLL_GetFreqDomain_SYS(void);
118 uint32_t RCC_PLL_GetFreqDomain_SAI(void);
119 uint32_t RCC_PLL_GetFreqDomain_48M(void);
120 #if defined(DSI)
121 uint32_t RCC_PLL_GetFreqDomain_DSI(void);
122 #endif /* DSI */
123 uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void);
124 uint32_t RCC_PLLSAI_GetFreqDomain_48M(void);
125 #if defined(LTDC)
126 uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void);
127 #endif /* LTDC */
128 uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);
129 uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void);
130 #if defined(SPDIFRX)
131 uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void);
132 #endif /* SPDIFRX */
133 /**
134 * @}
135 */
136
137
138 /* Exported functions --------------------------------------------------------*/
139 /** @addtogroup RCC_LL_Exported_Functions
140 * @{
141 */
142
143 /** @addtogroup RCC_LL_EF_Init
144 * @{
145 */
146
147 /**
148 * @brief Reset the RCC clock configuration to the default reset state.
149 * @note The default reset state of the clock configuration is given below:
150 * - HSI ON and used as system clock source
151 * - HSE, PLL, PLLI2S, PLLSAI OFF
152 * - AHB, APB1 and APB2 prescaler set to 1.
153 * - CSS, MCO OFF
154 * - All interrupts disabled
155 * @note This function doesn't modify the configuration of the
156 * - Peripheral clocks
157 * - LSI, LSE and RTC clocks
158 * @retval An ErrorStatus enumeration value:
159 * - SUCCESS: RCC registers are de-initialized
160 * - ERROR: not applicable
161 */
LL_RCC_DeInit(void)162 ErrorStatus LL_RCC_DeInit(void)
163 {
164 __IO uint32_t vl_mask;
165
166 /* Set HSION bit */
167 LL_RCC_HSI_Enable();
168
169 /* Wait for HSI READY bit */
170 while(LL_RCC_HSI_IsReady() != 1U)
171 {}
172
173 /* Reset CFGR register */
174 LL_RCC_WriteReg(CFGR, 0x00000000U);
175
176 /* Read CR register */
177 vl_mask = LL_RCC_ReadReg(CR);
178
179 /* Reset HSEON, HSEBYP, PLLON, CSSON, PLLI2SON and PLLSAION bits */
180 CLEAR_BIT(vl_mask, (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_PLLSAION | RCC_CR_PLLI2SON));
181
182 /* Write new value in CR register */
183 LL_RCC_WriteReg(CR, vl_mask);
184
185 /* Set HSITRIM bits to the reset value*/
186 LL_RCC_HSI_SetCalibTrimming(0x10U);
187
188 /* Wait for PLL READY bit to be reset */
189 while(LL_RCC_PLL_IsReady() != 0U)
190 {}
191
192 /* Wait for PLLI2S READY bit to be reset */
193 while(LL_RCC_PLLI2S_IsReady() != 0U)
194 {}
195
196 /* Wait for PLLSAI READY bit to be reset */
197 while(LL_RCC_PLLSAI_IsReady() != 0U)
198 {}
199
200 /* Reset PLLCFGR register */
201 LL_RCC_WriteReg(PLLCFGR, 0x24003010U);
202
203 /* Reset PLLI2SCFGR register */
204 LL_RCC_WriteReg(PLLI2SCFGR, 0x24003000U);
205
206 /* Reset PLLSAICFGR register */
207 LL_RCC_WriteReg(PLLSAICFGR, 0x24003000U);
208
209 /* Disable all interrupts */
210 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE | RCC_CIR_PLLI2SRDYIE | RCC_CIR_PLLSAIRDYIE);
211
212 /* Clear all interrupt flags */
213 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_PLLI2SRDYC | RCC_CIR_PLLSAIRDYC | RCC_CIR_CSSC);
214
215 /* Clear LSION bit */
216 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
217
218 /* Reset all CSR flags */
219 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
220
221 return SUCCESS;
222 }
223
224 /**
225 * @}
226 */
227
228 /** @addtogroup RCC_LL_EF_Get_Freq
229 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
230 * and different peripheral clocks available on the device.
231 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
232 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
233 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
234 * or HSI_VALUE(**) multiplied/divided by the PLL factors.
235 * @note (**) HSI_VALUE is a constant defined in this file (default value
236 * 16 MHz) but the real value may vary depending on the variations
237 * in voltage and temperature.
238 * @note (***) HSE_VALUE is a constant defined in this file (default value
239 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
240 * frequency of the crystal used. Otherwise, this function may
241 * have wrong result.
242 * @note The result of this function could be incorrect when using fractional
243 * value for HSE crystal.
244 * @note This function can be used by the user application to compute the
245 * baud-rate for the communication peripherals or configure other parameters.
246 * @{
247 */
248
249 /**
250 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
251 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
252 * must be called to update structure fields. Otherwise, any
253 * configuration based on this function will be incorrect.
254 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
255 * @retval None
256 */
LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef * RCC_Clocks)257 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
258 {
259 /* Get SYSCLK frequency */
260 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
261
262 /* HCLK clock frequency */
263 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
264
265 /* PCLK1 clock frequency */
266 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
267
268 /* PCLK2 clock frequency */
269 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
270 }
271
272 /**
273 * @brief Return USARTx clock frequency
274 * @param USARTxSource This parameter can be one of the following values:
275 * @arg @ref LL_RCC_USART1_CLKSOURCE
276 * @arg @ref LL_RCC_USART2_CLKSOURCE
277 * @arg @ref LL_RCC_USART3_CLKSOURCE
278 * @arg @ref LL_RCC_USART6_CLKSOURCE
279 * @retval USART clock frequency (in Hz)
280 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
281 */
LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)282 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
283 {
284 uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
285
286 /* Check parameter */
287 assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
288
289 if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
290 {
291 /* USART1CLK clock frequency */
292 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
293 {
294 case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
295 usart_frequency = RCC_GetSystemClockFreq();
296 break;
297
298 case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
299 if (LL_RCC_HSI_IsReady())
300 {
301 usart_frequency = HSI_VALUE;
302 }
303 break;
304
305 case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
306 if (LL_RCC_LSE_IsReady())
307 {
308 usart_frequency = LSE_VALUE;
309 }
310 break;
311
312 case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */
313 default:
314 usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
315 break;
316 }
317 }
318 else if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
319 {
320 /* USART2CLK clock frequency */
321 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
322 {
323 case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
324 usart_frequency = RCC_GetSystemClockFreq();
325 break;
326
327 case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
328 if (LL_RCC_HSI_IsReady())
329 {
330 usart_frequency = HSI_VALUE;
331 }
332 break;
333
334 case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
335 if (LL_RCC_LSE_IsReady())
336 {
337 usart_frequency = LSE_VALUE;
338 }
339 break;
340
341 case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
342 default:
343 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
344 break;
345 }
346 }
347 else if (USARTxSource == LL_RCC_USART6_CLKSOURCE)
348 {
349 /* USART6CLK clock frequency */
350 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
351 {
352 case LL_RCC_USART6_CLKSOURCE_SYSCLK: /* USART6 Clock is System Clock */
353 usart_frequency = RCC_GetSystemClockFreq();
354 break;
355
356 case LL_RCC_USART6_CLKSOURCE_HSI: /* USART6 Clock is HSI Osc. */
357 if (LL_RCC_HSI_IsReady())
358 {
359 usart_frequency = HSI_VALUE;
360 }
361 break;
362
363 case LL_RCC_USART6_CLKSOURCE_LSE: /* USART6 Clock is LSE Osc. */
364 if (LL_RCC_LSE_IsReady())
365 {
366 usart_frequency = LSE_VALUE;
367 }
368 break;
369
370 case LL_RCC_USART6_CLKSOURCE_PCLK2: /* USART6 Clock is PCLK2 */
371 default:
372 usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
373 break;
374 }
375 }
376 else
377 {
378 if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
379 {
380 /* USART3CLK clock frequency */
381 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
382 {
383 case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
384 usart_frequency = RCC_GetSystemClockFreq();
385 break;
386
387 case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */
388 if (LL_RCC_HSI_IsReady())
389 {
390 usart_frequency = HSI_VALUE;
391 }
392 break;
393
394 case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */
395 if (LL_RCC_LSE_IsReady())
396 {
397 usart_frequency = LSE_VALUE;
398 }
399 break;
400
401 case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */
402 default:
403 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
404 break;
405 }
406 }
407 }
408 return usart_frequency;
409 }
410
411 /**
412 * @brief Return UARTx clock frequency
413 * @param UARTxSource This parameter can be one of the following values:
414 * @arg @ref LL_RCC_UART4_CLKSOURCE
415 * @arg @ref LL_RCC_UART5_CLKSOURCE
416 * @arg @ref LL_RCC_UART7_CLKSOURCE
417 * @arg @ref LL_RCC_UART8_CLKSOURCE
418 * @retval UART clock frequency (in Hz)
419 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
420 */
LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)421 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
422 {
423 uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
424
425 /* Check parameter */
426 assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
427
428 if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
429 {
430 /* UART4CLK clock frequency */
431 switch (LL_RCC_GetUARTClockSource(UARTxSource))
432 {
433 case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */
434 uart_frequency = RCC_GetSystemClockFreq();
435 break;
436
437 case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */
438 if (LL_RCC_HSI_IsReady())
439 {
440 uart_frequency = HSI_VALUE;
441 }
442 break;
443
444 case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */
445 if (LL_RCC_LSE_IsReady())
446 {
447 uart_frequency = LSE_VALUE;
448 }
449 break;
450
451 case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */
452 default:
453 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
454 break;
455 }
456 }
457 else if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
458 {
459 /* UART5CLK clock frequency */
460 switch (LL_RCC_GetUARTClockSource(UARTxSource))
461 {
462 case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */
463 uart_frequency = RCC_GetSystemClockFreq();
464 break;
465
466 case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */
467 if (LL_RCC_HSI_IsReady())
468 {
469 uart_frequency = HSI_VALUE;
470 }
471 break;
472
473 case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */
474 if (LL_RCC_LSE_IsReady())
475 {
476 uart_frequency = LSE_VALUE;
477 }
478 break;
479
480 case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */
481 default:
482 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
483 break;
484 }
485 }
486 else if (UARTxSource == LL_RCC_UART7_CLKSOURCE)
487 {
488 /* UART7CLK clock frequency */
489 switch (LL_RCC_GetUARTClockSource(UARTxSource))
490 {
491 case LL_RCC_UART7_CLKSOURCE_SYSCLK: /* UART7 Clock is System Clock */
492 uart_frequency = RCC_GetSystemClockFreq();
493 break;
494
495 case LL_RCC_UART7_CLKSOURCE_HSI: /* UART7 Clock is HSI Osc. */
496 if (LL_RCC_HSI_IsReady())
497 {
498 uart_frequency = HSI_VALUE;
499 }
500 break;
501
502 case LL_RCC_UART7_CLKSOURCE_LSE: /* UART7 Clock is LSE Osc. */
503 if (LL_RCC_LSE_IsReady())
504 {
505 uart_frequency = LSE_VALUE;
506 }
507 break;
508
509 case LL_RCC_UART7_CLKSOURCE_PCLK1: /* UART7 Clock is PCLK1 */
510 default:
511 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
512 break;
513 }
514 }
515 else
516 {
517 if (UARTxSource == LL_RCC_UART8_CLKSOURCE)
518 {
519 /* UART8CLK clock frequency */
520 switch (LL_RCC_GetUARTClockSource(UARTxSource))
521 {
522 case LL_RCC_UART8_CLKSOURCE_SYSCLK: /* UART8 Clock is System Clock */
523 uart_frequency = RCC_GetSystemClockFreq();
524 break;
525
526 case LL_RCC_UART8_CLKSOURCE_HSI: /* UART8 Clock is HSI Osc. */
527 if (LL_RCC_HSI_IsReady())
528 {
529 uart_frequency = HSI_VALUE;
530 }
531 break;
532
533 case LL_RCC_UART8_CLKSOURCE_LSE: /* UART8 Clock is LSE Osc. */
534 if (LL_RCC_LSE_IsReady())
535 {
536 uart_frequency = LSE_VALUE;
537 }
538 break;
539
540 case LL_RCC_UART8_CLKSOURCE_PCLK1: /* UART8 Clock is PCLK1 */
541 default:
542 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
543 break;
544 }
545 }
546 }
547 return uart_frequency;
548 }
549
550 /**
551 * @brief Return I2Cx clock frequency
552 * @param I2CxSource This parameter can be one of the following values:
553 * @arg @ref LL_RCC_I2C1_CLKSOURCE
554 * @arg @ref LL_RCC_I2C2_CLKSOURCE
555 * @arg @ref LL_RCC_I2C3_CLKSOURCE
556 * @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
557 *
558 * (*) value not defined in all devices.
559 * @retval I2C clock frequency (in Hz)
560 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
561 */
LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)562 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
563 {
564 uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
565
566 /* Check parameter */
567 assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
568
569 if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
570 {
571 /* I2C1 CLK clock frequency */
572 switch (LL_RCC_GetI2CClockSource(I2CxSource))
573 {
574 case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
575 i2c_frequency = RCC_GetSystemClockFreq();
576 break;
577
578 case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
579 if (LL_RCC_HSI_IsReady())
580 {
581 i2c_frequency = HSI_VALUE;
582 }
583 break;
584
585 case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */
586 default:
587 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
588 break;
589 }
590 }
591 else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
592 {
593 /* I2C2 CLK clock frequency */
594 switch (LL_RCC_GetI2CClockSource(I2CxSource))
595 {
596 case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
597 i2c_frequency = RCC_GetSystemClockFreq();
598 break;
599
600 case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */
601 if (LL_RCC_HSI_IsReady())
602 {
603 i2c_frequency = HSI_VALUE;
604 }
605 break;
606
607 case LL_RCC_I2C2_CLKSOURCE_PCLK1: /* I2C2 Clock is PCLK1 */
608 default:
609 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
610 break;
611 }
612 }
613 else if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
614 {
615 /* I2C3 CLK clock frequency */
616 switch (LL_RCC_GetI2CClockSource(I2CxSource))
617 {
618 case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
619 i2c_frequency = RCC_GetSystemClockFreq();
620 break;
621
622 case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
623 if (LL_RCC_HSI_IsReady())
624 {
625 i2c_frequency = HSI_VALUE;
626 }
627 break;
628
629 case LL_RCC_I2C3_CLKSOURCE_PCLK1: /* I2C3 Clock is PCLK1 */
630 default:
631 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
632 break;
633 }
634 }
635 #if defined(I2C4)
636 else
637 {
638 if (I2CxSource == LL_RCC_I2C4_CLKSOURCE)
639 {
640 /* I2C4 CLK clock frequency */
641 switch (LL_RCC_GetI2CClockSource(I2CxSource))
642 {
643 case LL_RCC_I2C4_CLKSOURCE_SYSCLK: /* I2C4 Clock is System Clock */
644 i2c_frequency = RCC_GetSystemClockFreq();
645 break;
646
647 case LL_RCC_I2C4_CLKSOURCE_HSI: /* I2C4 Clock is HSI Osc. */
648 if (LL_RCC_HSI_IsReady())
649 {
650 i2c_frequency = HSI_VALUE;
651 }
652 break;
653
654 case LL_RCC_I2C4_CLKSOURCE_PCLK1: /* I2C4 Clock is PCLK1 */
655 default:
656 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
657 break;
658 }
659 }
660 }
661 #else
662 else
663 {
664 /* Nothing to do */
665 }
666 #endif /* I2C4 */
667
668 return i2c_frequency;
669 }
670
671 /**
672 * @brief Return I2Sx clock frequency
673 * @param I2SxSource This parameter can be one of the following values:
674 * @arg @ref LL_RCC_I2S1_CLKSOURCE
675 * @retval I2S clock frequency (in Hz)
676 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLLI2S oscillator is not ready
677 */
LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)678 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
679 {
680 uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
681
682 /* Check parameter */
683 assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
684
685 if (I2SxSource == LL_RCC_I2S1_CLKSOURCE)
686 {
687 /* I2S1 CLK clock frequency */
688 switch (LL_RCC_GetI2SClockSource(I2SxSource))
689 {
690 case LL_RCC_I2S1_CLKSOURCE_PLLI2S: /* I2S1 Clock is PLLI2S */
691 if (LL_RCC_PLLI2S_IsReady())
692 {
693 i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S();
694 }
695 break;
696
697 case LL_RCC_I2S1_CLKSOURCE_PIN: /* I2S1 Clock is External clock */
698 default:
699 i2s_frequency = EXTERNAL_CLOCK_VALUE;
700 break;
701 }
702 }
703
704 return i2s_frequency;
705 }
706
707 /**
708 * @brief Return LPTIMx clock frequency
709 * @param LPTIMxSource This parameter can be one of the following values:
710 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
711 * @retval LPTIM clock frequency (in Hz)
712 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
713 */
LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)714 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
715 {
716 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
717
718 /* Check parameter */
719 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
720
721 if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
722 {
723 /* LPTIM1CLK clock frequency */
724 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
725 {
726 case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
727 if (LL_RCC_LSI_IsReady())
728 {
729 lptim_frequency = LSI_VALUE;
730 }
731 break;
732
733 case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */
734 if (LL_RCC_HSI_IsReady())
735 {
736 lptim_frequency = HSI_VALUE;
737 }
738 break;
739
740 case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
741 if (LL_RCC_LSE_IsReady())
742 {
743 lptim_frequency = LSE_VALUE;
744 }
745 break;
746
747 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */
748 default:
749 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
750 break;
751 }
752 }
753
754 return lptim_frequency;
755 }
756
757 /**
758 * @brief Return SAIx clock frequency
759 * @param SAIxSource This parameter can be one of the following values:
760 * @arg @ref LL_RCC_SAI1_CLKSOURCE
761 * @arg @ref LL_RCC_SAI2_CLKSOURCE
762 * @retval SAI clock frequency (in Hz)
763 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
764 */
LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)765 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
766 {
767 uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
768
769 /* Check parameter */
770 assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
771
772 if (SAIxSource == LL_RCC_SAI1_CLKSOURCE)
773 {
774 /* SAI1CLK clock frequency */
775 switch (LL_RCC_GetSAIClockSource(SAIxSource))
776 {
777 case LL_RCC_SAI1_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 clock source */
778 if (LL_RCC_PLLSAI_IsReady())
779 {
780 sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
781 }
782 break;
783
784 case LL_RCC_SAI1_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 clock source */
785 if (LL_RCC_PLLI2S_IsReady())
786 {
787 sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
788 }
789 break;
790
791 #if defined(RCC_SAI1SEL_PLLSRC_SUPPORT)
792 case LL_RCC_SAI1_CLKSOURCE_PLLSRC:
793 switch (LL_RCC_PLL_GetMainSource())
794 {
795 case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI1 clock source */
796 if (LL_RCC_HSE_IsReady())
797 {
798 sai_frequency = HSE_VALUE;
799 }
800 break;
801
802 case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI1 clock source */
803 default:
804 if (LL_RCC_HSI_IsReady())
805 {
806 sai_frequency = HSI_VALUE;
807 }
808 break;
809 }
810 break;
811 #endif /* RCC_SAI1SEL_PLLSRC_SUPPORT */
812 case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */
813 sai_frequency = EXTERNAL_SAI1_CLOCK_VALUE;
814 break;
815
816 default:
817 break;
818 }
819 }
820 else
821 {
822 if (SAIxSource == LL_RCC_SAI2_CLKSOURCE)
823 {
824 /* SAI2CLK clock frequency */
825 switch (LL_RCC_GetSAIClockSource(SAIxSource))
826 {
827 case LL_RCC_SAI2_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI2 clock source */
828 if (LL_RCC_PLLSAI_IsReady())
829 {
830 sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
831 }
832 break;
833
834 case LL_RCC_SAI2_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI2 clock source */
835 if (LL_RCC_PLLI2S_IsReady())
836 {
837 sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
838 }
839 break;
840
841 #if defined(RCC_SAI2SEL_PLLSRC_SUPPORT)
842 case LL_RCC_SAI2_CLKSOURCE_PLLSRC:
843 switch (LL_RCC_PLL_GetMainSource())
844 {
845 case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI2 clock source */
846 if (LL_RCC_HSE_IsReady())
847 {
848 sai_frequency = HSE_VALUE;
849 }
850 break;
851
852 case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI2 clock source */
853 default:
854 if (LL_RCC_HSI_IsReady())
855 {
856 sai_frequency = HSI_VALUE;
857 }
858 break;
859 }
860 break;
861 #endif /* RCC_SAI2SEL_PLLSRC_SUPPORT */
862 case LL_RCC_SAI2_CLKSOURCE_PIN: /* External input clock used as SAI2 clock source */
863 sai_frequency = EXTERNAL_SAI2_CLOCK_VALUE;
864 break;
865
866 default:
867 break;
868 }
869 }
870 }
871
872 return sai_frequency;
873 }
874
875 /**
876 * @brief Return SDMMCx clock frequency
877 * @param SDMMCxSource This parameter can be one of the following values:
878 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE
879 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE (*)
880 *
881 * (*) value not defined in all devices.
882 * @retval SDMMC clock frequency (in Hz)
883 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLL is not ready
884 */
LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)885 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
886 {
887 uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
888
889 /* Check parameter */
890 assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource));
891
892 if (SDMMCxSource == LL_RCC_SDMMC1_CLKSOURCE)
893 {
894 /* SDMMC1CLK clock frequency */
895 switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
896 {
897 case LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK: /* PLL48 clock used as SDMMC1 clock source */
898 switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE))
899 {
900 case LL_RCC_CK48M_CLKSOURCE_PLL: /* PLL clock used as 48Mhz domain clock */
901 if (LL_RCC_PLL_IsReady())
902 {
903 sdmmc_frequency = RCC_PLL_GetFreqDomain_48M();
904 }
905 break;
906
907 case LL_RCC_CK48M_CLKSOURCE_PLLSAI: /* PLLSAI clock used as 48Mhz domain clock */
908 default:
909 if (LL_RCC_PLLSAI_IsReady())
910 {
911 sdmmc_frequency = RCC_PLLSAI_GetFreqDomain_48M();
912 }
913 break;
914 }
915 break;
916
917 case LL_RCC_SDMMC1_CLKSOURCE_SYSCLK: /* PLL clock used as SDMMC1 clock source */
918 default:
919 sdmmc_frequency = RCC_GetSystemClockFreq();
920 break;
921 }
922 }
923 #if defined(SDMMC2)
924 else
925 {
926 /* SDMMC2CLK clock frequency */
927 switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
928 {
929 case LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK: /* PLL48 clock used as SDMMC2 clock source */
930 switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE))
931 {
932 case LL_RCC_CK48M_CLKSOURCE_PLL: /* PLL clock used as 48Mhz domain clock */
933 if (LL_RCC_PLL_IsReady())
934 {
935 sdmmc_frequency = RCC_PLL_GetFreqDomain_48M();
936 }
937 break;
938
939 case LL_RCC_CK48M_CLKSOURCE_PLLSAI: /* PLLSAI clock used as 48Mhz domain clock */
940 default:
941 if (LL_RCC_PLLSAI_IsReady())
942 {
943 sdmmc_frequency = RCC_PLLSAI_GetFreqDomain_48M();
944 }
945 break;
946 }
947 break;
948
949 case LL_RCC_SDMMC2_CLKSOURCE_SYSCLK: /* PLL clock used as SDMMC2 clock source */
950 default:
951 sdmmc_frequency = RCC_GetSystemClockFreq();
952 break;
953 }
954 }
955 #endif /* SDMMC2 */
956
957 return sdmmc_frequency;
958 }
959
960 /**
961 * @brief Return RNGx clock frequency
962 * @param RNGxSource This parameter can be one of the following values:
963 * @arg @ref LL_RCC_RNG_CLKSOURCE
964 * @retval RNG clock frequency (in Hz)
965 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
966 */
LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)967 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
968 {
969 uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
970
971 /* Check parameter */
972 assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
973
974 /* RNGCLK clock frequency */
975 switch (LL_RCC_GetRNGClockSource(RNGxSource))
976 {
977 case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */
978 if (LL_RCC_PLL_IsReady())
979 {
980 rng_frequency = RCC_PLL_GetFreqDomain_48M();
981 }
982 break;
983
984 case LL_RCC_RNG_CLKSOURCE_PLLSAI: /* PLLSAI clock used as RNG clock source */
985 default:
986 if (LL_RCC_PLLSAI_IsReady())
987 {
988 rng_frequency = RCC_PLLSAI_GetFreqDomain_48M();
989 }
990 break;
991 }
992
993 return rng_frequency;
994 }
995
996 #if defined(CEC)
997 /**
998 * @brief Return CEC clock frequency
999 * @param CECxSource This parameter can be one of the following values:
1000 * @arg @ref LL_RCC_CEC_CLKSOURCE
1001 * @retval CEC clock frequency (in Hz)
1002 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
1003 */
LL_RCC_GetCECClockFreq(uint32_t CECxSource)1004 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
1005 {
1006 uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1007
1008 /* Check parameter */
1009 assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
1010
1011 /* CECCLK clock frequency */
1012 switch (LL_RCC_GetCECClockSource(CECxSource))
1013 {
1014 case LL_RCC_CEC_CLKSOURCE_LSE: /* CEC Clock is LSE Osc. */
1015 if (LL_RCC_LSE_IsReady())
1016 {
1017 cec_frequency = LSE_VALUE;
1018 }
1019 break;
1020
1021 case LL_RCC_CEC_CLKSOURCE_HSI_DIV488: /* CEC Clock is HSI Osc. */
1022 default:
1023 if (LL_RCC_HSI_IsReady())
1024 {
1025 cec_frequency = HSI_VALUE/488U;
1026 }
1027 break;
1028 }
1029
1030 return cec_frequency;
1031 }
1032 #endif /* CEC */
1033
1034 /**
1035 * @brief Return USBx clock frequency
1036 * @param USBxSource This parameter can be one of the following values:
1037 * @arg @ref LL_RCC_USB_CLKSOURCE
1038 * @retval USB clock frequency (in Hz)
1039 */
LL_RCC_GetUSBClockFreq(uint32_t USBxSource)1040 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
1041 {
1042 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1043
1044 /* Check parameter */
1045 assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
1046
1047 /* USBCLK clock frequency */
1048 switch (LL_RCC_GetUSBClockSource(USBxSource))
1049 {
1050 case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
1051 if (LL_RCC_PLL_IsReady())
1052 {
1053 usb_frequency = RCC_PLL_GetFreqDomain_48M();
1054 }
1055 break;
1056
1057 case LL_RCC_USB_CLKSOURCE_PLLSAI: /* PLLSAI clock used as USB clock source */
1058 default:
1059 if (LL_RCC_PLLSAI_IsReady())
1060 {
1061 usb_frequency = RCC_PLLSAI_GetFreqDomain_48M();
1062 }
1063 break;
1064 }
1065
1066 return usb_frequency;
1067 }
1068
1069 #if defined(DFSDM1_Channel0)
1070 /**
1071 * @brief Return DFSDMx clock frequency
1072 * @param DFSDMxSource This parameter can be one of the following values:
1073 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
1074 * @retval DFSDM clock frequency (in Hz)
1075 */
LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)1076 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
1077 {
1078 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1079
1080 /* Check parameter */
1081 assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource));
1082
1083 /* DFSDM1CLK clock frequency */
1084 switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
1085 {
1086 case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK: /* DFSDM1 Clock is SYSCLK */
1087 dfsdm_frequency = RCC_GetSystemClockFreq();
1088 break;
1089
1090 case LL_RCC_DFSDM1_CLKSOURCE_PCLK2: /* DFSDM1 Clock is PCLK2 */
1091 default:
1092 dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1093 break;
1094 }
1095
1096 return dfsdm_frequency;
1097 }
1098
1099 /**
1100 * @brief Return DFSDMx Audio clock frequency
1101 * @param DFSDMxSource This parameter can be one of the following values:
1102 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
1103 * @retval DFSDM clock frequency (in Hz)
1104 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1105 */
LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)1106 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)
1107 {
1108 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1109
1110 /* Check parameter */
1111 assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource));
1112
1113 /* DFSDM1CLK clock frequency */
1114 switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
1115 {
1116 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1: /* SAI1 clock used as DFSDM1 audio clock */
1117 dfsdm_frequency = LL_RCC_GetSAIClockFreq(LL_RCC_SAI1_CLKSOURCE);
1118 break;
1119
1120 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2: /* SAI2 clock used as DFSDM1 audio clock */
1121 default:
1122 dfsdm_frequency = LL_RCC_GetSAIClockFreq(LL_RCC_SAI2_CLKSOURCE);
1123 break;
1124 }
1125
1126 return dfsdm_frequency;
1127 }
1128 #endif /* DFSDM1_Channel0 */
1129
1130 #if defined(DSI)
1131 /**
1132 * @brief Return DSI clock frequency
1133 * @param DSIxSource This parameter can be one of the following values:
1134 * @arg @ref LL_RCC_DSI_CLKSOURCE
1135 * @retval DSI clock frequency (in Hz)
1136 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1137 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
1138 */
LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)1139 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
1140 {
1141 uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1142
1143 /* Check parameter */
1144 assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource));
1145
1146 /* DSICLK clock frequency */
1147 switch (LL_RCC_GetDSIClockSource(DSIxSource))
1148 {
1149 case LL_RCC_DSI_CLKSOURCE_PLL: /* DSI Clock is PLL Osc. */
1150 if (LL_RCC_PLL_IsReady())
1151 {
1152 dsi_frequency = RCC_PLL_GetFreqDomain_DSI();
1153 }
1154 break;
1155
1156 case LL_RCC_DSI_CLKSOURCE_PHY: /* DSI Clock is DSI physical clock. */
1157 default:
1158 dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1159 break;
1160 }
1161
1162 return dsi_frequency;
1163 }
1164 #endif /* DSI */
1165
1166 #if defined(LTDC)
1167 /**
1168 * @brief Return LTDC clock frequency
1169 * @param LTDCxSource This parameter can be one of the following values:
1170 * @arg @ref LL_RCC_LTDC_CLKSOURCE
1171 * @retval LTDC clock frequency (in Hz)
1172 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready
1173 */
LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)1174 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)
1175 {
1176 uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1177
1178 /* Check parameter */
1179 assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource));
1180
1181 if (LL_RCC_PLLSAI_IsReady())
1182 {
1183 ltdc_frequency = RCC_PLLSAI_GetFreqDomain_LTDC();
1184 }
1185
1186 return ltdc_frequency;
1187 }
1188 #endif /* LTDC */
1189
1190 #if defined(SPDIFRX)
1191 /**
1192 * @brief Return SPDIFRX clock frequency
1193 * @param SPDIFRXxSource This parameter can be one of the following values:
1194 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
1195 * @retval SPDIFRX clock frequency (in Hz)
1196 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1197 */
LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource)1198 uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource)
1199 {
1200 uint32_t spdifrx_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1201
1202 /* Check parameter */
1203 assert_param(IS_LL_RCC_SPDIFRX_CLKSOURCE(SPDIFRXxSource));
1204
1205 if (LL_RCC_PLLI2S_IsReady())
1206 {
1207 spdifrx_frequency = RCC_PLLI2S_GetFreqDomain_SPDIFRX();
1208 }
1209
1210 return spdifrx_frequency;
1211 }
1212 #endif /* SPDIFRX */
1213
1214 /**
1215 * @}
1216 */
1217
1218 /**
1219 * @}
1220 */
1221
1222 /** @addtogroup RCC_LL_Private_Functions
1223 * @{
1224 */
1225
1226 /**
1227 * @brief Return SYSTEM clock frequency
1228 * @retval SYSTEM clock frequency (in Hz)
1229 */
RCC_GetSystemClockFreq(void)1230 uint32_t RCC_GetSystemClockFreq(void)
1231 {
1232 uint32_t frequency = 0U;
1233
1234 /* Get SYSCLK source -------------------------------------------------------*/
1235 switch (LL_RCC_GetSysClkSource())
1236 {
1237 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
1238 frequency = HSI_VALUE;
1239 break;
1240
1241 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
1242 frequency = HSE_VALUE;
1243 break;
1244
1245 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
1246 frequency = RCC_PLL_GetFreqDomain_SYS();
1247 break;
1248
1249 default:
1250 frequency = HSI_VALUE;
1251 break;
1252 }
1253
1254 return frequency;
1255 }
1256
1257 /**
1258 * @brief Return HCLK clock frequency
1259 * @param SYSCLK_Frequency SYSCLK clock frequency
1260 * @retval HCLK clock frequency (in Hz)
1261 */
RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)1262 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
1263 {
1264 /* HCLK clock frequency */
1265 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
1266 }
1267
1268 /**
1269 * @brief Return PCLK1 clock frequency
1270 * @param HCLK_Frequency HCLK clock frequency
1271 * @retval PCLK1 clock frequency (in Hz)
1272 */
RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)1273 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
1274 {
1275 /* PCLK1 clock frequency */
1276 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
1277 }
1278
1279 /**
1280 * @brief Return PCLK2 clock frequency
1281 * @param HCLK_Frequency HCLK clock frequency
1282 * @retval PCLK2 clock frequency (in Hz)
1283 */
RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)1284 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
1285 {
1286 /* PCLK2 clock frequency */
1287 return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
1288 }
1289
1290 /**
1291 * @brief Return PLL clock frequency used for system domain
1292 * @retval PLL clock frequency (in Hz)
1293 */
RCC_PLL_GetFreqDomain_SYS(void)1294 uint32_t RCC_PLL_GetFreqDomain_SYS(void)
1295 {
1296 uint32_t pllinputfreq = 0U, pllsource = 0U;
1297
1298 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1299 SYSCLK = PLL_VCO / PLLP
1300 */
1301 pllsource = LL_RCC_PLL_GetMainSource();
1302
1303 switch (pllsource)
1304 {
1305 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1306 pllinputfreq = HSI_VALUE;
1307 break;
1308
1309 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1310 pllinputfreq = HSE_VALUE;
1311 break;
1312
1313 default:
1314 pllinputfreq = HSI_VALUE;
1315 break;
1316 }
1317 return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1318 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
1319 }
1320
1321 /**
1322 * @brief Return PLL clock frequency used for 48 MHz domain
1323 * @retval PLL clock frequency (in Hz)
1324 */
RCC_PLL_GetFreqDomain_48M(void)1325 uint32_t RCC_PLL_GetFreqDomain_48M(void)
1326 {
1327 uint32_t pllinputfreq = 0U, pllsource = 0U;
1328
1329 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN
1330 48M Domain clock = PLL_VCO / PLLQ
1331 */
1332 pllsource = LL_RCC_PLL_GetMainSource();
1333
1334 switch (pllsource)
1335 {
1336 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1337 pllinputfreq = HSI_VALUE;
1338 break;
1339
1340 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1341 pllinputfreq = HSE_VALUE;
1342 break;
1343
1344 default:
1345 pllinputfreq = HSI_VALUE;
1346 break;
1347 }
1348 return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1349 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
1350 }
1351
1352 #if defined(DSI)
1353 /**
1354 * @brief Return PLL clock frequency used for DSI clock
1355 * @retval PLL clock frequency (in Hz)
1356 */
RCC_PLL_GetFreqDomain_DSI(void)1357 uint32_t RCC_PLL_GetFreqDomain_DSI(void)
1358 {
1359 uint32_t pllinputfreq = 0U, pllsource = 0U;
1360
1361 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1362 DSICLK = PLL_VCO / PLLR
1363 */
1364 pllsource = LL_RCC_PLL_GetMainSource();
1365
1366 switch (pllsource)
1367 {
1368 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1369 pllinputfreq = HSE_VALUE;
1370 break;
1371
1372 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1373 default:
1374 pllinputfreq = HSI_VALUE;
1375 break;
1376 }
1377 return __LL_RCC_CALC_PLLCLK_DSI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1378 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1379 }
1380 #endif /* DSI */
1381
1382 /**
1383 * @brief Return PLLSAI clock frequency used for SAI1 and SAI2 domains
1384 * @retval PLLSAI clock frequency (in Hz)
1385 */
RCC_PLLSAI_GetFreqDomain_SAI(void)1386 uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void)
1387 {
1388 uint32_t pllinputfreq = 0U, pllsource = 0U;
1389
1390 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN
1391 SAI1 and SAI2 domains clock = (PLLSAI_VCO / PLLSAIQ) / PLLSAIDIVQ
1392 */
1393 pllsource = LL_RCC_PLL_GetMainSource();
1394
1395 switch (pllsource)
1396 {
1397 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
1398 pllinputfreq = HSI_VALUE;
1399 break;
1400
1401 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
1402 pllinputfreq = HSE_VALUE;
1403 break;
1404
1405 default:
1406 pllinputfreq = HSI_VALUE;
1407 break;
1408 }
1409 return __LL_RCC_CALC_PLLSAI_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1410 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetQ(), LL_RCC_PLLSAI_GetDIVQ());
1411 }
1412
1413 /**
1414 * @brief Return PLLSAI clock frequency used for 48Mhz domain
1415 * @retval PLLSAI clock frequency (in Hz)
1416 */
RCC_PLLSAI_GetFreqDomain_48M(void)1417 uint32_t RCC_PLLSAI_GetFreqDomain_48M(void)
1418 {
1419 uint32_t pllinputfreq = 0U, pllsource = 0U;
1420
1421 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN
1422 48M Domain clock = PLLSAI_VCO / PLLSAIP
1423 */
1424 pllsource = LL_RCC_PLL_GetMainSource();
1425
1426 switch (pllsource)
1427 {
1428 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
1429 pllinputfreq = HSI_VALUE;
1430 break;
1431
1432 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
1433 pllinputfreq = HSE_VALUE;
1434 break;
1435
1436 default:
1437 pllinputfreq = HSI_VALUE;
1438 break;
1439 }
1440 return __LL_RCC_CALC_PLLSAI_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1441 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetP());
1442 }
1443
1444 #if defined(LTDC)
1445 /**
1446 * @brief Return PLLSAI clock frequency used for LTDC domain
1447 * @retval PLLSAI clock frequency (in Hz)
1448 */
RCC_PLLSAI_GetFreqDomain_LTDC(void)1449 uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void)
1450 {
1451 uint32_t pllinputfreq = 0U, pllsource = 0U;
1452
1453 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN
1454 LTDC Domain clock = (PLLSAI_VCO / PLLSAIR) / PLLSAIDIVR
1455 */
1456 pllsource = LL_RCC_PLL_GetMainSource();
1457
1458 switch (pllsource)
1459 {
1460 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
1461 pllinputfreq = HSI_VALUE;
1462 break;
1463
1464 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
1465 pllinputfreq = HSE_VALUE;
1466 break;
1467
1468 default:
1469 pllinputfreq = HSI_VALUE;
1470 break;
1471 }
1472 return __LL_RCC_CALC_PLLSAI_LTDC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1473 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetR(), LL_RCC_PLLSAI_GetDIVR());
1474 }
1475 #endif /* LTDC */
1476
1477 /**
1478 * @brief Return PLLI2S clock frequency used for SAI1 and SAI2 domains
1479 * @retval PLLI2S clock frequency (in Hz)
1480 */
RCC_PLLI2S_GetFreqDomain_SAI(void)1481 uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void)
1482 {
1483 uint32_t pllinputfreq = 0U, pllsource = 0U;
1484
1485 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN
1486 SAI1 and SAI2 domains clock = (PLLI2S_VCO / PLLI2SQ) / PLLI2SDIVQ
1487 */
1488 pllsource = LL_RCC_PLL_GetMainSource();
1489
1490 switch (pllsource)
1491 {
1492 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
1493 pllinputfreq = HSI_VALUE;
1494 break;
1495
1496 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
1497 pllinputfreq = HSE_VALUE;
1498 break;
1499
1500 default:
1501 pllinputfreq = HSI_VALUE;
1502 break;
1503 }
1504 return __LL_RCC_CALC_PLLI2S_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1505 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ(), LL_RCC_PLLI2S_GetDIVQ());
1506 }
1507
1508 #if defined(SPDIFRX)
1509 /**
1510 * @brief Return PLLI2S clock frequency used for SPDIFRX domain
1511 * @retval PLLI2S clock frequency (in Hz)
1512 */
RCC_PLLI2S_GetFreqDomain_SPDIFRX(void)1513 uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void)
1514 {
1515 uint32_t pllinputfreq = 0U, pllsource = 0U;
1516
1517 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN
1518 SPDIFRX Domain clock = PLLI2S_VCO / PLLI2SP
1519 */
1520 pllsource = LL_RCC_PLL_GetMainSource();
1521
1522 switch (pllsource)
1523 {
1524 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
1525 pllinputfreq = HSI_VALUE;
1526 break;
1527
1528 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
1529 pllinputfreq = HSE_VALUE;
1530 break;
1531
1532 default:
1533 pllinputfreq = HSI_VALUE;
1534 break;
1535 }
1536
1537 return __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1538 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetP());
1539 }
1540 #endif /* SPDIFRX */
1541
1542 /**
1543 * @brief Return PLLI2S clock frequency used for I2S domain
1544 * @retval PLLI2S clock frequency (in Hz)
1545 */
RCC_PLLI2S_GetFreqDomain_I2S(void)1546 uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)
1547 {
1548 uint32_t pllinputfreq = 0U, pllsource = 0U;
1549
1550 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN
1551 I2S Domain clock = PLLI2S_VCO / PLLI2SR
1552 */
1553 pllsource = LL_RCC_PLL_GetMainSource();
1554
1555 switch (pllsource)
1556 {
1557 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
1558 pllinputfreq = HSE_VALUE;
1559 break;
1560
1561 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
1562 default:
1563 pllinputfreq = HSI_VALUE;
1564 break;
1565 }
1566 return __LL_RCC_CALC_PLLI2S_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1567 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR());
1568 }
1569
1570 /**
1571 * @}
1572 */
1573
1574 /**
1575 * @}
1576 */
1577
1578 #endif /* defined(RCC) */
1579
1580 /**
1581 * @}
1582 */
1583
1584 #endif /* USE_FULL_LL_DRIVER */
1585
1586
