1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_tim_ex.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer Extended peripheral:
8 * + Time Hall Sensor Interface Initialization
9 * + Time Hall Sensor Interface Start
10 * + Time Complementary signal break and dead time configuration
11 * + Time Master and Slave synchronization configuration
12 * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
13 * + Timer remapping capabilities configuration
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2017 STMicroelectronics.
18 * All rights reserved.
19 *
20 * This software is licensed under terms that can be found in the LICENSE file
21 * in the root directory of this software component.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
23 *
24 ******************************************************************************
25 @verbatim
26 ==============================================================================
27 ##### TIMER Extended features #####
28 ==============================================================================
29 [..]
30 The Timer Extended features include:
31 (#) Complementary outputs with programmable dead-time for :
32 (++) Output Compare
33 (++) PWM generation (Edge and Center-aligned Mode)
34 (++) One-pulse mode output
35 (#) Synchronization circuit to control the timer with external signals and to
36 interconnect several timers together.
37 (#) Break input to put the timer output signals in reset state or in a known state.
38 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
39 positioning purposes
40
41 ##### How to use this driver #####
42 ==============================================================================
43 [..]
44 (#) Initialize the TIM low level resources by implementing the following functions
45 depending on the selected feature:
46 (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
47
48 (#) Initialize the TIM low level resources :
49 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
50 (##) TIM pins configuration
51 (+++) Enable the clock for the TIM GPIOs using the following function:
52 __HAL_RCC_GPIOx_CLK_ENABLE();
53 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
54
55 (#) The external Clock can be configured, if needed (the default clock is the
56 internal clock from the APBx), using the following function:
57 HAL_TIM_ConfigClockSource, the clock configuration should be done before
58 any start function.
59
60 (#) Configure the TIM in the desired functioning mode using one of the
61 initialization function of this driver:
62 (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
63 Timer Hall Sensor Interface and the commutation event with the corresponding
64 Interrupt and DMA request if needed (Note that One Timer is used to interface
65 with the Hall sensor Interface and another Timer should be used to use
66 the commutation event).
67
68 (#) Activate the TIM peripheral using one of the start functions:
69 (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
70 HAL_TIMEx_OCN_Start_IT()
71 (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
72 HAL_TIMEx_PWMN_Start_IT()
73 (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
74 (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(),
75 HAL_TIMEx_HallSensor_Start_IT().
76
77 @endverbatim
78 ******************************************************************************
79 */
80
81 /* Includes ------------------------------------------------------------------*/
82 #include "stm32f7xx_hal.h"
83
84 /** @addtogroup STM32F7xx_HAL_Driver
85 * @{
86 */
87
88 /** @defgroup TIMEx TIMEx
89 * @brief TIM Extended HAL module driver
90 * @{
91 */
92
93 #ifdef HAL_TIM_MODULE_ENABLED
94
95 /* Private typedef -----------------------------------------------------------*/
96 /* Private define ------------------------------------------------------------*/
97 /* Private macros ------------------------------------------------------------*/
98 /* Private variables ---------------------------------------------------------*/
99 /* Private function prototypes -----------------------------------------------*/
100 static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
101 static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
102 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
103
104 /* Exported functions --------------------------------------------------------*/
105 /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
106 * @{
107 */
108
109 /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
110 * @brief Timer Hall Sensor functions
111 *
112 @verbatim
113 ==============================================================================
114 ##### Timer Hall Sensor functions #####
115 ==============================================================================
116 [..]
117 This section provides functions allowing to:
118 (+) Initialize and configure TIM HAL Sensor.
119 (+) De-initialize TIM HAL Sensor.
120 (+) Start the Hall Sensor Interface.
121 (+) Stop the Hall Sensor Interface.
122 (+) Start the Hall Sensor Interface and enable interrupts.
123 (+) Stop the Hall Sensor Interface and disable interrupts.
124 (+) Start the Hall Sensor Interface and enable DMA transfers.
125 (+) Stop the Hall Sensor Interface and disable DMA transfers.
126
127 @endverbatim
128 * @{
129 */
130 /**
131 * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
132 * @note When the timer instance is initialized in Hall Sensor Interface mode,
133 * timer channels 1 and channel 2 are reserved and cannot be used for
134 * other purpose.
135 * @param htim TIM Hall Sensor Interface handle
136 * @param sConfig TIM Hall Sensor configuration structure
137 * @retval HAL status
138 */
HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef * htim,const TIM_HallSensor_InitTypeDef * sConfig)139 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig)
140 {
141 TIM_OC_InitTypeDef OC_Config;
142
143 /* Check the TIM handle allocation */
144 if (htim == NULL)
145 {
146 return HAL_ERROR;
147 }
148
149 /* Check the parameters */
150 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
151 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
152 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
153 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
154 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
155 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
156 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
157 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
158
159 if (htim->State == HAL_TIM_STATE_RESET)
160 {
161 /* Allocate lock resource and initialize it */
162 htim->Lock = HAL_UNLOCKED;
163
164 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
165 /* Reset interrupt callbacks to legacy week callbacks */
166 TIM_ResetCallback(htim);
167
168 if (htim->HallSensor_MspInitCallback == NULL)
169 {
170 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
171 }
172 /* Init the low level hardware : GPIO, CLOCK, NVIC */
173 htim->HallSensor_MspInitCallback(htim);
174 #else
175 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
176 HAL_TIMEx_HallSensor_MspInit(htim);
177 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
178 }
179
180 /* Set the TIM state */
181 htim->State = HAL_TIM_STATE_BUSY;
182
183 /* Configure the Time base in the Encoder Mode */
184 TIM_Base_SetConfig(htim->Instance, &htim->Init);
185
186 /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
187 TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
188
189 /* Reset the IC1PSC Bits */
190 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
191 /* Set the IC1PSC value */
192 htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
193
194 /* Enable the Hall sensor interface (XOR function of the three inputs) */
195 htim->Instance->CR2 |= TIM_CR2_TI1S;
196
197 /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
198 htim->Instance->SMCR &= ~TIM_SMCR_TS;
199 htim->Instance->SMCR |= TIM_TS_TI1F_ED;
200
201 /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
202 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
203 htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
204
205 /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
206 OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
207 OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
208 OC_Config.OCMode = TIM_OCMODE_PWM2;
209 OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
210 OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
211 OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
212 OC_Config.Pulse = sConfig->Commutation_Delay;
213
214 TIM_OC2_SetConfig(htim->Instance, &OC_Config);
215
216 /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
217 register to 101 */
218 htim->Instance->CR2 &= ~TIM_CR2_MMS;
219 htim->Instance->CR2 |= TIM_TRGO_OC2REF;
220
221 /* Initialize the DMA burst operation state */
222 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
223
224 /* Initialize the TIM channels state */
225 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
226 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
227 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
228 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
229
230 /* Initialize the TIM state*/
231 htim->State = HAL_TIM_STATE_READY;
232
233 return HAL_OK;
234 }
235
236 /**
237 * @brief DeInitializes the TIM Hall Sensor interface
238 * @param htim TIM Hall Sensor Interface handle
239 * @retval HAL status
240 */
HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef * htim)241 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
242 {
243 /* Check the parameters */
244 assert_param(IS_TIM_INSTANCE(htim->Instance));
245
246 htim->State = HAL_TIM_STATE_BUSY;
247
248 /* Disable the TIM Peripheral Clock */
249 __HAL_TIM_DISABLE(htim);
250
251 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
252 if (htim->HallSensor_MspDeInitCallback == NULL)
253 {
254 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
255 }
256 /* DeInit the low level hardware */
257 htim->HallSensor_MspDeInitCallback(htim);
258 #else
259 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
260 HAL_TIMEx_HallSensor_MspDeInit(htim);
261 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
262
263 /* Change the DMA burst operation state */
264 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
265
266 /* Change the TIM channels state */
267 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
268 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
269 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
270 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
271
272 /* Change TIM state */
273 htim->State = HAL_TIM_STATE_RESET;
274
275 /* Release Lock */
276 __HAL_UNLOCK(htim);
277
278 return HAL_OK;
279 }
280
281 /**
282 * @brief Initializes the TIM Hall Sensor MSP.
283 * @param htim TIM Hall Sensor Interface handle
284 * @retval None
285 */
HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef * htim)286 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
287 {
288 /* Prevent unused argument(s) compilation warning */
289 UNUSED(htim);
290
291 /* NOTE : This function should not be modified, when the callback is needed,
292 the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
293 */
294 }
295
296 /**
297 * @brief DeInitializes TIM Hall Sensor MSP.
298 * @param htim TIM Hall Sensor Interface handle
299 * @retval None
300 */
HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef * htim)301 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
302 {
303 /* Prevent unused argument(s) compilation warning */
304 UNUSED(htim);
305
306 /* NOTE : This function should not be modified, when the callback is needed,
307 the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
308 */
309 }
310
311 /**
312 * @brief Starts the TIM Hall Sensor Interface.
313 * @param htim TIM Hall Sensor Interface handle
314 * @retval HAL status
315 */
HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef * htim)316 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
317 {
318 uint32_t tmpsmcr;
319 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
320 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
321 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
322 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
323
324 /* Check the parameters */
325 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
326
327 /* Check the TIM channels state */
328 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
329 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
330 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
331 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
332 {
333 return HAL_ERROR;
334 }
335
336 /* Set the TIM channels state */
337 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
338 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
339 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
340 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
341
342 /* Enable the Input Capture channel 1
343 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
344 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
345 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
346
347 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
348 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
349 {
350 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
351 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
352 {
353 __HAL_TIM_ENABLE(htim);
354 }
355 }
356 else
357 {
358 __HAL_TIM_ENABLE(htim);
359 }
360
361 /* Return function status */
362 return HAL_OK;
363 }
364
365 /**
366 * @brief Stops the TIM Hall sensor Interface.
367 * @param htim TIM Hall Sensor Interface handle
368 * @retval HAL status
369 */
HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef * htim)370 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
371 {
372 /* Check the parameters */
373 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
374
375 /* Disable the Input Capture channels 1, 2 and 3
376 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
377 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
378 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
379
380 /* Disable the Peripheral */
381 __HAL_TIM_DISABLE(htim);
382
383 /* Set the TIM channels state */
384 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
385 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
386 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
387 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
388
389 /* Return function status */
390 return HAL_OK;
391 }
392
393 /**
394 * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
395 * @param htim TIM Hall Sensor Interface handle
396 * @retval HAL status
397 */
HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef * htim)398 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
399 {
400 uint32_t tmpsmcr;
401 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
402 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
403 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
404 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
405
406 /* Check the parameters */
407 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
408
409 /* Check the TIM channels state */
410 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
411 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
412 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
413 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
414 {
415 return HAL_ERROR;
416 }
417
418 /* Set the TIM channels state */
419 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
420 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
421 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
422 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
423
424 /* Enable the capture compare Interrupts 1 event */
425 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
426
427 /* Enable the Input Capture channel 1
428 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
429 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
430 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
431
432 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
433 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
434 {
435 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
436 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
437 {
438 __HAL_TIM_ENABLE(htim);
439 }
440 }
441 else
442 {
443 __HAL_TIM_ENABLE(htim);
444 }
445
446 /* Return function status */
447 return HAL_OK;
448 }
449
450 /**
451 * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
452 * @param htim TIM Hall Sensor Interface handle
453 * @retval HAL status
454 */
HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef * htim)455 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
456 {
457 /* Check the parameters */
458 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
459
460 /* Disable the Input Capture channel 1
461 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
462 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
463 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
464
465 /* Disable the capture compare Interrupts event */
466 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
467
468 /* Disable the Peripheral */
469 __HAL_TIM_DISABLE(htim);
470
471 /* Set the TIM channels state */
472 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
473 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
474 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
475 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
476
477 /* Return function status */
478 return HAL_OK;
479 }
480
481 /**
482 * @brief Starts the TIM Hall Sensor Interface in DMA mode.
483 * @param htim TIM Hall Sensor Interface handle
484 * @param pData The destination Buffer address.
485 * @param Length The length of data to be transferred from TIM peripheral to memory.
486 * @retval HAL status
487 */
HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef * htim,uint32_t * pData,uint16_t Length)488 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
489 {
490 uint32_t tmpsmcr;
491 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
492 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
493
494 /* Check the parameters */
495 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
496
497 /* Set the TIM channel state */
498 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
499 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
500 {
501 return HAL_BUSY;
502 }
503 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
504 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
505 {
506 if ((pData == NULL) || (Length == 0U))
507 {
508 return HAL_ERROR;
509 }
510 else
511 {
512 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
513 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
514 }
515 }
516 else
517 {
518 return HAL_ERROR;
519 }
520
521 /* Enable the Input Capture channel 1
522 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
523 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
524 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
525
526 /* Set the DMA Input Capture 1 Callbacks */
527 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
528 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
529 /* Set the DMA error callback */
530 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
531
532 /* Enable the DMA stream for Capture 1*/
533 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
534 {
535 /* Return error status */
536 return HAL_ERROR;
537 }
538 /* Enable the capture compare 1 Interrupt */
539 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
540
541 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
542 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
543 {
544 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
545 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
546 {
547 __HAL_TIM_ENABLE(htim);
548 }
549 }
550 else
551 {
552 __HAL_TIM_ENABLE(htim);
553 }
554
555 /* Return function status */
556 return HAL_OK;
557 }
558
559 /**
560 * @brief Stops the TIM Hall Sensor Interface in DMA mode.
561 * @param htim TIM Hall Sensor Interface handle
562 * @retval HAL status
563 */
HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef * htim)564 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
565 {
566 /* Check the parameters */
567 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
568
569 /* Disable the Input Capture channel 1
570 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
571 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
572 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
573
574
575 /* Disable the capture compare Interrupts 1 event */
576 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
577
578 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
579
580 /* Disable the Peripheral */
581 __HAL_TIM_DISABLE(htim);
582
583 /* Set the TIM channel state */
584 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
585 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
586
587 /* Return function status */
588 return HAL_OK;
589 }
590
591 /**
592 * @}
593 */
594
595 /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
596 * @brief Timer Complementary Output Compare functions
597 *
598 @verbatim
599 ==============================================================================
600 ##### Timer Complementary Output Compare functions #####
601 ==============================================================================
602 [..]
603 This section provides functions allowing to:
604 (+) Start the Complementary Output Compare/PWM.
605 (+) Stop the Complementary Output Compare/PWM.
606 (+) Start the Complementary Output Compare/PWM and enable interrupts.
607 (+) Stop the Complementary Output Compare/PWM and disable interrupts.
608 (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
609 (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
610
611 @endverbatim
612 * @{
613 */
614
615 /**
616 * @brief Starts the TIM Output Compare signal generation on the complementary
617 * output.
618 * @param htim TIM Output Compare handle
619 * @param Channel TIM Channel to be enabled
620 * This parameter can be one of the following values:
621 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
622 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
623 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
624 * @retval HAL status
625 */
HAL_TIMEx_OCN_Start(TIM_HandleTypeDef * htim,uint32_t Channel)626 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
627 {
628 uint32_t tmpsmcr;
629
630 /* Check the parameters */
631 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
632
633 /* Check the TIM complementary channel state */
634 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
635 {
636 return HAL_ERROR;
637 }
638
639 /* Set the TIM complementary channel state */
640 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
641
642 /* Enable the Capture compare channel N */
643 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
644
645 /* Enable the Main Output */
646 __HAL_TIM_MOE_ENABLE(htim);
647
648 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
649 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
650 {
651 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
652 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
653 {
654 __HAL_TIM_ENABLE(htim);
655 }
656 }
657 else
658 {
659 __HAL_TIM_ENABLE(htim);
660 }
661
662 /* Return function status */
663 return HAL_OK;
664 }
665
666 /**
667 * @brief Stops the TIM Output Compare signal generation on the complementary
668 * output.
669 * @param htim TIM handle
670 * @param Channel TIM Channel to be disabled
671 * This parameter can be one of the following values:
672 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
673 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
674 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
675 * @retval HAL status
676 */
HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)677 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
678 {
679 /* Check the parameters */
680 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
681
682 /* Disable the Capture compare channel N */
683 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
684
685 /* Disable the Main Output */
686 __HAL_TIM_MOE_DISABLE(htim);
687
688 /* Disable the Peripheral */
689 __HAL_TIM_DISABLE(htim);
690
691 /* Set the TIM complementary channel state */
692 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
693
694 /* Return function status */
695 return HAL_OK;
696 }
697
698 /**
699 * @brief Starts the TIM Output Compare signal generation in interrupt mode
700 * on the complementary output.
701 * @param htim TIM OC handle
702 * @param Channel TIM Channel to be enabled
703 * This parameter can be one of the following values:
704 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
705 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
706 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
707 * @retval HAL status
708 */
HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)709 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
710 {
711 HAL_StatusTypeDef status = HAL_OK;
712 uint32_t tmpsmcr;
713
714 /* Check the parameters */
715 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
716
717 /* Check the TIM complementary channel state */
718 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
719 {
720 return HAL_ERROR;
721 }
722
723 /* Set the TIM complementary channel state */
724 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
725
726 switch (Channel)
727 {
728 case TIM_CHANNEL_1:
729 {
730 /* Enable the TIM Output Compare interrupt */
731 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
732 break;
733 }
734
735 case TIM_CHANNEL_2:
736 {
737 /* Enable the TIM Output Compare interrupt */
738 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
739 break;
740 }
741
742 case TIM_CHANNEL_3:
743 {
744 /* Enable the TIM Output Compare interrupt */
745 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
746 break;
747 }
748
749
750 default:
751 status = HAL_ERROR;
752 break;
753 }
754
755 if (status == HAL_OK)
756 {
757 /* Enable the TIM Break interrupt */
758 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
759
760 /* Enable the Capture compare channel N */
761 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
762
763 /* Enable the Main Output */
764 __HAL_TIM_MOE_ENABLE(htim);
765
766 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
767 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
768 {
769 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
770 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
771 {
772 __HAL_TIM_ENABLE(htim);
773 }
774 }
775 else
776 {
777 __HAL_TIM_ENABLE(htim);
778 }
779 }
780
781 /* Return function status */
782 return status;
783 }
784
785 /**
786 * @brief Stops the TIM Output Compare signal generation in interrupt mode
787 * on the complementary output.
788 * @param htim TIM Output Compare handle
789 * @param Channel TIM Channel to be disabled
790 * This parameter can be one of the following values:
791 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
792 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
793 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
794 * @retval HAL status
795 */
HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)796 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
797 {
798 HAL_StatusTypeDef status = HAL_OK;
799 uint32_t tmpccer;
800
801 /* Check the parameters */
802 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
803
804 switch (Channel)
805 {
806 case TIM_CHANNEL_1:
807 {
808 /* Disable the TIM Output Compare interrupt */
809 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
810 break;
811 }
812
813 case TIM_CHANNEL_2:
814 {
815 /* Disable the TIM Output Compare interrupt */
816 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
817 break;
818 }
819
820 case TIM_CHANNEL_3:
821 {
822 /* Disable the TIM Output Compare interrupt */
823 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
824 break;
825 }
826
827 default:
828 status = HAL_ERROR;
829 break;
830 }
831
832 if (status == HAL_OK)
833 {
834 /* Disable the Capture compare channel N */
835 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
836
837 /* Disable the TIM Break interrupt (only if no more channel is active) */
838 tmpccer = htim->Instance->CCER;
839 if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
840 {
841 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
842 }
843
844 /* Disable the Main Output */
845 __HAL_TIM_MOE_DISABLE(htim);
846
847 /* Disable the Peripheral */
848 __HAL_TIM_DISABLE(htim);
849
850 /* Set the TIM complementary channel state */
851 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
852 }
853
854 /* Return function status */
855 return status;
856 }
857
858 /**
859 * @brief Starts the TIM Output Compare signal generation in DMA mode
860 * on the complementary output.
861 * @param htim TIM Output Compare handle
862 * @param Channel TIM Channel to be enabled
863 * This parameter can be one of the following values:
864 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
865 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
866 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
867 * @param pData The source Buffer address.
868 * @param Length The length of data to be transferred from memory to TIM peripheral
869 * @retval HAL status
870 */
HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)871 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
872 uint16_t Length)
873 {
874 HAL_StatusTypeDef status = HAL_OK;
875 uint32_t tmpsmcr;
876
877 /* Check the parameters */
878 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
879
880 /* Set the TIM complementary channel state */
881 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
882 {
883 return HAL_BUSY;
884 }
885 else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
886 {
887 if ((pData == NULL) || (Length == 0U))
888 {
889 return HAL_ERROR;
890 }
891 else
892 {
893 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
894 }
895 }
896 else
897 {
898 return HAL_ERROR;
899 }
900
901 switch (Channel)
902 {
903 case TIM_CHANNEL_1:
904 {
905 /* Set the DMA compare callbacks */
906 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
907 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
908
909 /* Set the DMA error callback */
910 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
911
912 /* Enable the DMA stream */
913 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
914 Length) != HAL_OK)
915 {
916 /* Return error status */
917 return HAL_ERROR;
918 }
919 /* Enable the TIM Output Compare DMA request */
920 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
921 break;
922 }
923
924 case TIM_CHANNEL_2:
925 {
926 /* Set the DMA compare callbacks */
927 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
928 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
929
930 /* Set the DMA error callback */
931 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
932
933 /* Enable the DMA stream */
934 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
935 Length) != HAL_OK)
936 {
937 /* Return error status */
938 return HAL_ERROR;
939 }
940 /* Enable the TIM Output Compare DMA request */
941 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
942 break;
943 }
944
945 case TIM_CHANNEL_3:
946 {
947 /* Set the DMA compare callbacks */
948 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
949 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
950
951 /* Set the DMA error callback */
952 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
953
954 /* Enable the DMA stream */
955 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
956 Length) != HAL_OK)
957 {
958 /* Return error status */
959 return HAL_ERROR;
960 }
961 /* Enable the TIM Output Compare DMA request */
962 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
963 break;
964 }
965
966 default:
967 status = HAL_ERROR;
968 break;
969 }
970
971 if (status == HAL_OK)
972 {
973 /* Enable the Capture compare channel N */
974 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
975
976 /* Enable the Main Output */
977 __HAL_TIM_MOE_ENABLE(htim);
978
979 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
980 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
981 {
982 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
983 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
984 {
985 __HAL_TIM_ENABLE(htim);
986 }
987 }
988 else
989 {
990 __HAL_TIM_ENABLE(htim);
991 }
992 }
993
994 /* Return function status */
995 return status;
996 }
997
998 /**
999 * @brief Stops the TIM Output Compare signal generation in DMA mode
1000 * on the complementary output.
1001 * @param htim TIM Output Compare handle
1002 * @param Channel TIM Channel to be disabled
1003 * This parameter can be one of the following values:
1004 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1005 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1006 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1007 * @retval HAL status
1008 */
HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1009 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1010 {
1011 HAL_StatusTypeDef status = HAL_OK;
1012
1013 /* Check the parameters */
1014 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1015
1016 switch (Channel)
1017 {
1018 case TIM_CHANNEL_1:
1019 {
1020 /* Disable the TIM Output Compare DMA request */
1021 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1022 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1023 break;
1024 }
1025
1026 case TIM_CHANNEL_2:
1027 {
1028 /* Disable the TIM Output Compare DMA request */
1029 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1030 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1031 break;
1032 }
1033
1034 case TIM_CHANNEL_3:
1035 {
1036 /* Disable the TIM Output Compare DMA request */
1037 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1038 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1039 break;
1040 }
1041
1042 default:
1043 status = HAL_ERROR;
1044 break;
1045 }
1046
1047 if (status == HAL_OK)
1048 {
1049 /* Disable the Capture compare channel N */
1050 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1051
1052 /* Disable the Main Output */
1053 __HAL_TIM_MOE_DISABLE(htim);
1054
1055 /* Disable the Peripheral */
1056 __HAL_TIM_DISABLE(htim);
1057
1058 /* Set the TIM complementary channel state */
1059 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1060 }
1061
1062 /* Return function status */
1063 return status;
1064 }
1065
1066 /**
1067 * @}
1068 */
1069
1070 /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
1071 * @brief Timer Complementary PWM functions
1072 *
1073 @verbatim
1074 ==============================================================================
1075 ##### Timer Complementary PWM functions #####
1076 ==============================================================================
1077 [..]
1078 This section provides functions allowing to:
1079 (+) Start the Complementary PWM.
1080 (+) Stop the Complementary PWM.
1081 (+) Start the Complementary PWM and enable interrupts.
1082 (+) Stop the Complementary PWM and disable interrupts.
1083 (+) Start the Complementary PWM and enable DMA transfers.
1084 (+) Stop the Complementary PWM and disable DMA transfers.
1085 @endverbatim
1086 * @{
1087 */
1088
1089 /**
1090 * @brief Starts the PWM signal generation on the complementary output.
1091 * @param htim TIM handle
1092 * @param Channel TIM Channel to be enabled
1093 * This parameter can be one of the following values:
1094 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1095 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1096 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1097 * @retval HAL status
1098 */
HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1099 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1100 {
1101 uint32_t tmpsmcr;
1102
1103 /* Check the parameters */
1104 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1105
1106 /* Check the TIM complementary channel state */
1107 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1108 {
1109 return HAL_ERROR;
1110 }
1111
1112 /* Set the TIM complementary channel state */
1113 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1114
1115 /* Enable the complementary PWM output */
1116 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1117
1118 /* Enable the Main Output */
1119 __HAL_TIM_MOE_ENABLE(htim);
1120
1121 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1122 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1123 {
1124 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1125 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1126 {
1127 __HAL_TIM_ENABLE(htim);
1128 }
1129 }
1130 else
1131 {
1132 __HAL_TIM_ENABLE(htim);
1133 }
1134
1135 /* Return function status */
1136 return HAL_OK;
1137 }
1138
1139 /**
1140 * @brief Stops the PWM signal generation on the complementary output.
1141 * @param htim TIM handle
1142 * @param Channel TIM Channel to be disabled
1143 * This parameter can be one of the following values:
1144 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1145 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1146 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1147 * @retval HAL status
1148 */
HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1149 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1150 {
1151 /* Check the parameters */
1152 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1153
1154 /* Disable the complementary PWM output */
1155 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1156
1157 /* Disable the Main Output */
1158 __HAL_TIM_MOE_DISABLE(htim);
1159
1160 /* Disable the Peripheral */
1161 __HAL_TIM_DISABLE(htim);
1162
1163 /* Set the TIM complementary channel state */
1164 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1165
1166 /* Return function status */
1167 return HAL_OK;
1168 }
1169
1170 /**
1171 * @brief Starts the PWM signal generation in interrupt mode on the
1172 * complementary output.
1173 * @param htim TIM handle
1174 * @param Channel TIM Channel to be disabled
1175 * This parameter can be one of the following values:
1176 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1177 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1178 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1179 * @retval HAL status
1180 */
HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1181 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1182 {
1183 HAL_StatusTypeDef status = HAL_OK;
1184 uint32_t tmpsmcr;
1185
1186 /* Check the parameters */
1187 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1188
1189 /* Check the TIM complementary channel state */
1190 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1191 {
1192 return HAL_ERROR;
1193 }
1194
1195 /* Set the TIM complementary channel state */
1196 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1197
1198 switch (Channel)
1199 {
1200 case TIM_CHANNEL_1:
1201 {
1202 /* Enable the TIM Capture/Compare 1 interrupt */
1203 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1204 break;
1205 }
1206
1207 case TIM_CHANNEL_2:
1208 {
1209 /* Enable the TIM Capture/Compare 2 interrupt */
1210 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1211 break;
1212 }
1213
1214 case TIM_CHANNEL_3:
1215 {
1216 /* Enable the TIM Capture/Compare 3 interrupt */
1217 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1218 break;
1219 }
1220
1221 default:
1222 status = HAL_ERROR;
1223 break;
1224 }
1225
1226 if (status == HAL_OK)
1227 {
1228 /* Enable the TIM Break interrupt */
1229 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
1230
1231 /* Enable the complementary PWM output */
1232 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1233
1234 /* Enable the Main Output */
1235 __HAL_TIM_MOE_ENABLE(htim);
1236
1237 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1238 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1239 {
1240 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1241 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1242 {
1243 __HAL_TIM_ENABLE(htim);
1244 }
1245 }
1246 else
1247 {
1248 __HAL_TIM_ENABLE(htim);
1249 }
1250 }
1251
1252 /* Return function status */
1253 return status;
1254 }
1255
1256 /**
1257 * @brief Stops the PWM signal generation in interrupt mode on the
1258 * complementary output.
1259 * @param htim TIM handle
1260 * @param Channel TIM Channel to be disabled
1261 * This parameter can be one of the following values:
1262 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1263 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1264 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1265 * @retval HAL status
1266 */
HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1267 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1268 {
1269 HAL_StatusTypeDef status = HAL_OK;
1270 uint32_t tmpccer;
1271
1272 /* Check the parameters */
1273 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1274
1275 switch (Channel)
1276 {
1277 case TIM_CHANNEL_1:
1278 {
1279 /* Disable the TIM Capture/Compare 1 interrupt */
1280 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1281 break;
1282 }
1283
1284 case TIM_CHANNEL_2:
1285 {
1286 /* Disable the TIM Capture/Compare 2 interrupt */
1287 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1288 break;
1289 }
1290
1291 case TIM_CHANNEL_3:
1292 {
1293 /* Disable the TIM Capture/Compare 3 interrupt */
1294 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1295 break;
1296 }
1297
1298 default:
1299 status = HAL_ERROR;
1300 break;
1301 }
1302
1303 if (status == HAL_OK)
1304 {
1305 /* Disable the complementary PWM output */
1306 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1307
1308 /* Disable the TIM Break interrupt (only if no more channel is active) */
1309 tmpccer = htim->Instance->CCER;
1310 if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
1311 {
1312 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
1313 }
1314
1315 /* Disable the Main Output */
1316 __HAL_TIM_MOE_DISABLE(htim);
1317
1318 /* Disable the Peripheral */
1319 __HAL_TIM_DISABLE(htim);
1320
1321 /* Set the TIM complementary channel state */
1322 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1323 }
1324
1325 /* Return function status */
1326 return status;
1327 }
1328
1329 /**
1330 * @brief Starts the TIM PWM signal generation in DMA mode on the
1331 * complementary output
1332 * @param htim TIM handle
1333 * @param Channel TIM Channel to be enabled
1334 * This parameter can be one of the following values:
1335 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1336 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1337 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1338 * @param pData The source Buffer address.
1339 * @param Length The length of data to be transferred from memory to TIM peripheral
1340 * @retval HAL status
1341 */
HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1342 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1343 uint16_t Length)
1344 {
1345 HAL_StatusTypeDef status = HAL_OK;
1346 uint32_t tmpsmcr;
1347
1348 /* Check the parameters */
1349 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1350
1351 /* Set the TIM complementary channel state */
1352 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1353 {
1354 return HAL_BUSY;
1355 }
1356 else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1357 {
1358 if ((pData == NULL) || (Length == 0U))
1359 {
1360 return HAL_ERROR;
1361 }
1362 else
1363 {
1364 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1365 }
1366 }
1367 else
1368 {
1369 return HAL_ERROR;
1370 }
1371
1372 switch (Channel)
1373 {
1374 case TIM_CHANNEL_1:
1375 {
1376 /* Set the DMA compare callbacks */
1377 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1378 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1379
1380 /* Set the DMA error callback */
1381 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
1382
1383 /* Enable the DMA stream */
1384 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1385 Length) != HAL_OK)
1386 {
1387 /* Return error status */
1388 return HAL_ERROR;
1389 }
1390 /* Enable the TIM Capture/Compare 1 DMA request */
1391 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1392 break;
1393 }
1394
1395 case TIM_CHANNEL_2:
1396 {
1397 /* Set the DMA compare callbacks */
1398 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1399 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1400
1401 /* Set the DMA error callback */
1402 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
1403
1404 /* Enable the DMA stream */
1405 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1406 Length) != HAL_OK)
1407 {
1408 /* Return error status */
1409 return HAL_ERROR;
1410 }
1411 /* Enable the TIM Capture/Compare 2 DMA request */
1412 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1413 break;
1414 }
1415
1416 case TIM_CHANNEL_3:
1417 {
1418 /* Set the DMA compare callbacks */
1419 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1420 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1421
1422 /* Set the DMA error callback */
1423 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
1424
1425 /* Enable the DMA stream */
1426 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1427 Length) != HAL_OK)
1428 {
1429 /* Return error status */
1430 return HAL_ERROR;
1431 }
1432 /* Enable the TIM Capture/Compare 3 DMA request */
1433 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1434 break;
1435 }
1436
1437 default:
1438 status = HAL_ERROR;
1439 break;
1440 }
1441
1442 if (status == HAL_OK)
1443 {
1444 /* Enable the complementary PWM output */
1445 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1446
1447 /* Enable the Main Output */
1448 __HAL_TIM_MOE_ENABLE(htim);
1449
1450 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1451 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1452 {
1453 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1454 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1455 {
1456 __HAL_TIM_ENABLE(htim);
1457 }
1458 }
1459 else
1460 {
1461 __HAL_TIM_ENABLE(htim);
1462 }
1463 }
1464
1465 /* Return function status */
1466 return status;
1467 }
1468
1469 /**
1470 * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
1471 * output
1472 * @param htim TIM handle
1473 * @param Channel TIM Channel to be disabled
1474 * This parameter can be one of the following values:
1475 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1476 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1477 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1478 * @retval HAL status
1479 */
HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1480 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1481 {
1482 HAL_StatusTypeDef status = HAL_OK;
1483
1484 /* Check the parameters */
1485 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1486
1487 switch (Channel)
1488 {
1489 case TIM_CHANNEL_1:
1490 {
1491 /* Disable the TIM Capture/Compare 1 DMA request */
1492 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1493 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1494 break;
1495 }
1496
1497 case TIM_CHANNEL_2:
1498 {
1499 /* Disable the TIM Capture/Compare 2 DMA request */
1500 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1501 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1502 break;
1503 }
1504
1505 case TIM_CHANNEL_3:
1506 {
1507 /* Disable the TIM Capture/Compare 3 DMA request */
1508 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1509 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1510 break;
1511 }
1512
1513 default:
1514 status = HAL_ERROR;
1515 break;
1516 }
1517
1518 if (status == HAL_OK)
1519 {
1520 /* Disable the complementary PWM output */
1521 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1522
1523 /* Disable the Main Output */
1524 __HAL_TIM_MOE_DISABLE(htim);
1525
1526 /* Disable the Peripheral */
1527 __HAL_TIM_DISABLE(htim);
1528
1529 /* Set the TIM complementary channel state */
1530 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1531 }
1532
1533 /* Return function status */
1534 return status;
1535 }
1536
1537 /**
1538 * @}
1539 */
1540
1541 /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
1542 * @brief Timer Complementary One Pulse functions
1543 *
1544 @verbatim
1545 ==============================================================================
1546 ##### Timer Complementary One Pulse functions #####
1547 ==============================================================================
1548 [..]
1549 This section provides functions allowing to:
1550 (+) Start the Complementary One Pulse generation.
1551 (+) Stop the Complementary One Pulse.
1552 (+) Start the Complementary One Pulse and enable interrupts.
1553 (+) Stop the Complementary One Pulse and disable interrupts.
1554
1555 @endverbatim
1556 * @{
1557 */
1558
1559 /**
1560 * @brief Starts the TIM One Pulse signal generation on the complementary
1561 * output.
1562 * @note OutputChannel must match the pulse output channel chosen when calling
1563 * @ref HAL_TIM_OnePulse_ConfigChannel().
1564 * @param htim TIM One Pulse handle
1565 * @param OutputChannel pulse output channel to enable
1566 * This parameter can be one of the following values:
1567 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1568 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1569 * @retval HAL status
1570 */
HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1571 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1572 {
1573 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1574 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
1575 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
1576 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
1577 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
1578
1579 /* Check the parameters */
1580 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1581
1582 /* Check the TIM channels state */
1583 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1584 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
1585 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1586 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
1587 {
1588 return HAL_ERROR;
1589 }
1590
1591 /* Set the TIM channels state */
1592 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1593 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1594 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1595 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1596
1597 /* Enable the complementary One Pulse output channel and the Input Capture channel */
1598 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
1599 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
1600
1601 /* Enable the Main Output */
1602 __HAL_TIM_MOE_ENABLE(htim);
1603
1604 /* Return function status */
1605 return HAL_OK;
1606 }
1607
1608 /**
1609 * @brief Stops the TIM One Pulse signal generation on the complementary
1610 * output.
1611 * @note OutputChannel must match the pulse output channel chosen when calling
1612 * @ref HAL_TIM_OnePulse_ConfigChannel().
1613 * @param htim TIM One Pulse handle
1614 * @param OutputChannel pulse output channel to disable
1615 * This parameter can be one of the following values:
1616 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1617 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1618 * @retval HAL status
1619 */
HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1620 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1621 {
1622 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1623
1624 /* Check the parameters */
1625 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1626
1627 /* Disable the complementary One Pulse output channel and the Input Capture channel */
1628 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
1629 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
1630
1631 /* Disable the Main Output */
1632 __HAL_TIM_MOE_DISABLE(htim);
1633
1634 /* Disable the Peripheral */
1635 __HAL_TIM_DISABLE(htim);
1636
1637 /* Set the TIM channels state */
1638 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1639 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1640 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1641 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1642
1643 /* Return function status */
1644 return HAL_OK;
1645 }
1646
1647 /**
1648 * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
1649 * complementary channel.
1650 * @note OutputChannel must match the pulse output channel chosen when calling
1651 * @ref HAL_TIM_OnePulse_ConfigChannel().
1652 * @param htim TIM One Pulse handle
1653 * @param OutputChannel pulse output channel to enable
1654 * This parameter can be one of the following values:
1655 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1656 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1657 * @retval HAL status
1658 */
HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1659 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1660 {
1661 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1662 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
1663 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
1664 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
1665 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
1666
1667 /* Check the parameters */
1668 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1669
1670 /* Check the TIM channels state */
1671 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1672 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
1673 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1674 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
1675 {
1676 return HAL_ERROR;
1677 }
1678
1679 /* Set the TIM channels state */
1680 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1681 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1682 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1683 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1684
1685 /* Enable the TIM Capture/Compare 1 interrupt */
1686 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1687
1688 /* Enable the TIM Capture/Compare 2 interrupt */
1689 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1690
1691 /* Enable the complementary One Pulse output channel and the Input Capture channel */
1692 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
1693 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
1694
1695 /* Enable the Main Output */
1696 __HAL_TIM_MOE_ENABLE(htim);
1697
1698 /* Return function status */
1699 return HAL_OK;
1700 }
1701
1702 /**
1703 * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
1704 * complementary channel.
1705 * @note OutputChannel must match the pulse output channel chosen when calling
1706 * @ref HAL_TIM_OnePulse_ConfigChannel().
1707 * @param htim TIM One Pulse handle
1708 * @param OutputChannel pulse output channel to disable
1709 * This parameter can be one of the following values:
1710 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1711 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1712 * @retval HAL status
1713 */
HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1714 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1715 {
1716 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1717
1718 /* Check the parameters */
1719 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1720
1721 /* Disable the TIM Capture/Compare 1 interrupt */
1722 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1723
1724 /* Disable the TIM Capture/Compare 2 interrupt */
1725 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1726
1727 /* Disable the complementary One Pulse output channel and the Input Capture channel */
1728 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
1729 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
1730
1731 /* Disable the Main Output */
1732 __HAL_TIM_MOE_DISABLE(htim);
1733
1734 /* Disable the Peripheral */
1735 __HAL_TIM_DISABLE(htim);
1736
1737 /* Set the TIM channels state */
1738 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1739 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1740 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1741 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1742
1743 /* Return function status */
1744 return HAL_OK;
1745 }
1746
1747 /**
1748 * @}
1749 */
1750
1751 /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
1752 * @brief Peripheral Control functions
1753 *
1754 @verbatim
1755 ==============================================================================
1756 ##### Peripheral Control functions #####
1757 ==============================================================================
1758 [..]
1759 This section provides functions allowing to:
1760 (+) Configure the commutation event in case of use of the Hall sensor interface.
1761 (+) Configure Output channels for OC and PWM mode.
1762
1763 (+) Configure Complementary channels, break features and dead time.
1764 (+) Configure Master synchronization.
1765 (+) Configure timer remapping capabilities.
1766 (+) Enable or disable channel grouping.
1767
1768 @endverbatim
1769 * @{
1770 */
1771
1772 /**
1773 * @brief Configure the TIM commutation event sequence.
1774 * @note This function is mandatory to use the commutation event in order to
1775 * update the configuration at each commutation detection on the TRGI input of the Timer,
1776 * the typical use of this feature is with the use of another Timer(interface Timer)
1777 * configured in Hall sensor interface, this interface Timer will generate the
1778 * commutation at its TRGO output (connected to Timer used in this function) each time
1779 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1780 * @param htim TIM handle
1781 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
1782 * This parameter can be one of the following values:
1783 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1784 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1785 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1786 * @arg TIM_TS_ITR3: Internal trigger 3 selected
1787 * @arg TIM_TS_NONE: No trigger is needed
1788 * @param CommutationSource the Commutation Event source
1789 * This parameter can be one of the following values:
1790 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1791 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1792 * @retval HAL status
1793 */
HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)1794 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
1795 uint32_t CommutationSource)
1796 {
1797 /* Check the parameters */
1798 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
1799 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
1800
1801 __HAL_LOCK(htim);
1802
1803 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1804 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
1805 {
1806 /* Select the Input trigger */
1807 htim->Instance->SMCR &= ~TIM_SMCR_TS;
1808 htim->Instance->SMCR |= InputTrigger;
1809 }
1810
1811 /* Select the Capture Compare preload feature */
1812 htim->Instance->CR2 |= TIM_CR2_CCPC;
1813 /* Select the Commutation event source */
1814 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
1815 htim->Instance->CR2 |= CommutationSource;
1816
1817 /* Disable Commutation Interrupt */
1818 __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
1819
1820 /* Disable Commutation DMA request */
1821 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
1822
1823 __HAL_UNLOCK(htim);
1824
1825 return HAL_OK;
1826 }
1827
1828 /**
1829 * @brief Configure the TIM commutation event sequence with interrupt.
1830 * @note This function is mandatory to use the commutation event in order to
1831 * update the configuration at each commutation detection on the TRGI input of the Timer,
1832 * the typical use of this feature is with the use of another Timer(interface Timer)
1833 * configured in Hall sensor interface, this interface Timer will generate the
1834 * commutation at its TRGO output (connected to Timer used in this function) each time
1835 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1836 * @param htim TIM handle
1837 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
1838 * This parameter can be one of the following values:
1839 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1840 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1841 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1842 * @arg TIM_TS_ITR3: Internal trigger 3 selected
1843 * @arg TIM_TS_NONE: No trigger is needed
1844 * @param CommutationSource the Commutation Event source
1845 * This parameter can be one of the following values:
1846 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1847 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1848 * @retval HAL status
1849 */
HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)1850 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
1851 uint32_t CommutationSource)
1852 {
1853 /* Check the parameters */
1854 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
1855 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
1856
1857 __HAL_LOCK(htim);
1858
1859 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1860 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
1861 {
1862 /* Select the Input trigger */
1863 htim->Instance->SMCR &= ~TIM_SMCR_TS;
1864 htim->Instance->SMCR |= InputTrigger;
1865 }
1866
1867 /* Select the Capture Compare preload feature */
1868 htim->Instance->CR2 |= TIM_CR2_CCPC;
1869 /* Select the Commutation event source */
1870 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
1871 htim->Instance->CR2 |= CommutationSource;
1872
1873 /* Disable Commutation DMA request */
1874 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
1875
1876 /* Enable the Commutation Interrupt */
1877 __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
1878
1879 __HAL_UNLOCK(htim);
1880
1881 return HAL_OK;
1882 }
1883
1884 /**
1885 * @brief Configure the TIM commutation event sequence with DMA.
1886 * @note This function is mandatory to use the commutation event in order to
1887 * update the configuration at each commutation detection on the TRGI input of the Timer,
1888 * the typical use of this feature is with the use of another Timer(interface Timer)
1889 * configured in Hall sensor interface, this interface Timer will generate the
1890 * commutation at its TRGO output (connected to Timer used in this function) each time
1891 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1892 * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set
1893 * @param htim TIM handle
1894 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
1895 * This parameter can be one of the following values:
1896 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1897 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1898 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1899 * @arg TIM_TS_ITR3: Internal trigger 3 selected
1900 * @arg TIM_TS_NONE: No trigger is needed
1901 * @param CommutationSource the Commutation Event source
1902 * This parameter can be one of the following values:
1903 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1904 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1905 * @retval HAL status
1906 */
HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)1907 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
1908 uint32_t CommutationSource)
1909 {
1910 /* Check the parameters */
1911 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
1912 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
1913
1914 __HAL_LOCK(htim);
1915
1916 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1917 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
1918 {
1919 /* Select the Input trigger */
1920 htim->Instance->SMCR &= ~TIM_SMCR_TS;
1921 htim->Instance->SMCR |= InputTrigger;
1922 }
1923
1924 /* Select the Capture Compare preload feature */
1925 htim->Instance->CR2 |= TIM_CR2_CCPC;
1926 /* Select the Commutation event source */
1927 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
1928 htim->Instance->CR2 |= CommutationSource;
1929
1930 /* Enable the Commutation DMA Request */
1931 /* Set the DMA Commutation Callback */
1932 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
1933 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
1934 /* Set the DMA error callback */
1935 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
1936
1937 /* Disable Commutation Interrupt */
1938 __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
1939
1940 /* Enable the Commutation DMA Request */
1941 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
1942
1943 __HAL_UNLOCK(htim);
1944
1945 return HAL_OK;
1946 }
1947
1948 /**
1949 * @brief Configures the TIM in master mode.
1950 * @param htim TIM handle.
1951 * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
1952 * contains the selected trigger output (TRGO) and the Master/Slave
1953 * mode.
1954 * @retval HAL status
1955 */
HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef * htim,const TIM_MasterConfigTypeDef * sMasterConfig)1956 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
1957 const TIM_MasterConfigTypeDef *sMasterConfig)
1958 {
1959 uint32_t tmpcr2;
1960 uint32_t tmpsmcr;
1961
1962 /* Check the parameters */
1963 assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
1964 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
1965 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
1966
1967 /* Check input state */
1968 __HAL_LOCK(htim);
1969
1970 /* Change the handler state */
1971 htim->State = HAL_TIM_STATE_BUSY;
1972
1973 /* Get the TIMx CR2 register value */
1974 tmpcr2 = htim->Instance->CR2;
1975
1976 /* Get the TIMx SMCR register value */
1977 tmpsmcr = htim->Instance->SMCR;
1978
1979 /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
1980 if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
1981 {
1982 /* Check the parameters */
1983 assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
1984
1985 /* Clear the MMS2 bits */
1986 tmpcr2 &= ~TIM_CR2_MMS2;
1987 /* Select the TRGO2 source*/
1988 tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
1989 }
1990
1991 /* Reset the MMS Bits */
1992 tmpcr2 &= ~TIM_CR2_MMS;
1993 /* Select the TRGO source */
1994 tmpcr2 |= sMasterConfig->MasterOutputTrigger;
1995
1996 /* Update TIMx CR2 */
1997 htim->Instance->CR2 = tmpcr2;
1998
1999 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2000 {
2001 /* Reset the MSM Bit */
2002 tmpsmcr &= ~TIM_SMCR_MSM;
2003 /* Set master mode */
2004 tmpsmcr |= sMasterConfig->MasterSlaveMode;
2005
2006 /* Update TIMx SMCR */
2007 htim->Instance->SMCR = tmpsmcr;
2008 }
2009
2010 /* Change the htim state */
2011 htim->State = HAL_TIM_STATE_READY;
2012
2013 __HAL_UNLOCK(htim);
2014
2015 return HAL_OK;
2016 }
2017
2018 /**
2019 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
2020 * and the AOE(automatic output enable).
2021 * @param htim TIM handle
2022 * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
2023 * contains the BDTR Register configuration information for the TIM peripheral.
2024 * @note Interrupts can be generated when an active level is detected on the
2025 * break input, the break 2 input or the system break input. Break
2026 * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
2027 * @retval HAL status
2028 */
HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef * htim,const TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)2029 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
2030 const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
2031 {
2032 /* Keep this variable initialized to 0 as it is used to configure BDTR register */
2033 uint32_t tmpbdtr = 0U;
2034
2035 /* Check the parameters */
2036 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2037 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
2038 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
2039 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
2040 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
2041 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
2042 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
2043 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
2044 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
2045
2046 /* Check input state */
2047 __HAL_LOCK(htim);
2048
2049 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
2050 the OSSI State, the dead time value and the Automatic Output Enable Bit */
2051
2052 /* Set the BDTR bits */
2053 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
2054 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
2055 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
2056 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
2057 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
2058 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
2059 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
2060 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
2061
2062 if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
2063 {
2064 /* Check the parameters */
2065 assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
2066 assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
2067 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
2068
2069 /* Set the BREAK2 input related BDTR bits */
2070 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
2071 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
2072 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
2073 }
2074
2075 /* Set TIMx_BDTR */
2076 htim->Instance->BDTR = tmpbdtr;
2077
2078 __HAL_UNLOCK(htim);
2079
2080 return HAL_OK;
2081 }
2082 #if defined(TIM_BREAK_INPUT_SUPPORT)
2083
2084 /**
2085 * @brief Configures the break input source.
2086 * @param htim TIM handle.
2087 * @param BreakInput Break input to configure
2088 * This parameter can be one of the following values:
2089 * @arg TIM_BREAKINPUT_BRK: Timer break input
2090 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
2091 * @param sBreakInputConfig Break input source configuration
2092 * @retval HAL status
2093 */
HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef * htim,uint32_t BreakInput,const TIMEx_BreakInputConfigTypeDef * sBreakInputConfig)2094 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
2095 uint32_t BreakInput,
2096 const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
2097 {
2098 HAL_StatusTypeDef status = HAL_OK;
2099 uint32_t tmporx;
2100 uint32_t bkin_enable_mask;
2101 uint32_t bkin_polarity_mask;
2102 uint32_t bkin_enable_bitpos;
2103 uint32_t bkin_polarity_bitpos;
2104
2105 /* Check the parameters */
2106 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2107 assert_param(IS_TIM_BREAKINPUT(BreakInput));
2108 assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
2109 assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
2110 #if defined(DFSDM1_Channel0)
2111 if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
2112 {
2113 assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
2114 }
2115 #else
2116 assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
2117 #endif /* DFSDM1_Channel0 */
2118
2119 /* Check input state */
2120 __HAL_LOCK(htim);
2121
2122 switch (sBreakInputConfig->Source)
2123 {
2124 case TIM_BREAKINPUTSOURCE_BKIN:
2125 {
2126 bkin_enable_mask = TIM1_AF1_BKINE;
2127 bkin_enable_bitpos = TIM1_AF1_BKINE_Pos;
2128 bkin_polarity_mask = TIM1_AF1_BKINP;
2129 bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos;
2130 break;
2131 }
2132 #if defined(DFSDM1_Channel0)
2133 case TIM_BREAKINPUTSOURCE_DFSDM1:
2134 {
2135 bkin_enable_mask = TIM1_AF1_BKDF1BKE;
2136 bkin_enable_bitpos = TIM1_AF1_BKDF1BKE_Pos;
2137 bkin_polarity_mask = 0U;
2138 bkin_polarity_bitpos = 0U;
2139 break;
2140 }
2141 #endif /* DFSDM1_Channel0 */
2142
2143 default:
2144 {
2145 bkin_enable_mask = 0U;
2146 bkin_polarity_mask = 0U;
2147 bkin_enable_bitpos = 0U;
2148 bkin_polarity_bitpos = 0U;
2149 break;
2150 }
2151 }
2152
2153 switch (BreakInput)
2154 {
2155 case TIM_BREAKINPUT_BRK:
2156 {
2157 /* Get the TIMx_AF1 register value */
2158 tmporx = htim->Instance->AF1;
2159
2160 /* Enable the break input */
2161 tmporx &= ~bkin_enable_mask;
2162 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
2163
2164 /* Set the break input polarity */
2165 #if defined(DFSDM1_Channel0)
2166 if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
2167 #endif /* DFSDM1_Channel0 */
2168 {
2169 tmporx &= ~bkin_polarity_mask;
2170 tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
2171 }
2172
2173 /* Set TIMx_AF1 */
2174 htim->Instance->AF1 = tmporx;
2175 break;
2176 }
2177 case TIM_BREAKINPUT_BRK2:
2178 {
2179 /* Get the TIMx_AF2 register value */
2180 tmporx = htim->Instance->AF2;
2181
2182 /* Enable the break input */
2183 tmporx &= ~bkin_enable_mask;
2184 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
2185
2186 /* Set the break input polarity */
2187 #if defined(DFSDM1_Channel0)
2188 if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
2189 #endif /* DFSDM1_Channel0 */
2190 {
2191 tmporx &= ~bkin_polarity_mask;
2192 tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
2193 }
2194
2195 /* Set TIMx_AF2 */
2196 htim->Instance->AF2 = tmporx;
2197 break;
2198 }
2199 default:
2200 status = HAL_ERROR;
2201 break;
2202 }
2203
2204 __HAL_UNLOCK(htim);
2205
2206 return status;
2207 }
2208 #endif /*TIM_BREAK_INPUT_SUPPORT */
2209
2210 /**
2211 * @brief Configures the TIMx Remapping input capabilities.
2212 * @param htim TIM handle.
2213 * @param Remap specifies the TIM remapping source.
2214 * This parameter can be one of the following values:
2215 * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
2216 * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output.
2217 * @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.
2218 * @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.
2219 * @arg TIM_TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default)
2220 * @arg TIM_TIM5_LSI: TIM5 CH4 input is connected to LSI clock.
2221 * @arg TIM_TIM5_LSE: TIM5 CH4 input is connected to LSE clock.
2222 * @arg TIM_TIM5_RTC: TIM5 CH4 input is connected to RTC Output event.
2223 * @arg TIM_TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default)
2224 * @arg TIM_TIM11_SPDIF: SPDIF Frame synchronous
2225 * @arg TIM_TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock
2226 * (HSE divided by a programmable prescaler)
2227 * @arg TIM_TIM11_MCO1: TIM11 CH1 input is connected to MCO1
2228 *
2229 * @retval HAL status
2230 */
HAL_TIMEx_RemapConfig(TIM_HandleTypeDef * htim,uint32_t Remap)2231 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
2232 {
2233 /* Check parameters */
2234 assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
2235 assert_param(IS_TIM_REMAP(Remap));
2236
2237 __HAL_LOCK(htim);
2238
2239 /* Set the Timer remapping configuration */
2240 htim->Instance->OR = Remap;
2241
2242 htim->State = HAL_TIM_STATE_READY;
2243
2244 __HAL_UNLOCK(htim);
2245
2246 return HAL_OK;
2247 }
2248
2249 /**
2250 * @brief Group channel 5 and channel 1, 2 or 3
2251 * @param htim TIM handle.
2252 * @param Channels specifies the reference signal(s) the OC5REF is combined with.
2253 * This parameter can be any combination of the following values:
2254 * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
2255 * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
2256 * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
2257 * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
2258 * @retval HAL status
2259 */
HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef * htim,uint32_t Channels)2260 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
2261 {
2262 /* Check parameters */
2263 assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
2264 assert_param(IS_TIM_GROUPCH5(Channels));
2265
2266 /* Process Locked */
2267 __HAL_LOCK(htim);
2268
2269 htim->State = HAL_TIM_STATE_BUSY;
2270
2271 /* Clear GC5Cx bit fields */
2272 htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
2273
2274 /* Set GC5Cx bit fields */
2275 htim->Instance->CCR5 |= Channels;
2276
2277 /* Change the htim state */
2278 htim->State = HAL_TIM_STATE_READY;
2279
2280 __HAL_UNLOCK(htim);
2281
2282 return HAL_OK;
2283 }
2284
2285 /**
2286 * @}
2287 */
2288
2289 /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
2290 * @brief Extended Callbacks functions
2291 *
2292 @verbatim
2293 ==============================================================================
2294 ##### Extended Callbacks functions #####
2295 ==============================================================================
2296 [..]
2297 This section provides Extended TIM callback functions:
2298 (+) Timer Commutation callback
2299 (+) Timer Break callback
2300
2301 @endverbatim
2302 * @{
2303 */
2304
2305 /**
2306 * @brief Commutation callback in non-blocking mode
2307 * @param htim TIM handle
2308 * @retval None
2309 */
HAL_TIMEx_CommutCallback(TIM_HandleTypeDef * htim)2310 __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
2311 {
2312 /* Prevent unused argument(s) compilation warning */
2313 UNUSED(htim);
2314
2315 /* NOTE : This function should not be modified, when the callback is needed,
2316 the HAL_TIMEx_CommutCallback could be implemented in the user file
2317 */
2318 }
2319 /**
2320 * @brief Commutation half complete callback in non-blocking mode
2321 * @param htim TIM handle
2322 * @retval None
2323 */
HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef * htim)2324 __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
2325 {
2326 /* Prevent unused argument(s) compilation warning */
2327 UNUSED(htim);
2328
2329 /* NOTE : This function should not be modified, when the callback is needed,
2330 the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
2331 */
2332 }
2333
2334 /**
2335 * @brief Break detection callback in non-blocking mode
2336 * @param htim TIM handle
2337 * @retval None
2338 */
HAL_TIMEx_BreakCallback(TIM_HandleTypeDef * htim)2339 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
2340 {
2341 /* Prevent unused argument(s) compilation warning */
2342 UNUSED(htim);
2343
2344 /* NOTE : This function should not be modified, when the callback is needed,
2345 the HAL_TIMEx_BreakCallback could be implemented in the user file
2346 */
2347 }
2348
2349 /**
2350 * @brief Break2 detection callback in non blocking mode
2351 * @param htim: TIM handle
2352 * @retval None
2353 */
HAL_TIMEx_Break2Callback(TIM_HandleTypeDef * htim)2354 __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
2355 {
2356 /* Prevent unused argument(s) compilation warning */
2357 UNUSED(htim);
2358
2359 /* NOTE : This function Should not be modified, when the callback is needed,
2360 the HAL_TIMEx_Break2Callback could be implemented in the user file
2361 */
2362 }
2363 /**
2364 * @}
2365 */
2366
2367 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
2368 * @brief Extended Peripheral State functions
2369 *
2370 @verbatim
2371 ==============================================================================
2372 ##### Extended Peripheral State functions #####
2373 ==============================================================================
2374 [..]
2375 This subsection permits to get in run-time the status of the peripheral
2376 and the data flow.
2377
2378 @endverbatim
2379 * @{
2380 */
2381
2382 /**
2383 * @brief Return the TIM Hall Sensor interface handle state.
2384 * @param htim TIM Hall Sensor handle
2385 * @retval HAL state
2386 */
HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef * htim)2387 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim)
2388 {
2389 return htim->State;
2390 }
2391
2392 /**
2393 * @brief Return actual state of the TIM complementary channel.
2394 * @param htim TIM handle
2395 * @param ChannelN TIM Complementary channel
2396 * This parameter can be one of the following values:
2397 * @arg TIM_CHANNEL_1: TIM Channel 1
2398 * @arg TIM_CHANNEL_2: TIM Channel 2
2399 * @arg TIM_CHANNEL_3: TIM Channel 3
2400 * @retval TIM Complementary channel state
2401 */
HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef * htim,uint32_t ChannelN)2402 HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN)
2403 {
2404 HAL_TIM_ChannelStateTypeDef channel_state;
2405
2406 /* Check the parameters */
2407 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
2408
2409 channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
2410
2411 return channel_state;
2412 }
2413 /**
2414 * @}
2415 */
2416
2417 /**
2418 * @}
2419 */
2420
2421 /* Private functions ---------------------------------------------------------*/
2422 /** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
2423 * @{
2424 */
2425
2426 /**
2427 * @brief TIM DMA Commutation callback.
2428 * @param hdma pointer to DMA handle.
2429 * @retval None
2430 */
TIMEx_DMACommutationCplt(DMA_HandleTypeDef * hdma)2431 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
2432 {
2433 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2434
2435 /* Change the htim state */
2436 htim->State = HAL_TIM_STATE_READY;
2437
2438 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2439 htim->CommutationCallback(htim);
2440 #else
2441 HAL_TIMEx_CommutCallback(htim);
2442 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2443 }
2444
2445 /**
2446 * @brief TIM DMA Commutation half complete callback.
2447 * @param hdma pointer to DMA handle.
2448 * @retval None
2449 */
TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef * hdma)2450 void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
2451 {
2452 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2453
2454 /* Change the htim state */
2455 htim->State = HAL_TIM_STATE_READY;
2456
2457 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2458 htim->CommutationHalfCpltCallback(htim);
2459 #else
2460 HAL_TIMEx_CommutHalfCpltCallback(htim);
2461 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2462 }
2463
2464
2465 /**
2466 * @brief TIM DMA Delay Pulse complete callback (complementary channel).
2467 * @param hdma pointer to DMA handle.
2468 * @retval None
2469 */
TIM_DMADelayPulseNCplt(DMA_HandleTypeDef * hdma)2470 static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
2471 {
2472 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2473
2474 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
2475 {
2476 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
2477
2478 if (hdma->Init.Mode == DMA_NORMAL)
2479 {
2480 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2481 }
2482 }
2483 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
2484 {
2485 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
2486
2487 if (hdma->Init.Mode == DMA_NORMAL)
2488 {
2489 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2490 }
2491 }
2492 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
2493 {
2494 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
2495
2496 if (hdma->Init.Mode == DMA_NORMAL)
2497 {
2498 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
2499 }
2500 }
2501 else
2502 {
2503 /* nothing to do */
2504 }
2505
2506 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2507 htim->PWM_PulseFinishedCallback(htim);
2508 #else
2509 HAL_TIM_PWM_PulseFinishedCallback(htim);
2510 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2511
2512 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2513 }
2514
2515 /**
2516 * @brief TIM DMA error callback (complementary channel)
2517 * @param hdma pointer to DMA handle.
2518 * @retval None
2519 */
TIM_DMAErrorCCxN(DMA_HandleTypeDef * hdma)2520 static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
2521 {
2522 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2523
2524 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
2525 {
2526 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
2527 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2528 }
2529 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
2530 {
2531 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
2532 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2533 }
2534 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
2535 {
2536 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
2537 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
2538 }
2539 else
2540 {
2541 /* nothing to do */
2542 }
2543
2544 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2545 htim->ErrorCallback(htim);
2546 #else
2547 HAL_TIM_ErrorCallback(htim);
2548 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2549
2550 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2551 }
2552
2553 /**
2554 * @brief Enables or disables the TIM Capture Compare Channel xN.
2555 * @param TIMx to select the TIM peripheral
2556 * @param Channel specifies the TIM Channel
2557 * This parameter can be one of the following values:
2558 * @arg TIM_CHANNEL_1: TIM Channel 1
2559 * @arg TIM_CHANNEL_2: TIM Channel 2
2560 * @arg TIM_CHANNEL_3: TIM Channel 3
2561 * @param ChannelNState specifies the TIM Channel CCxNE bit new state.
2562 * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
2563 * @retval None
2564 */
TIM_CCxNChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelNState)2565 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
2566 {
2567 uint32_t tmp;
2568
2569 tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */
2570
2571 /* Reset the CCxNE Bit */
2572 TIMx->CCER &= ~tmp;
2573
2574 /* Set or reset the CCxNE Bit */
2575 TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */
2576 }
2577 /**
2578 * @}
2579 */
2580
2581 #endif /* HAL_TIM_MODULE_ENABLED */
2582 /**
2583 * @}
2584 */
2585
2586 /**
2587 * @}
2588 */
2589
