1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_tim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer (TIM) peripheral:
8 * + TIM Time Base Initialization
9 * + TIM Time Base Start
10 * + TIM Time Base Start Interruption
11 * + TIM Time Base Start DMA
12 * + TIM Output Compare/PWM Initialization
13 * + TIM Output Compare/PWM Channel Configuration
14 * + TIM Output Compare/PWM Start
15 * + TIM Output Compare/PWM Start Interruption
16 * + TIM Output Compare/PWM Start DMA
17 * + TIM Input Capture Initialization
18 * + TIM Input Capture Channel Configuration
19 * + TIM Input Capture Start
20 * + TIM Input Capture Start Interruption
21 * + TIM Input Capture Start DMA
22 * + TIM One Pulse Initialization
23 * + TIM One Pulse Channel Configuration
24 * + TIM One Pulse Start
25 * + TIM Encoder Interface Initialization
26 * + TIM Encoder Interface Start
27 * + TIM Encoder Interface Start Interruption
28 * + TIM Encoder Interface Start DMA
29 * + Commutation Event configuration with Interruption and DMA
30 * + TIM OCRef clear configuration
31 * + TIM External Clock configuration
32 ******************************************************************************
33 * @attention
34 *
35 * Copyright (c) 2017 STMicroelectronics.
36 * All rights reserved.
37 *
38 * This software is licensed under terms that can be found in the LICENSE file
39 * in the root directory of this software component.
40 * If no LICENSE file comes with this software, it is provided AS-IS.
41 *
42 ******************************************************************************
43 @verbatim
44 ==============================================================================
45 ##### TIMER Generic features #####
46 ==============================================================================
47 [..] The Timer features include:
48 (#) 16-bit up, down, up/down auto-reload counter.
49 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
50 counter clock frequency either by any factor between 1 and 65536.
51 (#) Up to 4 independent channels for:
52 (++) Input Capture
53 (++) Output Compare
54 (++) PWM generation (Edge and Center-aligned Mode)
55 (++) One-pulse mode output
56 (#) Synchronization circuit to control the timer with external signals and to interconnect
57 several timers together.
58 (#) Supports incremental encoder for positioning purposes
59
60 ##### How to use this driver #####
61 ==============================================================================
62 [..]
63 (#) Initialize the TIM low level resources by implementing the following functions
64 depending on the selected feature:
65 (++) Time Base : HAL_TIM_Base_MspInit()
66 (++) Input Capture : HAL_TIM_IC_MspInit()
67 (++) Output Compare : HAL_TIM_OC_MspInit()
68 (++) PWM generation : HAL_TIM_PWM_MspInit()
69 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
70 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
71
72 (#) Initialize the TIM low level resources :
73 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
74 (##) TIM pins configuration
75 (+++) Enable the clock for the TIM GPIOs using the following function:
76 __HAL_RCC_GPIOx_CLK_ENABLE();
77 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
78
79 (#) The external Clock can be configured, if needed (the default clock is the
80 internal clock from the APBx), using the following function:
81 HAL_TIM_ConfigClockSource, the clock configuration should be done before
82 any start function.
83
84 (#) Configure the TIM in the desired functioning mode using one of the
85 Initialization function of this driver:
86 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
87 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
88 Output Compare signal.
89 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
90 PWM signal.
91 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
92 external signal.
93 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
94 in One Pulse Mode.
95 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
96
97 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
98 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
99 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
100 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
101 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
102 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
103 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
104
105 (#) The DMA Burst is managed with the two following functions:
106 HAL_TIM_DMABurst_WriteStart()
107 HAL_TIM_DMABurst_ReadStart()
108
109 *** Callback registration ***
110 =============================================
111
112 [..]
113 The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
114 allows the user to configure dynamically the driver callbacks.
115
116 [..]
117 Use Function HAL_TIM_RegisterCallback() to register a callback.
118 HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
119 the Callback ID and a pointer to the user callback function.
120
121 [..]
122 Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
123 weak function.
124 HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
125 and the Callback ID.
126
127 [..]
128 These functions allow to register/unregister following callbacks:
129 (+) Base_MspInitCallback : TIM Base Msp Init Callback.
130 (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
131 (+) IC_MspInitCallback : TIM IC Msp Init Callback.
132 (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
133 (+) OC_MspInitCallback : TIM OC Msp Init Callback.
134 (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
135 (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
136 (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
137 (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
138 (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
139 (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
140 (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
141 (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
142 (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
143 (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
144 (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
145 (+) TriggerCallback : TIM Trigger Callback.
146 (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
147 (+) IC_CaptureCallback : TIM Input Capture Callback.
148 (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
149 (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
150 (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
151 (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
152 (+) ErrorCallback : TIM Error Callback.
153 (+) CommutationCallback : TIM Commutation Callback.
154 (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
155 (+) BreakCallback : TIM Break Callback.
156 (+) Break2Callback : TIM Break2 Callback.
157
158 [..]
159 By default, after the Init and when the state is HAL_TIM_STATE_RESET
160 all interrupt callbacks are set to the corresponding weak functions:
161 examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
162
163 [..]
164 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
165 functionalities in the Init / DeInit only when these callbacks are null
166 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
167 keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
168
169 [..]
170 Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
171 Exception done MspInit / MspDeInit that can be registered / unregistered
172 in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
173 thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
174 In that case first register the MspInit/MspDeInit user callbacks
175 using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
176
177 [..]
178 When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
179 not defined, the callback registration feature is not available and all callbacks
180 are set to the corresponding weak functions.
181
182 @endverbatim
183 ******************************************************************************
184 */
185
186 /* Includes ------------------------------------------------------------------*/
187 #include "stm32f7xx_hal.h"
188
189 /** @addtogroup STM32F7xx_HAL_Driver
190 * @{
191 */
192
193 /** @defgroup TIM TIM
194 * @brief TIM HAL module driver
195 * @{
196 */
197
198 #ifdef HAL_TIM_MODULE_ENABLED
199
200 /* Private typedef -----------------------------------------------------------*/
201 /* Private define ------------------------------------------------------------*/
202 /* Private macros ------------------------------------------------------------*/
203 /* Private variables ---------------------------------------------------------*/
204 /* Private function prototypes -----------------------------------------------*/
205 /** @addtogroup TIM_Private_Functions
206 * @{
207 */
208 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
209 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
210 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
211 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
212 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
213 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
214 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
215 uint32_t TIM_ICFilter);
216 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
217 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
218 uint32_t TIM_ICFilter);
219 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
220 uint32_t TIM_ICFilter);
221 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
222 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
223 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
224 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
225 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
226 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
227 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
228 const TIM_SlaveConfigTypeDef *sSlaveConfig);
229 /**
230 * @}
231 */
232 /* Exported functions --------------------------------------------------------*/
233
234 /** @defgroup TIM_Exported_Functions TIM Exported Functions
235 * @{
236 */
237
238 /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
239 * @brief Time Base functions
240 *
241 @verbatim
242 ==============================================================================
243 ##### Time Base functions #####
244 ==============================================================================
245 [..]
246 This section provides functions allowing to:
247 (+) Initialize and configure the TIM base.
248 (+) De-initialize the TIM base.
249 (+) Start the Time Base.
250 (+) Stop the Time Base.
251 (+) Start the Time Base and enable interrupt.
252 (+) Stop the Time Base and disable interrupt.
253 (+) Start the Time Base and enable DMA transfer.
254 (+) Stop the Time Base and disable DMA transfer.
255
256 @endverbatim
257 * @{
258 */
259 /**
260 * @brief Initializes the TIM Time base Unit according to the specified
261 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
262 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
263 * requires a timer reset to avoid unexpected direction
264 * due to DIR bit readonly in center aligned mode.
265 * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
266 * @param htim TIM Base handle
267 * @retval HAL status
268 */
HAL_TIM_Base_Init(TIM_HandleTypeDef * htim)269 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
270 {
271 /* Check the TIM handle allocation */
272 if (htim == NULL)
273 {
274 return HAL_ERROR;
275 }
276
277 /* Check the parameters */
278 assert_param(IS_TIM_INSTANCE(htim->Instance));
279 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
280 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
281 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
282 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
283
284 if (htim->State == HAL_TIM_STATE_RESET)
285 {
286 /* Allocate lock resource and initialize it */
287 htim->Lock = HAL_UNLOCKED;
288
289 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
290 /* Reset interrupt callbacks to legacy weak callbacks */
291 TIM_ResetCallback(htim);
292
293 if (htim->Base_MspInitCallback == NULL)
294 {
295 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
296 }
297 /* Init the low level hardware : GPIO, CLOCK, NVIC */
298 htim->Base_MspInitCallback(htim);
299 #else
300 /* Init the low level hardware : GPIO, CLOCK, NVIC */
301 HAL_TIM_Base_MspInit(htim);
302 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
303 }
304
305 /* Set the TIM state */
306 htim->State = HAL_TIM_STATE_BUSY;
307
308 /* Set the Time Base configuration */
309 TIM_Base_SetConfig(htim->Instance, &htim->Init);
310
311 /* Initialize the DMA burst operation state */
312 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
313
314 /* Initialize the TIM channels state */
315 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
316 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
317
318 /* Initialize the TIM state*/
319 htim->State = HAL_TIM_STATE_READY;
320
321 return HAL_OK;
322 }
323
324 /**
325 * @brief DeInitializes the TIM Base peripheral
326 * @param htim TIM Base handle
327 * @retval HAL status
328 */
HAL_TIM_Base_DeInit(TIM_HandleTypeDef * htim)329 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
330 {
331 /* Check the parameters */
332 assert_param(IS_TIM_INSTANCE(htim->Instance));
333
334 htim->State = HAL_TIM_STATE_BUSY;
335
336 /* Disable the TIM Peripheral Clock */
337 __HAL_TIM_DISABLE(htim);
338
339 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
340 if (htim->Base_MspDeInitCallback == NULL)
341 {
342 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
343 }
344 /* DeInit the low level hardware */
345 htim->Base_MspDeInitCallback(htim);
346 #else
347 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
348 HAL_TIM_Base_MspDeInit(htim);
349 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
350
351 /* Change the DMA burst operation state */
352 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
353
354 /* Change the TIM channels state */
355 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
356 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
357
358 /* Change TIM state */
359 htim->State = HAL_TIM_STATE_RESET;
360
361 /* Release Lock */
362 __HAL_UNLOCK(htim);
363
364 return HAL_OK;
365 }
366
367 /**
368 * @brief Initializes the TIM Base MSP.
369 * @param htim TIM Base handle
370 * @retval None
371 */
HAL_TIM_Base_MspInit(TIM_HandleTypeDef * htim)372 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
373 {
374 /* Prevent unused argument(s) compilation warning */
375 UNUSED(htim);
376
377 /* NOTE : This function should not be modified, when the callback is needed,
378 the HAL_TIM_Base_MspInit could be implemented in the user file
379 */
380 }
381
382 /**
383 * @brief DeInitializes TIM Base MSP.
384 * @param htim TIM Base handle
385 * @retval None
386 */
HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef * htim)387 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
388 {
389 /* Prevent unused argument(s) compilation warning */
390 UNUSED(htim);
391
392 /* NOTE : This function should not be modified, when the callback is needed,
393 the HAL_TIM_Base_MspDeInit could be implemented in the user file
394 */
395 }
396
397
398 /**
399 * @brief Starts the TIM Base generation.
400 * @param htim TIM Base handle
401 * @retval HAL status
402 */
HAL_TIM_Base_Start(TIM_HandleTypeDef * htim)403 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
404 {
405 uint32_t tmpsmcr;
406
407 /* Check the parameters */
408 assert_param(IS_TIM_INSTANCE(htim->Instance));
409
410 /* Check the TIM state */
411 if (htim->State != HAL_TIM_STATE_READY)
412 {
413 return HAL_ERROR;
414 }
415
416 /* Set the TIM state */
417 htim->State = HAL_TIM_STATE_BUSY;
418
419 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
420 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
421 {
422 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
423 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
424 {
425 __HAL_TIM_ENABLE(htim);
426 }
427 }
428 else
429 {
430 __HAL_TIM_ENABLE(htim);
431 }
432
433 /* Return function status */
434 return HAL_OK;
435 }
436
437 /**
438 * @brief Stops the TIM Base generation.
439 * @param htim TIM Base handle
440 * @retval HAL status
441 */
HAL_TIM_Base_Stop(TIM_HandleTypeDef * htim)442 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
443 {
444 /* Check the parameters */
445 assert_param(IS_TIM_INSTANCE(htim->Instance));
446
447 /* Disable the Peripheral */
448 __HAL_TIM_DISABLE(htim);
449
450 /* Set the TIM state */
451 htim->State = HAL_TIM_STATE_READY;
452
453 /* Return function status */
454 return HAL_OK;
455 }
456
457 /**
458 * @brief Starts the TIM Base generation in interrupt mode.
459 * @param htim TIM Base handle
460 * @retval HAL status
461 */
HAL_TIM_Base_Start_IT(TIM_HandleTypeDef * htim)462 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
463 {
464 uint32_t tmpsmcr;
465
466 /* Check the parameters */
467 assert_param(IS_TIM_INSTANCE(htim->Instance));
468
469 /* Check the TIM state */
470 if (htim->State != HAL_TIM_STATE_READY)
471 {
472 return HAL_ERROR;
473 }
474
475 /* Set the TIM state */
476 htim->State = HAL_TIM_STATE_BUSY;
477
478 /* Enable the TIM Update interrupt */
479 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
480
481 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
482 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
483 {
484 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
485 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
486 {
487 __HAL_TIM_ENABLE(htim);
488 }
489 }
490 else
491 {
492 __HAL_TIM_ENABLE(htim);
493 }
494
495 /* Return function status */
496 return HAL_OK;
497 }
498
499 /**
500 * @brief Stops the TIM Base generation in interrupt mode.
501 * @param htim TIM Base handle
502 * @retval HAL status
503 */
HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef * htim)504 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
505 {
506 /* Check the parameters */
507 assert_param(IS_TIM_INSTANCE(htim->Instance));
508
509 /* Disable the TIM Update interrupt */
510 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
511
512 /* Disable the Peripheral */
513 __HAL_TIM_DISABLE(htim);
514
515 /* Set the TIM state */
516 htim->State = HAL_TIM_STATE_READY;
517
518 /* Return function status */
519 return HAL_OK;
520 }
521
522 /**
523 * @brief Starts the TIM Base generation in DMA mode.
524 * @param htim TIM Base handle
525 * @param pData The source Buffer address.
526 * @param Length The length of data to be transferred from memory to peripheral.
527 * @retval HAL status
528 */
HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef * htim,const uint32_t * pData,uint16_t Length)529 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
530 {
531 uint32_t tmpsmcr;
532
533 /* Check the parameters */
534 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
535
536 /* Set the TIM state */
537 if (htim->State == HAL_TIM_STATE_BUSY)
538 {
539 return HAL_BUSY;
540 }
541 else if (htim->State == HAL_TIM_STATE_READY)
542 {
543 if ((pData == NULL) || (Length == 0U))
544 {
545 return HAL_ERROR;
546 }
547 else
548 {
549 htim->State = HAL_TIM_STATE_BUSY;
550 }
551 }
552 else
553 {
554 return HAL_ERROR;
555 }
556
557 /* Set the DMA Period elapsed callbacks */
558 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
559 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
560
561 /* Set the DMA error callback */
562 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
563
564 /* Enable the DMA stream */
565 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
566 Length) != HAL_OK)
567 {
568 /* Return error status */
569 return HAL_ERROR;
570 }
571
572 /* Enable the TIM Update DMA request */
573 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
574
575 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
576 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
577 {
578 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
579 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
580 {
581 __HAL_TIM_ENABLE(htim);
582 }
583 }
584 else
585 {
586 __HAL_TIM_ENABLE(htim);
587 }
588
589 /* Return function status */
590 return HAL_OK;
591 }
592
593 /**
594 * @brief Stops the TIM Base generation in DMA mode.
595 * @param htim TIM Base handle
596 * @retval HAL status
597 */
HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef * htim)598 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
599 {
600 /* Check the parameters */
601 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
602
603 /* Disable the TIM Update DMA request */
604 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
605
606 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
607
608 /* Disable the Peripheral */
609 __HAL_TIM_DISABLE(htim);
610
611 /* Set the TIM state */
612 htim->State = HAL_TIM_STATE_READY;
613
614 /* Return function status */
615 return HAL_OK;
616 }
617
618 /**
619 * @}
620 */
621
622 /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
623 * @brief TIM Output Compare functions
624 *
625 @verbatim
626 ==============================================================================
627 ##### TIM Output Compare functions #####
628 ==============================================================================
629 [..]
630 This section provides functions allowing to:
631 (+) Initialize and configure the TIM Output Compare.
632 (+) De-initialize the TIM Output Compare.
633 (+) Start the TIM Output Compare.
634 (+) Stop the TIM Output Compare.
635 (+) Start the TIM Output Compare and enable interrupt.
636 (+) Stop the TIM Output Compare and disable interrupt.
637 (+) Start the TIM Output Compare and enable DMA transfer.
638 (+) Stop the TIM Output Compare and disable DMA transfer.
639
640 @endverbatim
641 * @{
642 */
643 /**
644 * @brief Initializes the TIM Output Compare according to the specified
645 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
646 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
647 * requires a timer reset to avoid unexpected direction
648 * due to DIR bit readonly in center aligned mode.
649 * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
650 * @param htim TIM Output Compare handle
651 * @retval HAL status
652 */
HAL_TIM_OC_Init(TIM_HandleTypeDef * htim)653 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
654 {
655 /* Check the TIM handle allocation */
656 if (htim == NULL)
657 {
658 return HAL_ERROR;
659 }
660
661 /* Check the parameters */
662 assert_param(IS_TIM_INSTANCE(htim->Instance));
663 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
664 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
665 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
666 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
667
668 if (htim->State == HAL_TIM_STATE_RESET)
669 {
670 /* Allocate lock resource and initialize it */
671 htim->Lock = HAL_UNLOCKED;
672
673 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
674 /* Reset interrupt callbacks to legacy weak callbacks */
675 TIM_ResetCallback(htim);
676
677 if (htim->OC_MspInitCallback == NULL)
678 {
679 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
680 }
681 /* Init the low level hardware : GPIO, CLOCK, NVIC */
682 htim->OC_MspInitCallback(htim);
683 #else
684 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
685 HAL_TIM_OC_MspInit(htim);
686 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
687 }
688
689 /* Set the TIM state */
690 htim->State = HAL_TIM_STATE_BUSY;
691
692 /* Init the base time for the Output Compare */
693 TIM_Base_SetConfig(htim->Instance, &htim->Init);
694
695 /* Initialize the DMA burst operation state */
696 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
697
698 /* Initialize the TIM channels state */
699 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
700 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
701
702 /* Initialize the TIM state*/
703 htim->State = HAL_TIM_STATE_READY;
704
705 return HAL_OK;
706 }
707
708 /**
709 * @brief DeInitializes the TIM peripheral
710 * @param htim TIM Output Compare handle
711 * @retval HAL status
712 */
HAL_TIM_OC_DeInit(TIM_HandleTypeDef * htim)713 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
714 {
715 /* Check the parameters */
716 assert_param(IS_TIM_INSTANCE(htim->Instance));
717
718 htim->State = HAL_TIM_STATE_BUSY;
719
720 /* Disable the TIM Peripheral Clock */
721 __HAL_TIM_DISABLE(htim);
722
723 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
724 if (htim->OC_MspDeInitCallback == NULL)
725 {
726 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
727 }
728 /* DeInit the low level hardware */
729 htim->OC_MspDeInitCallback(htim);
730 #else
731 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
732 HAL_TIM_OC_MspDeInit(htim);
733 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
734
735 /* Change the DMA burst operation state */
736 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
737
738 /* Change the TIM channels state */
739 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
740 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
741
742 /* Change TIM state */
743 htim->State = HAL_TIM_STATE_RESET;
744
745 /* Release Lock */
746 __HAL_UNLOCK(htim);
747
748 return HAL_OK;
749 }
750
751 /**
752 * @brief Initializes the TIM Output Compare MSP.
753 * @param htim TIM Output Compare handle
754 * @retval None
755 */
HAL_TIM_OC_MspInit(TIM_HandleTypeDef * htim)756 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
757 {
758 /* Prevent unused argument(s) compilation warning */
759 UNUSED(htim);
760
761 /* NOTE : This function should not be modified, when the callback is needed,
762 the HAL_TIM_OC_MspInit could be implemented in the user file
763 */
764 }
765
766 /**
767 * @brief DeInitializes TIM Output Compare MSP.
768 * @param htim TIM Output Compare handle
769 * @retval None
770 */
HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef * htim)771 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
772 {
773 /* Prevent unused argument(s) compilation warning */
774 UNUSED(htim);
775
776 /* NOTE : This function should not be modified, when the callback is needed,
777 the HAL_TIM_OC_MspDeInit could be implemented in the user file
778 */
779 }
780
781 /**
782 * @brief Starts the TIM Output Compare signal generation.
783 * @param htim TIM Output Compare handle
784 * @param Channel TIM Channel to be enabled
785 * This parameter can be one of the following values:
786 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
787 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
788 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
789 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
790 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
791 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
792 * @retval HAL status
793 */
HAL_TIM_OC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)794 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
795 {
796 uint32_t tmpsmcr;
797
798 /* Check the parameters */
799 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
800
801 /* Check the TIM channel state */
802 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
803 {
804 return HAL_ERROR;
805 }
806
807 /* Set the TIM channel state */
808 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
809
810 /* Enable the Output compare channel */
811 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
812
813 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
814 {
815 /* Enable the main output */
816 __HAL_TIM_MOE_ENABLE(htim);
817 }
818
819 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
820 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
821 {
822 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
823 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
824 {
825 __HAL_TIM_ENABLE(htim);
826 }
827 }
828 else
829 {
830 __HAL_TIM_ENABLE(htim);
831 }
832
833 /* Return function status */
834 return HAL_OK;
835 }
836
837 /**
838 * @brief Stops the TIM Output Compare signal generation.
839 * @param htim TIM Output Compare handle
840 * @param Channel TIM Channel to be disabled
841 * This parameter can be one of the following values:
842 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
843 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
844 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
845 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
846 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
847 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
848 * @retval HAL status
849 */
HAL_TIM_OC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)850 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
851 {
852 /* Check the parameters */
853 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
854
855 /* Disable the Output compare channel */
856 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
857
858 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
859 {
860 /* Disable the Main Output */
861 __HAL_TIM_MOE_DISABLE(htim);
862 }
863
864 /* Disable the Peripheral */
865 __HAL_TIM_DISABLE(htim);
866
867 /* Set the TIM channel state */
868 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
869
870 /* Return function status */
871 return HAL_OK;
872 }
873
874 /**
875 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
876 * @param htim TIM Output Compare handle
877 * @param Channel TIM Channel to be enabled
878 * This parameter can be one of the following values:
879 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
880 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
881 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
882 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
883 * @retval HAL status
884 */
HAL_TIM_OC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)885 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
886 {
887 HAL_StatusTypeDef status = HAL_OK;
888 uint32_t tmpsmcr;
889
890 /* Check the parameters */
891 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
892
893 /* Check the TIM channel state */
894 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
895 {
896 return HAL_ERROR;
897 }
898
899 /* Set the TIM channel state */
900 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
901
902 switch (Channel)
903 {
904 case TIM_CHANNEL_1:
905 {
906 /* Enable the TIM Capture/Compare 1 interrupt */
907 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
908 break;
909 }
910
911 case TIM_CHANNEL_2:
912 {
913 /* Enable the TIM Capture/Compare 2 interrupt */
914 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
915 break;
916 }
917
918 case TIM_CHANNEL_3:
919 {
920 /* Enable the TIM Capture/Compare 3 interrupt */
921 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
922 break;
923 }
924
925 case TIM_CHANNEL_4:
926 {
927 /* Enable the TIM Capture/Compare 4 interrupt */
928 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
929 break;
930 }
931
932 default:
933 status = HAL_ERROR;
934 break;
935 }
936
937 if (status == HAL_OK)
938 {
939 /* Enable the Output compare channel */
940 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
941
942 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
943 {
944 /* Enable the main output */
945 __HAL_TIM_MOE_ENABLE(htim);
946 }
947
948 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
949 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
950 {
951 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
952 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
953 {
954 __HAL_TIM_ENABLE(htim);
955 }
956 }
957 else
958 {
959 __HAL_TIM_ENABLE(htim);
960 }
961 }
962
963 /* Return function status */
964 return status;
965 }
966
967 /**
968 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
969 * @param htim TIM Output Compare handle
970 * @param Channel TIM Channel to be disabled
971 * This parameter can be one of the following values:
972 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
973 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
974 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
975 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
976 * @retval HAL status
977 */
HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)978 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
979 {
980 HAL_StatusTypeDef status = HAL_OK;
981
982 /* Check the parameters */
983 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
984
985 switch (Channel)
986 {
987 case TIM_CHANNEL_1:
988 {
989 /* Disable the TIM Capture/Compare 1 interrupt */
990 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
991 break;
992 }
993
994 case TIM_CHANNEL_2:
995 {
996 /* Disable the TIM Capture/Compare 2 interrupt */
997 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
998 break;
999 }
1000
1001 case TIM_CHANNEL_3:
1002 {
1003 /* Disable the TIM Capture/Compare 3 interrupt */
1004 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1005 break;
1006 }
1007
1008 case TIM_CHANNEL_4:
1009 {
1010 /* Disable the TIM Capture/Compare 4 interrupt */
1011 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1012 break;
1013 }
1014
1015 default:
1016 status = HAL_ERROR;
1017 break;
1018 }
1019
1020 if (status == HAL_OK)
1021 {
1022 /* Disable the Output compare channel */
1023 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1024
1025 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1026 {
1027 /* Disable the Main Output */
1028 __HAL_TIM_MOE_DISABLE(htim);
1029 }
1030
1031 /* Disable the Peripheral */
1032 __HAL_TIM_DISABLE(htim);
1033
1034 /* Set the TIM channel state */
1035 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1036 }
1037
1038 /* Return function status */
1039 return status;
1040 }
1041
1042 /**
1043 * @brief Starts the TIM Output Compare signal generation in DMA mode.
1044 * @param htim TIM Output Compare handle
1045 * @param Channel TIM Channel to be enabled
1046 * This parameter can be one of the following values:
1047 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1048 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1049 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1050 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1051 * @param pData The source Buffer address.
1052 * @param Length The length of data to be transferred from memory to TIM peripheral
1053 * @retval HAL status
1054 */
HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1055 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1056 uint16_t Length)
1057 {
1058 HAL_StatusTypeDef status = HAL_OK;
1059 uint32_t tmpsmcr;
1060
1061 /* Check the parameters */
1062 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1063
1064 /* Set the TIM channel state */
1065 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1066 {
1067 return HAL_BUSY;
1068 }
1069 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1070 {
1071 if ((pData == NULL) || (Length == 0U))
1072 {
1073 return HAL_ERROR;
1074 }
1075 else
1076 {
1077 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1078 }
1079 }
1080 else
1081 {
1082 return HAL_ERROR;
1083 }
1084
1085 switch (Channel)
1086 {
1087 case TIM_CHANNEL_1:
1088 {
1089 /* Set the DMA compare callbacks */
1090 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1091 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1092
1093 /* Set the DMA error callback */
1094 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1095
1096 /* Enable the DMA stream */
1097 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1098 Length) != HAL_OK)
1099 {
1100 /* Return error status */
1101 return HAL_ERROR;
1102 }
1103
1104 /* Enable the TIM Capture/Compare 1 DMA request */
1105 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1106 break;
1107 }
1108
1109 case TIM_CHANNEL_2:
1110 {
1111 /* Set the DMA compare callbacks */
1112 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1113 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1114
1115 /* Set the DMA error callback */
1116 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1117
1118 /* Enable the DMA stream */
1119 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1120 Length) != HAL_OK)
1121 {
1122 /* Return error status */
1123 return HAL_ERROR;
1124 }
1125
1126 /* Enable the TIM Capture/Compare 2 DMA request */
1127 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1128 break;
1129 }
1130
1131 case TIM_CHANNEL_3:
1132 {
1133 /* Set the DMA compare callbacks */
1134 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1135 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1136
1137 /* Set the DMA error callback */
1138 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1139
1140 /* Enable the DMA stream */
1141 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1142 Length) != HAL_OK)
1143 {
1144 /* Return error status */
1145 return HAL_ERROR;
1146 }
1147 /* Enable the TIM Capture/Compare 3 DMA request */
1148 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1149 break;
1150 }
1151
1152 case TIM_CHANNEL_4:
1153 {
1154 /* Set the DMA compare callbacks */
1155 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1156 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1157
1158 /* Set the DMA error callback */
1159 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1160
1161 /* Enable the DMA stream */
1162 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1163 Length) != HAL_OK)
1164 {
1165 /* Return error status */
1166 return HAL_ERROR;
1167 }
1168 /* Enable the TIM Capture/Compare 4 DMA request */
1169 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1170 break;
1171 }
1172
1173 default:
1174 status = HAL_ERROR;
1175 break;
1176 }
1177
1178 if (status == HAL_OK)
1179 {
1180 /* Enable the Output compare channel */
1181 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1182
1183 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1184 {
1185 /* Enable the main output */
1186 __HAL_TIM_MOE_ENABLE(htim);
1187 }
1188
1189 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1190 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1191 {
1192 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1193 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1194 {
1195 __HAL_TIM_ENABLE(htim);
1196 }
1197 }
1198 else
1199 {
1200 __HAL_TIM_ENABLE(htim);
1201 }
1202 }
1203
1204 /* Return function status */
1205 return status;
1206 }
1207
1208 /**
1209 * @brief Stops the TIM Output Compare signal generation in DMA mode.
1210 * @param htim TIM Output Compare handle
1211 * @param Channel TIM Channel to be disabled
1212 * This parameter can be one of the following values:
1213 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1214 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1215 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1216 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1217 * @retval HAL status
1218 */
HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1219 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1220 {
1221 HAL_StatusTypeDef status = HAL_OK;
1222
1223 /* Check the parameters */
1224 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1225
1226 switch (Channel)
1227 {
1228 case TIM_CHANNEL_1:
1229 {
1230 /* Disable the TIM Capture/Compare 1 DMA request */
1231 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1232 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1233 break;
1234 }
1235
1236 case TIM_CHANNEL_2:
1237 {
1238 /* Disable the TIM Capture/Compare 2 DMA request */
1239 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1240 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1241 break;
1242 }
1243
1244 case TIM_CHANNEL_3:
1245 {
1246 /* Disable the TIM Capture/Compare 3 DMA request */
1247 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1248 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1249 break;
1250 }
1251
1252 case TIM_CHANNEL_4:
1253 {
1254 /* Disable the TIM Capture/Compare 4 interrupt */
1255 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1256 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1257 break;
1258 }
1259
1260 default:
1261 status = HAL_ERROR;
1262 break;
1263 }
1264
1265 if (status == HAL_OK)
1266 {
1267 /* Disable the Output compare channel */
1268 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1269
1270 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1271 {
1272 /* Disable the Main Output */
1273 __HAL_TIM_MOE_DISABLE(htim);
1274 }
1275
1276 /* Disable the Peripheral */
1277 __HAL_TIM_DISABLE(htim);
1278
1279 /* Set the TIM channel state */
1280 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1281 }
1282
1283 /* Return function status */
1284 return status;
1285 }
1286
1287 /**
1288 * @}
1289 */
1290
1291 /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
1292 * @brief TIM PWM functions
1293 *
1294 @verbatim
1295 ==============================================================================
1296 ##### TIM PWM functions #####
1297 ==============================================================================
1298 [..]
1299 This section provides functions allowing to:
1300 (+) Initialize and configure the TIM PWM.
1301 (+) De-initialize the TIM PWM.
1302 (+) Start the TIM PWM.
1303 (+) Stop the TIM PWM.
1304 (+) Start the TIM PWM and enable interrupt.
1305 (+) Stop the TIM PWM and disable interrupt.
1306 (+) Start the TIM PWM and enable DMA transfer.
1307 (+) Stop the TIM PWM and disable DMA transfer.
1308
1309 @endverbatim
1310 * @{
1311 */
1312 /**
1313 * @brief Initializes the TIM PWM Time Base according to the specified
1314 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1315 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1316 * requires a timer reset to avoid unexpected direction
1317 * due to DIR bit readonly in center aligned mode.
1318 * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
1319 * @param htim TIM PWM handle
1320 * @retval HAL status
1321 */
HAL_TIM_PWM_Init(TIM_HandleTypeDef * htim)1322 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
1323 {
1324 /* Check the TIM handle allocation */
1325 if (htim == NULL)
1326 {
1327 return HAL_ERROR;
1328 }
1329
1330 /* Check the parameters */
1331 assert_param(IS_TIM_INSTANCE(htim->Instance));
1332 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1333 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1334 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
1335 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1336
1337 if (htim->State == HAL_TIM_STATE_RESET)
1338 {
1339 /* Allocate lock resource and initialize it */
1340 htim->Lock = HAL_UNLOCKED;
1341
1342 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1343 /* Reset interrupt callbacks to legacy weak callbacks */
1344 TIM_ResetCallback(htim);
1345
1346 if (htim->PWM_MspInitCallback == NULL)
1347 {
1348 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
1349 }
1350 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1351 htim->PWM_MspInitCallback(htim);
1352 #else
1353 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1354 HAL_TIM_PWM_MspInit(htim);
1355 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1356 }
1357
1358 /* Set the TIM state */
1359 htim->State = HAL_TIM_STATE_BUSY;
1360
1361 /* Init the base time for the PWM */
1362 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1363
1364 /* Initialize the DMA burst operation state */
1365 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
1366
1367 /* Initialize the TIM channels state */
1368 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1369 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1370
1371 /* Initialize the TIM state*/
1372 htim->State = HAL_TIM_STATE_READY;
1373
1374 return HAL_OK;
1375 }
1376
1377 /**
1378 * @brief DeInitializes the TIM peripheral
1379 * @param htim TIM PWM handle
1380 * @retval HAL status
1381 */
HAL_TIM_PWM_DeInit(TIM_HandleTypeDef * htim)1382 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1383 {
1384 /* Check the parameters */
1385 assert_param(IS_TIM_INSTANCE(htim->Instance));
1386
1387 htim->State = HAL_TIM_STATE_BUSY;
1388
1389 /* Disable the TIM Peripheral Clock */
1390 __HAL_TIM_DISABLE(htim);
1391
1392 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1393 if (htim->PWM_MspDeInitCallback == NULL)
1394 {
1395 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
1396 }
1397 /* DeInit the low level hardware */
1398 htim->PWM_MspDeInitCallback(htim);
1399 #else
1400 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1401 HAL_TIM_PWM_MspDeInit(htim);
1402 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1403
1404 /* Change the DMA burst operation state */
1405 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
1406
1407 /* Change the TIM channels state */
1408 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1409 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1410
1411 /* Change TIM state */
1412 htim->State = HAL_TIM_STATE_RESET;
1413
1414 /* Release Lock */
1415 __HAL_UNLOCK(htim);
1416
1417 return HAL_OK;
1418 }
1419
1420 /**
1421 * @brief Initializes the TIM PWM MSP.
1422 * @param htim TIM PWM handle
1423 * @retval None
1424 */
HAL_TIM_PWM_MspInit(TIM_HandleTypeDef * htim)1425 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1426 {
1427 /* Prevent unused argument(s) compilation warning */
1428 UNUSED(htim);
1429
1430 /* NOTE : This function should not be modified, when the callback is needed,
1431 the HAL_TIM_PWM_MspInit could be implemented in the user file
1432 */
1433 }
1434
1435 /**
1436 * @brief DeInitializes TIM PWM MSP.
1437 * @param htim TIM PWM handle
1438 * @retval None
1439 */
HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef * htim)1440 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1441 {
1442 /* Prevent unused argument(s) compilation warning */
1443 UNUSED(htim);
1444
1445 /* NOTE : This function should not be modified, when the callback is needed,
1446 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1447 */
1448 }
1449
1450 /**
1451 * @brief Starts the PWM signal generation.
1452 * @param htim TIM handle
1453 * @param Channel TIM Channels to be enabled
1454 * This parameter can be one of the following values:
1455 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1456 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1457 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1458 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1459 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1460 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1461 * @retval HAL status
1462 */
HAL_TIM_PWM_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1463 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1464 {
1465 uint32_t tmpsmcr;
1466
1467 /* Check the parameters */
1468 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1469
1470 /* Check the TIM channel state */
1471 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1472 {
1473 return HAL_ERROR;
1474 }
1475
1476 /* Set the TIM channel state */
1477 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1478
1479 /* Enable the Capture compare channel */
1480 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1481
1482 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1483 {
1484 /* Enable the main output */
1485 __HAL_TIM_MOE_ENABLE(htim);
1486 }
1487
1488 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1489 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1490 {
1491 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1492 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1493 {
1494 __HAL_TIM_ENABLE(htim);
1495 }
1496 }
1497 else
1498 {
1499 __HAL_TIM_ENABLE(htim);
1500 }
1501
1502 /* Return function status */
1503 return HAL_OK;
1504 }
1505
1506 /**
1507 * @brief Stops the PWM signal generation.
1508 * @param htim TIM PWM handle
1509 * @param Channel TIM Channels to be disabled
1510 * This parameter can be one of the following values:
1511 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1512 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1513 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1514 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1515 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1516 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1517 * @retval HAL status
1518 */
HAL_TIM_PWM_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1519 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1520 {
1521 /* Check the parameters */
1522 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1523
1524 /* Disable the Capture compare channel */
1525 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1526
1527 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1528 {
1529 /* Disable the Main Output */
1530 __HAL_TIM_MOE_DISABLE(htim);
1531 }
1532
1533 /* Disable the Peripheral */
1534 __HAL_TIM_DISABLE(htim);
1535
1536 /* Set the TIM channel state */
1537 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1538
1539 /* Return function status */
1540 return HAL_OK;
1541 }
1542
1543 /**
1544 * @brief Starts the PWM signal generation in interrupt mode.
1545 * @param htim TIM PWM handle
1546 * @param Channel TIM Channel to be enabled
1547 * This parameter can be one of the following values:
1548 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1549 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1550 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1551 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1552 * @retval HAL status
1553 */
HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1554 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1555 {
1556 HAL_StatusTypeDef status = HAL_OK;
1557 uint32_t tmpsmcr;
1558
1559 /* Check the parameters */
1560 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1561
1562 /* Check the TIM channel state */
1563 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1564 {
1565 return HAL_ERROR;
1566 }
1567
1568 /* Set the TIM channel state */
1569 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1570
1571 switch (Channel)
1572 {
1573 case TIM_CHANNEL_1:
1574 {
1575 /* Enable the TIM Capture/Compare 1 interrupt */
1576 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1577 break;
1578 }
1579
1580 case TIM_CHANNEL_2:
1581 {
1582 /* Enable the TIM Capture/Compare 2 interrupt */
1583 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1584 break;
1585 }
1586
1587 case TIM_CHANNEL_3:
1588 {
1589 /* Enable the TIM Capture/Compare 3 interrupt */
1590 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1591 break;
1592 }
1593
1594 case TIM_CHANNEL_4:
1595 {
1596 /* Enable the TIM Capture/Compare 4 interrupt */
1597 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1598 break;
1599 }
1600
1601 default:
1602 status = HAL_ERROR;
1603 break;
1604 }
1605
1606 if (status == HAL_OK)
1607 {
1608 /* Enable the Capture compare channel */
1609 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1610
1611 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1612 {
1613 /* Enable the main output */
1614 __HAL_TIM_MOE_ENABLE(htim);
1615 }
1616
1617 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1618 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1619 {
1620 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1621 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1622 {
1623 __HAL_TIM_ENABLE(htim);
1624 }
1625 }
1626 else
1627 {
1628 __HAL_TIM_ENABLE(htim);
1629 }
1630 }
1631
1632 /* Return function status */
1633 return status;
1634 }
1635
1636 /**
1637 * @brief Stops the PWM signal generation in interrupt mode.
1638 * @param htim TIM PWM handle
1639 * @param Channel TIM Channels to be disabled
1640 * This parameter can be one of the following values:
1641 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1642 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1643 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1644 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1645 * @retval HAL status
1646 */
HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1647 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1648 {
1649 HAL_StatusTypeDef status = HAL_OK;
1650
1651 /* Check the parameters */
1652 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1653
1654 switch (Channel)
1655 {
1656 case TIM_CHANNEL_1:
1657 {
1658 /* Disable the TIM Capture/Compare 1 interrupt */
1659 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1660 break;
1661 }
1662
1663 case TIM_CHANNEL_2:
1664 {
1665 /* Disable the TIM Capture/Compare 2 interrupt */
1666 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1667 break;
1668 }
1669
1670 case TIM_CHANNEL_3:
1671 {
1672 /* Disable the TIM Capture/Compare 3 interrupt */
1673 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1674 break;
1675 }
1676
1677 case TIM_CHANNEL_4:
1678 {
1679 /* Disable the TIM Capture/Compare 4 interrupt */
1680 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1681 break;
1682 }
1683
1684 default:
1685 status = HAL_ERROR;
1686 break;
1687 }
1688
1689 if (status == HAL_OK)
1690 {
1691 /* Disable the Capture compare channel */
1692 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1693
1694 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1695 {
1696 /* Disable the Main Output */
1697 __HAL_TIM_MOE_DISABLE(htim);
1698 }
1699
1700 /* Disable the Peripheral */
1701 __HAL_TIM_DISABLE(htim);
1702
1703 /* Set the TIM channel state */
1704 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1705 }
1706
1707 /* Return function status */
1708 return status;
1709 }
1710
1711 /**
1712 * @brief Starts the TIM PWM signal generation in DMA mode.
1713 * @param htim TIM PWM handle
1714 * @param Channel TIM Channels to be enabled
1715 * This parameter can be one of the following values:
1716 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1717 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1718 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1719 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1720 * @param pData The source Buffer address.
1721 * @param Length The length of data to be transferred from memory to TIM peripheral
1722 * @retval HAL status
1723 */
HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1724 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1725 uint16_t Length)
1726 {
1727 HAL_StatusTypeDef status = HAL_OK;
1728 uint32_t tmpsmcr;
1729
1730 /* Check the parameters */
1731 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1732
1733 /* Set the TIM channel state */
1734 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1735 {
1736 return HAL_BUSY;
1737 }
1738 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1739 {
1740 if ((pData == NULL) || (Length == 0U))
1741 {
1742 return HAL_ERROR;
1743 }
1744 else
1745 {
1746 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1747 }
1748 }
1749 else
1750 {
1751 return HAL_ERROR;
1752 }
1753
1754 switch (Channel)
1755 {
1756 case TIM_CHANNEL_1:
1757 {
1758 /* Set the DMA compare callbacks */
1759 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1760 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1761
1762 /* Set the DMA error callback */
1763 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1764
1765 /* Enable the DMA stream */
1766 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1767 Length) != HAL_OK)
1768 {
1769 /* Return error status */
1770 return HAL_ERROR;
1771 }
1772
1773 /* Enable the TIM Capture/Compare 1 DMA request */
1774 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1775 break;
1776 }
1777
1778 case TIM_CHANNEL_2:
1779 {
1780 /* Set the DMA compare callbacks */
1781 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1782 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1783
1784 /* Set the DMA error callback */
1785 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1786
1787 /* Enable the DMA stream */
1788 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1789 Length) != HAL_OK)
1790 {
1791 /* Return error status */
1792 return HAL_ERROR;
1793 }
1794 /* Enable the TIM Capture/Compare 2 DMA request */
1795 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1796 break;
1797 }
1798
1799 case TIM_CHANNEL_3:
1800 {
1801 /* Set the DMA compare callbacks */
1802 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1803 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1804
1805 /* Set the DMA error callback */
1806 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1807
1808 /* Enable the DMA stream */
1809 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1810 Length) != HAL_OK)
1811 {
1812 /* Return error status */
1813 return HAL_ERROR;
1814 }
1815 /* Enable the TIM Output Capture/Compare 3 request */
1816 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1817 break;
1818 }
1819
1820 case TIM_CHANNEL_4:
1821 {
1822 /* Set the DMA compare callbacks */
1823 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1824 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1825
1826 /* Set the DMA error callback */
1827 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1828
1829 /* Enable the DMA stream */
1830 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1831 Length) != HAL_OK)
1832 {
1833 /* Return error status */
1834 return HAL_ERROR;
1835 }
1836 /* Enable the TIM Capture/Compare 4 DMA request */
1837 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1838 break;
1839 }
1840
1841 default:
1842 status = HAL_ERROR;
1843 break;
1844 }
1845
1846 if (status == HAL_OK)
1847 {
1848 /* Enable the Capture compare channel */
1849 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1850
1851 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1852 {
1853 /* Enable the main output */
1854 __HAL_TIM_MOE_ENABLE(htim);
1855 }
1856
1857 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1858 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1859 {
1860 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1861 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1862 {
1863 __HAL_TIM_ENABLE(htim);
1864 }
1865 }
1866 else
1867 {
1868 __HAL_TIM_ENABLE(htim);
1869 }
1870 }
1871
1872 /* Return function status */
1873 return status;
1874 }
1875
1876 /**
1877 * @brief Stops the TIM PWM signal generation in DMA mode.
1878 * @param htim TIM PWM handle
1879 * @param Channel TIM Channels to be disabled
1880 * This parameter can be one of the following values:
1881 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1882 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1883 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1884 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1885 * @retval HAL status
1886 */
HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1887 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1888 {
1889 HAL_StatusTypeDef status = HAL_OK;
1890
1891 /* Check the parameters */
1892 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1893
1894 switch (Channel)
1895 {
1896 case TIM_CHANNEL_1:
1897 {
1898 /* Disable the TIM Capture/Compare 1 DMA request */
1899 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1900 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1901 break;
1902 }
1903
1904 case TIM_CHANNEL_2:
1905 {
1906 /* Disable the TIM Capture/Compare 2 DMA request */
1907 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1908 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1909 break;
1910 }
1911
1912 case TIM_CHANNEL_3:
1913 {
1914 /* Disable the TIM Capture/Compare 3 DMA request */
1915 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1916 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1917 break;
1918 }
1919
1920 case TIM_CHANNEL_4:
1921 {
1922 /* Disable the TIM Capture/Compare 4 interrupt */
1923 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1924 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1925 break;
1926 }
1927
1928 default:
1929 status = HAL_ERROR;
1930 break;
1931 }
1932
1933 if (status == HAL_OK)
1934 {
1935 /* Disable the Capture compare channel */
1936 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1937
1938 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1939 {
1940 /* Disable the Main Output */
1941 __HAL_TIM_MOE_DISABLE(htim);
1942 }
1943
1944 /* Disable the Peripheral */
1945 __HAL_TIM_DISABLE(htim);
1946
1947 /* Set the TIM channel state */
1948 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1949 }
1950
1951 /* Return function status */
1952 return status;
1953 }
1954
1955 /**
1956 * @}
1957 */
1958
1959 /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
1960 * @brief TIM Input Capture functions
1961 *
1962 @verbatim
1963 ==============================================================================
1964 ##### TIM Input Capture functions #####
1965 ==============================================================================
1966 [..]
1967 This section provides functions allowing to:
1968 (+) Initialize and configure the TIM Input Capture.
1969 (+) De-initialize the TIM Input Capture.
1970 (+) Start the TIM Input Capture.
1971 (+) Stop the TIM Input Capture.
1972 (+) Start the TIM Input Capture and enable interrupt.
1973 (+) Stop the TIM Input Capture and disable interrupt.
1974 (+) Start the TIM Input Capture and enable DMA transfer.
1975 (+) Stop the TIM Input Capture and disable DMA transfer.
1976
1977 @endverbatim
1978 * @{
1979 */
1980 /**
1981 * @brief Initializes the TIM Input Capture Time base according to the specified
1982 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1983 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1984 * requires a timer reset to avoid unexpected direction
1985 * due to DIR bit readonly in center aligned mode.
1986 * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
1987 * @param htim TIM Input Capture handle
1988 * @retval HAL status
1989 */
HAL_TIM_IC_Init(TIM_HandleTypeDef * htim)1990 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1991 {
1992 /* Check the TIM handle allocation */
1993 if (htim == NULL)
1994 {
1995 return HAL_ERROR;
1996 }
1997
1998 /* Check the parameters */
1999 assert_param(IS_TIM_INSTANCE(htim->Instance));
2000 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2001 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2002 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
2003 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2004
2005 if (htim->State == HAL_TIM_STATE_RESET)
2006 {
2007 /* Allocate lock resource and initialize it */
2008 htim->Lock = HAL_UNLOCKED;
2009
2010 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2011 /* Reset interrupt callbacks to legacy weak callbacks */
2012 TIM_ResetCallback(htim);
2013
2014 if (htim->IC_MspInitCallback == NULL)
2015 {
2016 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
2017 }
2018 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2019 htim->IC_MspInitCallback(htim);
2020 #else
2021 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2022 HAL_TIM_IC_MspInit(htim);
2023 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2024 }
2025
2026 /* Set the TIM state */
2027 htim->State = HAL_TIM_STATE_BUSY;
2028
2029 /* Init the base time for the input capture */
2030 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2031
2032 /* Initialize the DMA burst operation state */
2033 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2034
2035 /* Initialize the TIM channels state */
2036 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
2037 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
2038
2039 /* Initialize the TIM state*/
2040 htim->State = HAL_TIM_STATE_READY;
2041
2042 return HAL_OK;
2043 }
2044
2045 /**
2046 * @brief DeInitializes the TIM peripheral
2047 * @param htim TIM Input Capture handle
2048 * @retval HAL status
2049 */
HAL_TIM_IC_DeInit(TIM_HandleTypeDef * htim)2050 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
2051 {
2052 /* Check the parameters */
2053 assert_param(IS_TIM_INSTANCE(htim->Instance));
2054
2055 htim->State = HAL_TIM_STATE_BUSY;
2056
2057 /* Disable the TIM Peripheral Clock */
2058 __HAL_TIM_DISABLE(htim);
2059
2060 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2061 if (htim->IC_MspDeInitCallback == NULL)
2062 {
2063 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
2064 }
2065 /* DeInit the low level hardware */
2066 htim->IC_MspDeInitCallback(htim);
2067 #else
2068 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
2069 HAL_TIM_IC_MspDeInit(htim);
2070 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2071
2072 /* Change the DMA burst operation state */
2073 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2074
2075 /* Change the TIM channels state */
2076 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2077 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2078
2079 /* Change TIM state */
2080 htim->State = HAL_TIM_STATE_RESET;
2081
2082 /* Release Lock */
2083 __HAL_UNLOCK(htim);
2084
2085 return HAL_OK;
2086 }
2087
2088 /**
2089 * @brief Initializes the TIM Input Capture MSP.
2090 * @param htim TIM Input Capture handle
2091 * @retval None
2092 */
HAL_TIM_IC_MspInit(TIM_HandleTypeDef * htim)2093 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
2094 {
2095 /* Prevent unused argument(s) compilation warning */
2096 UNUSED(htim);
2097
2098 /* NOTE : This function should not be modified, when the callback is needed,
2099 the HAL_TIM_IC_MspInit could be implemented in the user file
2100 */
2101 }
2102
2103 /**
2104 * @brief DeInitializes TIM Input Capture MSP.
2105 * @param htim TIM handle
2106 * @retval None
2107 */
HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef * htim)2108 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
2109 {
2110 /* Prevent unused argument(s) compilation warning */
2111 UNUSED(htim);
2112
2113 /* NOTE : This function should not be modified, when the callback is needed,
2114 the HAL_TIM_IC_MspDeInit could be implemented in the user file
2115 */
2116 }
2117
2118 /**
2119 * @brief Starts the TIM Input Capture measurement.
2120 * @param htim TIM Input Capture handle
2121 * @param Channel TIM Channels to be enabled
2122 * This parameter can be one of the following values:
2123 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2124 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2125 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2126 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2127 * @retval HAL status
2128 */
HAL_TIM_IC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)2129 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2130 {
2131 uint32_t tmpsmcr;
2132 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2133 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2134
2135 /* Check the parameters */
2136 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2137
2138 /* Check the TIM channel state */
2139 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2140 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2141 {
2142 return HAL_ERROR;
2143 }
2144
2145 /* Set the TIM channel state */
2146 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2147 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2148
2149 /* Enable the Input Capture channel */
2150 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2151
2152 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2153 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2154 {
2155 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2156 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2157 {
2158 __HAL_TIM_ENABLE(htim);
2159 }
2160 }
2161 else
2162 {
2163 __HAL_TIM_ENABLE(htim);
2164 }
2165
2166 /* Return function status */
2167 return HAL_OK;
2168 }
2169
2170 /**
2171 * @brief Stops the TIM Input Capture measurement.
2172 * @param htim TIM Input Capture handle
2173 * @param Channel TIM Channels to be disabled
2174 * This parameter can be one of the following values:
2175 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2176 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2177 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2178 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2179 * @retval HAL status
2180 */
HAL_TIM_IC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)2181 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2182 {
2183 /* Check the parameters */
2184 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2185
2186 /* Disable the Input Capture channel */
2187 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2188
2189 /* Disable the Peripheral */
2190 __HAL_TIM_DISABLE(htim);
2191
2192 /* Set the TIM channel state */
2193 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2194 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2195
2196 /* Return function status */
2197 return HAL_OK;
2198 }
2199
2200 /**
2201 * @brief Starts the TIM Input Capture measurement in interrupt mode.
2202 * @param htim TIM Input Capture handle
2203 * @param Channel TIM Channels to be enabled
2204 * This parameter can be one of the following values:
2205 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2206 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2207 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2208 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2209 * @retval HAL status
2210 */
HAL_TIM_IC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2211 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2212 {
2213 HAL_StatusTypeDef status = HAL_OK;
2214 uint32_t tmpsmcr;
2215
2216 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2217 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2218
2219 /* Check the parameters */
2220 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2221
2222 /* Check the TIM channel state */
2223 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2224 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2225 {
2226 return HAL_ERROR;
2227 }
2228
2229 /* Set the TIM channel state */
2230 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2231 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2232
2233 switch (Channel)
2234 {
2235 case TIM_CHANNEL_1:
2236 {
2237 /* Enable the TIM Capture/Compare 1 interrupt */
2238 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2239 break;
2240 }
2241
2242 case TIM_CHANNEL_2:
2243 {
2244 /* Enable the TIM Capture/Compare 2 interrupt */
2245 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2246 break;
2247 }
2248
2249 case TIM_CHANNEL_3:
2250 {
2251 /* Enable the TIM Capture/Compare 3 interrupt */
2252 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
2253 break;
2254 }
2255
2256 case TIM_CHANNEL_4:
2257 {
2258 /* Enable the TIM Capture/Compare 4 interrupt */
2259 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
2260 break;
2261 }
2262
2263 default:
2264 status = HAL_ERROR;
2265 break;
2266 }
2267
2268 if (status == HAL_OK)
2269 {
2270 /* Enable the Input Capture channel */
2271 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2272
2273 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2274 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2275 {
2276 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2277 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2278 {
2279 __HAL_TIM_ENABLE(htim);
2280 }
2281 }
2282 else
2283 {
2284 __HAL_TIM_ENABLE(htim);
2285 }
2286 }
2287
2288 /* Return function status */
2289 return status;
2290 }
2291
2292 /**
2293 * @brief Stops the TIM Input Capture measurement in interrupt mode.
2294 * @param htim TIM Input Capture handle
2295 * @param Channel TIM Channels to be disabled
2296 * This parameter can be one of the following values:
2297 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2298 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2299 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2300 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2301 * @retval HAL status
2302 */
HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2303 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2304 {
2305 HAL_StatusTypeDef status = HAL_OK;
2306
2307 /* Check the parameters */
2308 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2309
2310 switch (Channel)
2311 {
2312 case TIM_CHANNEL_1:
2313 {
2314 /* Disable the TIM Capture/Compare 1 interrupt */
2315 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2316 break;
2317 }
2318
2319 case TIM_CHANNEL_2:
2320 {
2321 /* Disable the TIM Capture/Compare 2 interrupt */
2322 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2323 break;
2324 }
2325
2326 case TIM_CHANNEL_3:
2327 {
2328 /* Disable the TIM Capture/Compare 3 interrupt */
2329 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
2330 break;
2331 }
2332
2333 case TIM_CHANNEL_4:
2334 {
2335 /* Disable the TIM Capture/Compare 4 interrupt */
2336 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
2337 break;
2338 }
2339
2340 default:
2341 status = HAL_ERROR;
2342 break;
2343 }
2344
2345 if (status == HAL_OK)
2346 {
2347 /* Disable the Input Capture channel */
2348 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2349
2350 /* Disable the Peripheral */
2351 __HAL_TIM_DISABLE(htim);
2352
2353 /* Set the TIM channel state */
2354 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2355 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2356 }
2357
2358 /* Return function status */
2359 return status;
2360 }
2361
2362 /**
2363 * @brief Starts the TIM Input Capture measurement in DMA mode.
2364 * @param htim TIM Input Capture handle
2365 * @param Channel TIM Channels to be enabled
2366 * This parameter can be one of the following values:
2367 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2368 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2369 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2370 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2371 * @param pData The destination Buffer address.
2372 * @param Length The length of data to be transferred from TIM peripheral to memory.
2373 * @retval HAL status
2374 */
HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)2375 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
2376 {
2377 HAL_StatusTypeDef status = HAL_OK;
2378 uint32_t tmpsmcr;
2379
2380 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2381 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2382
2383 /* Check the parameters */
2384 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2385 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2386
2387 /* Set the TIM channel state */
2388 if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
2389 || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
2390 {
2391 return HAL_BUSY;
2392 }
2393 else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
2394 && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
2395 {
2396 if ((pData == NULL) || (Length == 0U))
2397 {
2398 return HAL_ERROR;
2399 }
2400 else
2401 {
2402 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2403 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2404 }
2405 }
2406 else
2407 {
2408 return HAL_ERROR;
2409 }
2410
2411 /* Enable the Input Capture channel */
2412 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2413
2414 switch (Channel)
2415 {
2416 case TIM_CHANNEL_1:
2417 {
2418 /* Set the DMA capture callbacks */
2419 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2420 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2421
2422 /* Set the DMA error callback */
2423 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2424
2425 /* Enable the DMA stream */
2426 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
2427 Length) != HAL_OK)
2428 {
2429 /* Return error status */
2430 return HAL_ERROR;
2431 }
2432 /* Enable the TIM Capture/Compare 1 DMA request */
2433 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2434 break;
2435 }
2436
2437 case TIM_CHANNEL_2:
2438 {
2439 /* Set the DMA capture callbacks */
2440 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2441 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2442
2443 /* Set the DMA error callback */
2444 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2445
2446 /* Enable the DMA stream */
2447 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
2448 Length) != HAL_OK)
2449 {
2450 /* Return error status */
2451 return HAL_ERROR;
2452 }
2453 /* Enable the TIM Capture/Compare 2 DMA request */
2454 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2455 break;
2456 }
2457
2458 case TIM_CHANNEL_3:
2459 {
2460 /* Set the DMA capture callbacks */
2461 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
2462 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2463
2464 /* Set the DMA error callback */
2465 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
2466
2467 /* Enable the DMA stream */
2468 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
2469 Length) != HAL_OK)
2470 {
2471 /* Return error status */
2472 return HAL_ERROR;
2473 }
2474 /* Enable the TIM Capture/Compare 3 DMA request */
2475 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
2476 break;
2477 }
2478
2479 case TIM_CHANNEL_4:
2480 {
2481 /* Set the DMA capture callbacks */
2482 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
2483 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2484
2485 /* Set the DMA error callback */
2486 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
2487
2488 /* Enable the DMA stream */
2489 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
2490 Length) != HAL_OK)
2491 {
2492 /* Return error status */
2493 return HAL_ERROR;
2494 }
2495 /* Enable the TIM Capture/Compare 4 DMA request */
2496 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
2497 break;
2498 }
2499
2500 default:
2501 status = HAL_ERROR;
2502 break;
2503 }
2504
2505 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2506 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2507 {
2508 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2509 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2510 {
2511 __HAL_TIM_ENABLE(htim);
2512 }
2513 }
2514 else
2515 {
2516 __HAL_TIM_ENABLE(htim);
2517 }
2518
2519 /* Return function status */
2520 return status;
2521 }
2522
2523 /**
2524 * @brief Stops the TIM Input Capture measurement in DMA mode.
2525 * @param htim TIM Input Capture handle
2526 * @param Channel TIM Channels to be disabled
2527 * This parameter can be one of the following values:
2528 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2529 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2530 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2531 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2532 * @retval HAL status
2533 */
HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)2534 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2535 {
2536 HAL_StatusTypeDef status = HAL_OK;
2537
2538 /* Check the parameters */
2539 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2540 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2541
2542 /* Disable the Input Capture channel */
2543 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2544
2545 switch (Channel)
2546 {
2547 case TIM_CHANNEL_1:
2548 {
2549 /* Disable the TIM Capture/Compare 1 DMA request */
2550 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2551 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
2552 break;
2553 }
2554
2555 case TIM_CHANNEL_2:
2556 {
2557 /* Disable the TIM Capture/Compare 2 DMA request */
2558 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2559 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
2560 break;
2561 }
2562
2563 case TIM_CHANNEL_3:
2564 {
2565 /* Disable the TIM Capture/Compare 3 DMA request */
2566 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
2567 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
2568 break;
2569 }
2570
2571 case TIM_CHANNEL_4:
2572 {
2573 /* Disable the TIM Capture/Compare 4 DMA request */
2574 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
2575 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
2576 break;
2577 }
2578
2579 default:
2580 status = HAL_ERROR;
2581 break;
2582 }
2583
2584 if (status == HAL_OK)
2585 {
2586 /* Disable the Peripheral */
2587 __HAL_TIM_DISABLE(htim);
2588
2589 /* Set the TIM channel state */
2590 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2591 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2592 }
2593
2594 /* Return function status */
2595 return status;
2596 }
2597 /**
2598 * @}
2599 */
2600
2601 /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2602 * @brief TIM One Pulse functions
2603 *
2604 @verbatim
2605 ==============================================================================
2606 ##### TIM One Pulse functions #####
2607 ==============================================================================
2608 [..]
2609 This section provides functions allowing to:
2610 (+) Initialize and configure the TIM One Pulse.
2611 (+) De-initialize the TIM One Pulse.
2612 (+) Start the TIM One Pulse.
2613 (+) Stop the TIM One Pulse.
2614 (+) Start the TIM One Pulse and enable interrupt.
2615 (+) Stop the TIM One Pulse and disable interrupt.
2616 (+) Start the TIM One Pulse and enable DMA transfer.
2617 (+) Stop the TIM One Pulse and disable DMA transfer.
2618
2619 @endverbatim
2620 * @{
2621 */
2622 /**
2623 * @brief Initializes the TIM One Pulse Time Base according to the specified
2624 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
2625 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2626 * requires a timer reset to avoid unexpected direction
2627 * due to DIR bit readonly in center aligned mode.
2628 * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
2629 * @note When the timer instance is initialized in One Pulse mode, timer
2630 * channels 1 and channel 2 are reserved and cannot be used for other
2631 * purpose.
2632 * @param htim TIM One Pulse handle
2633 * @param OnePulseMode Select the One pulse mode.
2634 * This parameter can be one of the following values:
2635 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
2636 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
2637 * @retval HAL status
2638 */
HAL_TIM_OnePulse_Init(TIM_HandleTypeDef * htim,uint32_t OnePulseMode)2639 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
2640 {
2641 /* Check the TIM handle allocation */
2642 if (htim == NULL)
2643 {
2644 return HAL_ERROR;
2645 }
2646
2647 /* Check the parameters */
2648 assert_param(IS_TIM_INSTANCE(htim->Instance));
2649 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2650 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2651 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
2652 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
2653 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2654
2655 if (htim->State == HAL_TIM_STATE_RESET)
2656 {
2657 /* Allocate lock resource and initialize it */
2658 htim->Lock = HAL_UNLOCKED;
2659
2660 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2661 /* Reset interrupt callbacks to legacy weak callbacks */
2662 TIM_ResetCallback(htim);
2663
2664 if (htim->OnePulse_MspInitCallback == NULL)
2665 {
2666 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
2667 }
2668 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2669 htim->OnePulse_MspInitCallback(htim);
2670 #else
2671 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2672 HAL_TIM_OnePulse_MspInit(htim);
2673 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2674 }
2675
2676 /* Set the TIM state */
2677 htim->State = HAL_TIM_STATE_BUSY;
2678
2679 /* Configure the Time base in the One Pulse Mode */
2680 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2681
2682 /* Reset the OPM Bit */
2683 htim->Instance->CR1 &= ~TIM_CR1_OPM;
2684
2685 /* Configure the OPM Mode */
2686 htim->Instance->CR1 |= OnePulseMode;
2687
2688 /* Initialize the DMA burst operation state */
2689 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2690
2691 /* Initialize the TIM channels state */
2692 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2693 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2694 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2695 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2696
2697 /* Initialize the TIM state*/
2698 htim->State = HAL_TIM_STATE_READY;
2699
2700 return HAL_OK;
2701 }
2702
2703 /**
2704 * @brief DeInitializes the TIM One Pulse
2705 * @param htim TIM One Pulse handle
2706 * @retval HAL status
2707 */
HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef * htim)2708 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
2709 {
2710 /* Check the parameters */
2711 assert_param(IS_TIM_INSTANCE(htim->Instance));
2712
2713 htim->State = HAL_TIM_STATE_BUSY;
2714
2715 /* Disable the TIM Peripheral Clock */
2716 __HAL_TIM_DISABLE(htim);
2717
2718 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2719 if (htim->OnePulse_MspDeInitCallback == NULL)
2720 {
2721 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
2722 }
2723 /* DeInit the low level hardware */
2724 htim->OnePulse_MspDeInitCallback(htim);
2725 #else
2726 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2727 HAL_TIM_OnePulse_MspDeInit(htim);
2728 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2729
2730 /* Change the DMA burst operation state */
2731 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2732
2733 /* Set the TIM channel state */
2734 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2735 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2736 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2737 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2738
2739 /* Change TIM state */
2740 htim->State = HAL_TIM_STATE_RESET;
2741
2742 /* Release Lock */
2743 __HAL_UNLOCK(htim);
2744
2745 return HAL_OK;
2746 }
2747
2748 /**
2749 * @brief Initializes the TIM One Pulse MSP.
2750 * @param htim TIM One Pulse handle
2751 * @retval None
2752 */
HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef * htim)2753 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2754 {
2755 /* Prevent unused argument(s) compilation warning */
2756 UNUSED(htim);
2757
2758 /* NOTE : This function should not be modified, when the callback is needed,
2759 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2760 */
2761 }
2762
2763 /**
2764 * @brief DeInitializes TIM One Pulse MSP.
2765 * @param htim TIM One Pulse handle
2766 * @retval None
2767 */
HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef * htim)2768 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2769 {
2770 /* Prevent unused argument(s) compilation warning */
2771 UNUSED(htim);
2772
2773 /* NOTE : This function should not be modified, when the callback is needed,
2774 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2775 */
2776 }
2777
2778 /**
2779 * @brief Starts the TIM One Pulse signal generation.
2780 * @note Though OutputChannel parameter is deprecated and ignored by the function
2781 * it has been kept to avoid HAL_TIM API compatibility break.
2782 * @note The pulse output channel is determined when calling
2783 * @ref HAL_TIM_OnePulse_ConfigChannel().
2784 * @param htim TIM One Pulse handle
2785 * @param OutputChannel See note above
2786 * @retval HAL status
2787 */
HAL_TIM_OnePulse_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2788 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2789 {
2790 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2791 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2792 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2793 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2794
2795 /* Prevent unused argument(s) compilation warning */
2796 UNUSED(OutputChannel);
2797
2798 /* Check the TIM channels state */
2799 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2800 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2801 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2802 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2803 {
2804 return HAL_ERROR;
2805 }
2806
2807 /* Set the TIM channels state */
2808 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2809 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2810 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2811 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2812
2813 /* Enable the Capture compare and the Input Capture channels
2814 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2815 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2816 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2817 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2818
2819 No need to enable the counter, it's enabled automatically by hardware
2820 (the counter starts in response to a stimulus and generate a pulse */
2821
2822 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2823 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2824
2825 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2826 {
2827 /* Enable the main output */
2828 __HAL_TIM_MOE_ENABLE(htim);
2829 }
2830
2831 /* Return function status */
2832 return HAL_OK;
2833 }
2834
2835 /**
2836 * @brief Stops the TIM One Pulse signal generation.
2837 * @note Though OutputChannel parameter is deprecated and ignored by the function
2838 * it has been kept to avoid HAL_TIM API compatibility break.
2839 * @note The pulse output channel is determined when calling
2840 * @ref HAL_TIM_OnePulse_ConfigChannel().
2841 * @param htim TIM One Pulse handle
2842 * @param OutputChannel See note above
2843 * @retval HAL status
2844 */
HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2845 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2846 {
2847 /* Prevent unused argument(s) compilation warning */
2848 UNUSED(OutputChannel);
2849
2850 /* Disable the Capture compare and the Input Capture channels
2851 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2852 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2853 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2854 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2855
2856 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2857 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2858
2859 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2860 {
2861 /* Disable the Main Output */
2862 __HAL_TIM_MOE_DISABLE(htim);
2863 }
2864
2865 /* Disable the Peripheral */
2866 __HAL_TIM_DISABLE(htim);
2867
2868 /* Set the TIM channels state */
2869 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2870 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2871 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2872 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2873
2874 /* Return function status */
2875 return HAL_OK;
2876 }
2877
2878 /**
2879 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2880 * @note Though OutputChannel parameter is deprecated and ignored by the function
2881 * it has been kept to avoid HAL_TIM API compatibility break.
2882 * @note The pulse output channel is determined when calling
2883 * @ref HAL_TIM_OnePulse_ConfigChannel().
2884 * @param htim TIM One Pulse handle
2885 * @param OutputChannel See note above
2886 * @retval HAL status
2887 */
HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2888 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2889 {
2890 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2891 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2892 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2893 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2894
2895 /* Prevent unused argument(s) compilation warning */
2896 UNUSED(OutputChannel);
2897
2898 /* Check the TIM channels state */
2899 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2900 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2901 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2902 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2903 {
2904 return HAL_ERROR;
2905 }
2906
2907 /* Set the TIM channels state */
2908 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2909 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2910 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2911 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2912
2913 /* Enable the Capture compare and the Input Capture channels
2914 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2915 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2916 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2917 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2918
2919 No need to enable the counter, it's enabled automatically by hardware
2920 (the counter starts in response to a stimulus and generate a pulse */
2921
2922 /* Enable the TIM Capture/Compare 1 interrupt */
2923 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2924
2925 /* Enable the TIM Capture/Compare 2 interrupt */
2926 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2927
2928 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2929 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2930
2931 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2932 {
2933 /* Enable the main output */
2934 __HAL_TIM_MOE_ENABLE(htim);
2935 }
2936
2937 /* Return function status */
2938 return HAL_OK;
2939 }
2940
2941 /**
2942 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2943 * @note Though OutputChannel parameter is deprecated and ignored by the function
2944 * it has been kept to avoid HAL_TIM API compatibility break.
2945 * @note The pulse output channel is determined when calling
2946 * @ref HAL_TIM_OnePulse_ConfigChannel().
2947 * @param htim TIM One Pulse handle
2948 * @param OutputChannel See note above
2949 * @retval HAL status
2950 */
HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2951 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2952 {
2953 /* Prevent unused argument(s) compilation warning */
2954 UNUSED(OutputChannel);
2955
2956 /* Disable the TIM Capture/Compare 1 interrupt */
2957 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2958
2959 /* Disable the TIM Capture/Compare 2 interrupt */
2960 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2961
2962 /* Disable the Capture compare and the Input Capture channels
2963 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2964 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2965 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2966 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2967 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2968 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2969
2970 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2971 {
2972 /* Disable the Main Output */
2973 __HAL_TIM_MOE_DISABLE(htim);
2974 }
2975
2976 /* Disable the Peripheral */
2977 __HAL_TIM_DISABLE(htim);
2978
2979 /* Set the TIM channels state */
2980 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2981 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2982 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2983 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2984
2985 /* Return function status */
2986 return HAL_OK;
2987 }
2988
2989 /**
2990 * @}
2991 */
2992
2993 /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
2994 * @brief TIM Encoder functions
2995 *
2996 @verbatim
2997 ==============================================================================
2998 ##### TIM Encoder functions #####
2999 ==============================================================================
3000 [..]
3001 This section provides functions allowing to:
3002 (+) Initialize and configure the TIM Encoder.
3003 (+) De-initialize the TIM Encoder.
3004 (+) Start the TIM Encoder.
3005 (+) Stop the TIM Encoder.
3006 (+) Start the TIM Encoder and enable interrupt.
3007 (+) Stop the TIM Encoder and disable interrupt.
3008 (+) Start the TIM Encoder and enable DMA transfer.
3009 (+) Stop the TIM Encoder and disable DMA transfer.
3010
3011 @endverbatim
3012 * @{
3013 */
3014 /**
3015 * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
3016 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
3017 * requires a timer reset to avoid unexpected direction
3018 * due to DIR bit readonly in center aligned mode.
3019 * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
3020 * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
3021 * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
3022 * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
3023 * @note When the timer instance is initialized in Encoder mode, timer
3024 * channels 1 and channel 2 are reserved and cannot be used for other
3025 * purpose.
3026 * @param htim TIM Encoder Interface handle
3027 * @param sConfig TIM Encoder Interface configuration structure
3028 * @retval HAL status
3029 */
HAL_TIM_Encoder_Init(TIM_HandleTypeDef * htim,const TIM_Encoder_InitTypeDef * sConfig)3030 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
3031 {
3032 uint32_t tmpsmcr;
3033 uint32_t tmpccmr1;
3034 uint32_t tmpccer;
3035
3036 /* Check the TIM handle allocation */
3037 if (htim == NULL)
3038 {
3039 return HAL_ERROR;
3040 }
3041
3042 /* Check the parameters */
3043 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3044 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
3045 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
3046 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
3047 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
3048 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
3049 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
3050 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
3051 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
3052 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
3053 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
3054 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
3055 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
3056 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
3057
3058 if (htim->State == HAL_TIM_STATE_RESET)
3059 {
3060 /* Allocate lock resource and initialize it */
3061 htim->Lock = HAL_UNLOCKED;
3062
3063 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3064 /* Reset interrupt callbacks to legacy weak callbacks */
3065 TIM_ResetCallback(htim);
3066
3067 if (htim->Encoder_MspInitCallback == NULL)
3068 {
3069 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
3070 }
3071 /* Init the low level hardware : GPIO, CLOCK, NVIC */
3072 htim->Encoder_MspInitCallback(htim);
3073 #else
3074 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
3075 HAL_TIM_Encoder_MspInit(htim);
3076 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3077 }
3078
3079 /* Set the TIM state */
3080 htim->State = HAL_TIM_STATE_BUSY;
3081
3082 /* Reset the SMS and ECE bits */
3083 htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
3084
3085 /* Configure the Time base in the Encoder Mode */
3086 TIM_Base_SetConfig(htim->Instance, &htim->Init);
3087
3088 /* Get the TIMx SMCR register value */
3089 tmpsmcr = htim->Instance->SMCR;
3090
3091 /* Get the TIMx CCMR1 register value */
3092 tmpccmr1 = htim->Instance->CCMR1;
3093
3094 /* Get the TIMx CCER register value */
3095 tmpccer = htim->Instance->CCER;
3096
3097 /* Set the encoder Mode */
3098 tmpsmcr |= sConfig->EncoderMode;
3099
3100 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
3101 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
3102 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
3103
3104 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
3105 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
3106 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
3107 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
3108 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
3109
3110 /* Set the TI1 and the TI2 Polarities */
3111 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
3112 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
3113 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
3114
3115 /* Write to TIMx SMCR */
3116 htim->Instance->SMCR = tmpsmcr;
3117
3118 /* Write to TIMx CCMR1 */
3119 htim->Instance->CCMR1 = tmpccmr1;
3120
3121 /* Write to TIMx CCER */
3122 htim->Instance->CCER = tmpccer;
3123
3124 /* Initialize the DMA burst operation state */
3125 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
3126
3127 /* Set the TIM channels state */
3128 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3129 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3130 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3131 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3132
3133 /* Initialize the TIM state*/
3134 htim->State = HAL_TIM_STATE_READY;
3135
3136 return HAL_OK;
3137 }
3138
3139
3140 /**
3141 * @brief DeInitializes the TIM Encoder interface
3142 * @param htim TIM Encoder Interface handle
3143 * @retval HAL status
3144 */
HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef * htim)3145 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
3146 {
3147 /* Check the parameters */
3148 assert_param(IS_TIM_INSTANCE(htim->Instance));
3149
3150 htim->State = HAL_TIM_STATE_BUSY;
3151
3152 /* Disable the TIM Peripheral Clock */
3153 __HAL_TIM_DISABLE(htim);
3154
3155 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3156 if (htim->Encoder_MspDeInitCallback == NULL)
3157 {
3158 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
3159 }
3160 /* DeInit the low level hardware */
3161 htim->Encoder_MspDeInitCallback(htim);
3162 #else
3163 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
3164 HAL_TIM_Encoder_MspDeInit(htim);
3165 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3166
3167 /* Change the DMA burst operation state */
3168 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
3169
3170 /* Set the TIM channels state */
3171 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3172 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3173 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3174 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3175
3176 /* Change TIM state */
3177 htim->State = HAL_TIM_STATE_RESET;
3178
3179 /* Release Lock */
3180 __HAL_UNLOCK(htim);
3181
3182 return HAL_OK;
3183 }
3184
3185 /**
3186 * @brief Initializes the TIM Encoder Interface MSP.
3187 * @param htim TIM Encoder Interface handle
3188 * @retval None
3189 */
HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef * htim)3190 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
3191 {
3192 /* Prevent unused argument(s) compilation warning */
3193 UNUSED(htim);
3194
3195 /* NOTE : This function should not be modified, when the callback is needed,
3196 the HAL_TIM_Encoder_MspInit could be implemented in the user file
3197 */
3198 }
3199
3200 /**
3201 * @brief DeInitializes TIM Encoder Interface MSP.
3202 * @param htim TIM Encoder Interface handle
3203 * @retval None
3204 */
HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef * htim)3205 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
3206 {
3207 /* Prevent unused argument(s) compilation warning */
3208 UNUSED(htim);
3209
3210 /* NOTE : This function should not be modified, when the callback is needed,
3211 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
3212 */
3213 }
3214
3215 /**
3216 * @brief Starts the TIM Encoder Interface.
3217 * @param htim TIM Encoder Interface handle
3218 * @param Channel TIM Channels to be enabled
3219 * This parameter can be one of the following values:
3220 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3221 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3222 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3223 * @retval HAL status
3224 */
HAL_TIM_Encoder_Start(TIM_HandleTypeDef * htim,uint32_t Channel)3225 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
3226 {
3227 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3228 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3229 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3230 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3231
3232 /* Check the parameters */
3233 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3234
3235 /* Set the TIM channel(s) state */
3236 if (Channel == TIM_CHANNEL_1)
3237 {
3238 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3239 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3240 {
3241 return HAL_ERROR;
3242 }
3243 else
3244 {
3245 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3246 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3247 }
3248 }
3249 else if (Channel == TIM_CHANNEL_2)
3250 {
3251 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3252 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3253 {
3254 return HAL_ERROR;
3255 }
3256 else
3257 {
3258 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3259 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3260 }
3261 }
3262 else
3263 {
3264 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3265 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3266 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3267 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3268 {
3269 return HAL_ERROR;
3270 }
3271 else
3272 {
3273 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3274 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3275 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3276 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3277 }
3278 }
3279
3280 /* Enable the encoder interface channels */
3281 switch (Channel)
3282 {
3283 case TIM_CHANNEL_1:
3284 {
3285 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3286 break;
3287 }
3288
3289 case TIM_CHANNEL_2:
3290 {
3291 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3292 break;
3293 }
3294
3295 default :
3296 {
3297 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3298 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3299 break;
3300 }
3301 }
3302 /* Enable the Peripheral */
3303 __HAL_TIM_ENABLE(htim);
3304
3305 /* Return function status */
3306 return HAL_OK;
3307 }
3308
3309 /**
3310 * @brief Stops the TIM Encoder Interface.
3311 * @param htim TIM Encoder Interface handle
3312 * @param Channel TIM Channels to be disabled
3313 * This parameter can be one of the following values:
3314 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3315 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3316 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3317 * @retval HAL status
3318 */
HAL_TIM_Encoder_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)3319 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
3320 {
3321 /* Check the parameters */
3322 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3323
3324 /* Disable the Input Capture channels 1 and 2
3325 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3326 switch (Channel)
3327 {
3328 case TIM_CHANNEL_1:
3329 {
3330 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3331 break;
3332 }
3333
3334 case TIM_CHANNEL_2:
3335 {
3336 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3337 break;
3338 }
3339
3340 default :
3341 {
3342 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3343 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3344 break;
3345 }
3346 }
3347
3348 /* Disable the Peripheral */
3349 __HAL_TIM_DISABLE(htim);
3350
3351 /* Set the TIM channel(s) state */
3352 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3353 {
3354 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3355 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3356 }
3357 else
3358 {
3359 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3360 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3361 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3362 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3363 }
3364
3365 /* Return function status */
3366 return HAL_OK;
3367 }
3368
3369 /**
3370 * @brief Starts the TIM Encoder Interface in interrupt mode.
3371 * @param htim TIM Encoder Interface handle
3372 * @param Channel TIM Channels to be enabled
3373 * This parameter can be one of the following values:
3374 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3375 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3376 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3377 * @retval HAL status
3378 */
HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3379 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3380 {
3381 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3382 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3383 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3384 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3385
3386 /* Check the parameters */
3387 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3388
3389 /* Set the TIM channel(s) state */
3390 if (Channel == TIM_CHANNEL_1)
3391 {
3392 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3393 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3394 {
3395 return HAL_ERROR;
3396 }
3397 else
3398 {
3399 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3400 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3401 }
3402 }
3403 else if (Channel == TIM_CHANNEL_2)
3404 {
3405 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3406 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3407 {
3408 return HAL_ERROR;
3409 }
3410 else
3411 {
3412 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3413 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3414 }
3415 }
3416 else
3417 {
3418 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3419 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3420 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3421 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3422 {
3423 return HAL_ERROR;
3424 }
3425 else
3426 {
3427 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3428 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3429 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3430 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3431 }
3432 }
3433
3434 /* Enable the encoder interface channels */
3435 /* Enable the capture compare Interrupts 1 and/or 2 */
3436 switch (Channel)
3437 {
3438 case TIM_CHANNEL_1:
3439 {
3440 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3441 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3442 break;
3443 }
3444
3445 case TIM_CHANNEL_2:
3446 {
3447 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3448 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3449 break;
3450 }
3451
3452 default :
3453 {
3454 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3455 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3456 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3457 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3458 break;
3459 }
3460 }
3461
3462 /* Enable the Peripheral */
3463 __HAL_TIM_ENABLE(htim);
3464
3465 /* Return function status */
3466 return HAL_OK;
3467 }
3468
3469 /**
3470 * @brief Stops the TIM Encoder Interface in interrupt mode.
3471 * @param htim TIM Encoder Interface handle
3472 * @param Channel TIM Channels to be disabled
3473 * This parameter can be one of the following values:
3474 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3475 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3476 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3477 * @retval HAL status
3478 */
HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3479 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3480 {
3481 /* Check the parameters */
3482 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3483
3484 /* Disable the Input Capture channels 1 and 2
3485 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3486 if (Channel == TIM_CHANNEL_1)
3487 {
3488 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3489
3490 /* Disable the capture compare Interrupts 1 */
3491 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3492 }
3493 else if (Channel == TIM_CHANNEL_2)
3494 {
3495 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3496
3497 /* Disable the capture compare Interrupts 2 */
3498 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3499 }
3500 else
3501 {
3502 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3503 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3504
3505 /* Disable the capture compare Interrupts 1 and 2 */
3506 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3507 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3508 }
3509
3510 /* Disable the Peripheral */
3511 __HAL_TIM_DISABLE(htim);
3512
3513 /* Set the TIM channel(s) state */
3514 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3515 {
3516 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3517 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3518 }
3519 else
3520 {
3521 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3522 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3523 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3524 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3525 }
3526
3527 /* Return function status */
3528 return HAL_OK;
3529 }
3530
3531 /**
3532 * @brief Starts the TIM Encoder Interface in DMA mode.
3533 * @param htim TIM Encoder Interface handle
3534 * @param Channel TIM Channels to be enabled
3535 * This parameter can be one of the following values:
3536 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3537 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3538 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3539 * @param pData1 The destination Buffer address for IC1.
3540 * @param pData2 The destination Buffer address for IC2.
3541 * @param Length The length of data to be transferred from TIM peripheral to memory.
3542 * @retval HAL status
3543 */
HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData1,uint32_t * pData2,uint16_t Length)3544 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
3545 uint32_t *pData2, uint16_t Length)
3546 {
3547 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3548 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3549 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3550 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3551
3552 /* Check the parameters */
3553 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3554
3555 /* Set the TIM channel(s) state */
3556 if (Channel == TIM_CHANNEL_1)
3557 {
3558 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3559 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
3560 {
3561 return HAL_BUSY;
3562 }
3563 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3564 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
3565 {
3566 if ((pData1 == NULL) || (Length == 0U))
3567 {
3568 return HAL_ERROR;
3569 }
3570 else
3571 {
3572 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3573 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3574 }
3575 }
3576 else
3577 {
3578 return HAL_ERROR;
3579 }
3580 }
3581 else if (Channel == TIM_CHANNEL_2)
3582 {
3583 if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3584 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3585 {
3586 return HAL_BUSY;
3587 }
3588 else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3589 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3590 {
3591 if ((pData2 == NULL) || (Length == 0U))
3592 {
3593 return HAL_ERROR;
3594 }
3595 else
3596 {
3597 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3598 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3599 }
3600 }
3601 else
3602 {
3603 return HAL_ERROR;
3604 }
3605 }
3606 else
3607 {
3608 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3609 || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3610 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3611 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3612 {
3613 return HAL_BUSY;
3614 }
3615 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3616 && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3617 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3618 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3619 {
3620 if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U))
3621 {
3622 return HAL_ERROR;
3623 }
3624 else
3625 {
3626 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3627 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3628 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3629 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3630 }
3631 }
3632 else
3633 {
3634 return HAL_ERROR;
3635 }
3636 }
3637
3638 switch (Channel)
3639 {
3640 case TIM_CHANNEL_1:
3641 {
3642 /* Set the DMA capture callbacks */
3643 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3644 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3645
3646 /* Set the DMA error callback */
3647 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3648
3649 /* Enable the DMA stream */
3650 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3651 Length) != HAL_OK)
3652 {
3653 /* Return error status */
3654 return HAL_ERROR;
3655 }
3656 /* Enable the TIM Input Capture DMA request */
3657 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3658
3659 /* Enable the Capture compare channel */
3660 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3661
3662 /* Enable the Peripheral */
3663 __HAL_TIM_ENABLE(htim);
3664
3665 break;
3666 }
3667
3668 case TIM_CHANNEL_2:
3669 {
3670 /* Set the DMA capture callbacks */
3671 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3672 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3673
3674 /* Set the DMA error callback */
3675 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
3676 /* Enable the DMA stream */
3677 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3678 Length) != HAL_OK)
3679 {
3680 /* Return error status */
3681 return HAL_ERROR;
3682 }
3683 /* Enable the TIM Input Capture DMA request */
3684 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3685
3686 /* Enable the Capture compare channel */
3687 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3688
3689 /* Enable the Peripheral */
3690 __HAL_TIM_ENABLE(htim);
3691
3692 break;
3693 }
3694
3695 default:
3696 {
3697 /* Set the DMA capture callbacks */
3698 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3699 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3700
3701 /* Set the DMA error callback */
3702 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3703
3704 /* Enable the DMA stream */
3705 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3706 Length) != HAL_OK)
3707 {
3708 /* Return error status */
3709 return HAL_ERROR;
3710 }
3711
3712 /* Set the DMA capture callbacks */
3713 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3714 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3715
3716 /* Set the DMA error callback */
3717 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3718
3719 /* Enable the DMA stream */
3720 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3721 Length) != HAL_OK)
3722 {
3723 /* Return error status */
3724 return HAL_ERROR;
3725 }
3726
3727 /* Enable the TIM Input Capture DMA request */
3728 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3729 /* Enable the TIM Input Capture DMA request */
3730 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3731
3732 /* Enable the Capture compare channel */
3733 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3734 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3735
3736 /* Enable the Peripheral */
3737 __HAL_TIM_ENABLE(htim);
3738
3739 break;
3740 }
3741 }
3742
3743 /* Return function status */
3744 return HAL_OK;
3745 }
3746
3747 /**
3748 * @brief Stops the TIM Encoder Interface in DMA mode.
3749 * @param htim TIM Encoder Interface handle
3750 * @param Channel TIM Channels to be enabled
3751 * This parameter can be one of the following values:
3752 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3753 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3754 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3755 * @retval HAL status
3756 */
HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)3757 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
3758 {
3759 /* Check the parameters */
3760 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3761
3762 /* Disable the Input Capture channels 1 and 2
3763 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3764 if (Channel == TIM_CHANNEL_1)
3765 {
3766 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3767
3768 /* Disable the capture compare DMA Request 1 */
3769 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3770 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3771 }
3772 else if (Channel == TIM_CHANNEL_2)
3773 {
3774 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3775
3776 /* Disable the capture compare DMA Request 2 */
3777 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3778 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3779 }
3780 else
3781 {
3782 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3783 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3784
3785 /* Disable the capture compare DMA Request 1 and 2 */
3786 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3787 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3788 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3789 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3790 }
3791
3792 /* Disable the Peripheral */
3793 __HAL_TIM_DISABLE(htim);
3794
3795 /* Set the TIM channel(s) state */
3796 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3797 {
3798 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3799 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3800 }
3801 else
3802 {
3803 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3804 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3805 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3806 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3807 }
3808
3809 /* Return function status */
3810 return HAL_OK;
3811 }
3812
3813 /**
3814 * @}
3815 */
3816 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
3817 * @brief TIM IRQ handler management
3818 *
3819 @verbatim
3820 ==============================================================================
3821 ##### IRQ handler management #####
3822 ==============================================================================
3823 [..]
3824 This section provides Timer IRQ handler function.
3825
3826 @endverbatim
3827 * @{
3828 */
3829 /**
3830 * @brief This function handles TIM interrupts requests.
3831 * @param htim TIM handle
3832 * @retval None
3833 */
HAL_TIM_IRQHandler(TIM_HandleTypeDef * htim)3834 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
3835 {
3836 uint32_t itsource = htim->Instance->DIER;
3837 uint32_t itflag = htim->Instance->SR;
3838
3839 /* Capture compare 1 event */
3840 if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
3841 {
3842 if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
3843 {
3844 {
3845 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
3846 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3847
3848 /* Input capture event */
3849 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
3850 {
3851 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3852 htim->IC_CaptureCallback(htim);
3853 #else
3854 HAL_TIM_IC_CaptureCallback(htim);
3855 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3856 }
3857 /* Output compare event */
3858 else
3859 {
3860 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3861 htim->OC_DelayElapsedCallback(htim);
3862 htim->PWM_PulseFinishedCallback(htim);
3863 #else
3864 HAL_TIM_OC_DelayElapsedCallback(htim);
3865 HAL_TIM_PWM_PulseFinishedCallback(htim);
3866 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3867 }
3868 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3869 }
3870 }
3871 }
3872 /* Capture compare 2 event */
3873 if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
3874 {
3875 if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
3876 {
3877 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
3878 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3879 /* Input capture event */
3880 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
3881 {
3882 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3883 htim->IC_CaptureCallback(htim);
3884 #else
3885 HAL_TIM_IC_CaptureCallback(htim);
3886 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3887 }
3888 /* Output compare event */
3889 else
3890 {
3891 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3892 htim->OC_DelayElapsedCallback(htim);
3893 htim->PWM_PulseFinishedCallback(htim);
3894 #else
3895 HAL_TIM_OC_DelayElapsedCallback(htim);
3896 HAL_TIM_PWM_PulseFinishedCallback(htim);
3897 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3898 }
3899 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3900 }
3901 }
3902 /* Capture compare 3 event */
3903 if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
3904 {
3905 if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
3906 {
3907 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
3908 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3909 /* Input capture event */
3910 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
3911 {
3912 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3913 htim->IC_CaptureCallback(htim);
3914 #else
3915 HAL_TIM_IC_CaptureCallback(htim);
3916 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3917 }
3918 /* Output compare event */
3919 else
3920 {
3921 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3922 htim->OC_DelayElapsedCallback(htim);
3923 htim->PWM_PulseFinishedCallback(htim);
3924 #else
3925 HAL_TIM_OC_DelayElapsedCallback(htim);
3926 HAL_TIM_PWM_PulseFinishedCallback(htim);
3927 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3928 }
3929 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3930 }
3931 }
3932 /* Capture compare 4 event */
3933 if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
3934 {
3935 if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
3936 {
3937 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
3938 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3939 /* Input capture event */
3940 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
3941 {
3942 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3943 htim->IC_CaptureCallback(htim);
3944 #else
3945 HAL_TIM_IC_CaptureCallback(htim);
3946 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3947 }
3948 /* Output compare event */
3949 else
3950 {
3951 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3952 htim->OC_DelayElapsedCallback(htim);
3953 htim->PWM_PulseFinishedCallback(htim);
3954 #else
3955 HAL_TIM_OC_DelayElapsedCallback(htim);
3956 HAL_TIM_PWM_PulseFinishedCallback(htim);
3957 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3958 }
3959 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3960 }
3961 }
3962 /* TIM Update event */
3963 if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
3964 {
3965 if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
3966 {
3967 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
3968 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3969 htim->PeriodElapsedCallback(htim);
3970 #else
3971 HAL_TIM_PeriodElapsedCallback(htim);
3972 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3973 }
3974 }
3975 /* TIM Break input event */
3976 if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
3977 ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
3978 {
3979 if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
3980 {
3981 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
3982 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3983 htim->BreakCallback(htim);
3984 #else
3985 HAL_TIMEx_BreakCallback(htim);
3986 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3987 }
3988 }
3989 /* TIM Break2 input event */
3990 if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
3991 {
3992 if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
3993 {
3994 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
3995 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3996 htim->Break2Callback(htim);
3997 #else
3998 HAL_TIMEx_Break2Callback(htim);
3999 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4000 }
4001 }
4002 /* TIM Trigger detection event */
4003 if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
4004 {
4005 if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
4006 {
4007 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
4008 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4009 htim->TriggerCallback(htim);
4010 #else
4011 HAL_TIM_TriggerCallback(htim);
4012 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4013 }
4014 }
4015 /* TIM commutation event */
4016 if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
4017 {
4018 if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
4019 {
4020 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
4021 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4022 htim->CommutationCallback(htim);
4023 #else
4024 HAL_TIMEx_CommutCallback(htim);
4025 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4026 }
4027 }
4028 }
4029
4030 /**
4031 * @}
4032 */
4033
4034 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
4035 * @brief TIM Peripheral Control functions
4036 *
4037 @verbatim
4038 ==============================================================================
4039 ##### Peripheral Control functions #####
4040 ==============================================================================
4041 [..]
4042 This section provides functions allowing to:
4043 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
4044 (+) Configure External Clock source.
4045 (+) Configure Complementary channels, break features and dead time.
4046 (+) Configure Master and the Slave synchronization.
4047 (+) Configure the DMA Burst Mode.
4048
4049 @endverbatim
4050 * @{
4051 */
4052
4053 /**
4054 * @brief Initializes the TIM Output Compare Channels according to the specified
4055 * parameters in the TIM_OC_InitTypeDef.
4056 * @param htim TIM Output Compare handle
4057 * @param sConfig TIM Output Compare configuration structure
4058 * @param Channel TIM Channels to configure
4059 * This parameter can be one of the following values:
4060 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4061 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4062 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4063 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4064 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
4065 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
4066 * @retval HAL status
4067 */
HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4068 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
4069 const TIM_OC_InitTypeDef *sConfig,
4070 uint32_t Channel)
4071 {
4072 HAL_StatusTypeDef status = HAL_OK;
4073
4074 /* Check the parameters */
4075 assert_param(IS_TIM_CHANNELS(Channel));
4076 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
4077 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4078
4079 /* Process Locked */
4080 __HAL_LOCK(htim);
4081
4082 switch (Channel)
4083 {
4084 case TIM_CHANNEL_1:
4085 {
4086 /* Check the parameters */
4087 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4088
4089 /* Configure the TIM Channel 1 in Output Compare */
4090 TIM_OC1_SetConfig(htim->Instance, sConfig);
4091 break;
4092 }
4093
4094 case TIM_CHANNEL_2:
4095 {
4096 /* Check the parameters */
4097 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4098
4099 /* Configure the TIM Channel 2 in Output Compare */
4100 TIM_OC2_SetConfig(htim->Instance, sConfig);
4101 break;
4102 }
4103
4104 case TIM_CHANNEL_3:
4105 {
4106 /* Check the parameters */
4107 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4108
4109 /* Configure the TIM Channel 3 in Output Compare */
4110 TIM_OC3_SetConfig(htim->Instance, sConfig);
4111 break;
4112 }
4113
4114 case TIM_CHANNEL_4:
4115 {
4116 /* Check the parameters */
4117 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4118
4119 /* Configure the TIM Channel 4 in Output Compare */
4120 TIM_OC4_SetConfig(htim->Instance, sConfig);
4121 break;
4122 }
4123
4124 case TIM_CHANNEL_5:
4125 {
4126 /* Check the parameters */
4127 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
4128
4129 /* Configure the TIM Channel 5 in Output Compare */
4130 TIM_OC5_SetConfig(htim->Instance, sConfig);
4131 break;
4132 }
4133
4134 case TIM_CHANNEL_6:
4135 {
4136 /* Check the parameters */
4137 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
4138
4139 /* Configure the TIM Channel 6 in Output Compare */
4140 TIM_OC6_SetConfig(htim->Instance, sConfig);
4141 break;
4142 }
4143
4144 default:
4145 status = HAL_ERROR;
4146 break;
4147 }
4148
4149 __HAL_UNLOCK(htim);
4150
4151 return status;
4152 }
4153
4154 /**
4155 * @brief Initializes the TIM Input Capture Channels according to the specified
4156 * parameters in the TIM_IC_InitTypeDef.
4157 * @param htim TIM IC handle
4158 * @param sConfig TIM Input Capture configuration structure
4159 * @param Channel TIM Channel to configure
4160 * This parameter can be one of the following values:
4161 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4162 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4163 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4164 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4165 * @retval HAL status
4166 */
HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_IC_InitTypeDef * sConfig,uint32_t Channel)4167 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
4168 {
4169 HAL_StatusTypeDef status = HAL_OK;
4170
4171 /* Check the parameters */
4172 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4173 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
4174 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
4175 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
4176 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
4177
4178 /* Process Locked */
4179 __HAL_LOCK(htim);
4180
4181 if (Channel == TIM_CHANNEL_1)
4182 {
4183 /* TI1 Configuration */
4184 TIM_TI1_SetConfig(htim->Instance,
4185 sConfig->ICPolarity,
4186 sConfig->ICSelection,
4187 sConfig->ICFilter);
4188
4189 /* Reset the IC1PSC Bits */
4190 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4191
4192 /* Set the IC1PSC value */
4193 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
4194 }
4195 else if (Channel == TIM_CHANNEL_2)
4196 {
4197 /* TI2 Configuration */
4198 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4199
4200 TIM_TI2_SetConfig(htim->Instance,
4201 sConfig->ICPolarity,
4202 sConfig->ICSelection,
4203 sConfig->ICFilter);
4204
4205 /* Reset the IC2PSC Bits */
4206 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4207
4208 /* Set the IC2PSC value */
4209 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
4210 }
4211 else if (Channel == TIM_CHANNEL_3)
4212 {
4213 /* TI3 Configuration */
4214 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4215
4216 TIM_TI3_SetConfig(htim->Instance,
4217 sConfig->ICPolarity,
4218 sConfig->ICSelection,
4219 sConfig->ICFilter);
4220
4221 /* Reset the IC3PSC Bits */
4222 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
4223
4224 /* Set the IC3PSC value */
4225 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
4226 }
4227 else if (Channel == TIM_CHANNEL_4)
4228 {
4229 /* TI4 Configuration */
4230 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4231
4232 TIM_TI4_SetConfig(htim->Instance,
4233 sConfig->ICPolarity,
4234 sConfig->ICSelection,
4235 sConfig->ICFilter);
4236
4237 /* Reset the IC4PSC Bits */
4238 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
4239
4240 /* Set the IC4PSC value */
4241 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
4242 }
4243 else
4244 {
4245 status = HAL_ERROR;
4246 }
4247
4248 __HAL_UNLOCK(htim);
4249
4250 return status;
4251 }
4252
4253 /**
4254 * @brief Initializes the TIM PWM channels according to the specified
4255 * parameters in the TIM_OC_InitTypeDef.
4256 * @param htim TIM PWM handle
4257 * @param sConfig TIM PWM configuration structure
4258 * @param Channel TIM Channels to be configured
4259 * This parameter can be one of the following values:
4260 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4261 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4262 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4263 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4264 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
4265 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
4266 * @retval HAL status
4267 */
HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4268 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
4269 const TIM_OC_InitTypeDef *sConfig,
4270 uint32_t Channel)
4271 {
4272 HAL_StatusTypeDef status = HAL_OK;
4273
4274 /* Check the parameters */
4275 assert_param(IS_TIM_CHANNELS(Channel));
4276 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
4277 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4278 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
4279
4280 /* Process Locked */
4281 __HAL_LOCK(htim);
4282
4283 switch (Channel)
4284 {
4285 case TIM_CHANNEL_1:
4286 {
4287 /* Check the parameters */
4288 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4289
4290 /* Configure the Channel 1 in PWM mode */
4291 TIM_OC1_SetConfig(htim->Instance, sConfig);
4292
4293 /* Set the Preload enable bit for channel1 */
4294 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
4295
4296 /* Configure the Output Fast mode */
4297 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
4298 htim->Instance->CCMR1 |= sConfig->OCFastMode;
4299 break;
4300 }
4301
4302 case TIM_CHANNEL_2:
4303 {
4304 /* Check the parameters */
4305 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4306
4307 /* Configure the Channel 2 in PWM mode */
4308 TIM_OC2_SetConfig(htim->Instance, sConfig);
4309
4310 /* Set the Preload enable bit for channel2 */
4311 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
4312
4313 /* Configure the Output Fast mode */
4314 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
4315 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
4316 break;
4317 }
4318
4319 case TIM_CHANNEL_3:
4320 {
4321 /* Check the parameters */
4322 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4323
4324 /* Configure the Channel 3 in PWM mode */
4325 TIM_OC3_SetConfig(htim->Instance, sConfig);
4326
4327 /* Set the Preload enable bit for channel3 */
4328 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
4329
4330 /* Configure the Output Fast mode */
4331 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
4332 htim->Instance->CCMR2 |= sConfig->OCFastMode;
4333 break;
4334 }
4335
4336 case TIM_CHANNEL_4:
4337 {
4338 /* Check the parameters */
4339 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4340
4341 /* Configure the Channel 4 in PWM mode */
4342 TIM_OC4_SetConfig(htim->Instance, sConfig);
4343
4344 /* Set the Preload enable bit for channel4 */
4345 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
4346
4347 /* Configure the Output Fast mode */
4348 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
4349 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
4350 break;
4351 }
4352
4353 case TIM_CHANNEL_5:
4354 {
4355 /* Check the parameters */
4356 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
4357
4358 /* Configure the Channel 5 in PWM mode */
4359 TIM_OC5_SetConfig(htim->Instance, sConfig);
4360
4361 /* Set the Preload enable bit for channel5*/
4362 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
4363
4364 /* Configure the Output Fast mode */
4365 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
4366 htim->Instance->CCMR3 |= sConfig->OCFastMode;
4367 break;
4368 }
4369
4370 case TIM_CHANNEL_6:
4371 {
4372 /* Check the parameters */
4373 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
4374
4375 /* Configure the Channel 6 in PWM mode */
4376 TIM_OC6_SetConfig(htim->Instance, sConfig);
4377
4378 /* Set the Preload enable bit for channel6 */
4379 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
4380
4381 /* Configure the Output Fast mode */
4382 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
4383 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
4384 break;
4385 }
4386
4387 default:
4388 status = HAL_ERROR;
4389 break;
4390 }
4391
4392 __HAL_UNLOCK(htim);
4393
4394 return status;
4395 }
4396
4397 /**
4398 * @brief Initializes the TIM One Pulse Channels according to the specified
4399 * parameters in the TIM_OnePulse_InitTypeDef.
4400 * @param htim TIM One Pulse handle
4401 * @param sConfig TIM One Pulse configuration structure
4402 * @param OutputChannel TIM output channel to configure
4403 * This parameter can be one of the following values:
4404 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4405 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4406 * @param InputChannel TIM input Channel to configure
4407 * This parameter can be one of the following values:
4408 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4409 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4410 * @note To output a waveform with a minimum delay user can enable the fast
4411 * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
4412 * output is forced in response to the edge detection on TIx input,
4413 * without taking in account the comparison.
4414 * @retval HAL status
4415 */
HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OnePulse_InitTypeDef * sConfig,uint32_t OutputChannel,uint32_t InputChannel)4416 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
4417 uint32_t OutputChannel, uint32_t InputChannel)
4418 {
4419 HAL_StatusTypeDef status = HAL_OK;
4420 TIM_OC_InitTypeDef temp1;
4421
4422 /* Check the parameters */
4423 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
4424 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
4425
4426 if (OutputChannel != InputChannel)
4427 {
4428 /* Process Locked */
4429 __HAL_LOCK(htim);
4430
4431 htim->State = HAL_TIM_STATE_BUSY;
4432
4433 /* Extract the Output compare configuration from sConfig structure */
4434 temp1.OCMode = sConfig->OCMode;
4435 temp1.Pulse = sConfig->Pulse;
4436 temp1.OCPolarity = sConfig->OCPolarity;
4437 temp1.OCNPolarity = sConfig->OCNPolarity;
4438 temp1.OCIdleState = sConfig->OCIdleState;
4439 temp1.OCNIdleState = sConfig->OCNIdleState;
4440
4441 switch (OutputChannel)
4442 {
4443 case TIM_CHANNEL_1:
4444 {
4445 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4446
4447 TIM_OC1_SetConfig(htim->Instance, &temp1);
4448 break;
4449 }
4450
4451 case TIM_CHANNEL_2:
4452 {
4453 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4454
4455 TIM_OC2_SetConfig(htim->Instance, &temp1);
4456 break;
4457 }
4458
4459 default:
4460 status = HAL_ERROR;
4461 break;
4462 }
4463
4464 if (status == HAL_OK)
4465 {
4466 switch (InputChannel)
4467 {
4468 case TIM_CHANNEL_1:
4469 {
4470 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4471
4472 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
4473 sConfig->ICSelection, sConfig->ICFilter);
4474
4475 /* Reset the IC1PSC Bits */
4476 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4477
4478 /* Select the Trigger source */
4479 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4480 htim->Instance->SMCR |= TIM_TS_TI1FP1;
4481
4482 /* Select the Slave Mode */
4483 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4484 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4485 break;
4486 }
4487
4488 case TIM_CHANNEL_2:
4489 {
4490 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4491
4492 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
4493 sConfig->ICSelection, sConfig->ICFilter);
4494
4495 /* Reset the IC2PSC Bits */
4496 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4497
4498 /* Select the Trigger source */
4499 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4500 htim->Instance->SMCR |= TIM_TS_TI2FP2;
4501
4502 /* Select the Slave Mode */
4503 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4504 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4505 break;
4506 }
4507
4508 default:
4509 status = HAL_ERROR;
4510 break;
4511 }
4512 }
4513
4514 htim->State = HAL_TIM_STATE_READY;
4515
4516 __HAL_UNLOCK(htim);
4517
4518 return status;
4519 }
4520 else
4521 {
4522 return HAL_ERROR;
4523 }
4524 }
4525
4526 /**
4527 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
4528 * @param htim TIM handle
4529 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4530 * This parameter can be one of the following values:
4531 * @arg TIM_DMABASE_CR1
4532 * @arg TIM_DMABASE_CR2
4533 * @arg TIM_DMABASE_SMCR
4534 * @arg TIM_DMABASE_DIER
4535 * @arg TIM_DMABASE_SR
4536 * @arg TIM_DMABASE_EGR
4537 * @arg TIM_DMABASE_CCMR1
4538 * @arg TIM_DMABASE_CCMR2
4539 * @arg TIM_DMABASE_CCER
4540 * @arg TIM_DMABASE_CNT
4541 * @arg TIM_DMABASE_PSC
4542 * @arg TIM_DMABASE_ARR
4543 * @arg TIM_DMABASE_RCR
4544 * @arg TIM_DMABASE_CCR1
4545 * @arg TIM_DMABASE_CCR2
4546 * @arg TIM_DMABASE_CCR3
4547 * @arg TIM_DMABASE_CCR4
4548 * @arg TIM_DMABASE_BDTR
4549 * @arg TIM_DMABASE_OR
4550 * @arg TIM_DMABASE_CCMR3
4551 * @arg TIM_DMABASE_CCR5
4552 * @arg TIM_DMABASE_CCR6
4553 * @arg TIM_DMABASE_AF1 (*)
4554 * @arg TIM_DMABASE_AF2 (*)
4555 * (*) value not defined in all devices
4556 * @param BurstRequestSrc TIM DMA Request sources
4557 * This parameter can be one of the following values:
4558 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4559 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4560 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4561 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4562 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4563 * @arg TIM_DMA_COM: TIM Commutation DMA source
4564 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4565 * @param BurstBuffer The Buffer address.
4566 * @param BurstLength DMA Burst length. This parameter can be one value
4567 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4568 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4569 * @retval HAL status
4570 */
HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,const uint32_t * BurstBuffer,uint32_t BurstLength)4571 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4572 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
4573 uint32_t BurstLength)
4574 {
4575 HAL_StatusTypeDef status;
4576
4577 status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4578 ((BurstLength) >> 8U) + 1U);
4579
4580
4581
4582 return status;
4583 }
4584
4585 /**
4586 * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
4587 * @param htim TIM handle
4588 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4589 * This parameter can be one of the following values:
4590 * @arg TIM_DMABASE_CR1
4591 * @arg TIM_DMABASE_CR2
4592 * @arg TIM_DMABASE_SMCR
4593 * @arg TIM_DMABASE_DIER
4594 * @arg TIM_DMABASE_SR
4595 * @arg TIM_DMABASE_EGR
4596 * @arg TIM_DMABASE_CCMR1
4597 * @arg TIM_DMABASE_CCMR2
4598 * @arg TIM_DMABASE_CCER
4599 * @arg TIM_DMABASE_CNT
4600 * @arg TIM_DMABASE_PSC
4601 * @arg TIM_DMABASE_ARR
4602 * @arg TIM_DMABASE_RCR
4603 * @arg TIM_DMABASE_CCR1
4604 * @arg TIM_DMABASE_CCR2
4605 * @arg TIM_DMABASE_CCR3
4606 * @arg TIM_DMABASE_CCR4
4607 * @arg TIM_DMABASE_BDTR
4608 * @arg TIM_DMABASE_OR
4609 * @arg TIM_DMABASE_CCMR3
4610 * @arg TIM_DMABASE_CCR5
4611 * @arg TIM_DMABASE_CCR6
4612 * @arg TIM_DMABASE_AF1 (*)
4613 * @arg TIM_DMABASE_AF2 (*)
4614 * (*) value not defined in all devices
4615 * @param BurstRequestSrc TIM DMA Request sources
4616 * This parameter can be one of the following values:
4617 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4618 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4619 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4620 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4621 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4622 * @arg TIM_DMA_COM: TIM Commutation DMA source
4623 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4624 * @param BurstBuffer The Buffer address.
4625 * @param BurstLength DMA Burst length. This parameter can be one value
4626 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4627 * @param DataLength Data length. This parameter can be one value
4628 * between 1 and 0xFFFF.
4629 * @retval HAL status
4630 */
HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,const uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4631 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4632 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
4633 uint32_t BurstLength, uint32_t DataLength)
4634 {
4635 HAL_StatusTypeDef status = HAL_OK;
4636
4637 /* Check the parameters */
4638 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4639 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4640 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4641 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4642 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4643
4644 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4645 {
4646 return HAL_BUSY;
4647 }
4648 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4649 {
4650 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4651 {
4652 return HAL_ERROR;
4653 }
4654 else
4655 {
4656 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4657 }
4658 }
4659 else
4660 {
4661 /* nothing to do */
4662 }
4663
4664 switch (BurstRequestSrc)
4665 {
4666 case TIM_DMA_UPDATE:
4667 {
4668 /* Set the DMA Period elapsed callbacks */
4669 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4670 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4671
4672 /* Set the DMA error callback */
4673 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4674
4675 /* Enable the DMA stream */
4676 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
4677 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4678 {
4679 /* Return error status */
4680 return HAL_ERROR;
4681 }
4682 break;
4683 }
4684 case TIM_DMA_CC1:
4685 {
4686 /* Set the DMA compare callbacks */
4687 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
4688 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4689
4690 /* Set the DMA error callback */
4691 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4692
4693 /* Enable the DMA stream */
4694 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
4695 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4696 {
4697 /* Return error status */
4698 return HAL_ERROR;
4699 }
4700 break;
4701 }
4702 case TIM_DMA_CC2:
4703 {
4704 /* Set the DMA compare callbacks */
4705 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
4706 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4707
4708 /* Set the DMA error callback */
4709 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4710
4711 /* Enable the DMA stream */
4712 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
4713 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4714 {
4715 /* Return error status */
4716 return HAL_ERROR;
4717 }
4718 break;
4719 }
4720 case TIM_DMA_CC3:
4721 {
4722 /* Set the DMA compare callbacks */
4723 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
4724 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4725
4726 /* Set the DMA error callback */
4727 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4728
4729 /* Enable the DMA stream */
4730 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
4731 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4732 {
4733 /* Return error status */
4734 return HAL_ERROR;
4735 }
4736 break;
4737 }
4738 case TIM_DMA_CC4:
4739 {
4740 /* Set the DMA compare callbacks */
4741 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
4742 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4743
4744 /* Set the DMA error callback */
4745 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4746
4747 /* Enable the DMA stream */
4748 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
4749 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4750 {
4751 /* Return error status */
4752 return HAL_ERROR;
4753 }
4754 break;
4755 }
4756 case TIM_DMA_COM:
4757 {
4758 /* Set the DMA commutation callbacks */
4759 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4760 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
4761
4762 /* Set the DMA error callback */
4763 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4764
4765 /* Enable the DMA stream */
4766 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
4767 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4768 {
4769 /* Return error status */
4770 return HAL_ERROR;
4771 }
4772 break;
4773 }
4774 case TIM_DMA_TRIGGER:
4775 {
4776 /* Set the DMA trigger callbacks */
4777 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4778 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4779
4780 /* Set the DMA error callback */
4781 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4782
4783 /* Enable the DMA stream */
4784 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
4785 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4786 {
4787 /* Return error status */
4788 return HAL_ERROR;
4789 }
4790 break;
4791 }
4792 default:
4793 status = HAL_ERROR;
4794 break;
4795 }
4796
4797 if (status == HAL_OK)
4798 {
4799 /* Configure the DMA Burst Mode */
4800 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4801 /* Enable the TIM DMA Request */
4802 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4803 }
4804
4805 /* Return function status */
4806 return status;
4807 }
4808
4809 /**
4810 * @brief Stops the TIM DMA Burst mode
4811 * @param htim TIM handle
4812 * @param BurstRequestSrc TIM DMA Request sources to disable
4813 * @retval HAL status
4814 */
HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4815 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4816 {
4817 HAL_StatusTypeDef status = HAL_OK;
4818
4819 /* Check the parameters */
4820 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4821
4822 /* Abort the DMA transfer (at least disable the DMA stream) */
4823 switch (BurstRequestSrc)
4824 {
4825 case TIM_DMA_UPDATE:
4826 {
4827 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4828 break;
4829 }
4830 case TIM_DMA_CC1:
4831 {
4832 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4833 break;
4834 }
4835 case TIM_DMA_CC2:
4836 {
4837 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
4838 break;
4839 }
4840 case TIM_DMA_CC3:
4841 {
4842 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
4843 break;
4844 }
4845 case TIM_DMA_CC4:
4846 {
4847 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
4848 break;
4849 }
4850 case TIM_DMA_COM:
4851 {
4852 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
4853 break;
4854 }
4855 case TIM_DMA_TRIGGER:
4856 {
4857 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
4858 break;
4859 }
4860 default:
4861 status = HAL_ERROR;
4862 break;
4863 }
4864
4865 if (status == HAL_OK)
4866 {
4867 /* Disable the TIM Update DMA request */
4868 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4869
4870 /* Change the DMA burst operation state */
4871 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
4872 }
4873
4874 /* Return function status */
4875 return status;
4876 }
4877
4878 /**
4879 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4880 * @param htim TIM handle
4881 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4882 * This parameter can be one of the following values:
4883 * @arg TIM_DMABASE_CR1
4884 * @arg TIM_DMABASE_CR2
4885 * @arg TIM_DMABASE_SMCR
4886 * @arg TIM_DMABASE_DIER
4887 * @arg TIM_DMABASE_SR
4888 * @arg TIM_DMABASE_EGR
4889 * @arg TIM_DMABASE_CCMR1
4890 * @arg TIM_DMABASE_CCMR2
4891 * @arg TIM_DMABASE_CCER
4892 * @arg TIM_DMABASE_CNT
4893 * @arg TIM_DMABASE_PSC
4894 * @arg TIM_DMABASE_ARR
4895 * @arg TIM_DMABASE_RCR
4896 * @arg TIM_DMABASE_CCR1
4897 * @arg TIM_DMABASE_CCR2
4898 * @arg TIM_DMABASE_CCR3
4899 * @arg TIM_DMABASE_CCR4
4900 * @arg TIM_DMABASE_BDTR
4901 * @arg TIM_DMABASE_OR
4902 * @arg TIM_DMABASE_CCMR3
4903 * @arg TIM_DMABASE_CCR5
4904 * @arg TIM_DMABASE_CCR6
4905 * @arg TIM_DMABASE_AF1 (*)
4906 * @arg TIM_DMABASE_AF2 (*)
4907 * (*) value not defined in all devices
4908 * @param BurstRequestSrc TIM DMA Request sources
4909 * This parameter can be one of the following values:
4910 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4911 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4912 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4913 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4914 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4915 * @arg TIM_DMA_COM: TIM Commutation DMA source
4916 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4917 * @param BurstBuffer The Buffer address.
4918 * @param BurstLength DMA Burst length. This parameter can be one value
4919 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4920 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4921 * @retval HAL status
4922 */
HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)4923 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4924 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
4925 {
4926 HAL_StatusTypeDef status;
4927
4928 status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4929 ((BurstLength) >> 8U) + 1U);
4930
4931
4932 return status;
4933 }
4934
4935 /**
4936 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4937 * @param htim TIM handle
4938 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4939 * This parameter can be one of the following values:
4940 * @arg TIM_DMABASE_CR1
4941 * @arg TIM_DMABASE_CR2
4942 * @arg TIM_DMABASE_SMCR
4943 * @arg TIM_DMABASE_DIER
4944 * @arg TIM_DMABASE_SR
4945 * @arg TIM_DMABASE_EGR
4946 * @arg TIM_DMABASE_CCMR1
4947 * @arg TIM_DMABASE_CCMR2
4948 * @arg TIM_DMABASE_CCER
4949 * @arg TIM_DMABASE_CNT
4950 * @arg TIM_DMABASE_PSC
4951 * @arg TIM_DMABASE_ARR
4952 * @arg TIM_DMABASE_RCR
4953 * @arg TIM_DMABASE_CCR1
4954 * @arg TIM_DMABASE_CCR2
4955 * @arg TIM_DMABASE_CCR3
4956 * @arg TIM_DMABASE_CCR4
4957 * @arg TIM_DMABASE_BDTR
4958 * @arg TIM_DMABASE_OR
4959 * @arg TIM_DMABASE_CCMR3
4960 * @arg TIM_DMABASE_CCR5
4961 * @arg TIM_DMABASE_CCR6
4962 * @arg TIM_DMABASE_AF1 (*)
4963 * @arg TIM_DMABASE_AF2 (*)
4964 * (*) value not defined in all devices
4965 * @param BurstRequestSrc TIM DMA Request sources
4966 * This parameter can be one of the following values:
4967 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4968 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4969 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4970 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4971 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4972 * @arg TIM_DMA_COM: TIM Commutation DMA source
4973 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4974 * @param BurstBuffer The Buffer address.
4975 * @param BurstLength DMA Burst length. This parameter can be one value
4976 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4977 * @param DataLength Data length. This parameter can be one value
4978 * between 1 and 0xFFFF.
4979 * @retval HAL status
4980 */
HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4981 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4982 uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
4983 uint32_t BurstLength, uint32_t DataLength)
4984 {
4985 HAL_StatusTypeDef status = HAL_OK;
4986
4987 /* Check the parameters */
4988 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4989 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4990 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4991 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4992 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4993
4994 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4995 {
4996 return HAL_BUSY;
4997 }
4998 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4999 {
5000 if ((BurstBuffer == NULL) && (BurstLength > 0U))
5001 {
5002 return HAL_ERROR;
5003 }
5004 else
5005 {
5006 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
5007 }
5008 }
5009 else
5010 {
5011 /* nothing to do */
5012 }
5013 switch (BurstRequestSrc)
5014 {
5015 case TIM_DMA_UPDATE:
5016 {
5017 /* Set the DMA Period elapsed callbacks */
5018 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
5019 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
5020
5021 /* Set the DMA error callback */
5022 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
5023
5024 /* Enable the DMA stream */
5025 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5026 DataLength) != HAL_OK)
5027 {
5028 /* Return error status */
5029 return HAL_ERROR;
5030 }
5031 break;
5032 }
5033 case TIM_DMA_CC1:
5034 {
5035 /* Set the DMA capture callbacks */
5036 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
5037 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5038
5039 /* Set the DMA error callback */
5040 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
5041
5042 /* Enable the DMA stream */
5043 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5044 DataLength) != HAL_OK)
5045 {
5046 /* Return error status */
5047 return HAL_ERROR;
5048 }
5049 break;
5050 }
5051 case TIM_DMA_CC2:
5052 {
5053 /* Set the DMA capture callbacks */
5054 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
5055 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5056
5057 /* Set the DMA error callback */
5058 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
5059
5060 /* Enable the DMA stream */
5061 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5062 DataLength) != HAL_OK)
5063 {
5064 /* Return error status */
5065 return HAL_ERROR;
5066 }
5067 break;
5068 }
5069 case TIM_DMA_CC3:
5070 {
5071 /* Set the DMA capture callbacks */
5072 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
5073 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5074
5075 /* Set the DMA error callback */
5076 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
5077
5078 /* Enable the DMA stream */
5079 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5080 DataLength) != HAL_OK)
5081 {
5082 /* Return error status */
5083 return HAL_ERROR;
5084 }
5085 break;
5086 }
5087 case TIM_DMA_CC4:
5088 {
5089 /* Set the DMA capture callbacks */
5090 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
5091 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5092
5093 /* Set the DMA error callback */
5094 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
5095
5096 /* Enable the DMA stream */
5097 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5098 DataLength) != HAL_OK)
5099 {
5100 /* Return error status */
5101 return HAL_ERROR;
5102 }
5103 break;
5104 }
5105 case TIM_DMA_COM:
5106 {
5107 /* Set the DMA commutation callbacks */
5108 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
5109 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
5110
5111 /* Set the DMA error callback */
5112 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
5113
5114 /* Enable the DMA stream */
5115 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5116 DataLength) != HAL_OK)
5117 {
5118 /* Return error status */
5119 return HAL_ERROR;
5120 }
5121 break;
5122 }
5123 case TIM_DMA_TRIGGER:
5124 {
5125 /* Set the DMA trigger callbacks */
5126 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
5127 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
5128
5129 /* Set the DMA error callback */
5130 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
5131
5132 /* Enable the DMA stream */
5133 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5134 DataLength) != HAL_OK)
5135 {
5136 /* Return error status */
5137 return HAL_ERROR;
5138 }
5139 break;
5140 }
5141 default:
5142 status = HAL_ERROR;
5143 break;
5144 }
5145
5146 if (status == HAL_OK)
5147 {
5148 /* Configure the DMA Burst Mode */
5149 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
5150
5151 /* Enable the TIM DMA Request */
5152 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
5153 }
5154
5155 /* Return function status */
5156 return status;
5157 }
5158
5159 /**
5160 * @brief Stop the DMA burst reading
5161 * @param htim TIM handle
5162 * @param BurstRequestSrc TIM DMA Request sources to disable.
5163 * @retval HAL status
5164 */
HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)5165 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
5166 {
5167 HAL_StatusTypeDef status = HAL_OK;
5168
5169 /* Check the parameters */
5170 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
5171
5172 /* Abort the DMA transfer (at least disable the DMA stream) */
5173 switch (BurstRequestSrc)
5174 {
5175 case TIM_DMA_UPDATE:
5176 {
5177 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
5178 break;
5179 }
5180 case TIM_DMA_CC1:
5181 {
5182 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
5183 break;
5184 }
5185 case TIM_DMA_CC2:
5186 {
5187 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
5188 break;
5189 }
5190 case TIM_DMA_CC3:
5191 {
5192 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
5193 break;
5194 }
5195 case TIM_DMA_CC4:
5196 {
5197 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
5198 break;
5199 }
5200 case TIM_DMA_COM:
5201 {
5202 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
5203 break;
5204 }
5205 case TIM_DMA_TRIGGER:
5206 {
5207 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
5208 break;
5209 }
5210 default:
5211 status = HAL_ERROR;
5212 break;
5213 }
5214
5215 if (status == HAL_OK)
5216 {
5217 /* Disable the TIM Update DMA request */
5218 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
5219
5220 /* Change the DMA burst operation state */
5221 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
5222 }
5223
5224 /* Return function status */
5225 return status;
5226 }
5227
5228 /**
5229 * @brief Generate a software event
5230 * @param htim TIM handle
5231 * @param EventSource specifies the event source.
5232 * This parameter can be one of the following values:
5233 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
5234 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
5235 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
5236 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
5237 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
5238 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
5239 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
5240 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
5241 * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
5242 * @note Basic timers can only generate an update event.
5243 * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
5244 * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
5245 * only for timer instances supporting break input(s).
5246 * @retval HAL status
5247 */
5248
HAL_TIM_GenerateEvent(TIM_HandleTypeDef * htim,uint32_t EventSource)5249 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
5250 {
5251 /* Check the parameters */
5252 assert_param(IS_TIM_INSTANCE(htim->Instance));
5253 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
5254
5255 /* Process Locked */
5256 __HAL_LOCK(htim);
5257
5258 /* Change the TIM state */
5259 htim->State = HAL_TIM_STATE_BUSY;
5260
5261 /* Set the event sources */
5262 htim->Instance->EGR = EventSource;
5263
5264 /* Change the TIM state */
5265 htim->State = HAL_TIM_STATE_READY;
5266
5267 __HAL_UNLOCK(htim);
5268
5269 /* Return function status */
5270 return HAL_OK;
5271 }
5272
5273 /**
5274 * @brief Configures the OCRef clear feature
5275 * @param htim TIM handle
5276 * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
5277 * contains the OCREF clear feature and parameters for the TIM peripheral.
5278 * @param Channel specifies the TIM Channel
5279 * This parameter can be one of the following values:
5280 * @arg TIM_CHANNEL_1: TIM Channel 1
5281 * @arg TIM_CHANNEL_2: TIM Channel 2
5282 * @arg TIM_CHANNEL_3: TIM Channel 3
5283 * @arg TIM_CHANNEL_4: TIM Channel 4
5284 * @arg TIM_CHANNEL_5: TIM Channel 5
5285 * @arg TIM_CHANNEL_6: TIM Channel 6
5286 * @retval HAL status
5287 */
HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef * htim,const TIM_ClearInputConfigTypeDef * sClearInputConfig,uint32_t Channel)5288 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
5289 const TIM_ClearInputConfigTypeDef *sClearInputConfig,
5290 uint32_t Channel)
5291 {
5292 HAL_StatusTypeDef status = HAL_OK;
5293
5294 /* Check the parameters */
5295 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
5296 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
5297
5298 /* Process Locked */
5299 __HAL_LOCK(htim);
5300
5301 htim->State = HAL_TIM_STATE_BUSY;
5302
5303 switch (sClearInputConfig->ClearInputSource)
5304 {
5305 case TIM_CLEARINPUTSOURCE_NONE:
5306 {
5307 /* Clear the OCREF clear selection bit and the the ETR Bits */
5308 CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
5309 break;
5310 }
5311
5312 case TIM_CLEARINPUTSOURCE_ETR:
5313 {
5314 /* Check the parameters */
5315 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
5316 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
5317 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
5318
5319 /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
5320 if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
5321 {
5322 htim->State = HAL_TIM_STATE_READY;
5323 __HAL_UNLOCK(htim);
5324 return HAL_ERROR;
5325 }
5326
5327 TIM_ETR_SetConfig(htim->Instance,
5328 sClearInputConfig->ClearInputPrescaler,
5329 sClearInputConfig->ClearInputPolarity,
5330 sClearInputConfig->ClearInputFilter);
5331 break;
5332 }
5333
5334 default:
5335 status = HAL_ERROR;
5336 break;
5337 }
5338
5339 if (status == HAL_OK)
5340 {
5341 switch (Channel)
5342 {
5343 case TIM_CHANNEL_1:
5344 {
5345 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5346 {
5347 /* Enable the OCREF clear feature for Channel 1 */
5348 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5349 }
5350 else
5351 {
5352 /* Disable the OCREF clear feature for Channel 1 */
5353 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5354 }
5355 break;
5356 }
5357 case TIM_CHANNEL_2:
5358 {
5359 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5360 {
5361 /* Enable the OCREF clear feature for Channel 2 */
5362 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5363 }
5364 else
5365 {
5366 /* Disable the OCREF clear feature for Channel 2 */
5367 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5368 }
5369 break;
5370 }
5371 case TIM_CHANNEL_3:
5372 {
5373 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5374 {
5375 /* Enable the OCREF clear feature for Channel 3 */
5376 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5377 }
5378 else
5379 {
5380 /* Disable the OCREF clear feature for Channel 3 */
5381 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5382 }
5383 break;
5384 }
5385 case TIM_CHANNEL_4:
5386 {
5387 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5388 {
5389 /* Enable the OCREF clear feature for Channel 4 */
5390 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5391 }
5392 else
5393 {
5394 /* Disable the OCREF clear feature for Channel 4 */
5395 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5396 }
5397 break;
5398 }
5399 case TIM_CHANNEL_5:
5400 {
5401 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5402 {
5403 /* Enable the OCREF clear feature for Channel 5 */
5404 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
5405 }
5406 else
5407 {
5408 /* Disable the OCREF clear feature for Channel 5 */
5409 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
5410 }
5411 break;
5412 }
5413 case TIM_CHANNEL_6:
5414 {
5415 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5416 {
5417 /* Enable the OCREF clear feature for Channel 6 */
5418 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
5419 }
5420 else
5421 {
5422 /* Disable the OCREF clear feature for Channel 6 */
5423 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
5424 }
5425 break;
5426 }
5427 default:
5428 break;
5429 }
5430 }
5431
5432 htim->State = HAL_TIM_STATE_READY;
5433
5434 __HAL_UNLOCK(htim);
5435
5436 return status;
5437 }
5438
5439 /**
5440 * @brief Configures the clock source to be used
5441 * @param htim TIM handle
5442 * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
5443 * contains the clock source information for the TIM peripheral.
5444 * @retval HAL status
5445 */
HAL_TIM_ConfigClockSource(TIM_HandleTypeDef * htim,const TIM_ClockConfigTypeDef * sClockSourceConfig)5446 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
5447 {
5448 HAL_StatusTypeDef status = HAL_OK;
5449 uint32_t tmpsmcr;
5450
5451 /* Process Locked */
5452 __HAL_LOCK(htim);
5453
5454 htim->State = HAL_TIM_STATE_BUSY;
5455
5456 /* Check the parameters */
5457 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
5458
5459 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
5460 tmpsmcr = htim->Instance->SMCR;
5461 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
5462 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
5463 htim->Instance->SMCR = tmpsmcr;
5464
5465 switch (sClockSourceConfig->ClockSource)
5466 {
5467 case TIM_CLOCKSOURCE_INTERNAL:
5468 {
5469 assert_param(IS_TIM_INSTANCE(htim->Instance));
5470 break;
5471 }
5472
5473 case TIM_CLOCKSOURCE_ETRMODE1:
5474 {
5475 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
5476 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
5477
5478 /* Check ETR input conditioning related parameters */
5479 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5480 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5481 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5482
5483 /* Configure the ETR Clock source */
5484 TIM_ETR_SetConfig(htim->Instance,
5485 sClockSourceConfig->ClockPrescaler,
5486 sClockSourceConfig->ClockPolarity,
5487 sClockSourceConfig->ClockFilter);
5488
5489 /* Select the External clock mode1 and the ETRF trigger */
5490 tmpsmcr = htim->Instance->SMCR;
5491 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
5492 /* Write to TIMx SMCR */
5493 htim->Instance->SMCR = tmpsmcr;
5494 break;
5495 }
5496
5497 case TIM_CLOCKSOURCE_ETRMODE2:
5498 {
5499 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
5500 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
5501
5502 /* Check ETR input conditioning related parameters */
5503 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5504 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5505 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5506
5507 /* Configure the ETR Clock source */
5508 TIM_ETR_SetConfig(htim->Instance,
5509 sClockSourceConfig->ClockPrescaler,
5510 sClockSourceConfig->ClockPolarity,
5511 sClockSourceConfig->ClockFilter);
5512 /* Enable the External clock mode2 */
5513 htim->Instance->SMCR |= TIM_SMCR_ECE;
5514 break;
5515 }
5516
5517 case TIM_CLOCKSOURCE_TI1:
5518 {
5519 /* Check whether or not the timer instance supports external clock mode 1 */
5520 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5521
5522 /* Check TI1 input conditioning related parameters */
5523 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5524 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5525
5526 TIM_TI1_ConfigInputStage(htim->Instance,
5527 sClockSourceConfig->ClockPolarity,
5528 sClockSourceConfig->ClockFilter);
5529 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
5530 break;
5531 }
5532
5533 case TIM_CLOCKSOURCE_TI2:
5534 {
5535 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
5536 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5537
5538 /* Check TI2 input conditioning related parameters */
5539 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5540 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5541
5542 TIM_TI2_ConfigInputStage(htim->Instance,
5543 sClockSourceConfig->ClockPolarity,
5544 sClockSourceConfig->ClockFilter);
5545 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
5546 break;
5547 }
5548
5549 case TIM_CLOCKSOURCE_TI1ED:
5550 {
5551 /* Check whether or not the timer instance supports external clock mode 1 */
5552 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5553
5554 /* Check TI1 input conditioning related parameters */
5555 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5556 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5557
5558 TIM_TI1_ConfigInputStage(htim->Instance,
5559 sClockSourceConfig->ClockPolarity,
5560 sClockSourceConfig->ClockFilter);
5561 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
5562 break;
5563 }
5564
5565 case TIM_CLOCKSOURCE_ITR0:
5566 case TIM_CLOCKSOURCE_ITR1:
5567 case TIM_CLOCKSOURCE_ITR2:
5568 case TIM_CLOCKSOURCE_ITR3:
5569 {
5570 /* Check whether or not the timer instance supports internal trigger input */
5571 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
5572
5573 TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
5574 break;
5575 }
5576
5577 default:
5578 status = HAL_ERROR;
5579 break;
5580 }
5581 htim->State = HAL_TIM_STATE_READY;
5582
5583 __HAL_UNLOCK(htim);
5584
5585 return status;
5586 }
5587
5588 /**
5589 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
5590 * or a XOR combination between CH1_input, CH2_input & CH3_input
5591 * @param htim TIM handle.
5592 * @param TI1_Selection Indicate whether or not channel 1 is connected to the
5593 * output of a XOR gate.
5594 * This parameter can be one of the following values:
5595 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
5596 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
5597 * pins are connected to the TI1 input (XOR combination)
5598 * @retval HAL status
5599 */
HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef * htim,uint32_t TI1_Selection)5600 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
5601 {
5602 uint32_t tmpcr2;
5603
5604 /* Check the parameters */
5605 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
5606 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
5607
5608 /* Get the TIMx CR2 register value */
5609 tmpcr2 = htim->Instance->CR2;
5610
5611 /* Reset the TI1 selection */
5612 tmpcr2 &= ~TIM_CR2_TI1S;
5613
5614 /* Set the TI1 selection */
5615 tmpcr2 |= TI1_Selection;
5616
5617 /* Write to TIMxCR2 */
5618 htim->Instance->CR2 = tmpcr2;
5619
5620 return HAL_OK;
5621 }
5622
5623 /**
5624 * @brief Configures the TIM in Slave mode
5625 * @param htim TIM handle.
5626 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5627 * contains the selected trigger (internal trigger input, filtered
5628 * timer input or external trigger input) and the Slave mode
5629 * (Disable, Reset, Gated, Trigger, External clock mode 1).
5630 * @retval HAL status
5631 */
HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)5632 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
5633 {
5634 /* Check the parameters */
5635 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5636 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5637 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
5638
5639 __HAL_LOCK(htim);
5640
5641 htim->State = HAL_TIM_STATE_BUSY;
5642
5643 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5644 {
5645 htim->State = HAL_TIM_STATE_READY;
5646 __HAL_UNLOCK(htim);
5647 return HAL_ERROR;
5648 }
5649
5650 /* Disable Trigger Interrupt */
5651 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
5652
5653 /* Disable Trigger DMA request */
5654 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5655
5656 htim->State = HAL_TIM_STATE_READY;
5657
5658 __HAL_UNLOCK(htim);
5659
5660 return HAL_OK;
5661 }
5662
5663 /**
5664 * @brief Configures the TIM in Slave mode in interrupt mode
5665 * @param htim TIM handle.
5666 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5667 * contains the selected trigger (internal trigger input, filtered
5668 * timer input or external trigger input) and the Slave mode
5669 * (Disable, Reset, Gated, Trigger, External clock mode 1).
5670 * @retval HAL status
5671 */
HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)5672 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
5673 const TIM_SlaveConfigTypeDef *sSlaveConfig)
5674 {
5675 /* Check the parameters */
5676 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5677 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5678 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
5679
5680 __HAL_LOCK(htim);
5681
5682 htim->State = HAL_TIM_STATE_BUSY;
5683
5684 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5685 {
5686 htim->State = HAL_TIM_STATE_READY;
5687 __HAL_UNLOCK(htim);
5688 return HAL_ERROR;
5689 }
5690
5691 /* Enable Trigger Interrupt */
5692 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
5693
5694 /* Disable Trigger DMA request */
5695 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5696
5697 htim->State = HAL_TIM_STATE_READY;
5698
5699 __HAL_UNLOCK(htim);
5700
5701 return HAL_OK;
5702 }
5703
5704 /**
5705 * @brief Read the captured value from Capture Compare unit
5706 * @param htim TIM handle.
5707 * @param Channel TIM Channels to be enabled
5708 * This parameter can be one of the following values:
5709 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
5710 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
5711 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
5712 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
5713 * @retval Captured value
5714 */
HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef * htim,uint32_t Channel)5715 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)
5716 {
5717 uint32_t tmpreg = 0U;
5718
5719 switch (Channel)
5720 {
5721 case TIM_CHANNEL_1:
5722 {
5723 /* Check the parameters */
5724 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
5725
5726 /* Return the capture 1 value */
5727 tmpreg = htim->Instance->CCR1;
5728
5729 break;
5730 }
5731 case TIM_CHANNEL_2:
5732 {
5733 /* Check the parameters */
5734 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
5735
5736 /* Return the capture 2 value */
5737 tmpreg = htim->Instance->CCR2;
5738
5739 break;
5740 }
5741
5742 case TIM_CHANNEL_3:
5743 {
5744 /* Check the parameters */
5745 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
5746
5747 /* Return the capture 3 value */
5748 tmpreg = htim->Instance->CCR3;
5749
5750 break;
5751 }
5752
5753 case TIM_CHANNEL_4:
5754 {
5755 /* Check the parameters */
5756 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
5757
5758 /* Return the capture 4 value */
5759 tmpreg = htim->Instance->CCR4;
5760
5761 break;
5762 }
5763
5764 default:
5765 break;
5766 }
5767
5768 return tmpreg;
5769 }
5770
5771 /**
5772 * @}
5773 */
5774
5775 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
5776 * @brief TIM Callbacks functions
5777 *
5778 @verbatim
5779 ==============================================================================
5780 ##### TIM Callbacks functions #####
5781 ==============================================================================
5782 [..]
5783 This section provides TIM callback functions:
5784 (+) TIM Period elapsed callback
5785 (+) TIM Output Compare callback
5786 (+) TIM Input capture callback
5787 (+) TIM Trigger callback
5788 (+) TIM Error callback
5789
5790 @endverbatim
5791 * @{
5792 */
5793
5794 /**
5795 * @brief Period elapsed callback in non-blocking mode
5796 * @param htim TIM handle
5797 * @retval None
5798 */
HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef * htim)5799 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
5800 {
5801 /* Prevent unused argument(s) compilation warning */
5802 UNUSED(htim);
5803
5804 /* NOTE : This function should not be modified, when the callback is needed,
5805 the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
5806 */
5807 }
5808
5809 /**
5810 * @brief Period elapsed half complete callback in non-blocking mode
5811 * @param htim TIM handle
5812 * @retval None
5813 */
HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef * htim)5814 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
5815 {
5816 /* Prevent unused argument(s) compilation warning */
5817 UNUSED(htim);
5818
5819 /* NOTE : This function should not be modified, when the callback is needed,
5820 the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
5821 */
5822 }
5823
5824 /**
5825 * @brief Output Compare callback in non-blocking mode
5826 * @param htim TIM OC handle
5827 * @retval None
5828 */
HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef * htim)5829 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
5830 {
5831 /* Prevent unused argument(s) compilation warning */
5832 UNUSED(htim);
5833
5834 /* NOTE : This function should not be modified, when the callback is needed,
5835 the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
5836 */
5837 }
5838
5839 /**
5840 * @brief Input Capture callback in non-blocking mode
5841 * @param htim TIM IC handle
5842 * @retval None
5843 */
HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef * htim)5844 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
5845 {
5846 /* Prevent unused argument(s) compilation warning */
5847 UNUSED(htim);
5848
5849 /* NOTE : This function should not be modified, when the callback is needed,
5850 the HAL_TIM_IC_CaptureCallback could be implemented in the user file
5851 */
5852 }
5853
5854 /**
5855 * @brief Input Capture half complete callback in non-blocking mode
5856 * @param htim TIM IC handle
5857 * @retval None
5858 */
HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef * htim)5859 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
5860 {
5861 /* Prevent unused argument(s) compilation warning */
5862 UNUSED(htim);
5863
5864 /* NOTE : This function should not be modified, when the callback is needed,
5865 the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
5866 */
5867 }
5868
5869 /**
5870 * @brief PWM Pulse finished callback in non-blocking mode
5871 * @param htim TIM handle
5872 * @retval None
5873 */
HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef * htim)5874 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
5875 {
5876 /* Prevent unused argument(s) compilation warning */
5877 UNUSED(htim);
5878
5879 /* NOTE : This function should not be modified, when the callback is needed,
5880 the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
5881 */
5882 }
5883
5884 /**
5885 * @brief PWM Pulse finished half complete callback in non-blocking mode
5886 * @param htim TIM handle
5887 * @retval None
5888 */
HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef * htim)5889 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
5890 {
5891 /* Prevent unused argument(s) compilation warning */
5892 UNUSED(htim);
5893
5894 /* NOTE : This function should not be modified, when the callback is needed,
5895 the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
5896 */
5897 }
5898
5899 /**
5900 * @brief Hall Trigger detection callback in non-blocking mode
5901 * @param htim TIM handle
5902 * @retval None
5903 */
HAL_TIM_TriggerCallback(TIM_HandleTypeDef * htim)5904 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
5905 {
5906 /* Prevent unused argument(s) compilation warning */
5907 UNUSED(htim);
5908
5909 /* NOTE : This function should not be modified, when the callback is needed,
5910 the HAL_TIM_TriggerCallback could be implemented in the user file
5911 */
5912 }
5913
5914 /**
5915 * @brief Hall Trigger detection half complete callback in non-blocking mode
5916 * @param htim TIM handle
5917 * @retval None
5918 */
HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef * htim)5919 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
5920 {
5921 /* Prevent unused argument(s) compilation warning */
5922 UNUSED(htim);
5923
5924 /* NOTE : This function should not be modified, when the callback is needed,
5925 the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
5926 */
5927 }
5928
5929 /**
5930 * @brief Timer error callback in non-blocking mode
5931 * @param htim TIM handle
5932 * @retval None
5933 */
HAL_TIM_ErrorCallback(TIM_HandleTypeDef * htim)5934 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
5935 {
5936 /* Prevent unused argument(s) compilation warning */
5937 UNUSED(htim);
5938
5939 /* NOTE : This function should not be modified, when the callback is needed,
5940 the HAL_TIM_ErrorCallback could be implemented in the user file
5941 */
5942 }
5943
5944 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5945 /**
5946 * @brief Register a User TIM callback to be used instead of the weak predefined callback
5947 * @param htim tim handle
5948 * @param CallbackID ID of the callback to be registered
5949 * This parameter can be one of the following values:
5950 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
5951 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
5952 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
5953 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
5954 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
5955 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
5956 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
5957 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
5958 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
5959 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
5960 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
5961 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
5962 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
5963 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
5964 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
5965 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
5966 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
5967 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
5968 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
5969 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
5970 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
5971 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
5972 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
5973 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
5974 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
5975 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
5976 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
5977 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
5978 * @param pCallback pointer to the callback function
5979 * @retval status
5980 */
HAL_TIM_RegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID,pTIM_CallbackTypeDef pCallback)5981 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
5982 pTIM_CallbackTypeDef pCallback)
5983 {
5984 HAL_StatusTypeDef status = HAL_OK;
5985
5986 if (pCallback == NULL)
5987 {
5988 return HAL_ERROR;
5989 }
5990
5991 if (htim->State == HAL_TIM_STATE_READY)
5992 {
5993 switch (CallbackID)
5994 {
5995 case HAL_TIM_BASE_MSPINIT_CB_ID :
5996 htim->Base_MspInitCallback = pCallback;
5997 break;
5998
5999 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6000 htim->Base_MspDeInitCallback = pCallback;
6001 break;
6002
6003 case HAL_TIM_IC_MSPINIT_CB_ID :
6004 htim->IC_MspInitCallback = pCallback;
6005 break;
6006
6007 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6008 htim->IC_MspDeInitCallback = pCallback;
6009 break;
6010
6011 case HAL_TIM_OC_MSPINIT_CB_ID :
6012 htim->OC_MspInitCallback = pCallback;
6013 break;
6014
6015 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6016 htim->OC_MspDeInitCallback = pCallback;
6017 break;
6018
6019 case HAL_TIM_PWM_MSPINIT_CB_ID :
6020 htim->PWM_MspInitCallback = pCallback;
6021 break;
6022
6023 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6024 htim->PWM_MspDeInitCallback = pCallback;
6025 break;
6026
6027 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6028 htim->OnePulse_MspInitCallback = pCallback;
6029 break;
6030
6031 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6032 htim->OnePulse_MspDeInitCallback = pCallback;
6033 break;
6034
6035 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6036 htim->Encoder_MspInitCallback = pCallback;
6037 break;
6038
6039 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6040 htim->Encoder_MspDeInitCallback = pCallback;
6041 break;
6042
6043 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6044 htim->HallSensor_MspInitCallback = pCallback;
6045 break;
6046
6047 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6048 htim->HallSensor_MspDeInitCallback = pCallback;
6049 break;
6050
6051 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
6052 htim->PeriodElapsedCallback = pCallback;
6053 break;
6054
6055 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
6056 htim->PeriodElapsedHalfCpltCallback = pCallback;
6057 break;
6058
6059 case HAL_TIM_TRIGGER_CB_ID :
6060 htim->TriggerCallback = pCallback;
6061 break;
6062
6063 case HAL_TIM_TRIGGER_HALF_CB_ID :
6064 htim->TriggerHalfCpltCallback = pCallback;
6065 break;
6066
6067 case HAL_TIM_IC_CAPTURE_CB_ID :
6068 htim->IC_CaptureCallback = pCallback;
6069 break;
6070
6071 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
6072 htim->IC_CaptureHalfCpltCallback = pCallback;
6073 break;
6074
6075 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
6076 htim->OC_DelayElapsedCallback = pCallback;
6077 break;
6078
6079 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
6080 htim->PWM_PulseFinishedCallback = pCallback;
6081 break;
6082
6083 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
6084 htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
6085 break;
6086
6087 case HAL_TIM_ERROR_CB_ID :
6088 htim->ErrorCallback = pCallback;
6089 break;
6090
6091 case HAL_TIM_COMMUTATION_CB_ID :
6092 htim->CommutationCallback = pCallback;
6093 break;
6094
6095 case HAL_TIM_COMMUTATION_HALF_CB_ID :
6096 htim->CommutationHalfCpltCallback = pCallback;
6097 break;
6098
6099 case HAL_TIM_BREAK_CB_ID :
6100 htim->BreakCallback = pCallback;
6101 break;
6102
6103 case HAL_TIM_BREAK2_CB_ID :
6104 htim->Break2Callback = pCallback;
6105 break;
6106
6107 default :
6108 /* Return error status */
6109 status = HAL_ERROR;
6110 break;
6111 }
6112 }
6113 else if (htim->State == HAL_TIM_STATE_RESET)
6114 {
6115 switch (CallbackID)
6116 {
6117 case HAL_TIM_BASE_MSPINIT_CB_ID :
6118 htim->Base_MspInitCallback = pCallback;
6119 break;
6120
6121 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6122 htim->Base_MspDeInitCallback = pCallback;
6123 break;
6124
6125 case HAL_TIM_IC_MSPINIT_CB_ID :
6126 htim->IC_MspInitCallback = pCallback;
6127 break;
6128
6129 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6130 htim->IC_MspDeInitCallback = pCallback;
6131 break;
6132
6133 case HAL_TIM_OC_MSPINIT_CB_ID :
6134 htim->OC_MspInitCallback = pCallback;
6135 break;
6136
6137 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6138 htim->OC_MspDeInitCallback = pCallback;
6139 break;
6140
6141 case HAL_TIM_PWM_MSPINIT_CB_ID :
6142 htim->PWM_MspInitCallback = pCallback;
6143 break;
6144
6145 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6146 htim->PWM_MspDeInitCallback = pCallback;
6147 break;
6148
6149 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6150 htim->OnePulse_MspInitCallback = pCallback;
6151 break;
6152
6153 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6154 htim->OnePulse_MspDeInitCallback = pCallback;
6155 break;
6156
6157 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6158 htim->Encoder_MspInitCallback = pCallback;
6159 break;
6160
6161 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6162 htim->Encoder_MspDeInitCallback = pCallback;
6163 break;
6164
6165 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6166 htim->HallSensor_MspInitCallback = pCallback;
6167 break;
6168
6169 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6170 htim->HallSensor_MspDeInitCallback = pCallback;
6171 break;
6172
6173 default :
6174 /* Return error status */
6175 status = HAL_ERROR;
6176 break;
6177 }
6178 }
6179 else
6180 {
6181 /* Return error status */
6182 status = HAL_ERROR;
6183 }
6184
6185 return status;
6186 }
6187
6188 /**
6189 * @brief Unregister a TIM callback
6190 * TIM callback is redirected to the weak predefined callback
6191 * @param htim tim handle
6192 * @param CallbackID ID of the callback to be unregistered
6193 * This parameter can be one of the following values:
6194 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
6195 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
6196 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
6197 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
6198 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
6199 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
6200 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
6201 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
6202 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
6203 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
6204 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
6205 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
6206 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
6207 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
6208 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
6209 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
6210 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
6211 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
6212 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
6213 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
6214 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
6215 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
6216 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
6217 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
6218 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
6219 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
6220 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
6221 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
6222 * @retval status
6223 */
HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID)6224 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
6225 {
6226 HAL_StatusTypeDef status = HAL_OK;
6227
6228 if (htim->State == HAL_TIM_STATE_READY)
6229 {
6230 switch (CallbackID)
6231 {
6232 case HAL_TIM_BASE_MSPINIT_CB_ID :
6233 /* Legacy weak Base MspInit Callback */
6234 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
6235 break;
6236
6237 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6238 /* Legacy weak Base Msp DeInit Callback */
6239 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
6240 break;
6241
6242 case HAL_TIM_IC_MSPINIT_CB_ID :
6243 /* Legacy weak IC Msp Init Callback */
6244 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
6245 break;
6246
6247 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6248 /* Legacy weak IC Msp DeInit Callback */
6249 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
6250 break;
6251
6252 case HAL_TIM_OC_MSPINIT_CB_ID :
6253 /* Legacy weak OC Msp Init Callback */
6254 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
6255 break;
6256
6257 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6258 /* Legacy weak OC Msp DeInit Callback */
6259 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
6260 break;
6261
6262 case HAL_TIM_PWM_MSPINIT_CB_ID :
6263 /* Legacy weak PWM Msp Init Callback */
6264 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
6265 break;
6266
6267 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6268 /* Legacy weak PWM Msp DeInit Callback */
6269 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
6270 break;
6271
6272 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6273 /* Legacy weak One Pulse Msp Init Callback */
6274 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
6275 break;
6276
6277 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6278 /* Legacy weak One Pulse Msp DeInit Callback */
6279 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
6280 break;
6281
6282 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6283 /* Legacy weak Encoder Msp Init Callback */
6284 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
6285 break;
6286
6287 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6288 /* Legacy weak Encoder Msp DeInit Callback */
6289 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
6290 break;
6291
6292 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6293 /* Legacy weak Hall Sensor Msp Init Callback */
6294 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
6295 break;
6296
6297 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6298 /* Legacy weak Hall Sensor Msp DeInit Callback */
6299 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
6300 break;
6301
6302 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
6303 /* Legacy weak Period Elapsed Callback */
6304 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
6305 break;
6306
6307 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
6308 /* Legacy weak Period Elapsed half complete Callback */
6309 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
6310 break;
6311
6312 case HAL_TIM_TRIGGER_CB_ID :
6313 /* Legacy weak Trigger Callback */
6314 htim->TriggerCallback = HAL_TIM_TriggerCallback;
6315 break;
6316
6317 case HAL_TIM_TRIGGER_HALF_CB_ID :
6318 /* Legacy weak Trigger half complete Callback */
6319 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
6320 break;
6321
6322 case HAL_TIM_IC_CAPTURE_CB_ID :
6323 /* Legacy weak IC Capture Callback */
6324 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
6325 break;
6326
6327 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
6328 /* Legacy weak IC Capture half complete Callback */
6329 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
6330 break;
6331
6332 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
6333 /* Legacy weak OC Delay Elapsed Callback */
6334 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
6335 break;
6336
6337 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
6338 /* Legacy weak PWM Pulse Finished Callback */
6339 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
6340 break;
6341
6342 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
6343 /* Legacy weak PWM Pulse Finished half complete Callback */
6344 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
6345 break;
6346
6347 case HAL_TIM_ERROR_CB_ID :
6348 /* Legacy weak Error Callback */
6349 htim->ErrorCallback = HAL_TIM_ErrorCallback;
6350 break;
6351
6352 case HAL_TIM_COMMUTATION_CB_ID :
6353 /* Legacy weak Commutation Callback */
6354 htim->CommutationCallback = HAL_TIMEx_CommutCallback;
6355 break;
6356
6357 case HAL_TIM_COMMUTATION_HALF_CB_ID :
6358 /* Legacy weak Commutation half complete Callback */
6359 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
6360 break;
6361
6362 case HAL_TIM_BREAK_CB_ID :
6363 /* Legacy weak Break Callback */
6364 htim->BreakCallback = HAL_TIMEx_BreakCallback;
6365 break;
6366
6367 case HAL_TIM_BREAK2_CB_ID :
6368 /* Legacy weak Break2 Callback */
6369 htim->Break2Callback = HAL_TIMEx_Break2Callback;
6370 break;
6371
6372 default :
6373 /* Return error status */
6374 status = HAL_ERROR;
6375 break;
6376 }
6377 }
6378 else if (htim->State == HAL_TIM_STATE_RESET)
6379 {
6380 switch (CallbackID)
6381 {
6382 case HAL_TIM_BASE_MSPINIT_CB_ID :
6383 /* Legacy weak Base MspInit Callback */
6384 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
6385 break;
6386
6387 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6388 /* Legacy weak Base Msp DeInit Callback */
6389 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
6390 break;
6391
6392 case HAL_TIM_IC_MSPINIT_CB_ID :
6393 /* Legacy weak IC Msp Init Callback */
6394 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
6395 break;
6396
6397 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6398 /* Legacy weak IC Msp DeInit Callback */
6399 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
6400 break;
6401
6402 case HAL_TIM_OC_MSPINIT_CB_ID :
6403 /* Legacy weak OC Msp Init Callback */
6404 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
6405 break;
6406
6407 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6408 /* Legacy weak OC Msp DeInit Callback */
6409 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
6410 break;
6411
6412 case HAL_TIM_PWM_MSPINIT_CB_ID :
6413 /* Legacy weak PWM Msp Init Callback */
6414 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
6415 break;
6416
6417 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6418 /* Legacy weak PWM Msp DeInit Callback */
6419 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
6420 break;
6421
6422 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6423 /* Legacy weak One Pulse Msp Init Callback */
6424 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
6425 break;
6426
6427 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6428 /* Legacy weak One Pulse Msp DeInit Callback */
6429 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
6430 break;
6431
6432 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6433 /* Legacy weak Encoder Msp Init Callback */
6434 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
6435 break;
6436
6437 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6438 /* Legacy weak Encoder Msp DeInit Callback */
6439 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
6440 break;
6441
6442 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6443 /* Legacy weak Hall Sensor Msp Init Callback */
6444 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
6445 break;
6446
6447 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6448 /* Legacy weak Hall Sensor Msp DeInit Callback */
6449 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
6450 break;
6451
6452 default :
6453 /* Return error status */
6454 status = HAL_ERROR;
6455 break;
6456 }
6457 }
6458 else
6459 {
6460 /* Return error status */
6461 status = HAL_ERROR;
6462 }
6463
6464 return status;
6465 }
6466 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6467
6468 /**
6469 * @}
6470 */
6471
6472 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
6473 * @brief TIM Peripheral State functions
6474 *
6475 @verbatim
6476 ==============================================================================
6477 ##### Peripheral State functions #####
6478 ==============================================================================
6479 [..]
6480 This subsection permits to get in run-time the status of the peripheral
6481 and the data flow.
6482
6483 @endverbatim
6484 * @{
6485 */
6486
6487 /**
6488 * @brief Return the TIM Base handle state.
6489 * @param htim TIM Base handle
6490 * @retval HAL state
6491 */
HAL_TIM_Base_GetState(const TIM_HandleTypeDef * htim)6492 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim)
6493 {
6494 return htim->State;
6495 }
6496
6497 /**
6498 * @brief Return the TIM OC handle state.
6499 * @param htim TIM Output Compare handle
6500 * @retval HAL state
6501 */
HAL_TIM_OC_GetState(const TIM_HandleTypeDef * htim)6502 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim)
6503 {
6504 return htim->State;
6505 }
6506
6507 /**
6508 * @brief Return the TIM PWM handle state.
6509 * @param htim TIM handle
6510 * @retval HAL state
6511 */
HAL_TIM_PWM_GetState(const TIM_HandleTypeDef * htim)6512 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim)
6513 {
6514 return htim->State;
6515 }
6516
6517 /**
6518 * @brief Return the TIM Input Capture handle state.
6519 * @param htim TIM IC handle
6520 * @retval HAL state
6521 */
HAL_TIM_IC_GetState(const TIM_HandleTypeDef * htim)6522 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim)
6523 {
6524 return htim->State;
6525 }
6526
6527 /**
6528 * @brief Return the TIM One Pulse Mode handle state.
6529 * @param htim TIM OPM handle
6530 * @retval HAL state
6531 */
HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef * htim)6532 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim)
6533 {
6534 return htim->State;
6535 }
6536
6537 /**
6538 * @brief Return the TIM Encoder Mode handle state.
6539 * @param htim TIM Encoder Interface handle
6540 * @retval HAL state
6541 */
HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef * htim)6542 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim)
6543 {
6544 return htim->State;
6545 }
6546
6547 /**
6548 * @brief Return the TIM Encoder Mode handle state.
6549 * @param htim TIM handle
6550 * @retval Active channel
6551 */
HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef * htim)6552 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim)
6553 {
6554 return htim->Channel;
6555 }
6556
6557 /**
6558 * @brief Return actual state of the TIM channel.
6559 * @param htim TIM handle
6560 * @param Channel TIM Channel
6561 * This parameter can be one of the following values:
6562 * @arg TIM_CHANNEL_1: TIM Channel 1
6563 * @arg TIM_CHANNEL_2: TIM Channel 2
6564 * @arg TIM_CHANNEL_3: TIM Channel 3
6565 * @arg TIM_CHANNEL_4: TIM Channel 4
6566 * @arg TIM_CHANNEL_5: TIM Channel 5
6567 * @arg TIM_CHANNEL_6: TIM Channel 6
6568 * @retval TIM Channel state
6569 */
HAL_TIM_GetChannelState(const TIM_HandleTypeDef * htim,uint32_t Channel)6570 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel)
6571 {
6572 HAL_TIM_ChannelStateTypeDef channel_state;
6573
6574 /* Check the parameters */
6575 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
6576
6577 channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
6578
6579 return channel_state;
6580 }
6581
6582 /**
6583 * @brief Return actual state of a DMA burst operation.
6584 * @param htim TIM handle
6585 * @retval DMA burst state
6586 */
HAL_TIM_DMABurstState(const TIM_HandleTypeDef * htim)6587 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim)
6588 {
6589 /* Check the parameters */
6590 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
6591
6592 return htim->DMABurstState;
6593 }
6594
6595 /**
6596 * @}
6597 */
6598
6599 /**
6600 * @}
6601 */
6602
6603 /** @defgroup TIM_Private_Functions TIM Private Functions
6604 * @{
6605 */
6606
6607 /**
6608 * @brief TIM DMA error callback
6609 * @param hdma pointer to DMA handle.
6610 * @retval None
6611 */
TIM_DMAError(DMA_HandleTypeDef * hdma)6612 void TIM_DMAError(DMA_HandleTypeDef *hdma)
6613 {
6614 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6615
6616 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6617 {
6618 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6619 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6620 }
6621 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6622 {
6623 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6624 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6625 }
6626 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6627 {
6628 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6629 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6630 }
6631 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6632 {
6633 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6634 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6635 }
6636 else
6637 {
6638 htim->State = HAL_TIM_STATE_READY;
6639 }
6640
6641 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6642 htim->ErrorCallback(htim);
6643 #else
6644 HAL_TIM_ErrorCallback(htim);
6645 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6646
6647 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6648 }
6649
6650 /**
6651 * @brief TIM DMA Delay Pulse complete callback.
6652 * @param hdma pointer to DMA handle.
6653 * @retval None
6654 */
TIM_DMADelayPulseCplt(DMA_HandleTypeDef * hdma)6655 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
6656 {
6657 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6658
6659 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6660 {
6661 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6662
6663 if (hdma->Init.Mode == DMA_NORMAL)
6664 {
6665 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6666 }
6667 }
6668 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6669 {
6670 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6671
6672 if (hdma->Init.Mode == DMA_NORMAL)
6673 {
6674 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6675 }
6676 }
6677 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6678 {
6679 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6680
6681 if (hdma->Init.Mode == DMA_NORMAL)
6682 {
6683 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6684 }
6685 }
6686 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6687 {
6688 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6689
6690 if (hdma->Init.Mode == DMA_NORMAL)
6691 {
6692 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6693 }
6694 }
6695 else
6696 {
6697 /* nothing to do */
6698 }
6699
6700 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6701 htim->PWM_PulseFinishedCallback(htim);
6702 #else
6703 HAL_TIM_PWM_PulseFinishedCallback(htim);
6704 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6705
6706 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6707 }
6708
6709 /**
6710 * @brief TIM DMA Delay Pulse half complete callback.
6711 * @param hdma pointer to DMA handle.
6712 * @retval None
6713 */
TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef * hdma)6714 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
6715 {
6716 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6717
6718 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6719 {
6720 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6721 }
6722 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6723 {
6724 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6725 }
6726 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6727 {
6728 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6729 }
6730 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6731 {
6732 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6733 }
6734 else
6735 {
6736 /* nothing to do */
6737 }
6738
6739 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6740 htim->PWM_PulseFinishedHalfCpltCallback(htim);
6741 #else
6742 HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
6743 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6744
6745 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6746 }
6747
6748 /**
6749 * @brief TIM DMA Capture complete callback.
6750 * @param hdma pointer to DMA handle.
6751 * @retval None
6752 */
TIM_DMACaptureCplt(DMA_HandleTypeDef * hdma)6753 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
6754 {
6755 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6756
6757 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6758 {
6759 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6760
6761 if (hdma->Init.Mode == DMA_NORMAL)
6762 {
6763 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6764 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6765 }
6766 }
6767 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6768 {
6769 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6770
6771 if (hdma->Init.Mode == DMA_NORMAL)
6772 {
6773 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6774 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6775 }
6776 }
6777 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6778 {
6779 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6780
6781 if (hdma->Init.Mode == DMA_NORMAL)
6782 {
6783 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6784 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6785 }
6786 }
6787 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6788 {
6789 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6790
6791 if (hdma->Init.Mode == DMA_NORMAL)
6792 {
6793 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6794 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6795 }
6796 }
6797 else
6798 {
6799 /* nothing to do */
6800 }
6801
6802 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6803 htim->IC_CaptureCallback(htim);
6804 #else
6805 HAL_TIM_IC_CaptureCallback(htim);
6806 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6807
6808 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6809 }
6810
6811 /**
6812 * @brief TIM DMA Capture half complete callback.
6813 * @param hdma pointer to DMA handle.
6814 * @retval None
6815 */
TIM_DMACaptureHalfCplt(DMA_HandleTypeDef * hdma)6816 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
6817 {
6818 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6819
6820 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6821 {
6822 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6823 }
6824 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6825 {
6826 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6827 }
6828 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6829 {
6830 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6831 }
6832 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6833 {
6834 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6835 }
6836 else
6837 {
6838 /* nothing to do */
6839 }
6840
6841 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6842 htim->IC_CaptureHalfCpltCallback(htim);
6843 #else
6844 HAL_TIM_IC_CaptureHalfCpltCallback(htim);
6845 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6846
6847 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6848 }
6849
6850 /**
6851 * @brief TIM DMA Period Elapse complete callback.
6852 * @param hdma pointer to DMA handle.
6853 * @retval None
6854 */
TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef * hdma)6855 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
6856 {
6857 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6858
6859 if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
6860 {
6861 htim->State = HAL_TIM_STATE_READY;
6862 }
6863
6864 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6865 htim->PeriodElapsedCallback(htim);
6866 #else
6867 HAL_TIM_PeriodElapsedCallback(htim);
6868 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6869 }
6870
6871 /**
6872 * @brief TIM DMA Period Elapse half complete callback.
6873 * @param hdma pointer to DMA handle.
6874 * @retval None
6875 */
TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef * hdma)6876 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
6877 {
6878 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6879
6880 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6881 htim->PeriodElapsedHalfCpltCallback(htim);
6882 #else
6883 HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
6884 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6885 }
6886
6887 /**
6888 * @brief TIM DMA Trigger callback.
6889 * @param hdma pointer to DMA handle.
6890 * @retval None
6891 */
TIM_DMATriggerCplt(DMA_HandleTypeDef * hdma)6892 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
6893 {
6894 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6895
6896 if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
6897 {
6898 htim->State = HAL_TIM_STATE_READY;
6899 }
6900
6901 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6902 htim->TriggerCallback(htim);
6903 #else
6904 HAL_TIM_TriggerCallback(htim);
6905 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6906 }
6907
6908 /**
6909 * @brief TIM DMA Trigger half complete callback.
6910 * @param hdma pointer to DMA handle.
6911 * @retval None
6912 */
TIM_DMATriggerHalfCplt(DMA_HandleTypeDef * hdma)6913 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
6914 {
6915 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6916
6917 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6918 htim->TriggerHalfCpltCallback(htim);
6919 #else
6920 HAL_TIM_TriggerHalfCpltCallback(htim);
6921 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6922 }
6923
6924 /**
6925 * @brief Time Base configuration
6926 * @param TIMx TIM peripheral
6927 * @param Structure TIM Base configuration structure
6928 * @retval None
6929 */
TIM_Base_SetConfig(TIM_TypeDef * TIMx,const TIM_Base_InitTypeDef * Structure)6930 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
6931 {
6932 uint32_t tmpcr1;
6933 tmpcr1 = TIMx->CR1;
6934
6935 /* Set TIM Time Base Unit parameters ---------------------------------------*/
6936 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
6937 {
6938 /* Select the Counter Mode */
6939 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
6940 tmpcr1 |= Structure->CounterMode;
6941 }
6942
6943 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
6944 {
6945 /* Set the clock division */
6946 tmpcr1 &= ~TIM_CR1_CKD;
6947 tmpcr1 |= (uint32_t)Structure->ClockDivision;
6948 }
6949
6950 /* Set the auto-reload preload */
6951 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
6952
6953 TIMx->CR1 = tmpcr1;
6954
6955 /* Set the Autoreload value */
6956 TIMx->ARR = (uint32_t)Structure->Period ;
6957
6958 /* Set the Prescaler value */
6959 TIMx->PSC = Structure->Prescaler;
6960
6961 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
6962 {
6963 /* Set the Repetition Counter value */
6964 TIMx->RCR = Structure->RepetitionCounter;
6965 }
6966
6967 /* Generate an update event to reload the Prescaler
6968 and the repetition counter (only for advanced timer) value immediately */
6969 TIMx->EGR = TIM_EGR_UG;
6970
6971 /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
6972 if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
6973 {
6974 /* Clear the update flag */
6975 CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
6976 }
6977 }
6978
6979 /**
6980 * @brief Timer Output Compare 1 configuration
6981 * @param TIMx to select the TIM peripheral
6982 * @param OC_Config The output configuration structure
6983 * @retval None
6984 */
TIM_OC1_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)6985 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
6986 {
6987 uint32_t tmpccmrx;
6988 uint32_t tmpccer;
6989 uint32_t tmpcr2;
6990
6991 /* Get the TIMx CCER register value */
6992 tmpccer = TIMx->CCER;
6993
6994 /* Disable the Channel 1: Reset the CC1E Bit */
6995 TIMx->CCER &= ~TIM_CCER_CC1E;
6996
6997 /* Get the TIMx CR2 register value */
6998 tmpcr2 = TIMx->CR2;
6999
7000 /* Get the TIMx CCMR1 register value */
7001 tmpccmrx = TIMx->CCMR1;
7002
7003 /* Reset the Output Compare Mode Bits */
7004 tmpccmrx &= ~TIM_CCMR1_OC1M;
7005 tmpccmrx &= ~TIM_CCMR1_CC1S;
7006 /* Select the Output Compare Mode */
7007 tmpccmrx |= OC_Config->OCMode;
7008
7009 /* Reset the Output Polarity level */
7010 tmpccer &= ~TIM_CCER_CC1P;
7011 /* Set the Output Compare Polarity */
7012 tmpccer |= OC_Config->OCPolarity;
7013
7014 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
7015 {
7016 /* Check parameters */
7017 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7018
7019 /* Reset the Output N Polarity level */
7020 tmpccer &= ~TIM_CCER_CC1NP;
7021 /* Set the Output N Polarity */
7022 tmpccer |= OC_Config->OCNPolarity;
7023 /* Reset the Output N State */
7024 tmpccer &= ~TIM_CCER_CC1NE;
7025 }
7026
7027 if (IS_TIM_BREAK_INSTANCE(TIMx))
7028 {
7029 /* Check parameters */
7030 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7031 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7032
7033 /* Reset the Output Compare and Output Compare N IDLE State */
7034 tmpcr2 &= ~TIM_CR2_OIS1;
7035 tmpcr2 &= ~TIM_CR2_OIS1N;
7036 /* Set the Output Idle state */
7037 tmpcr2 |= OC_Config->OCIdleState;
7038 /* Set the Output N Idle state */
7039 tmpcr2 |= OC_Config->OCNIdleState;
7040 }
7041
7042 /* Write to TIMx CR2 */
7043 TIMx->CR2 = tmpcr2;
7044
7045 /* Write to TIMx CCMR1 */
7046 TIMx->CCMR1 = tmpccmrx;
7047
7048 /* Set the Capture Compare Register value */
7049 TIMx->CCR1 = OC_Config->Pulse;
7050
7051 /* Write to TIMx CCER */
7052 TIMx->CCER = tmpccer;
7053 }
7054
7055 /**
7056 * @brief Timer Output Compare 2 configuration
7057 * @param TIMx to select the TIM peripheral
7058 * @param OC_Config The output configuration structure
7059 * @retval None
7060 */
TIM_OC2_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7061 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7062 {
7063 uint32_t tmpccmrx;
7064 uint32_t tmpccer;
7065 uint32_t tmpcr2;
7066
7067 /* Get the TIMx CCER register value */
7068 tmpccer = TIMx->CCER;
7069
7070 /* Disable the Channel 2: Reset the CC2E Bit */
7071 TIMx->CCER &= ~TIM_CCER_CC2E;
7072
7073 /* Get the TIMx CR2 register value */
7074 tmpcr2 = TIMx->CR2;
7075
7076 /* Get the TIMx CCMR1 register value */
7077 tmpccmrx = TIMx->CCMR1;
7078
7079 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7080 tmpccmrx &= ~TIM_CCMR1_OC2M;
7081 tmpccmrx &= ~TIM_CCMR1_CC2S;
7082
7083 /* Select the Output Compare Mode */
7084 tmpccmrx |= (OC_Config->OCMode << 8U);
7085
7086 /* Reset the Output Polarity level */
7087 tmpccer &= ~TIM_CCER_CC2P;
7088 /* Set the Output Compare Polarity */
7089 tmpccer |= (OC_Config->OCPolarity << 4U);
7090
7091 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
7092 {
7093 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7094
7095 /* Reset the Output N Polarity level */
7096 tmpccer &= ~TIM_CCER_CC2NP;
7097 /* Set the Output N Polarity */
7098 tmpccer |= (OC_Config->OCNPolarity << 4U);
7099 /* Reset the Output N State */
7100 tmpccer &= ~TIM_CCER_CC2NE;
7101 }
7102
7103 if (IS_TIM_BREAK_INSTANCE(TIMx))
7104 {
7105 /* Check parameters */
7106 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7107 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7108
7109 /* Reset the Output Compare and Output Compare N IDLE State */
7110 tmpcr2 &= ~TIM_CR2_OIS2;
7111 tmpcr2 &= ~TIM_CR2_OIS2N;
7112 /* Set the Output Idle state */
7113 tmpcr2 |= (OC_Config->OCIdleState << 2U);
7114 /* Set the Output N Idle state */
7115 tmpcr2 |= (OC_Config->OCNIdleState << 2U);
7116 }
7117
7118 /* Write to TIMx CR2 */
7119 TIMx->CR2 = tmpcr2;
7120
7121 /* Write to TIMx CCMR1 */
7122 TIMx->CCMR1 = tmpccmrx;
7123
7124 /* Set the Capture Compare Register value */
7125 TIMx->CCR2 = OC_Config->Pulse;
7126
7127 /* Write to TIMx CCER */
7128 TIMx->CCER = tmpccer;
7129 }
7130
7131 /**
7132 * @brief Timer Output Compare 3 configuration
7133 * @param TIMx to select the TIM peripheral
7134 * @param OC_Config The output configuration structure
7135 * @retval None
7136 */
TIM_OC3_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7137 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7138 {
7139 uint32_t tmpccmrx;
7140 uint32_t tmpccer;
7141 uint32_t tmpcr2;
7142
7143 /* Get the TIMx CCER register value */
7144 tmpccer = TIMx->CCER;
7145
7146 /* Disable the Channel 3: Reset the CC2E Bit */
7147 TIMx->CCER &= ~TIM_CCER_CC3E;
7148
7149 /* Get the TIMx CR2 register value */
7150 tmpcr2 = TIMx->CR2;
7151
7152 /* Get the TIMx CCMR2 register value */
7153 tmpccmrx = TIMx->CCMR2;
7154
7155 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7156 tmpccmrx &= ~TIM_CCMR2_OC3M;
7157 tmpccmrx &= ~TIM_CCMR2_CC3S;
7158 /* Select the Output Compare Mode */
7159 tmpccmrx |= OC_Config->OCMode;
7160
7161 /* Reset the Output Polarity level */
7162 tmpccer &= ~TIM_CCER_CC3P;
7163 /* Set the Output Compare Polarity */
7164 tmpccer |= (OC_Config->OCPolarity << 8U);
7165
7166 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
7167 {
7168 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7169
7170 /* Reset the Output N Polarity level */
7171 tmpccer &= ~TIM_CCER_CC3NP;
7172 /* Set the Output N Polarity */
7173 tmpccer |= (OC_Config->OCNPolarity << 8U);
7174 /* Reset the Output N State */
7175 tmpccer &= ~TIM_CCER_CC3NE;
7176 }
7177
7178 if (IS_TIM_BREAK_INSTANCE(TIMx))
7179 {
7180 /* Check parameters */
7181 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7182 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7183
7184 /* Reset the Output Compare and Output Compare N IDLE State */
7185 tmpcr2 &= ~TIM_CR2_OIS3;
7186 tmpcr2 &= ~TIM_CR2_OIS3N;
7187 /* Set the Output Idle state */
7188 tmpcr2 |= (OC_Config->OCIdleState << 4U);
7189 /* Set the Output N Idle state */
7190 tmpcr2 |= (OC_Config->OCNIdleState << 4U);
7191 }
7192
7193 /* Write to TIMx CR2 */
7194 TIMx->CR2 = tmpcr2;
7195
7196 /* Write to TIMx CCMR2 */
7197 TIMx->CCMR2 = tmpccmrx;
7198
7199 /* Set the Capture Compare Register value */
7200 TIMx->CCR3 = OC_Config->Pulse;
7201
7202 /* Write to TIMx CCER */
7203 TIMx->CCER = tmpccer;
7204 }
7205
7206 /**
7207 * @brief Timer Output Compare 4 configuration
7208 * @param TIMx to select the TIM peripheral
7209 * @param OC_Config The output configuration structure
7210 * @retval None
7211 */
TIM_OC4_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7212 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7213 {
7214 uint32_t tmpccmrx;
7215 uint32_t tmpccer;
7216 uint32_t tmpcr2;
7217
7218 /* Get the TIMx CCER register value */
7219 tmpccer = TIMx->CCER;
7220
7221 /* Disable the Channel 4: Reset the CC4E Bit */
7222 TIMx->CCER &= ~TIM_CCER_CC4E;
7223
7224 /* Get the TIMx CR2 register value */
7225 tmpcr2 = TIMx->CR2;
7226
7227 /* Get the TIMx CCMR2 register value */
7228 tmpccmrx = TIMx->CCMR2;
7229
7230 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7231 tmpccmrx &= ~TIM_CCMR2_OC4M;
7232 tmpccmrx &= ~TIM_CCMR2_CC4S;
7233
7234 /* Select the Output Compare Mode */
7235 tmpccmrx |= (OC_Config->OCMode << 8U);
7236
7237 /* Reset the Output Polarity level */
7238 tmpccer &= ~TIM_CCER_CC4P;
7239 /* Set the Output Compare Polarity */
7240 tmpccer |= (OC_Config->OCPolarity << 12U);
7241
7242 if (IS_TIM_BREAK_INSTANCE(TIMx))
7243 {
7244 /* Check parameters */
7245 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7246
7247 /* Reset the Output Compare IDLE State */
7248 tmpcr2 &= ~TIM_CR2_OIS4;
7249
7250 /* Set the Output Idle state */
7251 tmpcr2 |= (OC_Config->OCIdleState << 6U);
7252 }
7253
7254 /* Write to TIMx CR2 */
7255 TIMx->CR2 = tmpcr2;
7256
7257 /* Write to TIMx CCMR2 */
7258 TIMx->CCMR2 = tmpccmrx;
7259
7260 /* Set the Capture Compare Register value */
7261 TIMx->CCR4 = OC_Config->Pulse;
7262
7263 /* Write to TIMx CCER */
7264 TIMx->CCER = tmpccer;
7265 }
7266
7267 /**
7268 * @brief Timer Output Compare 5 configuration
7269 * @param TIMx to select the TIM peripheral
7270 * @param OC_Config The output configuration structure
7271 * @retval None
7272 */
TIM_OC5_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7273 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
7274 const TIM_OC_InitTypeDef *OC_Config)
7275 {
7276 uint32_t tmpccmrx;
7277 uint32_t tmpccer;
7278 uint32_t tmpcr2;
7279
7280 /* Get the TIMx CCER register value */
7281 tmpccer = TIMx->CCER;
7282
7283 /* Disable the output: Reset the CCxE Bit */
7284 TIMx->CCER &= ~TIM_CCER_CC5E;
7285
7286 /* Get the TIMx CR2 register value */
7287 tmpcr2 = TIMx->CR2;
7288 /* Get the TIMx CCMR1 register value */
7289 tmpccmrx = TIMx->CCMR3;
7290
7291 /* Reset the Output Compare Mode Bits */
7292 tmpccmrx &= ~(TIM_CCMR3_OC5M);
7293 /* Select the Output Compare Mode */
7294 tmpccmrx |= OC_Config->OCMode;
7295
7296 /* Reset the Output Polarity level */
7297 tmpccer &= ~TIM_CCER_CC5P;
7298 /* Set the Output Compare Polarity */
7299 tmpccer |= (OC_Config->OCPolarity << 16U);
7300
7301 if (IS_TIM_BREAK_INSTANCE(TIMx))
7302 {
7303 /* Reset the Output Compare IDLE State */
7304 tmpcr2 &= ~TIM_CR2_OIS5;
7305 /* Set the Output Idle state */
7306 tmpcr2 |= (OC_Config->OCIdleState << 8U);
7307 }
7308 /* Write to TIMx CR2 */
7309 TIMx->CR2 = tmpcr2;
7310
7311 /* Write to TIMx CCMR3 */
7312 TIMx->CCMR3 = tmpccmrx;
7313
7314 /* Set the Capture Compare Register value */
7315 TIMx->CCR5 = OC_Config->Pulse;
7316
7317 /* Write to TIMx CCER */
7318 TIMx->CCER = tmpccer;
7319 }
7320
7321 /**
7322 * @brief Timer Output Compare 6 configuration
7323 * @param TIMx to select the TIM peripheral
7324 * @param OC_Config The output configuration structure
7325 * @retval None
7326 */
TIM_OC6_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7327 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
7328 const TIM_OC_InitTypeDef *OC_Config)
7329 {
7330 uint32_t tmpccmrx;
7331 uint32_t tmpccer;
7332 uint32_t tmpcr2;
7333
7334 /* Get the TIMx CCER register value */
7335 tmpccer = TIMx->CCER;
7336
7337 /* Disable the output: Reset the CCxE Bit */
7338 TIMx->CCER &= ~TIM_CCER_CC6E;
7339
7340 /* Get the TIMx CR2 register value */
7341 tmpcr2 = TIMx->CR2;
7342 /* Get the TIMx CCMR1 register value */
7343 tmpccmrx = TIMx->CCMR3;
7344
7345 /* Reset the Output Compare Mode Bits */
7346 tmpccmrx &= ~(TIM_CCMR3_OC6M);
7347 /* Select the Output Compare Mode */
7348 tmpccmrx |= (OC_Config->OCMode << 8U);
7349
7350 /* Reset the Output Polarity level */
7351 tmpccer &= (uint32_t)~TIM_CCER_CC6P;
7352 /* Set the Output Compare Polarity */
7353 tmpccer |= (OC_Config->OCPolarity << 20U);
7354
7355 if (IS_TIM_BREAK_INSTANCE(TIMx))
7356 {
7357 /* Reset the Output Compare IDLE State */
7358 tmpcr2 &= ~TIM_CR2_OIS6;
7359 /* Set the Output Idle state */
7360 tmpcr2 |= (OC_Config->OCIdleState << 10U);
7361 }
7362
7363 /* Write to TIMx CR2 */
7364 TIMx->CR2 = tmpcr2;
7365
7366 /* Write to TIMx CCMR3 */
7367 TIMx->CCMR3 = tmpccmrx;
7368
7369 /* Set the Capture Compare Register value */
7370 TIMx->CCR6 = OC_Config->Pulse;
7371
7372 /* Write to TIMx CCER */
7373 TIMx->CCER = tmpccer;
7374 }
7375
7376 /**
7377 * @brief Slave Timer configuration function
7378 * @param htim TIM handle
7379 * @param sSlaveConfig Slave timer configuration
7380 * @retval None
7381 */
TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)7382 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
7383 const TIM_SlaveConfigTypeDef *sSlaveConfig)
7384 {
7385 HAL_StatusTypeDef status = HAL_OK;
7386 uint32_t tmpsmcr;
7387 uint32_t tmpccmr1;
7388 uint32_t tmpccer;
7389
7390 /* Get the TIMx SMCR register value */
7391 tmpsmcr = htim->Instance->SMCR;
7392
7393 /* Reset the Trigger Selection Bits */
7394 tmpsmcr &= ~TIM_SMCR_TS;
7395 /* Set the Input Trigger source */
7396 tmpsmcr |= sSlaveConfig->InputTrigger;
7397
7398 /* Reset the slave mode Bits */
7399 tmpsmcr &= ~TIM_SMCR_SMS;
7400 /* Set the slave mode */
7401 tmpsmcr |= sSlaveConfig->SlaveMode;
7402
7403 /* Write to TIMx SMCR */
7404 htim->Instance->SMCR = tmpsmcr;
7405
7406 /* Configure the trigger prescaler, filter, and polarity */
7407 switch (sSlaveConfig->InputTrigger)
7408 {
7409 case TIM_TS_ETRF:
7410 {
7411 /* Check the parameters */
7412 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
7413 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
7414 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7415 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7416 /* Configure the ETR Trigger source */
7417 TIM_ETR_SetConfig(htim->Instance,
7418 sSlaveConfig->TriggerPrescaler,
7419 sSlaveConfig->TriggerPolarity,
7420 sSlaveConfig->TriggerFilter);
7421 break;
7422 }
7423
7424 case TIM_TS_TI1F_ED:
7425 {
7426 /* Check the parameters */
7427 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7428 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7429
7430 if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
7431 {
7432 return HAL_ERROR;
7433 }
7434
7435 /* Disable the Channel 1: Reset the CC1E Bit */
7436 tmpccer = htim->Instance->CCER;
7437 htim->Instance->CCER &= ~TIM_CCER_CC1E;
7438 tmpccmr1 = htim->Instance->CCMR1;
7439
7440 /* Set the filter */
7441 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7442 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
7443
7444 /* Write to TIMx CCMR1 and CCER registers */
7445 htim->Instance->CCMR1 = tmpccmr1;
7446 htim->Instance->CCER = tmpccer;
7447 break;
7448 }
7449
7450 case TIM_TS_TI1FP1:
7451 {
7452 /* Check the parameters */
7453 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7454 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7455 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7456
7457 /* Configure TI1 Filter and Polarity */
7458 TIM_TI1_ConfigInputStage(htim->Instance,
7459 sSlaveConfig->TriggerPolarity,
7460 sSlaveConfig->TriggerFilter);
7461 break;
7462 }
7463
7464 case TIM_TS_TI2FP2:
7465 {
7466 /* Check the parameters */
7467 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
7468 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7469 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7470
7471 /* Configure TI2 Filter and Polarity */
7472 TIM_TI2_ConfigInputStage(htim->Instance,
7473 sSlaveConfig->TriggerPolarity,
7474 sSlaveConfig->TriggerFilter);
7475 break;
7476 }
7477
7478 case TIM_TS_ITR0:
7479 case TIM_TS_ITR1:
7480 case TIM_TS_ITR2:
7481 case TIM_TS_ITR3:
7482 {
7483 /* Check the parameter */
7484 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
7485 break;
7486 }
7487
7488 default:
7489 status = HAL_ERROR;
7490 break;
7491 }
7492
7493 return status;
7494 }
7495
7496 /**
7497 * @brief Configure the TI1 as Input.
7498 * @param TIMx to select the TIM peripheral.
7499 * @param TIM_ICPolarity The Input Polarity.
7500 * This parameter can be one of the following values:
7501 * @arg TIM_ICPOLARITY_RISING
7502 * @arg TIM_ICPOLARITY_FALLING
7503 * @arg TIM_ICPOLARITY_BOTHEDGE
7504 * @param TIM_ICSelection specifies the input to be used.
7505 * This parameter can be one of the following values:
7506 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
7507 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
7508 * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
7509 * @param TIM_ICFilter Specifies the Input Capture Filter.
7510 * This parameter must be a value between 0x00 and 0x0F.
7511 * @retval None
7512 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
7513 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
7514 * protected against un-initialized filter and polarity values.
7515 */
TIM_TI1_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7516 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7517 uint32_t TIM_ICFilter)
7518 {
7519 uint32_t tmpccmr1;
7520 uint32_t tmpccer;
7521
7522 /* Disable the Channel 1: Reset the CC1E Bit */
7523 tmpccer = TIMx->CCER;
7524 TIMx->CCER &= ~TIM_CCER_CC1E;
7525 tmpccmr1 = TIMx->CCMR1;
7526
7527 /* Select the Input */
7528 if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
7529 {
7530 tmpccmr1 &= ~TIM_CCMR1_CC1S;
7531 tmpccmr1 |= TIM_ICSelection;
7532 }
7533 else
7534 {
7535 tmpccmr1 |= TIM_CCMR1_CC1S_0;
7536 }
7537
7538 /* Set the filter */
7539 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7540 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
7541
7542 /* Select the Polarity and set the CC1E Bit */
7543 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7544 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
7545
7546 /* Write to TIMx CCMR1 and CCER registers */
7547 TIMx->CCMR1 = tmpccmr1;
7548 TIMx->CCER = tmpccer;
7549 }
7550
7551 /**
7552 * @brief Configure the Polarity and Filter for TI1.
7553 * @param TIMx to select the TIM peripheral.
7554 * @param TIM_ICPolarity The Input Polarity.
7555 * This parameter can be one of the following values:
7556 * @arg TIM_ICPOLARITY_RISING
7557 * @arg TIM_ICPOLARITY_FALLING
7558 * @arg TIM_ICPOLARITY_BOTHEDGE
7559 * @param TIM_ICFilter Specifies the Input Capture Filter.
7560 * This parameter must be a value between 0x00 and 0x0F.
7561 * @retval None
7562 */
TIM_TI1_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7563 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7564 {
7565 uint32_t tmpccmr1;
7566 uint32_t tmpccer;
7567
7568 /* Disable the Channel 1: Reset the CC1E Bit */
7569 tmpccer = TIMx->CCER;
7570 TIMx->CCER &= ~TIM_CCER_CC1E;
7571 tmpccmr1 = TIMx->CCMR1;
7572
7573 /* Set the filter */
7574 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7575 tmpccmr1 |= (TIM_ICFilter << 4U);
7576
7577 /* Select the Polarity and set the CC1E Bit */
7578 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7579 tmpccer |= TIM_ICPolarity;
7580
7581 /* Write to TIMx CCMR1 and CCER registers */
7582 TIMx->CCMR1 = tmpccmr1;
7583 TIMx->CCER = tmpccer;
7584 }
7585
7586 /**
7587 * @brief Configure the TI2 as Input.
7588 * @param TIMx to select the TIM peripheral
7589 * @param TIM_ICPolarity The Input Polarity.
7590 * This parameter can be one of the following values:
7591 * @arg TIM_ICPOLARITY_RISING
7592 * @arg TIM_ICPOLARITY_FALLING
7593 * @arg TIM_ICPOLARITY_BOTHEDGE
7594 * @param TIM_ICSelection specifies the input to be used.
7595 * This parameter can be one of the following values:
7596 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
7597 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
7598 * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
7599 * @param TIM_ICFilter Specifies the Input Capture Filter.
7600 * This parameter must be a value between 0x00 and 0x0F.
7601 * @retval None
7602 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
7603 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
7604 * protected against un-initialized filter and polarity values.
7605 */
TIM_TI2_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7606 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7607 uint32_t TIM_ICFilter)
7608 {
7609 uint32_t tmpccmr1;
7610 uint32_t tmpccer;
7611
7612 /* Disable the Channel 2: Reset the CC2E Bit */
7613 tmpccer = TIMx->CCER;
7614 TIMx->CCER &= ~TIM_CCER_CC2E;
7615 tmpccmr1 = TIMx->CCMR1;
7616
7617 /* Select the Input */
7618 tmpccmr1 &= ~TIM_CCMR1_CC2S;
7619 tmpccmr1 |= (TIM_ICSelection << 8U);
7620
7621 /* Set the filter */
7622 tmpccmr1 &= ~TIM_CCMR1_IC2F;
7623 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
7624
7625 /* Select the Polarity and set the CC2E Bit */
7626 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7627 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
7628
7629 /* Write to TIMx CCMR1 and CCER registers */
7630 TIMx->CCMR1 = tmpccmr1 ;
7631 TIMx->CCER = tmpccer;
7632 }
7633
7634 /**
7635 * @brief Configure the Polarity and Filter for TI2.
7636 * @param TIMx to select the TIM peripheral.
7637 * @param TIM_ICPolarity The Input Polarity.
7638 * This parameter can be one of the following values:
7639 * @arg TIM_ICPOLARITY_RISING
7640 * @arg TIM_ICPOLARITY_FALLING
7641 * @arg TIM_ICPOLARITY_BOTHEDGE
7642 * @param TIM_ICFilter Specifies the Input Capture Filter.
7643 * This parameter must be a value between 0x00 and 0x0F.
7644 * @retval None
7645 */
TIM_TI2_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7646 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7647 {
7648 uint32_t tmpccmr1;
7649 uint32_t tmpccer;
7650
7651 /* Disable the Channel 2: Reset the CC2E Bit */
7652 tmpccer = TIMx->CCER;
7653 TIMx->CCER &= ~TIM_CCER_CC2E;
7654 tmpccmr1 = TIMx->CCMR1;
7655
7656 /* Set the filter */
7657 tmpccmr1 &= ~TIM_CCMR1_IC2F;
7658 tmpccmr1 |= (TIM_ICFilter << 12U);
7659
7660 /* Select the Polarity and set the CC2E Bit */
7661 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7662 tmpccer |= (TIM_ICPolarity << 4U);
7663
7664 /* Write to TIMx CCMR1 and CCER registers */
7665 TIMx->CCMR1 = tmpccmr1 ;
7666 TIMx->CCER = tmpccer;
7667 }
7668
7669 /**
7670 * @brief Configure the TI3 as Input.
7671 * @param TIMx to select the TIM peripheral
7672 * @param TIM_ICPolarity The Input Polarity.
7673 * This parameter can be one of the following values:
7674 * @arg TIM_ICPOLARITY_RISING
7675 * @arg TIM_ICPOLARITY_FALLING
7676 * @arg TIM_ICPOLARITY_BOTHEDGE
7677 * @param TIM_ICSelection specifies the input to be used.
7678 * This parameter can be one of the following values:
7679 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
7680 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
7681 * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
7682 * @param TIM_ICFilter Specifies the Input Capture Filter.
7683 * This parameter must be a value between 0x00 and 0x0F.
7684 * @retval None
7685 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
7686 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7687 * protected against un-initialized filter and polarity values.
7688 */
TIM_TI3_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7689 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7690 uint32_t TIM_ICFilter)
7691 {
7692 uint32_t tmpccmr2;
7693 uint32_t tmpccer;
7694
7695 /* Disable the Channel 3: Reset the CC3E Bit */
7696 tmpccer = TIMx->CCER;
7697 TIMx->CCER &= ~TIM_CCER_CC3E;
7698 tmpccmr2 = TIMx->CCMR2;
7699
7700 /* Select the Input */
7701 tmpccmr2 &= ~TIM_CCMR2_CC3S;
7702 tmpccmr2 |= TIM_ICSelection;
7703
7704 /* Set the filter */
7705 tmpccmr2 &= ~TIM_CCMR2_IC3F;
7706 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
7707
7708 /* Select the Polarity and set the CC3E Bit */
7709 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
7710 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
7711
7712 /* Write to TIMx CCMR2 and CCER registers */
7713 TIMx->CCMR2 = tmpccmr2;
7714 TIMx->CCER = tmpccer;
7715 }
7716
7717 /**
7718 * @brief Configure the TI4 as Input.
7719 * @param TIMx to select the TIM peripheral
7720 * @param TIM_ICPolarity The Input Polarity.
7721 * This parameter can be one of the following values:
7722 * @arg TIM_ICPOLARITY_RISING
7723 * @arg TIM_ICPOLARITY_FALLING
7724 * @arg TIM_ICPOLARITY_BOTHEDGE
7725 * @param TIM_ICSelection specifies the input to be used.
7726 * This parameter can be one of the following values:
7727 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
7728 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
7729 * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
7730 * @param TIM_ICFilter Specifies the Input Capture Filter.
7731 * This parameter must be a value between 0x00 and 0x0F.
7732 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
7733 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7734 * protected against un-initialized filter and polarity values.
7735 * @retval None
7736 */
TIM_TI4_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7737 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7738 uint32_t TIM_ICFilter)
7739 {
7740 uint32_t tmpccmr2;
7741 uint32_t tmpccer;
7742
7743 /* Disable the Channel 4: Reset the CC4E Bit */
7744 tmpccer = TIMx->CCER;
7745 TIMx->CCER &= ~TIM_CCER_CC4E;
7746 tmpccmr2 = TIMx->CCMR2;
7747
7748 /* Select the Input */
7749 tmpccmr2 &= ~TIM_CCMR2_CC4S;
7750 tmpccmr2 |= (TIM_ICSelection << 8U);
7751
7752 /* Set the filter */
7753 tmpccmr2 &= ~TIM_CCMR2_IC4F;
7754 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
7755
7756 /* Select the Polarity and set the CC4E Bit */
7757 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
7758 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
7759
7760 /* Write to TIMx CCMR2 and CCER registers */
7761 TIMx->CCMR2 = tmpccmr2;
7762 TIMx->CCER = tmpccer ;
7763 }
7764
7765 /**
7766 * @brief Selects the Input Trigger source
7767 * @param TIMx to select the TIM peripheral
7768 * @param InputTriggerSource The Input Trigger source.
7769 * This parameter can be one of the following values:
7770 * @arg TIM_TS_ITR0: Internal Trigger 0
7771 * @arg TIM_TS_ITR1: Internal Trigger 1
7772 * @arg TIM_TS_ITR2: Internal Trigger 2
7773 * @arg TIM_TS_ITR3: Internal Trigger 3
7774 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
7775 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
7776 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
7777 * @arg TIM_TS_ETRF: External Trigger input
7778 * @retval None
7779 */
TIM_ITRx_SetConfig(TIM_TypeDef * TIMx,uint32_t InputTriggerSource)7780 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
7781 {
7782 uint32_t tmpsmcr;
7783
7784 /* Get the TIMx SMCR register value */
7785 tmpsmcr = TIMx->SMCR;
7786 /* Reset the TS Bits */
7787 tmpsmcr &= ~TIM_SMCR_TS;
7788 /* Set the Input Trigger source and the slave mode*/
7789 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
7790 /* Write to TIMx SMCR */
7791 TIMx->SMCR = tmpsmcr;
7792 }
7793 /**
7794 * @brief Configures the TIMx External Trigger (ETR).
7795 * @param TIMx to select the TIM peripheral
7796 * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
7797 * This parameter can be one of the following values:
7798 * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
7799 * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
7800 * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
7801 * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
7802 * @param TIM_ExtTRGPolarity The external Trigger Polarity.
7803 * This parameter can be one of the following values:
7804 * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
7805 * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
7806 * @param ExtTRGFilter External Trigger Filter.
7807 * This parameter must be a value between 0x00 and 0x0F
7808 * @retval None
7809 */
TIM_ETR_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ExtTRGPrescaler,uint32_t TIM_ExtTRGPolarity,uint32_t ExtTRGFilter)7810 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
7811 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
7812 {
7813 uint32_t tmpsmcr;
7814
7815 tmpsmcr = TIMx->SMCR;
7816
7817 /* Reset the ETR Bits */
7818 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
7819
7820 /* Set the Prescaler, the Filter value and the Polarity */
7821 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
7822
7823 /* Write to TIMx SMCR */
7824 TIMx->SMCR = tmpsmcr;
7825 }
7826
7827 /**
7828 * @brief Enables or disables the TIM Capture Compare Channel x.
7829 * @param TIMx to select the TIM peripheral
7830 * @param Channel specifies the TIM Channel
7831 * This parameter can be one of the following values:
7832 * @arg TIM_CHANNEL_1: TIM Channel 1
7833 * @arg TIM_CHANNEL_2: TIM Channel 2
7834 * @arg TIM_CHANNEL_3: TIM Channel 3
7835 * @arg TIM_CHANNEL_4: TIM Channel 4
7836 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
7837 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
7838 * @param ChannelState specifies the TIM Channel CCxE bit new state.
7839 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
7840 * @retval None
7841 */
TIM_CCxChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelState)7842 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
7843 {
7844 uint32_t tmp;
7845
7846 /* Check the parameters */
7847 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
7848 assert_param(IS_TIM_CHANNELS(Channel));
7849
7850 tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
7851
7852 /* Reset the CCxE Bit */
7853 TIMx->CCER &= ~tmp;
7854
7855 /* Set or reset the CCxE Bit */
7856 TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
7857 }
7858
7859 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7860 /**
7861 * @brief Reset interrupt callbacks to the legacy weak callbacks.
7862 * @param htim pointer to a TIM_HandleTypeDef structure that contains
7863 * the configuration information for TIM module.
7864 * @retval None
7865 */
TIM_ResetCallback(TIM_HandleTypeDef * htim)7866 void TIM_ResetCallback(TIM_HandleTypeDef *htim)
7867 {
7868 /* Reset the TIM callback to the legacy weak callbacks */
7869 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
7870 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
7871 htim->TriggerCallback = HAL_TIM_TriggerCallback;
7872 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
7873 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
7874 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
7875 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
7876 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
7877 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
7878 htim->ErrorCallback = HAL_TIM_ErrorCallback;
7879 htim->CommutationCallback = HAL_TIMEx_CommutCallback;
7880 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
7881 htim->BreakCallback = HAL_TIMEx_BreakCallback;
7882 htim->Break2Callback = HAL_TIMEx_Break2Callback;
7883 }
7884 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7885
7886 /**
7887 * @}
7888 */
7889
7890 #endif /* HAL_TIM_MODULE_ENABLED */
7891 /**
7892 * @}
7893 */
7894
7895 /**
7896 * @}
7897 */
7898
