1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_spi.c
4 * @author MCD Application Team
5 * @brief SPI HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2017 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 ==============================================================================
25 ##### How to use this driver #####
26 ==============================================================================
27 [..]
28 The SPI HAL driver can be used as follows:
29
30 (#) Declare a SPI_HandleTypeDef handle structure, for example:
31 SPI_HandleTypeDef hspi;
32
33 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
34 (##) Enable the SPIx interface clock
35 (##) SPI pins configuration
36 (+++) Enable the clock for the SPI GPIOs
37 (+++) Configure these SPI pins as alternate function push-pull
38 (##) NVIC configuration if you need to use interrupt process
39 (+++) Configure the SPIx interrupt priority
40 (+++) Enable the NVIC SPI IRQ handle
41 (##) DMA Configuration if you need to use DMA process
42 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
43 (+++) Enable the DMAx clock
44 (+++) Configure the DMA handle parameters
45 (+++) Configure the DMA Tx or Rx Stream/Channel
46 (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle
47 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
48
49 (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
50 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
51
52 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
53 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
54 by calling the customized HAL_SPI_MspInit() API.
55 [..]
56 Circular mode restriction:
57 (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
58 (##) Master 2Lines RxOnly
59 (##) Master 1Line Rx
60 (#) The CRC feature is not managed when the DMA circular mode is enabled
61 (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
62 the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
63 [..]
64 Master Receive mode restriction:
65 (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
66 bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
67 does not initiate a new transfer the following procedure has to be respected:
68 (##) HAL_SPI_DeInit()
69 (##) HAL_SPI_Init()
70 [..]
71 Callback registration:
72
73 (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
74 allows the user to configure dynamically the driver callbacks.
75 Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
76
77 Function HAL_SPI_RegisterCallback() allows to register following callbacks:
78 (++) TxCpltCallback : SPI Tx Completed callback
79 (++) RxCpltCallback : SPI Rx Completed callback
80 (++) TxRxCpltCallback : SPI TxRx Completed callback
81 (++) TxHalfCpltCallback : SPI Tx Half Completed callback
82 (++) RxHalfCpltCallback : SPI Rx Half Completed callback
83 (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
84 (++) ErrorCallback : SPI Error callback
85 (++) AbortCpltCallback : SPI Abort callback
86 (++) MspInitCallback : SPI Msp Init callback
87 (++) MspDeInitCallback : SPI Msp DeInit callback
88 This function takes as parameters the HAL peripheral handle, the Callback ID
89 and a pointer to the user callback function.
90
91
92 (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
93 weak function.
94 HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
95 and the Callback ID.
96 This function allows to reset following callbacks:
97 (++) TxCpltCallback : SPI Tx Completed callback
98 (++) RxCpltCallback : SPI Rx Completed callback
99 (++) TxRxCpltCallback : SPI TxRx Completed callback
100 (++) TxHalfCpltCallback : SPI Tx Half Completed callback
101 (++) RxHalfCpltCallback : SPI Rx Half Completed callback
102 (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
103 (++) ErrorCallback : SPI Error callback
104 (++) AbortCpltCallback : SPI Abort callback
105 (++) MspInitCallback : SPI Msp Init callback
106 (++) MspDeInitCallback : SPI Msp DeInit callback
107
108 [..]
109 By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
110 all callbacks are set to the corresponding weak functions:
111 examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
112 Exception done for MspInit and MspDeInit functions that are
113 reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
114 these callbacks are null (not registered beforehand).
115 If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
116 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
117
118 [..]
119 Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
120 Exception done MspInit/MspDeInit functions that can be registered/unregistered
121 in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
122 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
123 Then, the user first registers the MspInit/MspDeInit user callbacks
124 using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
125 or HAL_SPI_Init() function.
126
127 [..]
128 When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
129 not defined, the callback registering feature is not available
130 and weak (surcharged) callbacks are used.
131
132 [..]
133 Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
134 the following table resume the max SPI frequency reached with data size 8bits/16bits,
135 according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
136
137 @endverbatim
138
139 Additional table :
140
141 DataSize = SPI_DATASIZE_8BIT:
142 +----------------------------------------------------------------------------------------------+
143 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
144 | Process | Transfer mode |---------------------|----------------------|----------------------|
145 | | | Master | Slave | Master | Slave | Master | Slave |
146 |==============================================================================================|
147 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
148 | X |----------------|----------|----------|-----------|----------|-----------|----------|
149 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
150 | R |----------------|----------|----------|-----------|----------|-----------|----------|
151 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
152 |=========|================|==========|==========|===========|==========|===========|==========|
153 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
154 | |----------------|----------|----------|-----------|----------|-----------|----------|
155 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
156 | X |----------------|----------|----------|-----------|----------|-----------|----------|
157 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
158 |=========|================|==========|==========|===========|==========|===========|==========|
159 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
160 | |----------------|----------|----------|-----------|----------|-----------|----------|
161 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
162 | X |----------------|----------|----------|-----------|----------|-----------|----------|
163 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
164 +----------------------------------------------------------------------------------------------+
165
166 DataSize = SPI_DATASIZE_16BIT:
167 +----------------------------------------------------------------------------------------------+
168 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
169 | Process | Transfer mode |---------------------|----------------------|----------------------|
170 | | | Master | Slave | Master | Slave | Master | Slave |
171 |==============================================================================================|
172 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
173 | X |----------------|----------|----------|-----------|----------|-----------|----------|
174 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
175 | R |----------------|----------|----------|-----------|----------|-----------|----------|
176 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
177 |=========|================|==========|==========|===========|==========|===========|==========|
178 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
179 | |----------------|----------|----------|-----------|----------|-----------|----------|
180 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
181 | X |----------------|----------|----------|-----------|----------|-----------|----------|
182 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
183 |=========|================|==========|==========|===========|==========|===========|==========|
184 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
185 | |----------------|----------|----------|-----------|----------|-----------|----------|
186 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
187 | X |----------------|----------|----------|-----------|----------|-----------|----------|
188 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
189 +----------------------------------------------------------------------------------------------+
190 @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
191 SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
192 @note
193 (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
194 (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
195 (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
196
197 */
198
199 /* Includes ------------------------------------------------------------------*/
200 #include "stm32f7xx_hal.h"
201
202 /** @addtogroup STM32F7xx_HAL_Driver
203 * @{
204 */
205
206 /** @defgroup SPI SPI
207 * @brief SPI HAL module driver
208 * @{
209 */
210 #ifdef HAL_SPI_MODULE_ENABLED
211
212 /* Private typedef -----------------------------------------------------------*/
213 /* Private defines -----------------------------------------------------------*/
214 /** @defgroup SPI_Private_Constants SPI Private Constants
215 * @{
216 */
217 #define SPI_DEFAULT_TIMEOUT 100U
218 #define SPI_BSY_FLAG_WORKAROUND_TIMEOUT 1000U /*!< Timeout 1000 µs */
219 /**
220 * @}
221 */
222
223 /* Private macros ------------------------------------------------------------*/
224 /* Private variables ---------------------------------------------------------*/
225 /* Private function prototypes -----------------------------------------------*/
226 /** @defgroup SPI_Private_Functions SPI Private Functions
227 * @{
228 */
229 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
230 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
231 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
232 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
233 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
234 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
235 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
236 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
237 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
238 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
239 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
240 uint32_t Timeout, uint32_t Tickstart);
241 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
242 uint32_t Timeout, uint32_t Tickstart);
243 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
244 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
245 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
246 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
247 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
248 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
249 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
250 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
251 #if (USE_SPI_CRC != 0U)
252 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
253 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
254 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
255 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
256 #endif /* USE_SPI_CRC */
257 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
258 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
259 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
260 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
261 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
262 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
263 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
264 /**
265 * @}
266 */
267
268 /* Exported functions --------------------------------------------------------*/
269 /** @defgroup SPI_Exported_Functions SPI Exported Functions
270 * @{
271 */
272
273 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
274 * @brief Initialization and Configuration functions
275 *
276 @verbatim
277 ===============================================================================
278 ##### Initialization and de-initialization functions #####
279 ===============================================================================
280 [..] This subsection provides a set of functions allowing to initialize and
281 de-initialize the SPIx peripheral:
282
283 (+) User must implement HAL_SPI_MspInit() function in which he configures
284 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
285
286 (+) Call the function HAL_SPI_Init() to configure the selected device with
287 the selected configuration:
288 (++) Mode
289 (++) Direction
290 (++) Data Size
291 (++) Clock Polarity and Phase
292 (++) NSS Management
293 (++) BaudRate Prescaler
294 (++) FirstBit
295 (++) TIMode
296 (++) CRC Calculation
297 (++) CRC Polynomial if CRC enabled
298 (++) CRC Length, used only with Data8 and Data16
299 (++) FIFO reception threshold
300
301 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
302 of the selected SPIx peripheral.
303
304 @endverbatim
305 * @{
306 */
307
308 /**
309 * @brief Initialize the SPI according to the specified parameters
310 * in the SPI_InitTypeDef and initialize the associated handle.
311 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
312 * the configuration information for SPI module.
313 * @retval HAL status
314 */
HAL_SPI_Init(SPI_HandleTypeDef * hspi)315 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
316 {
317 uint32_t frxth;
318
319 /* Check the SPI handle allocation */
320 if (hspi == NULL)
321 {
322 return HAL_ERROR;
323 }
324
325 /* Check the parameters */
326 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
327 assert_param(IS_SPI_MODE(hspi->Init.Mode));
328 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
329 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
330 assert_param(IS_SPI_NSS(hspi->Init.NSS));
331 assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
332 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
333 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
334 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
335 if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
336 {
337 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
338 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
339
340 if (hspi->Init.Mode == SPI_MODE_MASTER)
341 {
342 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
343 }
344 else
345 {
346 /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
347 hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
348 }
349 }
350 else
351 {
352 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
353
354 /* Force polarity and phase to TI protocaol requirements */
355 hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
356 hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
357 }
358 #if (USE_SPI_CRC != 0U)
359 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
360 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
361 {
362 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
363 assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
364 }
365 #else
366 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
367 #endif /* USE_SPI_CRC */
368
369 if (hspi->State == HAL_SPI_STATE_RESET)
370 {
371 /* Allocate lock resource and initialize it */
372 hspi->Lock = HAL_UNLOCKED;
373
374 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
375 /* Init the SPI Callback settings */
376 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
377 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
378 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
379 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
380 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
381 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
382 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
383 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
384
385 if (hspi->MspInitCallback == NULL)
386 {
387 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
388 }
389
390 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
391 hspi->MspInitCallback(hspi);
392 #else
393 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
394 HAL_SPI_MspInit(hspi);
395 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
396 }
397
398 hspi->State = HAL_SPI_STATE_BUSY;
399
400 /* Disable the selected SPI peripheral */
401 __HAL_SPI_DISABLE(hspi);
402
403 /* Align by default the rs fifo threshold on the data size */
404 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
405 {
406 frxth = SPI_RXFIFO_THRESHOLD_HF;
407 }
408 else
409 {
410 frxth = SPI_RXFIFO_THRESHOLD_QF;
411 }
412
413 /* CRC calculation is valid only for 16Bit and 8 Bit */
414 if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
415 {
416 /* CRC must be disabled */
417 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
418 }
419
420 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
421 /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
422 Communication speed, First bit and CRC calculation state */
423 WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
424 (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) |
425 (hspi->Init.CLKPolarity & SPI_CR1_CPOL) |
426 (hspi->Init.CLKPhase & SPI_CR1_CPHA) |
427 (hspi->Init.NSS & SPI_CR1_SSM) |
428 (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
429 (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
430 (hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
431 #if (USE_SPI_CRC != 0U)
432 /*---------------------------- SPIx CRCL Configuration -------------------*/
433 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
434 {
435 /* Align the CRC Length on the data size */
436 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
437 {
438 /* CRC Length aligned on the data size : value set by default */
439 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
440 {
441 hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
442 }
443 else
444 {
445 hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
446 }
447 }
448
449 /* Configure : CRC Length */
450 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
451 {
452 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCL);
453 }
454 }
455 #endif /* USE_SPI_CRC */
456
457 /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
458 WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
459 (hspi->Init.TIMode & SPI_CR2_FRF) |
460 (hspi->Init.NSSPMode & SPI_CR2_NSSP) |
461 (hspi->Init.DataSize & SPI_CR2_DS_Msk) |
462 (frxth & SPI_CR2_FRXTH)));
463
464 #if (USE_SPI_CRC != 0U)
465 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
466 /* Configure : CRC Polynomial */
467 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
468 {
469 WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk));
470 }
471 #endif /* USE_SPI_CRC */
472
473 #if defined(SPI_I2SCFGR_I2SMOD)
474 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
475 CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
476 #endif /* SPI_I2SCFGR_I2SMOD */
477
478 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
479 hspi->State = HAL_SPI_STATE_READY;
480
481 return HAL_OK;
482 }
483
484 /**
485 * @brief De-Initialize the SPI peripheral.
486 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
487 * the configuration information for SPI module.
488 * @retval HAL status
489 */
HAL_SPI_DeInit(SPI_HandleTypeDef * hspi)490 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
491 {
492 /* Check the SPI handle allocation */
493 if (hspi == NULL)
494 {
495 return HAL_ERROR;
496 }
497
498 /* Check SPI Instance parameter */
499 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
500
501 hspi->State = HAL_SPI_STATE_BUSY;
502
503 /* Disable the SPI Peripheral Clock */
504 __HAL_SPI_DISABLE(hspi);
505
506 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
507 if (hspi->MspDeInitCallback == NULL)
508 {
509 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
510 }
511
512 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
513 hspi->MspDeInitCallback(hspi);
514 #else
515 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
516 HAL_SPI_MspDeInit(hspi);
517 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
518
519 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
520 hspi->State = HAL_SPI_STATE_RESET;
521
522 /* Release Lock */
523 __HAL_UNLOCK(hspi);
524
525 return HAL_OK;
526 }
527
528 /**
529 * @brief Initialize the SPI MSP.
530 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
531 * the configuration information for SPI module.
532 * @retval None
533 */
HAL_SPI_MspInit(SPI_HandleTypeDef * hspi)534 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
535 {
536 /* Prevent unused argument(s) compilation warning */
537 UNUSED(hspi);
538
539 /* NOTE : This function should not be modified, when the callback is needed,
540 the HAL_SPI_MspInit should be implemented in the user file
541 */
542 }
543
544 /**
545 * @brief De-Initialize the SPI MSP.
546 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
547 * the configuration information for SPI module.
548 * @retval None
549 */
HAL_SPI_MspDeInit(SPI_HandleTypeDef * hspi)550 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
551 {
552 /* Prevent unused argument(s) compilation warning */
553 UNUSED(hspi);
554
555 /* NOTE : This function should not be modified, when the callback is needed,
556 the HAL_SPI_MspDeInit should be implemented in the user file
557 */
558 }
559
560 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
561 /**
562 * @brief Register a User SPI Callback
563 * To be used instead of the weak predefined callback
564 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
565 * the configuration information for the specified SPI.
566 * @param CallbackID ID of the callback to be registered
567 * @param pCallback pointer to the Callback function
568 * @retval HAL status
569 */
HAL_SPI_RegisterCallback(SPI_HandleTypeDef * hspi,HAL_SPI_CallbackIDTypeDef CallbackID,pSPI_CallbackTypeDef pCallback)570 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
571 pSPI_CallbackTypeDef pCallback)
572 {
573 HAL_StatusTypeDef status = HAL_OK;
574
575 if (pCallback == NULL)
576 {
577 /* Update the error code */
578 hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
579
580 return HAL_ERROR;
581 }
582 /* Process locked */
583 __HAL_LOCK(hspi);
584
585 if (HAL_SPI_STATE_READY == hspi->State)
586 {
587 switch (CallbackID)
588 {
589 case HAL_SPI_TX_COMPLETE_CB_ID :
590 hspi->TxCpltCallback = pCallback;
591 break;
592
593 case HAL_SPI_RX_COMPLETE_CB_ID :
594 hspi->RxCpltCallback = pCallback;
595 break;
596
597 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
598 hspi->TxRxCpltCallback = pCallback;
599 break;
600
601 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
602 hspi->TxHalfCpltCallback = pCallback;
603 break;
604
605 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
606 hspi->RxHalfCpltCallback = pCallback;
607 break;
608
609 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
610 hspi->TxRxHalfCpltCallback = pCallback;
611 break;
612
613 case HAL_SPI_ERROR_CB_ID :
614 hspi->ErrorCallback = pCallback;
615 break;
616
617 case HAL_SPI_ABORT_CB_ID :
618 hspi->AbortCpltCallback = pCallback;
619 break;
620
621 case HAL_SPI_MSPINIT_CB_ID :
622 hspi->MspInitCallback = pCallback;
623 break;
624
625 case HAL_SPI_MSPDEINIT_CB_ID :
626 hspi->MspDeInitCallback = pCallback;
627 break;
628
629 default :
630 /* Update the error code */
631 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
632
633 /* Return error status */
634 status = HAL_ERROR;
635 break;
636 }
637 }
638 else if (HAL_SPI_STATE_RESET == hspi->State)
639 {
640 switch (CallbackID)
641 {
642 case HAL_SPI_MSPINIT_CB_ID :
643 hspi->MspInitCallback = pCallback;
644 break;
645
646 case HAL_SPI_MSPDEINIT_CB_ID :
647 hspi->MspDeInitCallback = pCallback;
648 break;
649
650 default :
651 /* Update the error code */
652 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
653
654 /* Return error status */
655 status = HAL_ERROR;
656 break;
657 }
658 }
659 else
660 {
661 /* Update the error code */
662 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
663
664 /* Return error status */
665 status = HAL_ERROR;
666 }
667
668 /* Release Lock */
669 __HAL_UNLOCK(hspi);
670 return status;
671 }
672
673 /**
674 * @brief Unregister an SPI Callback
675 * SPI callback is redirected to the weak predefined callback
676 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
677 * the configuration information for the specified SPI.
678 * @param CallbackID ID of the callback to be unregistered
679 * @retval HAL status
680 */
HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef * hspi,HAL_SPI_CallbackIDTypeDef CallbackID)681 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
682 {
683 HAL_StatusTypeDef status = HAL_OK;
684
685 /* Process locked */
686 __HAL_LOCK(hspi);
687
688 if (HAL_SPI_STATE_READY == hspi->State)
689 {
690 switch (CallbackID)
691 {
692 case HAL_SPI_TX_COMPLETE_CB_ID :
693 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
694 break;
695
696 case HAL_SPI_RX_COMPLETE_CB_ID :
697 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
698 break;
699
700 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
701 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
702 break;
703
704 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
705 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
706 break;
707
708 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
709 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
710 break;
711
712 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
713 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
714 break;
715
716 case HAL_SPI_ERROR_CB_ID :
717 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
718 break;
719
720 case HAL_SPI_ABORT_CB_ID :
721 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
722 break;
723
724 case HAL_SPI_MSPINIT_CB_ID :
725 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
726 break;
727
728 case HAL_SPI_MSPDEINIT_CB_ID :
729 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
730 break;
731
732 default :
733 /* Update the error code */
734 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
735
736 /* Return error status */
737 status = HAL_ERROR;
738 break;
739 }
740 }
741 else if (HAL_SPI_STATE_RESET == hspi->State)
742 {
743 switch (CallbackID)
744 {
745 case HAL_SPI_MSPINIT_CB_ID :
746 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
747 break;
748
749 case HAL_SPI_MSPDEINIT_CB_ID :
750 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
751 break;
752
753 default :
754 /* Update the error code */
755 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
756
757 /* Return error status */
758 status = HAL_ERROR;
759 break;
760 }
761 }
762 else
763 {
764 /* Update the error code */
765 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
766
767 /* Return error status */
768 status = HAL_ERROR;
769 }
770
771 /* Release Lock */
772 __HAL_UNLOCK(hspi);
773 return status;
774 }
775 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
776 /**
777 * @}
778 */
779
780 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
781 * @brief Data transfers functions
782 *
783 @verbatim
784 ==============================================================================
785 ##### IO operation functions #####
786 ===============================================================================
787 [..]
788 This subsection provides a set of functions allowing to manage the SPI
789 data transfers.
790
791 [..] The SPI supports master and slave mode :
792
793 (#) There are two modes of transfer:
794 (++) Blocking mode: The communication is performed in polling mode.
795 The HAL status of all data processing is returned by the same function
796 after finishing transfer.
797 (++) No-Blocking mode: The communication is performed using Interrupts
798 or DMA, These APIs return the HAL status.
799 The end of the data processing will be indicated through the
800 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
801 using DMA mode.
802 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
803 will be executed respectively at the end of the transmit or Receive process
804 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
805
806 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
807 exist for 1Line (simplex) and 2Lines (full duplex) modes.
808
809 @endverbatim
810 * @{
811 */
812
813 /**
814 * @brief Transmit an amount of data in blocking mode.
815 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
816 * the configuration information for SPI module.
817 * @param pData pointer to data buffer
818 * @param Size amount of data to be sent
819 * @param Timeout Timeout duration
820 * @retval HAL status
821 */
HAL_SPI_Transmit(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size,uint32_t Timeout)822 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
823 {
824 uint32_t tickstart;
825 HAL_StatusTypeDef errorcode = HAL_OK;
826 uint16_t initial_TxXferCount;
827
828 /* Check Direction parameter */
829 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
830
831 /* Process Locked */
832 __HAL_LOCK(hspi);
833
834 /* Init tickstart for timeout management*/
835 tickstart = HAL_GetTick();
836 initial_TxXferCount = Size;
837
838 if (hspi->State != HAL_SPI_STATE_READY)
839 {
840 errorcode = HAL_BUSY;
841 goto error;
842 }
843
844 if ((pData == NULL) || (Size == 0U))
845 {
846 errorcode = HAL_ERROR;
847 goto error;
848 }
849
850 /* Set the transaction information */
851 hspi->State = HAL_SPI_STATE_BUSY_TX;
852 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
853 hspi->pTxBuffPtr = (uint8_t *)pData;
854 hspi->TxXferSize = Size;
855 hspi->TxXferCount = Size;
856
857 /*Init field not used in handle to zero */
858 hspi->pRxBuffPtr = (uint8_t *)NULL;
859 hspi->RxXferSize = 0U;
860 hspi->RxXferCount = 0U;
861 hspi->TxISR = NULL;
862 hspi->RxISR = NULL;
863
864 /* Configure communication direction : 1Line */
865 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
866 {
867 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
868 __HAL_SPI_DISABLE(hspi);
869 SPI_1LINE_TX(hspi);
870 }
871
872 #if (USE_SPI_CRC != 0U)
873 /* Reset CRC Calculation */
874 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
875 {
876 SPI_RESET_CRC(hspi);
877 }
878 #endif /* USE_SPI_CRC */
879
880 /* Check if the SPI is already enabled */
881 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
882 {
883 /* Enable SPI peripheral */
884 __HAL_SPI_ENABLE(hspi);
885 }
886
887 /* Transmit data in 16 Bit mode */
888 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
889 {
890 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
891 {
892 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
893 hspi->pTxBuffPtr += sizeof(uint16_t);
894 hspi->TxXferCount--;
895 }
896 /* Transmit data in 16 Bit mode */
897 while (hspi->TxXferCount > 0U)
898 {
899 /* Wait until TXE flag is set to send data */
900 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
901 {
902 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
903 hspi->pTxBuffPtr += sizeof(uint16_t);
904 hspi->TxXferCount--;
905 }
906 else
907 {
908 /* Timeout management */
909 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
910 {
911 errorcode = HAL_TIMEOUT;
912 hspi->State = HAL_SPI_STATE_READY;
913 goto error;
914 }
915 }
916 }
917 }
918 /* Transmit data in 8 Bit mode */
919 else
920 {
921 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
922 {
923 if (hspi->TxXferCount > 1U)
924 {
925 /* write on the data register in packing mode */
926 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
927 hspi->pTxBuffPtr += sizeof(uint16_t);
928 hspi->TxXferCount -= 2U;
929 }
930 else
931 {
932 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
933 hspi->pTxBuffPtr ++;
934 hspi->TxXferCount--;
935 }
936 }
937 while (hspi->TxXferCount > 0U)
938 {
939 /* Wait until TXE flag is set to send data */
940 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
941 {
942 if (hspi->TxXferCount > 1U)
943 {
944 /* write on the data register in packing mode */
945 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
946 hspi->pTxBuffPtr += sizeof(uint16_t);
947 hspi->TxXferCount -= 2U;
948 }
949 else
950 {
951 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
952 hspi->pTxBuffPtr++;
953 hspi->TxXferCount--;
954 }
955 }
956 else
957 {
958 /* Timeout management */
959 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
960 {
961 errorcode = HAL_TIMEOUT;
962 hspi->State = HAL_SPI_STATE_READY;
963 goto error;
964 }
965 }
966 }
967 }
968 #if (USE_SPI_CRC != 0U)
969 /* Enable CRC Transmission */
970 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
971 {
972 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
973 }
974 #endif /* USE_SPI_CRC */
975
976 /* Check the end of the transaction */
977 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
978 {
979 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
980 }
981
982 /* Clear overrun flag in 2 Lines communication mode because received is not read */
983 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
984 {
985 __HAL_SPI_CLEAR_OVRFLAG(hspi);
986 }
987
988 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
989 {
990 errorcode = HAL_ERROR;
991 }
992 else
993 {
994 hspi->State = HAL_SPI_STATE_READY;
995 }
996
997 error:
998 /* Process Unlocked */
999 __HAL_UNLOCK(hspi);
1000 return errorcode;
1001 }
1002
1003 /**
1004 * @brief Receive an amount of data in blocking mode.
1005 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1006 * the configuration information for SPI module.
1007 * @param pData pointer to data buffer
1008 * @param Size amount of data to be received
1009 * @param Timeout Timeout duration
1010 * @retval HAL status
1011 */
HAL_SPI_Receive(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size,uint32_t Timeout)1012 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1013 {
1014 #if (USE_SPI_CRC != 0U)
1015 __IO uint32_t tmpreg = 0U;
1016 __IO uint8_t *ptmpreg8;
1017 __IO uint8_t tmpreg8 = 0;
1018 #endif /* USE_SPI_CRC */
1019 uint32_t tickstart;
1020 HAL_StatusTypeDef errorcode = HAL_OK;
1021
1022 if (hspi->State != HAL_SPI_STATE_READY)
1023 {
1024 errorcode = HAL_BUSY;
1025 goto error;
1026 }
1027
1028 if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
1029 {
1030 hspi->State = HAL_SPI_STATE_BUSY_RX;
1031 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1032 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
1033 }
1034
1035 /* Process Locked */
1036 __HAL_LOCK(hspi);
1037
1038 /* Init tickstart for timeout management*/
1039 tickstart = HAL_GetTick();
1040
1041 if ((pData == NULL) || (Size == 0U))
1042 {
1043 errorcode = HAL_ERROR;
1044 goto error;
1045 }
1046
1047 /* Set the transaction information */
1048 hspi->State = HAL_SPI_STATE_BUSY_RX;
1049 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1050 hspi->pRxBuffPtr = (uint8_t *)pData;
1051 hspi->RxXferSize = Size;
1052 hspi->RxXferCount = Size;
1053
1054 /*Init field not used in handle to zero */
1055 hspi->pTxBuffPtr = (uint8_t *)NULL;
1056 hspi->TxXferSize = 0U;
1057 hspi->TxXferCount = 0U;
1058 hspi->RxISR = NULL;
1059 hspi->TxISR = NULL;
1060
1061 #if (USE_SPI_CRC != 0U)
1062 /* Reset CRC Calculation */
1063 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1064 {
1065 SPI_RESET_CRC(hspi);
1066 /* this is done to handle the CRCNEXT before the latest data */
1067 hspi->RxXferCount--;
1068 }
1069 #endif /* USE_SPI_CRC */
1070
1071 /* Set the Rx Fifo threshold */
1072 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1073 {
1074 /* Set RX Fifo threshold according the reception data length: 16bit */
1075 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1076 }
1077 else
1078 {
1079 /* Set RX Fifo threshold according the reception data length: 8bit */
1080 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1081 }
1082
1083 /* Configure communication direction: 1Line */
1084 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1085 {
1086 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1087 __HAL_SPI_DISABLE(hspi);
1088 SPI_1LINE_RX(hspi);
1089 }
1090
1091 /* Check if the SPI is already enabled */
1092 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1093 {
1094 /* Enable SPI peripheral */
1095 __HAL_SPI_ENABLE(hspi);
1096 }
1097
1098 /* Receive data in 8 Bit mode */
1099 if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
1100 {
1101 /* Transfer loop */
1102 while (hspi->RxXferCount > 0U)
1103 {
1104 /* Check the RXNE flag */
1105 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1106 {
1107 /* read the received data */
1108 (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1109 hspi->pRxBuffPtr += sizeof(uint8_t);
1110 hspi->RxXferCount--;
1111 }
1112 else
1113 {
1114 /* Timeout management */
1115 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1116 {
1117 errorcode = HAL_TIMEOUT;
1118 hspi->State = HAL_SPI_STATE_READY;
1119 goto error;
1120 }
1121 }
1122 }
1123 }
1124 else
1125 {
1126 /* Transfer loop */
1127 while (hspi->RxXferCount > 0U)
1128 {
1129 /* Check the RXNE flag */
1130 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1131 {
1132 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1133 hspi->pRxBuffPtr += sizeof(uint16_t);
1134 hspi->RxXferCount--;
1135 }
1136 else
1137 {
1138 /* Timeout management */
1139 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1140 {
1141 errorcode = HAL_TIMEOUT;
1142 hspi->State = HAL_SPI_STATE_READY;
1143 goto error;
1144 }
1145 }
1146 }
1147 }
1148
1149 #if (USE_SPI_CRC != 0U)
1150 /* Handle the CRC Transmission */
1151 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1152 {
1153 /* freeze the CRC before the latest data */
1154 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1155
1156 /* Read the latest data */
1157 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1158 {
1159 /* the latest data has not been received */
1160 errorcode = HAL_TIMEOUT;
1161 goto error;
1162 }
1163
1164 /* Receive last data in 16 Bit mode */
1165 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1166 {
1167 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1168 }
1169 /* Receive last data in 8 Bit mode */
1170 else
1171 {
1172 (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1173 }
1174
1175 /* Wait the CRC data */
1176 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1177 {
1178 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1179 errorcode = HAL_TIMEOUT;
1180 goto error;
1181 }
1182
1183 /* Read CRC to Flush DR and RXNE flag */
1184 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1185 {
1186 /* Read 16bit CRC */
1187 tmpreg = READ_REG(hspi->Instance->DR);
1188 /* To avoid GCC warning */
1189 UNUSED(tmpreg);
1190 }
1191 else
1192 {
1193 /* Initialize the 8bit temporary pointer */
1194 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
1195 /* Read 8bit CRC */
1196 tmpreg8 = *ptmpreg8;
1197 /* To avoid GCC warning */
1198 UNUSED(tmpreg8);
1199
1200 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1201 {
1202 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1203 {
1204 /* Error on the CRC reception */
1205 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1206 errorcode = HAL_TIMEOUT;
1207 goto error;
1208 }
1209 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
1210 tmpreg8 = *ptmpreg8;
1211 /* To avoid GCC warning */
1212 UNUSED(tmpreg8);
1213 }
1214 }
1215 }
1216 #endif /* USE_SPI_CRC */
1217
1218 /* Check the end of the transaction */
1219 if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1220 {
1221 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1222 }
1223
1224 #if (USE_SPI_CRC != 0U)
1225 /* Check if CRC error occurred */
1226 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1227 {
1228 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1229 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1230 }
1231 #endif /* USE_SPI_CRC */
1232
1233 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1234 {
1235 errorcode = HAL_ERROR;
1236 }
1237 else
1238 {
1239 hspi->State = HAL_SPI_STATE_READY;
1240 }
1241
1242 error :
1243 __HAL_UNLOCK(hspi);
1244 return errorcode;
1245 }
1246
1247 /**
1248 * @brief Transmit and Receive an amount of data in blocking mode.
1249 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1250 * the configuration information for SPI module.
1251 * @param pTxData pointer to transmission data buffer
1252 * @param pRxData pointer to reception data buffer
1253 * @param Size amount of data to be sent and received
1254 * @param Timeout Timeout duration
1255 * @retval HAL status
1256 */
HAL_SPI_TransmitReceive(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size,uint32_t Timeout)1257 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
1258 uint32_t Timeout)
1259 {
1260 uint16_t initial_TxXferCount;
1261 uint16_t initial_RxXferCount;
1262 uint32_t tmp_mode;
1263 HAL_SPI_StateTypeDef tmp_state;
1264 uint32_t tickstart;
1265 #if (USE_SPI_CRC != 0U)
1266 __IO uint32_t tmpreg = 0U;
1267 uint32_t spi_cr1;
1268 uint32_t spi_cr2;
1269 __IO uint8_t *ptmpreg8;
1270 __IO uint8_t tmpreg8 = 0;
1271 #endif /* USE_SPI_CRC */
1272
1273 /* Variable used to alternate Rx and Tx during transfer */
1274 uint32_t txallowed = 1U;
1275 HAL_StatusTypeDef errorcode = HAL_OK;
1276
1277 /* Check Direction parameter */
1278 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1279
1280 /* Process Locked */
1281 __HAL_LOCK(hspi);
1282
1283 /* Init tickstart for timeout management*/
1284 tickstart = HAL_GetTick();
1285
1286 /* Init temporary variables */
1287 tmp_state = hspi->State;
1288 tmp_mode = hspi->Init.Mode;
1289 initial_TxXferCount = Size;
1290 initial_RxXferCount = Size;
1291 #if (USE_SPI_CRC != 0U)
1292 spi_cr1 = READ_REG(hspi->Instance->CR1);
1293 spi_cr2 = READ_REG(hspi->Instance->CR2);
1294 #endif /* USE_SPI_CRC */
1295
1296 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1297 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1298 {
1299 errorcode = HAL_BUSY;
1300 goto error;
1301 }
1302
1303 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1304 {
1305 errorcode = HAL_ERROR;
1306 goto error;
1307 }
1308
1309 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1310 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1311 {
1312 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1313 }
1314
1315 /* Set the transaction information */
1316 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1317 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1318 hspi->RxXferCount = Size;
1319 hspi->RxXferSize = Size;
1320 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1321 hspi->TxXferCount = Size;
1322 hspi->TxXferSize = Size;
1323
1324 /*Init field not used in handle to zero */
1325 hspi->RxISR = NULL;
1326 hspi->TxISR = NULL;
1327
1328 #if (USE_SPI_CRC != 0U)
1329 /* Reset CRC Calculation */
1330 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1331 {
1332 SPI_RESET_CRC(hspi);
1333 }
1334 #endif /* USE_SPI_CRC */
1335
1336 /* Set the Rx Fifo threshold */
1337 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U))
1338 {
1339 /* Set fiforxthreshold according the reception data length: 16bit */
1340 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1341 }
1342 else
1343 {
1344 /* Set fiforxthreshold according the reception data length: 8bit */
1345 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1346 }
1347
1348 /* Check if the SPI is already enabled */
1349 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1350 {
1351 /* Enable SPI peripheral */
1352 __HAL_SPI_ENABLE(hspi);
1353 }
1354
1355 /* Transmit and Receive data in 16 Bit mode */
1356 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1357 {
1358 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1359 {
1360 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1361 hspi->pTxBuffPtr += sizeof(uint16_t);
1362 hspi->TxXferCount--;
1363
1364 #if (USE_SPI_CRC != 0U)
1365 /* Enable CRC Transmission */
1366 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1367 {
1368 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
1369 if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
1370 {
1371 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
1372 }
1373 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1374 }
1375 #endif /* USE_SPI_CRC */
1376
1377 }
1378 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1379 {
1380 /* Check TXE flag */
1381 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1382 {
1383 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1384 hspi->pTxBuffPtr += sizeof(uint16_t);
1385 hspi->TxXferCount--;
1386 /* Next Data is a reception (Rx). Tx not allowed */
1387 txallowed = 0U;
1388
1389 #if (USE_SPI_CRC != 0U)
1390 /* Enable CRC Transmission */
1391 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1392 {
1393 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
1394 if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
1395 {
1396 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
1397 }
1398 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1399 }
1400 #endif /* USE_SPI_CRC */
1401 }
1402
1403 /* Check RXNE flag */
1404 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1405 {
1406 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1407 hspi->pRxBuffPtr += sizeof(uint16_t);
1408 hspi->RxXferCount--;
1409 /* Next Data is a Transmission (Tx). Tx is allowed */
1410 txallowed = 1U;
1411 }
1412 if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
1413 {
1414 errorcode = HAL_TIMEOUT;
1415 hspi->State = HAL_SPI_STATE_READY;
1416 goto error;
1417 }
1418 }
1419 }
1420 /* Transmit and Receive data in 8 Bit mode */
1421 else
1422 {
1423 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1424 {
1425 if (hspi->TxXferCount > 1U)
1426 {
1427 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1428 hspi->pTxBuffPtr += sizeof(uint16_t);
1429 hspi->TxXferCount -= 2U;
1430 }
1431 else
1432 {
1433 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
1434 hspi->pTxBuffPtr++;
1435 hspi->TxXferCount--;
1436
1437 #if (USE_SPI_CRC != 0U)
1438 /* Enable CRC Transmission */
1439 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1440 {
1441 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
1442 if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
1443 {
1444 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
1445 }
1446 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1447 }
1448 #endif /* USE_SPI_CRC */
1449 }
1450 }
1451 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1452 {
1453 /* Check TXE flag */
1454 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1455 {
1456 if (hspi->TxXferCount > 1U)
1457 {
1458 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1459 hspi->pTxBuffPtr += sizeof(uint16_t);
1460 hspi->TxXferCount -= 2U;
1461 }
1462 else
1463 {
1464 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
1465 hspi->pTxBuffPtr++;
1466 hspi->TxXferCount--;
1467 }
1468 /* Next Data is a reception (Rx). Tx not allowed */
1469 txallowed = 0U;
1470
1471 #if (USE_SPI_CRC != 0U)
1472 /* Enable CRC Transmission */
1473 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1474 {
1475 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
1476 if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
1477 {
1478 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
1479 }
1480 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1481 }
1482 #endif /* USE_SPI_CRC */
1483 }
1484
1485 /* Wait until RXNE flag is reset */
1486 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1487 {
1488 if (hspi->RxXferCount > 1U)
1489 {
1490 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1491 hspi->pRxBuffPtr += sizeof(uint16_t);
1492 hspi->RxXferCount -= 2U;
1493 if (hspi->RxXferCount <= 1U)
1494 {
1495 /* Set RX Fifo threshold before to switch on 8 bit data size */
1496 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1497 }
1498 }
1499 else
1500 {
1501 (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1502 hspi->pRxBuffPtr++;
1503 hspi->RxXferCount--;
1504 }
1505 /* Next Data is a Transmission (Tx). Tx is allowed */
1506 txallowed = 1U;
1507 }
1508 if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
1509 {
1510 errorcode = HAL_TIMEOUT;
1511 hspi->State = HAL_SPI_STATE_READY;
1512 goto error;
1513 }
1514 }
1515 }
1516
1517 #if (USE_SPI_CRC != 0U)
1518 /* Read CRC from DR to close CRC calculation process */
1519 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1520 {
1521 /* Wait until TXE flag */
1522 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1523 {
1524 /* Error on the CRC reception */
1525 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1526 errorcode = HAL_TIMEOUT;
1527 goto error;
1528 }
1529 /* Read CRC */
1530 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1531 {
1532 /* Read 16bit CRC */
1533 tmpreg = READ_REG(hspi->Instance->DR);
1534 /* To avoid GCC warning */
1535 UNUSED(tmpreg);
1536 }
1537 else
1538 {
1539 /* Initialize the 8bit temporary pointer */
1540 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
1541 /* Read 8bit CRC */
1542 tmpreg8 = *ptmpreg8;
1543 /* To avoid GCC warning */
1544 UNUSED(tmpreg8);
1545
1546 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
1547 {
1548 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1549 {
1550 /* Error on the CRC reception */
1551 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1552 errorcode = HAL_TIMEOUT;
1553 goto error;
1554 }
1555 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
1556 tmpreg8 = *ptmpreg8;
1557 /* To avoid GCC warning */
1558 UNUSED(tmpreg8);
1559 }
1560 }
1561 }
1562
1563 /* Check if CRC error occurred */
1564 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1565 {
1566 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1567 /* Clear CRC Flag */
1568 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1569
1570 errorcode = HAL_ERROR;
1571 }
1572 #endif /* USE_SPI_CRC */
1573
1574 /* Check the end of the transaction */
1575 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1576 {
1577 errorcode = HAL_ERROR;
1578 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1579 }
1580
1581 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1582 {
1583 errorcode = HAL_ERROR;
1584 }
1585 else
1586 {
1587 hspi->State = HAL_SPI_STATE_READY;
1588 }
1589
1590 error :
1591 __HAL_UNLOCK(hspi);
1592 return errorcode;
1593 }
1594
1595 /**
1596 * @brief Transmit an amount of data in non-blocking mode with Interrupt.
1597 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1598 * the configuration information for SPI module.
1599 * @param pData pointer to data buffer
1600 * @param Size amount of data to be sent
1601 * @retval HAL status
1602 */
HAL_SPI_Transmit_IT(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1603 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1604 {
1605 HAL_StatusTypeDef errorcode = HAL_OK;
1606
1607 /* Check Direction parameter */
1608 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1609
1610
1611 if ((pData == NULL) || (Size == 0U))
1612 {
1613 errorcode = HAL_ERROR;
1614 goto error;
1615 }
1616
1617 if (hspi->State != HAL_SPI_STATE_READY)
1618 {
1619 errorcode = HAL_BUSY;
1620 goto error;
1621 }
1622
1623 /* Process Locked */
1624 __HAL_LOCK(hspi);
1625
1626 /* Set the transaction information */
1627 hspi->State = HAL_SPI_STATE_BUSY_TX;
1628 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1629 hspi->pTxBuffPtr = (uint8_t *)pData;
1630 hspi->TxXferSize = Size;
1631 hspi->TxXferCount = Size;
1632
1633 /* Init field not used in handle to zero */
1634 hspi->pRxBuffPtr = (uint8_t *)NULL;
1635 hspi->RxXferSize = 0U;
1636 hspi->RxXferCount = 0U;
1637 hspi->RxISR = NULL;
1638
1639 /* Set the function for IT treatment */
1640 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1641 {
1642 hspi->TxISR = SPI_TxISR_16BIT;
1643 }
1644 else
1645 {
1646 hspi->TxISR = SPI_TxISR_8BIT;
1647 }
1648
1649 /* Configure communication direction : 1Line */
1650 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1651 {
1652 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1653 __HAL_SPI_DISABLE(hspi);
1654 SPI_1LINE_TX(hspi);
1655 }
1656
1657 #if (USE_SPI_CRC != 0U)
1658 /* Reset CRC Calculation */
1659 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1660 {
1661 SPI_RESET_CRC(hspi);
1662 }
1663 #endif /* USE_SPI_CRC */
1664
1665 /* Check if the SPI is already enabled */
1666 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1667 {
1668 /* Enable SPI peripheral */
1669 __HAL_SPI_ENABLE(hspi);
1670 }
1671
1672 /* Process Unlocked */
1673 __HAL_UNLOCK(hspi);
1674 /* Enable TXE and ERR interrupt */
1675 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
1676
1677 error :
1678 return errorcode;
1679 }
1680
1681 /**
1682 * @brief Receive an amount of data in non-blocking mode with Interrupt.
1683 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1684 * the configuration information for SPI module.
1685 * @param pData pointer to data buffer
1686 * @param Size amount of data to be sent
1687 * @retval HAL status
1688 */
HAL_SPI_Receive_IT(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1689 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1690 {
1691 HAL_StatusTypeDef errorcode = HAL_OK;
1692
1693
1694 if (hspi->State != HAL_SPI_STATE_READY)
1695 {
1696 errorcode = HAL_BUSY;
1697 goto error;
1698 }
1699
1700 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1701 {
1702 hspi->State = HAL_SPI_STATE_BUSY_RX;
1703 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1704 return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
1705 }
1706
1707
1708 if ((pData == NULL) || (Size == 0U))
1709 {
1710 errorcode = HAL_ERROR;
1711 goto error;
1712 }
1713
1714 /* Process Locked */
1715 __HAL_LOCK(hspi);
1716
1717 /* Set the transaction information */
1718 hspi->State = HAL_SPI_STATE_BUSY_RX;
1719 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1720 hspi->pRxBuffPtr = (uint8_t *)pData;
1721 hspi->RxXferSize = Size;
1722 hspi->RxXferCount = Size;
1723
1724 /* Init field not used in handle to zero */
1725 hspi->pTxBuffPtr = (uint8_t *)NULL;
1726 hspi->TxXferSize = 0U;
1727 hspi->TxXferCount = 0U;
1728 hspi->TxISR = NULL;
1729
1730 /* Check the data size to adapt Rx threshold and the set the function for IT treatment */
1731 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1732 {
1733 /* Set RX Fifo threshold according the reception data length: 16 bit */
1734 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1735 hspi->RxISR = SPI_RxISR_16BIT;
1736 }
1737 else
1738 {
1739 /* Set RX Fifo threshold according the reception data length: 8 bit */
1740 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1741 hspi->RxISR = SPI_RxISR_8BIT;
1742 }
1743
1744 /* Configure communication direction : 1Line */
1745 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1746 {
1747 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1748 __HAL_SPI_DISABLE(hspi);
1749 SPI_1LINE_RX(hspi);
1750 }
1751
1752 #if (USE_SPI_CRC != 0U)
1753 /* Reset CRC Calculation */
1754 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1755 {
1756 hspi->CRCSize = 1U;
1757 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1758 {
1759 hspi->CRCSize = 2U;
1760 }
1761 SPI_RESET_CRC(hspi);
1762 }
1763 else
1764 {
1765 hspi->CRCSize = 0U;
1766 }
1767 #endif /* USE_SPI_CRC */
1768
1769 /* Note : The SPI must be enabled after unlocking current process
1770 to avoid the risk of SPI interrupt handle execution before current
1771 process unlock */
1772
1773 /* Check if the SPI is already enabled */
1774 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1775 {
1776 /* Enable SPI peripheral */
1777 __HAL_SPI_ENABLE(hspi);
1778 }
1779
1780 /* Process Unlocked */
1781 __HAL_UNLOCK(hspi);
1782 /* Enable RXNE and ERR interrupt */
1783 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
1784
1785 error :
1786 return errorcode;
1787 }
1788
1789 /**
1790 * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
1791 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1792 * the configuration information for SPI module.
1793 * @param pTxData pointer to transmission data buffer
1794 * @param pRxData pointer to reception data buffer
1795 * @param Size amount of data to be sent and received
1796 * @retval HAL status
1797 */
HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size)1798 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
1799 {
1800 uint32_t tmp_mode;
1801 HAL_SPI_StateTypeDef tmp_state;
1802 HAL_StatusTypeDef errorcode = HAL_OK;
1803
1804 /* Check Direction parameter */
1805 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1806
1807 /* Init temporary variables */
1808 tmp_state = hspi->State;
1809 tmp_mode = hspi->Init.Mode;
1810
1811 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1812 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1813 {
1814 errorcode = HAL_BUSY;
1815 goto error;
1816 }
1817
1818 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1819 {
1820 errorcode = HAL_ERROR;
1821 goto error;
1822 }
1823
1824 /* Process locked */
1825 __HAL_LOCK(hspi);
1826
1827 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1828 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1829 {
1830 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1831 }
1832
1833 /* Set the transaction information */
1834 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1835 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1836 hspi->TxXferSize = Size;
1837 hspi->TxXferCount = Size;
1838 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1839 hspi->RxXferSize = Size;
1840 hspi->RxXferCount = Size;
1841
1842 /* Set the function for IT treatment */
1843 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1844 {
1845 hspi->RxISR = SPI_2linesRxISR_16BIT;
1846 hspi->TxISR = SPI_2linesTxISR_16BIT;
1847 }
1848 else
1849 {
1850 hspi->RxISR = SPI_2linesRxISR_8BIT;
1851 hspi->TxISR = SPI_2linesTxISR_8BIT;
1852 }
1853
1854 #if (USE_SPI_CRC != 0U)
1855 /* Reset CRC Calculation */
1856 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1857 {
1858 hspi->CRCSize = 1U;
1859 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1860 {
1861 hspi->CRCSize = 2U;
1862 }
1863 SPI_RESET_CRC(hspi);
1864 }
1865 else
1866 {
1867 hspi->CRCSize = 0U;
1868 }
1869 #endif /* USE_SPI_CRC */
1870
1871 /* Check if packing mode is enabled and if there is more than 2 data to receive */
1872 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U))
1873 {
1874 /* Set RX Fifo threshold according the reception data length: 16 bit */
1875 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1876 }
1877 else
1878 {
1879 /* Set RX Fifo threshold according the reception data length: 8 bit */
1880 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1881 }
1882
1883
1884 /* Check if the SPI is already enabled */
1885 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1886 {
1887 /* Enable SPI peripheral */
1888 __HAL_SPI_ENABLE(hspi);
1889 }
1890
1891 /* Process Unlocked */
1892 __HAL_UNLOCK(hspi);
1893 /* Enable TXE, RXNE and ERR interrupt */
1894 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
1895
1896 error :
1897 return errorcode;
1898 }
1899
1900 /**
1901 * @brief Transmit an amount of data in non-blocking mode with DMA.
1902 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1903 * the configuration information for SPI module.
1904 * @param pData pointer to data buffer
1905 * @param Size amount of data to be sent
1906 * @retval HAL status
1907 */
HAL_SPI_Transmit_DMA(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1908 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1909 {
1910 HAL_StatusTypeDef errorcode = HAL_OK;
1911
1912 /* Check tx dma handle */
1913 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1914
1915 /* Check Direction parameter */
1916 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1917
1918 /* Process Locked */
1919 __HAL_LOCK(hspi);
1920
1921 if (hspi->State != HAL_SPI_STATE_READY)
1922 {
1923 errorcode = HAL_BUSY;
1924 goto error;
1925 }
1926
1927 if ((pData == NULL) || (Size == 0U))
1928 {
1929 errorcode = HAL_ERROR;
1930 goto error;
1931 }
1932
1933 /* Set the transaction information */
1934 hspi->State = HAL_SPI_STATE_BUSY_TX;
1935 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1936 hspi->pTxBuffPtr = (uint8_t *)pData;
1937 hspi->TxXferSize = Size;
1938 hspi->TxXferCount = Size;
1939
1940 /* Init field not used in handle to zero */
1941 hspi->pRxBuffPtr = (uint8_t *)NULL;
1942 hspi->TxISR = NULL;
1943 hspi->RxISR = NULL;
1944 hspi->RxXferSize = 0U;
1945 hspi->RxXferCount = 0U;
1946
1947 /* Configure communication direction : 1Line */
1948 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1949 {
1950 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1951 __HAL_SPI_DISABLE(hspi);
1952 SPI_1LINE_TX(hspi);
1953 }
1954
1955 #if (USE_SPI_CRC != 0U)
1956 /* Reset CRC Calculation */
1957 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1958 {
1959 SPI_RESET_CRC(hspi);
1960 }
1961 #endif /* USE_SPI_CRC */
1962
1963 /* Set the SPI TxDMA Half transfer complete callback */
1964 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
1965
1966 /* Set the SPI TxDMA transfer complete callback */
1967 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
1968
1969 /* Set the DMA error callback */
1970 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
1971
1972 /* Set the DMA AbortCpltCallback */
1973 hspi->hdmatx->XferAbortCallback = NULL;
1974
1975 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1976 /* Packing mode is enabled only if the DMA setting is HALWORD */
1977 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
1978 {
1979 /* Check the even/odd of the data size + crc if enabled */
1980 if ((hspi->TxXferCount & 0x1U) == 0U)
1981 {
1982 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1983 hspi->TxXferCount = (hspi->TxXferCount >> 1U);
1984 }
1985 else
1986 {
1987 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1988 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
1989 }
1990 }
1991
1992 /* Enable the Tx DMA Stream/Channel */
1993 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
1994 hspi->TxXferCount))
1995 {
1996 /* Update SPI error code */
1997 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
1998 errorcode = HAL_ERROR;
1999
2000 goto error;
2001 }
2002
2003 /* Check if the SPI is already enabled */
2004 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
2005 {
2006 /* Enable SPI peripheral */
2007 __HAL_SPI_ENABLE(hspi);
2008 }
2009
2010 /* Enable the SPI Error Interrupt Bit */
2011 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
2012
2013 /* Enable Tx DMA Request */
2014 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2015
2016 error :
2017 /* Process Unlocked */
2018 __HAL_UNLOCK(hspi);
2019 return errorcode;
2020 }
2021
2022 /**
2023 * @brief Receive an amount of data in non-blocking mode with DMA.
2024 * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
2025 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2026 * the configuration information for SPI module.
2027 * @param pData pointer to data buffer
2028 * @note When the CRC feature is enabled the pData Length must be Size + 1.
2029 * @param Size amount of data to be sent
2030 * @retval HAL status
2031 */
HAL_SPI_Receive_DMA(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)2032 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
2033 {
2034 HAL_StatusTypeDef errorcode = HAL_OK;
2035
2036 /* Check rx dma handle */
2037 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
2038
2039 if (hspi->State != HAL_SPI_STATE_READY)
2040 {
2041 errorcode = HAL_BUSY;
2042 goto error;
2043 }
2044
2045 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
2046 {
2047 hspi->State = HAL_SPI_STATE_BUSY_RX;
2048
2049 /* Check tx dma handle */
2050 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
2051
2052 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
2053 return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
2054 }
2055
2056 /* Process Locked */
2057 __HAL_LOCK(hspi);
2058
2059 if ((pData == NULL) || (Size == 0U))
2060 {
2061 errorcode = HAL_ERROR;
2062 goto error;
2063 }
2064
2065 /* Set the transaction information */
2066 hspi->State = HAL_SPI_STATE_BUSY_RX;
2067 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2068 hspi->pRxBuffPtr = (uint8_t *)pData;
2069 hspi->RxXferSize = Size;
2070 hspi->RxXferCount = Size;
2071
2072 /*Init field not used in handle to zero */
2073 hspi->RxISR = NULL;
2074 hspi->TxISR = NULL;
2075 hspi->TxXferSize = 0U;
2076 hspi->TxXferCount = 0U;
2077
2078 /* Configure communication direction : 1Line */
2079 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
2080 {
2081 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
2082 __HAL_SPI_DISABLE(hspi);
2083 SPI_1LINE_RX(hspi);
2084 }
2085
2086 #if (USE_SPI_CRC != 0U)
2087 /* Reset CRC Calculation */
2088 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2089 {
2090 SPI_RESET_CRC(hspi);
2091 }
2092 #endif /* USE_SPI_CRC */
2093
2094
2095 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2096 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
2097 {
2098 /* Set RX Fifo threshold according the reception data length: 16bit */
2099 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2100 }
2101 else
2102 {
2103 /* Set RX Fifo threshold according the reception data length: 8bit */
2104 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2105
2106 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2107 {
2108 /* Set RX Fifo threshold according the reception data length: 16bit */
2109 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2110
2111 if ((hspi->RxXferCount & 0x1U) == 0x0U)
2112 {
2113 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2114 hspi->RxXferCount = hspi->RxXferCount >> 1U;
2115 }
2116 else
2117 {
2118 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2119 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
2120 }
2121 }
2122 }
2123
2124 /* Set the SPI RxDMA Half transfer complete callback */
2125 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
2126
2127 /* Set the SPI Rx DMA transfer complete callback */
2128 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
2129
2130 /* Set the DMA error callback */
2131 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
2132
2133 /* Set the DMA AbortCpltCallback */
2134 hspi->hdmarx->XferAbortCallback = NULL;
2135
2136 /* Enable the Rx DMA Stream/Channel */
2137 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
2138 hspi->RxXferCount))
2139 {
2140 /* Update SPI error code */
2141 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2142 errorcode = HAL_ERROR;
2143
2144 goto error;
2145 }
2146
2147 /* Check if the SPI is already enabled */
2148 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
2149 {
2150 /* Enable SPI peripheral */
2151 __HAL_SPI_ENABLE(hspi);
2152 }
2153
2154 /* Enable the SPI Error Interrupt Bit */
2155 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
2156
2157 /* Enable Rx DMA Request */
2158 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2159
2160 error:
2161 /* Process Unlocked */
2162 __HAL_UNLOCK(hspi);
2163 return errorcode;
2164 }
2165
2166 /**
2167 * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
2168 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2169 * the configuration information for SPI module.
2170 * @param pTxData pointer to transmission data buffer
2171 * @param pRxData pointer to reception data buffer
2172 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
2173 * @param Size amount of data to be sent
2174 * @retval HAL status
2175 */
HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size)2176 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
2177 uint16_t Size)
2178 {
2179 uint32_t tmp_mode;
2180 HAL_SPI_StateTypeDef tmp_state;
2181 HAL_StatusTypeDef errorcode = HAL_OK;
2182
2183 /* Check rx & tx dma handles */
2184 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
2185 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
2186
2187 /* Check Direction parameter */
2188 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
2189
2190 /* Process locked */
2191 __HAL_LOCK(hspi);
2192
2193 /* Init temporary variables */
2194 tmp_state = hspi->State;
2195 tmp_mode = hspi->Init.Mode;
2196
2197 if (!((tmp_state == HAL_SPI_STATE_READY) ||
2198 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
2199 {
2200 errorcode = HAL_BUSY;
2201 goto error;
2202 }
2203
2204 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
2205 {
2206 errorcode = HAL_ERROR;
2207 goto error;
2208 }
2209
2210 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
2211 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
2212 {
2213 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
2214 }
2215
2216 /* Set the transaction information */
2217 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2218 hspi->pTxBuffPtr = (uint8_t *)pTxData;
2219 hspi->TxXferSize = Size;
2220 hspi->TxXferCount = Size;
2221 hspi->pRxBuffPtr = (uint8_t *)pRxData;
2222 hspi->RxXferSize = Size;
2223 hspi->RxXferCount = Size;
2224
2225 /* Init field not used in handle to zero */
2226 hspi->RxISR = NULL;
2227 hspi->TxISR = NULL;
2228
2229 #if (USE_SPI_CRC != 0U)
2230 /* Reset CRC Calculation */
2231 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2232 {
2233 SPI_RESET_CRC(hspi);
2234 }
2235 #endif /* USE_SPI_CRC */
2236
2237 /* Reset the threshold bit */
2238 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
2239
2240 /* The packing mode management is enabled by the DMA settings according the spi data size */
2241 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
2242 {
2243 /* Set fiforxthreshold according the reception data length: 16bit */
2244 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2245 }
2246 else
2247 {
2248 /* Set RX Fifo threshold according the reception data length: 8bit */
2249 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2250
2251 if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2252 {
2253 if ((hspi->TxXferSize & 0x1U) == 0x0U)
2254 {
2255 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
2256 hspi->TxXferCount = hspi->TxXferCount >> 1U;
2257 }
2258 else
2259 {
2260 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
2261 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
2262 }
2263 }
2264
2265 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2266 {
2267 /* Set RX Fifo threshold according the reception data length: 16bit */
2268 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2269
2270 if ((hspi->RxXferCount & 0x1U) == 0x0U)
2271 {
2272 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2273 hspi->RxXferCount = hspi->RxXferCount >> 1U;
2274 }
2275 else
2276 {
2277 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2278 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
2279 }
2280 }
2281 }
2282
2283 /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
2284 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
2285 {
2286 /* Set the SPI Rx DMA Half transfer complete callback */
2287 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
2288 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
2289 }
2290 else
2291 {
2292 /* Set the SPI Tx/Rx DMA Half transfer complete callback */
2293 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
2294 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
2295 }
2296
2297 /* Set the DMA error callback */
2298 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
2299
2300 /* Set the DMA AbortCpltCallback */
2301 hspi->hdmarx->XferAbortCallback = NULL;
2302
2303 /* Enable the Rx DMA Stream/Channel */
2304 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
2305 hspi->RxXferCount))
2306 {
2307 /* Update SPI error code */
2308 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2309 errorcode = HAL_ERROR;
2310
2311 goto error;
2312 }
2313
2314 /* Enable Rx DMA Request */
2315 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2316
2317 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
2318 is performed in DMA reception complete callback */
2319 hspi->hdmatx->XferHalfCpltCallback = NULL;
2320 hspi->hdmatx->XferCpltCallback = NULL;
2321 hspi->hdmatx->XferErrorCallback = NULL;
2322 hspi->hdmatx->XferAbortCallback = NULL;
2323
2324 /* Enable the Tx DMA Stream/Channel */
2325 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
2326 hspi->TxXferCount))
2327 {
2328 /* Update SPI error code */
2329 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2330 errorcode = HAL_ERROR;
2331
2332 goto error;
2333 }
2334
2335 /* Check if the SPI is already enabled */
2336 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
2337 {
2338 /* Enable SPI peripheral */
2339 __HAL_SPI_ENABLE(hspi);
2340 }
2341 /* Enable the SPI Error Interrupt Bit */
2342 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
2343
2344 /* Enable Tx DMA Request */
2345 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2346
2347 error :
2348 /* Process Unlocked */
2349 __HAL_UNLOCK(hspi);
2350 return errorcode;
2351 }
2352
2353 /**
2354 * @brief Abort ongoing transfer (blocking mode).
2355 * @param hspi SPI handle.
2356 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2357 * started in Interrupt or DMA mode.
2358 * This procedure performs following operations :
2359 * - Disable SPI Interrupts (depending of transfer direction)
2360 * - Disable the DMA transfer in the peripheral register (if enabled)
2361 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
2362 * - Set handle State to READY
2363 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
2364 * @retval HAL status
2365 */
HAL_SPI_Abort(SPI_HandleTypeDef * hspi)2366 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
2367 {
2368 HAL_StatusTypeDef errorcode;
2369 __IO uint32_t count;
2370 __IO uint32_t resetcount;
2371
2372 /* Initialized local variable */
2373 errorcode = HAL_OK;
2374 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2375 count = resetcount;
2376
2377 /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
2378 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2379
2380 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
2381 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2382 {
2383 hspi->TxISR = SPI_AbortTx_ISR;
2384 /* Wait HAL_SPI_STATE_ABORT state */
2385 do
2386 {
2387 if (count == 0U)
2388 {
2389 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2390 break;
2391 }
2392 count--;
2393 } while (hspi->State != HAL_SPI_STATE_ABORT);
2394 /* Reset Timeout Counter */
2395 count = resetcount;
2396 }
2397
2398 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2399 {
2400 hspi->RxISR = SPI_AbortRx_ISR;
2401 /* Wait HAL_SPI_STATE_ABORT state */
2402 do
2403 {
2404 if (count == 0U)
2405 {
2406 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2407 break;
2408 }
2409 count--;
2410 } while (hspi->State != HAL_SPI_STATE_ABORT);
2411 /* Reset Timeout Counter */
2412 count = resetcount;
2413 }
2414
2415 /* Disable the SPI DMA Tx request if enabled */
2416 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2417 {
2418 /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
2419 if (hspi->hdmatx != NULL)
2420 {
2421 /* Set the SPI DMA Abort callback :
2422 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2423 hspi->hdmatx->XferAbortCallback = NULL;
2424
2425 /* Abort DMA Tx Handle linked to SPI Peripheral */
2426 if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
2427 {
2428 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2429 }
2430
2431 /* Disable Tx DMA Request */
2432 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
2433
2434 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2435 {
2436 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2437 }
2438
2439 /* Disable SPI Peripheral */
2440 __HAL_SPI_DISABLE(hspi);
2441
2442 /* Empty the FRLVL fifo */
2443 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2444 {
2445 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2446 }
2447 }
2448 }
2449
2450 /* Disable the SPI DMA Rx request if enabled */
2451 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2452 {
2453 /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
2454 if (hspi->hdmarx != NULL)
2455 {
2456 /* Set the SPI DMA Abort callback :
2457 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2458 hspi->hdmarx->XferAbortCallback = NULL;
2459
2460 /* Abort DMA Rx Handle linked to SPI Peripheral */
2461 if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
2462 {
2463 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2464 }
2465
2466 /* Disable peripheral */
2467 __HAL_SPI_DISABLE(hspi);
2468
2469 /* Control the BSY flag */
2470 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2471 {
2472 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2473 }
2474
2475 /* Empty the FRLVL fifo */
2476 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2477 {
2478 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2479 }
2480
2481 /* Disable Rx DMA Request */
2482 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
2483 }
2484 }
2485 /* Reset Tx and Rx transfer counters */
2486 hspi->RxXferCount = 0U;
2487 hspi->TxXferCount = 0U;
2488
2489 /* Check error during Abort procedure */
2490 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2491 {
2492 /* return HAL_Error in case of error during Abort procedure */
2493 errorcode = HAL_ERROR;
2494 }
2495 else
2496 {
2497 /* Reset errorCode */
2498 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2499 }
2500
2501 /* Clear the Error flags in the SR register */
2502 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2503 __HAL_SPI_CLEAR_FREFLAG(hspi);
2504
2505 /* Restore hspi->state to ready */
2506 hspi->State = HAL_SPI_STATE_READY;
2507
2508 return errorcode;
2509 }
2510
2511 /**
2512 * @brief Abort ongoing transfer (Interrupt mode).
2513 * @param hspi SPI handle.
2514 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2515 * started in Interrupt or DMA mode.
2516 * This procedure performs following operations :
2517 * - Disable SPI Interrupts (depending of transfer direction)
2518 * - Disable the DMA transfer in the peripheral register (if enabled)
2519 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
2520 * - Set handle State to READY
2521 * - At abort completion, call user abort complete callback
2522 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
2523 * considered as completed only when user abort complete callback is executed (not when exiting function).
2524 * @retval HAL status
2525 */
HAL_SPI_Abort_IT(SPI_HandleTypeDef * hspi)2526 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
2527 {
2528 HAL_StatusTypeDef errorcode;
2529 uint32_t abortcplt ;
2530 __IO uint32_t count;
2531 __IO uint32_t resetcount;
2532
2533 /* Initialized local variable */
2534 errorcode = HAL_OK;
2535 abortcplt = 1U;
2536 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2537 count = resetcount;
2538
2539 /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
2540 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2541
2542 /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
2543 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2544 {
2545 hspi->TxISR = SPI_AbortTx_ISR;
2546 /* Wait HAL_SPI_STATE_ABORT state */
2547 do
2548 {
2549 if (count == 0U)
2550 {
2551 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2552 break;
2553 }
2554 count--;
2555 } while (hspi->State != HAL_SPI_STATE_ABORT);
2556 /* Reset Timeout Counter */
2557 count = resetcount;
2558 }
2559
2560 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2561 {
2562 hspi->RxISR = SPI_AbortRx_ISR;
2563 /* Wait HAL_SPI_STATE_ABORT state */
2564 do
2565 {
2566 if (count == 0U)
2567 {
2568 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2569 break;
2570 }
2571 count--;
2572 } while (hspi->State != HAL_SPI_STATE_ABORT);
2573 /* Reset Timeout Counter */
2574 count = resetcount;
2575 }
2576
2577 /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
2578 before any call to DMA Abort functions */
2579 /* DMA Tx Handle is valid */
2580 if (hspi->hdmatx != NULL)
2581 {
2582 /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
2583 Otherwise, set it to NULL */
2584 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2585 {
2586 hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
2587 }
2588 else
2589 {
2590 hspi->hdmatx->XferAbortCallback = NULL;
2591 }
2592 }
2593 /* DMA Rx Handle is valid */
2594 if (hspi->hdmarx != NULL)
2595 {
2596 /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
2597 Otherwise, set it to NULL */
2598 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2599 {
2600 hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
2601 }
2602 else
2603 {
2604 hspi->hdmarx->XferAbortCallback = NULL;
2605 }
2606 }
2607
2608 /* Disable the SPI DMA Tx request if enabled */
2609 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2610 {
2611 /* Abort the SPI DMA Tx Stream/Channel */
2612 if (hspi->hdmatx != NULL)
2613 {
2614 /* Abort DMA Tx Handle linked to SPI Peripheral */
2615 if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
2616 {
2617 hspi->hdmatx->XferAbortCallback = NULL;
2618 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2619 }
2620 else
2621 {
2622 abortcplt = 0U;
2623 }
2624 }
2625 }
2626 /* Disable the SPI DMA Rx request if enabled */
2627 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2628 {
2629 /* Abort the SPI DMA Rx Stream/Channel */
2630 if (hspi->hdmarx != NULL)
2631 {
2632 /* Abort DMA Rx Handle linked to SPI Peripheral */
2633 if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
2634 {
2635 hspi->hdmarx->XferAbortCallback = NULL;
2636 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2637 }
2638 else
2639 {
2640 abortcplt = 0U;
2641 }
2642 }
2643 }
2644
2645 if (abortcplt == 1U)
2646 {
2647 /* Reset Tx and Rx transfer counters */
2648 hspi->RxXferCount = 0U;
2649 hspi->TxXferCount = 0U;
2650
2651 /* Check error during Abort procedure */
2652 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2653 {
2654 /* return HAL_Error in case of error during Abort procedure */
2655 errorcode = HAL_ERROR;
2656 }
2657 else
2658 {
2659 /* Reset errorCode */
2660 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2661 }
2662
2663 /* Clear the Error flags in the SR register */
2664 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2665 __HAL_SPI_CLEAR_FREFLAG(hspi);
2666
2667 /* Restore hspi->State to Ready */
2668 hspi->State = HAL_SPI_STATE_READY;
2669
2670 /* As no DMA to be aborted, call directly user Abort complete callback */
2671 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2672 hspi->AbortCpltCallback(hspi);
2673 #else
2674 HAL_SPI_AbortCpltCallback(hspi);
2675 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2676 }
2677
2678 return errorcode;
2679 }
2680
2681 /**
2682 * @brief Pause the DMA Transfer.
2683 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2684 * the configuration information for the specified SPI module.
2685 * @retval HAL status
2686 */
HAL_SPI_DMAPause(SPI_HandleTypeDef * hspi)2687 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
2688 {
2689 /* Process Locked */
2690 __HAL_LOCK(hspi);
2691
2692 /* Disable the SPI DMA Tx & Rx requests */
2693 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2694
2695 /* Process Unlocked */
2696 __HAL_UNLOCK(hspi);
2697
2698 return HAL_OK;
2699 }
2700
2701 /**
2702 * @brief Resume the DMA Transfer.
2703 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2704 * the configuration information for the specified SPI module.
2705 * @retval HAL status
2706 */
HAL_SPI_DMAResume(SPI_HandleTypeDef * hspi)2707 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
2708 {
2709 /* Process Locked */
2710 __HAL_LOCK(hspi);
2711
2712 /* Enable the SPI DMA Tx & Rx requests */
2713 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2714
2715 /* Process Unlocked */
2716 __HAL_UNLOCK(hspi);
2717
2718 return HAL_OK;
2719 }
2720
2721 /**
2722 * @brief Stop the DMA Transfer.
2723 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2724 * the configuration information for the specified SPI module.
2725 * @retval HAL status
2726 */
HAL_SPI_DMAStop(SPI_HandleTypeDef * hspi)2727 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
2728 {
2729 HAL_StatusTypeDef errorcode = HAL_OK;
2730 /* The Lock is not implemented on this API to allow the user application
2731 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
2732 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
2733 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
2734 */
2735
2736 /* Abort the SPI DMA tx Stream/Channel */
2737 if (hspi->hdmatx != NULL)
2738 {
2739 if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
2740 {
2741 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2742 errorcode = HAL_ERROR;
2743 }
2744 }
2745 /* Abort the SPI DMA rx Stream/Channel */
2746 if (hspi->hdmarx != NULL)
2747 {
2748 if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
2749 {
2750 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2751 errorcode = HAL_ERROR;
2752 }
2753 }
2754
2755 /* Disable the SPI DMA Tx & Rx requests */
2756 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2757 hspi->State = HAL_SPI_STATE_READY;
2758 return errorcode;
2759 }
2760
2761 /**
2762 * @brief Handle SPI interrupt request.
2763 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2764 * the configuration information for the specified SPI module.
2765 * @retval None
2766 */
HAL_SPI_IRQHandler(SPI_HandleTypeDef * hspi)2767 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
2768 {
2769 uint32_t itsource = hspi->Instance->CR2;
2770 uint32_t itflag = hspi->Instance->SR;
2771
2772 /* SPI in mode Receiver ----------------------------------------------------*/
2773 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
2774 (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
2775 {
2776 hspi->RxISR(hspi);
2777 return;
2778 }
2779
2780 /* SPI in mode Transmitter -------------------------------------------------*/
2781 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
2782 {
2783 hspi->TxISR(hspi);
2784 return;
2785 }
2786
2787 /* SPI in Error Treatment --------------------------------------------------*/
2788 if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
2789 || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
2790 {
2791 /* SPI Overrun error interrupt occurred ----------------------------------*/
2792 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
2793 {
2794 if (hspi->State != HAL_SPI_STATE_BUSY_TX)
2795 {
2796 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
2797 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2798 }
2799 else
2800 {
2801 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2802 return;
2803 }
2804 }
2805
2806 /* SPI Mode Fault error interrupt occurred -------------------------------*/
2807 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
2808 {
2809 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
2810 __HAL_SPI_CLEAR_MODFFLAG(hspi);
2811 }
2812
2813 /* SPI Frame error interrupt occurred ------------------------------------*/
2814 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
2815 {
2816 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
2817 __HAL_SPI_CLEAR_FREFLAG(hspi);
2818 }
2819
2820 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2821 {
2822 /* Disable all interrupts */
2823 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
2824
2825 hspi->State = HAL_SPI_STATE_READY;
2826 /* Disable the SPI DMA requests if enabled */
2827 if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
2828 {
2829 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
2830
2831 /* Abort the SPI DMA Rx channel */
2832 if (hspi->hdmarx != NULL)
2833 {
2834 /* Set the SPI DMA Abort callback :
2835 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2836 hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
2837 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
2838 {
2839 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2840 }
2841 }
2842 /* Abort the SPI DMA Tx channel */
2843 if (hspi->hdmatx != NULL)
2844 {
2845 /* Set the SPI DMA Abort callback :
2846 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2847 hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
2848 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
2849 {
2850 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2851 }
2852 }
2853 }
2854 else
2855 {
2856 /* Call user error callback */
2857 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2858 hspi->ErrorCallback(hspi);
2859 #else
2860 HAL_SPI_ErrorCallback(hspi);
2861 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2862 }
2863 }
2864 return;
2865 }
2866 }
2867
2868 /**
2869 * @brief Tx Transfer completed callback.
2870 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2871 * the configuration information for SPI module.
2872 * @retval None
2873 */
HAL_SPI_TxCpltCallback(SPI_HandleTypeDef * hspi)2874 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
2875 {
2876 /* Prevent unused argument(s) compilation warning */
2877 UNUSED(hspi);
2878
2879 /* NOTE : This function should not be modified, when the callback is needed,
2880 the HAL_SPI_TxCpltCallback should be implemented in the user file
2881 */
2882 }
2883
2884 /**
2885 * @brief Rx Transfer completed callback.
2886 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2887 * the configuration information for SPI module.
2888 * @retval None
2889 */
HAL_SPI_RxCpltCallback(SPI_HandleTypeDef * hspi)2890 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
2891 {
2892 /* Prevent unused argument(s) compilation warning */
2893 UNUSED(hspi);
2894
2895 /* NOTE : This function should not be modified, when the callback is needed,
2896 the HAL_SPI_RxCpltCallback should be implemented in the user file
2897 */
2898 }
2899
2900 /**
2901 * @brief Tx and Rx Transfer completed callback.
2902 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2903 * the configuration information for SPI module.
2904 * @retval None
2905 */
HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef * hspi)2906 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
2907 {
2908 /* Prevent unused argument(s) compilation warning */
2909 UNUSED(hspi);
2910
2911 /* NOTE : This function should not be modified, when the callback is needed,
2912 the HAL_SPI_TxRxCpltCallback should be implemented in the user file
2913 */
2914 }
2915
2916 /**
2917 * @brief Tx Half Transfer completed callback.
2918 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2919 * the configuration information for SPI module.
2920 * @retval None
2921 */
HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef * hspi)2922 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2923 {
2924 /* Prevent unused argument(s) compilation warning */
2925 UNUSED(hspi);
2926
2927 /* NOTE : This function should not be modified, when the callback is needed,
2928 the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
2929 */
2930 }
2931
2932 /**
2933 * @brief Rx Half Transfer completed callback.
2934 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2935 * the configuration information for SPI module.
2936 * @retval None
2937 */
HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef * hspi)2938 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2939 {
2940 /* Prevent unused argument(s) compilation warning */
2941 UNUSED(hspi);
2942
2943 /* NOTE : This function should not be modified, when the callback is needed,
2944 the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
2945 */
2946 }
2947
2948 /**
2949 * @brief Tx and Rx Half Transfer callback.
2950 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2951 * the configuration information for SPI module.
2952 * @retval None
2953 */
HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef * hspi)2954 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2955 {
2956 /* Prevent unused argument(s) compilation warning */
2957 UNUSED(hspi);
2958
2959 /* NOTE : This function should not be modified, when the callback is needed,
2960 the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
2961 */
2962 }
2963
2964 /**
2965 * @brief SPI error callback.
2966 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2967 * the configuration information for SPI module.
2968 * @retval None
2969 */
HAL_SPI_ErrorCallback(SPI_HandleTypeDef * hspi)2970 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
2971 {
2972 /* Prevent unused argument(s) compilation warning */
2973 UNUSED(hspi);
2974
2975 /* NOTE : This function should not be modified, when the callback is needed,
2976 the HAL_SPI_ErrorCallback should be implemented in the user file
2977 */
2978 /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
2979 and user can use HAL_SPI_GetError() API to check the latest error occurred
2980 */
2981 }
2982
2983 /**
2984 * @brief SPI Abort Complete callback.
2985 * @param hspi SPI handle.
2986 * @retval None
2987 */
HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef * hspi)2988 __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
2989 {
2990 /* Prevent unused argument(s) compilation warning */
2991 UNUSED(hspi);
2992
2993 /* NOTE : This function should not be modified, when the callback is needed,
2994 the HAL_SPI_AbortCpltCallback can be implemented in the user file.
2995 */
2996 }
2997
2998 /**
2999 * @}
3000 */
3001
3002 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
3003 * @brief SPI control functions
3004 *
3005 @verbatim
3006 ===============================================================================
3007 ##### Peripheral State and Errors functions #####
3008 ===============================================================================
3009 [..]
3010 This subsection provides a set of functions allowing to control the SPI.
3011 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
3012 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
3013 @endverbatim
3014 * @{
3015 */
3016
3017 /**
3018 * @brief Return the SPI handle state.
3019 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3020 * the configuration information for SPI module.
3021 * @retval SPI state
3022 */
HAL_SPI_GetState(SPI_HandleTypeDef * hspi)3023 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
3024 {
3025 /* Return SPI handle state */
3026 return hspi->State;
3027 }
3028
3029 /**
3030 * @brief Return the SPI error code.
3031 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3032 * the configuration information for SPI module.
3033 * @retval SPI error code in bitmap format
3034 */
HAL_SPI_GetError(SPI_HandleTypeDef * hspi)3035 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
3036 {
3037 /* Return SPI ErrorCode */
3038 return hspi->ErrorCode;
3039 }
3040
3041 /**
3042 * @}
3043 */
3044
3045 /**
3046 * @}
3047 */
3048
3049 /** @addtogroup SPI_Private_Functions
3050 * @brief Private functions
3051 * @{
3052 */
3053
3054 /**
3055 * @brief DMA SPI transmit process complete callback.
3056 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3057 * the configuration information for the specified DMA module.
3058 * @retval None
3059 */
SPI_DMATransmitCplt(DMA_HandleTypeDef * hdma)3060 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
3061 {
3062 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3063 uint32_t tickstart;
3064
3065 /* Init tickstart for timeout management*/
3066 tickstart = HAL_GetTick();
3067
3068 /* DMA Normal Mode */
3069 if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
3070 {
3071 /* Disable ERR interrupt */
3072 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3073
3074 /* Disable Tx DMA Request */
3075 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
3076
3077 /* Check the end of the transaction */
3078 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3079 {
3080 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3081 }
3082
3083 /* Clear overrun flag in 2 Lines communication mode because received data is not read */
3084 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
3085 {
3086 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3087 }
3088
3089 hspi->TxXferCount = 0U;
3090 hspi->State = HAL_SPI_STATE_READY;
3091
3092 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3093 {
3094 /* Call user error callback */
3095 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3096 hspi->ErrorCallback(hspi);
3097 #else
3098 HAL_SPI_ErrorCallback(hspi);
3099 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3100 return;
3101 }
3102 }
3103 /* Call user Tx complete callback */
3104 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3105 hspi->TxCpltCallback(hspi);
3106 #else
3107 HAL_SPI_TxCpltCallback(hspi);
3108 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3109 }
3110
3111 /**
3112 * @brief DMA SPI receive process complete callback.
3113 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3114 * the configuration information for the specified DMA module.
3115 * @retval None
3116 */
SPI_DMAReceiveCplt(DMA_HandleTypeDef * hdma)3117 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
3118 {
3119 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3120 uint32_t tickstart;
3121 #if (USE_SPI_CRC != 0U)
3122 __IO uint32_t tmpreg = 0U;
3123 __IO uint8_t *ptmpreg8;
3124 __IO uint8_t tmpreg8 = 0;
3125 #endif /* USE_SPI_CRC */
3126
3127 /* Init tickstart for timeout management*/
3128 tickstart = HAL_GetTick();
3129
3130 /* DMA Normal Mode */
3131 if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
3132 {
3133 /* Disable ERR interrupt */
3134 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3135
3136 #if (USE_SPI_CRC != 0U)
3137 /* CRC handling */
3138 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3139 {
3140 /* Wait until RXNE flag */
3141 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3142 {
3143 /* Error on the CRC reception */
3144 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3145 }
3146 /* Read CRC */
3147 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
3148 {
3149 /* Read 16bit CRC */
3150 tmpreg = READ_REG(hspi->Instance->DR);
3151 /* To avoid GCC warning */
3152 UNUSED(tmpreg);
3153 }
3154 else
3155 {
3156 /* Initialize the 8bit temporary pointer */
3157 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3158 /* Read 8bit CRC */
3159 tmpreg8 = *ptmpreg8;
3160 /* To avoid GCC warning */
3161 UNUSED(tmpreg8);
3162
3163 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
3164 {
3165 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3166 {
3167 /* Error on the CRC reception */
3168 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3169 }
3170 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
3171 tmpreg8 = *ptmpreg8;
3172 /* To avoid GCC warning */
3173 UNUSED(tmpreg8);
3174 }
3175 }
3176 }
3177 #endif /* USE_SPI_CRC */
3178
3179 /* Check if we are in Master RX 2 line mode */
3180 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
3181 {
3182 /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
3183 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3184 }
3185 else
3186 {
3187 /* Normal case */
3188 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
3189 }
3190
3191 /* Check the end of the transaction */
3192 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3193 {
3194 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
3195 }
3196
3197 hspi->RxXferCount = 0U;
3198 hspi->State = HAL_SPI_STATE_READY;
3199
3200 #if (USE_SPI_CRC != 0U)
3201 /* Check if CRC error occurred */
3202 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
3203 {
3204 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3205 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3206 }
3207 #endif /* USE_SPI_CRC */
3208
3209 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3210 {
3211 /* Call user error callback */
3212 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3213 hspi->ErrorCallback(hspi);
3214 #else
3215 HAL_SPI_ErrorCallback(hspi);
3216 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3217 return;
3218 }
3219 }
3220 /* Call user Rx complete callback */
3221 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3222 hspi->RxCpltCallback(hspi);
3223 #else
3224 HAL_SPI_RxCpltCallback(hspi);
3225 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3226 }
3227
3228 /**
3229 * @brief DMA SPI transmit receive process complete callback.
3230 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3231 * the configuration information for the specified DMA module.
3232 * @retval None
3233 */
SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef * hdma)3234 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
3235 {
3236 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3237 uint32_t tickstart;
3238 #if (USE_SPI_CRC != 0U)
3239 __IO uint32_t tmpreg = 0U;
3240 __IO uint8_t *ptmpreg8;
3241 __IO uint8_t tmpreg8 = 0;
3242 #endif /* USE_SPI_CRC */
3243
3244 /* Init tickstart for timeout management*/
3245 tickstart = HAL_GetTick();
3246
3247 /* DMA Normal Mode */
3248 if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
3249 {
3250 /* Disable ERR interrupt */
3251 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3252
3253 #if (USE_SPI_CRC != 0U)
3254 /* CRC handling */
3255 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3256 {
3257 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
3258 {
3259 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
3260 tickstart) != HAL_OK)
3261 {
3262 /* Error on the CRC reception */
3263 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3264 }
3265 /* Initialize the 8bit temporary pointer */
3266 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3267 /* Read 8bit CRC */
3268 tmpreg8 = *ptmpreg8;
3269 /* To avoid GCC warning */
3270 UNUSED(tmpreg8);
3271 }
3272 else
3273 {
3274 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3275 {
3276 /* Error on the CRC reception */
3277 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3278 }
3279 /* Read CRC to Flush DR and RXNE flag */
3280 tmpreg = READ_REG(hspi->Instance->DR);
3281 /* To avoid GCC warning */
3282 UNUSED(tmpreg);
3283 }
3284 }
3285 #endif /* USE_SPI_CRC */
3286
3287 /* Check the end of the transaction */
3288 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3289 {
3290 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3291 }
3292
3293 /* Disable Rx/Tx DMA Request */
3294 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3295
3296 hspi->TxXferCount = 0U;
3297 hspi->RxXferCount = 0U;
3298 hspi->State = HAL_SPI_STATE_READY;
3299
3300 #if (USE_SPI_CRC != 0U)
3301 /* Check if CRC error occurred */
3302 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
3303 {
3304 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3305 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3306 }
3307 #endif /* USE_SPI_CRC */
3308
3309 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3310 {
3311 /* Call user error callback */
3312 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3313 hspi->ErrorCallback(hspi);
3314 #else
3315 HAL_SPI_ErrorCallback(hspi);
3316 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3317 return;
3318 }
3319 }
3320 /* Call user TxRx complete callback */
3321 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3322 hspi->TxRxCpltCallback(hspi);
3323 #else
3324 HAL_SPI_TxRxCpltCallback(hspi);
3325 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3326 }
3327
3328 /**
3329 * @brief DMA SPI half transmit process complete callback.
3330 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3331 * the configuration information for the specified DMA module.
3332 * @retval None
3333 */
SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef * hdma)3334 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
3335 {
3336 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3337
3338 /* Call user Tx half complete callback */
3339 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3340 hspi->TxHalfCpltCallback(hspi);
3341 #else
3342 HAL_SPI_TxHalfCpltCallback(hspi);
3343 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3344 }
3345
3346 /**
3347 * @brief DMA SPI half receive process complete callback
3348 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3349 * the configuration information for the specified DMA module.
3350 * @retval None
3351 */
SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef * hdma)3352 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
3353 {
3354 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3355
3356 /* Call user Rx half complete callback */
3357 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3358 hspi->RxHalfCpltCallback(hspi);
3359 #else
3360 HAL_SPI_RxHalfCpltCallback(hspi);
3361 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3362 }
3363
3364 /**
3365 * @brief DMA SPI half transmit receive process complete callback.
3366 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3367 * the configuration information for the specified DMA module.
3368 * @retval None
3369 */
SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef * hdma)3370 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
3371 {
3372 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3373
3374 /* Call user TxRx half complete callback */
3375 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3376 hspi->TxRxHalfCpltCallback(hspi);
3377 #else
3378 HAL_SPI_TxRxHalfCpltCallback(hspi);
3379 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3380 }
3381
3382 /**
3383 * @brief DMA SPI communication error callback.
3384 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3385 * the configuration information for the specified DMA module.
3386 * @retval None
3387 */
SPI_DMAError(DMA_HandleTypeDef * hdma)3388 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
3389 {
3390 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3391
3392 /* Stop the disable DMA transfer on SPI side */
3393 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3394
3395 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
3396 hspi->State = HAL_SPI_STATE_READY;
3397 /* Call user error callback */
3398 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3399 hspi->ErrorCallback(hspi);
3400 #else
3401 HAL_SPI_ErrorCallback(hspi);
3402 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3403 }
3404
3405 /**
3406 * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
3407 * (To be called at end of DMA Abort procedure following error occurrence).
3408 * @param hdma DMA handle.
3409 * @retval None
3410 */
SPI_DMAAbortOnError(DMA_HandleTypeDef * hdma)3411 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
3412 {
3413 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3414 hspi->RxXferCount = 0U;
3415 hspi->TxXferCount = 0U;
3416
3417 /* Call user error callback */
3418 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3419 hspi->ErrorCallback(hspi);
3420 #else
3421 HAL_SPI_ErrorCallback(hspi);
3422 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3423 }
3424
3425 /**
3426 * @brief DMA SPI Tx communication abort callback, when initiated by user
3427 * (To be called at end of DMA Tx Abort procedure following user abort request).
3428 * @note When this callback is executed, User Abort complete call back is called only if no
3429 * Abort still ongoing for Rx DMA Handle.
3430 * @param hdma DMA handle.
3431 * @retval None
3432 */
SPI_DMATxAbortCallback(DMA_HandleTypeDef * hdma)3433 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
3434 {
3435 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3436
3437 hspi->hdmatx->XferAbortCallback = NULL;
3438
3439 /* Disable Tx DMA Request */
3440 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
3441
3442 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3443 {
3444 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3445 }
3446
3447 /* Disable SPI Peripheral */
3448 __HAL_SPI_DISABLE(hspi);
3449
3450 /* Empty the FRLVL fifo */
3451 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3452 {
3453 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3454 }
3455
3456 /* Check if an Abort process is still ongoing */
3457 if (hspi->hdmarx != NULL)
3458 {
3459 if (hspi->hdmarx->XferAbortCallback != NULL)
3460 {
3461 return;
3462 }
3463 }
3464
3465 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3466 hspi->RxXferCount = 0U;
3467 hspi->TxXferCount = 0U;
3468
3469 /* Check no error during Abort procedure */
3470 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3471 {
3472 /* Reset errorCode */
3473 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3474 }
3475
3476 /* Clear the Error flags in the SR register */
3477 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3478 __HAL_SPI_CLEAR_FREFLAG(hspi);
3479
3480 /* Restore hspi->State to Ready */
3481 hspi->State = HAL_SPI_STATE_READY;
3482
3483 /* Call user Abort complete callback */
3484 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3485 hspi->AbortCpltCallback(hspi);
3486 #else
3487 HAL_SPI_AbortCpltCallback(hspi);
3488 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3489 }
3490
3491 /**
3492 * @brief DMA SPI Rx communication abort callback, when initiated by user
3493 * (To be called at end of DMA Rx Abort procedure following user abort request).
3494 * @note When this callback is executed, User Abort complete call back is called only if no
3495 * Abort still ongoing for Tx DMA Handle.
3496 * @param hdma DMA handle.
3497 * @retval None
3498 */
SPI_DMARxAbortCallback(DMA_HandleTypeDef * hdma)3499 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
3500 {
3501 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3502
3503 /* Disable SPI Peripheral */
3504 __HAL_SPI_DISABLE(hspi);
3505
3506 hspi->hdmarx->XferAbortCallback = NULL;
3507
3508 /* Disable Rx DMA Request */
3509 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
3510
3511 /* Control the BSY flag */
3512 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3513 {
3514 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3515 }
3516
3517 /* Empty the FRLVL fifo */
3518 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3519 {
3520 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3521 }
3522
3523 /* Check if an Abort process is still ongoing */
3524 if (hspi->hdmatx != NULL)
3525 {
3526 if (hspi->hdmatx->XferAbortCallback != NULL)
3527 {
3528 return;
3529 }
3530 }
3531
3532 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3533 hspi->RxXferCount = 0U;
3534 hspi->TxXferCount = 0U;
3535
3536 /* Check no error during Abort procedure */
3537 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3538 {
3539 /* Reset errorCode */
3540 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3541 }
3542
3543 /* Clear the Error flags in the SR register */
3544 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3545 __HAL_SPI_CLEAR_FREFLAG(hspi);
3546
3547 /* Restore hspi->State to Ready */
3548 hspi->State = HAL_SPI_STATE_READY;
3549
3550 /* Call user Abort complete callback */
3551 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3552 hspi->AbortCpltCallback(hspi);
3553 #else
3554 HAL_SPI_AbortCpltCallback(hspi);
3555 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3556 }
3557
3558 /**
3559 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3560 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3561 * the configuration information for SPI module.
3562 * @retval None
3563 */
SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3564 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3565 {
3566 /* Receive data in packing mode */
3567 if (hspi->RxXferCount > 1U)
3568 {
3569 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3570 hspi->pRxBuffPtr += sizeof(uint16_t);
3571 hspi->RxXferCount -= 2U;
3572 if (hspi->RxXferCount == 1U)
3573 {
3574 /* Set RX Fifo threshold according the reception data length: 8bit */
3575 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
3576 }
3577 }
3578 /* Receive data in 8 Bit mode */
3579 else
3580 {
3581 *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
3582 hspi->pRxBuffPtr++;
3583 hspi->RxXferCount--;
3584 }
3585
3586 /* Check end of the reception */
3587 if (hspi->RxXferCount == 0U)
3588 {
3589 #if (USE_SPI_CRC != 0U)
3590 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3591 {
3592 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
3593 hspi->RxISR = SPI_2linesRxISR_8BITCRC;
3594 return;
3595 }
3596 #endif /* USE_SPI_CRC */
3597
3598 /* Disable RXNE and ERR interrupt */
3599 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3600
3601 if (hspi->TxXferCount == 0U)
3602 {
3603 SPI_CloseRxTx_ISR(hspi);
3604 }
3605 }
3606 }
3607
3608 #if (USE_SPI_CRC != 0U)
3609 /**
3610 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3611 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3612 * the configuration information for SPI module.
3613 * @retval None
3614 */
SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef * hspi)3615 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3616 {
3617 __IO uint8_t *ptmpreg8;
3618 __IO uint8_t tmpreg8 = 0;
3619
3620 /* Initialize the 8bit temporary pointer */
3621 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3622 /* Read 8bit CRC to flush Data Register */
3623 tmpreg8 = *ptmpreg8;
3624 /* To avoid GCC warning */
3625 UNUSED(tmpreg8);
3626
3627 hspi->CRCSize--;
3628
3629 /* Check end of the reception */
3630 if (hspi->CRCSize == 0U)
3631 {
3632 /* Disable RXNE and ERR interrupt */
3633 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3634
3635 if (hspi->TxXferCount == 0U)
3636 {
3637 SPI_CloseRxTx_ISR(hspi);
3638 }
3639 }
3640 }
3641 #endif /* USE_SPI_CRC */
3642
3643 /**
3644 * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
3645 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3646 * the configuration information for SPI module.
3647 * @retval None
3648 */
SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3649 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3650 {
3651 /* Transmit data in packing Bit mode */
3652 if (hspi->TxXferCount >= 2U)
3653 {
3654 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3655 hspi->pTxBuffPtr += sizeof(uint16_t);
3656 hspi->TxXferCount -= 2U;
3657 }
3658 /* Transmit data in 8 Bit mode */
3659 else
3660 {
3661 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3662 hspi->pTxBuffPtr++;
3663 hspi->TxXferCount--;
3664 }
3665
3666 /* Check the end of the transmission */
3667 if (hspi->TxXferCount == 0U)
3668 {
3669 #if (USE_SPI_CRC != 0U)
3670 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3671 {
3672 /* Set CRC Next Bit to send CRC */
3673 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3674 /* Disable TXE interrupt */
3675 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3676 return;
3677 }
3678 #endif /* USE_SPI_CRC */
3679
3680 /* Disable TXE interrupt */
3681 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3682
3683 if (hspi->RxXferCount == 0U)
3684 {
3685 SPI_CloseRxTx_ISR(hspi);
3686 }
3687 }
3688 }
3689
3690 /**
3691 * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
3692 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3693 * the configuration information for SPI module.
3694 * @retval None
3695 */
SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3696 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3697 {
3698 /* Receive data in 16 Bit mode */
3699 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3700 hspi->pRxBuffPtr += sizeof(uint16_t);
3701 hspi->RxXferCount--;
3702
3703 if (hspi->RxXferCount == 0U)
3704 {
3705 #if (USE_SPI_CRC != 0U)
3706 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3707 {
3708 hspi->RxISR = SPI_2linesRxISR_16BITCRC;
3709 return;
3710 }
3711 #endif /* USE_SPI_CRC */
3712
3713 /* Disable RXNE interrupt */
3714 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3715
3716 if (hspi->TxXferCount == 0U)
3717 {
3718 SPI_CloseRxTx_ISR(hspi);
3719 }
3720 }
3721 }
3722
3723 #if (USE_SPI_CRC != 0U)
3724 /**
3725 * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
3726 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3727 * the configuration information for SPI module.
3728 * @retval None
3729 */
SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef * hspi)3730 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3731 {
3732 __IO uint32_t tmpreg = 0U;
3733
3734 /* Read 16bit CRC to flush Data Register */
3735 tmpreg = READ_REG(hspi->Instance->DR);
3736 /* To avoid GCC warning */
3737 UNUSED(tmpreg);
3738
3739 /* Disable RXNE interrupt */
3740 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3741
3742 SPI_CloseRxTx_ISR(hspi);
3743 }
3744 #endif /* USE_SPI_CRC */
3745
3746 /**
3747 * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
3748 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3749 * the configuration information for SPI module.
3750 * @retval None
3751 */
SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3752 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3753 {
3754 /* Transmit data in 16 Bit mode */
3755 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3756 hspi->pTxBuffPtr += sizeof(uint16_t);
3757 hspi->TxXferCount--;
3758
3759 /* Enable CRC Transmission */
3760 if (hspi->TxXferCount == 0U)
3761 {
3762 #if (USE_SPI_CRC != 0U)
3763 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3764 {
3765 /* Set CRC Next Bit to send CRC */
3766 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3767 /* Disable TXE interrupt */
3768 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3769 return;
3770 }
3771 #endif /* USE_SPI_CRC */
3772
3773 /* Disable TXE interrupt */
3774 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3775
3776 if (hspi->RxXferCount == 0U)
3777 {
3778 SPI_CloseRxTx_ISR(hspi);
3779 }
3780 }
3781 }
3782
3783 #if (USE_SPI_CRC != 0U)
3784 /**
3785 * @brief Manage the CRC 8-bit receive in Interrupt context.
3786 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3787 * the configuration information for SPI module.
3788 * @retval None
3789 */
SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef * hspi)3790 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3791 {
3792 __IO uint8_t *ptmpreg8;
3793 __IO uint8_t tmpreg8 = 0;
3794
3795 /* Initialize the 8bit temporary pointer */
3796 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3797 /* Read 8bit CRC to flush Data Register */
3798 tmpreg8 = *ptmpreg8;
3799 /* To avoid GCC warning */
3800 UNUSED(tmpreg8);
3801
3802 hspi->CRCSize--;
3803
3804 if (hspi->CRCSize == 0U)
3805 {
3806 SPI_CloseRx_ISR(hspi);
3807 }
3808 }
3809 #endif /* USE_SPI_CRC */
3810
3811 /**
3812 * @brief Manage the receive 8-bit in Interrupt context.
3813 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3814 * the configuration information for SPI module.
3815 * @retval None
3816 */
SPI_RxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3817 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3818 {
3819 *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
3820 hspi->pRxBuffPtr++;
3821 hspi->RxXferCount--;
3822
3823 #if (USE_SPI_CRC != 0U)
3824 /* Enable CRC Transmission */
3825 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3826 {
3827 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3828 }
3829 #endif /* USE_SPI_CRC */
3830
3831 if (hspi->RxXferCount == 0U)
3832 {
3833 #if (USE_SPI_CRC != 0U)
3834 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3835 {
3836 hspi->RxISR = SPI_RxISR_8BITCRC;
3837 return;
3838 }
3839 #endif /* USE_SPI_CRC */
3840 SPI_CloseRx_ISR(hspi);
3841 }
3842 }
3843
3844 #if (USE_SPI_CRC != 0U)
3845 /**
3846 * @brief Manage the CRC 16-bit receive in Interrupt context.
3847 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3848 * the configuration information for SPI module.
3849 * @retval None
3850 */
SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef * hspi)3851 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3852 {
3853 __IO uint32_t tmpreg = 0U;
3854
3855 /* Read 16bit CRC to flush Data Register */
3856 tmpreg = READ_REG(hspi->Instance->DR);
3857 /* To avoid GCC warning */
3858 UNUSED(tmpreg);
3859
3860 /* Disable RXNE and ERR interrupt */
3861 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3862
3863 SPI_CloseRx_ISR(hspi);
3864 }
3865 #endif /* USE_SPI_CRC */
3866
3867 /**
3868 * @brief Manage the 16-bit receive in Interrupt context.
3869 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3870 * the configuration information for SPI module.
3871 * @retval None
3872 */
SPI_RxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3873 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3874 {
3875 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3876 hspi->pRxBuffPtr += sizeof(uint16_t);
3877 hspi->RxXferCount--;
3878
3879 #if (USE_SPI_CRC != 0U)
3880 /* Enable CRC Transmission */
3881 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3882 {
3883 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3884 }
3885 #endif /* USE_SPI_CRC */
3886
3887 if (hspi->RxXferCount == 0U)
3888 {
3889 #if (USE_SPI_CRC != 0U)
3890 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3891 {
3892 hspi->RxISR = SPI_RxISR_16BITCRC;
3893 return;
3894 }
3895 #endif /* USE_SPI_CRC */
3896 SPI_CloseRx_ISR(hspi);
3897 }
3898 }
3899
3900 /**
3901 * @brief Handle the data 8-bit transmit in Interrupt mode.
3902 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3903 * the configuration information for SPI module.
3904 * @retval None
3905 */
SPI_TxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3906 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3907 {
3908 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3909 hspi->pTxBuffPtr++;
3910 hspi->TxXferCount--;
3911
3912 if (hspi->TxXferCount == 0U)
3913 {
3914 #if (USE_SPI_CRC != 0U)
3915 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3916 {
3917 /* Enable CRC Transmission */
3918 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3919 }
3920 #endif /* USE_SPI_CRC */
3921 SPI_CloseTx_ISR(hspi);
3922 }
3923 }
3924
3925 /**
3926 * @brief Handle the data 16-bit transmit in Interrupt mode.
3927 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3928 * the configuration information for SPI module.
3929 * @retval None
3930 */
SPI_TxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3931 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3932 {
3933 /* Transmit data in 16 Bit mode */
3934 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3935 hspi->pTxBuffPtr += sizeof(uint16_t);
3936 hspi->TxXferCount--;
3937
3938 if (hspi->TxXferCount == 0U)
3939 {
3940 #if (USE_SPI_CRC != 0U)
3941 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3942 {
3943 /* Enable CRC Transmission */
3944 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3945 }
3946 #endif /* USE_SPI_CRC */
3947 SPI_CloseTx_ISR(hspi);
3948 }
3949 }
3950
3951 /**
3952 * @brief Handle SPI Communication Timeout.
3953 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3954 * the configuration information for SPI module.
3955 * @param Flag SPI flag to check
3956 * @param State flag state to check
3957 * @param Timeout Timeout duration
3958 * @param Tickstart tick start value
3959 * @retval HAL status
3960 */
SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef * hspi,uint32_t Flag,FlagStatus State,uint32_t Timeout,uint32_t Tickstart)3961 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
3962 uint32_t Timeout, uint32_t Tickstart)
3963 {
3964 __IO uint32_t count;
3965 uint32_t tmp_timeout;
3966 uint32_t tmp_tickstart;
3967
3968 /* Adjust Timeout value in case of end of transfer */
3969 tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
3970 tmp_tickstart = HAL_GetTick();
3971
3972 /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
3973 count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
3974
3975 while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
3976 {
3977 if (Timeout != HAL_MAX_DELAY)
3978 {
3979 if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
3980 {
3981 /* Disable the SPI and reset the CRC: the CRC value should be cleared
3982 on both master and slave sides in order to resynchronize the master
3983 and slave for their respective CRC calculation */
3984
3985 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
3986 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
3987
3988 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3989 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3990 {
3991 /* Disable SPI peripheral */
3992 __HAL_SPI_DISABLE(hspi);
3993 }
3994
3995 /* Reset CRC Calculation */
3996 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3997 {
3998 SPI_RESET_CRC(hspi);
3999 }
4000
4001 hspi->State = HAL_SPI_STATE_READY;
4002
4003 /* Process Unlocked */
4004 __HAL_UNLOCK(hspi);
4005
4006 return HAL_TIMEOUT;
4007 }
4008 /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
4009 if (count == 0U)
4010 {
4011 tmp_timeout = 0U;
4012 }
4013 count--;
4014 }
4015 }
4016
4017 return HAL_OK;
4018 }
4019
4020 /**
4021 * @brief Handle SPI FIFO Communication Timeout.
4022 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4023 * the configuration information for SPI module.
4024 * @param Fifo Fifo to check
4025 * @param State Fifo state to check
4026 * @param Timeout Timeout duration
4027 * @param Tickstart tick start value
4028 * @retval HAL status
4029 */
SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef * hspi,uint32_t Fifo,uint32_t State,uint32_t Timeout,uint32_t Tickstart)4030 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
4031 uint32_t Timeout, uint32_t Tickstart)
4032 {
4033 __IO uint32_t count;
4034 uint32_t tmp_timeout;
4035 uint32_t tmp_tickstart;
4036 __IO uint8_t *ptmpreg8;
4037 __IO uint8_t tmpreg8 = 0;
4038
4039 /* Adjust Timeout value in case of end of transfer */
4040 tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
4041 tmp_tickstart = HAL_GetTick();
4042
4043 /* Initialize the 8bit temporary pointer */
4044 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
4045
4046 /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
4047 count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U);
4048
4049 while ((hspi->Instance->SR & Fifo) != State)
4050 {
4051 if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
4052 {
4053 /* Flush Data Register by a blank read */
4054 tmpreg8 = *ptmpreg8;
4055 /* To avoid GCC warning */
4056 UNUSED(tmpreg8);
4057 }
4058
4059 if (Timeout != HAL_MAX_DELAY)
4060 {
4061 if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
4062 {
4063 /* Disable the SPI and reset the CRC: the CRC value should be cleared
4064 on both master and slave sides in order to resynchronize the master
4065 and slave for their respective CRC calculation */
4066
4067 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
4068 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
4069
4070 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
4071 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
4072 {
4073 /* Disable SPI peripheral */
4074 __HAL_SPI_DISABLE(hspi);
4075 }
4076
4077 /* Reset CRC Calculation */
4078 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
4079 {
4080 SPI_RESET_CRC(hspi);
4081 }
4082
4083 hspi->State = HAL_SPI_STATE_READY;
4084
4085 /* Process Unlocked */
4086 __HAL_UNLOCK(hspi);
4087
4088 return HAL_TIMEOUT;
4089 }
4090 /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
4091 if (count == 0U)
4092 {
4093 tmp_timeout = 0U;
4094 }
4095 count--;
4096 }
4097 }
4098
4099 return HAL_OK;
4100 }
4101
4102 /**
4103 * @brief Handle the check of the RX transaction complete.
4104 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4105 * the configuration information for SPI module.
4106 * @param Timeout Timeout duration
4107 * @param Tickstart tick start value
4108 * @retval HAL status
4109 */
SPI_EndRxTransaction(SPI_HandleTypeDef * hspi,uint32_t Timeout,uint32_t Tickstart)4110 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
4111 {
4112 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
4113 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
4114 {
4115 /* Disable SPI peripheral */
4116 __HAL_SPI_DISABLE(hspi);
4117 }
4118
4119 /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */
4120 if (hspi->Init.Mode == SPI_MODE_MASTER)
4121 {
4122 /* Control the BSY flag */
4123 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
4124 {
4125 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4126 return HAL_TIMEOUT;
4127 }
4128 }
4129 else /* SPI_MODE_SLAVE */
4130 {
4131 /* Timeout in µs */
4132 __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U);
4133
4134 /* Wait BSY flag during 1 Byte time transfer in case of Rx transfer
4135 * If Timeout is reached, the transfer is considered as finish.
4136 * User have to calculate the timeout value to fit with the time of 1 byte transfer.
4137 * This time is directly link with the SPI clock from Master device.
4138 */
4139 do
4140 {
4141 if (count == 0U)
4142 {
4143 break;
4144 }
4145 count--;
4146 } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET);
4147 }
4148
4149 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
4150 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
4151 {
4152 /* Empty the FRLVL fifo */
4153 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
4154 {
4155 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4156 return HAL_TIMEOUT;
4157 }
4158 }
4159 return HAL_OK;
4160 }
4161
4162 /**
4163 * @brief Handle the check of the RXTX or TX transaction complete.
4164 * @param hspi SPI handle
4165 * @param Timeout Timeout duration
4166 * @param Tickstart tick start value
4167 * @retval HAL status
4168 */
SPI_EndRxTxTransaction(SPI_HandleTypeDef * hspi,uint32_t Timeout,uint32_t Tickstart)4169 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
4170 {
4171 /* Control if the TX fifo is empty */
4172 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
4173 {
4174 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4175 return HAL_TIMEOUT;
4176 }
4177
4178 /* Timeout in µs */
4179 __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U);
4180 /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */
4181 if (hspi->Init.Mode == SPI_MODE_MASTER)
4182 {
4183 /* Control the BSY flag */
4184 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
4185 {
4186 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4187 return HAL_TIMEOUT;
4188 }
4189 }
4190 else
4191 {
4192 /* Wait BSY flag during 1 Byte time transfer in case of Full-Duplex and Tx transfer
4193 * If Timeout is reached, the transfer is considered as finish.
4194 * User have to calculate the timeout value to fit with the time of 1 byte transfer.
4195 * This time is directly link with the SPI clock from Master device.
4196 */
4197 do
4198 {
4199 if (count == 0U)
4200 {
4201 break;
4202 }
4203 count--;
4204 } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET);
4205 }
4206
4207
4208 /* Control if the RX fifo is empty */
4209 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
4210 {
4211 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4212 return HAL_TIMEOUT;
4213 }
4214
4215 return HAL_OK;
4216 }
4217
4218 /**
4219 * @brief Handle the end of the RXTX transaction.
4220 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4221 * the configuration information for SPI module.
4222 * @retval None
4223 */
SPI_CloseRxTx_ISR(SPI_HandleTypeDef * hspi)4224 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
4225 {
4226 uint32_t tickstart;
4227
4228 /* Init tickstart for timeout management */
4229 tickstart = HAL_GetTick();
4230
4231 /* Disable ERR interrupt */
4232 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
4233
4234 /* Check the end of the transaction */
4235 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
4236 {
4237 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4238 }
4239
4240 #if (USE_SPI_CRC != 0U)
4241 /* Check if CRC error occurred */
4242 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
4243 {
4244 hspi->State = HAL_SPI_STATE_READY;
4245 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
4246 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
4247 /* Call user error callback */
4248 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4249 hspi->ErrorCallback(hspi);
4250 #else
4251 HAL_SPI_ErrorCallback(hspi);
4252 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4253 }
4254 else
4255 {
4256 #endif /* USE_SPI_CRC */
4257 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
4258 {
4259 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
4260 {
4261 hspi->State = HAL_SPI_STATE_READY;
4262 /* Call user Rx complete callback */
4263 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4264 hspi->RxCpltCallback(hspi);
4265 #else
4266 HAL_SPI_RxCpltCallback(hspi);
4267 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4268 }
4269 else
4270 {
4271 hspi->State = HAL_SPI_STATE_READY;
4272 /* Call user TxRx complete callback */
4273 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4274 hspi->TxRxCpltCallback(hspi);
4275 #else
4276 HAL_SPI_TxRxCpltCallback(hspi);
4277 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4278 }
4279 }
4280 else
4281 {
4282 hspi->State = HAL_SPI_STATE_READY;
4283 /* Call user error callback */
4284 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4285 hspi->ErrorCallback(hspi);
4286 #else
4287 HAL_SPI_ErrorCallback(hspi);
4288 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4289 }
4290 #if (USE_SPI_CRC != 0U)
4291 }
4292 #endif /* USE_SPI_CRC */
4293 }
4294
4295 /**
4296 * @brief Handle the end of the RX transaction.
4297 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4298 * the configuration information for SPI module.
4299 * @retval None
4300 */
SPI_CloseRx_ISR(SPI_HandleTypeDef * hspi)4301 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
4302 {
4303 /* Disable RXNE and ERR interrupt */
4304 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
4305
4306 /* Check the end of the transaction */
4307 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4308 {
4309 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4310 }
4311 hspi->State = HAL_SPI_STATE_READY;
4312
4313 #if (USE_SPI_CRC != 0U)
4314 /* Check if CRC error occurred */
4315 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
4316 {
4317 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
4318 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
4319 /* Call user error callback */
4320 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4321 hspi->ErrorCallback(hspi);
4322 #else
4323 HAL_SPI_ErrorCallback(hspi);
4324 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4325 }
4326 else
4327 {
4328 #endif /* USE_SPI_CRC */
4329 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
4330 {
4331 /* Call user Rx complete callback */
4332 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4333 hspi->RxCpltCallback(hspi);
4334 #else
4335 HAL_SPI_RxCpltCallback(hspi);
4336 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4337 }
4338 else
4339 {
4340 /* Call user error callback */
4341 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4342 hspi->ErrorCallback(hspi);
4343 #else
4344 HAL_SPI_ErrorCallback(hspi);
4345 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4346 }
4347 #if (USE_SPI_CRC != 0U)
4348 }
4349 #endif /* USE_SPI_CRC */
4350 }
4351
4352 /**
4353 * @brief Handle the end of the TX transaction.
4354 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4355 * the configuration information for SPI module.
4356 * @retval None
4357 */
SPI_CloseTx_ISR(SPI_HandleTypeDef * hspi)4358 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
4359 {
4360 uint32_t tickstart;
4361
4362 /* Init tickstart for timeout management*/
4363 tickstart = HAL_GetTick();
4364
4365 /* Disable TXE and ERR interrupt */
4366 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
4367
4368 /* Check the end of the transaction */
4369 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
4370 {
4371 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4372 }
4373
4374 /* Clear overrun flag in 2 Lines communication mode because received is not read */
4375 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
4376 {
4377 __HAL_SPI_CLEAR_OVRFLAG(hspi);
4378 }
4379
4380 hspi->State = HAL_SPI_STATE_READY;
4381 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
4382 {
4383 /* Call user error callback */
4384 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4385 hspi->ErrorCallback(hspi);
4386 #else
4387 HAL_SPI_ErrorCallback(hspi);
4388 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4389 }
4390 else
4391 {
4392 /* Call user Rx complete callback */
4393 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4394 hspi->TxCpltCallback(hspi);
4395 #else
4396 HAL_SPI_TxCpltCallback(hspi);
4397 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4398 }
4399 }
4400
4401 /**
4402 * @brief Handle abort a Rx transaction.
4403 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4404 * the configuration information for SPI module.
4405 * @retval None
4406 */
SPI_AbortRx_ISR(SPI_HandleTypeDef * hspi)4407 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
4408 {
4409 __IO uint32_t count;
4410
4411 /* Disable SPI Peripheral */
4412 __HAL_SPI_DISABLE(hspi);
4413
4414 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
4415
4416 /* Disable RXNEIE interrupt */
4417 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
4418
4419 /* Check RXNEIE is disabled */
4420 do
4421 {
4422 if (count == 0U)
4423 {
4424 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4425 break;
4426 }
4427 count--;
4428 } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
4429
4430 /* Control the BSY flag */
4431 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4432 {
4433 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4434 }
4435
4436 /* Empty the FRLVL fifo */
4437 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4438 {
4439 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4440 }
4441
4442 hspi->State = HAL_SPI_STATE_ABORT;
4443 }
4444
4445 /**
4446 * @brief Handle abort a Tx or Rx/Tx transaction.
4447 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4448 * the configuration information for SPI module.
4449 * @retval None
4450 */
SPI_AbortTx_ISR(SPI_HandleTypeDef * hspi)4451 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
4452 {
4453 __IO uint32_t count;
4454
4455 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
4456
4457 /* Disable TXEIE interrupt */
4458 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
4459
4460 /* Check TXEIE is disabled */
4461 do
4462 {
4463 if (count == 0U)
4464 {
4465 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4466 break;
4467 }
4468 count--;
4469 } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
4470
4471 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4472 {
4473 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4474 }
4475
4476 /* Disable SPI Peripheral */
4477 __HAL_SPI_DISABLE(hspi);
4478
4479 /* Empty the FRLVL fifo */
4480 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4481 {
4482 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4483 }
4484
4485 /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */
4486 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
4487 {
4488 /* Disable RXNEIE interrupt */
4489 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
4490
4491 /* Check RXNEIE is disabled */
4492 do
4493 {
4494 if (count == 0U)
4495 {
4496 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4497 break;
4498 }
4499 count--;
4500 } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
4501
4502 /* Control the BSY flag */
4503 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4504 {
4505 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4506 }
4507
4508 /* Empty the FRLVL fifo */
4509 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4510 {
4511 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4512 }
4513 }
4514 hspi->State = HAL_SPI_STATE_ABORT;
4515 }
4516
4517 /**
4518 * @}
4519 */
4520
4521 #endif /* HAL_SPI_MODULE_ENABLED */
4522
4523 /**
4524 * @}
4525 */
4526
4527 /**
4528 * @}
4529 */
4530
4531
