1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_pwr.c
4 * @author MCD Application Team
5 * @brief PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller (PWR) peripheral:
8 * + Initialization and de-initialization functions
9 * + Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2017 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file
18 * in the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 *
21 ******************************************************************************
22 */
23
24 /* Includes ------------------------------------------------------------------*/
25 #include "stm32f7xx_hal.h"
26
27 /** @addtogroup STM32F7xx_HAL_Driver
28 * @{
29 */
30
31 /** @defgroup PWR PWR
32 * @brief PWR HAL module driver
33 * @{
34 */
35
36 #ifdef HAL_PWR_MODULE_ENABLED
37
38 /* Private typedef -----------------------------------------------------------*/
39 /* Private define ------------------------------------------------------------*/
40 /** @addtogroup PWR_Private_Constants
41 * @{
42 */
43
44 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
45 * @{
46 */
47 #define PVD_MODE_IT ((uint32_t)0x00010000U)
48 #define PVD_MODE_EVT ((uint32_t)0x00020000U)
49 #define PVD_RISING_EDGE ((uint32_t)0x00000001U)
50 #define PVD_FALLING_EDGE ((uint32_t)0x00000002U)
51 /**
52 * @}
53 */
54
55 /** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask
56 * @{
57 */
58 #define PWR_EWUP_MASK ((uint32_t)0x00003F00)
59 /**
60 * @}
61 */
62
63 /**
64 * @}
65 */
66 /* Private macro -------------------------------------------------------------*/
67 /* Private variables ---------------------------------------------------------*/
68 /* Private function prototypes -----------------------------------------------*/
69 /* Private functions ---------------------------------------------------------*/
70
71 /** @defgroup PWR_Exported_Functions PWR Exported Functions
72 * @{
73 */
74
75 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
76 * @brief Initialization and de-initialization functions
77 *
78 @verbatim
79 ===============================================================================
80 ##### Initialization and de-initialization functions #####
81 ===============================================================================
82 [..]
83 After reset, the backup domain (RTC registers, RTC backup data
84 registers and backup SRAM) is protected against possible unwanted
85 write accesses.
86 To enable access to the RTC Domain and RTC registers, proceed as follows:
87 (+) Enable the Power Controller (PWR) APB1 interface clock using the
88 __HAL_RCC_PWR_CLK_ENABLE() macro.
89 (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
90
91 @endverbatim
92 * @{
93 */
94
95 /**
96 * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
97 * @retval None
98 */
HAL_PWR_DeInit(void)99 void HAL_PWR_DeInit(void)
100 {
101 __HAL_RCC_PWR_FORCE_RESET();
102 __HAL_RCC_PWR_RELEASE_RESET();
103 }
104
105 /**
106 * @brief Enables access to the backup domain (RTC registers, RTC
107 * backup data registers and backup SRAM).
108 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
109 * Backup Domain Access should be kept enabled.
110 * @retval None
111 */
HAL_PWR_EnableBkUpAccess(void)112 void HAL_PWR_EnableBkUpAccess(void)
113 {
114 /* Enable access to RTC and backup registers */
115 SET_BIT(PWR->CR1, PWR_CR1_DBP);
116 }
117
118 /**
119 * @brief Disables access to the backup domain (RTC registers, RTC
120 * backup data registers and backup SRAM).
121 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
122 * Backup Domain Access should be kept enabled.
123 * @retval None
124 */
HAL_PWR_DisableBkUpAccess(void)125 void HAL_PWR_DisableBkUpAccess(void)
126 {
127 /* Disable access to RTC and backup registers */
128 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
129 }
130
131 /**
132 * @}
133 */
134
135 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
136 * @brief Low Power modes configuration functions
137 *
138 @verbatim
139
140 ===============================================================================
141 ##### Peripheral Control functions #####
142 ===============================================================================
143
144 *** PVD configuration ***
145 =========================
146 [..]
147 (+) The PVD is used to monitor the VDD power supply by comparing it to a
148 threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
149 (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
150 than the PVD threshold. This event is internally connected to the EXTI
151 line16 and can generate an interrupt if enabled. This is done through
152 __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
153 (+) The PVD is stopped in Standby mode.
154
155 *** Wake-up pin configuration ***
156 ================================
157 [..]
158 (+) Wake-up pin is used to wake up the system from Standby mode. This pin is
159 forced in input pull-down configuration and is active on rising edges.
160 (+) There are up to 6 Wake-up pin in the STM32F7 devices family
161
162 *** Low Power modes configuration ***
163 =====================================
164 [..]
165 The devices feature 3 low-power modes:
166 (+) Sleep mode: Cortex-M7 core stopped, peripherals kept running.
167 (+) Stop mode: all clocks are stopped, regulator running, regulator
168 in low power mode
169 (+) Standby mode: 1.2V domain powered off.
170
171 *** Sleep mode ***
172 ==================
173 [..]
174 (+) Entry:
175 The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)
176 functions with
177 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
178 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
179
180 -@@- The Regulator parameter is not used for the STM32F7 family
181 and is kept as parameter just to maintain compatibility with the
182 lower power families (STM32L).
183 (+) Exit:
184 Any peripheral interrupt acknowledged by the nested vectored interrupt
185 controller (NVIC) can wake up the device from Sleep mode.
186
187 *** Stop mode ***
188 =================
189 [..]
190 In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
191 and the HSE RC oscillators are disabled. Internal SRAM and register contents
192 are preserved.
193 The voltage regulator can be configured either in normal or low-power mode.
194 To minimize the consumption In Stop mode, FLASH can be powered off before
195 entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
196 It can be switched on again by software after exiting the Stop mode using
197 the HAL_PWREx_DisableFlashPowerDown() function.
198
199 (+) Entry:
200 The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON)
201 function with:
202 (++) Main regulator ON.
203 (++) Low Power regulator ON.
204 (+) Exit:
205 Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
206
207 *** Standby mode ***
208 ====================
209 [..]
210 (+)
211 The Standby mode allows to achieve the lowest power consumption. It is based
212 on the Cortex-M7 deep sleep mode, with the voltage regulator disabled.
213 The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
214 the HSE oscillator are also switched off. SRAM and register contents are lost
215 except for the RTC registers, RTC backup registers, backup SRAM and Standby
216 circuitry.
217
218 The voltage regulator is OFF.
219
220 (++) Entry:
221 (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
222 (++) Exit:
223 (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
224 wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.
225
226 *** Auto-wakeup (AWU) from low-power mode ***
227 =============================================
228 [..]
229
230 (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
231 Wakeup event, a tamper event or a time-stamp event, without depending on
232 an external interrupt (Auto-wakeup mode).
233
234 (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
235
236 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
237 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
238
239 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
240 is necessary to configure the RTC to detect the tamper or time stamp event using the
241 HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
242
243 (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
244 configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
245
246 @endverbatim
247 * @{
248 */
249
250 /**
251 * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
252 * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
253 * information for the PVD.
254 * @note Refer to the electrical characteristics of your device datasheet for
255 * more details about the voltage threshold corresponding to each
256 * detection level.
257 * @retval None
258 */
HAL_PWR_ConfigPVD(PWR_PVDTypeDef * sConfigPVD)259 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
260 {
261 /* Check the parameters */
262 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
263 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
264
265 /* Set PLS[7:5] bits according to PVDLevel value */
266 MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
267
268 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
269 __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
270 __HAL_PWR_PVD_EXTI_DISABLE_IT();
271 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
272 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
273
274 /* Configure interrupt mode */
275 if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
276 {
277 __HAL_PWR_PVD_EXTI_ENABLE_IT();
278 }
279
280 /* Configure event mode */
281 if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
282 {
283 __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
284 }
285
286 /* Configure the edge */
287 if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
288 {
289 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
290 }
291
292 if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
293 {
294 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
295 }
296 }
297
298 /**
299 * @brief Enables the Power Voltage Detector(PVD).
300 * @retval None
301 */
HAL_PWR_EnablePVD(void)302 void HAL_PWR_EnablePVD(void)
303 {
304 /* Enable the power voltage detector */
305 SET_BIT(PWR->CR1, PWR_CR1_PVDE);
306 }
307
308 /**
309 * @brief Disables the Power Voltage Detector(PVD).
310 * @retval None
311 */
HAL_PWR_DisablePVD(void)312 void HAL_PWR_DisablePVD(void)
313 {
314 /* Disable the power voltage detector */
315 CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE);
316 }
317
318 /**
319 * @brief Enable the WakeUp PINx functionality.
320 * @param WakeUpPinPolarity Specifies which Wake-Up pin to enable.
321 * This parameter can be one of the following legacy values, which sets the default polarity:
322 * detection on high level (rising edge):
323 * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6
324 * or one of the following value where the user can explicitly states the enabled pin and
325 * the chosen polarity
326 * @arg PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
327 * @arg PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
328 * @arg PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
329 * @arg PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
330 * @arg PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
331 * @arg PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW
332 * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
333 * @retval None
334 */
HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)335 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
336 {
337 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
338
339 /* Enable wake-up pin */
340 SET_BIT(PWR->CSR2, (PWR_EWUP_MASK & WakeUpPinPolarity));
341
342 /* Specifies the Wake-Up pin polarity for the event detection
343 (rising or falling edge) */
344 MODIFY_REG(PWR->CR2, (PWR_EWUP_MASK & WakeUpPinPolarity), (WakeUpPinPolarity >> 0x06));
345 }
346
347 /**
348 * @brief Disables the WakeUp PINx functionality.
349 * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
350 * This parameter can be one of the following values:
351 * @arg PWR_WAKEUP_PIN1
352 * @arg PWR_WAKEUP_PIN2
353 * @arg PWR_WAKEUP_PIN3
354 * @arg PWR_WAKEUP_PIN4
355 * @arg PWR_WAKEUP_PIN5
356 * @arg PWR_WAKEUP_PIN6
357 * @retval None
358 */
HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)359 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
360 {
361 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
362
363 CLEAR_BIT(PWR->CSR2, WakeUpPinx);
364 }
365
366 /**
367 * @brief Enters Sleep mode.
368 *
369 * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
370 *
371 * @note In Sleep mode, the systick is stopped to avoid exit from this mode with
372 * systick interrupt when used as time base for Timeout
373 *
374 * @param Regulator Specifies the regulator state in SLEEP mode.
375 * This parameter can be one of the following values:
376 * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
377 * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
378 * @note This parameter is not used for the STM32F7 family and is kept as parameter
379 * just to maintain compatibility with the lower power families.
380 * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction.
381 * This parameter can be one of the following values:
382 * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
383 * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
384 * @retval None
385 */
HAL_PWR_EnterSLEEPMode(uint32_t Regulator,uint8_t SLEEPEntry)386 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
387 {
388 /* Check the parameters */
389 assert_param(IS_PWR_REGULATOR(Regulator));
390 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
391
392 /* Prevent unused argument(s) compilation warning */
393 UNUSED(Regulator);
394
395 /* Clear SLEEPDEEP bit of Cortex System Control Register */
396 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
397
398 /* Ensure that all instructions done before entering SLEEP mode */
399 __DSB();
400 __ISB();
401
402 /* Select SLEEP mode entry -------------------------------------------------*/
403 if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
404 {
405 /* Request Wait For Interrupt */
406 __WFI();
407 }
408 else
409 {
410 /* Request Wait For Event */
411 __SEV();
412 __WFE();
413 __WFE();
414 }
415 }
416
417 /**
418 * @brief Enters Stop mode.
419 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
420 * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
421 * the HSI RC oscillator is selected as system clock.
422 * @note When the voltage regulator operates in low power mode, an additional
423 * startup delay is incurred when waking up from Stop mode.
424 * By keeping the internal regulator ON during Stop mode, the consumption
425 * is higher although the startup time is reduced.
426 * @param Regulator Specifies the regulator state in Stop mode.
427 * This parameter can be one of the following values:
428 * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
429 * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
430 * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction.
431 * This parameter can be one of the following values:
432 * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
433 * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
434 * @retval None
435 */
HAL_PWR_EnterSTOPMode(uint32_t Regulator,uint8_t STOPEntry)436 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
437 {
438 uint32_t tmpreg = 0;
439
440 /* Check the parameters */
441 assert_param(IS_PWR_REGULATOR(Regulator));
442 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
443
444 /* Select the regulator state in Stop mode ---------------------------------*/
445 tmpreg = PWR->CR1;
446 /* Clear PDDS and LPDS bits */
447 tmpreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS);
448
449 /* Set LPDS, MRLVDS and LPLVDS bits according to Regulator value */
450 tmpreg |= Regulator;
451
452 /* Store the new value */
453 PWR->CR1 = tmpreg;
454
455 /* Set SLEEPDEEP bit of Cortex System Control Register */
456 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
457
458 /* Ensure that all instructions done before entering STOP mode */
459 __DSB();
460 __ISB();
461
462 /* Select Stop mode entry --------------------------------------------------*/
463 if(STOPEntry == PWR_STOPENTRY_WFI)
464 {
465 /* Request Wait For Interrupt */
466 __WFI();
467 }
468 else
469 {
470 /* Request Wait For Event */
471 __SEV();
472 __WFE();
473 __WFE();
474 }
475 /* Reset SLEEPDEEP bit of Cortex System Control Register */
476 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
477 }
478
479 /**
480 * @brief Enters Standby mode.
481 * @note In Standby mode, all I/O pins are high impedance except for:
482 * - Reset pad (still available)
483 * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
484 * Alarm out, or RTC clock calibration out.
485 * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
486 * - WKUP pins if enabled.
487 * @retval None
488 */
HAL_PWR_EnterSTANDBYMode(void)489 void HAL_PWR_EnterSTANDBYMode(void)
490 {
491 /* Select Standby mode */
492 PWR->CR1 |= PWR_CR1_PDDS;
493
494 /* Set SLEEPDEEP bit of Cortex System Control Register */
495 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
496
497 /* This option is used to ensure that store operations are completed */
498 #if defined ( __CC_ARM)
499 __force_stores();
500 #endif
501 /* Request Wait For Interrupt */
502 __WFI();
503 }
504
505 /**
506 * @brief This function handles the PWR PVD interrupt request.
507 * @note This API should be called under the PVD_IRQHandler().
508 * @retval None
509 */
HAL_PWR_PVD_IRQHandler(void)510 void HAL_PWR_PVD_IRQHandler(void)
511 {
512 /* Check PWR Exti flag */
513 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
514 {
515 /* PWR PVD interrupt user callback */
516 HAL_PWR_PVDCallback();
517
518 /* Clear PWR Exti pending bit */
519 __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
520 }
521 }
522
523 /**
524 * @brief PWR PVD interrupt callback
525 * @retval None
526 */
HAL_PWR_PVDCallback(void)527 __weak void HAL_PWR_PVDCallback(void)
528 {
529 /* NOTE : This function Should not be modified, when the callback is needed,
530 the HAL_PWR_PVDCallback could be implemented in the user file
531 */
532 }
533
534 /**
535 * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
536 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
537 * re-enters SLEEP mode when an interruption handling is over.
538 * Setting this bit is useful when the processor is expected to run only on
539 * interruptions handling.
540 * @retval None
541 */
HAL_PWR_EnableSleepOnExit(void)542 void HAL_PWR_EnableSleepOnExit(void)
543 {
544 /* Set SLEEPONEXIT bit of Cortex System Control Register */
545 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
546 }
547
548 /**
549 * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
550 * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
551 * re-enters SLEEP mode when an interruption handling is over.
552 * @retval None
553 */
HAL_PWR_DisableSleepOnExit(void)554 void HAL_PWR_DisableSleepOnExit(void)
555 {
556 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
557 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
558 }
559
560 /**
561 * @brief Enables CORTEX M4 SEVONPEND bit.
562 * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
563 * WFE to wake up when an interrupt moves from inactive to pended.
564 * @retval None
565 */
HAL_PWR_EnableSEVOnPend(void)566 void HAL_PWR_EnableSEVOnPend(void)
567 {
568 /* Set SEVONPEND bit of Cortex System Control Register */
569 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
570 }
571
572 /**
573 * @brief Disables CORTEX M4 SEVONPEND bit.
574 * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
575 * WFE to wake up when an interrupt moves from inactive to pended.
576 * @retval None
577 */
HAL_PWR_DisableSEVOnPend(void)578 void HAL_PWR_DisableSEVOnPend(void)
579 {
580 /* Clear SEVONPEND bit of Cortex System Control Register */
581 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
582 }
583
584 /**
585 * @}
586 */
587
588 /**
589 * @}
590 */
591
592 #endif /* HAL_PWR_MODULE_ENABLED */
593 /**
594 * @}
595 */
596
597 /**
598 * @}
599 */
600
601
