1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_cryp.c
4 * @author MCD Application Team
5 * @brief CRYP HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Cryptography (CRYP) peripheral:
8 * + Initialization, de-initialization, set config and get config functions
9 * + DES/TDES, AES processing functions
10 * + DMA callback functions
11 * + CRYP IRQ handler management
12 * + Peripheral State functions
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2017 STMicroelectronics.
18 * All rights reserved.
19 *
20 * This software is licensed under terms that can be found in the LICENSE file
21 * in the root directory of this software component.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
23 *
24 ******************************************************************************
25 @verbatim
26 ==============================================================================
27 ##### How to use this driver #####
28 ==============================================================================
29 [..]
30 The CRYP HAL driver can be used in CRYP or TinyAES IP as follows:
31
32 (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
33 (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()or __HAL_RCC_AES_CLK_ENABLE for TinyAES IP
34 (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT())
35 (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
36 (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
37 (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
38 (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA())
39 (+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE()
40 (+++) Configure and enable two DMA streams one for managing data transfer from
41 memory to peripheral (input stream) and another stream for managing data
42 transfer from peripheral to memory (output stream)
43 (+++) Associate the initialized DMA handle to the CRYP DMA handle
44 using __HAL_LINKDMA()
45 (+++) Configure the priority and enable the NVIC for the transfer complete
46 interrupt on the two DMA Streams. The output stream should have higher
47 priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
48
49 (#)Initialize the CRYP according to the specified parameters :
50 (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
51 (##) The key size: 128, 192 or 256.
52 (##) The AlgoMode DES/ TDES Algorithm ECB/CBC or AES Algorithm ECB/CBC/CTR/GCM or CCM.
53 (##) The initialization vector (counter). It is not used in ECB mode.
54 (##) The key buffer used for encryption/decryption.
55 (##) The Header used only in AES GCM and CCM Algorithm for authentication.
56 (##) The HeaderSize The size of header buffer in word.
57 (##) The B0 block is the first authentication block used only in AES CCM mode.
58
59 (#)Three processing (encryption/decryption) functions are available:
60 (##) Polling mode: encryption and decryption APIs are blocking functions
61 i.e. they process the data and wait till the processing is finished,
62 e.g. HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
63 (##) Interrupt mode: encryption and decryption APIs are not blocking functions
64 i.e. they process the data under interrupt,
65 e.g. HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
66 (##) DMA mode: encryption and decryption APIs are not blocking functions
67 i.e. the data transfer is ensured by DMA,
68 e.g. HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
69
70 (#)When the processing function is called at first time after HAL_CRYP_Init()
71 the CRYP peripheral is configured and processes the buffer in input.
72 At second call, no need to Initialize the CRYP, user have to get current configuration via
73 HAL_CRYP_GetConfig() API, then only HAL_CRYP_SetConfig() is requested to set
74 new parametres, finally user can start encryption/decryption.
75
76 (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
77
78 (#)To process a single message with consecutive calls to HAL_CRYP_Encrypt() or HAL_CRYP_Decrypt()
79 without having to configure again the Key or the Initialization Vector between each API call,
80 the field KeyIVConfigSkip of the initialization structure must be set to CRYP_KEYIVCONFIG_ONCE.
81 Same is true for consecutive calls of HAL_CRYP_Encrypt_IT(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_DMA()
82 or HAL_CRYP_Decrypt_DMA().
83
84 [..]
85 The cryptographic processor supports following standards:
86 (#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 IP:
87 (##)64-bit data block processing
88 (##) chaining modes supported :
89 (+++) Electronic Code Book(ECB)
90 (+++) Cipher Block Chaining (CBC)
91 (##) keys length supported :64-bit, 128-bit and 192-bit.
92 (#) The advanced encryption standard (AES) supported by CRYP1 & TinyAES IP:
93 (##)128-bit data block processing
94 (##) chaining modes supported :
95 (+++) Electronic Code Book(ECB)
96 (+++) Cipher Block Chaining (CBC)
97 (+++) Counter mode (CTR)
98 (+++) Galois/counter mode (GCM/GMAC)
99 (+++) Counter with Cipher Block Chaining-Message(CCM)
100 (##) keys length Supported :
101 (+++) for CRYP1 IP: 128-bit, 192-bit and 256-bit.
102 (+++) for TinyAES IP: 128-bit and 256-bit
103
104 [..] This section describes the AES Galois/counter mode (GCM) supported by both CRYP1 IP:
105 (#) Algorithm supported :
106 (##) Galois/counter mode (GCM)
107 (##) Galois message authentication code (GMAC) :is exactly the same as
108 GCM algorithm composed only by an header.
109 (#) Four phases are performed in GCM :
110 (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
111 (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
112 computation only.
113 (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
114 encryption + data XORing. It works in a similar way for ciphertext (C).
115 (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
116 (#) structure of message construction in GCM is defined as below :
117 (##) 16 bytes Initial Counter Block (ICB)composed of IV and counter
118 (##) The authenticated header A (also knows as Additional Authentication Data AAD)
119 this part of the message is only authenticated, not encrypted.
120 (##) The plaintext message P is both authenticated and encrypted as ciphertext.
121 GCM standard specifies that ciphertext has same bit length as the plaintext.
122 (##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext
123 (on 64 bits)
124
125 [..] This section describe The AES Counter with Cipher Block Chaining-Message
126 Authentication Code (CCM) supported by both CRYP1 IP:
127 (#) Specific parameters for CCM :
128
129 (##) B0 block : According to NIST Special Publication 800-38C,
130 The first block B0 is formatted as follows, where l(m) is encoded in
131 most-significant-byte first order(see below table 3)
132
133 (+++) Q: a bit string representation of the octet length of P (plaintext)
134 (+++) q The octet length of the binary representation of the octet length of the payload
135 (+++) A nonce (N), n The octet length of the where n+q=15.
136 (+++) Flags: most significant octet containing four flags for control information,
137 (+++) t The octet length of the MAC.
138 (##) B1 block (header) : associated data length(a) concatenated with Associated Data (A)
139 the associated data length expressed in bytes (a) defined as below:
140 (+++) If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets
141 (+++) If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six octets
142 (+++) If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten octets
143 (##) CTRx block : control blocks
144 (+++) Generation of CTR1 from first block B0 information :
145 equal to B0 with first 5 bits zeroed and most significant bits storing octet
146 length of P also zeroed, then incremented by one ( see below Table 4)
147 (+++) Generation of CTR0: same as CTR1 with bit[0] set to zero.
148
149 (#) Four phases are performed in CCM for CRYP1 IP:
150 (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
151 (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
152 computation only.
153 (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
154 encryption + data XORing. It works in a similar way for ciphertext (C).
155 (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
156
157 *** Callback registration ***
158 =============================================
159
160 The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
161 allows the user to configure dynamically the driver callbacks.
162 Use Functions HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
163 to register an interrupt callback.
164
165 Function HAL_CRYP_RegisterCallback() allows to register following callbacks:
166 (+) InCpltCallback : Input FIFO transfer completed callback.
167 (+) OutCpltCallback : Output FIFO transfer completed callback.
168 (+) ErrorCallback : callback for error detection.
169 (+) MspInitCallback : CRYP MspInit.
170 (+) MspDeInitCallback : CRYP MspDeInit.
171 This function takes as parameters the HAL peripheral handle, the Callback ID
172 and a pointer to the user callback function.
173
174 Use function HAL_CRYP_UnRegisterCallback() to reset a callback to the default
175 weak function.
176 HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
177 and the Callback ID.
178 This function allows to reset following callbacks:
179 (+) InCpltCallback : Input FIFO transfer completed callback.
180 (+) OutCpltCallback : Output FIFO transfer completed callback.
181 (+) ErrorCallback : callback for error detection.
182 (+) MspInitCallback : CRYP MspInit.
183 (+) MspDeInitCallback : CRYP MspDeInit.
184
185 By default, after the HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
186 all callbacks are set to the corresponding weak functions :
187 examples HAL_CRYP_InCpltCallback() , HAL_CRYP_OutCpltCallback().
188 Exception done for MspInit and MspDeInit functions that are
189 reset to the legacy weak function in the HAL_CRYP_Init()/ HAL_CRYP_DeInit() only when
190 these callbacks are null (not registered beforehand).
191 if not, MspInit or MspDeInit are not null, the HAL_CRYP_Init() / HAL_CRYP_DeInit()
192 keep and use the user MspInit/MspDeInit functions (registered beforehand)
193
194 Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only.
195 Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
196 in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
197 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
198 In that case first register the MspInit/MspDeInit user callbacks
199 using HAL_CRYP_RegisterCallback() before calling HAL_CRYP_DeInit()
200 or HAL_CRYP_Init() function.
201
202 When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
203 not defined, the callback registration feature is not available and all callbacks
204 are set to the corresponding weak functions.
205
206 Table 1. Initial Counter Block (ICB)
207 +-------------------------------------------------------+
208 | Initialization vector (IV) | Counter |
209 |----------------|----------------|-----------|---------|
210 127 95 63 31 0
211
212
213 Bit Number Register Contents
214 ---------- --------------- -----------
215 127 ...96 CRYP_IV1R[31:0] ICB[127:96]
216 95 ...64 CRYP_IV1L[31:0] B0[95:64]
217 63 ... 32 CRYP_IV0R[31:0] ICB[63:32]
218 31 ... 0 CRYP_IV0L[31:0] ICB[31:0], where 32-bit counter= 0x2
219
220 Table 2. GCM last block definition
221
222 +-------------------------------------------------------------------+
223 | Bit[0] | Bit[32] | Bit[64] | Bit[96] |
224 |-----------|--------------------|-----------|----------------------|
225 | 0x0 | Header length[31:0]| 0x0 | Payload length[31:0] |
226 |-----------|--------------------|-----------|----------------------|
227
228 Table 3. B0 block
229 Octet Number Contents
230 ------------ ---------
231 0 Flags
232 1 ... 15-q Nonce N
233 16-q ... 15 Q
234
235 the Flags field is formatted as follows:
236
237 Bit Number Contents
238 ---------- ----------------------
239 7 Reserved (always zero)
240 6 Adata
241 5 ... 3 (t-2)/2
242 2 ... 0 [q-1]3
243
244 Table 4. CTRx block
245 Bit Number Register Contents
246 ---------- --------------- -----------
247 127 ...96 CRYP_IV1R[31:0] B0[127:96], where Q length bits are set to 0, except for
248 bit 0 that is set to 1
249 95 ...64 CRYP_IV1L[31:0] B0[95:64]
250 63 ... 32 CRYP_IV0R[31:0] B0[63:32]
251 31 ... 0 CRYP_IV0L[31:0] B0[31:0], where flag bits set to 0
252
253 @endverbatim
254 ******************************************************************************
255 */
256
257 /* Includes ------------------------------------------------------------------*/
258 #include "stm32f7xx_hal.h"
259
260 /** @addtogroup STM32F7xx_HAL_Driver
261 * @{
262 */
263
264 #if defined (AES) || defined (CRYP)
265
266 /** @defgroup CRYP CRYP
267 * @brief CRYP HAL module driver.
268 * @{
269 */
270
271
272 #ifdef HAL_CRYP_MODULE_ENABLED
273
274 /* Private typedef -----------------------------------------------------------*/
275 /* Private define ------------------------------------------------------------*/
276 /** @addtogroup CRYP_Private_Defines
277 * @{
278 */
279 #define CRYP_TIMEOUT_KEYPREPARATION 82U /*The latency of key preparation operation is 82 clock cycles.*/
280 #define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/
281 #define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/
282
283 #define CRYP_PHASE_READY 0x00000001U /*!< CRYP peripheral is ready for initialization. */
284 #define CRYP_PHASE_PROCESS 0x00000002U /*!< CRYP peripheral is in processing phase */
285
286 #if defined(AES)
287 #define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode(Mode 1) */
288 #define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode only used when performing ECB and CBC decryptions (Mode 2) */
289 #define CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1 /*!< Decryption (Mode 3) */
290 #define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE /*!< Key derivation and decryption only used when performing ECB and CBC decryptions (Mode 4) */
291 #define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
292 #define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */
293 #define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */
294 #define CRYP_PHASE_FINAL AES_CR_GCMPH /*!< GCM/GMAC or CCM final phase */
295 #else /* CRYP */
296 #define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
297 #define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0 /*!< GCM/GMAC or CCM header phase */
298 #define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1 /*!< GCM(/CCM) payload phase */
299 #define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH /*!< GCM/GMAC or CCM final phase */
300 #define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode */
301 #define CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR /*!< Decryption */
302 #endif /* End CRYP or AES */
303
304 /* CTR1 information to use in CCM algorithm */
305 #define CRYP_CCM_CTR1_0 0x07FFFFFFU
306 #define CRYP_CCM_CTR1_1 0xFFFFFF00U
307 #define CRYP_CCM_CTR1_2 0x00000001U
308
309
310 /**
311 * @}
312 */
313
314
315 /* Private macro -------------------------------------------------------------*/
316 /** @addtogroup CRYP_Private_Macros
317 * @{
318 */
319
320 #if defined(CRYP)
321
322 #define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
323 (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
324 }while(0)
325
326 #define HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)
327
328 #else /*AES*/
329 #define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~AES_CR_GCMPH);\
330 (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
331 }while(0)
332 #endif /* End AES or CRYP*/
333
334
335 /**
336 * @}
337 */
338
339 /* Private struct -------------------------------------------------------------*/
340 /* Private variables ---------------------------------------------------------*/
341 /* Private function prototypes -----------------------------------------------*/
342 /** @addtogroup CRYP_Private_Functions_prototypes
343 * @{
344 */
345
346 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
347 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
348 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
349 static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
350 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize);
351 static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp);
352
353 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
354 static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp);
355 static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp);
356 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp);
357 static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
358 static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
359 static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp);
360 static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
361 static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
362 static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp);
363 static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
364
365 static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcrypt, uint32_t Timeout);
366 static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
367 static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
368 static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp);
369 static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp);
370 static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp);
371 #if defined (CRYP)
372 static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp);
373
374 static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
375
376 static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
377 static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
378 static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
379 #else /*AES*/
380 static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
381 #endif /* End CRYP or AES */
382
383 /**
384 * @}
385 */
386
387 /* Exported functions ---------------------------------------------------------*/
388
389 /** @defgroup CRYP_Exported_Functions CRYP Exported Functions
390 * @{
391 */
392
393
394 /** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
395 * @brief Initialization and Configuration functions.
396 *
397 @verbatim
398 ========================================================================================
399 ##### Initialization, de-initialization and Set and Get configuration functions #####
400 ========================================================================================
401 [..] This section provides functions allowing to:
402 (+) Initialize the CRYP
403 (+) DeInitialize the CRYP
404 (+) Initialize the CRYP MSP
405 (+) DeInitialize the CRYP MSP
406 (+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef
407 Parameters which are configured in This section are :
408 (+) Key size
409 (+) Data Type : 32,16, 8 or 1bit
410 (+) AlgoMode :
411 - for CRYP1 IP :
412 ECB and CBC in DES/TDES Standard
413 ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
414 - for TinyAES2 IP, only ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard are supported.
415 (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef
416
417
418 @endverbatim
419 * @{
420 */
421
422
423 /**
424 * @brief Initializes the CRYP according to the specified
425 * parameters in the CRYP_ConfigTypeDef and creates the associated handle.
426 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
427 * the configuration information for CRYP module
428 * @retval HAL status
429 */
HAL_CRYP_Init(CRYP_HandleTypeDef * hcryp)430 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
431 {
432 /* Check the CRYP handle allocation */
433 if (hcryp == NULL)
434 {
435 return HAL_ERROR;
436 }
437
438 /* Check parameters */
439 assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
440 assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
441 assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm));
442 assert_param(IS_CRYP_INIT(hcryp->Init.KeyIVConfigSkip));
443
444 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
445 if (hcryp->State == HAL_CRYP_STATE_RESET)
446 {
447 /* Allocate lock resource and initialize it */
448 hcryp->Lock = HAL_UNLOCKED;
449
450 hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
451 hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
452 hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
453
454 if (hcryp->MspInitCallback == NULL)
455 {
456 hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy weak MspInit */
457 }
458
459 /* Init the low level hardware */
460 hcryp->MspInitCallback(hcryp);
461 }
462 #else
463 if (hcryp->State == HAL_CRYP_STATE_RESET)
464 {
465 /* Allocate lock resource and initialize it */
466 hcryp->Lock = HAL_UNLOCKED;
467
468 /* Init the low level hardware */
469 HAL_CRYP_MspInit(hcryp);
470 }
471 #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
472
473 /* Set the key size(This bit field is don't care in the DES or TDES modes) data type and Algorithm */
474 #if defined (CRYP)
475
476 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
477 hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
478
479 #else /*AES*/
480
481 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD,
482 hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
483
484 #endif /* End AES or CRYP*/
485
486 /* Reset Error Code field */
487 hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
488
489 /* Change the CRYP state */
490 hcryp->State = HAL_CRYP_STATE_READY;
491
492 /* Set the default CRYP phase */
493 hcryp->Phase = CRYP_PHASE_READY;
494
495 /* Return function status */
496 return HAL_OK;
497 }
498
499 /**
500 * @brief De-Initializes the CRYP peripheral.
501 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
502 * the configuration information for CRYP module
503 * @retval HAL status
504 */
HAL_CRYP_DeInit(CRYP_HandleTypeDef * hcryp)505 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
506 {
507 /* Check the CRYP handle allocation */
508 if (hcryp == NULL)
509 {
510 return HAL_ERROR;
511 }
512
513 /* Set the default CRYP phase */
514 hcryp->Phase = CRYP_PHASE_READY;
515
516 /* Reset CrypInCount and CrypOutCount */
517 hcryp->CrypInCount = 0;
518 hcryp->CrypOutCount = 0;
519 hcryp->CrypHeaderCount = 0;
520
521 /* Disable the CRYP peripheral clock */
522 __HAL_CRYP_DISABLE(hcryp);
523
524 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
525
526 if (hcryp->MspDeInitCallback == NULL)
527 {
528 hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy weak MspDeInit */
529 }
530 /* DeInit the low level hardware */
531 hcryp->MspDeInitCallback(hcryp);
532
533 #else
534
535 /* DeInit the low level hardware: CLOCK, NVIC.*/
536 HAL_CRYP_MspDeInit(hcryp);
537
538 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
539
540 /* Change the CRYP state */
541 hcryp->State = HAL_CRYP_STATE_RESET;
542
543 /* Release Lock */
544 __HAL_UNLOCK(hcryp);
545
546 /* Return function status */
547 return HAL_OK;
548 }
549
550 /**
551 * @brief Configure the CRYP according to the specified
552 * parameters in the CRYP_ConfigTypeDef
553 * @param hcryp: pointer to a CRYP_HandleTypeDef structure
554 * @param pConf: pointer to a CRYP_ConfigTypeDef structure that contains
555 * the configuration information for CRYP module
556 * @retval HAL status
557 */
HAL_CRYP_SetConfig(CRYP_HandleTypeDef * hcryp,CRYP_ConfigTypeDef * pConf)558 HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
559 {
560 /* Check the CRYP handle allocation */
561 if ((hcryp == NULL) || (pConf == NULL))
562 {
563 return HAL_ERROR;
564 }
565
566 /* Check parameters */
567 assert_param(IS_CRYP_KEYSIZE(pConf->KeySize));
568 assert_param(IS_CRYP_DATATYPE(pConf->DataType));
569 assert_param(IS_CRYP_ALGORITHM(pConf->Algorithm));
570
571 if (hcryp->State == HAL_CRYP_STATE_READY)
572 {
573 /* Change the CRYP state */
574 hcryp->State = HAL_CRYP_STATE_BUSY;
575
576 /* Process locked */
577 __HAL_LOCK(hcryp);
578
579 /* Set CRYP parameters */
580 hcryp->Init.DataType = pConf->DataType;
581 hcryp->Init.pKey = pConf->pKey;
582 hcryp->Init.Algorithm = pConf->Algorithm;
583 hcryp->Init.KeySize = pConf->KeySize;
584 hcryp->Init.pInitVect = pConf->pInitVect;
585 hcryp->Init.Header = pConf->Header;
586 hcryp->Init.HeaderSize = pConf->HeaderSize;
587 hcryp->Init.B0 = pConf->B0;
588 hcryp->Init.DataWidthUnit = pConf->DataWidthUnit;
589 hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip;
590 hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit;
591
592 /* Set the key size(This bit field is don't care in the DES or TDES modes) data type, AlgoMode and operating mode*/
593 #if defined (CRYP)
594
595 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
596 hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
597
598 #else /*AES*/
599 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD,
600 hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
601
602 /*clear error flags*/
603 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR);
604
605 #endif /* End AES or CRYP */
606
607 /* Process Unlocked */
608 __HAL_UNLOCK(hcryp);
609
610 /* Reset Error Code field */
611 hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
612
613 /* Change the CRYP state */
614 hcryp->State = HAL_CRYP_STATE_READY;
615
616 /* Set the default CRYP phase */
617 hcryp->Phase = CRYP_PHASE_READY;
618
619 /* Return function status */
620 return HAL_OK;
621 }
622 else
623 {
624 /* Process Unlocked */
625 __HAL_UNLOCK(hcryp);
626
627 /* Busy error code field */
628 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
629 return HAL_ERROR;
630 }
631 }
632
633 /**
634 * @brief Get CRYP Configuration parameters in associated handle.
635 * @param pConf: pointer to a CRYP_ConfigTypeDef structure
636 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
637 * the configuration information for CRYP module
638 * @retval HAL status
639 */
HAL_CRYP_GetConfig(CRYP_HandleTypeDef * hcryp,CRYP_ConfigTypeDef * pConf)640 HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
641 {
642 /* Check the CRYP handle allocation */
643 if ((hcryp == NULL) || (pConf == NULL))
644 {
645 return HAL_ERROR;
646 }
647
648 if (hcryp->State == HAL_CRYP_STATE_READY)
649 {
650 /* Change the CRYP state */
651 hcryp->State = HAL_CRYP_STATE_BUSY;
652
653 /* Process locked */
654 __HAL_LOCK(hcryp);
655
656 /* Get CRYP parameters */
657 pConf->DataType = hcryp->Init.DataType;
658 pConf->pKey = hcryp->Init.pKey;
659 pConf->Algorithm = hcryp->Init.Algorithm;
660 pConf->KeySize = hcryp->Init.KeySize ;
661 pConf->pInitVect = hcryp->Init.pInitVect;
662 pConf->Header = hcryp->Init.Header ;
663 pConf->HeaderSize = hcryp->Init.HeaderSize;
664 pConf->B0 = hcryp->Init.B0;
665 pConf->DataWidthUnit = hcryp->Init.DataWidthUnit;
666 pConf->KeyIVConfigSkip = hcryp->Init.KeyIVConfigSkip;
667 pConf->HeaderWidthUnit = hcryp->Init.HeaderWidthUnit;
668
669 /* Process Unlocked */
670 __HAL_UNLOCK(hcryp);
671
672 /* Change the CRYP state */
673 hcryp->State = HAL_CRYP_STATE_READY;
674
675 /* Return function status */
676 return HAL_OK;
677 }
678 else
679 {
680 /* Process Unlocked */
681 __HAL_UNLOCK(hcryp);
682
683 /* Busy error code field */
684 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
685 return HAL_ERROR;
686 }
687 }
688 /**
689 * @brief Initializes the CRYP MSP.
690 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
691 * the configuration information for CRYP module
692 * @retval None
693 */
HAL_CRYP_MspInit(CRYP_HandleTypeDef * hcryp)694 __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
695 {
696 /* Prevent unused argument(s) compilation warning */
697 UNUSED(hcryp);
698
699 /* NOTE : This function should not be modified, when the callback is needed,
700 the HAL_CRYP_MspInit can be implemented in the user file
701 */
702 }
703
704 /**
705 * @brief DeInitializes CRYP MSP.
706 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
707 * the configuration information for CRYP module
708 * @retval None
709 */
HAL_CRYP_MspDeInit(CRYP_HandleTypeDef * hcryp)710 __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
711 {
712 /* Prevent unused argument(s) compilation warning */
713 UNUSED(hcryp);
714
715 /* NOTE : This function should not be modified, when the callback is needed,
716 the HAL_CRYP_MspDeInit can be implemented in the user file
717 */
718 }
719
720 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
721 /**
722 * @brief Register a User CRYP Callback
723 * To be used instead of the weak predefined callback
724 * @param hcryp cryp handle
725 * @param CallbackID ID of the callback to be registered
726 * This parameter can be one of the following values:
727 * @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
728 * @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
729 * @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
730 * @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
731 * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
732 * @param pCallback pointer to the Callback function
733 * @retval status
734 */
HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef * hcryp,HAL_CRYP_CallbackIDTypeDef CallbackID,pCRYP_CallbackTypeDef pCallback)735 HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
736 pCRYP_CallbackTypeDef pCallback)
737 {
738 HAL_StatusTypeDef status = HAL_OK;
739
740 if (pCallback == NULL)
741 {
742 /* Update the error code */
743 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
744
745 return HAL_ERROR;
746 }
747 /* Process locked */
748 __HAL_LOCK(hcryp);
749
750 if (hcryp->State == HAL_CRYP_STATE_READY)
751 {
752 switch (CallbackID)
753 {
754 case HAL_CRYP_INPUT_COMPLETE_CB_ID :
755 hcryp->InCpltCallback = pCallback;
756 break;
757
758 case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
759 hcryp->OutCpltCallback = pCallback;
760 break;
761
762 case HAL_CRYP_ERROR_CB_ID :
763 hcryp->ErrorCallback = pCallback;
764 break;
765
766 case HAL_CRYP_MSPINIT_CB_ID :
767 hcryp->MspInitCallback = pCallback;
768 break;
769
770 case HAL_CRYP_MSPDEINIT_CB_ID :
771 hcryp->MspDeInitCallback = pCallback;
772 break;
773
774 default :
775 /* Update the error code */
776 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
777 /* Return error status */
778 status = HAL_ERROR;
779 break;
780 }
781 }
782 else if (hcryp->State == HAL_CRYP_STATE_RESET)
783 {
784 switch (CallbackID)
785 {
786 case HAL_CRYP_MSPINIT_CB_ID :
787 hcryp->MspInitCallback = pCallback;
788 break;
789
790 case HAL_CRYP_MSPDEINIT_CB_ID :
791 hcryp->MspDeInitCallback = pCallback;
792 break;
793
794 default :
795 /* Update the error code */
796 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
797 /* Return error status */
798 status = HAL_ERROR;
799 break;
800 }
801 }
802 else
803 {
804 /* Update the error code */
805 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
806 /* Return error status */
807 status = HAL_ERROR;
808 }
809
810 /* Release Lock */
811 __HAL_UNLOCK(hcryp);
812
813 return status;
814 }
815
816 /**
817 * @brief Unregister an CRYP Callback
818 * CRYP callback is redirected to the weak predefined callback
819 * @param hcryp cryp handle
820 * @param CallbackID ID of the callback to be unregistered
821 * This parameter can be one of the following values:
822 * @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
823 * @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
824 * @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
825 * @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
826 * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
827 * @retval status
828 */
HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef * hcryp,HAL_CRYP_CallbackIDTypeDef CallbackID)829 HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
830 {
831 HAL_StatusTypeDef status = HAL_OK;
832
833 /* Process locked */
834 __HAL_LOCK(hcryp);
835
836 if (hcryp->State == HAL_CRYP_STATE_READY)
837 {
838 switch (CallbackID)
839 {
840 case HAL_CRYP_INPUT_COMPLETE_CB_ID :
841 hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
842 break;
843
844 case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
845 hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
846 break;
847
848 case HAL_CRYP_ERROR_CB_ID :
849 hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
850 break;
851
852 case HAL_CRYP_MSPINIT_CB_ID :
853 hcryp->MspInitCallback = HAL_CRYP_MspInit;
854 break;
855
856 case HAL_CRYP_MSPDEINIT_CB_ID :
857 hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
858 break;
859
860 default :
861 /* Update the error code */
862 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
863 /* Return error status */
864 status = HAL_ERROR;
865 break;
866 }
867 }
868 else if (hcryp->State == HAL_CRYP_STATE_RESET)
869 {
870 switch (CallbackID)
871 {
872 case HAL_CRYP_MSPINIT_CB_ID :
873 hcryp->MspInitCallback = HAL_CRYP_MspInit;
874 break;
875
876 case HAL_CRYP_MSPDEINIT_CB_ID :
877 hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
878 break;
879
880 default :
881 /* Update the error code */
882 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
883 /* Return error status */
884 status = HAL_ERROR;
885 break;
886 }
887 }
888 else
889 {
890 /* Update the error code */
891 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
892 /* Return error status */
893 status = HAL_ERROR;
894 }
895
896 /* Release Lock */
897 __HAL_UNLOCK(hcryp);
898
899 return status;
900 }
901 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
902 /**
903 * @}
904 */
905
906 /** @defgroup CRYP_Exported_Functions_Group2 Encrypt Decrypt functions
907 * @brief processing functions.
908 *
909 @verbatim
910 ==============================================================================
911 ##### Encrypt Decrypt functions #####
912 ==============================================================================
913 [..] This section provides API allowing to Encrypt/Decrypt Data following
914 Standard DES/TDES or AES, and Algorithm configured by the user:
915 (+) Standard DES/TDES only supported by CRYP1 IP, below list of Algorithm supported :
916 - Electronic Code Book(ECB)
917 - Cipher Block Chaining (CBC)
918 (+) Standard AES supported by CRYP1 IP & TinyAES, list of Algorithm supported:
919 - Electronic Code Book(ECB)
920 - Cipher Block Chaining (CBC)
921 - Counter mode (CTR)
922 - Cipher Block Chaining (CBC)
923 - Counter mode (CTR)
924 - Galois/counter mode (GCM)
925 - Counter with Cipher Block Chaining-Message(CCM)
926 [..] Three processing functions are available:
927 (+) Polling mode : HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
928 (+) Interrupt mode : HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
929 (+) DMA mode : HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
930
931 @endverbatim
932 * @{
933 */
934
935
936 /**
937 * @brief Encryption mode.
938 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
939 * the configuration information for CRYP module
940 * @param Input: Pointer to the input buffer (plaintext)
941 * @param Size: Length of the plaintext buffer in word.
942 * @param Output: Pointer to the output buffer(ciphertext)
943 * @param Timeout: Specify Timeout value
944 * @retval HAL status
945 */
HAL_CRYP_Encrypt(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output,uint32_t Timeout)946 HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
947 uint32_t Timeout)
948 {
949 uint32_t algo;
950 HAL_StatusTypeDef status;
951
952 if (hcryp->State == HAL_CRYP_STATE_READY)
953 {
954 /* Change state Busy */
955 hcryp->State = HAL_CRYP_STATE_BUSY;
956
957 /* Process locked */
958 __HAL_LOCK(hcryp);
959
960 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
961 hcryp->CrypInCount = 0U;
962 hcryp->CrypOutCount = 0U;
963 hcryp->pCrypInBuffPtr = Input;
964 hcryp->pCrypOutBuffPtr = Output;
965
966 /* Calculate Size parameter in Byte*/
967 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
968 {
969 hcryp->Size = Size * 4U;
970 }
971 else
972 {
973 hcryp->Size = Size;
974 }
975
976 #if defined (CRYP)
977 /* Set Encryption operating mode*/
978 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
979
980 /* algo get algorithm selected */
981 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
982
983 switch (algo)
984 {
985 case CRYP_DES_ECB:
986 case CRYP_DES_CBC:
987 case CRYP_TDES_ECB:
988 case CRYP_TDES_CBC:
989
990 /*Set Key */
991 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
992 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
993 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
994 {
995 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
996 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
997 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
998 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
999 }
1000
1001 /*Set Initialization Vector (IV)*/
1002 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1003 {
1004 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1005 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1006 }
1007
1008 /* Flush FIFO */
1009 HAL_CRYP_FIFO_FLUSH(hcryp);
1010
1011 /* Set the phase */
1012 hcryp->Phase = CRYP_PHASE_PROCESS;
1013
1014 /* Start DES/TDES encryption process */
1015 status = CRYP_TDES_Process(hcryp, Timeout);
1016 break;
1017
1018 case CRYP_AES_ECB:
1019 case CRYP_AES_CBC:
1020 case CRYP_AES_CTR:
1021
1022 /* AES encryption */
1023 status = CRYP_AES_Encrypt(hcryp, Timeout);
1024 break;
1025
1026 case CRYP_AES_GCM:
1027
1028 /* AES GCM encryption */
1029 status = CRYP_AESGCM_Process(hcryp, Timeout);
1030
1031 break;
1032
1033 case CRYP_AES_CCM:
1034
1035 /* AES CCM encryption */
1036 status = CRYP_AESCCM_Process(hcryp, Timeout);
1037 break;
1038
1039 default:
1040 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1041 /* Change the CRYP peripheral state */
1042 hcryp->State = HAL_CRYP_STATE_READY;
1043 /* Process unlocked */
1044 __HAL_UNLOCK(hcryp);
1045 return HAL_ERROR;
1046 }
1047
1048 #else /*AES*/
1049
1050 /* Set the operating mode*/
1051 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
1052
1053 /* algo get algorithm selected */
1054 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1055
1056 switch (algo)
1057 {
1058
1059 case CRYP_AES_ECB:
1060 case CRYP_AES_CBC:
1061 case CRYP_AES_CTR:
1062
1063 /* AES encryption */
1064 status = CRYP_AES_Encrypt(hcryp, Timeout);
1065 break;
1066
1067 case CRYP_AES_GCM_GMAC:
1068
1069 /* AES GCM encryption */
1070 status = CRYP_AESGCM_Process(hcryp, Timeout) ;
1071 break;
1072
1073 case CRYP_AES_CCM:
1074
1075 /* AES CCM encryption */
1076 status = CRYP_AESCCM_Process(hcryp, Timeout);
1077 break;
1078
1079 default:
1080 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1081 /* Change the CRYP peripheral state */
1082 hcryp->State = HAL_CRYP_STATE_READY;
1083 /* Process unlocked */
1084 __HAL_UNLOCK(hcryp);
1085 return HAL_ERROR;
1086 }
1087 #endif /*end AES or CRYP */
1088
1089 if (status == HAL_OK)
1090 {
1091 /* Change the CRYP peripheral state */
1092 hcryp->State = HAL_CRYP_STATE_READY;
1093
1094 /* Process unlocked */
1095 __HAL_UNLOCK(hcryp);
1096 }
1097 }
1098 else
1099 {
1100 /* Busy error code field */
1101 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1102 return HAL_ERROR;
1103 }
1104
1105 /* Return function status */
1106 return HAL_OK;
1107 }
1108
1109 /**
1110 * @brief Decryption mode.
1111 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1112 * the configuration information for CRYP module
1113 * @param Input: Pointer to the input buffer (ciphertext )
1114 * @param Size: Length of the plaintext buffer in word.
1115 * @param Output: Pointer to the output buffer(plaintext)
1116 * @param Timeout: Specify Timeout value
1117 * @retval HAL status
1118 */
HAL_CRYP_Decrypt(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output,uint32_t Timeout)1119 HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
1120 uint32_t Timeout)
1121 {
1122 HAL_StatusTypeDef status;
1123 uint32_t algo;
1124
1125 if (hcryp->State == HAL_CRYP_STATE_READY)
1126 {
1127 /* Change state Busy */
1128 hcryp->State = HAL_CRYP_STATE_BUSY;
1129
1130 /* Process locked */
1131 __HAL_LOCK(hcryp);
1132
1133 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
1134 hcryp->CrypInCount = 0U;
1135 hcryp->CrypOutCount = 0U;
1136 hcryp->pCrypInBuffPtr = Input;
1137 hcryp->pCrypOutBuffPtr = Output;
1138
1139 /* Calculate Size parameter in Byte*/
1140 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1141 {
1142 hcryp->Size = Size * 4U;
1143 }
1144 else
1145 {
1146 hcryp->Size = Size;
1147 }
1148
1149 #if defined (CRYP)
1150
1151 /* Set Decryption operating mode*/
1152 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
1153
1154 /* algo get algorithm selected */
1155 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1156
1157 switch (algo)
1158 {
1159 case CRYP_DES_ECB:
1160 case CRYP_DES_CBC:
1161 case CRYP_TDES_ECB:
1162 case CRYP_TDES_CBC:
1163
1164 /*Set Key */
1165 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1166 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1167 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1168 {
1169 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1170 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1171 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1172 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1173 }
1174
1175 /*Set Initialization Vector (IV)*/
1176 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1177 {
1178 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1179 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1180 }
1181
1182 /* Flush FIFO */
1183 HAL_CRYP_FIFO_FLUSH(hcryp);
1184
1185 /* Set the phase */
1186 hcryp->Phase = CRYP_PHASE_PROCESS;
1187
1188 /* Start DES/TDES decryption process */
1189 status = CRYP_TDES_Process(hcryp, Timeout);
1190
1191 break;
1192
1193 case CRYP_AES_ECB:
1194 case CRYP_AES_CBC:
1195 case CRYP_AES_CTR:
1196
1197 /* AES decryption */
1198 status = CRYP_AES_Decrypt(hcryp, Timeout);
1199 break;
1200
1201 case CRYP_AES_GCM:
1202
1203 /* AES GCM decryption */
1204 status = CRYP_AESGCM_Process(hcryp, Timeout) ;
1205 break;
1206
1207 case CRYP_AES_CCM:
1208
1209 /* AES CCM decryption */
1210 status = CRYP_AESCCM_Process(hcryp, Timeout);
1211 break;
1212
1213 default:
1214 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1215 /* Change the CRYP peripheral state */
1216 hcryp->State = HAL_CRYP_STATE_READY;
1217 /* Process unlocked */
1218 __HAL_UNLOCK(hcryp);
1219 return HAL_ERROR;
1220 }
1221
1222 #else /*AES*/
1223
1224 /* Set Decryption operating mode*/
1225 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
1226
1227 /* algo get algorithm selected */
1228 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1229
1230 switch (algo)
1231 {
1232
1233 case CRYP_AES_ECB:
1234 case CRYP_AES_CBC:
1235 case CRYP_AES_CTR:
1236
1237 /* AES decryption */
1238 status = CRYP_AES_Decrypt(hcryp, Timeout);
1239 break;
1240
1241 case CRYP_AES_GCM_GMAC:
1242
1243 /* AES GCM decryption */
1244 status = CRYP_AESGCM_Process(hcryp, Timeout) ;
1245 break;
1246
1247 case CRYP_AES_CCM:
1248
1249 /* AES CCM decryption */
1250 status = CRYP_AESCCM_Process(hcryp, Timeout);
1251 break;
1252
1253 default:
1254 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1255 /* Change the CRYP peripheral state */
1256 hcryp->State = HAL_CRYP_STATE_READY;
1257 /* Process unlocked */
1258 __HAL_UNLOCK(hcryp);
1259 return HAL_ERROR;
1260 }
1261 #endif /* End AES or CRYP */
1262
1263 if (status == HAL_OK)
1264 {
1265 /* Change the CRYP peripheral state */
1266 hcryp->State = HAL_CRYP_STATE_READY;
1267
1268 /* Process unlocked */
1269 __HAL_UNLOCK(hcryp);
1270 }
1271 }
1272 else
1273 {
1274 /* Busy error code field */
1275 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1276 return HAL_ERROR;
1277 }
1278
1279 /* Return function status */
1280 return HAL_OK;
1281 }
1282
1283 /**
1284 * @brief Encryption in interrupt mode.
1285 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1286 * the configuration information for CRYP module
1287 * @param Input: Pointer to the input buffer (plaintext)
1288 * @param Size: Length of the plaintext buffer in word
1289 * @param Output: Pointer to the output buffer(ciphertext)
1290 * @retval HAL status
1291 */
HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output)1292 HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1293 {
1294 uint32_t algo;
1295 HAL_StatusTypeDef status = HAL_OK;
1296
1297 if (hcryp->State == HAL_CRYP_STATE_READY)
1298 {
1299 /* Change state Busy */
1300 hcryp->State = HAL_CRYP_STATE_BUSY;
1301
1302 /* Process locked */
1303 __HAL_LOCK(hcryp);
1304
1305 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
1306 hcryp->CrypInCount = 0U;
1307 hcryp->CrypOutCount = 0U;
1308 hcryp->pCrypInBuffPtr = Input;
1309 hcryp->pCrypOutBuffPtr = Output;
1310
1311 /* Calculate Size parameter in Byte*/
1312 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1313 {
1314 hcryp->Size = Size * 4U;
1315 }
1316 else
1317 {
1318 hcryp->Size = Size;
1319 }
1320
1321 #if defined (CRYP)
1322
1323 /* Set encryption operating mode*/
1324 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
1325
1326 /* algo get algorithm selected */
1327 algo = (hcryp->Instance->CR & CRYP_CR_ALGOMODE);
1328
1329 switch (algo)
1330 {
1331 case CRYP_DES_ECB:
1332 case CRYP_DES_CBC:
1333 case CRYP_TDES_ECB:
1334 case CRYP_TDES_CBC:
1335
1336 /*Set Key */
1337 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1338 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1339 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1340 {
1341 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1342 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1343 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1344 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1345 }
1346 /* Set the Initialization Vector*/
1347 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1348 {
1349 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1350 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1351 }
1352
1353 /* Flush FIFO */
1354 HAL_CRYP_FIFO_FLUSH(hcryp);
1355
1356 /* Set the phase */
1357 hcryp->Phase = CRYP_PHASE_PROCESS;
1358
1359 /* Enable interrupts */
1360 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
1361
1362 /* Enable CRYP to start DES/TDES process*/
1363 __HAL_CRYP_ENABLE(hcryp);
1364 break;
1365
1366 case CRYP_AES_ECB:
1367 case CRYP_AES_CBC:
1368 case CRYP_AES_CTR:
1369
1370 status = CRYP_AES_Encrypt_IT(hcryp);
1371 break;
1372
1373 case CRYP_AES_GCM:
1374
1375 status = CRYP_AESGCM_Process_IT(hcryp) ;
1376 break;
1377
1378 case CRYP_AES_CCM:
1379
1380 status = CRYP_AESCCM_Process_IT(hcryp);
1381 break;
1382
1383 default:
1384 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1385 /* Change the CRYP peripheral state */
1386 hcryp->State = HAL_CRYP_STATE_READY;
1387 /* Process unlocked */
1388 __HAL_UNLOCK(hcryp);
1389 status = HAL_ERROR;
1390 break;
1391 }
1392
1393 #else /* AES */
1394
1395 /* Set encryption operating mode*/
1396 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
1397
1398 /* algo get algorithm selected */
1399 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1400
1401 switch (algo)
1402 {
1403 case CRYP_AES_ECB:
1404 case CRYP_AES_CBC:
1405 case CRYP_AES_CTR:
1406
1407 /* AES encryption */
1408 status = CRYP_AES_Encrypt_IT(hcryp);
1409 break;
1410
1411 case CRYP_AES_GCM_GMAC:
1412
1413 /* AES GCM encryption */
1414 status = CRYP_AESGCM_Process_IT(hcryp) ;
1415 break;
1416
1417 case CRYP_AES_CCM:
1418
1419 /* AES CCM encryption */
1420 status = CRYP_AESCCM_Process_IT(hcryp);
1421 break;
1422
1423 default:
1424 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1425 /* Change the CRYP peripheral state */
1426 hcryp->State = HAL_CRYP_STATE_READY;
1427 /* Process unlocked */
1428 __HAL_UNLOCK(hcryp);
1429 status = HAL_ERROR;
1430 break;
1431 }
1432 #endif /*end AES or CRYP*/
1433
1434 }
1435 else
1436 {
1437 /* Busy error code field */
1438 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1439 status = HAL_ERROR;
1440 }
1441
1442 /* Return function status */
1443 return status;
1444 }
1445
1446 /**
1447 * @brief Decryption in itnterrupt mode.
1448 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1449 * the configuration information for CRYP module
1450 * @param Input: Pointer to the input buffer (ciphertext )
1451 * @param Size: Length of the plaintext buffer in word.
1452 * @param Output: Pointer to the output buffer(plaintext)
1453 * @retval HAL status
1454 */
HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output)1455 HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1456 {
1457 uint32_t algo;
1458 HAL_StatusTypeDef status = HAL_OK;
1459
1460 if (hcryp->State == HAL_CRYP_STATE_READY)
1461 {
1462 /* Change state Busy */
1463 hcryp->State = HAL_CRYP_STATE_BUSY;
1464
1465 /* Process locked */
1466 __HAL_LOCK(hcryp);
1467
1468 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
1469 hcryp->CrypInCount = 0U;
1470 hcryp->CrypOutCount = 0U;
1471 hcryp->pCrypInBuffPtr = Input;
1472 hcryp->pCrypOutBuffPtr = Output;
1473
1474 /* Calculate Size parameter in Byte*/
1475 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1476 {
1477 hcryp->Size = Size * 4U;
1478 }
1479 else
1480 {
1481 hcryp->Size = Size;
1482 }
1483
1484 #if defined (CRYP)
1485
1486 /* Set decryption operating mode*/
1487 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
1488
1489 /* algo get algorithm selected */
1490 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1491
1492 switch (algo)
1493 {
1494 case CRYP_DES_ECB:
1495 case CRYP_DES_CBC:
1496 case CRYP_TDES_ECB:
1497 case CRYP_TDES_CBC:
1498
1499 /*Set Key */
1500 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1501 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1502 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1503 {
1504 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1505 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1506 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1507 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1508 }
1509
1510 /* Set the Initialization Vector*/
1511 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1512 {
1513 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1514 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1515 }
1516 /* Flush FIFO */
1517 HAL_CRYP_FIFO_FLUSH(hcryp);
1518
1519 /* Set the phase */
1520 hcryp->Phase = CRYP_PHASE_PROCESS;
1521
1522 /* Enable interrupts */
1523 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
1524
1525 /* Enable CRYP and start DES/TDES process*/
1526 __HAL_CRYP_ENABLE(hcryp);
1527
1528 break;
1529
1530 case CRYP_AES_ECB:
1531 case CRYP_AES_CBC:
1532 case CRYP_AES_CTR:
1533
1534 /* AES decryption */
1535 status = CRYP_AES_Decrypt_IT(hcryp);
1536 break;
1537
1538 case CRYP_AES_GCM:
1539
1540 /* AES GCM decryption */
1541 status = CRYP_AESGCM_Process_IT(hcryp) ;
1542 break;
1543
1544 case CRYP_AES_CCM:
1545
1546 /* AES CCMdecryption */
1547 status = CRYP_AESCCM_Process_IT(hcryp);
1548 break;
1549
1550 default:
1551 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1552 /* Change the CRYP peripheral state */
1553 hcryp->State = HAL_CRYP_STATE_READY;
1554 /* Process unlocked */
1555 __HAL_UNLOCK(hcryp);
1556 status = HAL_ERROR;
1557 break;
1558 }
1559
1560 #else /*AES*/
1561
1562 /* Set decryption operating mode*/
1563 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
1564
1565 /* algo get algorithm selected */
1566 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1567
1568 switch (algo)
1569 {
1570 case CRYP_AES_ECB:
1571 case CRYP_AES_CBC:
1572 case CRYP_AES_CTR:
1573
1574 /* AES decryption */
1575 status = CRYP_AES_Decrypt_IT(hcryp);
1576 break;
1577
1578 case CRYP_AES_GCM_GMAC:
1579
1580 /* AES GCM decryption */
1581 status = CRYP_AESGCM_Process_IT(hcryp) ;
1582 break;
1583
1584 case CRYP_AES_CCM:
1585
1586 /* AES CCM decryption */
1587 status = CRYP_AESCCM_Process_IT(hcryp);
1588 break;
1589
1590 default:
1591 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1592 /* Change the CRYP peripheral state */
1593 hcryp->State = HAL_CRYP_STATE_READY;
1594 /* Process unlocked */
1595 __HAL_UNLOCK(hcryp);
1596 status = HAL_ERROR;
1597 break;
1598 }
1599 #endif /* End AES or CRYP */
1600
1601 }
1602 else
1603 {
1604 /* Busy error code field */
1605 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1606 status = HAL_ERROR;
1607 }
1608
1609 /* Return function status */
1610 return status;
1611 }
1612
1613 /**
1614 * @brief Encryption in DMA mode.
1615 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1616 * the configuration information for CRYP module
1617 * @param Input: Pointer to the input buffer (plaintext)
1618 * @param Size: Length of the plaintext buffer in word.
1619 * @param Output: Pointer to the output buffer(ciphertext)
1620 * @retval HAL status
1621 */
HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output)1622 HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1623 {
1624 uint32_t algo;
1625 HAL_StatusTypeDef status = HAL_OK;
1626 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
1627
1628 if (hcryp->State == HAL_CRYP_STATE_READY)
1629 {
1630 /* Change state Busy */
1631 hcryp->State = HAL_CRYP_STATE_BUSY;
1632
1633 /* Process locked */
1634 __HAL_LOCK(hcryp);
1635
1636 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
1637 hcryp->CrypInCount = 0U;
1638 hcryp->CrypOutCount = 0U;
1639 hcryp->pCrypInBuffPtr = Input;
1640 hcryp->pCrypOutBuffPtr = Output;
1641
1642 /* Calculate Size parameter in Byte*/
1643 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1644 {
1645 hcryp->Size = Size * 4U;
1646 }
1647 else
1648 {
1649 hcryp->Size = Size;
1650 }
1651
1652 #if defined (CRYP)
1653
1654 /* Set encryption operating mode*/
1655 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
1656
1657 /* algo get algorithm selected */
1658 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1659
1660 switch (algo)
1661 {
1662 case CRYP_DES_ECB:
1663 case CRYP_DES_CBC:
1664 case CRYP_TDES_ECB:
1665 case CRYP_TDES_CBC:
1666
1667 /*Set Key */
1668 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1669 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1670 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1671 {
1672 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1673 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1674 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1675 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1676 }
1677
1678 /* Set the Initialization Vector*/
1679 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1680 {
1681 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1682 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1683 }
1684
1685 /* Flush FIFO */
1686 HAL_CRYP_FIFO_FLUSH(hcryp);
1687
1688 /* Set the phase */
1689 hcryp->Phase = CRYP_PHASE_PROCESS;
1690
1691 /* Start DMA process transfer for DES/TDES */
1692 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U),
1693 (uint32_t)(hcryp->pCrypOutBuffPtr));
1694 break;
1695
1696 case CRYP_AES_ECB:
1697 case CRYP_AES_CBC:
1698 case CRYP_AES_CTR:
1699
1700 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
1701 {
1702 if (hcryp->KeyIVConfig == 1U)
1703 {
1704 /* If the Key and IV configuration has to be done only once
1705 and if it has already been done, skip it */
1706 DoKeyIVConfig = 0U;
1707 }
1708 else
1709 {
1710 /* If the Key and IV configuration has to be done only once
1711 and if it has not been done already, do it and set KeyIVConfig
1712 to keep track it won't have to be done again next time */
1713 hcryp->KeyIVConfig = 1U;
1714 }
1715 }
1716
1717 if (DoKeyIVConfig == 1U)
1718 {
1719 /* Set the Key*/
1720 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
1721
1722 /* Set the Initialization Vector*/
1723 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
1724 {
1725 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1726 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
1727 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
1728 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
1729 }
1730 } /* if (DoKeyIVConfig == 1U) */
1731
1732 /* Set the phase */
1733 hcryp->Phase = CRYP_PHASE_PROCESS;
1734
1735 /* Start DMA process transfer for AES */
1736 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U),
1737 (uint32_t)(hcryp->pCrypOutBuffPtr));
1738 break;
1739
1740 case CRYP_AES_GCM:
1741 /* AES GCM encryption */
1742 status = CRYP_AESGCM_Process_DMA(hcryp) ;
1743 break;
1744
1745 case CRYP_AES_CCM:
1746 /* AES CCM encryption */
1747 status = CRYP_AESCCM_Process_DMA(hcryp);
1748 break;
1749
1750 default:
1751 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1752 /* Change the CRYP peripheral state */
1753 hcryp->State = HAL_CRYP_STATE_READY;
1754 /* Process unlocked */
1755 __HAL_UNLOCK(hcryp);
1756 status = HAL_ERROR;
1757 break;
1758 }
1759
1760 #else /*AES*/
1761 /* Set encryption operating mode*/
1762 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
1763
1764 /* algo get algorithm selected */
1765 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1766
1767 switch (algo)
1768 {
1769
1770 case CRYP_AES_ECB:
1771 case CRYP_AES_CBC:
1772 case CRYP_AES_CTR:
1773
1774 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
1775 {
1776 if (hcryp->KeyIVConfig == 1U)
1777 {
1778 /* If the Key and IV configuration has to be done only once
1779 and if it has already been done, skip it */
1780 DoKeyIVConfig = 0U;
1781 }
1782 else
1783 {
1784 /* If the Key and IV configuration has to be done only once
1785 and if it has not been done already, do it and set KeyIVConfig
1786 to keep track it won't have to be done again next time */
1787 hcryp->KeyIVConfig = 1U;
1788 }
1789 }
1790
1791 if (DoKeyIVConfig == 1U)
1792 {
1793 /* Set the Key*/
1794 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
1795
1796 /* Set the Initialization Vector*/
1797 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
1798 {
1799 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
1800 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1801 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
1802 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
1803 }
1804 } /* if (DoKeyIVConfig == 1U) */
1805 /* Set the phase */
1806 hcryp->Phase = CRYP_PHASE_PROCESS;
1807
1808 /* Start DMA process transfer for AES */
1809 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
1810 break;
1811
1812 case CRYP_AES_GCM_GMAC:
1813 /* AES GCM encryption */
1814 status = CRYP_AESGCM_Process_DMA(hcryp) ;
1815 break;
1816
1817 case CRYP_AES_CCM:
1818 /* AES CCM encryption */
1819 status = CRYP_AESCCM_Process_DMA(hcryp);
1820 break;
1821
1822 default:
1823 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1824 /* Change the CRYP peripheral state */
1825 hcryp->State = HAL_CRYP_STATE_READY;
1826 /* Process unlocked */
1827 __HAL_UNLOCK(hcryp);
1828 status = HAL_ERROR;
1829 break;
1830 }
1831 #endif /* End AES or CRYP */
1832
1833 }
1834 else
1835 {
1836 /* Busy error code field */
1837 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1838 status = HAL_ERROR;
1839 }
1840
1841 /* Return function status */
1842 return status;
1843 }
1844
1845 /**
1846 * @brief Decryption in DMA mode.
1847 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1848 * the configuration information for CRYP module
1849 * @param Input: Pointer to the input buffer (ciphertext )
1850 * @param Size: Length of the plaintext buffer in word
1851 * @param Output: Pointer to the output buffer(plaintext)
1852 * @retval HAL status
1853 */
HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output)1854 HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1855 {
1856 uint32_t algo;
1857 HAL_StatusTypeDef status = HAL_OK;
1858
1859 if (hcryp->State == HAL_CRYP_STATE_READY)
1860 {
1861
1862 /* Change state Busy */
1863 hcryp->State = HAL_CRYP_STATE_BUSY;
1864
1865 /* Process locked */
1866 __HAL_LOCK(hcryp);
1867
1868 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
1869 hcryp->CrypInCount = 0U;
1870 hcryp->CrypOutCount = 0U;
1871 hcryp->pCrypInBuffPtr = Input;
1872 hcryp->pCrypOutBuffPtr = Output;
1873
1874 /* Calculate Size parameter in Byte*/
1875 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1876 {
1877 hcryp->Size = Size * 4U;
1878 }
1879 else
1880 {
1881 hcryp->Size = Size;
1882 }
1883
1884 #if defined (CRYP)
1885
1886 /* Set decryption operating mode*/
1887 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
1888
1889 /* algo get algorithm selected */
1890 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1891
1892 switch (algo)
1893 {
1894 case CRYP_DES_ECB:
1895 case CRYP_DES_CBC:
1896 case CRYP_TDES_ECB:
1897 case CRYP_TDES_CBC:
1898
1899 /*Set Key */
1900 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1901 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1902 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1903 {
1904 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1905 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1906 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1907 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1908 }
1909
1910 /* Set the Initialization Vector*/
1911 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1912 {
1913 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1914 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1915 }
1916
1917 /* Flush FIFO */
1918 HAL_CRYP_FIFO_FLUSH(hcryp);
1919
1920 /* Set the phase */
1921 hcryp->Phase = CRYP_PHASE_PROCESS;
1922
1923 /* Start DMA process transfer for DES/TDES */
1924 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U),
1925 (uint32_t)(hcryp->pCrypOutBuffPtr));
1926 break;
1927
1928 case CRYP_AES_ECB:
1929 case CRYP_AES_CBC:
1930 case CRYP_AES_CTR:
1931
1932 /* AES decryption */
1933 status = CRYP_AES_Decrypt_DMA(hcryp);
1934 break;
1935
1936 case CRYP_AES_GCM:
1937 /* AES GCM decryption */
1938 status = CRYP_AESGCM_Process_DMA(hcryp) ;
1939 break;
1940
1941 case CRYP_AES_CCM:
1942 /* AES CCM decryption */
1943 status = CRYP_AESCCM_Process_DMA(hcryp);
1944 break;
1945
1946 default:
1947 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1948 /* Change the CRYP peripheral state */
1949 hcryp->State = HAL_CRYP_STATE_READY;
1950 /* Process unlocked */
1951 __HAL_UNLOCK(hcryp);
1952 status = HAL_ERROR;
1953 break;
1954 }
1955
1956 #else /*AES*/
1957
1958 /* Set decryption operating mode*/
1959 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
1960
1961 /* algo get algorithm selected */
1962 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1963
1964 switch (algo)
1965 {
1966
1967 case CRYP_AES_ECB:
1968 case CRYP_AES_CBC:
1969 case CRYP_AES_CTR:
1970
1971 /* AES decryption */
1972 status = CRYP_AES_Decrypt_DMA(hcryp);
1973 break;
1974
1975 case CRYP_AES_GCM_GMAC:
1976 /* AES GCM decryption */
1977 status = CRYP_AESGCM_Process_DMA(hcryp) ;
1978 break;
1979
1980 case CRYP_AES_CCM:
1981 /* AES CCM decryption */
1982 status = CRYP_AESCCM_Process_DMA(hcryp);
1983 break;
1984
1985 default:
1986 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1987 /* Change the CRYP peripheral state */
1988 hcryp->State = HAL_CRYP_STATE_READY;
1989 /* Process unlocked */
1990 __HAL_UNLOCK(hcryp);
1991 status = HAL_ERROR;
1992 break;
1993 }
1994 #endif /* End AES or CRYP */
1995 }
1996 else
1997 {
1998 /* Busy error code field */
1999 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
2000 status = HAL_ERROR;
2001 }
2002
2003 /* Return function status */
2004 return status;
2005 }
2006
2007 /**
2008 * @}
2009 */
2010
2011 /** @defgroup CRYP_Exported_Functions_Group3 CRYP IRQ handler management
2012 * @brief CRYP IRQ handler.
2013 *
2014 @verbatim
2015 ==============================================================================
2016 ##### CRYP IRQ handler management #####
2017 ==============================================================================
2018 [..] This section provides CRYP IRQ handler and callback functions.
2019 (+) HAL_CRYP_IRQHandler CRYP interrupt request
2020 (+) HAL_CRYP_InCpltCallback input data transfer complete callback
2021 (+) HAL_CRYP_OutCpltCallback output data transfer complete callback
2022 (+) HAL_CRYP_ErrorCallback CRYP error callback
2023 (+) HAL_CRYP_GetState return the CRYP state
2024 (+) HAL_CRYP_GetError return the CRYP error code
2025 @endverbatim
2026 * @{
2027 */
2028
2029 /**
2030 * @brief This function handles cryptographic interrupt request.
2031 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2032 * the configuration information for CRYP module
2033 * @retval None
2034 */
HAL_CRYP_IRQHandler(CRYP_HandleTypeDef * hcryp)2035 void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
2036 {
2037
2038 #if defined (CRYP)
2039
2040 uint32_t itstatus = hcryp->Instance->MISR;
2041
2042 if ((itstatus & (CRYP_IT_INI | CRYP_IT_OUTI)) != 0U)
2043 {
2044 if ((hcryp->Init.Algorithm == CRYP_DES_ECB) || (hcryp->Init.Algorithm == CRYP_DES_CBC)
2045 || (hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
2046 {
2047 CRYP_TDES_IT(hcryp); /* DES or TDES*/
2048 }
2049 else if ((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC)
2050 || (hcryp->Init.Algorithm == CRYP_AES_CTR))
2051 {
2052 CRYP_AES_IT(hcryp); /*AES*/
2053 }
2054
2055 else if ((hcryp->Init.Algorithm == CRYP_AES_GCM) || (hcryp->Init.Algorithm == CRYP_CR_ALGOMODE_AES_CCM))
2056 {
2057 /* if header phase */
2058 if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER)
2059 {
2060 CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
2061 }
2062 else /* if payload phase */
2063 {
2064 CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
2065 }
2066 }
2067
2068 else
2069 {
2070 /* Nothing to do */
2071 }
2072 }
2073
2074 #else /*AES*/
2075 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_CCF) != RESET)
2076 {
2077 if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET)
2078 {
2079
2080 /* Clear computation complete flag */
2081 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
2082
2083 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
2084 {
2085
2086 /* if header phase */
2087 if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER)
2088 {
2089 CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
2090 }
2091 else /* if payload phase */
2092 {
2093 CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
2094 }
2095 }
2096 else if (hcryp->Init.Algorithm == CRYP_AES_CCM)
2097 {
2098 /* if header phase */
2099 if (hcryp->Init.HeaderSize >= hcryp->CrypHeaderCount)
2100 {
2101 CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
2102 }
2103 else /* if payload phase */
2104 {
2105 CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
2106 }
2107 }
2108 else /* AES Algorithm ECB,CBC or CTR*/
2109 {
2110 CRYP_AES_IT(hcryp);
2111 }
2112 }
2113 }
2114 /* Check if error occurred */
2115 if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_ERRIE) != RESET)
2116 {
2117 /* If write Error occurred */
2118 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_WRERR) != RESET)
2119 {
2120 hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE;
2121 }
2122 /* If read Error occurred */
2123 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_RDERR) != RESET)
2124 {
2125 hcryp->ErrorCode |= HAL_CRYP_ERROR_READ;
2126 }
2127 }
2128 #endif /* End AES or CRYP */
2129 }
2130
2131 /**
2132 * @brief Return the CRYP error code.
2133 * @param hcryp : pointer to a CRYP_HandleTypeDef structure that contains
2134 * the configuration information for the CRYP IP
2135 * @retval CRYP error code
2136 */
HAL_CRYP_GetError(CRYP_HandleTypeDef * hcryp)2137 uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp)
2138 {
2139 return hcryp->ErrorCode;
2140 }
2141
2142 /**
2143 * @brief Returns the CRYP state.
2144 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2145 * the configuration information for CRYP module.
2146 * @retval HAL state
2147 */
HAL_CRYP_GetState(CRYP_HandleTypeDef * hcryp)2148 HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
2149 {
2150 return hcryp->State;
2151 }
2152
2153 /**
2154 * @brief Input FIFO transfer completed callback.
2155 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2156 * the configuration information for CRYP module.
2157 * @retval None
2158 */
HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef * hcryp)2159 __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
2160 {
2161 /* Prevent unused argument(s) compilation warning */
2162 UNUSED(hcryp);
2163
2164 /* NOTE : This function should not be modified, when the callback is needed,
2165 the HAL_CRYP_InCpltCallback can be implemented in the user file
2166 */
2167 }
2168
2169 /**
2170 * @brief Output FIFO transfer completed callback.
2171 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2172 * the configuration information for CRYP module.
2173 * @retval None
2174 */
HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef * hcryp)2175 __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
2176 {
2177 /* Prevent unused argument(s) compilation warning */
2178 UNUSED(hcryp);
2179
2180 /* NOTE : This function should not be modified, when the callback is needed,
2181 the HAL_CRYP_OutCpltCallback can be implemented in the user file
2182 */
2183 }
2184
2185 /**
2186 * @brief CRYP error callback.
2187 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2188 * the configuration information for CRYP module.
2189 * @retval None
2190 */
HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef * hcryp)2191 __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
2192 {
2193 /* Prevent unused argument(s) compilation warning */
2194 UNUSED(hcryp);
2195
2196 /* NOTE : This function Should not be modified, when the callback is needed,
2197 the HAL_CRYP_ErrorCallback could be implemented in the user file
2198 */
2199 }
2200 /**
2201 * @}
2202 */
2203
2204 /* Private functions ---------------------------------------------------------*/
2205 /** @addtogroup CRYP_Private_Functions
2206 * @{
2207 */
2208
2209 #if defined (CRYP)
2210
2211 /**
2212 * @brief Encryption in ECB/CBC Algorithm with DES/TDES standard.
2213 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2214 * the configuration information for CRYP module
2215 * @param Timeout: specify Timeout value
2216 * @retval HAL status
2217 */
CRYP_TDES_Process(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)2218 static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
2219 {
2220 uint32_t temp[2]; /* Temporary CrypOutBuff */
2221 uint16_t incount; /* Temporary CrypInCount Value */
2222 uint16_t outcount; /* Temporary CrypOutCount Value */
2223 uint32_t i;
2224
2225 /* Enable CRYP */
2226 __HAL_CRYP_ENABLE(hcryp);
2227 /*Temporary CrypOutCount Value*/
2228 outcount = hcryp->CrypOutCount;
2229
2230 /*Start processing*/
2231 while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
2232 {
2233 /* Temporary CrypInCount Value */
2234 incount = hcryp->CrypInCount;
2235 /* Write plain data and get cipher data */
2236 if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
2237 {
2238 /* Write the input block in the IN FIFO */
2239 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2240 hcryp->CrypInCount++;
2241 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2242 hcryp->CrypInCount++;
2243 }
2244
2245 /* Wait for OFNE flag to be raised */
2246 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
2247 {
2248 /* Disable the CRYP peripheral clock */
2249 __HAL_CRYP_DISABLE(hcryp);
2250
2251 /* Change state & errorCode*/
2252 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2253 hcryp->State = HAL_CRYP_STATE_READY;
2254
2255 /* Process unlocked */
2256 __HAL_UNLOCK(hcryp);
2257 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2258 /*Call registered error callback*/
2259 hcryp->ErrorCallback(hcryp);
2260 #else
2261 /*Call legacy weak error callback*/
2262 HAL_CRYP_ErrorCallback(hcryp);
2263 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2264 }
2265
2266 /*Temporary CrypOutCount Value*/
2267 outcount = hcryp->CrypOutCount;
2268
2269 if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
2270 {
2271 /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
2272 for (i = 0U; i < 2U; i++)
2273 {
2274 temp[i] = hcryp->Instance->DOUT;
2275 }
2276 i = 0U;
2277 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 2U))
2278 {
2279 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
2280 hcryp->CrypOutCount++;
2281 i++;
2282 }
2283 }
2284 /*Temporary CrypOutCount Value*/
2285 outcount = hcryp->CrypOutCount;
2286 }
2287 /* Disable CRYP */
2288 __HAL_CRYP_DISABLE(hcryp);
2289 /* Change the CRYP state */
2290 hcryp->State = HAL_CRYP_STATE_READY;
2291
2292 /* Return function status */
2293 return HAL_OK;
2294 }
2295
2296 /**
2297 * @brief CRYP block input/output data handling under interruption with DES/TDES standard.
2298 * @note The function is called under interruption only, once
2299 * interruptions have been enabled by CRYP_Decrypt_IT() and CRYP_Encrypt_IT().
2300 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2301 * the configuration information for CRYP module.
2302 * @retval none
2303 */
CRYP_TDES_IT(CRYP_HandleTypeDef * hcryp)2304 static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp)
2305 {
2306 uint32_t temp[2]; /* Temporary CrypOutBuff */
2307 uint32_t i;
2308
2309 if (hcryp->State == HAL_CRYP_STATE_BUSY)
2310 {
2311 if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U)
2312 {
2313 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_INRIS) != 0x0U)
2314 {
2315 /* Write input block in the IN FIFO */
2316 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2317 hcryp->CrypInCount++;
2318 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2319 hcryp->CrypInCount++;
2320
2321 if (hcryp->CrypInCount == ((uint16_t)(hcryp->Size) / 4U))
2322 {
2323 /* Disable interruption */
2324 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
2325 /* Call the input data transfer complete callback */
2326 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
2327 /*Call registered Input complete callback*/
2328 hcryp->InCpltCallback(hcryp);
2329 #else
2330 /*Call legacy weak Input complete callback*/
2331 HAL_CRYP_InCpltCallback(hcryp);
2332 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2333 }
2334 }
2335 }
2336 if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U)
2337 {
2338 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_OUTRIS) != 0x0U)
2339 {
2340 /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
2341 for (i = 0U; i < 2U; i++)
2342 {
2343 temp[i] = hcryp->Instance->DOUT;
2344 }
2345 i = 0U;
2346 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 2U))
2347 {
2348 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
2349 hcryp->CrypOutCount++;
2350 i++;
2351 }
2352 if (hcryp->CrypOutCount == ((uint16_t)(hcryp->Size) / 4U))
2353 {
2354 /* Disable interruption */
2355 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
2356
2357 /* Disable CRYP */
2358 __HAL_CRYP_DISABLE(hcryp);
2359
2360 /* Process unlocked */
2361 __HAL_UNLOCK(hcryp);
2362
2363 /* Change the CRYP state */
2364 hcryp->State = HAL_CRYP_STATE_READY;
2365 /* Call output transfer complete callback */
2366 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2367 /*Call registered Output complete callback*/
2368 hcryp->OutCpltCallback(hcryp);
2369 #else
2370 /*Call legacy weak Output complete callback*/
2371 HAL_CRYP_OutCpltCallback(hcryp);
2372 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2373 }
2374 }
2375 }
2376 }
2377 else
2378 {
2379 /* Process unlocked */
2380 __HAL_UNLOCK(hcryp);
2381 /* Busy error code field */
2382 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
2383 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2384 /*Call registered error callback*/
2385 hcryp->ErrorCallback(hcryp);
2386 #else
2387 /*Call legacy weak error callback*/
2388 HAL_CRYP_ErrorCallback(hcryp);
2389 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2390 }
2391 }
2392
2393 #endif /* CRYP */
2394
2395 /**
2396 * @brief Encryption in ECB/CBC & CTR Algorithm with AES Standard
2397 * @param hcryp: pointer to a CRYP_HandleTypeDef structure
2398 * @param Timeout: specify Timeout value
2399 * @retval HAL status
2400 */
CRYP_AES_Encrypt(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)2401 static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
2402 {
2403 uint16_t outcount; /* Temporary CrypOutCount Value */
2404 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2405
2406 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2407 {
2408 if (hcryp->KeyIVConfig == 1U)
2409 {
2410 /* If the Key and IV configuration has to be done only once
2411 and if it has already been done, skip it */
2412 DoKeyIVConfig = 0U;
2413 }
2414 else
2415 {
2416 /* If the Key and IV configuration has to be done only once
2417 and if it has not been done already, do it and set KeyIVConfig
2418 to keep track it won't have to be done again next time */
2419 hcryp->KeyIVConfig = 1U;
2420 }
2421 }
2422
2423 if (DoKeyIVConfig == 1U)
2424 {
2425
2426 /* Set the Key*/
2427 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2428
2429 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2430 {
2431 /* Set the Initialization Vector*/
2432 #if defined (AES)
2433 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
2434 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2435 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2436 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2437 #else /* CRYP */
2438 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2439 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2440 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2441 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2442 #endif /* End AES or CRYP */
2443 }
2444 } /* if (DoKeyIVConfig == 1U) */
2445
2446 /* Set the phase */
2447 hcryp->Phase = CRYP_PHASE_PROCESS;
2448
2449 /* Enable CRYP */
2450 __HAL_CRYP_ENABLE(hcryp);
2451
2452 /*Temporary CrypOutCount Value*/
2453 outcount = hcryp->CrypOutCount;
2454
2455 while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
2456 {
2457 /* Write plain Ddta and get cipher data */
2458 CRYP_AES_ProcessData(hcryp, Timeout);
2459 /*Temporary CrypOutCount Value*/
2460 outcount = hcryp->CrypOutCount;
2461 }
2462
2463 /* Disable CRYP */
2464 __HAL_CRYP_DISABLE(hcryp);
2465
2466 /* Change the CRYP state */
2467 hcryp->State = HAL_CRYP_STATE_READY;
2468
2469 /* Return function status */
2470 return HAL_OK;
2471 }
2472
2473 /**
2474 * @brief Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
2475 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2476 * the configuration information for CRYP module
2477 * @retval HAL status
2478 */
CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef * hcryp)2479 static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
2480 {
2481 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2482
2483 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2484 {
2485 if (hcryp->KeyIVConfig == 1U)
2486 {
2487 /* If the Key and IV configuration has to be done only once
2488 and if it has already been done, skip it */
2489 DoKeyIVConfig = 0U;
2490 }
2491 else
2492 {
2493 /* If the Key and IV configuration has to be done only once
2494 and if it has not been done already, do it and set KeyIVConfig
2495 to keep track it won't have to be done again next time */
2496 hcryp->KeyIVConfig = 1U;
2497 }
2498 }
2499
2500 if (DoKeyIVConfig == 1U)
2501 {
2502 /* Set the Key*/
2503 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2504
2505 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2506 {
2507 /* Set the Initialization Vector*/
2508 #if defined (AES)
2509 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
2510 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2511 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2512 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2513
2514 #else /* CRYP */
2515 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2516 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2517 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2518 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2519 #endif /* End AES or CRYP */
2520 }
2521 } /* if (DoKeyIVConfig == 1U) */
2522
2523 /* Set the phase */
2524 hcryp->Phase = CRYP_PHASE_PROCESS;
2525
2526 if (hcryp->Size != 0U)
2527 {
2528 #if defined (AES)
2529
2530 /* Enable computation complete flag and error interrupts */
2531 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
2532
2533 /* Enable CRYP */
2534 __HAL_CRYP_ENABLE(hcryp);
2535
2536 /* Increment the pointer before writing the input block in the IN FIFO to make sure that
2537 when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value
2538 and it is ready for the next operation. */
2539 hcryp->CrypInCount++;
2540 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
2541 hcryp->CrypInCount++;
2542 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
2543 hcryp->CrypInCount++;
2544 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
2545 hcryp->CrypInCount++;
2546 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
2547
2548 #else /* CRYP */
2549
2550 /* Enable interrupts */
2551 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
2552
2553 /* Enable CRYP */
2554 __HAL_CRYP_ENABLE(hcryp);
2555
2556 #endif /* End AES or CRYP */
2557 }
2558 else
2559 {
2560 /* Change the CRYP state */
2561 hcryp->State = HAL_CRYP_STATE_READY;
2562
2563 /* Process unlocked */
2564 __HAL_UNLOCK(hcryp);
2565 }
2566
2567 /* Return function status */
2568 return HAL_OK;
2569 }
2570
2571 /**
2572 * @brief Decryption in ECB/CBC & CTR mode with AES Standard
2573 * @param hcryp: pointer to a CRYP_HandleTypeDef structure
2574 * @param Timeout: Specify Timeout value
2575 * @retval HAL status
2576 */
CRYP_AES_Decrypt(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)2577 static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
2578 {
2579 uint16_t outcount; /* Temporary CrypOutCount Value */
2580 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2581
2582 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2583 {
2584 if (hcryp->KeyIVConfig == 1U)
2585 {
2586 /* If the Key and IV configuration has to be done only once
2587 and if it has already been done, skip it */
2588 DoKeyIVConfig = 0U;
2589 }
2590 else
2591 {
2592 /* If the Key and IV configuration has to be done only once
2593 and if it has not been done already, do it and set KeyIVConfig
2594 to keep track it won't have to be done again next time */
2595 hcryp->KeyIVConfig = 1U;
2596 }
2597 }
2598
2599 if (DoKeyIVConfig == 1U)
2600 {
2601 /* Key preparation for ECB/CBC */
2602 if (hcryp->Init.Algorithm != CRYP_AES_CTR)
2603 {
2604 #if defined (AES)
2605 if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
2606 {
2607 /* Set key preparation for decryption operating mode*/
2608 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
2609
2610 /* Set the Key*/
2611 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2612
2613 /* Enable CRYP */
2614 __HAL_CRYP_ENABLE(hcryp);
2615
2616 /* Wait for CCF flag to be raised */
2617 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
2618 {
2619 /* Disable the CRYP peripheral clock */
2620 __HAL_CRYP_DISABLE(hcryp);
2621
2622 /* Change state & error code*/
2623 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2624 hcryp->State = HAL_CRYP_STATE_READY;
2625
2626 /* Process unlocked */
2627 __HAL_UNLOCK(hcryp);
2628 return HAL_ERROR;
2629 }
2630 /* Clear CCF Flag */
2631 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
2632
2633 /* Return to decryption operating mode(Mode 3)*/
2634 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
2635 }
2636 else /*Mode 4 : decryption & Key preparation*/
2637 {
2638 /* Set the Key*/
2639 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2640
2641 /* Set decryption & Key preparation operating mode*/
2642 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
2643 }
2644 #else /* CRYP */
2645 /* change ALGOMODE to key preparation for decryption*/
2646 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
2647
2648 /* Set the Key*/
2649 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2650
2651 /* Enable CRYP */
2652 __HAL_CRYP_ENABLE(hcryp);
2653
2654 /* Wait for BUSY flag to be raised */
2655 if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
2656 {
2657 /* Disable the CRYP peripheral clock */
2658 __HAL_CRYP_DISABLE(hcryp);
2659
2660 /* Change state */
2661 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2662 hcryp->State = HAL_CRYP_STATE_READY;
2663
2664 /* Process unlocked */
2665 __HAL_UNLOCK(hcryp);
2666 return HAL_ERROR;
2667 }
2668 /* Turn back to ALGOMODE of the configuration */
2669 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
2670
2671 #endif /* End AES or CRYP */
2672 }
2673 else /*Algorithm CTR */
2674 {
2675 /* Set the Key*/
2676 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2677 }
2678
2679 /* Set IV */
2680 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2681 {
2682 /* Set the Initialization Vector*/
2683 #if defined (AES)
2684 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
2685 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2686 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2687 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2688 #else /* CRYP */
2689 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2690 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2691 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2692 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2693 #endif /* End AES or CRYP */
2694 }
2695 } /* if (DoKeyIVConfig == 1U) */
2696 /* Set the phase */
2697 hcryp->Phase = CRYP_PHASE_PROCESS;
2698
2699 /* Enable CRYP */
2700 __HAL_CRYP_ENABLE(hcryp);
2701
2702 /*Temporary CrypOutCount Value*/
2703 outcount = hcryp->CrypOutCount;
2704
2705 while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
2706 {
2707 /* Write plain data and get cipher data */
2708 CRYP_AES_ProcessData(hcryp, Timeout);
2709 /*Temporary CrypOutCount Value*/
2710 outcount = hcryp->CrypOutCount;
2711 }
2712
2713 /* Disable CRYP */
2714 __HAL_CRYP_DISABLE(hcryp);
2715
2716 /* Change the CRYP state */
2717 hcryp->State = HAL_CRYP_STATE_READY;
2718
2719 /* Return function status */
2720 return HAL_OK;
2721 }
2722 /**
2723 * @brief Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
2724 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2725 * the configuration information for CRYP module
2726 * @retval HAL status
2727 */
CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef * hcryp)2728 static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
2729 {
2730 __IO uint32_t count = 0U;
2731 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2732
2733 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2734 {
2735 if (hcryp->KeyIVConfig == 1U)
2736 {
2737 /* If the Key and IV configuration has to be done only once
2738 and if it has already been done, skip it */
2739 DoKeyIVConfig = 0U;
2740 }
2741 else
2742 {
2743 /* If the Key and IV configuration has to be done only once
2744 and if it has not been done already, do it and set KeyIVConfig
2745 to keep track it won't have to be done again next time */
2746 hcryp->KeyIVConfig = 1U;
2747 }
2748 }
2749
2750 if (DoKeyIVConfig == 1U)
2751 {
2752 /* Key preparation for ECB/CBC */
2753 if (hcryp->Init.Algorithm != CRYP_AES_CTR)
2754 {
2755 #if defined (AES)
2756 if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
2757 {
2758 /* Set key preparation for decryption operating mode*/
2759 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
2760
2761 /* Set the Key*/
2762 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2763
2764 /* Enable CRYP */
2765 __HAL_CRYP_ENABLE(hcryp);
2766
2767 /* Wait for CCF flag to be raised */
2768 count = CRYP_TIMEOUT_KEYPREPARATION;
2769 do
2770 {
2771 count-- ;
2772 if (count == 0U)
2773 {
2774 /* Disable the CRYP peripheral clock */
2775 __HAL_CRYP_DISABLE(hcryp);
2776
2777 /* Change state */
2778 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2779 hcryp->State = HAL_CRYP_STATE_READY;
2780
2781 /* Process unlocked */
2782 __HAL_UNLOCK(hcryp);
2783 return HAL_ERROR;
2784 }
2785 }
2786 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
2787
2788 /* Clear CCF Flag */
2789 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
2790
2791 /* Return to decryption operating mode(Mode 3)*/
2792 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
2793 }
2794 else /*Mode 4 : decryption & key preparation*/
2795 {
2796 /* Set the Key*/
2797 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2798
2799 /* Set decryption & key preparation operating mode*/
2800 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
2801 }
2802 #else /* CRYP */
2803
2804 /* change ALGOMODE to key preparation for decryption*/
2805 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
2806
2807 /* Set the Key*/
2808 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2809
2810 /* Enable CRYP */
2811 __HAL_CRYP_ENABLE(hcryp);
2812
2813 /* Wait for BUSY flag to be raised */
2814 count = CRYP_TIMEOUT_KEYPREPARATION;
2815 do
2816 {
2817 count-- ;
2818 if (count == 0U)
2819 {
2820 /* Change state */
2821 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2822 hcryp->State = HAL_CRYP_STATE_READY;
2823
2824 /* Process unlocked */
2825 __HAL_UNLOCK(hcryp);
2826 return HAL_ERROR;
2827 }
2828 }
2829 while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
2830
2831 /* Turn back to ALGOMODE of the configuration */
2832 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
2833
2834 #endif /* End AES or CRYP */
2835 }
2836
2837 else /*Algorithm CTR */
2838 {
2839 /* Set the Key*/
2840 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2841 }
2842
2843 /* Set IV */
2844 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2845 {
2846 /* Set the Initialization Vector*/
2847 #if defined (AES)
2848 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
2849 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2850 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2851 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2852 #else /* CRYP */
2853 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2854 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2855 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2856 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2857 #endif /* End AES or CRYP */
2858 }
2859 } /* if (DoKeyIVConfig == 1U) */
2860
2861 /* Set the phase */
2862 hcryp->Phase = CRYP_PHASE_PROCESS;
2863 if (hcryp->Size != 0U)
2864 {
2865
2866 #if defined (AES)
2867
2868 /* Enable computation complete flag and error interrupts */
2869 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
2870
2871 /* Enable CRYP */
2872 __HAL_CRYP_ENABLE(hcryp);
2873
2874 /* Increment the pointer before writing the input block in the IN FIFO to make sure that
2875 when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value
2876 and it is ready for the next operation. */
2877 hcryp->CrypInCount++;
2878 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
2879 hcryp->CrypInCount++;
2880 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
2881 hcryp->CrypInCount++;
2882 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
2883 hcryp->CrypInCount++;
2884 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
2885
2886 #else /* CRYP */
2887
2888 /* Enable interrupts */
2889 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
2890
2891 /* Enable CRYP */
2892 __HAL_CRYP_ENABLE(hcryp);
2893
2894 #endif /* End AES or CRYP */
2895 }
2896 else
2897 {
2898 /* Process locked */
2899 __HAL_UNLOCK(hcryp);
2900
2901 /* Change the CRYP state */
2902 hcryp->State = HAL_CRYP_STATE_READY;
2903 }
2904
2905 /* Return function status */
2906 return HAL_OK;
2907 }
2908 /**
2909 * @brief Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode
2910 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2911 * the configuration information for CRYP module
2912 * @retval HAL status
2913 */
CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef * hcryp)2914 static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
2915 {
2916 __IO uint32_t count = 0U;
2917 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2918
2919 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2920 {
2921 if (hcryp->KeyIVConfig == 1U)
2922 {
2923 /* If the Key and IV configuration has to be done only once
2924 and if it has already been done, skip it */
2925 DoKeyIVConfig = 0U;
2926 }
2927 else
2928 {
2929 /* If the Key and IV configuration has to be done only once
2930 and if it has not been done already, do it and set KeyIVConfig
2931 to keep track it won't have to be done again next time */
2932 hcryp->KeyIVConfig = 1U;
2933 }
2934 }
2935 if (DoKeyIVConfig == 1U)
2936 {
2937 /* Key preparation for ECB/CBC */
2938 if (hcryp->Init.Algorithm != CRYP_AES_CTR)
2939 {
2940 #if defined (AES)
2941 if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 key preparation*/
2942 {
2943 /* Set key preparation for decryption operating mode*/
2944 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
2945
2946 /* Set the Key*/
2947 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2948
2949 /* Enable CRYP */
2950 __HAL_CRYP_ENABLE(hcryp);
2951
2952 /* Wait for CCF flag to be raised */
2953 count = CRYP_TIMEOUT_KEYPREPARATION;
2954 do
2955 {
2956 count-- ;
2957 if (count == 0U)
2958 {
2959 /* Disable the CRYP peripheral clock */
2960 __HAL_CRYP_DISABLE(hcryp);
2961
2962 /* Change state */
2963 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2964 hcryp->State = HAL_CRYP_STATE_READY;
2965
2966 /* Process unlocked */
2967 __HAL_UNLOCK(hcryp);
2968 return HAL_ERROR;
2969 }
2970 }
2971 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
2972
2973 /* Clear CCF Flag */
2974 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
2975
2976 /* Return to decryption operating mode(Mode 3)*/
2977 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
2978 }
2979 else /*Mode 4 : decryption & key preparation*/
2980 {
2981 /* Set the Key*/
2982 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2983
2984 /* Set decryption & Key preparation operating mode*/
2985 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
2986 }
2987 #else /* CRYP */
2988 /* change ALGOMODE to key preparation for decryption*/
2989 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
2990
2991 /* Set the Key*/
2992 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2993
2994 /* Enable CRYP */
2995 __HAL_CRYP_ENABLE(hcryp);
2996
2997 /* Wait for BUSY flag to be raised */
2998 count = CRYP_TIMEOUT_KEYPREPARATION;
2999 do
3000 {
3001 count-- ;
3002 if (count == 0U)
3003 {
3004 /* Disable the CRYP peripheral clock */
3005 __HAL_CRYP_DISABLE(hcryp);
3006
3007 /* Change state */
3008 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3009 hcryp->State = HAL_CRYP_STATE_READY;
3010
3011 /* Process unlocked */
3012 __HAL_UNLOCK(hcryp);
3013 return HAL_ERROR;
3014 }
3015 }
3016 while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
3017
3018 /* Turn back to ALGOMODE of the configuration */
3019 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
3020
3021 #endif /* End AES or CRYP */
3022 }
3023 else /*Algorithm CTR */
3024 {
3025 /* Set the Key*/
3026 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3027 }
3028
3029 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
3030 {
3031 /* Set the Initialization Vector*/
3032 #if defined (AES)
3033 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
3034 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3035 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3036 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3037 #else /* CRYP */
3038 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
3039 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3040 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3041 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3042 #endif /* End AES or CRYP */
3043 }
3044 } /* if (DoKeyIVConfig == 1U) */
3045
3046 /* Set the phase */
3047 hcryp->Phase = CRYP_PHASE_PROCESS;
3048
3049 if (hcryp->Size != 0U)
3050 {
3051 /* Set the input and output addresses and start DMA transfer */
3052 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
3053 }
3054 else
3055 {
3056 /* Process unlocked */
3057 __HAL_UNLOCK(hcryp);
3058
3059 /* Change the CRYP state */
3060 hcryp->State = HAL_CRYP_STATE_READY;
3061 }
3062
3063 /* Return function status */
3064 return HAL_OK;
3065 }
3066
3067
3068 /**
3069 * @brief DMA CRYP input data process complete callback.
3070 * @param hdma: DMA handle
3071 * @retval None
3072 */
CRYP_DMAInCplt(DMA_HandleTypeDef * hdma)3073 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
3074 {
3075 CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3076
3077 /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
3078 in the DMACR register */
3079 #if defined (CRYP)
3080 hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
3081
3082 #else /* AES */
3083 CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
3084
3085 /* TinyAES2, No output on CCM AES, unlock should be done when input data process complete */
3086 if ((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM)
3087 {
3088 /* Clear CCF flag */
3089 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3090
3091 /* Change the CRYP state to ready */
3092 hcryp->State = HAL_CRYP_STATE_READY;
3093
3094 /* Process Unlocked */
3095 __HAL_UNLOCK(hcryp);
3096 }
3097 #endif /* End AES or CRYP */
3098
3099 /* Call input data transfer complete callback */
3100 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3101 /*Call registered Input complete callback*/
3102 hcryp->InCpltCallback(hcryp);
3103 #else
3104 /*Call legacy weak Input complete callback*/
3105 HAL_CRYP_InCpltCallback(hcryp);
3106 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3107 }
3108
3109 /**
3110 * @brief DMA CRYP output data process complete callback.
3111 * @param hdma: DMA handle
3112 * @retval None
3113 */
CRYP_DMAOutCplt(DMA_HandleTypeDef * hdma)3114 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
3115 {
3116 CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3117
3118 /* Disable the DMA transfer for output FIFO request by resetting
3119 the DOEN bit in the DMACR register */
3120
3121 #if defined (CRYP)
3122
3123 hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
3124 if ((hcryp->Init.Algorithm & CRYP_AES_GCM) != CRYP_AES_GCM)
3125 {
3126 /* Disable CRYP (not allowed in GCM)*/
3127 __HAL_CRYP_DISABLE(hcryp);
3128 }
3129 #else /* AES */
3130
3131 CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
3132
3133 /* Clear CCF flag */
3134 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3135
3136 if ((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
3137 {
3138 /* Disable CRYP (not allowed in GCM)*/
3139 __HAL_CRYP_DISABLE(hcryp);
3140 }
3141 #endif /* End AES or CRYP */
3142
3143 /* Change the CRYP state to ready */
3144 hcryp->State = HAL_CRYP_STATE_READY;
3145
3146 /* Process unlocked */
3147 __HAL_UNLOCK(hcryp);
3148 /* Call output data transfer complete callback */
3149 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3150 /*Call registered Output complete callback*/
3151 hcryp->OutCpltCallback(hcryp);
3152 #else
3153 /*Call legacy weak Output complete callback*/
3154 HAL_CRYP_OutCpltCallback(hcryp);
3155 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3156 }
3157
3158 /**
3159 * @brief DMA CRYP communication error callback.
3160 * @param hdma: DMA handle
3161 * @retval None
3162 */
CRYP_DMAError(DMA_HandleTypeDef * hdma)3163 static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
3164 {
3165 CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3166
3167 /* Change the CRYP peripheral state */
3168 hcryp->State = HAL_CRYP_STATE_READY;
3169
3170 /* DMA error code field */
3171 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3172
3173 #if defined (AES)
3174
3175 /* Clear CCF flag */
3176 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3177
3178 #endif /* AES */
3179
3180 /* Call error callback */
3181 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3182 /*Call registered error callback*/
3183 hcryp->ErrorCallback(hcryp);
3184 #else
3185 /*Call legacy weak error callback*/
3186 HAL_CRYP_ErrorCallback(hcryp);
3187 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3188 }
3189
3190 /**
3191 * @brief Set the DMA configuration and start the DMA transfer
3192 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3193 * the configuration information for CRYP module
3194 * @param inputaddr: address of the input buffer
3195 * @param Size: size of the input buffer, must be a multiple of 16.
3196 * @param outputaddr: address of the output buffer
3197 * @retval None
3198 */
CRYP_SetDMAConfig(CRYP_HandleTypeDef * hcryp,uint32_t inputaddr,uint16_t Size,uint32_t outputaddr)3199 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
3200 {
3201 /* Set the CRYP DMA transfer complete callback */
3202 hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
3203
3204 /* Set the DMA input error callback */
3205 hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
3206
3207 /* Set the CRYP DMA transfer complete callback */
3208 hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
3209
3210 /* Set the DMA output error callback */
3211 hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
3212
3213 #if defined (CRYP)
3214
3215 /* Enable CRYP */
3216 __HAL_CRYP_ENABLE(hcryp);
3217
3218 /* Enable the input DMA Stream */
3219 if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DIN, Size) != HAL_OK)
3220 {
3221 /* DMA error code field */
3222 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3223
3224 /* Call error callback */
3225 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3226 /*Call registered error callback*/
3227 hcryp->ErrorCallback(hcryp);
3228 #else
3229 /*Call legacy weak error callback*/
3230 HAL_CRYP_ErrorCallback(hcryp);
3231 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3232 }
3233 /* Enable the output DMA Stream */
3234 if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size) != HAL_OK)
3235 {
3236 /* DMA error code field */
3237 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3238
3239 /* Call error callback */
3240 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3241 /*Call registered error callback*/
3242 hcryp->ErrorCallback(hcryp);
3243 #else
3244 /*Call legacy weak error callback*/
3245 HAL_CRYP_ErrorCallback(hcryp);
3246 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3247 }
3248 /* Enable In/Out DMA request */
3249 hcryp->Instance->DMACR = CRYP_DMACR_DOEN | CRYP_DMACR_DIEN;
3250
3251 #else /* AES */
3252
3253 if (((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
3254 && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM))
3255 {
3256 /* Enable CRYP (not allowed in GCM & CCM)*/
3257 __HAL_CRYP_ENABLE(hcryp);
3258 }
3259
3260 /* Enable the DMA input stream */
3261 if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size) != HAL_OK)
3262 {
3263 /* DMA error code field */
3264 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3265
3266 /* Call error callback */
3267 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3268 /*Call registered error callback*/
3269 hcryp->ErrorCallback(hcryp);
3270 #else
3271 /*Call legacy weak error callback*/
3272 HAL_CRYP_ErrorCallback(hcryp);
3273 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3274 }
3275 /* Enable the DMA output stream */
3276 if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size) != HAL_OK)
3277 {
3278 /* DMA error code field */
3279 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3280
3281 /* Call error callback */
3282 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3283 /*Call registered error callback*/
3284 hcryp->ErrorCallback(hcryp);
3285 #else
3286 /*Call legacy weak error callback*/
3287 HAL_CRYP_ErrorCallback(hcryp);
3288 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3289 }
3290 /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
3291 /* Enable In and Out DMA requests */
3292 if ((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM)
3293 {
3294 /* Enable only In DMA requests for CCM*/
3295 SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN));
3296 }
3297 else
3298 {
3299 /* Enable In and Out DMA requests */
3300 SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));
3301 }
3302 #endif /* End AES or CRYP */
3303 }
3304
3305 /**
3306 * @brief Process Data: Write Input data in polling mode and used in AES functions.
3307 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3308 * the configuration information for CRYP module
3309 * @param Timeout: Specify Timeout value
3310 * @retval None
3311 */
CRYP_AES_ProcessData(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)3312 static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
3313 {
3314
3315 uint32_t temp[4]; /* Temporary CrypOutBuff */
3316 uint32_t i;
3317 #if defined (CRYP)
3318 uint16_t incount; /* Temporary CrypInCount Value */
3319 uint16_t outcount; /* Temporary CrypOutCount Value */
3320 #endif
3321
3322 #if defined (CRYP)
3323
3324 /*Temporary CrypOutCount Value*/
3325 incount = hcryp->CrypInCount;
3326
3327 if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
3328 {
3329 /* Write the input block in the IN FIFO */
3330 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3331 hcryp->CrypInCount++;
3332 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3333 hcryp->CrypInCount++;
3334 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3335 hcryp->CrypInCount++;
3336 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3337 hcryp->CrypInCount++;
3338 }
3339
3340 /* Wait for OFNE flag to be raised */
3341 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
3342 {
3343 /* Disable the CRYP peripheral clock */
3344 __HAL_CRYP_DISABLE(hcryp);
3345
3346 /* Change state & error code*/
3347 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3348 hcryp->State = HAL_CRYP_STATE_READY;
3349
3350 /* Process unlocked */
3351 __HAL_UNLOCK(hcryp);
3352 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3353 /*Call registered error callback*/
3354 hcryp->ErrorCallback(hcryp);
3355 #else
3356 /*Call legacy weak error callback*/
3357 HAL_CRYP_ErrorCallback(hcryp);
3358 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3359 }
3360
3361 /*Temporary CrypOutCount Value*/
3362 outcount = hcryp->CrypOutCount;
3363
3364 if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
3365 {
3366 /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
3367 for (i = 0U; i < 4U; i++)
3368 {
3369 temp[i] = hcryp->Instance->DOUT;
3370 }
3371 i = 0U;
3372 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
3373 {
3374 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3375 hcryp->CrypOutCount++;
3376 i++;
3377 }
3378 }
3379
3380 #else /* AES */
3381
3382 /* Write the input block in the IN FIFO */
3383 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3384 hcryp->CrypInCount++;
3385 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3386 hcryp->CrypInCount++;
3387 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3388 hcryp->CrypInCount++;
3389 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3390 hcryp->CrypInCount++;
3391
3392 /* Wait for CCF flag to be raised */
3393 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
3394 {
3395 /* Disable the CRYP peripheral clock */
3396 __HAL_CRYP_DISABLE(hcryp);
3397
3398 /* Change state */
3399 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3400 hcryp->State = HAL_CRYP_STATE_READY;
3401
3402 /* Process unlocked */
3403 __HAL_UNLOCK(hcryp);
3404 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3405 /*Call registered error callback*/
3406 hcryp->ErrorCallback(hcryp);
3407 #else
3408 /*Call legacy weak error callback*/
3409 HAL_CRYP_ErrorCallback(hcryp);
3410 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3411 }
3412
3413 /* Clear CCF Flag */
3414 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3415
3416 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
3417 for (i = 0U; i < 4U; i++)
3418 {
3419 temp[i] = hcryp->Instance->DOUTR;
3420 }
3421 i = 0U;
3422 while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
3423 {
3424 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3425 hcryp->CrypOutCount++;
3426 i++;
3427 }
3428 #endif /* End AES or CRYP */
3429 }
3430
3431 /**
3432 * @brief Handle CRYP block input/output data handling under interruption.
3433 * @note The function is called under interruption only, once
3434 * interruptions have been enabled by HAL_CRYP_Encrypt_IT or HAL_CRYP_Decrypt_IT.
3435 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3436 * the configuration information for CRYP module.
3437 * @retval HAL status
3438 */
CRYP_AES_IT(CRYP_HandleTypeDef * hcryp)3439 static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
3440 {
3441 uint32_t temp[4]; /* Temporary CrypOutBuff */
3442 uint32_t i;
3443 #if defined (CRYP)
3444 uint16_t incount; /* Temporary CrypInCount Value */
3445 uint16_t outcount; /* Temporary CrypOutCount Value */
3446 #endif
3447
3448 if (hcryp->State == HAL_CRYP_STATE_BUSY)
3449 {
3450 #if defined (CRYP)
3451
3452 /*Temporary CrypOutCount Value*/
3453 incount = hcryp->CrypInCount;
3454 if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
3455 {
3456 /* Write the input block in the IN FIFO */
3457 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3458 hcryp->CrypInCount++;
3459 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3460 hcryp->CrypInCount++;
3461 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3462 hcryp->CrypInCount++;
3463 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3464 hcryp->CrypInCount++;
3465 if (hcryp->CrypInCount == ((uint16_t)(hcryp->Size) / 4U))
3466 {
3467 /* Disable interrupts */
3468 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
3469
3470 /* Call the input data transfer complete callback */
3471 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3472 /*Call registered Input complete callback*/
3473 hcryp->InCpltCallback(hcryp);
3474 #else
3475 /*Call legacy weak Input complete callback*/
3476 HAL_CRYP_InCpltCallback(hcryp);
3477 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3478 }
3479 }
3480 /*Temporary CrypOutCount Value*/
3481 outcount = hcryp->CrypOutCount;
3482
3483 if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
3484 {
3485 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
3486 for (i = 0U; i < 4U; i++)
3487 {
3488 temp[i] = hcryp->Instance->DOUT;
3489 }
3490 i = 0U;
3491 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
3492 {
3493 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3494 hcryp->CrypOutCount++;
3495 i++;
3496 }
3497 if (hcryp->CrypOutCount == ((uint16_t)(hcryp->Size) / 4U))
3498 {
3499 /* Disable interrupts */
3500 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
3501
3502 /* Change the CRYP state */
3503 hcryp->State = HAL_CRYP_STATE_READY;
3504
3505 /* Disable CRYP */
3506 __HAL_CRYP_DISABLE(hcryp);
3507
3508 /* Process unlocked */
3509 __HAL_UNLOCK(hcryp);
3510
3511 /* Call Output transfer complete callback */
3512 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3513 /*Call registered Output complete callback*/
3514 hcryp->OutCpltCallback(hcryp);
3515 #else
3516 /*Call legacy weak Output complete callback*/
3517 HAL_CRYP_OutCpltCallback(hcryp);
3518 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3519 }
3520 }
3521
3522 #else /*AES*/
3523
3524 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
3525 for (i = 0U; i < 4U; i++)
3526 {
3527 temp[i] = hcryp->Instance->DOUTR;
3528 }
3529 i = 0U;
3530 while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
3531 {
3532 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3533 hcryp->CrypOutCount++;
3534 i++;
3535 }
3536
3537 if (hcryp->CrypOutCount == (hcryp->Size / 4U))
3538 {
3539 /* Disable Computation Complete flag and errors interrupts */
3540 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
3541
3542 /* Change the CRYP state */
3543 hcryp->State = HAL_CRYP_STATE_READY;
3544
3545 /* Disable CRYP */
3546 __HAL_CRYP_DISABLE(hcryp);
3547
3548 /* Process Unlocked */
3549 __HAL_UNLOCK(hcryp);
3550
3551 /* Call Output transfer complete callback */
3552 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3553 /*Call registered Output complete callback*/
3554 hcryp->OutCpltCallback(hcryp);
3555 #else
3556 /*Call legacy weak Output complete callback*/
3557 HAL_CRYP_OutCpltCallback(hcryp);
3558 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3559 }
3560 else
3561 {
3562 /* Write the input block in the IN FIFO */
3563 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3564 hcryp->CrypInCount++;
3565 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3566 hcryp->CrypInCount++;
3567 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3568 hcryp->CrypInCount++;
3569 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3570 hcryp->CrypInCount++;
3571
3572 if (hcryp->CrypInCount == (hcryp->Size / 4U))
3573 {
3574 /* Call Input transfer complete callback */
3575 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
3576 /*Call registered Input complete callback*/
3577 hcryp->InCpltCallback(hcryp);
3578 #else
3579 /*Call legacy weak Input complete callback*/
3580 HAL_CRYP_InCpltCallback(hcryp);
3581 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3582 }
3583 }
3584 #endif /* End AES or CRYP */
3585
3586 }
3587 else
3588 {
3589 /* Busy error code field */
3590 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
3591 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3592 /*Call registered error callback*/
3593 hcryp->ErrorCallback(hcryp);
3594 #else
3595 /*Call legacy weak error callback*/
3596 HAL_CRYP_ErrorCallback(hcryp);
3597 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3598 }
3599 }
3600
3601 /**
3602 * @brief Writes Key in Key registers.
3603 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3604 * the configuration information for CRYP module
3605 * @param KeySize: Size of Key
3606 * @retval None
3607 */
CRYP_SetKey(CRYP_HandleTypeDef * hcryp,uint32_t KeySize)3608 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
3609 {
3610 #if defined (CRYP)
3611
3612 switch (KeySize)
3613 {
3614 case CRYP_KEYSIZE_256B:
3615 hcryp->Instance->K0LR = *(uint32_t *)(hcryp->Init.pKey);
3616 hcryp->Instance->K0RR = *(uint32_t *)(hcryp->Init.pKey + 1);
3617 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey + 2);
3618 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 3);
3619 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 4);
3620 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 5);
3621 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 6);
3622 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 7);
3623 break;
3624 case CRYP_KEYSIZE_192B:
3625 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
3626 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
3627 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
3628 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
3629 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
3630 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
3631 break;
3632 case CRYP_KEYSIZE_128B:
3633 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey);
3634 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 1);
3635 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 2);
3636 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 3);
3637
3638 break;
3639 default:
3640 break;
3641 }
3642 #else /*AES*/
3643 switch (KeySize)
3644 {
3645 case CRYP_KEYSIZE_256B:
3646 hcryp->Instance->KEYR7 = *(uint32_t *)(hcryp->Init.pKey);
3647 hcryp->Instance->KEYR6 = *(uint32_t *)(hcryp->Init.pKey + 1);
3648 hcryp->Instance->KEYR5 = *(uint32_t *)(hcryp->Init.pKey + 2);
3649 hcryp->Instance->KEYR4 = *(uint32_t *)(hcryp->Init.pKey + 3);
3650 hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey + 4);
3651 hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 5);
3652 hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 6);
3653 hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 7);
3654 break;
3655 case CRYP_KEYSIZE_128B:
3656 hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey);
3657 hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 1);
3658 hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 2);
3659 hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 3);
3660
3661 break;
3662 default:
3663 break;
3664 }
3665 #endif /* End AES or CRYP */
3666 }
3667
3668
3669 /**
3670 * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG
3671 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3672 * the configuration information for CRYP module
3673 * @param Timeout: Timeout duration
3674 * @retval HAL status
3675 */
CRYP_AESGCM_Process(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)3676 static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
3677 {
3678 uint32_t tickstart;
3679 uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U ;
3680 uint16_t outcount; /* Temporary CrypOutCount Value */
3681 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
3682
3683 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
3684 {
3685 if (hcryp->KeyIVConfig == 1U)
3686 {
3687 /* If the Key and IV configuration has to be done only once
3688 and if it has already been done, skip it */
3689 DoKeyIVConfig = 0U;
3690 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
3691 }
3692 else
3693 {
3694 /* If the Key and IV configuration has to be done only once
3695 and if it has not been done already, do it and set KeyIVConfig
3696 to keep track it won't have to be done again next time */
3697 hcryp->KeyIVConfig = 1U;
3698 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
3699 }
3700 }
3701 else
3702 {
3703 hcryp->SizesSum = hcryp->Size;
3704 }
3705
3706 if (DoKeyIVConfig == 1U)
3707 {
3708 /* Reset CrypHeaderCount */
3709 hcryp->CrypHeaderCount = 0U;
3710
3711 /****************************** Init phase **********************************/
3712
3713 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
3714
3715 /* Set the key */
3716 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3717
3718 #if defined(CRYP)
3719
3720 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3721 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
3722 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3723 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3724 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3725
3726 /* Enable the CRYP peripheral */
3727 __HAL_CRYP_ENABLE(hcryp);
3728
3729 /* Get tick */
3730 tickstart = HAL_GetTick();
3731
3732 /*Wait for the CRYPEN bit to be cleared*/
3733 while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
3734 {
3735 /* Check for the Timeout */
3736 if (Timeout != HAL_MAX_DELAY)
3737 {
3738 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3739 {
3740 /* Disable the CRYP peripheral clock */
3741 __HAL_CRYP_DISABLE(hcryp);
3742
3743 /* Change state */
3744 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3745 hcryp->State = HAL_CRYP_STATE_READY;
3746
3747 /* Process unlocked */
3748 __HAL_UNLOCK(hcryp);
3749 return HAL_ERROR;
3750 }
3751 }
3752 }
3753
3754 #else /* AES */
3755 /* Workaround 1 : only AES.
3756 Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re
3757 enabling the IP, datatype different from 32 bits can be configured.*/
3758 /* Select DATATYPE 32 */
3759 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
3760
3761 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3762 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
3763 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3764 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3765 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3766
3767 /* Enable the CRYP peripheral */
3768 __HAL_CRYP_ENABLE(hcryp);
3769
3770 /* just wait for hash computation */
3771 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
3772 {
3773 /* Change state */
3774 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3775 hcryp->State = HAL_CRYP_STATE_READY;
3776
3777 /* Process unlocked & return error */
3778 __HAL_UNLOCK(hcryp);
3779 return HAL_ERROR;
3780 }
3781 /* Clear CCF flag */
3782 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3783
3784 #endif /* End AES or CRYP */
3785
3786 /************************ Header phase *************************************/
3787
3788 if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
3789 {
3790 return HAL_ERROR;
3791 }
3792
3793 /*************************Payload phase ************************************/
3794
3795 /* Set the phase */
3796 hcryp->Phase = CRYP_PHASE_PROCESS;
3797
3798 #if defined(CRYP)
3799
3800 /* Disable the CRYP peripheral */
3801 __HAL_CRYP_DISABLE(hcryp);
3802
3803 /* Select payload phase once the header phase is performed */
3804 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
3805
3806 /* Enable the CRYP peripheral */
3807 __HAL_CRYP_ENABLE(hcryp);
3808
3809 #else /* AES */
3810
3811 /* Select payload phase once the header phase is performed */
3812 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
3813
3814 #endif /* End AES or CRYP */
3815 } /* if (DoKeyIVConfig == 1U) */
3816
3817 if ((hcryp->Size % 16U) != 0U)
3818 {
3819 /* recalculate wordsize */
3820 wordsize = ((wordsize / 4U) * 4U) ;
3821 }
3822
3823 /* Get tick */
3824 tickstart = HAL_GetTick();
3825 /*Temporary CrypOutCount Value*/
3826 outcount = hcryp->CrypOutCount;
3827
3828 /* Write input data and get output Data */
3829 while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
3830 {
3831 /* Write plain data and get cipher data */
3832 CRYP_AES_ProcessData(hcryp, Timeout);
3833
3834 /*Temporary CrypOutCount Value*/
3835 outcount = hcryp->CrypOutCount;
3836
3837 /* Check for the Timeout */
3838 if (Timeout != HAL_MAX_DELAY)
3839 {
3840 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3841 {
3842 /* Disable the CRYP peripheral clock */
3843 __HAL_CRYP_DISABLE(hcryp);
3844
3845 /* Change state & error code */
3846 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3847 hcryp->State = HAL_CRYP_STATE_READY;
3848
3849 /* Process unlocked */
3850 __HAL_UNLOCK(hcryp);
3851 return HAL_ERROR;
3852 }
3853 }
3854 }
3855
3856 if ((hcryp->Size % 16U) != 0U)
3857 {
3858 /* Workaround 2 : CRYP1 & AES generates correct TAG for GCM mode only when input block size is multiple of
3859 128 bits. If lthe size of the last block of payload is inferior to 128 bits, when GCM encryption
3860 is selected, then the TAG message will be wrong.*/
3861 CRYP_Workaround(hcryp, Timeout);
3862 }
3863
3864 /* Return function status */
3865 return HAL_OK;
3866 }
3867
3868 /**
3869 * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode
3870 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3871 * the configuration information for CRYP module
3872 * @retval HAL status
3873 */
CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef * hcryp)3874 static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
3875 {
3876 __IO uint32_t count = 0U;
3877 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
3878 #if defined(AES)
3879 uint32_t loopcounter;
3880 uint32_t lastwordsize;
3881 uint32_t npblb;
3882 #endif /* AES */
3883
3884 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
3885 {
3886 if (hcryp->KeyIVConfig == 1U)
3887 {
3888 /* If the Key and IV configuration has to be done only once
3889 and if it has already been done, skip it */
3890 DoKeyIVConfig = 0U;
3891 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
3892 }
3893 else
3894 {
3895 /* If the Key and IV configuration has to be done only once
3896 and if it has not been done already, do it and set KeyIVConfig
3897 to keep track it won't have to be done again next time */
3898 hcryp->KeyIVConfig = 1U;
3899 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
3900 }
3901 }
3902 else
3903 {
3904 hcryp->SizesSum = hcryp->Size;
3905 }
3906
3907 /* Configure Key, IV and process message (header and payload) */
3908 if (DoKeyIVConfig == 1U)
3909 {
3910 /* Reset CrypHeaderCount */
3911 hcryp->CrypHeaderCount = 0U;
3912
3913 /******************************* Init phase *********************************/
3914
3915 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
3916
3917 /* Set the key */
3918 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3919
3920 #if defined(CRYP)
3921 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3922 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
3923 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3924 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3925 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3926
3927 /* Enable the CRYP peripheral */
3928 __HAL_CRYP_ENABLE(hcryp);
3929
3930 /*Wait for the CRYPEN bit to be cleared*/
3931 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
3932 do
3933 {
3934 count-- ;
3935 if (count == 0U)
3936 {
3937 /* Disable the CRYP peripheral clock */
3938 __HAL_CRYP_DISABLE(hcryp);
3939
3940 /* Change state */
3941 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3942 hcryp->State = HAL_CRYP_STATE_READY;
3943
3944 /* Process unlocked */
3945 __HAL_UNLOCK(hcryp);
3946 return HAL_ERROR;
3947 }
3948 }
3949 while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
3950
3951 #else /* AES */
3952
3953 /* Workaround 1 : only AES
3954 Datatype configuration must be 32 bits during INIT phase. Only, after INIT, and before re
3955 enabling the IP, datatype different from 32 bits can be configured.*/
3956 /* Select DATATYPE 32 */
3957 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
3958
3959 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3960 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
3961 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3962 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3963 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3964
3965 /* Enable the CRYP peripheral */
3966 __HAL_CRYP_ENABLE(hcryp);
3967
3968 /* just wait for hash computation */
3969 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
3970 do
3971 {
3972 count-- ;
3973 if (count == 0U)
3974 {
3975 /* Disable the CRYP peripheral clock */
3976 __HAL_CRYP_DISABLE(hcryp);
3977
3978 /* Change state */
3979 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3980 hcryp->State = HAL_CRYP_STATE_READY;
3981
3982 /* Process unlocked */
3983 __HAL_UNLOCK(hcryp);
3984 return HAL_ERROR;
3985 }
3986 }
3987 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
3988
3989 /* Clear CCF flag */
3990 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3991
3992 #endif /* End AES or CRYP */
3993
3994 /***************************** Header phase *********************************/
3995
3996 #if defined(CRYP)
3997
3998 /* Select header phase */
3999 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4000
4001 /* Enable interrupts */
4002 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
4003
4004 /* Enable CRYP */
4005 __HAL_CRYP_ENABLE(hcryp);
4006
4007 #else /* AES */
4008
4009 /* Workaround 1: only AES , before re-enabling the IP, datatype can be configured*/
4010 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
4011
4012 /* Select header phase */
4013 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4014
4015 /* Enable computation complete flag and error interrupts */
4016 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
4017
4018 /* Enable the CRYP peripheral */
4019 __HAL_CRYP_ENABLE(hcryp);
4020
4021 if (hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/
4022 {
4023 /* Set the phase */
4024 hcryp->Phase = CRYP_PHASE_PROCESS;
4025
4026 /* Select payload phase once the header phase is performed */
4027 MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
4028
4029 /* Write the payload Input block in the IN FIFO */
4030 if (hcryp->Size == 0U)
4031 {
4032 /* Disable interrupts */
4033 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
4034
4035 /* Change the CRYP state */
4036 hcryp->State = HAL_CRYP_STATE_READY;
4037
4038 /* Process unlocked */
4039 __HAL_UNLOCK(hcryp);
4040 }
4041 else if (hcryp->Size >= 16U)
4042 {
4043 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4044 hcryp->CrypInCount++;
4045 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4046 hcryp->CrypInCount++;
4047 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4048 hcryp->CrypInCount++;
4049 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4050 hcryp->CrypInCount++;
4051 if (hcryp->CrypInCount == (hcryp->Size / 4U))
4052 {
4053 /* Call Input transfer complete callback */
4054 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
4055 /*Call registered Input complete callback*/
4056 hcryp->InCpltCallback(hcryp);
4057 #else
4058 /*Call legacy weak Input complete callback*/
4059 HAL_CRYP_InCpltCallback(hcryp);
4060 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4061 }
4062 }
4063 else /* Size < 16Bytes : first block is the last block*/
4064 {
4065 /* Workaround not implemented*/
4066 /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
4067 Workaround is implemented in polling mode, so if last block of
4068 payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
4069
4070 /* Compute the number of padding bytes in last block of payload */
4071 npblb = 16U - (uint32_t)(hcryp->Size);
4072
4073 /* Number of valid words (lastwordsize) in last block */
4074 if ((npblb % 4U) == 0U)
4075 {
4076 lastwordsize = (16U - npblb) / 4U;
4077 }
4078 else
4079 {
4080 lastwordsize = ((16U - npblb) / 4U) + 1U;
4081 }
4082
4083 /* last block optionally pad the data with zeros*/
4084 for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++)
4085 {
4086 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4087 hcryp->CrypInCount++;
4088 }
4089 while (loopcounter < 4U)
4090 {
4091 /* pad the data with zeros to have a complete block */
4092 hcryp->Instance->DINR = 0x0U;
4093 loopcounter++;
4094 }
4095 }
4096 }
4097 else if ((hcryp->Init.HeaderSize) < 4U)
4098 {
4099 for (loopcounter = 0U; loopcounter < hcryp->Init.HeaderSize ; loopcounter++)
4100 {
4101 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4102 hcryp->CrypHeaderCount++ ;
4103 }
4104 while (loopcounter < 4U)
4105 {
4106 /* pad the data with zeros to have a complete block */
4107 hcryp->Instance->DINR = 0x0U;
4108 loopcounter++;
4109 }
4110 /* Set the phase */
4111 hcryp->Phase = CRYP_PHASE_PROCESS;
4112
4113 /* Select payload phase once the header phase is performed */
4114 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
4115
4116 /* Call Input transfer complete callback */
4117 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
4118 /*Call registered Input complete callback*/
4119 hcryp->InCpltCallback(hcryp);
4120 #else
4121 /*Call legacy weak Input complete callback*/
4122 HAL_CRYP_InCpltCallback(hcryp);
4123 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4124 }
4125 else if ((hcryp->Init.HeaderSize) >= 4U)
4126 {
4127 /* Write the input block in the IN FIFO */
4128 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4129 hcryp->CrypHeaderCount++;
4130 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4131 hcryp->CrypHeaderCount++;
4132 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4133 hcryp->CrypHeaderCount++;
4134 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4135 hcryp->CrypHeaderCount++;
4136 }
4137 else
4138 {
4139 /* Nothing to do */
4140 }
4141
4142 #endif /* End AES or CRYP */
4143 } /* end of if (DoKeyIVConfig == 1U) */
4144
4145 /* Return function status */
4146 return HAL_OK;
4147 }
4148
4149
4150 /**
4151 * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA
4152 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4153 * the configuration information for CRYP module
4154 * @retval HAL status
4155 */
CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef * hcryp)4156 static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
4157 {
4158 __IO uint32_t count = 0U;
4159 uint32_t wordsize;
4160 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4161
4162 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4163 {
4164 if (hcryp->KeyIVConfig == 1U)
4165 {
4166 /* If the Key and IV configuration has to be done only once
4167 and if it has already been done, skip it */
4168 DoKeyIVConfig = 0U;
4169 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4170 }
4171 else
4172 {
4173 /* If the Key and IV configuration has to be done only once
4174 and if it has not been done already, do it and set KeyIVConfig
4175 to keep track it won't have to be done again next time */
4176 hcryp->KeyIVConfig = 1U;
4177 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4178 }
4179 }
4180 else
4181 {
4182 hcryp->SizesSum = hcryp->Size;
4183 }
4184
4185 if (DoKeyIVConfig == 1U)
4186 {
4187 /* Reset CrypHeaderCount */
4188 hcryp->CrypHeaderCount = 0U;
4189
4190 /*************************** Init phase ************************************/
4191
4192 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
4193
4194 /* Set the key */
4195 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4196
4197 #if defined(CRYP)
4198 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
4199 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
4200 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
4201 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
4202 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
4203
4204 /* Enable the CRYP peripheral */
4205 __HAL_CRYP_ENABLE(hcryp);
4206
4207 /*Wait for the CRYPEN bit to be cleared*/
4208 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
4209 do
4210 {
4211 count-- ;
4212 if (count == 0U)
4213 {
4214 /* Disable the CRYP peripheral clock */
4215 __HAL_CRYP_DISABLE(hcryp);
4216
4217 /* Change state */
4218 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4219 hcryp->State = HAL_CRYP_STATE_READY;
4220
4221 /* Process unlocked */
4222 __HAL_UNLOCK(hcryp);
4223 return HAL_ERROR;
4224 }
4225 }
4226 while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
4227
4228 #else /* AES */
4229
4230 /*Workaround 1 : only AES
4231 Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re
4232 enabling the IP, datatype different from 32 bits can be configured.*/
4233 /* Select DATATYPE 32 */
4234 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
4235
4236 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
4237 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
4238 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
4239 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
4240 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
4241
4242 /* Enable the CRYP peripheral */
4243 __HAL_CRYP_ENABLE(hcryp);
4244
4245 /* just wait for hash computation */
4246 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
4247 do
4248 {
4249 count-- ;
4250 if (count == 0U)
4251 {
4252 /* Disable the CRYP peripheral clock */
4253 __HAL_CRYP_DISABLE(hcryp);
4254
4255 /* Change state */
4256 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4257 hcryp->State = HAL_CRYP_STATE_READY;
4258
4259 /* Process unlocked */
4260 __HAL_UNLOCK(hcryp);
4261 return HAL_ERROR;
4262 }
4263 }
4264 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
4265
4266 /* Clear CCF flag */
4267 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4268
4269 #endif /* End AES or CRYP */
4270
4271 /************************ Header phase *************************************/
4272
4273 if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
4274 {
4275 return HAL_ERROR;
4276 }
4277
4278 /************************ Payload phase ************************************/
4279
4280 /* Set the phase */
4281 hcryp->Phase = CRYP_PHASE_PROCESS;
4282
4283 #if defined(CRYP)
4284
4285 /* Disable the CRYP peripheral */
4286 __HAL_CRYP_DISABLE(hcryp);
4287
4288 #endif /* CRYP */
4289
4290 /* Select payload phase once the header phase is performed */
4291 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
4292
4293 } /* if (DoKeyIVConfig == 1U) */
4294
4295 if (hcryp->Size != 0U)
4296 {
4297 /* CRYP1 IP V < 2.2.1 Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
4298 Workaround is implemented in polling mode, so if last block of
4299 payload <128bit don't use DMA mode otherwise TAG is incorrectly generated . */
4300 /* Set the input and output addresses and start DMA transfer */
4301 if ((hcryp->Size % 16U) == 0U)
4302 {
4303 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
4304 }
4305 else /*to compute last word<128bits, otherwise it will not be encrypted/decrypted */
4306 {
4307 wordsize = (uint32_t)(hcryp->Size) + (16U - ((uint32_t)(hcryp->Size) % 16U)) ;
4308
4309 /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4 */
4310 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)wordsize / 4U),
4311 (uint32_t)(hcryp->pCrypOutBuffPtr));
4312 }
4313 }
4314 else
4315 {
4316 /* Process unLocked */
4317 __HAL_UNLOCK(hcryp);
4318
4319 /* Change the CRYP state and phase */
4320 hcryp->State = HAL_CRYP_STATE_READY;
4321 }
4322
4323 /* Return function status */
4324 return HAL_OK;
4325 }
4326
4327
4328 /**
4329 * @brief AES CCM encryption/decryption processing in polling mode
4330 * for TinyAES IP, no encrypt/decrypt performed, only authentication preparation.
4331 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4332 * the configuration information for CRYP module
4333 * @param Timeout: Timeout duration
4334 * @retval HAL status
4335 */
CRYP_AESCCM_Process(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)4336 static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
4337 {
4338 uint32_t tickstart;
4339 uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U;
4340 uint16_t outcount; /* Temporary CrypOutCount Value */
4341 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4342 #if defined(AES)
4343 uint32_t loopcounter;
4344 uint32_t npblb;
4345 uint32_t lastwordsize;
4346 #endif /* AES */
4347
4348 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4349 {
4350 if (hcryp->KeyIVConfig == 1U)
4351 {
4352 /* If the Key and IV configuration has to be done only once
4353 and if it has already been done, skip it */
4354 DoKeyIVConfig = 0U;
4355 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4356 }
4357 else
4358 {
4359 /* If the Key and IV configuration has to be done only once
4360 and if it has not been done already, do it and set KeyIVConfig
4361 to keep track it won't have to be done again next time */
4362 hcryp->KeyIVConfig = 1U;
4363 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4364 }
4365 }
4366 else
4367 {
4368 hcryp->SizesSum = hcryp->Size;
4369 }
4370
4371 if (DoKeyIVConfig == 1U)
4372 {
4373
4374 /* Reset CrypHeaderCount */
4375 hcryp->CrypHeaderCount = 0U;
4376
4377 #if defined(CRYP)
4378
4379 /********************** Init phase ******************************************/
4380
4381 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
4382
4383 /* Set the key */
4384 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4385
4386 /* Set the initialization vector (IV) with CTR1 information */
4387 hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
4388 hcryp->Instance->IV0RR = hcryp->Init.B0[1];
4389 hcryp->Instance->IV1LR = hcryp->Init.B0[2];
4390 hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
4391
4392
4393 /* Enable the CRYP peripheral */
4394 __HAL_CRYP_ENABLE(hcryp);
4395
4396 /*Write B0 packet into CRYP_DIN Register*/
4397 if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
4398 {
4399 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
4400 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
4401 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
4402 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
4403 }
4404 else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
4405 {
4406 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
4407 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
4408 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
4409 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
4410 }
4411 else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
4412 {
4413 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
4414 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
4415 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
4416 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
4417 }
4418 else
4419 {
4420 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
4421 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
4422 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
4423 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
4424 }
4425 /* Get tick */
4426 tickstart = HAL_GetTick();
4427
4428 /*Wait for the CRYPEN bit to be cleared*/
4429 while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
4430 {
4431 /* Check for the Timeout */
4432 if (Timeout != HAL_MAX_DELAY)
4433 {
4434 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
4435 {
4436 /* Disable the CRYP peripheral clock */
4437 __HAL_CRYP_DISABLE(hcryp);
4438
4439 /* Change state */
4440 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4441 hcryp->State = HAL_CRYP_STATE_READY;
4442
4443 /* Process unlocked */
4444 __HAL_UNLOCK(hcryp);
4445 return HAL_ERROR;
4446 }
4447 }
4448 }
4449 #else /* AES */
4450 /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
4451 /* Select header phase */
4452 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4453
4454 /* configured encryption mode */
4455 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
4456
4457 /* Set the key */
4458 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4459
4460 /* Set the initialization vector with zero values*/
4461 hcryp->Instance->IVR3 = 0U;
4462 hcryp->Instance->IVR2 = 0U;
4463 hcryp->Instance->IVR1 = 0U;
4464 hcryp->Instance->IVR0 = 0U;
4465
4466 /* Enable the CRYP peripheral */
4467 __HAL_CRYP_ENABLE(hcryp);
4468
4469 /*Write the B0 packet into CRYP_DIN*/
4470 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0);
4471 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1);
4472 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2);
4473 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3);
4474
4475 /* wait until the end of computation */
4476 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4477 {
4478 /* Change state */
4479 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4480 hcryp->State = HAL_CRYP_STATE_READY;
4481
4482 /* Process unlocked & return error */
4483 __HAL_UNLOCK(hcryp);
4484 return HAL_ERROR;
4485 }
4486 /* Clear CCF flag */
4487 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4488
4489 /* Set the phase */
4490 hcryp->Phase = CRYP_PHASE_PROCESS;
4491
4492 /* From that point the whole message must be processed, first the Header then the payload.
4493 First the Header block(B1) : associated data length expressed in bytes concatenated with Associated Data (A)*/
4494
4495 if (hcryp->Init.HeaderSize != 0U)
4496 {
4497 if ((hcryp->Init.HeaderSize % 4U) == 0U)
4498 {
4499 /* HeaderSize %4, no padding */
4500 for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
4501 {
4502 /* Write the Input block in the Data Input register */
4503 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4504 hcryp->CrypHeaderCount++ ;
4505 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4506 hcryp->CrypHeaderCount++ ;
4507 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4508 hcryp->CrypHeaderCount++ ;
4509 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4510 hcryp->CrypHeaderCount++ ;
4511
4512 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4513 {
4514 /* Disable the CRYP peripheral clock */
4515 __HAL_CRYP_DISABLE(hcryp);
4516
4517 /* Change state */
4518 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4519 hcryp->State = HAL_CRYP_STATE_READY;
4520
4521 /* Process unlocked */
4522 __HAL_UNLOCK(hcryp);
4523 return HAL_ERROR;
4524 }
4525 /* Clear CCF Flag */
4526 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4527 }
4528 }
4529 else
4530 {
4531 /*Write Header block in the IN FIFO without last block */
4532 for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
4533 {
4534 /* Write the input block in the data input register */
4535 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4536 hcryp->CrypHeaderCount++ ;
4537 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4538 hcryp->CrypHeaderCount++ ;
4539 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4540 hcryp->CrypHeaderCount++ ;
4541 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4542 hcryp->CrypHeaderCount++ ;
4543
4544 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4545 {
4546 /* Disable the CRYP peripheral clock */
4547 __HAL_CRYP_DISABLE(hcryp);
4548
4549 /* Change state */
4550 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4551 hcryp->State = HAL_CRYP_STATE_READY;
4552
4553 /* Process unlocked */
4554 __HAL_UNLOCK(hcryp);
4555 return HAL_ERROR;
4556 }
4557 /* Clear CCF Flag */
4558 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4559 }
4560 /* Last block optionally pad the data with zeros*/
4561 for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
4562 {
4563 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4564 hcryp->CrypHeaderCount++ ;
4565 }
4566 while (loopcounter < 4U)
4567 {
4568 /* Pad the data with zeros to have a complete block */
4569 hcryp->Instance->DINR = 0x0U;
4570 loopcounter++;
4571 }
4572
4573 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4574 {
4575 /* Disable the CRYP peripheral clock */
4576 __HAL_CRYP_DISABLE(hcryp);
4577
4578 /* Change state */
4579 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4580 hcryp->State = HAL_CRYP_STATE_READY;
4581
4582 /* Process unlocked */
4583 __HAL_UNLOCK(hcryp);
4584 return HAL_ERROR;
4585 }
4586 /* Clear CCF flag */
4587 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4588 }
4589 }
4590 } /* if (DoKeyIVConfig == 1U) */
4591 /* Then the payload: cleartext payload (not the ciphertext payload).
4592 Write input Data, no output Data to get */
4593 if (hcryp->Size != 0U)
4594 {
4595 if ((hcryp->Size % 16U) != 0U)
4596 {
4597 /* recalculate wordsize */
4598 wordsize = ((wordsize / 4U) * 4U) ;
4599 }
4600
4601 /* Get tick */
4602 tickstart = HAL_GetTick();
4603 /*Temporary CrypOutCount Value*/
4604 outcount = hcryp->CrypOutCount;
4605
4606 while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
4607 {
4608 /* Write plain data and get cipher data */
4609 CRYP_AES_ProcessData(hcryp, Timeout);
4610
4611 /*Temporary CrypOutCount Value*/
4612 outcount = hcryp->CrypOutCount;
4613
4614 /* Check for the Timeout */
4615 if (Timeout != HAL_MAX_DELAY)
4616 {
4617 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
4618 {
4619 /* Disable the CRYP peripheral clock */
4620 __HAL_CRYP_DISABLE(hcryp);
4621
4622 /* Change state */
4623 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4624 hcryp->State = HAL_CRYP_STATE_READY;
4625
4626 /* Process unlocked */
4627 __HAL_UNLOCK(hcryp);
4628 return HAL_ERROR;
4629 }
4630 }
4631 }
4632
4633 if ((hcryp->Size % 16U) != 0U)
4634 {
4635 /* Compute the number of padding bytes in last block of payload */
4636 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
4637
4638 /* Number of valid words (lastwordsize) in last block */
4639 if ((npblb % 4U) == 0U)
4640 {
4641 lastwordsize = (16U - npblb) / 4U;
4642 }
4643 else
4644 {
4645 lastwordsize = ((16U - npblb) / 4U) + 1U;
4646 }
4647 /* Last block optionally pad the data with zeros*/
4648 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++)
4649 {
4650 /* Write the last input block in the IN FIFO */
4651 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4652 hcryp->CrypInCount++;
4653 }
4654 while (loopcounter < 4U)
4655 {
4656 /* Pad the data with zeros to have a complete block */
4657 hcryp->Instance->DINR = 0U;
4658 loopcounter++;
4659 }
4660 /* Wait for CCF flag to be raised */
4661 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4662 {
4663 /* Disable the CRYP peripheral clock */
4664 __HAL_CRYP_DISABLE(hcryp);
4665
4666 /* Change state */
4667 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4668 hcryp->State = HAL_CRYP_STATE_READY;
4669
4670 /* Process unlocked */
4671 __HAL_UNLOCK(hcryp);
4672 return HAL_ERROR;
4673 }
4674 /* Clear CCF flag */
4675 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4676
4677 }
4678 }
4679 #endif /* End AES or CRYP */
4680
4681 #if defined(CRYP)
4682
4683 /************************* Header phase *************************************/
4684 /* Header block(B1) : associated data length expressed in bytes concatenated
4685 with Associated Data (A)*/
4686
4687 if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
4688 {
4689 return HAL_ERROR;
4690 }
4691
4692 /********************** Payload phase ***************************************/
4693
4694 /* Set the phase */
4695 hcryp->Phase = CRYP_PHASE_PROCESS;
4696
4697 /* Disable the CRYP peripheral */
4698 __HAL_CRYP_DISABLE(hcryp);
4699
4700 /* Select payload phase once the header phase is performed */
4701 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
4702
4703 /* Enable the CRYP peripheral */
4704 __HAL_CRYP_ENABLE(hcryp);
4705
4706 } /* if (DoKeyIVConfig == 1U) */
4707
4708 if ((hcryp->Size % 16U) != 0U)
4709 {
4710 /* recalculate wordsize */
4711 wordsize = ((wordsize / 4U) * 4U) ;
4712 }
4713 /* Get tick */
4714 tickstart = HAL_GetTick();
4715 /*Temporary CrypOutCount Value*/
4716 outcount = hcryp->CrypOutCount;
4717
4718 /* Write input data and get output data */
4719 while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
4720 {
4721 /* Write plain data and get cipher data */
4722 CRYP_AES_ProcessData(hcryp, Timeout);
4723
4724 /* Check for the Timeout */
4725 if (Timeout != HAL_MAX_DELAY)
4726 {
4727 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
4728 {
4729 /* Disable the CRYP peripheral clock */
4730 __HAL_CRYP_DISABLE(hcryp);
4731
4732 /* Change state */
4733 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4734 hcryp->State = HAL_CRYP_STATE_READY;
4735
4736 /* Process unlocked */
4737 __HAL_UNLOCK(hcryp);
4738 return HAL_ERROR;
4739 }
4740 }
4741 }
4742
4743 if ((hcryp->Size % 16U) != 0U)
4744 {
4745 /* CRYP Workaround : CRYP1 generates correct TAG during CCM decryption only when ciphertext blocks size is multiple of
4746 128 bits. If lthe size of the last block of payload is inferior to 128 bits, when CCM decryption
4747 is selected, then the TAG message will be wrong.*/
4748 CRYP_Workaround(hcryp, Timeout);
4749 }
4750 #endif /* CRYP */
4751
4752 /* Return function status */
4753 return HAL_OK;
4754 }
4755
4756 /**
4757 * @brief AES CCM encryption/decryption process in interrupt mode
4758 * for TinyAES IP, no encrypt/decrypt performed, only authentication preparation.
4759 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4760 * the configuration information for CRYP module
4761 * @retval HAL status
4762 */
4763 static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
4764 {
4765 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4766 #if defined(CRYP)
4767 __IO uint32_t count = 0U;
4768 #endif /* CRYP */
4769
4770 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4771 {
4772 if (hcryp->KeyIVConfig == 1U)
4773 {
4774 /* If the Key and IV configuration has to be done only once
4775 and if it has already been done, skip it */
4776 DoKeyIVConfig = 0U;
4777 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4778 }
4779 else
4780 {
4781 /* If the Key and IV configuration has to be done only once
4782 and if it has not been done already, do it and set KeyIVConfig
4783 to keep track it won't have to be done again next time */
4784 hcryp->KeyIVConfig = 1U;
4785 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4786 }
4787 }
4788 else
4789 {
4790 hcryp->SizesSum = hcryp->Size;
4791 }
4792
4793 /* Configure Key, IV and process message (header and payload) */
4794 if (DoKeyIVConfig == 1U)
4795 {
4796 /* Reset CrypHeaderCount */
4797 hcryp->CrypHeaderCount = 0U;
4798
4799 #if defined(CRYP)
4800
4801 /************ Init phase ************/
4802
4803 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
4804
4805 /* Set the key */
4806 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4807
4808 /* Set the initialization vector (IV) with CTR1 information */
4809 hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
4810 hcryp->Instance->IV0RR = hcryp->Init.B0[1];
4811 hcryp->Instance->IV1LR = hcryp->Init.B0[2];
4812 hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
4813
4814 /* Enable the CRYP peripheral */
4815 __HAL_CRYP_ENABLE(hcryp);
4816
4817 /*Write the B0 packet into CRYP_DIN Register*/
4818 if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
4819 {
4820 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
4821 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
4822 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
4823 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
4824 }
4825 else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
4826 {
4827 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
4828 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
4829 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
4830 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
4831 }
4832 else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
4833 {
4834 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
4835 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
4836 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
4837 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
4838 }
4839 else
4840 {
4841 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
4842 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
4843 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
4844 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
4845 }
4846 /*Wait for the CRYPEN bit to be cleared*/
4847 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
4848 do
4849 {
4850 count-- ;
4851 if (count == 0U)
4852 {
4853 /* Disable the CRYP peripheral clock */
4854 __HAL_CRYP_DISABLE(hcryp);
4855
4856 /* Change state */
4857 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4858 hcryp->State = HAL_CRYP_STATE_READY;
4859
4860 /* Process unlocked */
4861 __HAL_UNLOCK(hcryp);
4862 return HAL_ERROR;
4863 }
4864 }
4865 while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
4866
4867 /* Select header phase */
4868 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4869
4870 } /* end of if (DoKeyIVConfig == 1U) */
4871
4872 /* Enable interrupts */
4873 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
4874
4875 /* Enable CRYP */
4876 __HAL_CRYP_ENABLE(hcryp);
4877
4878 #else /* AES */
4879
4880 /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
4881 /* Select header phase */
4882 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4883
4884 /* configured mode and encryption mode */
4885 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
4886
4887 /* Set the key */
4888 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4889
4890 /* Set the initialization vector with zero values*/
4891 hcryp->Instance->IVR3 = 0U;
4892 hcryp->Instance->IVR2 = 0U;
4893 hcryp->Instance->IVR1 = 0U;
4894 hcryp->Instance->IVR0 = 0U;
4895
4896 /* Enable interrupts */
4897 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
4898 /* Enable the CRYP peripheral */
4899 __HAL_CRYP_ENABLE(hcryp);
4900
4901 /*Write the B0 packet into CRYP_DIN*/
4902 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0);
4903 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1);
4904 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2);
4905 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3);
4906
4907 } /* end of if (DoKeyIVConfig == 1U) */
4908 #endif /* End AES or CRYP */
4909
4910 /* Return function status */
4911 return HAL_OK;
4912 }
4913 /**
4914 * @brief AES CCM encryption/decryption process in DMA mode
4915 * for TinyAES IP, no encrypt/decrypt performed, only authentication preparation.
4916 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4917 * the configuration information for CRYP module
4918 * @retval HAL status
4919 */
4920 static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
4921 {
4922 uint32_t wordsize;
4923 __IO uint32_t count = 0U;
4924 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4925 #if defined(AES)
4926 uint32_t loopcounter;
4927 uint32_t npblb;
4928 uint32_t lastwordsize;
4929 #endif
4930
4931 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4932 {
4933 if (hcryp->KeyIVConfig == 1U)
4934 {
4935 /* If the Key and IV configuration has to be done only once
4936 and if it has already been done, skip it */
4937 DoKeyIVConfig = 0U;
4938 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4939 }
4940 else
4941 {
4942 /* If the Key and IV configuration has to be done only once
4943 and if it has not been done already, do it and set KeyIVConfig
4944 to keep track it won't have to be done again next time */
4945 hcryp->KeyIVConfig = 1U;
4946 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4947 }
4948 }
4949 else
4950 {
4951 hcryp->SizesSum = hcryp->Size;
4952 }
4953
4954 if (DoKeyIVConfig == 1U)
4955 {
4956
4957 /* Reset CrypHeaderCount */
4958 hcryp->CrypHeaderCount = 0U;
4959
4960 #if defined(CRYP)
4961
4962 /************************** Init phase **************************************/
4963
4964 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
4965
4966 /* Set the key */
4967 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4968
4969 /* Set the initialization vector (IV) with CTR1 information */
4970 hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
4971 hcryp->Instance->IV0RR = hcryp->Init.B0[1];
4972 hcryp->Instance->IV1LR = hcryp->Init.B0[2];
4973 hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
4974
4975 /* Enable the CRYP peripheral */
4976 __HAL_CRYP_ENABLE(hcryp);
4977
4978 /*Write the B0 packet into CRYP_DIN Register*/
4979 if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
4980 {
4981 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
4982 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
4983 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
4984 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
4985 }
4986 else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
4987 {
4988 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
4989 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
4990 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
4991 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
4992 }
4993 else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
4994 {
4995 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
4996 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
4997 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
4998 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
4999 }
5000 else
5001 {
5002 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
5003 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
5004 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
5005 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
5006 }
5007
5008 /*Wait for the CRYPEN bit to be cleared*/
5009 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5010 do
5011 {
5012 count-- ;
5013 if (count == 0U)
5014 {
5015 /* Disable the CRYP peripheral clock */
5016 __HAL_CRYP_DISABLE(hcryp);
5017
5018 /* Change state */
5019 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5020 hcryp->State = HAL_CRYP_STATE_READY;
5021
5022 /* Process unlocked */
5023 __HAL_UNLOCK(hcryp);
5024 return HAL_ERROR;
5025 }
5026 }
5027 while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
5028
5029 #else /* AES */
5030
5031 /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
5032 /* Select header phase */
5033 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5034
5035 /* configured encryption mode */
5036 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
5037
5038 /* Set the key */
5039 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
5040
5041 /* Set the initialization vector with zero values*/
5042 hcryp->Instance->IVR3 = 0U;
5043 hcryp->Instance->IVR2 = 0U;
5044 hcryp->Instance->IVR1 = 0U;
5045 hcryp->Instance->IVR0 = 0U;
5046
5047 /* Enable the CRYP peripheral */
5048 __HAL_CRYP_ENABLE(hcryp);
5049
5050 /*Write the B0 packet into CRYP_DIN*/
5051 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0);
5052 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1);
5053 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2);
5054 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3);
5055
5056 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5057 do
5058 {
5059 count-- ;
5060 if (count == 0U)
5061 {
5062 /* Disable the CRYP peripheral clock */
5063 __HAL_CRYP_DISABLE(hcryp);
5064
5065 /* Change state */
5066 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5067 hcryp->State = HAL_CRYP_STATE_READY;
5068
5069 /* Process Unlocked */
5070 __HAL_UNLOCK(hcryp);
5071 return HAL_ERROR;
5072 }
5073 }
5074 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5075 /* Clear CCF flag */
5076 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5077
5078 /* Set the phase */
5079 hcryp->Phase = CRYP_PHASE_PROCESS;
5080
5081 /* From that point the whole message must be processed, first the Header then the payload.
5082 First the Header block(B1) : associated data length expressed in bytes concatenated with Associated Data (A)*/
5083
5084 if (hcryp->Init.HeaderSize != 0U)
5085 {
5086 if ((hcryp->Init.HeaderSize % 4U) == 0U)
5087 {
5088 /* HeaderSize %4, no padding */
5089 for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
5090 {
5091 /* Write the Input block in the Data Input register */
5092 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5093 hcryp->CrypHeaderCount++ ;
5094 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5095 hcryp->CrypHeaderCount++ ;
5096 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5097 hcryp->CrypHeaderCount++ ;
5098 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5099 hcryp->CrypHeaderCount++ ;
5100
5101 /* wait until the end of computation */
5102 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5103 do
5104 {
5105 count-- ;
5106 if (count == 0U)
5107 {
5108 /* Disable the CRYP peripheral clock */
5109 __HAL_CRYP_DISABLE(hcryp);
5110
5111 /* Change state */
5112 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5113 hcryp->State = HAL_CRYP_STATE_READY;
5114
5115 /* Process Unlocked */
5116 __HAL_UNLOCK(hcryp);
5117 return HAL_ERROR;
5118 }
5119 }
5120 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5121 /* Clear CCF flag */
5122 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5123 }
5124 }
5125 else
5126 {
5127 /*Write Header block in the IN FIFO without last block */
5128 for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
5129 {
5130 /* Write the input block in the data input register */
5131 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5132 hcryp->CrypHeaderCount++ ;
5133 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5134 hcryp->CrypHeaderCount++ ;
5135 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5136 hcryp->CrypHeaderCount++ ;
5137 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5138 hcryp->CrypHeaderCount++ ;
5139
5140 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5141 do
5142 {
5143 count-- ;
5144 if (count == 0U)
5145 {
5146 /* Disable the CRYP peripheral clock */
5147 __HAL_CRYP_DISABLE(hcryp);
5148
5149 /* Change state */
5150 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5151 hcryp->State = HAL_CRYP_STATE_READY;
5152
5153 /* Process Unlocked */
5154 __HAL_UNLOCK(hcryp);
5155 return HAL_ERROR;
5156 }
5157 }
5158 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5159 /* Clear CCF flag */
5160 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5161 }
5162 /* Last block optionally pad the data with zeros*/
5163 for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
5164 {
5165 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5166 hcryp->CrypHeaderCount++ ;
5167 }
5168 while (loopcounter < 4U)
5169 {
5170 /* Pad the data with zeros to have a complete block */
5171 hcryp->Instance->DINR = 0x0U;
5172 loopcounter++;
5173 }
5174
5175 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5176 do
5177 {
5178 count-- ;
5179 if (count == 0U)
5180 {
5181 /* Disable the CRYP peripheral clock */
5182 __HAL_CRYP_DISABLE(hcryp);
5183
5184 /* Change state */
5185 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5186 hcryp->State = HAL_CRYP_STATE_READY;
5187
5188 /* Process Unlocked */
5189 __HAL_UNLOCK(hcryp);
5190 return HAL_ERROR;
5191 }
5192 }
5193 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5194 /* Clear CCF flag */
5195 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5196 }
5197 }
5198 } /* if (DoKeyIVConfig == 1U) */
5199 /* Then the payload: cleartext payload (not the ciphertext payload).
5200 Write input Data, no output Data to get */
5201 if (hcryp->Size != 0U)
5202 {
5203 if (hcryp->Size >= 16U)
5204 {
5205 if ((hcryp->Size % 16U) == 0U)
5206 {
5207 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
5208 }
5209 else /*to compute last word<128bits, otherwise it will not be encrypted/decrypted */
5210 {
5211 wordsize = (uint32_t)(hcryp->Size) + (16U - ((uint32_t)(hcryp->Size) % 16U)) ;
5212
5213 /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4 */
5214 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)wordsize / 4U),
5215 (uint32_t)(hcryp->pCrypOutBuffPtr));
5216 }
5217 }
5218 if ((hcryp->Size < 16U) != 0U)
5219 {
5220 /* Compute the number of padding bytes in last block of payload */
5221 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
5222
5223 /* Number of valid words (lastwordsize) in last block */
5224 if ((npblb % 4U) == 0U)
5225 {
5226 lastwordsize = (16U - npblb) / 4U;
5227 }
5228 else
5229 {
5230 lastwordsize = ((16U - npblb) / 4U) + 1U;
5231 }
5232 /* Last block optionally pad the data with zeros*/
5233 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++)
5234 {
5235 /* Write the last input block in the IN FIFO */
5236 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5237 hcryp->CrypInCount++;
5238 }
5239 while (loopcounter < 4U)
5240 {
5241 /* Pad the data with zeros to have a complete block */
5242 hcryp->Instance->DINR = 0U;
5243 loopcounter++;
5244 }
5245 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5246 do
5247 {
5248 count-- ;
5249 if (count == 0U)
5250 {
5251 /* Disable the CRYP peripheral clock */
5252 __HAL_CRYP_DISABLE(hcryp);
5253
5254 /* Change state */
5255 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5256 hcryp->State = HAL_CRYP_STATE_READY;
5257
5258 /* Process Unlocked */
5259 __HAL_UNLOCK(hcryp);
5260 return HAL_ERROR;
5261 }
5262 }
5263 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5264 /* Clear CCF flag */
5265 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5266
5267 /* Process unlocked */
5268 __HAL_UNLOCK(hcryp);
5269
5270 /* Change the CRYP state and phase */
5271 hcryp->State = HAL_CRYP_STATE_READY;
5272 }
5273 }
5274 else
5275 {
5276 /* Process unLocked */
5277 __HAL_UNLOCK(hcryp);
5278
5279 /* Change the CRYP state and phase */
5280 hcryp->State = HAL_CRYP_STATE_READY;
5281 }
5282 #endif /* AES */
5283 #if defined(CRYP)
5284 /********************* Header phase *****************************************/
5285
5286 if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
5287 {
5288 return HAL_ERROR;
5289 }
5290
5291 /******************** Payload phase *****************************************/
5292
5293 /* Set the phase */
5294 hcryp->Phase = CRYP_PHASE_PROCESS;
5295
5296 /* Disable the CRYP peripheral */
5297 __HAL_CRYP_DISABLE(hcryp);
5298
5299 /* Select payload phase once the header phase is performed */
5300 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
5301
5302 } /* if (DoKeyIVConfig == 1U) */
5303 if (hcryp->Size != 0U)
5304 {
5305 /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption & CCM Decryption
5306 Workaround is implemented in polling mode, so if last block of
5307 payload <128bit don't use HAL_CRYP_AESGCM_DMA otherwise TAG is incorrectly generated for GCM Encryption. */
5308 /* Set the input and output addresses and start DMA transfer */
5309 if ((hcryp->Size % 16U) == 0U)
5310 {
5311 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), hcryp->Size / 4U, (uint32_t)(hcryp->pCrypOutBuffPtr));
5312 }
5313 else
5314 {
5315 wordsize = (uint32_t)(hcryp->Size) + 16U - ((uint32_t)(hcryp->Size) % 16U) ;
5316
5317 /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4*/
5318 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t)wordsize / 4U,
5319 (uint32_t)(hcryp->pCrypOutBuffPtr));
5320 }
5321 }
5322 else /*Size = 0*/
5323 {
5324 /* Process unlocked */
5325 __HAL_UNLOCK(hcryp);
5326
5327 /* Change the CRYP state and phase */
5328 hcryp->State = HAL_CRYP_STATE_READY;
5329 }
5330 #endif /* CRYP */
5331 /* Return function status */
5332 return HAL_OK;
5333 }
5334
5335 /**
5336 * @brief Sets the payload phase in interrupt mode
5337 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
5338 * the configuration information for CRYP module
5339 * @retval state
5340 */
5341 static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
5342 {
5343 uint32_t loopcounter;
5344 uint32_t temp[4]; /* Temporary CrypOutBuff */
5345 uint32_t lastwordsize;
5346 uint32_t npblb;
5347 uint32_t i;
5348 #if defined(AES)
5349 uint16_t outcount; /* Temporary CrypOutCount Value */
5350 #endif /* AES */
5351
5352 /***************************** Payload phase *******************************/
5353
5354 #if defined(CRYP)
5355 if (hcryp->Size == 0U)
5356 {
5357 /* Disable interrupts */
5358 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
5359
5360 /* Process unlocked */
5361 __HAL_UNLOCK(hcryp);
5362
5363 /* Change the CRYP state */
5364 hcryp->State = HAL_CRYP_STATE_READY;
5365 }
5366
5367 else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
5368 {
5369 /* Write the input block in the IN FIFO */
5370 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5371 hcryp->CrypInCount++;
5372 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5373 hcryp->CrypInCount++;
5374 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5375 hcryp->CrypInCount++;
5376 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5377 hcryp->CrypInCount++;
5378 if (((hcryp->Size / 4U) == hcryp->CrypInCount) && ((hcryp->Size % 16U) == 0U))
5379 {
5380 /* Disable interrupts */
5381 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
5382
5383 /* Call the input data transfer complete callback */
5384 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
5385 /*Call registered Input complete callback*/
5386 hcryp->InCpltCallback(hcryp);
5387 #else
5388 /*Call legacy weak Input complete callback*/
5389 HAL_CRYP_InCpltCallback(hcryp);
5390 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5391 }
5392 if (hcryp->CrypOutCount < (hcryp->Size / 4U))
5393 {
5394 /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
5395 for (i = 0U; i < 4U; i++)
5396 {
5397 temp[i] = hcryp->Instance->DOUT;
5398 }
5399 i = 0U;
5400 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
5401 {
5402 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
5403 hcryp->CrypOutCount++;
5404 i++;
5405 }
5406 if (((hcryp->Size / 4U) == hcryp->CrypOutCount) && ((hcryp->Size % 16U) == 0U))
5407 {
5408 /* Disable interrupts */
5409 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
5410
5411 /* Change the CRYP state */
5412 hcryp->State = HAL_CRYP_STATE_READY;
5413
5414 /* Disable CRYP */
5415 __HAL_CRYP_DISABLE(hcryp);
5416
5417 /* Process unlocked */
5418 __HAL_UNLOCK(hcryp);
5419
5420 /* Call output transfer complete callback */
5421 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
5422 /*Call registered Output complete callback*/
5423 hcryp->OutCpltCallback(hcryp);
5424 #else
5425 /*Call legacy weak Output complete callback*/
5426 HAL_CRYP_OutCpltCallback(hcryp);
5427 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5428 }
5429 }
5430 }
5431 else if ((hcryp->Size % 16U) != 0U)
5432 {
5433 /* Size should be %4 in word and %16 in byte otherwise TAG will be incorrectly generated for GCM Encryption & CCM Decryption
5434 Workaround is implemented in polling mode, so if last block of
5435 payload <128bit don't use CRYP_AESGCM_Encrypt_IT otherwise TAG is incorrectly generated. */
5436
5437 /* Compute the number of padding bytes in last block of payload */
5438 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
5439
5440 /* Number of valid words (lastwordsize) in last block */
5441 if ((npblb % 4U) == 0U)
5442 {
5443 lastwordsize = (16U - npblb) / 4U;
5444 }
5445 else
5446 {
5447 lastwordsize = ((16U - npblb) / 4U) + 1U;
5448 }
5449
5450 /* Last block optionally pad the data with zeros*/
5451 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
5452 {
5453 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5454 hcryp->CrypInCount++;
5455 }
5456 while (loopcounter < 4U)
5457 {
5458 /* Pad the data with zeros to have a complete block */
5459 hcryp->Instance->DIN = 0x0U;
5460 loopcounter++;
5461 }
5462 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
5463
5464 if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
5465 {
5466 for (i = 0U; i < 4U; i++)
5467 {
5468 temp[i] = hcryp->Instance->DOUT;
5469 }
5470 if (((hcryp->Size) / 4U) == 0U)
5471 {
5472 for (i = 0U; i < ((uint32_t)(hcryp->Size) % 4U); i++)
5473 {
5474 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
5475 hcryp->CrypOutCount++;
5476 }
5477 }
5478 i = 0x0U;
5479 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
5480 {
5481 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
5482 hcryp->CrypOutCount++;
5483 i++;
5484 }
5485 }
5486 if (hcryp->CrypOutCount >= (hcryp->Size / 4U))
5487 {
5488 /* Disable interrupts */
5489 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI | CRYP_IT_INI);
5490
5491 /* Change the CRYP peripheral state */
5492 hcryp->State = HAL_CRYP_STATE_READY;
5493
5494 /* Process unlocked */
5495 __HAL_UNLOCK(hcryp);
5496
5497 /* Call output transfer complete callback */
5498 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
5499 /*Call registered Output complete callback*/
5500 hcryp->OutCpltCallback(hcryp);
5501 #else
5502 /*Call legacy weak Output complete callback*/
5503 HAL_CRYP_OutCpltCallback(hcryp);
5504 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5505 }
5506 }
5507 else
5508 {
5509 /* Nothing to do */
5510 }
5511 #else /* AES */
5512
5513 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
5514 for (i = 0U; i < 4U; i++)
5515 {
5516 temp[i] = hcryp->Instance->DOUTR;
5517 }
5518 i = 0U;
5519 while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
5520 {
5521 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
5522 hcryp->CrypOutCount++;
5523 i++;
5524 }
5525 /*Temporary CrypOutCount Value*/
5526 outcount = hcryp->CrypOutCount;
5527
5528 if ((hcryp->CrypOutCount >= (hcryp->Size / 4U)) && ((outcount * 4U) >= hcryp->Size))
5529 {
5530 /* Disable computation complete flag and errors interrupts */
5531 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
5532
5533 /* Change the CRYP state */
5534 hcryp->State = HAL_CRYP_STATE_READY;
5535
5536 /* Process unlocked */
5537 __HAL_UNLOCK(hcryp);
5538
5539 /* Call output transfer complete callback */
5540 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
5541 /*Call registered Output complete callback*/
5542 hcryp->OutCpltCallback(hcryp);
5543 #else
5544 /*Call legacy weak Output complete callback*/
5545 HAL_CRYP_OutCpltCallback(hcryp);
5546 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5547 }
5548
5549 else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
5550 {
5551 /* Write the input block in the IN FIFO */
5552 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5553 hcryp->CrypInCount++;
5554 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5555 hcryp->CrypInCount++;
5556 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5557 hcryp->CrypInCount++;
5558 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5559 hcryp->CrypInCount++;
5560 if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
5561 {
5562 /* Call Input transfer complete callback */
5563 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
5564 /*Call registered Input complete callback*/
5565 hcryp->InCpltCallback(hcryp);
5566 #else
5567 /*Call legacy weak Input complete callback*/
5568 HAL_CRYP_InCpltCallback(hcryp);
5569 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5570 }
5571 }
5572 else /* Last block of payload < 128bit*/
5573 {
5574 /* Workaround not implemented, Size should be %4 otherwise Tag will be incorrectly
5575 generated for GCM Encryption & CCM Decryption. Workaround is implemented in polling mode, so if last block of
5576 payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption & CCM Decryption. */
5577
5578 /* Compute the number of padding bytes in last block of payload */
5579 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
5580
5581 /* Number of valid words (lastwordsize) in last block */
5582 if ((npblb % 4U) == 0U)
5583 {
5584 lastwordsize = (16U - npblb) / 4U;
5585 }
5586 else
5587 {
5588 lastwordsize = ((16U - npblb) / 4U) + 1U;
5589 }
5590
5591 /* Last block optionally pad the data with zeros*/
5592 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
5593 {
5594 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5595 hcryp->CrypInCount++;
5596 }
5597 while (loopcounter < 4U)
5598 {
5599 /* pad the data with zeros to have a complete block */
5600 hcryp->Instance->DINR = 0x0U;
5601 loopcounter++;
5602 }
5603 }
5604 #endif /* AES */
5605
5606 }
5607
5608
5609 /**
5610 * @brief Sets the header phase in polling mode
5611 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
5612 * the configuration information for CRYP module(Header & HeaderSize)
5613 * @param Timeout: Timeout value
5614 * @retval state
5615 */
5616 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
5617 {
5618 uint32_t loopcounter;
5619 uint32_t size_in_bytes;
5620 uint32_t tmp;
5621 uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
5622 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
5623 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
5624
5625 /***************************** Header phase for GCM/GMAC or CCM *********************************/
5626
5627 if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
5628 {
5629 size_in_bytes = hcryp->Init.HeaderSize * 4U;
5630 }
5631 else
5632 {
5633 size_in_bytes = hcryp->Init.HeaderSize;
5634 }
5635
5636 if (size_in_bytes != 0U)
5637 {
5638
5639 #if defined(CRYP)
5640
5641 /* Select header phase */
5642 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5643
5644 /* Enable the CRYP peripheral */
5645 __HAL_CRYP_ENABLE(hcryp);
5646
5647 if ((size_in_bytes % 16U) == 0U)
5648 {
5649 /* HeaderSize %4, no padding */
5650 for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U)
5651 {
5652 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5653 hcryp->CrypHeaderCount++ ;
5654 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5655 hcryp->CrypHeaderCount++ ;
5656 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5657 hcryp->CrypHeaderCount++ ;
5658 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5659 hcryp->CrypHeaderCount++ ;
5660
5661 /* Wait for IFEM to be raised */
5662 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
5663 {
5664 /* Disable the CRYP peripheral clock */
5665 __HAL_CRYP_DISABLE(hcryp);
5666
5667 /* Change state */
5668 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5669 hcryp->State = HAL_CRYP_STATE_READY;
5670
5671 /* Process unlocked */
5672 __HAL_UNLOCK(hcryp);
5673 return HAL_ERROR;
5674 }
5675 }
5676 }
5677 else
5678 {
5679 /*Write header block in the IN FIFO without last block */
5680 for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 16U) * 4U)); loopcounter += 4U)
5681 {
5682 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5683 hcryp->CrypHeaderCount++ ;
5684 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5685 hcryp->CrypHeaderCount++ ;
5686 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5687 hcryp->CrypHeaderCount++ ;
5688 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5689 hcryp->CrypHeaderCount++ ;
5690
5691 /* Wait for IFEM to be raised */
5692 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
5693 {
5694 /* Disable the CRYP peripheral clock */
5695 __HAL_CRYP_DISABLE(hcryp);
5696
5697 /* Change state */
5698 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5699 hcryp->State = HAL_CRYP_STATE_READY;
5700
5701 /* Process unlocked */
5702 __HAL_UNLOCK(hcryp);
5703 return HAL_ERROR;
5704 }
5705 }
5706 /* Last block optionally pad the data with zeros*/
5707 for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 4U) % 4U)); loopcounter++)
5708 {
5709 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5710 hcryp->CrypHeaderCount++ ;
5711 }
5712 /* If the header size is a multiple of words */
5713 if ((size_in_bytes % 4U) == 0U)
5714 {
5715 /* Pad the data with zeros to have a complete block */
5716 while (loopcounter < 4U)
5717 {
5718 hcryp->Instance->DIN = 0x0U;
5719 loopcounter++;
5720 }
5721 }
5722 else
5723 {
5724 /* Enter last bytes, padded with zeroes */
5725 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5726 tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)];
5727 hcryp->Instance->DIN = tmp;
5728 loopcounter++;
5729 /* Pad the data with zeros to have a complete block */
5730 while (loopcounter < 4U)
5731 {
5732 hcryp->Instance->DIN = 0x0U;
5733 loopcounter++;
5734 }
5735 }
5736 /* Wait for CCF IFEM to be raised */
5737 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
5738 {
5739 /* Disable the CRYP peripheral clock */
5740 __HAL_CRYP_DISABLE(hcryp);
5741
5742 /* Change state */
5743 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5744 hcryp->State = HAL_CRYP_STATE_READY;
5745
5746 /* Process unlocked */
5747 __HAL_UNLOCK(hcryp);
5748 return HAL_ERROR;
5749 }
5750 }
5751 /* Wait until the complete message has been processed */
5752 if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
5753 {
5754 /* Disable the CRYP peripheral clock */
5755 __HAL_CRYP_DISABLE(hcryp);
5756
5757 /* Change state */
5758 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5759 hcryp->State = HAL_CRYP_STATE_READY;
5760
5761 /* Process unlocked & return error */
5762 __HAL_UNLOCK(hcryp);
5763 return HAL_ERROR;
5764 }
5765
5766 #else /* AES */
5767
5768 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
5769 {
5770 /* Workaround 1 :only AES before re-enabling the IP, datatype can be configured.*/
5771 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
5772
5773 /* Select header phase */
5774 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5775
5776 /* Enable the CRYP peripheral */
5777 __HAL_CRYP_ENABLE(hcryp);
5778
5779 }
5780 /* If size_in_bytes is a multiple of blocks (a multiple of four 32-bits words ) */
5781 if ((size_in_bytes % 16U) == 0U)
5782 {
5783 /* No padding */
5784 for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U)
5785 {
5786 /* Write the input block in the data input register */
5787 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5788 hcryp->CrypHeaderCount++ ;
5789 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5790 hcryp->CrypHeaderCount++ ;
5791 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5792 hcryp->CrypHeaderCount++ ;
5793 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5794 hcryp->CrypHeaderCount++ ;
5795
5796 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5797 {
5798 /* Disable the CRYP peripheral clock */
5799 __HAL_CRYP_DISABLE(hcryp);
5800
5801 /* Change state */
5802 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5803 hcryp->State = HAL_CRYP_STATE_READY;
5804
5805 /* Process unlocked */
5806 __HAL_UNLOCK(hcryp);
5807 return HAL_ERROR;
5808 }
5809 /* Clear CCF flag */
5810 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5811 }
5812 }
5813 else
5814 {
5815 /*Write header block in the IN FIFO without last block */
5816 for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 16U) * 4U)); loopcounter += 4U)
5817 {
5818 /* Write the input block in the data input register */
5819 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5820 hcryp->CrypHeaderCount++ ;
5821 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5822 hcryp->CrypHeaderCount++ ;
5823 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5824 hcryp->CrypHeaderCount++ ;
5825 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5826 hcryp->CrypHeaderCount++ ;
5827
5828 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5829 {
5830 /* Disable the CRYP peripheral clock */
5831 __HAL_CRYP_DISABLE(hcryp);
5832
5833 /* Change state */
5834 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5835 hcryp->State = HAL_CRYP_STATE_READY;
5836
5837 /* Process unlocked */
5838 __HAL_UNLOCK(hcryp);
5839 return HAL_ERROR;
5840 }
5841 /* Clear CCF flag */
5842 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5843 }
5844 /* Write last complete words */
5845 for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 4U) % 4U)); loopcounter++)
5846 {
5847 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5848 hcryp->CrypHeaderCount++ ;
5849 }
5850 /* If the header size is a multiple of words */
5851 if ((size_in_bytes % 4U) == 0U)
5852 {
5853 /* Pad the data with zeros to have a complete block */
5854 while (loopcounter < 4U)
5855 {
5856 hcryp->Instance->DINR = 0x0U;
5857 loopcounter++;
5858 }
5859 }
5860 else
5861 {
5862 /* Enter last bytes, padded with zeroes */
5863 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5864 tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)];
5865 hcryp->Instance->DINR = tmp;
5866 loopcounter++;
5867 /* Pad the data with zeros to have a complete block */
5868 while (loopcounter < 4U)
5869 {
5870 hcryp->Instance->DINR = 0x0U;
5871 loopcounter++;
5872 }
5873 }
5874
5875 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5876 {
5877 /* Disable the CRYP peripheral clock */
5878 __HAL_CRYP_DISABLE(hcryp);
5879
5880 /* Change state */
5881 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5882 hcryp->State = HAL_CRYP_STATE_READY;
5883
5884 /* Process unlocked */
5885 __HAL_UNLOCK(hcryp);
5886 return HAL_ERROR;
5887 }
5888 /* Clear CCF flag */
5889 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5890 }
5891 #endif /* End AES or CRYP */
5892 }
5893 else
5894 {
5895 #if defined(AES)
5896 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
5897 {
5898 /*Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
5899 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
5900
5901 /* Select header phase */
5902 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5903
5904 /* Enable the CRYP peripheral */
5905 __HAL_CRYP_ENABLE(hcryp);
5906 }
5907 #endif /* AES */
5908 }
5909 /* Return function status */
5910 return HAL_OK;
5911 }
5912
5913 /**
5914 * @brief Sets the header phase when using DMA in process
5915 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
5916 * the configuration information for CRYP module(Header & HeaderSize)
5917 * @retval None
5918 */
5919 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp)
5920 {
5921 __IO uint32_t count = 0U;
5922 uint32_t loopcounter;
5923 uint32_t headersize_in_bytes;
5924 uint32_t tmp;
5925 uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
5926 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
5927 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
5928
5929 /***************************** Header phase for GCM/GMAC or CCM *********************************/
5930 if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
5931 {
5932 headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
5933 }
5934 else
5935 {
5936 headersize_in_bytes = hcryp->Init.HeaderSize;
5937 }
5938
5939 if (headersize_in_bytes != 0U)
5940 {
5941
5942 #if defined(CRYP)
5943
5944 /* Select header phase */
5945 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5946
5947 /* Enable the CRYP peripheral */
5948 __HAL_CRYP_ENABLE(hcryp);
5949
5950 if ((headersize_in_bytes % 16U) == 0U)
5951 {
5952 /* HeaderSize %4, no padding */
5953 for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter += 4U)
5954 {
5955 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5956 hcryp->CrypHeaderCount++ ;
5957 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5958 hcryp->CrypHeaderCount++ ;
5959 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5960 hcryp->CrypHeaderCount++ ;
5961 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5962 hcryp->CrypHeaderCount++ ;
5963
5964 /* Wait for IFEM to be raised */
5965 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
5966 do
5967 {
5968 count-- ;
5969 if (count == 0U)
5970 {
5971 /* Disable the CRYP peripheral clock */
5972 __HAL_CRYP_DISABLE(hcryp);
5973
5974 /* Change state */
5975 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5976 hcryp->State = HAL_CRYP_STATE_READY;
5977
5978 /* Process unlocked */
5979 __HAL_UNLOCK(hcryp);
5980 return HAL_ERROR;
5981 }
5982 }
5983 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
5984 }
5985 }
5986 else
5987 {
5988 /*Write header block in the IN FIFO without last block */
5989 for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 16U) * 4U)); loopcounter += 4U)
5990 {
5991 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5992 hcryp->CrypHeaderCount++ ;
5993 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5994 hcryp->CrypHeaderCount++ ;
5995 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5996 hcryp->CrypHeaderCount++ ;
5997 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5998 hcryp->CrypHeaderCount++ ;
5999
6000 /* Wait for IFEM to be raised */
6001 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6002 do
6003 {
6004 count-- ;
6005 if (count == 0U)
6006 {
6007 /* Disable the CRYP peripheral clock */
6008 __HAL_CRYP_DISABLE(hcryp);
6009
6010 /* Change state */
6011 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6012 hcryp->State = HAL_CRYP_STATE_READY;
6013
6014 /* Process unlocked */
6015 __HAL_UNLOCK(hcryp);
6016 return HAL_ERROR;
6017 }
6018 }
6019 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
6020 }
6021 /* Last block optionally pad the data with zeros*/
6022 for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
6023 {
6024 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6025 hcryp->CrypHeaderCount++ ;
6026 }
6027 /* If the header size is a multiple of words */
6028 if ((headersize_in_bytes % 4U) == 0U)
6029 {
6030 /* Pad the data with zeros to have a complete block */
6031 while (loopcounter < 4U)
6032 {
6033 hcryp->Instance->DIN = 0x0U;
6034 loopcounter++;
6035 }
6036 }
6037 else
6038 {
6039 /* Enter last bytes, padded with zeroes */
6040 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6041 tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
6042 hcryp->Instance->DIN = tmp;
6043 loopcounter++;
6044 /* Pad the data with zeros to have a complete block */
6045 while (loopcounter < 4U)
6046 {
6047 hcryp->Instance->DIN = 0x0U;
6048 loopcounter++;
6049 }
6050 }
6051 /* Wait for IFEM to be raised */
6052 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6053 do
6054 {
6055 count-- ;
6056 if (count == 0U)
6057 {
6058 /* Disable the CRYP peripheral clock */
6059 __HAL_CRYP_DISABLE(hcryp);
6060
6061 /* Change state */
6062 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6063 hcryp->State = HAL_CRYP_STATE_READY;
6064
6065 /* Process unlocked */
6066 __HAL_UNLOCK(hcryp);
6067 return HAL_ERROR;
6068 }
6069 }
6070 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
6071 }
6072 /* Wait until the complete message has been processed */
6073 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6074 do
6075 {
6076 count-- ;
6077 if (count == 0U)
6078 {
6079 /* Disable the CRYP peripheral clock */
6080 __HAL_CRYP_DISABLE(hcryp);
6081
6082 /* Change state */
6083 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6084 hcryp->State = HAL_CRYP_STATE_READY;
6085
6086 /* Process unlocked */
6087 __HAL_UNLOCK(hcryp);
6088 return HAL_ERROR;
6089 }
6090 }
6091 while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
6092
6093 #else /* AES */
6094
6095 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
6096 {
6097 /* Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
6098 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
6099
6100 /* Select header phase */
6101 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
6102
6103 /* Enable the CRYP peripheral */
6104 __HAL_CRYP_ENABLE(hcryp);
6105 }
6106 if ((headersize_in_bytes % 16U) == 0U)
6107 {
6108 /* HeaderSize %4, no padding */
6109 for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter += 4U)
6110 {
6111 /* Write the input block in the data input register */
6112 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6113 hcryp->CrypHeaderCount++ ;
6114 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6115 hcryp->CrypHeaderCount++ ;
6116 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6117 hcryp->CrypHeaderCount++ ;
6118 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6119 hcryp->CrypHeaderCount++ ;
6120
6121 /*Wait on CCF flag*/
6122 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6123 do
6124 {
6125 count-- ;
6126 if (count == 0U)
6127 {
6128 /* Disable the CRYP peripheral clock */
6129 __HAL_CRYP_DISABLE(hcryp);
6130
6131 /* Change state */
6132 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6133 hcryp->State = HAL_CRYP_STATE_READY;
6134
6135 /* Process unlocked */
6136 __HAL_UNLOCK(hcryp);
6137 return HAL_ERROR;
6138 }
6139 }
6140 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
6141
6142 /* Clear CCF flag */
6143 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6144 }
6145 }
6146 else
6147 {
6148 /*Write header block in the IN FIFO without last block */
6149 for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 16U) * 4U)); loopcounter += 4U)
6150 {
6151 /* Write the Input block in the Data Input register */
6152 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6153 hcryp->CrypHeaderCount++ ;
6154 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6155 hcryp->CrypHeaderCount++ ;
6156 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6157 hcryp->CrypHeaderCount++ ;
6158 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6159 hcryp->CrypHeaderCount++ ;
6160
6161 /*Wait on CCF flag*/
6162 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6163 do
6164 {
6165 count-- ;
6166 if (count == 0U)
6167 {
6168 /* Disable the CRYP peripheral clock */
6169 __HAL_CRYP_DISABLE(hcryp);
6170
6171 /* Change state */
6172 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6173 hcryp->State = HAL_CRYP_STATE_READY;
6174
6175 /* Process unlocked */
6176 __HAL_UNLOCK(hcryp);
6177 return HAL_ERROR;
6178 }
6179 }
6180 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
6181
6182 /* Clear CCF flag */
6183 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6184 }
6185 /* Last block optionally pad the data with zeros*/
6186 for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
6187 {
6188 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6189 hcryp->CrypHeaderCount++ ;
6190 }
6191 /* If the header size is a multiple of words */
6192 if ((headersize_in_bytes % 4U) == 0U)
6193 {
6194 /* Pad the data with zeros to have a complete block */
6195 while (loopcounter < 4U)
6196 {
6197 hcryp->Instance->DINR = 0x0U;
6198 loopcounter++;
6199 }
6200 }
6201 else
6202 {
6203 /* Enter last bytes, padded with zeroes */
6204 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6205 tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
6206 hcryp->Instance->DINR = tmp;
6207 loopcounter++;
6208 /* Pad the data with zeros to have a complete block */
6209 while (loopcounter < 4U)
6210 {
6211 hcryp->Instance->DINR = 0x0U;
6212 loopcounter++;
6213 }
6214 }
6215 /*Wait on CCF flag*/
6216 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6217 do
6218 {
6219 count-- ;
6220 if (count == 0U)
6221 {
6222 /* Disable the CRYP peripheral clock */
6223 __HAL_CRYP_DISABLE(hcryp);
6224
6225 /* Change state */
6226 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6227 hcryp->State = HAL_CRYP_STATE_READY;
6228
6229 /* Process unlocked */
6230 __HAL_UNLOCK(hcryp);
6231 return HAL_ERROR;
6232 }
6233 }
6234 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
6235
6236 /* Clear CCF flag */
6237 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6238 }
6239 #endif /* End AES or CRYP */
6240 }
6241 else
6242 {
6243 #if defined(AES)
6244 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
6245 {
6246 /*Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
6247 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
6248
6249 /* Select header phase */
6250 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
6251
6252 /* Enable the CRYP peripheral */
6253 __HAL_CRYP_ENABLE(hcryp);
6254 }
6255 #endif /* AES */
6256 }
6257 /* Return function status */
6258 return HAL_OK;
6259 }
6260
6261 /**
6262 * @brief Sets the header phase in interrupt mode
6263 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
6264 * the configuration information for CRYP module(Header & HeaderSize)
6265 * @retval None
6266 */
6267 static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
6268 {
6269 uint32_t loopcounter;
6270 #if defined(AES)
6271 uint32_t lastwordsize;
6272 uint32_t npblb;
6273 #endif
6274 uint32_t headersize_in_bytes;
6275 uint32_t tmp;
6276 uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
6277 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
6278 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
6279
6280 if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
6281 {
6282 headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
6283 }
6284 else
6285 {
6286 headersize_in_bytes = hcryp->Init.HeaderSize;
6287 }
6288
6289 /***************************** Header phase *********************************/
6290
6291 #if defined(CRYP)
6292 if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U))
6293 {
6294 /* Disable interrupts */
6295 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
6296
6297 /* Disable the CRYP peripheral */
6298 __HAL_CRYP_DISABLE(hcryp);
6299
6300 /* Set the phase */
6301 hcryp->Phase = CRYP_PHASE_PROCESS;
6302
6303 /* Select payload phase once the header phase is performed */
6304 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
6305
6306 /* Enable Interrupts */
6307 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
6308
6309 /* Enable the CRYP peripheral */
6310 __HAL_CRYP_ENABLE(hcryp);
6311 }
6312 else if (((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U)
6313
6314 {
6315 /* HeaderSize %4, no padding */
6316 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6317 hcryp->CrypHeaderCount++ ;
6318 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6319 hcryp->CrypHeaderCount++ ;
6320 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6321 hcryp->CrypHeaderCount++ ;
6322 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6323 hcryp->CrypHeaderCount++ ;
6324 }
6325 else
6326 {
6327 /* Last block optionally pad the data with zeros*/
6328 for (loopcounter = 0U; loopcounter < ((headersize_in_bytes / 4U) % 4U); loopcounter++)
6329 {
6330 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6331 hcryp->CrypHeaderCount++ ;
6332 }
6333 if ((headersize_in_bytes % 4U) == 0U)
6334 {
6335 /* Pad the data with zeros to have a complete block */
6336 while (loopcounter < 4U)
6337 {
6338 hcryp->Instance->DIN = 0x0U;
6339 loopcounter++;
6340 hcryp->CrypHeaderCount++;
6341 }
6342 }
6343 else
6344 {
6345 /* Enter last bytes, padded with zeros */
6346 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6347 tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
6348 hcryp->Instance->DIN = tmp;
6349 loopcounter++;
6350 hcryp->CrypHeaderCount++;
6351 /* Pad the data with zeros to have a complete block */
6352 while (loopcounter < 4U)
6353 {
6354 hcryp->Instance->DIN = 0x0U;
6355 loopcounter++;
6356 hcryp->CrypHeaderCount++;
6357 }
6358 }
6359 }
6360 #else /* AES */
6361
6362 if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U))
6363 {
6364 /* Set the phase */
6365 hcryp->Phase = CRYP_PHASE_PROCESS;
6366
6367 /* Payload phase not supported in CCM AES2 */
6368 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
6369 {
6370 /* Select payload phase once the header phase is performed */
6371 MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
6372 }
6373 if (hcryp->Init.Algorithm == CRYP_AES_CCM)
6374 {
6375 /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */
6376 hcryp->CrypHeaderCount++;
6377 }
6378 /* Write the payload Input block in the IN FIFO */
6379 if (hcryp->Size == 0U)
6380 {
6381 /* Disable interrupts */
6382 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
6383
6384 /* Change the CRYP state */
6385 hcryp->State = HAL_CRYP_STATE_READY;
6386
6387 /* Process unlocked */
6388 __HAL_UNLOCK(hcryp);
6389 }
6390 else if (hcryp->Size >= 16U)
6391 {
6392 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6393 hcryp->CrypInCount++;
6394 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6395 hcryp->CrypInCount++;
6396 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6397 hcryp->CrypInCount++;
6398 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6399 hcryp->CrypInCount++;
6400
6401 if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
6402 {
6403 /* Call the input data transfer complete callback */
6404 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
6405 /*Call registered Input complete callback*/
6406 hcryp->InCpltCallback(hcryp);
6407 #else
6408 /*Call legacy weak Input complete callback*/
6409 HAL_CRYP_InCpltCallback(hcryp);
6410 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6411 }
6412 }
6413 else /* Size < 4 words : first block is the last block*/
6414 {
6415 /* Workaround not implemented, Size should be %4 otherwise Tag will be incorrectly
6416 generated for GCM Encryption. Workaround is implemented in polling mode, so if last block of
6417 payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
6418
6419 /* Compute the number of padding bytes in last block of payload */
6420 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
6421
6422 /* Number of valid words (lastwordsize) in last block */
6423 if ((npblb % 4U) == 0U)
6424 {
6425 lastwordsize = (16U - npblb) / 4U;
6426 }
6427 else
6428 {
6429 lastwordsize = ((16U - npblb) / 4U) + 1U;
6430 }
6431
6432 /* Last block optionally pad the data with zeros*/
6433 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
6434 {
6435 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6436 hcryp->CrypInCount++;
6437 }
6438 while (loopcounter < 4U)
6439 {
6440 /* Pad the data with zeros to have a complete block */
6441 hcryp->Instance->DINR = 0x0U;
6442 loopcounter++;
6443 }
6444 }
6445 }
6446 else if (((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U)
6447 {
6448 /* Write the input block in the IN FIFO */
6449 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6450 hcryp->CrypHeaderCount++;
6451 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6452 hcryp->CrypHeaderCount++;
6453 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6454 hcryp->CrypHeaderCount++;
6455 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6456 hcryp->CrypHeaderCount++;
6457 }
6458 else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/
6459 {
6460 /* Last block optionally pad the data with zeros*/
6461 for (loopcounter = 0U; loopcounter < ((headersize_in_bytes / 4U) % 4U); loopcounter++)
6462 {
6463 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6464 hcryp->CrypHeaderCount++ ;
6465 }
6466 /* If the header size is a multiple of words */
6467 if ((headersize_in_bytes % 4U) == 0U)
6468 {
6469 /* Pad the data with zeros to have a complete block */
6470 while (loopcounter < 4U)
6471 {
6472 hcryp->Instance->DINR = 0x0U;
6473 loopcounter++;
6474 hcryp->CrypHeaderCount++;
6475 }
6476 }
6477 else
6478 {
6479 /* Enter last bytes, padded with zeros */
6480 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6481 tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
6482 hcryp->Instance->DINR = tmp;
6483 loopcounter++;
6484 hcryp->CrypHeaderCount++;
6485 /* Pad the data with zeros to have a complete block */
6486 while (loopcounter < 4U)
6487 {
6488 hcryp->Instance->DINR = 0x0U;
6489 loopcounter++;
6490 hcryp->CrypHeaderCount++;
6491 }
6492 }
6493 }
6494 #endif /* End AES or CRYP */
6495 }
6496
6497
6498 /**
6499 * @brief Workaround used for GCM/CCM mode.
6500 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
6501 * the configuration information for CRYP module
6502 * @param Timeout: specify Timeout value
6503 * @retval None
6504 */
6505 static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
6506 {
6507 uint32_t lastwordsize;
6508 uint32_t npblb;
6509 #if defined(CRYP)
6510 uint32_t iv1temp;
6511 uint32_t temp[4] = {0};
6512 uint32_t temp2[4] = {0};
6513 #endif /* CRYP */
6514 uint32_t intermediate_data[4] = {0};
6515 uint32_t index;
6516
6517 /* Compute the number of padding bytes in last block of payload */
6518 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
6519
6520 /* Number of valid words (lastwordsize) in last block */
6521 if ((npblb % 4U) == 0U)
6522 {
6523 lastwordsize = (16U - npblb) / 4U;
6524 }
6525 else
6526 {
6527 lastwordsize = ((16U - npblb) / 4U) + 1U;
6528 }
6529
6530 #if defined(CRYP)
6531
6532 /* Workaround 2, case GCM encryption */
6533 if (hcryp->Init.Algorithm == CRYP_AES_GCM)
6534 {
6535 if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
6536 {
6537 /*Workaround in order to properly compute authentication tags while doing
6538 a GCM encryption with the last block of payload size inferior to 128 bits*/
6539 /* Disable CRYP to start the final phase */
6540 __HAL_CRYP_DISABLE(hcryp);
6541
6542 /*Update CRYP_IV1R register and ALGOMODE*/
6543 hcryp->Instance->IV1RR = ((hcryp->Instance->CSGCMCCM7R) - 1U);
6544 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
6545
6546 /* Enable CRYP to start the final phase */
6547 __HAL_CRYP_ENABLE(hcryp);
6548 }
6549 /* Last block optionally pad the data with zeros*/
6550 for (index = 0; index < lastwordsize; index ++)
6551 {
6552 /* Write the last input block in the IN FIFO */
6553 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6554 hcryp->CrypInCount++;
6555 }
6556 while (index < 4U)
6557 {
6558 /* Pad the data with zeros to have a complete block */
6559 hcryp->Instance->DIN = 0U;
6560 index++;
6561 }
6562 /* Wait for OFNE flag to be raised */
6563 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
6564 {
6565 /* Disable the CRYP peripheral clock */
6566 __HAL_CRYP_DISABLE(hcryp);
6567
6568 /* Change state */
6569 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6570 hcryp->State = HAL_CRYP_STATE_READY;
6571
6572 /* Process Unlocked */
6573 __HAL_UNLOCK(hcryp);
6574 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
6575 /*Call registered error callback*/
6576 hcryp->ErrorCallback(hcryp);
6577 #else
6578 /*Call legacy weak error callback*/
6579 HAL_CRYP_ErrorCallback(hcryp);
6580 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6581 }
6582 if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
6583 {
6584 for (index = 0U; index < 4U; index++)
6585 {
6586 /* Read the output block from the output FIFO */
6587 intermediate_data[index] = hcryp->Instance->DOUT;
6588
6589 /* Intermediate data buffer to be used in for the workaround*/
6590 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index];
6591 hcryp->CrypOutCount++;
6592 }
6593 }
6594
6595 if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
6596 {
6597 /*workaround in order to properly compute authentication tags while doing
6598 a GCM encryption with the last block of payload size inferior to 128 bits*/
6599 /* Change the AES mode to GCM mode and Select Final phase */
6600 /* configured CHMOD GCM */
6601 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_GCM);
6602
6603 /* configured final phase */
6604 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
6605
6606 if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_32B)
6607 {
6608 if ((npblb % 4U) == 1U)
6609 {
6610 intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U;
6611 }
6612 if ((npblb % 4U) == 2U)
6613 {
6614 intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U;
6615 }
6616 if ((npblb % 4U) == 3U)
6617 {
6618 intermediate_data[lastwordsize - 1U] &= 0xFF000000U;
6619 }
6620 }
6621 else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_8B)
6622 {
6623 if ((npblb % 4U) == 1U)
6624 {
6625 intermediate_data[lastwordsize - 1U] &= __REV(0xFFFFFF00U);
6626 }
6627 if ((npblb % 4U) == 2U)
6628 {
6629 intermediate_data[lastwordsize - 1U] &= __REV(0xFFFF0000U);
6630 }
6631 if ((npblb % 4U) == 3U)
6632 {
6633 intermediate_data[lastwordsize - 1U] &= __REV(0xFF000000U);
6634 }
6635 }
6636 else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_16B)
6637 {
6638 if ((npblb % 4U) == 1U)
6639 {
6640 intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFFFF00U), 16);
6641 }
6642 if ((npblb % 4U) == 2U)
6643 {
6644 intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFF0000U), 16);
6645 }
6646 if ((npblb % 4U) == 3U)
6647 {
6648 intermediate_data[lastwordsize - 1U] &= __ROR((0xFF000000U), 16);
6649 }
6650 }
6651 else /*CRYP_DATATYPE_1B*/
6652 {
6653 if ((npblb % 4U) == 1U)
6654 {
6655 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFFFF00U);
6656 }
6657 if ((npblb % 4U) == 2U)
6658 {
6659 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFF0000U);
6660 }
6661 if ((npblb % 4U) == 3U)
6662 {
6663 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFF000000U);
6664 }
6665 }
6666 for (index = 0U; index < lastwordsize; index ++)
6667 {
6668 /*Write the intermediate_data in the IN FIFO */
6669 hcryp->Instance->DIN = intermediate_data[index];
6670 }
6671 while (index < 4U)
6672 {
6673 /* Pad the data with zeros to have a complete block */
6674 hcryp->Instance->DIN = 0x0U;
6675 index++;
6676 }
6677 /* Wait for OFNE flag to be raised */
6678 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
6679 {
6680 /* Disable the CRYP peripheral clock */
6681 __HAL_CRYP_DISABLE(hcryp);
6682
6683 /* Change state */
6684 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6685 hcryp->State = HAL_CRYP_STATE_READY;
6686
6687 /* Process unlocked */
6688 __HAL_UNLOCK(hcryp);
6689 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
6690 /*Call registered error callback*/
6691 hcryp->ErrorCallback(hcryp);
6692 #else
6693 /*Call legacy weak error callback*/
6694 HAL_CRYP_ErrorCallback(hcryp);
6695 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6696 }
6697
6698 if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
6699 {
6700 for (index = 0U; index < 4U; index++)
6701 {
6702 intermediate_data[index] = hcryp->Instance->DOUT;
6703 }
6704 }
6705 }
6706 } /* End of GCM encryption */
6707 else
6708 {
6709 /* Workaround 2, case CCM decryption, in order to properly compute
6710 authentication tags while doing a CCM decryption with the last block
6711 of payload size inferior to 128 bits*/
6712
6713 if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
6714 {
6715 iv1temp = hcryp->Instance->CSGCMCCM7R;
6716
6717 /* Disable CRYP to start the final phase */
6718 __HAL_CRYP_DISABLE(hcryp);
6719
6720 temp[0] = hcryp->Instance->CSGCMCCM0R;
6721 temp[1] = hcryp->Instance->CSGCMCCM1R;
6722 temp[2] = hcryp->Instance->CSGCMCCM2R;
6723 temp[3] = hcryp->Instance->CSGCMCCM3R;
6724
6725 hcryp->Instance->IV1RR = iv1temp;
6726
6727 /* Configured CHMOD CTR */
6728 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
6729
6730 /* Enable CRYP to start the final phase */
6731 __HAL_CRYP_ENABLE(hcryp);
6732 }
6733 /* Last block optionally pad the data with zeros*/
6734 for (index = 0; index < lastwordsize; index ++)
6735 {
6736 /* Write the last Input block in the IN FIFO */
6737 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6738 hcryp->CrypInCount++;
6739 }
6740 while (index < 4U)
6741 {
6742 /* Pad the data with zeros to have a complete block */
6743 hcryp->Instance->DIN = 0U;
6744 index++;
6745 }
6746 /* Wait for OFNE flag to be raised */
6747 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
6748 {
6749 /* Disable the CRYP peripheral clock */
6750 __HAL_CRYP_DISABLE(hcryp);
6751
6752 /* Change state */
6753 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6754 hcryp->State = HAL_CRYP_STATE_READY;
6755
6756 /* Process Unlocked */
6757 __HAL_UNLOCK(hcryp);
6758 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6759 /*Call registered error callback*/
6760 hcryp->ErrorCallback(hcryp);
6761 #else
6762 /*Call legacy weak error callback*/
6763 HAL_CRYP_ErrorCallback(hcryp);
6764 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6765 }
6766
6767 if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
6768 {
6769 for (index = 0U; index < 4U; index++)
6770 {
6771 /* Read the Output block from the Output FIFO */
6772 intermediate_data[index] = hcryp->Instance->DOUT;
6773
6774 /*intermediate data buffer to be used in for the workaround*/
6775 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index];
6776 hcryp->CrypOutCount++;
6777 }
6778 }
6779
6780 if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
6781 {
6782 temp2[0] = hcryp->Instance->CSGCMCCM0R;
6783 temp2[1] = hcryp->Instance->CSGCMCCM1R;
6784 temp2[2] = hcryp->Instance->CSGCMCCM2R;
6785 temp2[3] = hcryp->Instance->CSGCMCCM3R;
6786
6787 /* configured CHMOD CCM */
6788 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CCM);
6789
6790 /* configured Header phase */
6791 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_HEADER);
6792
6793 /*set to zero the bits corresponding to the padded bits*/
6794 for (index = lastwordsize; index < 4U; index ++)
6795 {
6796 intermediate_data[index] = 0U;
6797 }
6798 if ((npblb % 4U) == 1U)
6799 {
6800 intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U;
6801 }
6802 if ((npblb % 4U) == 2U)
6803 {
6804 intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U;
6805 }
6806 if ((npblb % 4U) == 3U)
6807 {
6808 intermediate_data[lastwordsize - 1U] &= 0xFF000000U;
6809 }
6810 for (index = 0U; index < 4U ; index ++)
6811 {
6812 intermediate_data[index] ^= temp[index];
6813 intermediate_data[index] ^= temp2[index];
6814 }
6815 for (index = 0U; index < 4U; index ++)
6816 {
6817 /* Write the last Input block in the IN FIFO */
6818 hcryp->Instance->DIN = intermediate_data[index] ;
6819 }
6820
6821 /* Wait for BUSY flag to be raised */
6822 if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
6823 {
6824 /* Disable the CRYP peripheral clock */
6825 __HAL_CRYP_DISABLE(hcryp);
6826
6827 /* Change state */
6828 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6829 hcryp->State = HAL_CRYP_STATE_READY;
6830
6831 /* Process Unlocked */
6832 __HAL_UNLOCK(hcryp);
6833 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6834 /*Call registered error callback*/
6835 hcryp->ErrorCallback(hcryp);
6836 #else
6837 /*Call legacy weak error callback*/
6838 HAL_CRYP_ErrorCallback(hcryp);
6839 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6840 }
6841 }
6842 } /* End of CCM WKA*/
6843
6844 /* Process Unlocked */
6845 __HAL_UNLOCK(hcryp);
6846
6847 #else /* AES */
6848
6849 /*Workaround 2: case GCM encryption, during payload phase and before inserting
6850 the last block of paylaod, which size is inferior to 128 bits */
6851
6852 if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
6853 {
6854 /* configured CHMOD CTR */
6855 MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_CTR);
6856 }
6857 /* last block optionally pad the data with zeros*/
6858 for (index = 0U; index < lastwordsize; index ++)
6859 {
6860 /* Write the last Input block in the IN FIFO */
6861 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6862 hcryp->CrypInCount++;
6863 }
6864 while (index < 4U)
6865 {
6866 /* pad the data with zeros to have a complete block */
6867 hcryp->Instance->DINR = 0U;
6868 index++;
6869 }
6870 /* Wait for CCF flag to be raised */
6871 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
6872 {
6873 hcryp->State = HAL_CRYP_STATE_READY;
6874 __HAL_UNLOCK(hcryp);
6875 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6876 /*Call registered error callback*/
6877 hcryp->ErrorCallback(hcryp);
6878 #else
6879 /*Call legacy weak error callback*/
6880 HAL_CRYP_ErrorCallback(hcryp);
6881 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6882 }
6883
6884 /* Clear CCF Flag */
6885 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6886
6887 for (index = 0U; index < 4U; index++)
6888 {
6889 /* Read the Output block from the Output FIFO */
6890 intermediate_data[index] = hcryp->Instance->DOUTR;
6891
6892 /*intermediate data buffer to be used in the workaround*/
6893 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index];
6894 hcryp->CrypOutCount++;
6895 }
6896
6897 if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
6898 {
6899 /* configured CHMOD GCM */
6900 MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_GCM_GMAC);
6901
6902 /* Select final phase */
6903 MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
6904
6905 if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_32B)
6906 {
6907 if ((npblb % 4U) == 1U)
6908 {
6909 intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U;
6910 }
6911 if ((npblb % 4U) == 2U)
6912 {
6913 intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U;
6914 }
6915 if ((npblb % 4U) == 3U)
6916 {
6917 intermediate_data[lastwordsize - 1U] &= 0xFF000000U;
6918 }
6919 }
6920 else if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_8B)
6921 {
6922 if ((npblb % 4U) == 1U)
6923 {
6924 intermediate_data[lastwordsize - 1U] &= __REV(0xFFFFFF00U);
6925 }
6926 if ((npblb % 4U) == 2U)
6927 {
6928 intermediate_data[lastwordsize - 1U] &= __REV(0xFFFF0000U);
6929 }
6930 if ((npblb % 4U) == 3U)
6931 {
6932 intermediate_data[lastwordsize - 1U] &= __REV(0xFF000000U);
6933 }
6934 }
6935 else if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_16B)
6936 {
6937 if ((npblb % 4U) == 1U)
6938 {
6939 intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFFFF00U), 16);
6940 }
6941 if ((npblb % 4U) == 2U)
6942 {
6943 intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFF0000U), 16);
6944 }
6945 if ((npblb % 4U) == 3U)
6946 {
6947 intermediate_data[lastwordsize - 1U] &= __ROR((0xFF000000U), 16);
6948 }
6949 }
6950 else /*CRYP_DATATYPE_1B*/
6951 {
6952 if ((npblb % 4U) == 1U)
6953 {
6954 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFFFF00U);
6955 }
6956 if ((npblb % 4U) == 2U)
6957 {
6958 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFF0000U);
6959 }
6960 if ((npblb % 4U) == 3U)
6961 {
6962 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFF000000U);
6963 }
6964 }
6965
6966 /*Write the intermediate_data in the IN FIFO */
6967 for (index = 0U; index < lastwordsize; index ++)
6968 {
6969 hcryp->Instance->DINR = intermediate_data[index];
6970 }
6971 while (index < 4U)
6972 {
6973 /* pad the data with zeros to have a complete block */
6974 hcryp->Instance->DINR = 0U;
6975 index++;
6976 }
6977 /* Wait for CCF flag to be raised */
6978 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
6979 {
6980 /* Disable the CRYP peripheral clock */
6981 __HAL_CRYP_DISABLE(hcryp);
6982
6983 /* Change state */
6984 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6985 hcryp->State = HAL_CRYP_STATE_READY;
6986
6987 /* Process Unlocked */
6988 __HAL_UNLOCK(hcryp);
6989 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6990 /*Call registered error callback*/
6991 hcryp->ErrorCallback(hcryp);
6992 #else
6993 /*Call legacy weak error callback*/
6994 HAL_CRYP_ErrorCallback(hcryp);
6995 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6996 }
6997 /* Clear CCF Flag */
6998 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6999
7000 for (index = 0U; index < 4U; index++)
7001 {
7002 intermediate_data[index] = hcryp->Instance->DOUTR;
7003 }
7004 }/*End of Workaround 2*/
7005 #endif /* End AES or CRYP */
7006 }
7007
7008 #if defined (CRYP)
7009
7010 /**
7011 * @brief Handle CRYP hardware block Timeout when waiting for IFEM flag to be raised.
7012 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
7013 * the configuration information for CRYP module.
7014 * @param Timeout: Timeout duration.
7015 * @retval HAL status
7016 */
7017 static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
7018 {
7019 uint32_t tickstart;
7020
7021 /* Get timeout */
7022 tickstart = HAL_GetTick();
7023
7024 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
7025 {
7026 /* Check for the Timeout */
7027 if (Timeout != HAL_MAX_DELAY)
7028 {
7029 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7030 {
7031 return HAL_ERROR;
7032 }
7033 }
7034 }
7035 return HAL_OK;
7036 }
7037
7038 /**
7039 * @brief Handle CRYP hardware block Timeout when waiting for BUSY flag to be raised.
7040 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
7041 * the configuration information for CRYP module.
7042 * @param Timeout: Timeout duration.
7043 * @retval HAL status
7044 */
7045 static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
7046 {
7047 uint32_t tickstart;
7048
7049 /* Get timeout */
7050 tickstart = HAL_GetTick();
7051
7052 while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
7053 {
7054 /* Check for the Timeout */
7055 if (Timeout != HAL_MAX_DELAY)
7056 {
7057 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7058 {
7059 return HAL_ERROR;
7060 }
7061 }
7062 }
7063 return HAL_OK;
7064 }
7065
7066
7067 /**
7068 * @brief Handle CRYP hardware block Timeout when waiting for OFNE flag to be raised.
7069 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
7070 * the configuration information for CRYP module.
7071 * @param Timeout: Timeout duration.
7072 * @retval HAL status
7073 */
7074 static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
7075 {
7076 uint32_t tickstart;
7077
7078 /* Get timeout */
7079 tickstart = HAL_GetTick();
7080
7081 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
7082 {
7083 /* Check for the Timeout */
7084 if (Timeout != HAL_MAX_DELAY)
7085 {
7086 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7087 {
7088 return HAL_ERROR;
7089 }
7090 }
7091 }
7092 return HAL_OK;
7093 }
7094
7095 #else /* AES */
7096
7097 /**
7098 * @brief Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.
7099 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
7100 * the configuration information for CRYP module.
7101 * @param Timeout: Timeout duration.
7102 * @retval HAL status
7103 */
7104 static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
7105 {
7106 uint32_t tickstart;
7107
7108 /* Get timeout */
7109 tickstart = HAL_GetTick();
7110
7111 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
7112 {
7113 /* Check for the Timeout */
7114 if (Timeout != HAL_MAX_DELAY)
7115 {
7116 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7117 {
7118 return HAL_ERROR;
7119 }
7120 }
7121 }
7122 return HAL_OK;
7123 }
7124
7125 #endif /* End AES or CRYP */
7126
7127
7128 /**
7129 * @}
7130 */
7131
7132
7133
7134 /**
7135 * @}
7136 */
7137
7138 /**
7139 * @}
7140 */
7141
7142 #endif /* HAL_CRYP_MODULE_ENABLED */
7143
7144
7145 /**
7146 * @}
7147 */
7148 #endif /* TinyAES or CRYP*/
7149 /**
7150 * @}
7151 */
7152
7153
