1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_usart.c
4 * @author MCD Application Team
5 * @brief USART LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f4xx_ll_usart.h"
23 #include "stm32f4xx_ll_rcc.h"
24 #include "stm32f4xx_ll_bus.h"
25 #ifdef USE_FULL_ASSERT
26 #include "stm32_assert.h"
27 #else
28 #define assert_param(expr) ((void)0U)
29 #endif
30
31 /** @addtogroup STM32F4xx_LL_Driver
32 * @{
33 */
34
35 #if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (UART10)
36
37 /** @addtogroup USART_LL
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /** @addtogroup USART_LL_Private_Constants
45 * @{
46 */
47
48 /**
49 * @}
50 */
51
52
53 /* Private macros ------------------------------------------------------------*/
54 /** @addtogroup USART_LL_Private_Macros
55 * @{
56 */
57
58 /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
59 * divided by the smallest oversampling used on the USART (i.e. 8) */
60 #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 12500000U)
61
62 /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
63 #define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
64
65 #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
66 || ((__VALUE__) == LL_USART_DIRECTION_RX) \
67 || ((__VALUE__) == LL_USART_DIRECTION_TX) \
68 || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
69
70 #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
71 || ((__VALUE__) == LL_USART_PARITY_EVEN) \
72 || ((__VALUE__) == LL_USART_PARITY_ODD))
73
74 #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
75 || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
76
77 #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
78 || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
79
80 #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
81 || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
82
83 #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
84 || ((__VALUE__) == LL_USART_PHASE_2EDGE))
85
86 #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
87 || ((__VALUE__) == LL_USART_POLARITY_HIGH))
88
89 #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
90 || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
91
92 #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
93 || ((__VALUE__) == LL_USART_STOPBITS_1) \
94 || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
95 || ((__VALUE__) == LL_USART_STOPBITS_2))
96
97 #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
98 || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
99 || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
100 || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
101
102 /**
103 * @}
104 */
105
106 /* Private function prototypes -----------------------------------------------*/
107
108 /* Exported functions --------------------------------------------------------*/
109 /** @addtogroup USART_LL_Exported_Functions
110 * @{
111 */
112
113 /** @addtogroup USART_LL_EF_Init
114 * @{
115 */
116
117 /**
118 * @brief De-initialize USART registers (Registers restored to their default values).
119 * @param USARTx USART Instance
120 * @retval An ErrorStatus enumeration value:
121 * - SUCCESS: USART registers are de-initialized
122 * - ERROR: USART registers are not de-initialized
123 */
LL_USART_DeInit(USART_TypeDef * USARTx)124 ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
125 {
126 ErrorStatus status = SUCCESS;
127
128 /* Check the parameters */
129 assert_param(IS_UART_INSTANCE(USARTx));
130
131 if (USARTx == USART1)
132 {
133 /* Force reset of USART clock */
134 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
135
136 /* Release reset of USART clock */
137 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
138 }
139 else if (USARTx == USART2)
140 {
141 /* Force reset of USART clock */
142 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
143
144 /* Release reset of USART clock */
145 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
146 }
147 #if defined(USART3)
148 else if (USARTx == USART3)
149 {
150 /* Force reset of USART clock */
151 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
152
153 /* Release reset of USART clock */
154 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
155 }
156 #endif /* USART3 */
157 #if defined(USART6)
158 else if (USARTx == USART6)
159 {
160 /* Force reset of USART clock */
161 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART6);
162
163 /* Release reset of USART clock */
164 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART6);
165 }
166 #endif /* USART6 */
167 #if defined(UART4)
168 else if (USARTx == UART4)
169 {
170 /* Force reset of UART clock */
171 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
172
173 /* Release reset of UART clock */
174 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
175 }
176 #endif /* UART4 */
177 #if defined(UART5)
178 else if (USARTx == UART5)
179 {
180 /* Force reset of UART clock */
181 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
182
183 /* Release reset of UART clock */
184 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
185 }
186 #endif /* UART5 */
187 #if defined(UART7)
188 else if (USARTx == UART7)
189 {
190 /* Force reset of UART clock */
191 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART7);
192
193 /* Release reset of UART clock */
194 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART7);
195 }
196 #endif /* UART7 */
197 #if defined(UART8)
198 else if (USARTx == UART8)
199 {
200 /* Force reset of UART clock */
201 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART8);
202
203 /* Release reset of UART clock */
204 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART8);
205 }
206 #endif /* UART8 */
207 #if defined(UART9)
208 else if (USARTx == UART9)
209 {
210 /* Force reset of UART clock */
211 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_UART9);
212
213 /* Release reset of UART clock */
214 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_UART9);
215 }
216 #endif /* UART9 */
217 #if defined(UART10)
218 else if (USARTx == UART10)
219 {
220 /* Force reset of UART clock */
221 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_UART10);
222
223 /* Release reset of UART clock */
224 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_UART10);
225 }
226 #endif /* UART10 */
227 else
228 {
229 status = ERROR;
230 }
231
232 return (status);
233 }
234
235 /**
236 * @brief Initialize USART registers according to the specified
237 * parameters in USART_InitStruct.
238 * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
239 * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
240 * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
241 * @param USARTx USART Instance
242 * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
243 * that contains the configuration information for the specified USART peripheral.
244 * @retval An ErrorStatus enumeration value:
245 * - SUCCESS: USART registers are initialized according to USART_InitStruct content
246 * - ERROR: Problem occurred during USART Registers initialization
247 */
LL_USART_Init(USART_TypeDef * USARTx,LL_USART_InitTypeDef * USART_InitStruct)248 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
249 {
250 ErrorStatus status = ERROR;
251 uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
252 LL_RCC_ClocksTypeDef rcc_clocks;
253
254 /* Check the parameters */
255 assert_param(IS_UART_INSTANCE(USARTx));
256 assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
257 assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
258 assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
259 assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
260 assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
261 assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
262 assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
263
264 /* USART needs to be in disabled state, in order to be able to configure some bits in
265 CRx registers */
266 if (LL_USART_IsEnabled(USARTx) == 0U)
267 {
268 /*---------------------------- USART CR1 Configuration -----------------------
269 * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
270 * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
271 * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
272 * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
273 * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
274 */
275 MODIFY_REG(USARTx->CR1,
276 (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
277 USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
278 (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
279 USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
280
281 /*---------------------------- USART CR2 Configuration -----------------------
282 * Configure USARTx CR2 (Stop bits) with parameters:
283 * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
284 * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
285 */
286 LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
287
288 /*---------------------------- USART CR3 Configuration -----------------------
289 * Configure USARTx CR3 (Hardware Flow Control) with parameters:
290 * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
291 */
292 LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
293
294 /*---------------------------- USART BRR Configuration -----------------------
295 * Retrieve Clock frequency used for USART Peripheral
296 */
297 LL_RCC_GetSystemClocksFreq(&rcc_clocks);
298 if (USARTx == USART1)
299 {
300 periphclk = rcc_clocks.PCLK2_Frequency;
301 }
302 else if (USARTx == USART2)
303 {
304 periphclk = rcc_clocks.PCLK1_Frequency;
305 }
306 #if defined(USART3)
307 else if (USARTx == USART3)
308 {
309 periphclk = rcc_clocks.PCLK1_Frequency;
310 }
311 #endif /* USART3 */
312 #if defined(USART6)
313 else if (USARTx == USART6)
314 {
315 periphclk = rcc_clocks.PCLK2_Frequency;
316 }
317 #endif /* USART6 */
318 #if defined(UART4)
319 else if (USARTx == UART4)
320 {
321 periphclk = rcc_clocks.PCLK1_Frequency;
322 }
323 #endif /* UART4 */
324 #if defined(UART5)
325 else if (USARTx == UART5)
326 {
327 periphclk = rcc_clocks.PCLK1_Frequency;
328 }
329 #endif /* UART5 */
330 #if defined(UART7)
331 else if (USARTx == UART7)
332 {
333 periphclk = rcc_clocks.PCLK1_Frequency;
334 }
335 #endif /* UART7 */
336 #if defined(UART8)
337 else if (USARTx == UART8)
338 {
339 periphclk = rcc_clocks.PCLK1_Frequency;
340 }
341 #endif /* UART8 */
342 #if defined(UART9)
343 else if (USARTx == UART9)
344 {
345 periphclk = rcc_clocks.PCLK2_Frequency;
346 }
347 #endif /* UART9 */
348 #if defined(UART10)
349 else if (USARTx == UART10)
350 {
351 periphclk = rcc_clocks.PCLK2_Frequency;
352 }
353 #endif /* UART10 */
354 else
355 {
356 /* Nothing to do, as error code is already assigned to ERROR value */
357 }
358
359 /* Configure the USART Baud Rate :
360 - valid baud rate value (different from 0) is required
361 - Peripheral clock as returned by RCC service, should be valid (different from 0).
362 */
363 if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
364 && (USART_InitStruct->BaudRate != 0U))
365 {
366 status = SUCCESS;
367 LL_USART_SetBaudRate(USARTx,
368 periphclk,
369 USART_InitStruct->OverSampling,
370 USART_InitStruct->BaudRate);
371
372 /* Check BRR is greater than or equal to 16d */
373 assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
374 }
375 }
376 /* Endif (=> USART not in Disabled state => return ERROR) */
377
378 return (status);
379 }
380
381 /**
382 * @brief Set each @ref LL_USART_InitTypeDef field to default value.
383 * @param USART_InitStruct Pointer to a @ref LL_USART_InitTypeDef structure
384 * whose fields will be set to default values.
385 * @retval None
386 */
387
LL_USART_StructInit(LL_USART_InitTypeDef * USART_InitStruct)388 void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
389 {
390 /* Set USART_InitStruct fields to default values */
391 USART_InitStruct->BaudRate = 9600U;
392 USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
393 USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
394 USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
395 USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
396 USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
397 USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
398 }
399
400 /**
401 * @brief Initialize USART Clock related settings according to the
402 * specified parameters in the USART_ClockInitStruct.
403 * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
404 * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
405 * @param USARTx USART Instance
406 * @param USART_ClockInitStruct Pointer to a @ref LL_USART_ClockInitTypeDef structure
407 * that contains the Clock configuration information for the specified USART peripheral.
408 * @retval An ErrorStatus enumeration value:
409 * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
410 * - ERROR: Problem occurred during USART Registers initialization
411 */
LL_USART_ClockInit(USART_TypeDef * USARTx,LL_USART_ClockInitTypeDef * USART_ClockInitStruct)412 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
413 {
414 ErrorStatus status = SUCCESS;
415
416 /* Check USART Instance and Clock signal output parameters */
417 assert_param(IS_UART_INSTANCE(USARTx));
418 assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
419
420 /* USART needs to be in disabled state, in order to be able to configure some bits in
421 CRx registers */
422 if (LL_USART_IsEnabled(USARTx) == 0U)
423 {
424 /*---------------------------- USART CR2 Configuration -----------------------*/
425 /* If Clock signal has to be output */
426 if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
427 {
428 /* Deactivate Clock signal delivery :
429 * - Disable Clock Output: USART_CR2_CLKEN cleared
430 */
431 LL_USART_DisableSCLKOutput(USARTx);
432 }
433 else
434 {
435 /* Ensure USART instance is USART capable */
436 assert_param(IS_USART_INSTANCE(USARTx));
437
438 /* Check clock related parameters */
439 assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
440 assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
441 assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
442
443 /*---------------------------- USART CR2 Configuration -----------------------
444 * Configure USARTx CR2 (Clock signal related bits) with parameters:
445 * - Enable Clock Output: USART_CR2_CLKEN set
446 * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
447 * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
448 * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
449 */
450 MODIFY_REG(USARTx->CR2,
451 USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
452 USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
453 USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
454 }
455 }
456 /* Else (USART not in Disabled state => return ERROR */
457 else
458 {
459 status = ERROR;
460 }
461
462 return (status);
463 }
464
465 /**
466 * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
467 * @param USART_ClockInitStruct Pointer to a @ref LL_USART_ClockInitTypeDef structure
468 * whose fields will be set to default values.
469 * @retval None
470 */
LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef * USART_ClockInitStruct)471 void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
472 {
473 /* Set LL_USART_ClockInitStruct fields with default values */
474 USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
475 USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
476 USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
477 USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
478 }
479
480 /**
481 * @}
482 */
483
484 /**
485 * @}
486 */
487
488 /**
489 * @}
490 */
491
492 #endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || UART10 */
493
494 /**
495 * @}
496 */
497
498 #endif /* USE_FULL_LL_DRIVER */
499
500
501
