1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_rcc.c
4 * @author MCD Application Team
5 * @brief RCC LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 ******************************************************************************
16 */
17 #if defined(USE_FULL_LL_DRIVER)
18
19 /* Includes ------------------------------------------------------------------*/
20 #include "stm32f4xx_ll_rcc.h"
21 #ifdef USE_FULL_ASSERT
22 #include "stm32_assert.h"
23 #else
24 #define assert_param(expr) ((void)0U)
25 #endif /* USE_FULL_ASSERT */
26 /** @addtogroup STM32F4xx_LL_Driver
27 * @{
28 */
29
30 #if defined(RCC)
31
32 /** @addtogroup RCC_LL
33 * @{
34 */
35
36 /* Private types -------------------------------------------------------------*/
37 /* Private variables ---------------------------------------------------------*/
38 /* Private constants ---------------------------------------------------------*/
39 /* Private macros ------------------------------------------------------------*/
40 /** @addtogroup RCC_LL_Private_Macros
41 * @{
42 */
43 #if defined(FMPI2C1)
44 #define IS_LL_RCC_FMPI2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_FMPI2C1_CLKSOURCE)
45 #endif /* FMPI2C1 */
46
47 #if defined(LPTIM1)
48 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE))
49 #endif /* LPTIM1 */
50
51 #if defined(SAI1)
52 #if defined(RCC_DCKCFGR_SAI1SRC)
53 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
54 || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
55 #elif defined(RCC_DCKCFGR_SAI1ASRC)
56 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_A_CLKSOURCE) \
57 || ((__VALUE__) == LL_RCC_SAI1_B_CLKSOURCE))
58 #endif /* RCC_DCKCFGR_SAI1SRC */
59 #endif /* SAI1 */
60
61 #if defined(SDIO)
62 #define IS_LL_RCC_SDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDIO_CLKSOURCE))
63 #endif /* SDIO */
64
65 #if defined(RNG)
66 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
67 #endif /* RNG */
68
69 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
70 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
71 #endif /* USB_OTG_FS || USB_OTG_HS */
72
73 #if defined(DFSDM2_Channel0)
74 #define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
75
76 #define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE) \
77 || ((__VALUE__) == LL_RCC_DFSDM2_AUDIO_CLKSOURCE))
78 #elif defined(DFSDM1_Channel0)
79 #define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
80
81 #define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE))
82 #endif /* DFSDM2_Channel0 */
83
84 #if defined(RCC_DCKCFGR_I2S2SRC)
85 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE) \
86 || ((__VALUE__) == LL_RCC_I2S2_CLKSOURCE))
87 #else
88 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE))
89 #endif /* RCC_DCKCFGR_I2S2SRC */
90
91 #if defined(CEC)
92 #define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
93 #endif /* CEC */
94
95 #if defined(DSI)
96 #define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DSI_CLKSOURCE))
97 #endif /* DSI */
98
99 #if defined(LTDC)
100 #define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE))
101 #endif /* LTDC */
102
103 #if defined(SPDIFRX)
104 #define IS_LL_RCC_SPDIFRX_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPDIFRX1_CLKSOURCE))
105 #endif /* SPDIFRX */
106 /**
107 * @}
108 */
109
110 /* Private function prototypes -----------------------------------------------*/
111 /** @defgroup RCC_LL_Private_Functions RCC Private functions
112 * @{
113 */
114 uint32_t RCC_GetSystemClockFreq(void);
115 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
116 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
117 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
118 uint32_t RCC_PLL_GetFreqDomain_SYS(uint32_t SYSCLK_Source);
119 uint32_t RCC_PLL_GetFreqDomain_48M(void);
120 #if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)
121 uint32_t RCC_PLL_GetFreqDomain_I2S(void);
122 #endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */
123 #if defined(SPDIFRX)
124 uint32_t RCC_PLL_GetFreqDomain_SPDIFRX(void);
125 #endif /* SPDIFRX */
126 #if defined(RCC_PLLCFGR_PLLR)
127 #if defined(SAI1)
128 uint32_t RCC_PLL_GetFreqDomain_SAI(void);
129 #endif /* SAI1 */
130 #endif /* RCC_PLLCFGR_PLLR */
131 #if defined(DSI)
132 uint32_t RCC_PLL_GetFreqDomain_DSI(void);
133 #endif /* DSI */
134 #if defined(RCC_PLLSAI_SUPPORT)
135 uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void);
136 #if defined(RCC_PLLSAICFGR_PLLSAIP)
137 uint32_t RCC_PLLSAI_GetFreqDomain_48M(void);
138 #endif /* RCC_PLLSAICFGR_PLLSAIP */
139 #if defined(LTDC)
140 uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void);
141 #endif /* LTDC */
142 #endif /* RCC_PLLSAI_SUPPORT */
143 #if defined(RCC_PLLI2S_SUPPORT)
144 uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);
145 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
146 uint32_t RCC_PLLI2S_GetFreqDomain_48M(void);
147 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
148 #if defined(SAI1)
149 uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void);
150 #endif /* SAI1 */
151 #if defined(SPDIFRX)
152 uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void);
153 #endif /* SPDIFRX */
154 #endif /* RCC_PLLI2S_SUPPORT */
155 /**
156 * @}
157 */
158
159
160 /* Exported functions --------------------------------------------------------*/
161 /** @addtogroup RCC_LL_Exported_Functions
162 * @{
163 */
164
165 /** @addtogroup RCC_LL_EF_Init
166 * @{
167 */
168
169 /**
170 * @brief Reset the RCC clock configuration to the default reset state.
171 * @note The default reset state of the clock configuration is given below:
172 * - HSI ON and used as system clock source
173 * - HSE and PLL OFF
174 * - AHB, APB1 and APB2 prescaler set to 1.
175 * - CSS, MCO OFF
176 * - All interrupts disabled
177 * @note This function doesn't modify the configuration of the
178 * - Peripheral clocks
179 * - LSI, LSE and RTC clocks
180 * @retval An ErrorStatus enumeration value:
181 * - SUCCESS: RCC registers are de-initialized
182 * - ERROR: not applicable
183 */
LL_RCC_DeInit(void)184 ErrorStatus LL_RCC_DeInit(void)
185 {
186 __IO uint32_t vl_mask;
187
188 /* Set HSION bit */
189 LL_RCC_HSI_Enable();
190
191 /* Wait for HSI READY bit */
192 while (LL_RCC_HSI_IsReady() != 1U)
193 {}
194
195 /* Reset CFGR register */
196 LL_RCC_WriteReg(CFGR, 0x00000000U);
197
198 /* Read CR register */
199 vl_mask = LL_RCC_ReadReg(CR);
200
201 /* Reset HSEON, HSEBYP, PLLON, CSSON bits */
202 CLEAR_BIT(vl_mask,
203 (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON));
204
205 #if defined(RCC_PLLSAI_SUPPORT)
206 /* Reset PLLSAION bit */
207 CLEAR_BIT(vl_mask, RCC_CR_PLLSAION);
208 #endif /* RCC_PLLSAI_SUPPORT */
209
210 #if defined(RCC_PLLI2S_SUPPORT)
211 /* Reset PLLI2SON bit */
212 CLEAR_BIT(vl_mask, RCC_CR_PLLI2SON);
213 #endif /* RCC_PLLI2S_SUPPORT */
214
215 /* Write new value in CR register */
216 LL_RCC_WriteReg(CR, vl_mask);
217
218 /* Set HSITRIM bits to the reset value*/
219 LL_RCC_HSI_SetCalibTrimming(0x10U);
220
221 /* Wait for PLL READY bit to be reset */
222 while (LL_RCC_PLL_IsReady() != 0U)
223 {}
224
225 /* Reset PLLCFGR register */
226 LL_RCC_WriteReg(PLLCFGR, RCC_PLLCFGR_RST_VALUE);
227
228 #if defined(RCC_PLLI2S_SUPPORT)
229 /* Reset PLLI2SCFGR register */
230 LL_RCC_WriteReg(PLLI2SCFGR, RCC_PLLI2SCFGR_RST_VALUE);
231 #endif /* RCC_PLLI2S_SUPPORT */
232
233 #if defined(RCC_PLLSAI_SUPPORT)
234 /* Reset PLLSAICFGR register */
235 LL_RCC_WriteReg(PLLSAICFGR, RCC_PLLSAICFGR_RST_VALUE);
236 #endif /* RCC_PLLSAI_SUPPORT */
237
238 /* Disable all interrupts */
239 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE);
240
241 #if defined(RCC_CIR_PLLI2SRDYIE)
242 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
243 #endif /* RCC_CIR_PLLI2SRDYIE */
244
245 #if defined(RCC_CIR_PLLSAIRDYIE)
246 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
247 #endif /* RCC_CIR_PLLSAIRDYIE */
248
249 /* Clear all interrupt flags */
250 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC |
251 RCC_CIR_CSSC);
252
253 #if defined(RCC_CIR_PLLI2SRDYC)
254 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
255 #endif /* RCC_CIR_PLLI2SRDYC */
256
257 #if defined(RCC_CIR_PLLSAIRDYC)
258 SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
259 #endif /* RCC_CIR_PLLSAIRDYC */
260
261 /* Clear LSION bit */
262 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
263
264 /* Reset all CSR flags */
265 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
266
267 return SUCCESS;
268 }
269
270 /**
271 * @}
272 */
273
274 /** @addtogroup RCC_LL_EF_Get_Freq
275 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
276 * and different peripheral clocks available on the device.
277 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
278 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
279 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
280 * or HSI_VALUE(**) multiplied/divided by the PLL factors.
281 * @note (**) HSI_VALUE is a constant defined in this file (default value
282 * 16 MHz) but the real value may vary depending on the variations
283 * in voltage and temperature.
284 * @note (***) HSE_VALUE is a constant defined in this file (default value
285 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
286 * frequency of the crystal used. Otherwise, this function may
287 * have wrong result.
288 * @note The result of this function could be incorrect when using fractional
289 * value for HSE crystal.
290 * @note This function can be used by the user application to compute the
291 * baud-rate for the communication peripherals or configure other parameters.
292 * @{
293 */
294
295 /**
296 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
297 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
298 * must be called to update structure fields. Otherwise, any
299 * configuration based on this function will be incorrect.
300 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
301 * @retval None
302 */
LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef * RCC_Clocks)303 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
304 {
305 /* Get SYSCLK frequency */
306 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
307
308 /* HCLK clock frequency */
309 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
310
311 /* PCLK1 clock frequency */
312 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
313
314 /* PCLK2 clock frequency */
315 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
316 }
317
318 #if defined(FMPI2C1)
319 /**
320 * @brief Return FMPI2Cx clock frequency
321 * @param FMPI2CxSource This parameter can be one of the following values:
322 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE
323 * @retval FMPI2C clock frequency (in Hz)
324 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
325 */
LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource)326 uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource)
327 {
328 uint32_t FMPI2C_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
329
330 /* Check parameter */
331 assert_param(IS_LL_RCC_FMPI2C_CLKSOURCE(FMPI2CxSource));
332
333 if (FMPI2CxSource == LL_RCC_FMPI2C1_CLKSOURCE)
334 {
335 /* FMPI2C1 CLK clock frequency */
336 switch (LL_RCC_GetFMPI2CClockSource(FMPI2CxSource))
337 {
338 case LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK: /* FMPI2C1 Clock is System Clock */
339 FMPI2C_frequency = RCC_GetSystemClockFreq();
340 break;
341
342 case LL_RCC_FMPI2C1_CLKSOURCE_HSI: /* FMPI2C1 Clock is HSI Osc. */
343 if (LL_RCC_HSI_IsReady())
344 {
345 FMPI2C_frequency = HSI_VALUE;
346 }
347 break;
348
349 case LL_RCC_FMPI2C1_CLKSOURCE_PCLK1: /* FMPI2C1 Clock is PCLK1 */
350 default:
351 FMPI2C_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
352 break;
353 }
354 }
355
356 return FMPI2C_frequency;
357 }
358 #endif /* FMPI2C1 */
359
360 /**
361 * @brief Return I2Sx clock frequency
362 * @param I2SxSource This parameter can be one of the following values:
363 * @arg @ref LL_RCC_I2S1_CLKSOURCE
364 * @arg @ref LL_RCC_I2S2_CLKSOURCE (*)
365 *
366 * (*) value not defined in all devices.
367 * @retval I2S clock frequency (in Hz)
368 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
369 */
LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)370 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
371 {
372 uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
373
374 /* Check parameter */
375 assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
376
377 if (I2SxSource == LL_RCC_I2S1_CLKSOURCE)
378 {
379 /* I2S1 CLK clock frequency */
380 switch (LL_RCC_GetI2SClockSource(I2SxSource))
381 {
382 #if defined(RCC_PLLI2S_SUPPORT)
383 case LL_RCC_I2S1_CLKSOURCE_PLLI2S: /* I2S1 Clock is PLLI2S */
384 if (LL_RCC_PLLI2S_IsReady())
385 {
386 i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S();
387 }
388 break;
389 #endif /* RCC_PLLI2S_SUPPORT */
390
391 #if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)
392 case LL_RCC_I2S1_CLKSOURCE_PLL: /* I2S1 Clock is PLL */
393 if (LL_RCC_PLL_IsReady())
394 {
395 i2s_frequency = RCC_PLL_GetFreqDomain_I2S();
396 }
397 break;
398
399 case LL_RCC_I2S1_CLKSOURCE_PLLSRC: /* I2S1 Clock is PLL Main source */
400 switch (LL_RCC_PLL_GetMainSource())
401 {
402 case LL_RCC_PLLSOURCE_HSE: /* I2S1 Clock is HSE Osc. */
403 if (LL_RCC_HSE_IsReady())
404 {
405 i2s_frequency = HSE_VALUE;
406 }
407 break;
408
409 case LL_RCC_PLLSOURCE_HSI: /* I2S1 Clock is HSI Osc. */
410 default:
411 if (LL_RCC_HSI_IsReady())
412 {
413 i2s_frequency = HSI_VALUE;
414 }
415 break;
416 }
417 break;
418 #endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */
419
420 case LL_RCC_I2S1_CLKSOURCE_PIN: /* I2S1 Clock is External clock */
421 default:
422 i2s_frequency = EXTERNAL_CLOCK_VALUE;
423 break;
424 }
425 }
426 #if defined(RCC_DCKCFGR_I2S2SRC)
427 else
428 {
429 /* I2S2 CLK clock frequency */
430 switch (LL_RCC_GetI2SClockSource(I2SxSource))
431 {
432 case LL_RCC_I2S2_CLKSOURCE_PLLI2S: /* I2S2 Clock is PLLI2S */
433 if (LL_RCC_PLLI2S_IsReady())
434 {
435 i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S();
436 }
437 break;
438
439 case LL_RCC_I2S2_CLKSOURCE_PLL: /* I2S2 Clock is PLL */
440 if (LL_RCC_PLL_IsReady())
441 {
442 i2s_frequency = RCC_PLL_GetFreqDomain_I2S();
443 }
444 break;
445
446 case LL_RCC_I2S2_CLKSOURCE_PLLSRC: /* I2S2 Clock is PLL Main source */
447 switch (LL_RCC_PLL_GetMainSource())
448 {
449 case LL_RCC_PLLSOURCE_HSE: /* I2S2 Clock is HSE Osc. */
450 if (LL_RCC_HSE_IsReady())
451 {
452 i2s_frequency = HSE_VALUE;
453 }
454 break;
455
456 case LL_RCC_PLLSOURCE_HSI: /* I2S2 Clock is HSI Osc. */
457 default:
458 if (LL_RCC_HSI_IsReady())
459 {
460 i2s_frequency = HSI_VALUE;
461 }
462 break;
463 }
464 break;
465
466 case LL_RCC_I2S2_CLKSOURCE_PIN: /* I2S2 Clock is External clock */
467 default:
468 i2s_frequency = EXTERNAL_CLOCK_VALUE;
469 break;
470 }
471 }
472 #endif /* RCC_DCKCFGR_I2S2SRC */
473
474 return i2s_frequency;
475 }
476
477 #if defined(LPTIM1)
478 /**
479 * @brief Return LPTIMx clock frequency
480 * @param LPTIMxSource This parameter can be one of the following values:
481 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
482 * @retval LPTIM clock frequency (in Hz)
483 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
484 */
LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)485 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
486 {
487 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
488
489 /* Check parameter */
490 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
491
492 if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
493 {
494 /* LPTIM1CLK clock frequency */
495 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
496 {
497 case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
498 if (LL_RCC_LSI_IsReady())
499 {
500 lptim_frequency = LSI_VALUE;
501 }
502 break;
503
504 case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */
505 if (LL_RCC_HSI_IsReady())
506 {
507 lptim_frequency = HSI_VALUE;
508 }
509 break;
510
511 case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
512 if (LL_RCC_LSE_IsReady())
513 {
514 lptim_frequency = LSE_VALUE;
515 }
516 break;
517
518 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */
519 default:
520 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
521 break;
522 }
523 }
524
525 return lptim_frequency;
526 }
527 #endif /* LPTIM1 */
528
529 #if defined(SAI1)
530 /**
531 * @brief Return SAIx clock frequency
532 * @param SAIxSource This parameter can be one of the following values:
533 * @arg @ref LL_RCC_SAI1_CLKSOURCE (*)
534 * @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
535 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*)
536 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*)
537 *
538 * (*) value not defined in all devices.
539 * @retval SAI clock frequency (in Hz)
540 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
541 */
LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)542 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
543 {
544 uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
545
546 /* Check parameter */
547 assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
548
549 #if defined(RCC_DCKCFGR_SAI1SRC)
550 if ((SAIxSource == LL_RCC_SAI1_CLKSOURCE) || (SAIxSource == LL_RCC_SAI2_CLKSOURCE))
551 {
552 /* SAI1CLK clock frequency */
553 switch (LL_RCC_GetSAIClockSource(SAIxSource))
554 {
555 case LL_RCC_SAI1_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 clock source */
556 case LL_RCC_SAI2_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI2 clock source */
557 if (LL_RCC_PLLSAI_IsReady())
558 {
559 sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
560 }
561 break;
562
563 case LL_RCC_SAI1_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 clock source */
564 case LL_RCC_SAI2_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI2 clock source */
565 if (LL_RCC_PLLI2S_IsReady())
566 {
567 sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
568 }
569 break;
570
571 case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */
572 case LL_RCC_SAI2_CLKSOURCE_PLL: /* PLL clock used as SAI2 clock source */
573 if (LL_RCC_PLL_IsReady())
574 {
575 sai_frequency = RCC_PLL_GetFreqDomain_SAI();
576 }
577 break;
578
579 case LL_RCC_SAI2_CLKSOURCE_PLLSRC:
580 switch (LL_RCC_PLL_GetMainSource())
581 {
582 case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI2 clock source */
583 if (LL_RCC_HSE_IsReady())
584 {
585 sai_frequency = HSE_VALUE;
586 }
587 break;
588
589 case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI2 clock source */
590 default:
591 if (LL_RCC_HSI_IsReady())
592 {
593 sai_frequency = HSI_VALUE;
594 }
595 break;
596 }
597 break;
598
599 case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */
600 default:
601 sai_frequency = EXTERNAL_CLOCK_VALUE;
602 break;
603 }
604 }
605 #endif /* RCC_DCKCFGR_SAI1SRC */
606 #if defined(RCC_DCKCFGR_SAI1ASRC)
607 if ((SAIxSource == LL_RCC_SAI1_A_CLKSOURCE) || (SAIxSource == LL_RCC_SAI1_B_CLKSOURCE))
608 {
609 /* SAI1CLK clock frequency */
610 switch (LL_RCC_GetSAIClockSource(SAIxSource))
611 {
612 #if defined(RCC_PLLSAI_SUPPORT)
613 case LL_RCC_SAI1_A_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 Block A clock source */
614 case LL_RCC_SAI1_B_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 Block B clock source */
615 if (LL_RCC_PLLSAI_IsReady())
616 {
617 sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
618 }
619 break;
620 #endif /* RCC_PLLSAI_SUPPORT */
621
622 case LL_RCC_SAI1_A_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 Block A clock source */
623 case LL_RCC_SAI1_B_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 Block B clock source */
624 if (LL_RCC_PLLI2S_IsReady())
625 {
626 sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
627 }
628 break;
629
630 #if defined(RCC_SAI1A_PLLSOURCE_SUPPORT)
631 case LL_RCC_SAI1_A_CLKSOURCE_PLL: /* PLL clock used as SAI1 Block A clock source */
632 case LL_RCC_SAI1_B_CLKSOURCE_PLL: /* PLL clock used as SAI1 Block B clock source */
633 if (LL_RCC_PLL_IsReady())
634 {
635 sai_frequency = RCC_PLL_GetFreqDomain_SAI();
636 }
637 break;
638
639 case LL_RCC_SAI1_A_CLKSOURCE_PLLSRC:
640 case LL_RCC_SAI1_B_CLKSOURCE_PLLSRC:
641 switch (LL_RCC_PLL_GetMainSource())
642 {
643 case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI1 Block A or B clock source */
644 if (LL_RCC_HSE_IsReady())
645 {
646 sai_frequency = HSE_VALUE;
647 }
648 break;
649
650 case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI1 Block A or B clock source */
651 default:
652 if (LL_RCC_HSI_IsReady())
653 {
654 sai_frequency = HSI_VALUE;
655 }
656 break;
657 }
658 break;
659 #endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */
660
661 case LL_RCC_SAI1_A_CLKSOURCE_PIN: /* External input clock used as SAI1 Block A clock source */
662 case LL_RCC_SAI1_B_CLKSOURCE_PIN: /* External input clock used as SAI1 Block B clock source */
663 default:
664 sai_frequency = EXTERNAL_CLOCK_VALUE;
665 break;
666 }
667 }
668 #endif /* RCC_DCKCFGR_SAI1ASRC */
669
670 return sai_frequency;
671 }
672 #endif /* SAI1 */
673
674 #if defined(SDIO)
675 /**
676 * @brief Return SDIOx clock frequency
677 * @param SDIOxSource This parameter can be one of the following values:
678 * @arg @ref LL_RCC_SDIO_CLKSOURCE
679 * @retval SDIO clock frequency (in Hz)
680 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
681 */
LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource)682 uint32_t LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource)
683 {
684 uint32_t SDIO_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
685
686 /* Check parameter */
687 assert_param(IS_LL_RCC_SDIO_CLKSOURCE(SDIOxSource));
688
689 if (SDIOxSource == LL_RCC_SDIO_CLKSOURCE)
690 {
691 #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
692 /* SDIOCLK clock frequency */
693 switch (LL_RCC_GetSDIOClockSource(SDIOxSource))
694 {
695 case LL_RCC_SDIO_CLKSOURCE_PLL48CLK: /* PLL48M clock used as SDIO clock source */
696 switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE))
697 {
698 case LL_RCC_CK48M_CLKSOURCE_PLL: /* PLL clock used as 48Mhz domain clock */
699 if (LL_RCC_PLL_IsReady())
700 {
701 SDIO_frequency = RCC_PLL_GetFreqDomain_48M();
702 }
703 break;
704
705 #if defined(RCC_PLLSAI_SUPPORT)
706 case LL_RCC_CK48M_CLKSOURCE_PLLSAI: /* PLLSAI clock used as 48Mhz domain clock */
707 default:
708 if (LL_RCC_PLLSAI_IsReady())
709 {
710 SDIO_frequency = RCC_PLLSAI_GetFreqDomain_48M();
711 }
712 break;
713 #endif /* RCC_PLLSAI_SUPPORT */
714
715 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
716 case LL_RCC_CK48M_CLKSOURCE_PLLI2S: /* PLLI2S clock used as 48Mhz domain clock */
717 default:
718 if (LL_RCC_PLLI2S_IsReady())
719 {
720 SDIO_frequency = RCC_PLLI2S_GetFreqDomain_48M();
721 }
722 break;
723 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
724 }
725 break;
726
727 case LL_RCC_SDIO_CLKSOURCE_SYSCLK: /* PLL clock used as SDIO clock source */
728 default:
729 SDIO_frequency = RCC_GetSystemClockFreq();
730 break;
731 }
732 #else
733 /* PLL clock used as 48Mhz domain clock */
734 if (LL_RCC_PLL_IsReady())
735 {
736 SDIO_frequency = RCC_PLL_GetFreqDomain_48M();
737 }
738 #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
739 }
740
741 return SDIO_frequency;
742 }
743 #endif /* SDIO */
744
745 #if defined(RNG)
746 /**
747 * @brief Return RNGx clock frequency
748 * @param RNGxSource This parameter can be one of the following values:
749 * @arg @ref LL_RCC_RNG_CLKSOURCE
750 * @retval RNG clock frequency (in Hz)
751 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
752 */
LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)753 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
754 {
755 uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
756
757 /* Check parameter */
758 assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
759
760 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
761 /* RNGCLK clock frequency */
762 switch (LL_RCC_GetRNGClockSource(RNGxSource))
763 {
764 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
765 case LL_RCC_RNG_CLKSOURCE_PLLI2S: /* PLLI2S clock used as RNG clock source */
766 if (LL_RCC_PLLI2S_IsReady())
767 {
768 rng_frequency = RCC_PLLI2S_GetFreqDomain_48M();
769 }
770 break;
771 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
772
773 #if defined(RCC_PLLSAI_SUPPORT)
774 case LL_RCC_RNG_CLKSOURCE_PLLSAI: /* PLLSAI clock used as RNG clock source */
775 if (LL_RCC_PLLSAI_IsReady())
776 {
777 rng_frequency = RCC_PLLSAI_GetFreqDomain_48M();
778 }
779 break;
780 #endif /* RCC_PLLSAI_SUPPORT */
781
782 case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */
783 default:
784 if (LL_RCC_PLL_IsReady())
785 {
786 rng_frequency = RCC_PLL_GetFreqDomain_48M();
787 }
788 break;
789 }
790 #else
791 /* PLL clock used as RNG clock source */
792 if (LL_RCC_PLL_IsReady())
793 {
794 rng_frequency = RCC_PLL_GetFreqDomain_48M();
795 }
796 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
797
798 return rng_frequency;
799 }
800 #endif /* RNG */
801
802 #if defined(CEC)
803 /**
804 * @brief Return CEC clock frequency
805 * @param CECxSource This parameter can be one of the following values:
806 * @arg @ref LL_RCC_CEC_CLKSOURCE
807 * @retval CEC clock frequency (in Hz)
808 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
809 */
LL_RCC_GetCECClockFreq(uint32_t CECxSource)810 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
811 {
812 uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
813
814 /* Check parameter */
815 assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
816
817 /* CECCLK clock frequency */
818 switch (LL_RCC_GetCECClockSource(CECxSource))
819 {
820 case LL_RCC_CEC_CLKSOURCE_LSE: /* CEC Clock is LSE Osc. */
821 if (LL_RCC_LSE_IsReady())
822 {
823 cec_frequency = LSE_VALUE;
824 }
825 break;
826
827 case LL_RCC_CEC_CLKSOURCE_HSI_DIV488: /* CEC Clock is HSI Osc. */
828 default:
829 if (LL_RCC_HSI_IsReady())
830 {
831 cec_frequency = HSI_VALUE / 488U;
832 }
833 break;
834 }
835
836 return cec_frequency;
837 }
838 #endif /* CEC */
839
840 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
841 /**
842 * @brief Return USBx clock frequency
843 * @param USBxSource This parameter can be one of the following values:
844 * @arg @ref LL_RCC_USB_CLKSOURCE
845 * @retval USB clock frequency (in Hz)
846 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
847 */
LL_RCC_GetUSBClockFreq(uint32_t USBxSource)848 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
849 {
850 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
851
852 /* Check parameter */
853 assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
854
855 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
856 /* USBCLK clock frequency */
857 switch (LL_RCC_GetUSBClockSource(USBxSource))
858 {
859 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
860 case LL_RCC_USB_CLKSOURCE_PLLI2S: /* PLLI2S clock used as USB clock source */
861 if (LL_RCC_PLLI2S_IsReady())
862 {
863 usb_frequency = RCC_PLLI2S_GetFreqDomain_48M();
864 }
865 break;
866
867 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
868
869 #if defined(RCC_PLLSAI_SUPPORT)
870 case LL_RCC_USB_CLKSOURCE_PLLSAI: /* PLLSAI clock used as USB clock source */
871 if (LL_RCC_PLLSAI_IsReady())
872 {
873 usb_frequency = RCC_PLLSAI_GetFreqDomain_48M();
874 }
875 break;
876 #endif /* RCC_PLLSAI_SUPPORT */
877
878 case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
879 default:
880 if (LL_RCC_PLL_IsReady())
881 {
882 usb_frequency = RCC_PLL_GetFreqDomain_48M();
883 }
884 break;
885 }
886 #else
887 /* PLL clock used as USB clock source */
888 if (LL_RCC_PLL_IsReady())
889 {
890 usb_frequency = RCC_PLL_GetFreqDomain_48M();
891 }
892 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
893
894 return usb_frequency;
895 }
896 #endif /* USB_OTG_FS || USB_OTG_HS */
897
898 #if defined(DFSDM1_Channel0)
899 /**
900 * @brief Return DFSDMx clock frequency
901 * @param DFSDMxSource This parameter can be one of the following values:
902 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
903 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*)
904 *
905 * (*) value not defined in all devices.
906 * @retval DFSDM clock frequency (in Hz)
907 */
LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)908 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
909 {
910 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
911
912 /* Check parameter */
913 assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource));
914
915 if (DFSDMxSource == LL_RCC_DFSDM1_CLKSOURCE)
916 {
917 /* DFSDM1CLK clock frequency */
918 switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
919 {
920 case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK: /* DFSDM1 Clock is SYSCLK */
921 dfsdm_frequency = RCC_GetSystemClockFreq();
922 break;
923
924 case LL_RCC_DFSDM1_CLKSOURCE_PCLK2: /* DFSDM1 Clock is PCLK2 */
925 default:
926 dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
927 break;
928 }
929 }
930 #if defined(DFSDM2_Channel0)
931 else
932 {
933 /* DFSDM2CLK clock frequency */
934 switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
935 {
936 case LL_RCC_DFSDM2_CLKSOURCE_SYSCLK: /* DFSDM2 Clock is SYSCLK */
937 dfsdm_frequency = RCC_GetSystemClockFreq();
938 break;
939
940 case LL_RCC_DFSDM2_CLKSOURCE_PCLK2: /* DFSDM2 Clock is PCLK2 */
941 default:
942 dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
943 break;
944 }
945 }
946 #endif /* DFSDM2_Channel0 */
947
948 return dfsdm_frequency;
949 }
950
951 /**
952 * @brief Return DFSDMx Audio clock frequency
953 * @param DFSDMxSource This parameter can be one of the following values:
954 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
955 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*)
956 *
957 * (*) value not defined in all devices.
958 * @retval DFSDM clock frequency (in Hz)
959 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
960 */
LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)961 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)
962 {
963 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
964
965 /* Check parameter */
966 assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource));
967
968 if (DFSDMxSource == LL_RCC_DFSDM1_AUDIO_CLKSOURCE)
969 {
970 /* DFSDM1CLK clock frequency */
971 switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
972 {
973 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1: /* I2S1 clock used as DFSDM1 clock */
974 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
975 break;
976
977 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2: /* I2S2 clock used as DFSDM1 clock */
978 default:
979 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S2_CLKSOURCE);
980 break;
981 }
982 }
983 #if defined(DFSDM2_Channel0)
984 else
985 {
986 /* DFSDM2CLK clock frequency */
987 switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
988 {
989 case LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1: /* I2S1 clock used as DFSDM2 clock */
990 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
991 break;
992
993 case LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2: /* I2S2 clock used as DFSDM2 clock */
994 default:
995 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S2_CLKSOURCE);
996 break;
997 }
998 }
999 #endif /* DFSDM2_Channel0 */
1000
1001 return dfsdm_frequency;
1002 }
1003 #endif /* DFSDM1_Channel0 */
1004
1005 #if defined(DSI)
1006 /**
1007 * @brief Return DSI clock frequency
1008 * @param DSIxSource This parameter can be one of the following values:
1009 * @arg @ref LL_RCC_DSI_CLKSOURCE
1010 * @retval DSI clock frequency (in Hz)
1011 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1012 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
1013 */
LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)1014 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
1015 {
1016 uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1017
1018 /* Check parameter */
1019 assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource));
1020
1021 /* DSICLK clock frequency */
1022 switch (LL_RCC_GetDSIClockSource(DSIxSource))
1023 {
1024 case LL_RCC_DSI_CLKSOURCE_PLL: /* DSI Clock is PLL Osc. */
1025 if (LL_RCC_PLL_IsReady())
1026 {
1027 dsi_frequency = RCC_PLL_GetFreqDomain_DSI();
1028 }
1029 break;
1030
1031 case LL_RCC_DSI_CLKSOURCE_PHY: /* DSI Clock is DSI physical clock. */
1032 default:
1033 dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1034 break;
1035 }
1036
1037 return dsi_frequency;
1038 }
1039 #endif /* DSI */
1040
1041 #if defined(LTDC)
1042 /**
1043 * @brief Return LTDC clock frequency
1044 * @param LTDCxSource This parameter can be one of the following values:
1045 * @arg @ref LL_RCC_LTDC_CLKSOURCE
1046 * @retval LTDC clock frequency (in Hz)
1047 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready
1048 */
LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)1049 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)
1050 {
1051 uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1052
1053 /* Check parameter */
1054 assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource));
1055
1056 if (LL_RCC_PLLSAI_IsReady())
1057 {
1058 ltdc_frequency = RCC_PLLSAI_GetFreqDomain_LTDC();
1059 }
1060
1061 return ltdc_frequency;
1062 }
1063 #endif /* LTDC */
1064
1065 #if defined(SPDIFRX)
1066 /**
1067 * @brief Return SPDIFRX clock frequency
1068 * @param SPDIFRXxSource This parameter can be one of the following values:
1069 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
1070 * @retval SPDIFRX clock frequency (in Hz)
1071 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1072 */
LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource)1073 uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource)
1074 {
1075 uint32_t spdifrx_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1076
1077 /* Check parameter */
1078 assert_param(IS_LL_RCC_SPDIFRX_CLKSOURCE(SPDIFRXxSource));
1079
1080 /* SPDIFRX1CLK clock frequency */
1081 switch (LL_RCC_GetSPDIFRXClockSource(SPDIFRXxSource))
1082 {
1083 case LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S: /* SPDIFRX Clock is PLLI2S Osc. */
1084 if (LL_RCC_PLLI2S_IsReady())
1085 {
1086 spdifrx_frequency = RCC_PLLI2S_GetFreqDomain_SPDIFRX();
1087 }
1088 break;
1089
1090 case LL_RCC_SPDIFRX1_CLKSOURCE_PLL: /* SPDIFRX Clock is PLL Osc. */
1091 default:
1092 if (LL_RCC_PLL_IsReady())
1093 {
1094 spdifrx_frequency = RCC_PLL_GetFreqDomain_SPDIFRX();
1095 }
1096 break;
1097 }
1098
1099 return spdifrx_frequency;
1100 }
1101 #endif /* SPDIFRX */
1102
1103 /**
1104 * @}
1105 */
1106
1107 /**
1108 * @}
1109 */
1110
1111 /** @addtogroup RCC_LL_Private_Functions
1112 * @{
1113 */
1114
1115 /**
1116 * @brief Return SYSTEM clock frequency
1117 * @retval SYSTEM clock frequency (in Hz)
1118 */
RCC_GetSystemClockFreq(void)1119 uint32_t RCC_GetSystemClockFreq(void)
1120 {
1121 uint32_t frequency = 0U;
1122
1123 /* Get SYSCLK source -------------------------------------------------------*/
1124 switch (LL_RCC_GetSysClkSource())
1125 {
1126 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
1127 frequency = HSI_VALUE;
1128 break;
1129
1130 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
1131 frequency = HSE_VALUE;
1132 break;
1133
1134 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
1135 frequency = RCC_PLL_GetFreqDomain_SYS(LL_RCC_SYS_CLKSOURCE_STATUS_PLL);
1136 break;
1137
1138 #if defined(RCC_PLLR_SYSCLK_SUPPORT)
1139 case LL_RCC_SYS_CLKSOURCE_STATUS_PLLR: /* PLLR used as system clock source */
1140 frequency = RCC_PLL_GetFreqDomain_SYS(LL_RCC_SYS_CLKSOURCE_STATUS_PLLR);
1141 break;
1142 #endif /* RCC_PLLR_SYSCLK_SUPPORT */
1143
1144 default:
1145 frequency = HSI_VALUE;
1146 break;
1147 }
1148
1149 return frequency;
1150 }
1151
1152 /**
1153 * @brief Return HCLK clock frequency
1154 * @param SYSCLK_Frequency SYSCLK clock frequency
1155 * @retval HCLK clock frequency (in Hz)
1156 */
RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)1157 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
1158 {
1159 /* HCLK clock frequency */
1160 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
1161 }
1162
1163 /**
1164 * @brief Return PCLK1 clock frequency
1165 * @param HCLK_Frequency HCLK clock frequency
1166 * @retval PCLK1 clock frequency (in Hz)
1167 */
RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)1168 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
1169 {
1170 /* PCLK1 clock frequency */
1171 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
1172 }
1173
1174 /**
1175 * @brief Return PCLK2 clock frequency
1176 * @param HCLK_Frequency HCLK clock frequency
1177 * @retval PCLK2 clock frequency (in Hz)
1178 */
RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)1179 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
1180 {
1181 /* PCLK2 clock frequency */
1182 return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
1183 }
1184
1185 /**
1186 * @brief Return PLL clock frequency used for system domain
1187 * @param SYSCLK_Source System clock source
1188 * @retval PLL clock frequency (in Hz)
1189 */
RCC_PLL_GetFreqDomain_SYS(uint32_t SYSCLK_Source)1190 uint32_t RCC_PLL_GetFreqDomain_SYS(uint32_t SYSCLK_Source)
1191 {
1192 uint32_t pllinputfreq = 0U;
1193 uint32_t pllsource = 0U;
1194 uint32_t plloutputfreq = 0U;
1195
1196 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1197 SYSCLK = PLL_VCO / (PLLP or PLLR)
1198 */
1199 pllsource = LL_RCC_PLL_GetMainSource();
1200
1201 switch (pllsource)
1202 {
1203 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1204 pllinputfreq = HSI_VALUE;
1205 break;
1206
1207 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1208 pllinputfreq = HSE_VALUE;
1209 break;
1210
1211 default:
1212 pllinputfreq = HSI_VALUE;
1213 break;
1214 }
1215
1216 if (SYSCLK_Source == LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
1217 {
1218 plloutputfreq = __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1219 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
1220 }
1221 #if defined(RCC_PLLR_SYSCLK_SUPPORT)
1222 else
1223 {
1224 plloutputfreq = __LL_RCC_CALC_PLLRCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1225 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1226 }
1227 #endif /* RCC_PLLR_SYSCLK_SUPPORT */
1228
1229 return plloutputfreq;
1230 }
1231
1232 /**
1233 * @brief Return PLL clock frequency used for 48 MHz domain
1234 * @retval PLL clock frequency (in Hz)
1235 */
RCC_PLL_GetFreqDomain_48M(void)1236 uint32_t RCC_PLL_GetFreqDomain_48M(void)
1237 {
1238 uint32_t pllinputfreq = 0U;
1239 uint32_t pllsource = 0U;
1240
1241 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN
1242 48M Domain clock = PLL_VCO / PLLQ
1243 */
1244 pllsource = LL_RCC_PLL_GetMainSource();
1245
1246 switch (pllsource)
1247 {
1248 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1249 pllinputfreq = HSI_VALUE;
1250 break;
1251
1252 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1253 pllinputfreq = HSE_VALUE;
1254 break;
1255
1256 default:
1257 pllinputfreq = HSI_VALUE;
1258 break;
1259 }
1260 return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1261 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
1262 }
1263
1264 #if defined(DSI)
1265 /**
1266 * @brief Return PLL clock frequency used for DSI clock
1267 * @retval PLL clock frequency (in Hz)
1268 */
RCC_PLL_GetFreqDomain_DSI(void)1269 uint32_t RCC_PLL_GetFreqDomain_DSI(void)
1270 {
1271 uint32_t pllinputfreq = 0U;
1272 uint32_t pllsource = 0U;
1273
1274 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1275 DSICLK = PLL_VCO / PLLR
1276 */
1277 pllsource = LL_RCC_PLL_GetMainSource();
1278
1279 switch (pllsource)
1280 {
1281 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1282 pllinputfreq = HSE_VALUE;
1283 break;
1284
1285 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1286 default:
1287 pllinputfreq = HSI_VALUE;
1288 break;
1289 }
1290 return __LL_RCC_CALC_PLLCLK_DSI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1291 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1292 }
1293 #endif /* DSI */
1294
1295 #if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)
1296 /**
1297 * @brief Return PLL clock frequency used for I2S clock
1298 * @retval PLL clock frequency (in Hz)
1299 */
RCC_PLL_GetFreqDomain_I2S(void)1300 uint32_t RCC_PLL_GetFreqDomain_I2S(void)
1301 {
1302 uint32_t pllinputfreq = 0U;
1303 uint32_t pllsource = 0U;
1304
1305 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1306 I2SCLK = PLL_VCO / PLLR
1307 */
1308 pllsource = LL_RCC_PLL_GetMainSource();
1309
1310 switch (pllsource)
1311 {
1312 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1313 pllinputfreq = HSE_VALUE;
1314 break;
1315
1316 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1317 default:
1318 pllinputfreq = HSI_VALUE;
1319 break;
1320 }
1321 return __LL_RCC_CALC_PLLCLK_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1322 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1323 }
1324 #endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */
1325
1326 #if defined(SPDIFRX)
1327 /**
1328 * @brief Return PLL clock frequency used for SPDIFRX clock
1329 * @retval PLL clock frequency (in Hz)
1330 */
RCC_PLL_GetFreqDomain_SPDIFRX(void)1331 uint32_t RCC_PLL_GetFreqDomain_SPDIFRX(void)
1332 {
1333 uint32_t pllinputfreq = 0U;
1334 uint32_t pllsource = 0U;
1335
1336 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1337 SPDIFRXCLK = PLL_VCO / PLLR
1338 */
1339 pllsource = LL_RCC_PLL_GetMainSource();
1340
1341 switch (pllsource)
1342 {
1343 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1344 pllinputfreq = HSE_VALUE;
1345 break;
1346
1347 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1348 default:
1349 pllinputfreq = HSI_VALUE;
1350 break;
1351 }
1352 return __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1353 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1354 }
1355 #endif /* SPDIFRX */
1356
1357 #if defined(RCC_PLLCFGR_PLLR)
1358 #if defined(SAI1)
1359 /**
1360 * @brief Return PLL clock frequency used for SAI clock
1361 * @retval PLL clock frequency (in Hz)
1362 */
RCC_PLL_GetFreqDomain_SAI(void)1363 uint32_t RCC_PLL_GetFreqDomain_SAI(void)
1364 {
1365 uint32_t pllinputfreq = 0U;
1366 uint32_t pllsource = 0U;
1367 uint32_t plloutputfreq = 0U;
1368
1369 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1370 SAICLK = (PLL_VCO / PLLR) / PLLDIVR
1371 or
1372 SAICLK = PLL_VCO / PLLR
1373 */
1374 pllsource = LL_RCC_PLL_GetMainSource();
1375
1376 switch (pllsource)
1377 {
1378 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1379 pllinputfreq = HSE_VALUE;
1380 break;
1381
1382 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1383 default:
1384 pllinputfreq = HSI_VALUE;
1385 break;
1386 }
1387
1388 #if defined(RCC_DCKCFGR_PLLDIVR)
1389 plloutputfreq = __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1390 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR(), LL_RCC_PLL_GetDIVR());
1391 #else
1392 plloutputfreq = __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1393 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1394 #endif /* RCC_DCKCFGR_PLLDIVR */
1395
1396 return plloutputfreq;
1397 }
1398 #endif /* SAI1 */
1399 #endif /* RCC_PLLCFGR_PLLR */
1400
1401 #if defined(RCC_PLLSAI_SUPPORT)
1402 /**
1403 * @brief Return PLLSAI clock frequency used for SAI domain
1404 * @retval PLLSAI clock frequency (in Hz)
1405 */
RCC_PLLSAI_GetFreqDomain_SAI(void)1406 uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void)
1407 {
1408 uint32_t pllinputfreq = 0U;
1409 uint32_t pllsource = 0U;
1410
1411 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN
1412 SAI domain clock = (PLLSAI_VCO / PLLSAIQ) / PLLSAIDIVQ
1413 */
1414 pllsource = LL_RCC_PLL_GetMainSource();
1415
1416 switch (pllsource)
1417 {
1418 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
1419 pllinputfreq = HSI_VALUE;
1420 break;
1421
1422 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
1423 pllinputfreq = HSE_VALUE;
1424 break;
1425
1426 default:
1427 pllinputfreq = HSI_VALUE;
1428 break;
1429 }
1430 return __LL_RCC_CALC_PLLSAI_SAI_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),
1431 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetQ(), LL_RCC_PLLSAI_GetDIVQ());
1432 }
1433
1434 #if defined(RCC_PLLSAICFGR_PLLSAIP)
1435 /**
1436 * @brief Return PLLSAI clock frequency used for 48Mhz domain
1437 * @retval PLLSAI clock frequency (in Hz)
1438 */
RCC_PLLSAI_GetFreqDomain_48M(void)1439 uint32_t RCC_PLLSAI_GetFreqDomain_48M(void)
1440 {
1441 uint32_t pllinputfreq = 0U;
1442 uint32_t pllsource = 0U;
1443
1444 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN
1445 48M Domain clock = PLLSAI_VCO / PLLSAIP
1446 */
1447 pllsource = LL_RCC_PLL_GetMainSource();
1448
1449 switch (pllsource)
1450 {
1451 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
1452 pllinputfreq = HSI_VALUE;
1453 break;
1454
1455 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
1456 pllinputfreq = HSE_VALUE;
1457 break;
1458
1459 default:
1460 pllinputfreq = HSI_VALUE;
1461 break;
1462 }
1463 return __LL_RCC_CALC_PLLSAI_48M_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),
1464 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetP());
1465 }
1466 #endif /* RCC_PLLSAICFGR_PLLSAIP */
1467
1468 #if defined(LTDC)
1469 /**
1470 * @brief Return PLLSAI clock frequency used for LTDC domain
1471 * @retval PLLSAI clock frequency (in Hz)
1472 */
RCC_PLLSAI_GetFreqDomain_LTDC(void)1473 uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void)
1474 {
1475 uint32_t pllinputfreq = 0U;
1476 uint32_t pllsource = 0U;
1477
1478 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN
1479 LTDC Domain clock = (PLLSAI_VCO / PLLSAIR) / PLLSAIDIVR
1480 */
1481 pllsource = LL_RCC_PLL_GetMainSource();
1482
1483 switch (pllsource)
1484 {
1485 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
1486 pllinputfreq = HSI_VALUE;
1487 break;
1488
1489 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
1490 pllinputfreq = HSE_VALUE;
1491 break;
1492
1493 default:
1494 pllinputfreq = HSI_VALUE;
1495 break;
1496 }
1497 return __LL_RCC_CALC_PLLSAI_LTDC_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),
1498 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetR(), LL_RCC_PLLSAI_GetDIVR());
1499 }
1500 #endif /* LTDC */
1501 #endif /* RCC_PLLSAI_SUPPORT */
1502
1503 #if defined(RCC_PLLI2S_SUPPORT)
1504 #if defined(SAI1)
1505 /**
1506 * @brief Return PLLI2S clock frequency used for SAI domains
1507 * @retval PLLI2S clock frequency (in Hz)
1508 */
RCC_PLLI2S_GetFreqDomain_SAI(void)1509 uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void)
1510 {
1511 uint32_t plli2sinputfreq = 0;
1512 uint32_t plli2ssource = 0U;
1513 uint32_t plli2soutputfreq = 0U;
1514
1515 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
1516 SAI domain clock = (PLLI2S_VCO / PLLI2SQ) / PLLI2SDIVQ
1517 or
1518 SAI domain clock = (PLLI2S_VCO / PLLI2SR) / PLLI2SDIVR
1519 */
1520 plli2ssource = LL_RCC_PLLI2S_GetMainSource();
1521
1522 switch (plli2ssource)
1523 {
1524 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
1525 plli2sinputfreq = HSE_VALUE;
1526 break;
1527
1528 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
1529 case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */
1530 plli2sinputfreq = EXTERNAL_CLOCK_VALUE;
1531 break;
1532 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
1533
1534 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
1535 default:
1536 plli2sinputfreq = HSI_VALUE;
1537 break;
1538 }
1539
1540 #if defined(RCC_DCKCFGR_PLLI2SDIVQ)
1541 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_SAI_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
1542 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ(), LL_RCC_PLLI2S_GetDIVQ());
1543 #else
1544 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_SAI_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
1545 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR(), LL_RCC_PLLI2S_GetDIVR());
1546 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */
1547
1548 return plli2soutputfreq;
1549 }
1550 #endif /* SAI1 */
1551
1552 #if defined(SPDIFRX)
1553 /**
1554 * @brief Return PLLI2S clock frequency used for SPDIFRX domain
1555 * @retval PLLI2S clock frequency (in Hz)
1556 */
RCC_PLLI2S_GetFreqDomain_SPDIFRX(void)1557 uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void)
1558 {
1559 uint32_t pllinputfreq = 0U;
1560 uint32_t pllsource = 0U;
1561
1562 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
1563 SPDIFRX Domain clock = PLLI2S_VCO / PLLI2SP
1564 */
1565 pllsource = LL_RCC_PLLI2S_GetMainSource();
1566
1567 switch (pllsource)
1568 {
1569 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
1570 pllinputfreq = HSE_VALUE;
1571 break;
1572
1573 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
1574 default:
1575 pllinputfreq = HSI_VALUE;
1576 break;
1577 }
1578
1579 return __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLLI2S_GetDivider(),
1580 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetP());
1581 }
1582 #endif /* SPDIFRX */
1583
1584 /**
1585 * @brief Return PLLI2S clock frequency used for I2S domain
1586 * @retval PLLI2S clock frequency (in Hz)
1587 */
RCC_PLLI2S_GetFreqDomain_I2S(void)1588 uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)
1589 {
1590 uint32_t plli2sinputfreq = 0U;
1591 uint32_t plli2ssource = 0U;
1592 uint32_t plli2soutputfreq = 0U;
1593
1594 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
1595 I2S Domain clock = PLLI2S_VCO / PLLI2SR
1596 */
1597 plli2ssource = LL_RCC_PLLI2S_GetMainSource();
1598
1599 switch (plli2ssource)
1600 {
1601 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
1602 plli2sinputfreq = HSE_VALUE;
1603 break;
1604
1605 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
1606 case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */
1607 plli2sinputfreq = EXTERNAL_CLOCK_VALUE;
1608 break;
1609 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
1610
1611 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
1612 default:
1613 plli2sinputfreq = HSI_VALUE;
1614 break;
1615 }
1616
1617 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_I2S_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
1618 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR());
1619
1620 return plli2soutputfreq;
1621 }
1622
1623 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
1624 /**
1625 * @brief Return PLLI2S clock frequency used for 48Mhz domain
1626 * @retval PLLI2S clock frequency (in Hz)
1627 */
RCC_PLLI2S_GetFreqDomain_48M(void)1628 uint32_t RCC_PLLI2S_GetFreqDomain_48M(void)
1629 {
1630 uint32_t plli2sinputfreq = 0U;
1631 uint32_t plli2ssource = 0U;
1632 uint32_t plli2soutputfreq = 0U;
1633
1634 /* PLL48M_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
1635 48M Domain clock = PLLI2S_VCO / PLLI2SQ
1636 */
1637 plli2ssource = LL_RCC_PLLI2S_GetMainSource();
1638
1639 switch (plli2ssource)
1640 {
1641 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
1642 plli2sinputfreq = HSE_VALUE;
1643 break;
1644
1645 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
1646 case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */
1647 plli2sinputfreq = EXTERNAL_CLOCK_VALUE;
1648 break;
1649 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
1650
1651 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
1652 default:
1653 plli2sinputfreq = HSI_VALUE;
1654 break;
1655 }
1656
1657 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_48M_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
1658 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ());
1659
1660 return plli2soutputfreq;
1661 }
1662 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
1663 #endif /* RCC_PLLI2S_SUPPORT */
1664 /**
1665 * @}
1666 */
1667
1668 /**
1669 * @}
1670 */
1671
1672 #endif /* defined(RCC) */
1673
1674 /**
1675 * @}
1676 */
1677
1678 #endif /* USE_FULL_LL_DRIVER */
1679
1680
