1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_fmc.c
4 * @author MCD Application Team
5 * @brief FMC Low Layer HAL module driver.
6 *
7 * This file provides firmware functions to manage the following
8 * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
9 * + Initialization/de-initialization functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 *
13 ******************************************************************************
14 * @attention
15 *
16 * Copyright (c) 2016 STMicroelectronics.
17 * All rights reserved.
18 *
19 * This software is licensed under terms that can be found in the LICENSE file
20 * in the root directory of this software component.
21 * If no LICENSE file comes with this software, it is provided AS-IS.
22 *
23 ******************************************************************************
24 @verbatim
25 ==============================================================================
26 ##### FMC peripheral features #####
27 ==============================================================================
28 [..] The Flexible memory controller (FMC) includes following memory controllers:
29 (+) The NOR/PSRAM memory controller
30 (+) The NAND/PC Card memory controller
31 (+) The Synchronous DRAM (SDRAM) controller
32
33 [..] The FMC functional block makes the interface with synchronous and asynchronous static
34 memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
35 (+) to translate AHB transactions into the appropriate external device protocol
36 (+) to meet the access time requirements of the external memory devices
37
38 [..] All external memories share the addresses, data and control signals with the controller.
39 Each external device is accessed by means of a unique Chip Select. The FMC performs
40 only one access at a time to an external device.
41 The main features of the FMC controller are the following:
42 (+) Interface with static-memory mapped devices including:
43 (++) Static random access memory (SRAM)
44 (++) Read-only memory (ROM)
45 (++) NOR Flash memory/OneNAND Flash memory
46 (++) PSRAM (4 memory banks)
47 (++) 16-bit PC Card compatible devices
48 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
49 data
50 (+) Interface with synchronous DRAM (SDRAM) memories
51 (+) Independent Chip Select control for each memory bank
52 (+) Independent configuration for each memory bank
53
54 @endverbatim
55 ******************************************************************************
56 */
57
58 /* Includes ------------------------------------------------------------------*/
59 #include "stm32f4xx_hal.h"
60
61 /** @addtogroup STM32F4xx_HAL_Driver
62 * @{
63 */
64 #if defined(HAL_NOR_MODULE_ENABLED) || (defined(HAL_NAND_MODULE_ENABLED)) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)\
65 || defined(HAL_SRAM_MODULE_ENABLED)
66
67 /** @defgroup FMC_LL FMC Low Layer
68 * @brief FMC driver modules
69 * @{
70 */
71
72 /* Private typedef -----------------------------------------------------------*/
73 /* Private define ------------------------------------------------------------*/
74
75 /** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants
76 * @{
77 */
78
79 /* ----------------------- FMC registers bit mask --------------------------- */
80
81 #if defined(FMC_Bank1)
82 /* --- BCR Register ---*/
83 /* BCR register clear mask */
84
85 /* --- BTR Register ---*/
86 /* BTR register clear mask */
87 #define BTR_CLEAR_MASK ((uint32_t)(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD |\
88 FMC_BTR1_DATAST | FMC_BTR1_BUSTURN |\
89 FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT |\
90 FMC_BTR1_ACCMOD))
91
92 /* --- BWTR Register ---*/
93 /* BWTR register clear mask */
94 #define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD |\
95 FMC_BWTR1_DATAST | FMC_BWTR1_BUSTURN |\
96 FMC_BWTR1_ACCMOD))
97 #endif /* FMC_Bank1 */
98 #if defined(FMC_Bank3) || defined(FMC_Bank2_3)
99
100 #if defined (FMC_PCR_PWAITEN)
101 /* --- PCR Register ---*/
102 /* PCR register clear mask */
103 #define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | \
104 FMC_PCR_PTYP | FMC_PCR_PWID | \
105 FMC_PCR_ECCEN | FMC_PCR_TCLR | \
106 FMC_PCR_TAR | FMC_PCR_ECCPS))
107 /* --- PMEM Register ---*/
108 /* PMEM register clear mask */
109 #define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET2 | FMC_PMEM_MEMWAIT2 |\
110 FMC_PMEM_MEMHOLD2 | FMC_PMEM_MEMHIZ2))
111
112 /* --- PATT Register ---*/
113 /* PATT register clear mask */
114 #define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET2 | FMC_PATT_ATTWAIT2 |\
115 FMC_PATT_ATTHOLD2 | FMC_PATT_ATTHIZ2))
116 #else
117 /* --- PCR Register ---*/
118 /* PCR register clear mask */
119 #define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR2_PWAITEN | FMC_PCR2_PBKEN | \
120 FMC_PCR2_PTYP | FMC_PCR2_PWID | \
121 FMC_PCR2_ECCEN | FMC_PCR2_TCLR | \
122 FMC_PCR2_TAR | FMC_PCR2_ECCPS))
123 /* --- PMEM Register ---*/
124 /* PMEM register clear mask */
125 #define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM2_MEMSET2 | FMC_PMEM2_MEMWAIT2 |\
126 FMC_PMEM2_MEMHOLD2 | FMC_PMEM2_MEMHIZ2))
127
128 /* --- PATT Register ---*/
129 /* PATT register clear mask */
130 #define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT2_ATTSET2 | FMC_PATT2_ATTWAIT2 |\
131 FMC_PATT2_ATTHOLD2 | FMC_PATT2_ATTHIZ2))
132
133 #endif /* FMC_PCR_PWAITEN */
134 #endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
135 #if defined(FMC_Bank4)
136 /* --- PCR Register ---*/
137 /* PCR register clear mask */
138 #define PCR4_CLEAR_MASK ((uint32_t)(FMC_PCR4_PWAITEN | FMC_PCR4_PBKEN | \
139 FMC_PCR4_PTYP | FMC_PCR4_PWID | \
140 FMC_PCR4_ECCEN | FMC_PCR4_TCLR | \
141 FMC_PCR4_TAR | FMC_PCR4_ECCPS))
142 /* --- PMEM Register ---*/
143 /* PMEM register clear mask */
144 #define PMEM4_CLEAR_MASK ((uint32_t)(FMC_PMEM4_MEMSET4 | FMC_PMEM4_MEMWAIT4 |\
145 FMC_PMEM4_MEMHOLD4 | FMC_PMEM4_MEMHIZ4))
146
147 /* --- PATT Register ---*/
148 /* PATT register clear mask */
149 #define PATT4_CLEAR_MASK ((uint32_t)(FMC_PATT4_ATTSET4 | FMC_PATT4_ATTWAIT4 |\
150 FMC_PATT4_ATTHOLD4 | FMC_PATT4_ATTHIZ4))
151
152 /* --- PIO4 Register ---*/
153 /* PIO4 register clear mask */
154 #define PIO4_CLEAR_MASK ((uint32_t)(FMC_PIO4_IOSET4 | FMC_PIO4_IOWAIT4 | \
155 FMC_PIO4_IOHOLD4 | FMC_PIO4_IOHIZ4))
156
157 #endif /* FMC_Bank4 */
158 #if defined(FMC_Bank5_6)
159
160 /* --- SDCR Register ---*/
161 /* SDCR register clear mask */
162 #define SDCR_CLEAR_MASK ((uint32_t)(FMC_SDCR1_NC | FMC_SDCR1_NR | \
163 FMC_SDCR1_MWID | FMC_SDCR1_NB | \
164 FMC_SDCR1_CAS | FMC_SDCR1_WP | \
165 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | \
166 FMC_SDCR1_RPIPE))
167
168 /* --- SDTR Register ---*/
169 /* SDTR register clear mask */
170 #define SDTR_CLEAR_MASK ((uint32_t)(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | \
171 FMC_SDTR1_TRAS | FMC_SDTR1_TRC | \
172 FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
173 FMC_SDTR1_TRCD))
174 #endif /* FMC_Bank5_6 */
175
176 /**
177 * @}
178 */
179
180 /* Private macro -------------------------------------------------------------*/
181 /* Private variables ---------------------------------------------------------*/
182 /* Private function prototypes -----------------------------------------------*/
183 /* Exported functions --------------------------------------------------------*/
184
185 /** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
186 * @{
187 */
188
189 #if defined(FMC_Bank1)
190
191 /** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions
192 * @brief NORSRAM Controller functions
193 *
194 @verbatim
195 ==============================================================================
196 ##### How to use NORSRAM device driver #####
197 ==============================================================================
198
199 [..]
200 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
201 to run the NORSRAM external devices.
202
203 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
204 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
205 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
206 (+) FMC NORSRAM bank extended timing configuration using the function
207 FMC_NORSRAM_Extended_Timing_Init()
208 (+) FMC NORSRAM bank enable/disable write operation using the functions
209 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
210
211 @endverbatim
212 * @{
213 */
214
215 /** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
216 * @brief Initialization and Configuration functions
217 *
218 @verbatim
219 ==============================================================================
220 ##### Initialization and de_initialization functions #####
221 ==============================================================================
222 [..]
223 This section provides functions allowing to:
224 (+) Initialize and configure the FMC NORSRAM interface
225 (+) De-initialize the FMC NORSRAM interface
226 (+) Configure the FMC clock and associated GPIOs
227
228 @endverbatim
229 * @{
230 */
231
232 /**
233 * @brief Initialize the FMC_NORSRAM device according to the specified
234 * control parameters in the FMC_NORSRAM_InitTypeDef
235 * @param Device Pointer to NORSRAM device instance
236 * @param Init Pointer to NORSRAM Initialization structure
237 * @retval HAL status
238 */
FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef * Device,FMC_NORSRAM_InitTypeDef * Init)239 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
240 FMC_NORSRAM_InitTypeDef *Init)
241 {
242 uint32_t flashaccess;
243 uint32_t btcr_reg;
244 uint32_t mask;
245
246 /* Check the parameters */
247 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
248 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
249 assert_param(IS_FMC_MUX(Init->DataAddressMux));
250 assert_param(IS_FMC_MEMORY(Init->MemoryType));
251 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
252 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
253 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
254 #if defined(FMC_BCR1_WRAPMOD)
255 assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
256 #endif /* FMC_BCR1_WRAPMOD */
257 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
258 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
259 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
260 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
261 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
262 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
263 #if defined(FMC_BCR1_CCLKEN)
264 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
265 #endif
266 #if defined(FMC_BCR1_WFDIS)
267 assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
268 #endif /* FMC_BCR1_WFDIS */
269 assert_param(IS_FMC_PAGESIZE(Init->PageSize));
270
271 /* Disable NORSRAM Device */
272 __FMC_NORSRAM_DISABLE(Device, Init->NSBank);
273
274 /* Set NORSRAM device control parameters */
275 if (Init->MemoryType == FMC_MEMORY_TYPE_NOR)
276 {
277 flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE;
278 }
279 else
280 {
281 flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE;
282 }
283
284 btcr_reg = (flashaccess | \
285 Init->DataAddressMux | \
286 Init->MemoryType | \
287 Init->MemoryDataWidth | \
288 Init->BurstAccessMode | \
289 Init->WaitSignalPolarity | \
290 Init->WaitSignalActive | \
291 Init->WriteOperation | \
292 Init->WaitSignal | \
293 Init->ExtendedMode | \
294 Init->AsynchronousWait | \
295 Init->WriteBurst);
296
297 #if defined(FMC_BCR1_WRAPMOD)
298 btcr_reg |= Init->WrapMode;
299 #endif /* FMC_BCR1_WRAPMOD */
300 #if defined(FMC_BCR1_CCLKEN)
301 btcr_reg |= Init->ContinuousClock;
302 #endif /* FMC_BCR1_CCLKEN */
303 #if defined(FMC_BCR1_WFDIS)
304 btcr_reg |= Init->WriteFifo;
305 #endif /* FMC_BCR1_WFDIS */
306 btcr_reg |= Init->PageSize;
307
308 mask = (FMC_BCR1_MBKEN |
309 FMC_BCR1_MUXEN |
310 FMC_BCR1_MTYP |
311 FMC_BCR1_MWID |
312 FMC_BCR1_FACCEN |
313 FMC_BCR1_BURSTEN |
314 FMC_BCR1_WAITPOL |
315 FMC_BCR1_WAITCFG |
316 FMC_BCR1_WREN |
317 FMC_BCR1_WAITEN |
318 FMC_BCR1_EXTMOD |
319 FMC_BCR1_ASYNCWAIT |
320 FMC_BCR1_CBURSTRW);
321
322 #if defined(FMC_BCR1_WRAPMOD)
323 mask |= FMC_BCR1_WRAPMOD;
324 #endif /* FMC_BCR1_WRAPMOD */
325 #if defined(FMC_BCR1_CCLKEN)
326 mask |= FMC_BCR1_CCLKEN;
327 #endif
328 #if defined(FMC_BCR1_WFDIS)
329 mask |= FMC_BCR1_WFDIS;
330 #endif /* FMC_BCR1_WFDIS */
331 mask |= FMC_BCR1_CPSIZE;
332
333 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
334
335 #if defined(FMC_BCR1_CCLKEN)
336 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
337 if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
338 {
339 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);
340 }
341 #endif
342 #if defined(FMC_BCR1_WFDIS)
343
344 if (Init->NSBank != FMC_NORSRAM_BANK1)
345 {
346 /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */
347 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));
348 }
349 #endif /* FMC_BCR1_WFDIS */
350
351 return HAL_OK;
352 }
353
354 /**
355 * @brief DeInitialize the FMC_NORSRAM peripheral
356 * @param Device Pointer to NORSRAM device instance
357 * @param ExDevice Pointer to NORSRAM extended mode device instance
358 * @param Bank NORSRAM bank number
359 * @retval HAL status
360 */
FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef * Device,FMC_NORSRAM_EXTENDED_TypeDef * ExDevice,uint32_t Bank)361 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
362 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
363 {
364 /* Check the parameters */
365 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
366 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
367 assert_param(IS_FMC_NORSRAM_BANK(Bank));
368
369 /* Disable the FMC_NORSRAM device */
370 __FMC_NORSRAM_DISABLE(Device, Bank);
371
372 /* De-initialize the FMC_NORSRAM device */
373 /* FMC_NORSRAM_BANK1 */
374 if (Bank == FMC_NORSRAM_BANK1)
375 {
376 Device->BTCR[Bank] = 0x000030DBU;
377 }
378 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
379 else
380 {
381 Device->BTCR[Bank] = 0x000030D2U;
382 }
383
384 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
385 ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
386
387 return HAL_OK;
388 }
389
390 /**
391 * @brief Initialize the FMC_NORSRAM Timing according to the specified
392 * parameters in the FMC_NORSRAM_TimingTypeDef
393 * @param Device Pointer to NORSRAM device instance
394 * @param Timing Pointer to NORSRAM Timing structure
395 * @param Bank NORSRAM bank number
396 * @retval HAL status
397 */
FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef * Device,FMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank)398 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
399 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
400 {
401 #if defined(FMC_BCR1_CCLKEN)
402 uint32_t tmpr;
403 #endif
404
405 /* Check the parameters */
406 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
407 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
408 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
409 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
410 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
411 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
412 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
413 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
414 assert_param(IS_FMC_NORSRAM_BANK(Bank));
415
416 /* Set FMC_NORSRAM device timing parameters */
417 MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime |
418 ((Timing->AddressHoldTime) << FMC_BTR1_ADDHLD_Pos) |
419 ((Timing->DataSetupTime) << FMC_BTR1_DATAST_Pos) |
420 ((Timing->BusTurnAroundDuration) << FMC_BTR1_BUSTURN_Pos) |
421 (((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos) |
422 (((Timing->DataLatency) - 2U) << FMC_BTR1_DATLAT_Pos) |
423 (Timing->AccessMode)));
424
425 #if defined(FMC_BCR1_CCLKEN)
426 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
427 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
428 {
429 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTR1_CLKDIV_Pos));
430 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos);
431 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTR1_CLKDIV, tmpr);
432 }
433
434 #endif
435 return HAL_OK;
436 }
437
438 /**
439 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
440 * parameters in the FMC_NORSRAM_TimingTypeDef
441 * @param Device Pointer to NORSRAM device instance
442 * @param Timing Pointer to NORSRAM Timing structure
443 * @param Bank NORSRAM bank number
444 * @param ExtendedMode FMC Extended Mode
445 * This parameter can be one of the following values:
446 * @arg FMC_EXTENDED_MODE_DISABLE
447 * @arg FMC_EXTENDED_MODE_ENABLE
448 * @retval HAL status
449 */
FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef * Device,FMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank,uint32_t ExtendedMode)450 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
451 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
452 uint32_t ExtendedMode)
453 {
454 /* Check the parameters */
455 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
456
457 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
458 if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
459 {
460 /* Check the parameters */
461 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
462 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
463 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
464 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
465 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
466 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
467 assert_param(IS_FMC_NORSRAM_BANK(Bank));
468
469 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
470 MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime |
471 ((Timing->AddressHoldTime) << FMC_BWTR1_ADDHLD_Pos) |
472 ((Timing->DataSetupTime) << FMC_BWTR1_DATAST_Pos) |
473 Timing->AccessMode |
474 ((Timing->BusTurnAroundDuration) << FMC_BWTR1_BUSTURN_Pos)));
475 }
476 else
477 {
478 Device->BWTR[Bank] = 0x0FFFFFFFU;
479 }
480
481 return HAL_OK;
482 }
483 /**
484 * @}
485 */
486
487 /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
488 * @brief management functions
489 *
490 @verbatim
491 ==============================================================================
492 ##### FMC_NORSRAM Control functions #####
493 ==============================================================================
494 [..]
495 This subsection provides a set of functions allowing to control dynamically
496 the FMC NORSRAM interface.
497
498 @endverbatim
499 * @{
500 */
501
502 /**
503 * @brief Enables dynamically FMC_NORSRAM write operation.
504 * @param Device Pointer to NORSRAM device instance
505 * @param Bank NORSRAM bank number
506 * @retval HAL status
507 */
FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef * Device,uint32_t Bank)508 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
509 {
510 /* Check the parameters */
511 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
512 assert_param(IS_FMC_NORSRAM_BANK(Bank));
513
514 /* Enable write operation */
515 SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
516
517 return HAL_OK;
518 }
519
520 /**
521 * @brief Disables dynamically FMC_NORSRAM write operation.
522 * @param Device Pointer to NORSRAM device instance
523 * @param Bank NORSRAM bank number
524 * @retval HAL status
525 */
FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef * Device,uint32_t Bank)526 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
527 {
528 /* Check the parameters */
529 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
530 assert_param(IS_FMC_NORSRAM_BANK(Bank));
531
532 /* Disable write operation */
533 CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
534
535 return HAL_OK;
536 }
537
538 /**
539 * @}
540 */
541
542 /**
543 * @}
544 */
545 #endif /* FMC_Bank1 */
546
547 #if defined(FMC_Bank3) || defined(FMC_Bank2_3)
548
549 /** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions
550 * @brief NAND Controller functions
551 *
552 @verbatim
553 ==============================================================================
554 ##### How to use NAND device driver #####
555 ==============================================================================
556 [..]
557 This driver contains a set of APIs to interface with the FMC NAND banks in order
558 to run the NAND external devices.
559
560 (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
561 (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
562 (+) FMC NAND bank common space timing configuration using the function
563 FMC_NAND_CommonSpace_Timing_Init()
564 (+) FMC NAND bank attribute space timing configuration using the function
565 FMC_NAND_AttributeSpace_Timing_Init()
566 (+) FMC NAND bank enable/disable ECC correction feature using the functions
567 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
568 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
569
570 @endverbatim
571 * @{
572 */
573
574 /** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
575 * @brief Initialization and Configuration functions
576 *
577 @verbatim
578 ==============================================================================
579 ##### Initialization and de_initialization functions #####
580 ==============================================================================
581 [..]
582 This section provides functions allowing to:
583 (+) Initialize and configure the FMC NAND interface
584 (+) De-initialize the FMC NAND interface
585 (+) Configure the FMC clock and associated GPIOs
586
587 @endverbatim
588 * @{
589 */
590
591 /**
592 * @brief Initializes the FMC_NAND device according to the specified
593 * control parameters in the FMC_NAND_HandleTypeDef
594 * @param Device Pointer to NAND device instance
595 * @param Init Pointer to NAND Initialization structure
596 * @retval HAL status
597 */
FMC_NAND_Init(FMC_NAND_TypeDef * Device,FMC_NAND_InitTypeDef * Init)598 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
599 {
600 /* Check the parameters */
601 assert_param(IS_FMC_NAND_DEVICE(Device));
602 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
603 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
604 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
605 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
606 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
607 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
608 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
609
610 #if defined(FMC_Bank2_3)
611 /* Set NAND device control parameters */
612 if (Init->NandBank == FMC_NAND_BANK2)
613 {
614 /* NAND bank 2 registers configuration */
615 MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature |
616 FMC_PCR_MEMORY_TYPE_NAND |
617 Init->MemoryDataWidth |
618 Init->EccComputation |
619 Init->ECCPageSize |
620 ((Init->TCLRSetupTime) << FMC_PCR2_TCLR_Pos) |
621 ((Init->TARSetupTime) << FMC_PCR2_TAR_Pos)));
622 }
623 else
624 {
625 /* NAND bank 3 registers configuration */
626 MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature |
627 FMC_PCR_MEMORY_TYPE_NAND |
628 Init->MemoryDataWidth |
629 Init->EccComputation |
630 Init->ECCPageSize |
631 ((Init->TCLRSetupTime) << FMC_PCR2_TCLR_Pos) |
632 ((Init->TARSetupTime) << FMC_PCR2_TAR_Pos)));
633 }
634 #else
635 /* NAND bank 3 registers configuration */
636 MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature |
637 FMC_PCR_MEMORY_TYPE_NAND |
638 Init->MemoryDataWidth |
639 Init->EccComputation |
640 Init->ECCPageSize |
641 ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos) |
642 ((Init->TARSetupTime) << FMC_PCR_TAR_Pos)));
643 #endif
644
645 return HAL_OK;
646 }
647
648 /**
649 * @brief Initializes the FMC_NAND Common space Timing according to the specified
650 * parameters in the FMC_NAND_PCC_TimingTypeDef
651 * @param Device Pointer to NAND device instance
652 * @param Timing Pointer to NAND timing structure
653 * @param Bank NAND bank number
654 * @retval HAL status
655 */
FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef * Device,FMC_NAND_PCC_TimingTypeDef * Timing,uint32_t Bank)656 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
657 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
658 {
659 /* Check the parameters */
660 assert_param(IS_FMC_NAND_DEVICE(Device));
661 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
662 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
663 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
664 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
665 assert_param(IS_FMC_NAND_BANK(Bank));
666
667 #if defined(FMC_Bank2_3)
668 /* Set FMC_NAND device timing parameters */
669 if (Bank == FMC_NAND_BANK2)
670 {
671 /* NAND bank 2 registers configuration */
672 MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime |
673 ((Timing->WaitSetupTime) << FMC_PMEM2_MEMWAIT2_Pos) |
674 ((Timing->HoldSetupTime) << FMC_PMEM2_MEMHOLD2_Pos) |
675 ((Timing->HiZSetupTime) << FMC_PMEM2_MEMHIZ2_Pos)));
676 }
677 else
678 {
679 /* NAND bank 3 registers configuration */
680 MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime |
681 ((Timing->WaitSetupTime) << FMC_PMEM2_MEMWAIT2_Pos) |
682 ((Timing->HoldSetupTime) << FMC_PMEM2_MEMHOLD2_Pos) |
683 ((Timing->HiZSetupTime) << FMC_PMEM2_MEMHIZ2_Pos)));
684 }
685 #else
686 /* Prevent unused argument(s) compilation warning if no assert_param check */
687 UNUSED(Bank);
688
689 /* NAND bank 3 registers configuration */
690 MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime |
691 ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT2_Pos) |
692 ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD2_Pos) |
693 ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ2_Pos)));
694 #endif
695
696 return HAL_OK;
697 }
698
699 /**
700 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
701 * parameters in the FMC_NAND_PCC_TimingTypeDef
702 * @param Device Pointer to NAND device instance
703 * @param Timing Pointer to NAND timing structure
704 * @param Bank NAND bank number
705 * @retval HAL status
706 */
FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef * Device,FMC_NAND_PCC_TimingTypeDef * Timing,uint32_t Bank)707 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
708 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
709 {
710 /* Check the parameters */
711 assert_param(IS_FMC_NAND_DEVICE(Device));
712 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
713 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
714 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
715 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
716 assert_param(IS_FMC_NAND_BANK(Bank));
717
718 #if defined(FMC_Bank2_3)
719 /* Set FMC_NAND device timing parameters */
720 if (Bank == FMC_NAND_BANK2)
721 {
722 /* NAND bank 2 registers configuration */
723 MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime |
724 ((Timing->WaitSetupTime) << FMC_PATT2_ATTWAIT2_Pos) |
725 ((Timing->HoldSetupTime) << FMC_PATT2_ATTHOLD2_Pos) |
726 ((Timing->HiZSetupTime) << FMC_PATT2_ATTHIZ2_Pos)));
727 }
728 else
729 {
730 /* NAND bank 3 registers configuration */
731 MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime |
732 ((Timing->WaitSetupTime) << FMC_PATT2_ATTWAIT2_Pos) |
733 ((Timing->HoldSetupTime) << FMC_PATT2_ATTHOLD2_Pos) |
734 ((Timing->HiZSetupTime) << FMC_PATT2_ATTHIZ2_Pos)));
735 }
736 #else
737 /* Prevent unused argument(s) compilation warning if no assert_param check */
738 UNUSED(Bank);
739
740 /* NAND bank 3 registers configuration */
741 MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime |
742 ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT2_Pos) |
743 ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD2_Pos) |
744 ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ2_Pos)));
745 #endif
746
747 return HAL_OK;
748 }
749
750 /**
751 * @brief DeInitializes the FMC_NAND device
752 * @param Device Pointer to NAND device instance
753 * @param Bank NAND bank number
754 * @retval HAL status
755 */
FMC_NAND_DeInit(FMC_NAND_TypeDef * Device,uint32_t Bank)756 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
757 {
758 /* Check the parameters */
759 assert_param(IS_FMC_NAND_DEVICE(Device));
760 assert_param(IS_FMC_NAND_BANK(Bank));
761
762 /* Disable the NAND Bank */
763 __FMC_NAND_DISABLE(Device, Bank);
764
765 /* De-initialize the NAND Bank */
766 #if defined(FMC_Bank2_3)
767 if (Bank == FMC_NAND_BANK2)
768 {
769 /* Set the FMC_NAND_BANK2 registers to their reset values */
770 WRITE_REG(Device->PCR2, 0x00000018U);
771 WRITE_REG(Device->SR2, 0x00000040U);
772 WRITE_REG(Device->PMEM2, 0xFCFCFCFCU);
773 WRITE_REG(Device->PATT2, 0xFCFCFCFCU);
774 }
775 /* FMC_Bank3_NAND */
776 else
777 {
778 /* Set the FMC_NAND_BANK3 registers to their reset values */
779 WRITE_REG(Device->PCR3, 0x00000018U);
780 WRITE_REG(Device->SR3, 0x00000040U);
781 WRITE_REG(Device->PMEM3, 0xFCFCFCFCU);
782 WRITE_REG(Device->PATT3, 0xFCFCFCFCU);
783 }
784 #else
785 /* Prevent unused argument(s) compilation warning if no assert_param check */
786 UNUSED(Bank);
787
788 /* Set the FMC_NAND_BANK3 registers to their reset values */
789 WRITE_REG(Device->PCR, 0x00000018U);
790 WRITE_REG(Device->SR, 0x00000040U);
791 WRITE_REG(Device->PMEM, 0xFCFCFCFCU);
792 WRITE_REG(Device->PATT, 0xFCFCFCFCU);
793 #endif
794
795 return HAL_OK;
796 }
797
798 /**
799 * @}
800 */
801
802 /** @defgroup HAL_FMC_NAND_Group2 Peripheral Control functions
803 * @brief management functions
804 *
805 @verbatim
806 ==============================================================================
807 ##### FMC_NAND Control functions #####
808 ==============================================================================
809 [..]
810 This subsection provides a set of functions allowing to control dynamically
811 the FMC NAND interface.
812
813 @endverbatim
814 * @{
815 */
816
817
818 /**
819 * @brief Enables dynamically FMC_NAND ECC feature.
820 * @param Device Pointer to NAND device instance
821 * @param Bank NAND bank number
822 * @retval HAL status
823 */
FMC_NAND_ECC_Enable(FMC_NAND_TypeDef * Device,uint32_t Bank)824 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
825 {
826 /* Check the parameters */
827 assert_param(IS_FMC_NAND_DEVICE(Device));
828 assert_param(IS_FMC_NAND_BANK(Bank));
829
830 /* Enable ECC feature */
831 #if defined(FMC_Bank2_3)
832 if (Bank == FMC_NAND_BANK2)
833 {
834 SET_BIT(Device->PCR2, FMC_PCR2_ECCEN);
835 }
836 else
837 {
838 SET_BIT(Device->PCR3, FMC_PCR2_ECCEN);
839 }
840 #else
841 /* Prevent unused argument(s) compilation warning if no assert_param check */
842 UNUSED(Bank);
843
844 SET_BIT(Device->PCR, FMC_PCR_ECCEN);
845 #endif
846
847 return HAL_OK;
848 }
849
850
851 /**
852 * @brief Disables dynamically FMC_NAND ECC feature.
853 * @param Device Pointer to NAND device instance
854 * @param Bank NAND bank number
855 * @retval HAL status
856 */
FMC_NAND_ECC_Disable(FMC_NAND_TypeDef * Device,uint32_t Bank)857 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
858 {
859 /* Check the parameters */
860 assert_param(IS_FMC_NAND_DEVICE(Device));
861 assert_param(IS_FMC_NAND_BANK(Bank));
862
863 /* Disable ECC feature */
864 #if defined(FMC_Bank2_3)
865 if (Bank == FMC_NAND_BANK2)
866 {
867 CLEAR_BIT(Device->PCR2, FMC_PCR2_ECCEN);
868 }
869 else
870 {
871 CLEAR_BIT(Device->PCR3, FMC_PCR2_ECCEN);
872 }
873 #else
874 /* Prevent unused argument(s) compilation warning if no assert_param check */
875 UNUSED(Bank);
876
877 CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);
878 #endif
879
880 return HAL_OK;
881 }
882
883 /**
884 * @brief Disables dynamically FMC_NAND ECC feature.
885 * @param Device Pointer to NAND device instance
886 * @param ECCval Pointer to ECC value
887 * @param Bank NAND bank number
888 * @param Timeout Timeout wait value
889 * @retval HAL status
890 */
FMC_NAND_GetECC(FMC_NAND_TypeDef * Device,uint32_t * ECCval,uint32_t Bank,uint32_t Timeout)891 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
892 uint32_t Timeout)
893 {
894 uint32_t tickstart;
895
896 /* Check the parameters */
897 assert_param(IS_FMC_NAND_DEVICE(Device));
898 assert_param(IS_FMC_NAND_BANK(Bank));
899
900 /* Get tick */
901 tickstart = HAL_GetTick();
902
903 /* Wait until FIFO is empty */
904 while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
905 {
906 /* Check for the Timeout */
907 if (Timeout != HAL_MAX_DELAY)
908 {
909 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
910 {
911 return HAL_TIMEOUT;
912 }
913 }
914 }
915
916 #if defined(FMC_Bank2_3)
917 if (Bank == FMC_NAND_BANK2)
918 {
919 /* Get the ECCR2 register value */
920 *ECCval = (uint32_t)Device->ECCR2;
921 }
922 else
923 {
924 /* Get the ECCR3 register value */
925 *ECCval = (uint32_t)Device->ECCR3;
926 }
927 #else
928 /* Prevent unused argument(s) compilation warning if no assert_param check */
929 UNUSED(Bank);
930
931 /* Get the ECCR register value */
932 *ECCval = (uint32_t)Device->ECCR;
933 #endif
934
935 return HAL_OK;
936 }
937
938 /**
939 * @}
940 */
941 #endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
942
943 #if defined(FMC_Bank4)
944
945 /** @addtogroup FMC_LL_PCCARD
946 * @brief PCCARD Controller functions
947 *
948 @verbatim
949 ==============================================================================
950 ##### How to use PCCARD device driver #####
951 ==============================================================================
952 [..]
953 This driver contains a set of APIs to interface with the FMC PCCARD bank in order
954 to run the PCCARD/compact flash external devices.
955
956 (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit()
957 (+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init()
958 (+) FMC PCCARD bank common space timing configuration using the function
959 FMC_PCCARD_CommonSpace_Timing_Init()
960 (+) FMC PCCARD bank attribute space timing configuration using the function
961 FMC_PCCARD_AttributeSpace_Timing_Init()
962 (+) FMC PCCARD bank IO space timing configuration using the function
963 FMC_PCCARD_IOSpace_Timing_Init()
964 @endverbatim
965 * @{
966 */
967
968 /** @addtogroup FMC_LL_PCCARD_Private_Functions_Group1
969 * @brief Initialization and Configuration functions
970 *
971 @verbatim
972 ==============================================================================
973 ##### Initialization and de_initialization functions #####
974 ==============================================================================
975 [..]
976 This section provides functions allowing to:
977 (+) Initialize and configure the FMC PCCARD interface
978 (+) De-initialize the FMC PCCARD interface
979 (+) Configure the FMC clock and associated GPIOs
980
981 @endverbatim
982 * @{
983 */
984
985 /**
986 * @brief Initializes the FMC_PCCARD device according to the specified
987 * control parameters in the FMC_PCCARD_HandleTypeDef
988 * @param Device Pointer to PCCARD device instance
989 * @param Init Pointer to PCCARD Initialization structure
990 * @retval HAL status
991 */
FMC_PCCARD_Init(FMC_PCCARD_TypeDef * Device,FMC_PCCARD_InitTypeDef * Init)992 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init)
993 {
994 /* Check the parameters */
995 assert_param(IS_FMC_PCCARD_DEVICE(Device));
996 #if defined(FMC_Bank3) || defined(FMC_Bank2_3)
997 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
998 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
999 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
1000 #endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
1001
1002 /* Set FMC_PCCARD device control parameters */
1003 MODIFY_REG(Device->PCR4,
1004 (FMC_PCR4_PTYP |
1005 FMC_PCR4_PWAITEN |
1006 FMC_PCR4_PWID |
1007 FMC_PCR4_TCLR |
1008 FMC_PCR4_TAR),
1009 (FMC_PCR_MEMORY_TYPE_PCCARD |
1010 Init->Waitfeature |
1011 FMC_NAND_PCC_MEM_BUS_WIDTH_16 |
1012 (Init->TCLRSetupTime << FMC_PCR4_TCLR_Pos) |
1013 (Init->TARSetupTime << FMC_PCR4_TAR_Pos)));
1014
1015 return HAL_OK;
1016 }
1017
1018 /**
1019 * @brief Initializes the FMC_PCCARD Common space Timing according to the specified
1020 * parameters in the FMC_NAND_PCC_TimingTypeDef
1021 * @param Device Pointer to PCCARD device instance
1022 * @param Timing Pointer to PCCARD timing structure
1023 * @retval HAL status
1024 */
FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef * Device,FMC_NAND_PCC_TimingTypeDef * Timing)1025 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
1026 FMC_NAND_PCC_TimingTypeDef *Timing)
1027 {
1028 /* Check the parameters */
1029 assert_param(IS_FMC_PCCARD_DEVICE(Device));
1030 #if defined(FMC_Bank3) || defined(FMC_Bank2_3)
1031 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
1032 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
1033 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
1034 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
1035 #endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
1036
1037 /* Set PCCARD timing parameters */
1038 MODIFY_REG(Device->PMEM4, PMEM4_CLEAR_MASK,
1039 (Timing->SetupTime |
1040 ((Timing->WaitSetupTime) << FMC_PMEM4_MEMWAIT4_Pos) |
1041 ((Timing->HoldSetupTime) << FMC_PMEM4_MEMHOLD4_Pos) |
1042 ((Timing->HiZSetupTime) << FMC_PMEM4_MEMHIZ4_Pos)));
1043
1044 return HAL_OK;
1045 }
1046
1047 /**
1048 * @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified
1049 * parameters in the FMC_NAND_PCC_TimingTypeDef
1050 * @param Device Pointer to PCCARD device instance
1051 * @param Timing Pointer to PCCARD timing structure
1052 * @retval HAL status
1053 */
FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef * Device,FMC_NAND_PCC_TimingTypeDef * Timing)1054 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
1055 FMC_NAND_PCC_TimingTypeDef *Timing)
1056 {
1057 /* Check the parameters */
1058 assert_param(IS_FMC_PCCARD_DEVICE(Device));
1059 #if defined(FMC_Bank3) || defined(FMC_Bank2_3)
1060 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
1061 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
1062 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
1063 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
1064 #endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
1065
1066 /* Set PCCARD timing parameters */
1067 MODIFY_REG(Device->PATT4, PATT4_CLEAR_MASK,
1068 (Timing->SetupTime |
1069 ((Timing->WaitSetupTime) << FMC_PATT4_ATTWAIT4_Pos) |
1070 ((Timing->HoldSetupTime) << FMC_PATT4_ATTHOLD4_Pos) |
1071 ((Timing->HiZSetupTime) << FMC_PATT4_ATTHIZ4_Pos)));
1072
1073 return HAL_OK;
1074 }
1075
1076 /**
1077 * @brief Initializes the FMC_PCCARD IO space Timing according to the specified
1078 * parameters in the FMC_NAND_PCC_TimingTypeDef
1079 * @param Device Pointer to PCCARD device instance
1080 * @param Timing Pointer to PCCARD timing structure
1081 * @retval HAL status
1082 */
FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef * Device,FMC_NAND_PCC_TimingTypeDef * Timing)1083 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
1084 FMC_NAND_PCC_TimingTypeDef *Timing)
1085 {
1086 /* Check the parameters */
1087 assert_param(IS_FMC_PCCARD_DEVICE(Device));
1088 #if defined(FMC_Bank3) || defined(FMC_Bank2_3)
1089 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
1090 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
1091 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
1092 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
1093 #endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
1094
1095 /* Set FMC_PCCARD device timing parameters */
1096 MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK,
1097 (Timing->SetupTime |
1098 (Timing->WaitSetupTime << FMC_PIO4_IOWAIT4_Pos) |
1099 (Timing->HoldSetupTime << FMC_PIO4_IOHOLD4_Pos) |
1100 (Timing->HiZSetupTime << FMC_PIO4_IOHIZ4_Pos)));
1101
1102 return HAL_OK;
1103 }
1104
1105 /**
1106 * @brief DeInitializes the FMC_PCCARD device
1107 * @param Device Pointer to PCCARD device instance
1108 * @retval HAL status
1109 */
FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef * Device)1110 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
1111 {
1112 /* Check the parameters */
1113 assert_param(IS_FMC_PCCARD_DEVICE(Device));
1114
1115 /* Disable the FMC_PCCARD device */
1116 __FMC_PCCARD_DISABLE(Device);
1117
1118 /* De-initialize the FMC_PCCARD device */
1119 Device->PCR4 = 0x00000018U;
1120 Device->SR4 = 0x00000040U;
1121 Device->PMEM4 = 0xFCFCFCFCU;
1122 Device->PATT4 = 0xFCFCFCFCU;
1123 Device->PIO4 = 0xFCFCFCFCU;
1124
1125 return HAL_OK;
1126 }
1127
1128 /**
1129 * @}
1130 */
1131 #endif /* FMC_Bank4 */
1132
1133 #if defined(FMC_Bank5_6)
1134
1135 /** @defgroup FMC_LL_SDRAM
1136 * @brief SDRAM Controller functions
1137 *
1138 @verbatim
1139 ==============================================================================
1140 ##### How to use SDRAM device driver #####
1141 ==============================================================================
1142 [..]
1143 This driver contains a set of APIs to interface with the FMC SDRAM banks in order
1144 to run the SDRAM external devices.
1145
1146 (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
1147 (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
1148 (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
1149 (+) FMC SDRAM bank enable/disable write operation using the functions
1150 FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
1151 (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
1152
1153 @endverbatim
1154 * @{
1155 */
1156
1157 /** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
1158 * @brief Initialization and Configuration functions
1159 *
1160 @verbatim
1161 ==============================================================================
1162 ##### Initialization and de_initialization functions #####
1163 ==============================================================================
1164 [..]
1165 This section provides functions allowing to:
1166 (+) Initialize and configure the FMC SDRAM interface
1167 (+) De-initialize the FMC SDRAM interface
1168 (+) Configure the FMC clock and associated GPIOs
1169
1170 @endverbatim
1171 * @{
1172 */
1173
1174 /**
1175 * @brief Initializes the FMC_SDRAM device according to the specified
1176 * control parameters in the FMC_SDRAM_InitTypeDef
1177 * @param Device Pointer to SDRAM device instance
1178 * @param Init Pointer to SDRAM Initialization structure
1179 * @retval HAL status
1180 */
FMC_SDRAM_Init(FMC_SDRAM_TypeDef * Device,FMC_SDRAM_InitTypeDef * Init)1181 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
1182 {
1183 /* Check the parameters */
1184 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1185 assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
1186 assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
1187 assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
1188 assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
1189 assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
1190 assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
1191 assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
1192 assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
1193 assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
1194 assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
1195
1196 /* Set SDRAM bank configuration parameters */
1197 if (Init->SDBank == FMC_SDRAM_BANK1)
1198 {
1199 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
1200 SDCR_CLEAR_MASK,
1201 (Init->ColumnBitsNumber |
1202 Init->RowBitsNumber |
1203 Init->MemoryDataWidth |
1204 Init->InternalBankNumber |
1205 Init->CASLatency |
1206 Init->WriteProtection |
1207 Init->SDClockPeriod |
1208 Init->ReadBurst |
1209 Init->ReadPipeDelay));
1210 }
1211 else /* FMC_Bank2_SDRAM */
1212 {
1213 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
1214 FMC_SDCR1_SDCLK |
1215 FMC_SDCR1_RBURST |
1216 FMC_SDCR1_RPIPE,
1217 (Init->SDClockPeriod |
1218 Init->ReadBurst |
1219 Init->ReadPipeDelay));
1220
1221 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2],
1222 SDCR_CLEAR_MASK,
1223 (Init->ColumnBitsNumber |
1224 Init->RowBitsNumber |
1225 Init->MemoryDataWidth |
1226 Init->InternalBankNumber |
1227 Init->CASLatency |
1228 Init->WriteProtection));
1229 }
1230
1231 return HAL_OK;
1232 }
1233
1234
1235 /**
1236 * @brief Initializes the FMC_SDRAM device timing according to the specified
1237 * parameters in the FMC_SDRAM_TimingTypeDef
1238 * @param Device Pointer to SDRAM device instance
1239 * @param Timing Pointer to SDRAM Timing structure
1240 * @param Bank SDRAM bank number
1241 * @retval HAL status
1242 */
FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef * Device,FMC_SDRAM_TimingTypeDef * Timing,uint32_t Bank)1243 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device,
1244 FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
1245 {
1246 /* Check the parameters */
1247 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1248 assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
1249 assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
1250 assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
1251 assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
1252 assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
1253 assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
1254 assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
1255 assert_param(IS_FMC_SDRAM_BANK(Bank));
1256
1257 /* Set SDRAM device timing parameters */
1258 if (Bank == FMC_SDRAM_BANK1)
1259 {
1260 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
1261 SDTR_CLEAR_MASK,
1262 (((Timing->LoadToActiveDelay) - 1U) |
1263 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTR1_TXSR_Pos) |
1264 (((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) |
1265 (((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) |
1266 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) |
1267 (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos) |
1268 (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos)));
1269 }
1270 else /* FMC_Bank2_SDRAM */
1271 {
1272 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
1273 FMC_SDTR1_TRC |
1274 FMC_SDTR1_TRP,
1275 (((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) |
1276 (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos));
1277
1278 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2],
1279 SDTR_CLEAR_MASK,
1280 (((Timing->LoadToActiveDelay) - 1U) |
1281 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTR1_TXSR_Pos) |
1282 (((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) |
1283 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) |
1284 (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos)));
1285 }
1286
1287 return HAL_OK;
1288 }
1289
1290 /**
1291 * @brief DeInitializes the FMC_SDRAM peripheral
1292 * @param Device Pointer to SDRAM device instance
1293 * @retval HAL status
1294 */
FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef * Device,uint32_t Bank)1295 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1296 {
1297 /* Check the parameters */
1298 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1299 assert_param(IS_FMC_SDRAM_BANK(Bank));
1300
1301 /* De-initialize the SDRAM device */
1302 Device->SDCR[Bank] = 0x000002D0U;
1303 Device->SDTR[Bank] = 0x0FFFFFFFU;
1304 Device->SDCMR = 0x00000000U;
1305 Device->SDRTR = 0x00000000U;
1306 Device->SDSR = 0x00000000U;
1307
1308 return HAL_OK;
1309 }
1310
1311 /**
1312 * @}
1313 */
1314
1315 /** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
1316 * @brief management functions
1317 *
1318 @verbatim
1319 ==============================================================================
1320 ##### FMC_SDRAM Control functions #####
1321 ==============================================================================
1322 [..]
1323 This subsection provides a set of functions allowing to control dynamically
1324 the FMC SDRAM interface.
1325
1326 @endverbatim
1327 * @{
1328 */
1329
1330 /**
1331 * @brief Enables dynamically FMC_SDRAM write protection.
1332 * @param Device Pointer to SDRAM device instance
1333 * @param Bank SDRAM bank number
1334 * @retval HAL status
1335 */
FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef * Device,uint32_t Bank)1336 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1337 {
1338 /* Check the parameters */
1339 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1340 assert_param(IS_FMC_SDRAM_BANK(Bank));
1341
1342 /* Enable write protection */
1343 SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
1344
1345 return HAL_OK;
1346 }
1347
1348 /**
1349 * @brief Disables dynamically FMC_SDRAM write protection.
1350 * @param hsdram FMC_SDRAM handle
1351 * @retval HAL status
1352 */
FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef * Device,uint32_t Bank)1353 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1354 {
1355 /* Check the parameters */
1356 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1357 assert_param(IS_FMC_SDRAM_BANK(Bank));
1358
1359 /* Disable write protection */
1360 CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
1361
1362 return HAL_OK;
1363 }
1364
1365 /**
1366 * @brief Send Command to the FMC SDRAM bank
1367 * @param Device Pointer to SDRAM device instance
1368 * @param Command Pointer to SDRAM command structure
1369 * @param Timing Pointer to SDRAM Timing structure
1370 * @param Timeout Timeout wait value
1371 * @retval HAL state
1372 */
FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef * Device,FMC_SDRAM_CommandTypeDef * Command,uint32_t Timeout)1373 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device,
1374 FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
1375 {
1376 uint32_t tickstart = 0U;
1377 /* Check the parameters */
1378 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1379 assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
1380 assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
1381 assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
1382 assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
1383
1384 /* Set command register */
1385 MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC_SDCMR_MRD),
1386 ((Command->CommandMode) | (Command->CommandTarget) |
1387 (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) |
1388 ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos)));
1389 /* Get tick */
1390 tickstart = HAL_GetTick();
1391
1392 /* wait until command is send */
1393 while (HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))
1394 {
1395 /* Check for the Timeout */
1396 if (Timeout != HAL_MAX_DELAY)
1397 {
1398 if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
1399 {
1400 return HAL_TIMEOUT;
1401 }
1402 }
1403 }
1404 return HAL_OK;
1405 }
1406
1407 /**
1408 * @brief Program the SDRAM Memory Refresh rate.
1409 * @param Device Pointer to SDRAM device instance
1410 * @param RefreshRate The SDRAM refresh rate value.
1411 * @retval HAL state
1412 */
FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef * Device,uint32_t RefreshRate)1413 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
1414 {
1415 /* Check the parameters */
1416 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1417 assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
1418
1419 /* Set the refresh rate in command register */
1420 MODIFY_REG(Device->SDRTR, FMC_SDRTR_COUNT, (RefreshRate << FMC_SDRTR_COUNT_Pos));
1421
1422 return HAL_OK;
1423 }
1424
1425 /**
1426 * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.
1427 * @param Device Pointer to SDRAM device instance
1428 * @param AutoRefreshNumber Specifies the auto Refresh number.
1429 * @retval None
1430 */
FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef * Device,uint32_t AutoRefreshNumber)1431 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device,
1432 uint32_t AutoRefreshNumber)
1433 {
1434 /* Check the parameters */
1435 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1436 assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
1437
1438 /* Set the Auto-refresh number in command register */
1439 MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos));
1440
1441 return HAL_OK;
1442 }
1443
1444 /**
1445 * @brief Returns the indicated FMC SDRAM bank mode status.
1446 * @param Device Pointer to SDRAM device instance
1447 * @param Bank Defines the FMC SDRAM bank. This parameter can be
1448 * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
1449 * @retval The FMC SDRAM bank mode status, could be on of the following values:
1450 * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
1451 * FMC_SDRAM_POWER_DOWN_MODE.
1452 */
FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef * Device,uint32_t Bank)1453 uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1454 {
1455 uint32_t tmpreg;
1456
1457 /* Check the parameters */
1458 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1459 assert_param(IS_FMC_SDRAM_BANK(Bank));
1460
1461 /* Get the corresponding bank mode */
1462 if (Bank == FMC_SDRAM_BANK1)
1463 {
1464 tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
1465 }
1466 else
1467 {
1468 tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U);
1469 }
1470
1471 /* Return the mode status */
1472 return tmpreg;
1473 }
1474
1475 /**
1476 * @}
1477 */
1478
1479 /**
1480 * @}
1481 */
1482
1483 #endif /* FMC_Bank5_6 */
1484
1485 /**
1486 * @}
1487 */
1488
1489 /**
1490 * @}
1491 */
1492
1493 #endif /* HAL_NOR_MODULE_ENABLED */
1494 /**
1495 * @}
1496 */
1497 /**
1498 * @}
1499 */
1500
