1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_sdram.c
4 * @author MCD Application Team
5 * @brief SDRAM HAL module driver.
6 * This file provides a generic firmware to drive SDRAM memories mounted
7 * as external device.
8 *
9 ******************************************************************************
10 * @attention
11 *
12 * Copyright (c) 2016 STMicroelectronics.
13 * All rights reserved.
14 *
15 * This software is licensed under terms that can be found in the LICENSE file
16 * in the root directory of this software component.
17 * If no LICENSE file comes with this software, it is provided AS-IS.
18 *
19 ******************************************************************************
20 @verbatim
21 ==============================================================================
22 ##### How to use this driver #####
23 ==============================================================================
24 [..]
25 This driver is a generic layered driver which contains a set of APIs used to
26 control SDRAM memories. It uses the FMC layer functions to interface
27 with SDRAM devices.
28 The following sequence should be followed to configure the FMC to interface
29 with SDRAM memories:
30
31 (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
32 SDRAM_HandleTypeDef hsdram
33
34 (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
35 values of the structure member.
36
37 (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
38 base register instance for NOR or SDRAM device
39
40 (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
41 FMC_SDRAM_TimingTypeDef Timing;
42 and fill its fields with the allowed values of the structure member.
43
44 (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
45 performs the following sequence:
46
47 (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
48 (##) Control register configuration using the FMC SDRAM interface function
49 FMC_SDRAM_Init()
50 (##) Timing register configuration using the FMC SDRAM interface function
51 FMC_SDRAM_Timing_Init()
52 (##) Program the SDRAM external device by applying its initialization sequence
53 according to the device plugged in your hardware. This step is mandatory
54 for accessing the SDRAM device.
55
56 (#) At this stage you can perform read/write accesses from/to the memory connected
57 to the SDRAM Bank. You can perform either polling or DMA transfer using the
58 following APIs:
59 (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
60 (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
61
62 (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
63 HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
64 the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
65 device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
66 structure.
67
68 (#) You can continuously monitor the SDRAM device HAL state by calling the function
69 HAL_SDRAM_GetState()
70
71 *** Callback registration ***
72 =============================================
73 [..]
74 The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS when set to 1
75 allows the user to configure dynamically the driver callbacks.
76
77 Use Functions HAL_SDRAM_RegisterCallback() to register a user callback,
78 it allows to register following callbacks:
79 (+) MspInitCallback : SDRAM MspInit.
80 (+) MspDeInitCallback : SDRAM MspDeInit.
81 This function takes as parameters the HAL peripheral handle, the Callback ID
82 and a pointer to the user callback function.
83
84 Use function HAL_SDRAM_UnRegisterCallback() to reset a callback to the default
85 weak (overridden) function. It allows to reset following callbacks:
86 (+) MspInitCallback : SDRAM MspInit.
87 (+) MspDeInitCallback : SDRAM MspDeInit.
88 This function) takes as parameters the HAL peripheral handle and the Callback ID.
89
90 By default, after the HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET
91 all callbacks are reset to the corresponding legacy weak (overridden) functions.
92 Exception done for MspInit and MspDeInit callbacks that are respectively
93 reset to the legacy weak (overridden) functions in the HAL_SDRAM_Init
94 and HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand).
95 If not, MspInit or MspDeInit are not null, the HAL_SDRAM_Init and HAL_SDRAM_DeInit
96 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
97
98 Callbacks can be registered/unregistered in READY state only.
99 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
100 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
101 during the Init/DeInit.
102 In that case first register the MspInit/MspDeInit user callbacks
103 using HAL_SDRAM_RegisterCallback before calling HAL_SDRAM_DeInit
104 or HAL_SDRAM_Init function.
105
106 When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or
107 not defined, the callback registering feature is not available
108 and weak (overridden) callbacks are used.
109
110 @endverbatim
111 ******************************************************************************
112 */
113
114 /* Includes ------------------------------------------------------------------*/
115 #include "stm32f4xx_hal.h"
116
117 #if defined(FMC_Bank5_6)
118
119 /** @addtogroup STM32F4xx_HAL_Driver
120 * @{
121 */
122
123 #ifdef HAL_SDRAM_MODULE_ENABLED
124
125 /** @defgroup SDRAM SDRAM
126 * @brief SDRAM driver modules
127 * @{
128 */
129
130 /* Private typedef -----------------------------------------------------------*/
131 /* Private define ------------------------------------------------------------*/
132 /* Private macro -------------------------------------------------------------*/
133 /* Private variables ---------------------------------------------------------*/
134 /* Private function prototypes -----------------------------------------------*/
135 /** @addtogroup SDRAM_Private_Functions SDRAM Private Functions
136 * @{
137 */
138 static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma);
139 static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
140 static void SDRAM_DMAError(DMA_HandleTypeDef *hdma);
141 /**
142 * @}
143 */
144
145 /* Exported functions --------------------------------------------------------*/
146 /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
147 * @{
148 */
149
150 /** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions
151 * @brief Initialization and Configuration functions
152 *
153 @verbatim
154 ==============================================================================
155 ##### SDRAM Initialization and de_initialization functions #####
156 ==============================================================================
157 [..]
158 This section provides functions allowing to initialize/de-initialize
159 the SDRAM memory
160
161 @endverbatim
162 * @{
163 */
164
165 /**
166 * @brief Performs the SDRAM device initialization sequence.
167 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
168 * the configuration information for SDRAM module.
169 * @param Timing Pointer to SDRAM control timing structure
170 * @retval HAL status
171 */
HAL_SDRAM_Init(SDRAM_HandleTypeDef * hsdram,FMC_SDRAM_TimingTypeDef * Timing)172 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
173 {
174 /* Check the SDRAM handle parameter */
175 if (hsdram == NULL)
176 {
177 return HAL_ERROR;
178 }
179
180 if (hsdram->State == HAL_SDRAM_STATE_RESET)
181 {
182 /* Allocate lock resource and initialize it */
183 hsdram->Lock = HAL_UNLOCKED;
184 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
185 if (hsdram->MspInitCallback == NULL)
186 {
187 hsdram->MspInitCallback = HAL_SDRAM_MspInit;
188 }
189 hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
190 hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
191 hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
192
193 /* Init the low level hardware */
194 hsdram->MspInitCallback(hsdram);
195 #else
196 /* Initialize the low level hardware (MSP) */
197 HAL_SDRAM_MspInit(hsdram);
198 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
199 }
200
201 /* Initialize the SDRAM controller state */
202 hsdram->State = HAL_SDRAM_STATE_BUSY;
203
204 /* Initialize SDRAM control Interface */
205 (void)FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
206
207 /* Initialize SDRAM timing Interface */
208 (void)FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
209 /* Update the SDRAM controller state */
210 hsdram->State = HAL_SDRAM_STATE_READY;
211
212 return HAL_OK;
213 }
214
215 /**
216 * @brief Perform the SDRAM device initialization sequence.
217 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
218 * the configuration information for SDRAM module.
219 * @retval HAL status
220 */
HAL_SDRAM_DeInit(SDRAM_HandleTypeDef * hsdram)221 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
222 {
223 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
224 if (hsdram->MspDeInitCallback == NULL)
225 {
226 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
227 }
228
229 /* DeInit the low level hardware */
230 hsdram->MspDeInitCallback(hsdram);
231 #else
232 /* Initialize the low level hardware (MSP) */
233 HAL_SDRAM_MspDeInit(hsdram);
234 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
235
236 /* Configure the SDRAM registers with their reset values */
237 (void)FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
238
239 /* Reset the SDRAM controller state */
240 hsdram->State = HAL_SDRAM_STATE_RESET;
241
242 /* Release Lock */
243 __HAL_UNLOCK(hsdram);
244
245 return HAL_OK;
246 }
247
248 /**
249 * @brief SDRAM MSP Init.
250 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
251 * the configuration information for SDRAM module.
252 * @retval None
253 */
HAL_SDRAM_MspInit(SDRAM_HandleTypeDef * hsdram)254 __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
255 {
256 /* Prevent unused argument(s) compilation warning */
257 UNUSED(hsdram);
258
259 /* NOTE: This function Should not be modified, when the callback is needed,
260 the HAL_SDRAM_MspInit could be implemented in the user file
261 */
262 }
263
264 /**
265 * @brief SDRAM MSP DeInit.
266 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
267 * the configuration information for SDRAM module.
268 * @retval None
269 */
HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef * hsdram)270 __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
271 {
272 /* Prevent unused argument(s) compilation warning */
273 UNUSED(hsdram);
274
275 /* NOTE: This function Should not be modified, when the callback is needed,
276 the HAL_SDRAM_MspDeInit could be implemented in the user file
277 */
278 }
279
280 /**
281 * @brief This function handles SDRAM refresh error interrupt request.
282 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
283 * the configuration information for SDRAM module.
284 * @retval HAL status
285 */
HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef * hsdram)286 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
287 {
288 /* Check SDRAM interrupt Rising edge flag */
289 if (__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
290 {
291 /* SDRAM refresh error interrupt callback */
292 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
293 hsdram->RefreshErrorCallback(hsdram);
294 #else
295 HAL_SDRAM_RefreshErrorCallback(hsdram);
296 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
297
298 /* Clear SDRAM refresh error interrupt pending bit */
299 __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
300 }
301 }
302
303 /**
304 * @brief SDRAM Refresh error callback.
305 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
306 * the configuration information for SDRAM module.
307 * @retval None
308 */
HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef * hsdram)309 __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
310 {
311 /* Prevent unused argument(s) compilation warning */
312 UNUSED(hsdram);
313
314 /* NOTE: This function Should not be modified, when the callback is needed,
315 the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
316 */
317 }
318
319 /**
320 * @brief DMA transfer complete callback.
321 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
322 * the configuration information for the specified DMA module.
323 * @retval None
324 */
HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef * hdma)325 __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
326 {
327 /* Prevent unused argument(s) compilation warning */
328 UNUSED(hdma);
329
330 /* NOTE: This function Should not be modified, when the callback is needed,
331 the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
332 */
333 }
334
335 /**
336 * @brief DMA transfer complete error callback.
337 * @param hdma DMA handle
338 * @retval None
339 */
HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef * hdma)340 __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
341 {
342 /* Prevent unused argument(s) compilation warning */
343 UNUSED(hdma);
344
345 /* NOTE: This function Should not be modified, when the callback is needed,
346 the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
347 */
348 }
349
350 /**
351 * @}
352 */
353
354 /** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions
355 * @brief Input Output and memory control functions
356 *
357 @verbatim
358 ==============================================================================
359 ##### SDRAM Input and Output functions #####
360 ==============================================================================
361 [..]
362 This section provides functions allowing to use and control the SDRAM memory
363
364 @endverbatim
365 * @{
366 */
367
368 /**
369 * @brief Reads 8-bit data buffer from the SDRAM memory.
370 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
371 * the configuration information for SDRAM module.
372 * @param pAddress Pointer to read start address
373 * @param pDstBuffer Pointer to destination buffer
374 * @param BufferSize Size of the buffer to read from memory
375 * @retval HAL status
376 */
HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint8_t * pDstBuffer,uint32_t BufferSize)377 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer,
378 uint32_t BufferSize)
379 {
380 uint32_t size;
381 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
382 uint8_t *pdestbuff = pDstBuffer;
383 HAL_SDRAM_StateTypeDef state = hsdram->State;
384
385 /* Check the SDRAM controller state */
386 if (state == HAL_SDRAM_STATE_BUSY)
387 {
388 return HAL_BUSY;
389 }
390 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
391 {
392 /* Process Locked */
393 __HAL_LOCK(hsdram);
394
395 /* Update the SDRAM controller state */
396 hsdram->State = HAL_SDRAM_STATE_BUSY;
397
398 /* Read data from source */
399 for (size = BufferSize; size != 0U; size--)
400 {
401 *pdestbuff = *(__IO uint8_t *)pSdramAddress;
402 pdestbuff++;
403 pSdramAddress++;
404 }
405
406 /* Update the SDRAM controller state */
407 hsdram->State = state;
408
409 /* Process Unlocked */
410 __HAL_UNLOCK(hsdram);
411 }
412 else
413 {
414 return HAL_ERROR;
415 }
416
417 return HAL_OK;
418 }
419
420 /**
421 * @brief Writes 8-bit data buffer to SDRAM memory.
422 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
423 * the configuration information for SDRAM module.
424 * @param pAddress Pointer to write start address
425 * @param pSrcBuffer Pointer to source buffer to write
426 * @param BufferSize Size of the buffer to write to memory
427 * @retval HAL status
428 */
HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint8_t * pSrcBuffer,uint32_t BufferSize)429 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer,
430 uint32_t BufferSize)
431 {
432 uint32_t size;
433 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
434 uint8_t *psrcbuff = pSrcBuffer;
435
436 /* Check the SDRAM controller state */
437 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
438 {
439 return HAL_BUSY;
440 }
441 else if (hsdram->State == HAL_SDRAM_STATE_READY)
442 {
443 /* Process Locked */
444 __HAL_LOCK(hsdram);
445
446 /* Update the SDRAM controller state */
447 hsdram->State = HAL_SDRAM_STATE_BUSY;
448
449 /* Write data to memory */
450 for (size = BufferSize; size != 0U; size--)
451 {
452 *(__IO uint8_t *)pSdramAddress = *psrcbuff;
453 psrcbuff++;
454 pSdramAddress++;
455 }
456
457 /* Update the SDRAM controller state */
458 hsdram->State = HAL_SDRAM_STATE_READY;
459
460 /* Process Unlocked */
461 __HAL_UNLOCK(hsdram);
462 }
463 else
464 {
465 return HAL_ERROR;
466 }
467
468 return HAL_OK;
469 }
470
471 /**
472 * @brief Reads 16-bit data buffer from the SDRAM memory.
473 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
474 * the configuration information for SDRAM module.
475 * @param pAddress Pointer to read start address
476 * @param pDstBuffer Pointer to destination buffer
477 * @param BufferSize Size of the buffer to read from memory
478 * @retval HAL status
479 */
HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint16_t * pDstBuffer,uint32_t BufferSize)480 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer,
481 uint32_t BufferSize)
482 {
483 uint32_t size;
484 __IO uint32_t *pSdramAddress = pAddress;
485 uint16_t *pdestbuff = pDstBuffer;
486 HAL_SDRAM_StateTypeDef state = hsdram->State;
487
488 /* Check the SDRAM controller state */
489 if (state == HAL_SDRAM_STATE_BUSY)
490 {
491 return HAL_BUSY;
492 }
493 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
494 {
495 /* Process Locked */
496 __HAL_LOCK(hsdram);
497
498 /* Update the SDRAM controller state */
499 hsdram->State = HAL_SDRAM_STATE_BUSY;
500
501 /* Read data from memory */
502 for (size = BufferSize; size >= 2U ; size -= 2U)
503 {
504 *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
505 pdestbuff++;
506 *pdestbuff = (uint16_t)(((*pSdramAddress) & 0xFFFF0000U) >> 16U);
507 pdestbuff++;
508 pSdramAddress++;
509 }
510
511 /* Read last 16-bits if size is not 32-bits multiple */
512 if ((BufferSize % 2U) != 0U)
513 {
514 *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
515 }
516
517 /* Update the SDRAM controller state */
518 hsdram->State = state;
519
520 /* Process Unlocked */
521 __HAL_UNLOCK(hsdram);
522 }
523 else
524 {
525 return HAL_ERROR;
526 }
527
528 return HAL_OK;
529 }
530
531 /**
532 * @brief Writes 16-bit data buffer to SDRAM memory.
533 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
534 * the configuration information for SDRAM module.
535 * @param pAddress Pointer to write start address
536 * @param pSrcBuffer Pointer to source buffer to write
537 * @param BufferSize Size of the buffer to write to memory
538 * @retval HAL status
539 */
HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint16_t * pSrcBuffer,uint32_t BufferSize)540 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer,
541 uint32_t BufferSize)
542 {
543 uint32_t size;
544 __IO uint32_t *psdramaddress = pAddress;
545 uint16_t *psrcbuff = pSrcBuffer;
546
547 /* Check the SDRAM controller state */
548 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
549 {
550 return HAL_BUSY;
551 }
552 else if (hsdram->State == HAL_SDRAM_STATE_READY)
553 {
554 /* Process Locked */
555 __HAL_LOCK(hsdram);
556
557 /* Update the SDRAM controller state */
558 hsdram->State = HAL_SDRAM_STATE_BUSY;
559
560 /* Write data to memory */
561 for (size = BufferSize; size >= 2U ; size -= 2U)
562 {
563 *psdramaddress = (uint32_t)(*psrcbuff);
564 psrcbuff++;
565 *psdramaddress |= ((uint32_t)(*psrcbuff) << 16U);
566 psrcbuff++;
567 psdramaddress++;
568 }
569
570 /* Write last 16-bits if size is not 32-bits multiple */
571 if ((BufferSize % 2U) != 0U)
572 {
573 *psdramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psdramaddress) & 0xFFFF0000U);
574 }
575
576 /* Update the SDRAM controller state */
577 hsdram->State = HAL_SDRAM_STATE_READY;
578
579 /* Process Unlocked */
580 __HAL_UNLOCK(hsdram);
581 }
582 else
583 {
584 return HAL_ERROR;
585 }
586
587 return HAL_OK;
588 }
589
590 /**
591 * @brief Reads 32-bit data buffer from the SDRAM memory.
592 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
593 * the configuration information for SDRAM module.
594 * @param pAddress Pointer to read start address
595 * @param pDstBuffer Pointer to destination buffer
596 * @param BufferSize Size of the buffer to read from memory
597 * @retval HAL status
598 */
HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)599 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
600 uint32_t BufferSize)
601 {
602 uint32_t size;
603 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
604 uint32_t *pdestbuff = pDstBuffer;
605 HAL_SDRAM_StateTypeDef state = hsdram->State;
606
607 /* Check the SDRAM controller state */
608 if (state == HAL_SDRAM_STATE_BUSY)
609 {
610 return HAL_BUSY;
611 }
612 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
613 {
614 /* Process Locked */
615 __HAL_LOCK(hsdram);
616
617 /* Update the SDRAM controller state */
618 hsdram->State = HAL_SDRAM_STATE_BUSY;
619
620 /* Read data from source */
621 for (size = BufferSize; size != 0U; size--)
622 {
623 *pdestbuff = *(__IO uint32_t *)pSdramAddress;
624 pdestbuff++;
625 pSdramAddress++;
626 }
627
628 /* Update the SDRAM controller state */
629 hsdram->State = state;
630
631 /* Process Unlocked */
632 __HAL_UNLOCK(hsdram);
633 }
634 else
635 {
636 return HAL_ERROR;
637 }
638
639 return HAL_OK;
640 }
641
642 /**
643 * @brief Writes 32-bit data buffer to SDRAM memory.
644 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
645 * the configuration information for SDRAM module.
646 * @param pAddress Pointer to write start address
647 * @param pSrcBuffer Pointer to source buffer to write
648 * @param BufferSize Size of the buffer to write to memory
649 * @retval HAL status
650 */
HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)651 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
652 uint32_t BufferSize)
653 {
654 uint32_t size;
655 __IO uint32_t *pSdramAddress = pAddress;
656 uint32_t *psrcbuff = pSrcBuffer;
657
658 /* Check the SDRAM controller state */
659 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
660 {
661 return HAL_BUSY;
662 }
663 else if (hsdram->State == HAL_SDRAM_STATE_READY)
664 {
665 /* Process Locked */
666 __HAL_LOCK(hsdram);
667
668 /* Update the SDRAM controller state */
669 hsdram->State = HAL_SDRAM_STATE_BUSY;
670
671 /* Write data to memory */
672 for (size = BufferSize; size != 0U; size--)
673 {
674 *pSdramAddress = *psrcbuff;
675 psrcbuff++;
676 pSdramAddress++;
677 }
678
679 /* Update the SDRAM controller state */
680 hsdram->State = HAL_SDRAM_STATE_READY;
681
682 /* Process Unlocked */
683 __HAL_UNLOCK(hsdram);
684 }
685 else
686 {
687 return HAL_ERROR;
688 }
689
690 return HAL_OK;
691 }
692
693 /**
694 * @brief Reads a Words data from the SDRAM memory using DMA transfer.
695 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
696 * the configuration information for SDRAM module.
697 * @param pAddress Pointer to read start address
698 * @param pDstBuffer Pointer to destination buffer
699 * @param BufferSize Size of the buffer to read from memory
700 * @retval HAL status
701 */
HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)702 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
703 uint32_t BufferSize)
704 {
705 HAL_StatusTypeDef status;
706 HAL_SDRAM_StateTypeDef state = hsdram->State;
707
708 /* Check the SDRAM controller state */
709 if (state == HAL_SDRAM_STATE_BUSY)
710 {
711 status = HAL_BUSY;
712 }
713 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
714 {
715 /* Process Locked */
716 __HAL_LOCK(hsdram);
717
718 /* Update the SDRAM controller state */
719 hsdram->State = HAL_SDRAM_STATE_BUSY;
720
721 /* Configure DMA user callbacks */
722 if (state == HAL_SDRAM_STATE_READY)
723 {
724 hsdram->hdma->XferCpltCallback = SDRAM_DMACplt;
725 }
726 else
727 {
728 hsdram->hdma->XferCpltCallback = SDRAM_DMACpltProt;
729 }
730 hsdram->hdma->XferErrorCallback = SDRAM_DMAError;
731
732 /* Enable the DMA Stream */
733 status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
734
735 /* Process Unlocked */
736 __HAL_UNLOCK(hsdram);
737 }
738 else
739 {
740 status = HAL_ERROR;
741 }
742
743 return status;
744 }
745
746 /**
747 * @brief Writes a Words data buffer to SDRAM memory using DMA transfer.
748 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
749 * the configuration information for SDRAM module.
750 * @param pAddress Pointer to write start address
751 * @param pSrcBuffer Pointer to source buffer to write
752 * @param BufferSize Size of the buffer to write to memory
753 * @retval HAL status
754 */
HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)755 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
756 uint32_t BufferSize)
757 {
758 HAL_StatusTypeDef status;
759
760 /* Check the SDRAM controller state */
761 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
762 {
763 status = HAL_BUSY;
764 }
765 else if (hsdram->State == HAL_SDRAM_STATE_READY)
766 {
767 /* Process Locked */
768 __HAL_LOCK(hsdram);
769
770 /* Update the SDRAM controller state */
771 hsdram->State = HAL_SDRAM_STATE_BUSY;
772
773 /* Configure DMA user callbacks */
774 hsdram->hdma->XferCpltCallback = SDRAM_DMACplt;
775 hsdram->hdma->XferErrorCallback = SDRAM_DMAError;
776
777 /* Enable the DMA Stream */
778 status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
779
780 /* Process Unlocked */
781 __HAL_UNLOCK(hsdram);
782 }
783 else
784 {
785 status = HAL_ERROR;
786 }
787
788 return status;
789 }
790
791 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
792 /**
793 * @brief Register a User SDRAM Callback
794 * To be used to override the weak predefined callback
795 * @param hsdram : SDRAM handle
796 * @param CallbackId : ID of the callback to be registered
797 * This parameter can be one of the following values:
798 * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID
799 * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID
800 * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID
801 * @param pCallback : pointer to the Callback function
802 * @retval status
803 */
HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef * hsdram,HAL_SDRAM_CallbackIDTypeDef CallbackId,pSDRAM_CallbackTypeDef pCallback)804 HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
805 pSDRAM_CallbackTypeDef pCallback)
806 {
807 HAL_StatusTypeDef status = HAL_OK;
808 HAL_SDRAM_StateTypeDef state;
809
810 if (pCallback == NULL)
811 {
812 return HAL_ERROR;
813 }
814
815 state = hsdram->State;
816 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
817 {
818 switch (CallbackId)
819 {
820 case HAL_SDRAM_MSP_INIT_CB_ID :
821 hsdram->MspInitCallback = pCallback;
822 break;
823 case HAL_SDRAM_MSP_DEINIT_CB_ID :
824 hsdram->MspDeInitCallback = pCallback;
825 break;
826 case HAL_SDRAM_REFRESH_ERR_CB_ID :
827 hsdram->RefreshErrorCallback = pCallback;
828 break;
829 default :
830 /* update return status */
831 status = HAL_ERROR;
832 break;
833 }
834 }
835 else if (hsdram->State == HAL_SDRAM_STATE_RESET)
836 {
837 switch (CallbackId)
838 {
839 case HAL_SDRAM_MSP_INIT_CB_ID :
840 hsdram->MspInitCallback = pCallback;
841 break;
842 case HAL_SDRAM_MSP_DEINIT_CB_ID :
843 hsdram->MspDeInitCallback = pCallback;
844 break;
845 default :
846 /* update return status */
847 status = HAL_ERROR;
848 break;
849 }
850 }
851 else
852 {
853 /* update return status */
854 status = HAL_ERROR;
855 }
856
857 return status;
858 }
859
860 /**
861 * @brief Unregister a User SDRAM Callback
862 * SDRAM Callback is redirected to the weak predefined callback
863 * @param hsdram : SDRAM handle
864 * @param CallbackId : ID of the callback to be unregistered
865 * This parameter can be one of the following values:
866 * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID
867 * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID
868 * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID
869 * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID
870 * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID
871 * @retval status
872 */
HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef * hsdram,HAL_SDRAM_CallbackIDTypeDef CallbackId)873 HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId)
874 {
875 HAL_StatusTypeDef status = HAL_OK;
876 HAL_SDRAM_StateTypeDef state;
877
878 state = hsdram->State;
879 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
880 {
881 switch (CallbackId)
882 {
883 case HAL_SDRAM_MSP_INIT_CB_ID :
884 hsdram->MspInitCallback = HAL_SDRAM_MspInit;
885 break;
886 case HAL_SDRAM_MSP_DEINIT_CB_ID :
887 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
888 break;
889 case HAL_SDRAM_REFRESH_ERR_CB_ID :
890 hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
891 break;
892 case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
893 hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
894 break;
895 case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
896 hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
897 break;
898 default :
899 /* update return status */
900 status = HAL_ERROR;
901 break;
902 }
903 }
904 else if (hsdram->State == HAL_SDRAM_STATE_RESET)
905 {
906 switch (CallbackId)
907 {
908 case HAL_SDRAM_MSP_INIT_CB_ID :
909 hsdram->MspInitCallback = HAL_SDRAM_MspInit;
910 break;
911 case HAL_SDRAM_MSP_DEINIT_CB_ID :
912 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
913 break;
914 default :
915 /* update return status */
916 status = HAL_ERROR;
917 break;
918 }
919 }
920 else
921 {
922 /* update return status */
923 status = HAL_ERROR;
924 }
925
926 return status;
927 }
928
929 /**
930 * @brief Register a User SDRAM Callback for DMA transfers
931 * To be used to override the weak predefined callback
932 * @param hsdram : SDRAM handle
933 * @param CallbackId : ID of the callback to be registered
934 * This parameter can be one of the following values:
935 * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID
936 * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID
937 * @param pCallback : pointer to the Callback function
938 * @retval status
939 */
HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef * hsdram,HAL_SDRAM_CallbackIDTypeDef CallbackId,pSDRAM_DmaCallbackTypeDef pCallback)940 HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
941 pSDRAM_DmaCallbackTypeDef pCallback)
942 {
943 HAL_StatusTypeDef status = HAL_OK;
944 HAL_SDRAM_StateTypeDef state;
945
946 if (pCallback == NULL)
947 {
948 return HAL_ERROR;
949 }
950
951 /* Process locked */
952 __HAL_LOCK(hsdram);
953
954 state = hsdram->State;
955 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
956 {
957 switch (CallbackId)
958 {
959 case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
960 hsdram->DmaXferCpltCallback = pCallback;
961 break;
962 case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
963 hsdram->DmaXferErrorCallback = pCallback;
964 break;
965 default :
966 /* update return status */
967 status = HAL_ERROR;
968 break;
969 }
970 }
971 else
972 {
973 /* update return status */
974 status = HAL_ERROR;
975 }
976
977 /* Release Lock */
978 __HAL_UNLOCK(hsdram);
979 return status;
980 }
981 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
982
983 /**
984 * @}
985 */
986
987 /** @defgroup SDRAM_Exported_Functions_Group3 Control functions
988 * @brief management functions
989 *
990 @verbatim
991 ==============================================================================
992 ##### SDRAM Control functions #####
993 ==============================================================================
994 [..]
995 This subsection provides a set of functions allowing to control dynamically
996 the SDRAM interface.
997
998 @endverbatim
999 * @{
1000 */
1001
1002 /**
1003 * @brief Enables dynamically SDRAM write protection.
1004 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1005 * the configuration information for SDRAM module.
1006 * @retval HAL status
1007 */
HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef * hsdram)1008 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
1009 {
1010 /* Check the SDRAM controller state */
1011 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
1012 {
1013 return HAL_BUSY;
1014 }
1015 else if (hsdram->State == HAL_SDRAM_STATE_READY)
1016 {
1017 /* Update the SDRAM state */
1018 hsdram->State = HAL_SDRAM_STATE_BUSY;
1019
1020 /* Enable write protection */
1021 (void)FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
1022
1023 /* Update the SDRAM state */
1024 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
1025 }
1026 else
1027 {
1028 return HAL_ERROR;
1029 }
1030
1031 return HAL_OK;
1032 }
1033
1034 /**
1035 * @brief Disables dynamically SDRAM write protection.
1036 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1037 * the configuration information for SDRAM module.
1038 * @retval HAL status
1039 */
HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef * hsdram)1040 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
1041 {
1042 HAL_SDRAM_StateTypeDef state = hsdram->State;
1043
1044 /* Check the SDRAM controller state */
1045 if (state == HAL_SDRAM_STATE_BUSY)
1046 {
1047 return HAL_BUSY;
1048 }
1049 else if (state == HAL_SDRAM_STATE_WRITE_PROTECTED)
1050 {
1051 /* Update the SDRAM state */
1052 hsdram->State = HAL_SDRAM_STATE_BUSY;
1053
1054 /* Disable write protection */
1055 (void)FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
1056
1057 /* Update the SDRAM state */
1058 hsdram->State = HAL_SDRAM_STATE_READY;
1059 }
1060 else
1061 {
1062 return HAL_ERROR;
1063 }
1064
1065 return HAL_OK;
1066 }
1067
1068 /**
1069 * @brief Sends Command to the SDRAM bank.
1070 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1071 * the configuration information for SDRAM module.
1072 * @param Command SDRAM command structure
1073 * @param Timeout Timeout duration
1074 * @retval HAL status
1075 */
HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef * hsdram,FMC_SDRAM_CommandTypeDef * Command,uint32_t Timeout)1076 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command,
1077 uint32_t Timeout)
1078 {
1079 HAL_SDRAM_StateTypeDef state = hsdram->State;
1080
1081 /* Check the SDRAM controller state */
1082 if (state == HAL_SDRAM_STATE_BUSY)
1083 {
1084 return HAL_BUSY;
1085 }
1086 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_PRECHARGED))
1087 {
1088 /* Update the SDRAM state */
1089 hsdram->State = HAL_SDRAM_STATE_BUSY;
1090
1091 /* Send SDRAM command */
1092 (void)FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
1093
1094 /* Update the SDRAM controller state state */
1095 if (Command->CommandMode == FMC_SDRAM_CMD_PALL)
1096 {
1097 hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
1098 }
1099 else
1100 {
1101 hsdram->State = HAL_SDRAM_STATE_READY;
1102 }
1103 }
1104 else
1105 {
1106 return HAL_ERROR;
1107 }
1108
1109 return HAL_OK;
1110 }
1111
1112 /**
1113 * @brief Programs the SDRAM Memory Refresh rate.
1114 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1115 * the configuration information for SDRAM module.
1116 * @param RefreshRate The SDRAM refresh rate value
1117 * @retval HAL status
1118 */
HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef * hsdram,uint32_t RefreshRate)1119 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
1120 {
1121 /* Check the SDRAM controller state */
1122 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
1123 {
1124 return HAL_BUSY;
1125 }
1126 else if (hsdram->State == HAL_SDRAM_STATE_READY)
1127 {
1128 /* Update the SDRAM state */
1129 hsdram->State = HAL_SDRAM_STATE_BUSY;
1130
1131 /* Program the refresh rate */
1132 (void)FMC_SDRAM_ProgramRefreshRate(hsdram->Instance, RefreshRate);
1133
1134 /* Update the SDRAM state */
1135 hsdram->State = HAL_SDRAM_STATE_READY;
1136 }
1137 else
1138 {
1139 return HAL_ERROR;
1140 }
1141
1142 return HAL_OK;
1143 }
1144
1145 /**
1146 * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
1147 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1148 * the configuration information for SDRAM module.
1149 * @param AutoRefreshNumber The SDRAM auto Refresh number
1150 * @retval HAL status
1151 */
HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef * hsdram,uint32_t AutoRefreshNumber)1152 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
1153 {
1154 /* Check the SDRAM controller state */
1155 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
1156 {
1157 return HAL_BUSY;
1158 }
1159 else if (hsdram->State == HAL_SDRAM_STATE_READY)
1160 {
1161 /* Update the SDRAM state */
1162 hsdram->State = HAL_SDRAM_STATE_BUSY;
1163
1164 /* Set the Auto-Refresh number */
1165 (void)FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance, AutoRefreshNumber);
1166
1167 /* Update the SDRAM state */
1168 hsdram->State = HAL_SDRAM_STATE_READY;
1169 }
1170 else
1171 {
1172 return HAL_ERROR;
1173 }
1174
1175 return HAL_OK;
1176 }
1177
1178 /**
1179 * @brief Returns the SDRAM memory current mode.
1180 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1181 * the configuration information for SDRAM module.
1182 * @retval The SDRAM memory mode.
1183 */
HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef * hsdram)1184 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
1185 {
1186 /* Return the SDRAM memory current mode */
1187 return (FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
1188 }
1189
1190 /**
1191 * @}
1192 */
1193
1194 /** @defgroup SDRAM_Exported_Functions_Group4 State functions
1195 * @brief Peripheral State functions
1196 *
1197 @verbatim
1198 ==============================================================================
1199 ##### SDRAM State functions #####
1200 ==============================================================================
1201 [..]
1202 This subsection permits to get in run-time the status of the SDRAM controller
1203 and the data flow.
1204
1205 @endverbatim
1206 * @{
1207 */
1208
1209 /**
1210 * @brief Returns the SDRAM state.
1211 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1212 * the configuration information for SDRAM module.
1213 * @retval HAL state
1214 */
HAL_SDRAM_GetState(SDRAM_HandleTypeDef * hsdram)1215 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
1216 {
1217 return hsdram->State;
1218 }
1219
1220 /**
1221 * @}
1222 */
1223
1224 /**
1225 * @}
1226 */
1227
1228 /** @addtogroup SDRAM_Private_Functions SDRAM Private Functions
1229 * @{
1230 */
1231 /**
1232 * @brief DMA SDRAM process complete callback.
1233 * @param hdma : DMA handle
1234 * @retval None
1235 */
SDRAM_DMACplt(DMA_HandleTypeDef * hdma)1236 static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma)
1237 {
1238 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
1239
1240 /* Disable the DMA channel */
1241 __HAL_DMA_DISABLE(hdma);
1242
1243 /* Update the SDRAM controller state */
1244 hsdram->State = HAL_SDRAM_STATE_READY;
1245
1246 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
1247 hsdram->DmaXferCpltCallback(hdma);
1248 #else
1249 HAL_SDRAM_DMA_XferCpltCallback(hdma);
1250 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
1251 }
1252
1253 /**
1254 * @brief DMA SRAM process complete callback.
1255 * @param hdma : DMA handle
1256 * @retval None
1257 */
SDRAM_DMACpltProt(DMA_HandleTypeDef * hdma)1258 static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
1259 {
1260 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
1261
1262 /* Disable the DMA channel */
1263 __HAL_DMA_DISABLE(hdma);
1264
1265 /* Update the SDRAM controller state */
1266 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
1267
1268 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
1269 hsdram->DmaXferCpltCallback(hdma);
1270 #else
1271 HAL_SDRAM_DMA_XferCpltCallback(hdma);
1272 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
1273 }
1274
1275 /**
1276 * @brief DMA SDRAM error callback.
1277 * @param hdma : DMA handle
1278 * @retval None
1279 */
SDRAM_DMAError(DMA_HandleTypeDef * hdma)1280 static void SDRAM_DMAError(DMA_HandleTypeDef *hdma)
1281 {
1282 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
1283
1284 /* Disable the DMA channel */
1285 __HAL_DMA_DISABLE(hdma);
1286
1287 /* Update the SDRAM controller state */
1288 hsdram->State = HAL_SDRAM_STATE_ERROR;
1289
1290 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
1291 hsdram->DmaXferErrorCallback(hdma);
1292 #else
1293 HAL_SDRAM_DMA_XferErrorCallback(hdma);
1294 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
1295 }
1296
1297 /**
1298 * @}
1299 */
1300 /**
1301 * @}
1302 */
1303
1304 #endif /* HAL_SDRAM_MODULE_ENABLED */
1305
1306 /**
1307 * @}
1308 */
1309
1310 #endif /* FMC_Bank5_6 */
1311
