1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_adc.c
4 * @author MCD Application Team
5 * @brief This file provides firmware functions to manage the following
6 * functionalities of the Analog to Digital Converter (ADC) peripheral:
7 * + Initialization and de-initialization functions
8 * + Peripheral Control functions
9 * + Peripheral State functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2017 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file
18 * in the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 *
21 ******************************************************************************
22 @verbatim
23 ==============================================================================
24 ##### ADC Peripheral features #####
25 ==============================================================================
26 [..]
27 (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
28 (#) Interrupt generation at the end of conversion, end of injected conversion,
29 and in case of analog watchdog or overrun events
30 (#) Single and continuous conversion modes.
31 (#) Scan mode for automatic conversion of channel 0 to channel x.
32 (#) Data alignment with in-built data coherency.
33 (#) Channel-wise programmable sampling time.
34 (#) External trigger option with configurable polarity for both regular and
35 injected conversion.
36 (#) Dual/Triple mode (on devices with 2 ADCs or more).
37 (#) Configurable DMA data storage in Dual/Triple ADC mode.
38 (#) Configurable delay between conversions in Dual/Triple interleaved mode.
39 (#) ADC conversion type (refer to the datasheets).
40 (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
41 slower speed.
42 (#) ADC input range: VREF(minus) = VIN = VREF(plus).
43 (#) DMA request generation during regular channel conversion.
44
45
46 ##### How to use this driver #####
47 ==============================================================================
48 [..]
49 (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
50 (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
51 (##) ADC pins configuration
52 (+++) Enable the clock for the ADC GPIOs using the following function:
53 __HAL_RCC_GPIOx_CLK_ENABLE()
54 (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
55 (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
56 (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
57 (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
58 (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
59 (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
60 (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
61 (+++) Configure and enable two DMA streams stream for managing data
62 transfer from peripheral to memory (output stream)
63 (+++) Associate the initialized DMA handle to the CRYP DMA handle
64 using __HAL_LINKDMA()
65 (+++) Configure the priority and enable the NVIC for the transfer complete
66 interrupt on the two DMA Streams. The output stream should have higher
67 priority than the input stream.
68
69 *** Configuration of ADC, groups regular/injected, channels parameters ***
70 ==============================================================================
71 [..]
72 (#) Configure the ADC parameters (resolution, data alignment, ...)
73 and regular group parameters (conversion trigger, sequencer, ...)
74 using function HAL_ADC_Init().
75
76 (#) Configure the channels for regular group parameters (channel number,
77 channel rank into sequencer, ..., into regular group)
78 using function HAL_ADC_ConfigChannel().
79
80 (#) Optionally, configure the injected group parameters (conversion trigger,
81 sequencer, ..., of injected group)
82 and the channels for injected group parameters (channel number,
83 channel rank into sequencer, ..., into injected group)
84 using function HAL_ADCEx_InjectedConfigChannel().
85
86 (#) Optionally, configure the analog watchdog parameters (channels
87 monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig().
88
89 (#) Optionally, for devices with several ADC instances: configure the
90 multimode parameters using function HAL_ADCEx_MultiModeConfigChannel().
91
92 *** Execution of ADC conversions ***
93 ==============================================================================
94 [..]
95 (#) ADC driver can be used among three modes: polling, interruption,
96 transfer by DMA.
97
98 *** Polling mode IO operation ***
99 =================================
100 [..]
101 (+) Start the ADC peripheral using HAL_ADC_Start()
102 (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
103 user can specify the value of timeout according to his end application
104 (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
105 (+) Stop the ADC peripheral using HAL_ADC_Stop()
106
107 *** Interrupt mode IO operation ***
108 ===================================
109 [..]
110 (+) Start the ADC peripheral using HAL_ADC_Start_IT()
111 (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
112 (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can
113 add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
114 (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can
115 add his own code by customization of function pointer HAL_ADC_ErrorCallback
116 (+) Stop the ADC peripheral using HAL_ADC_Stop_IT()
117
118 *** DMA mode IO operation ***
119 ==============================
120 [..]
121 (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length
122 of data to be transferred at each end of conversion
123 (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can
124 add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
125 (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can
126 add his own code by customization of function pointer HAL_ADC_ErrorCallback
127 (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA()
128
129 *** ADC HAL driver macros list ***
130 =============================================
131 [..]
132 Below the list of most used macros in ADC HAL driver.
133
134 (+) __HAL_ADC_ENABLE : Enable the ADC peripheral
135 (+) __HAL_ADC_DISABLE : Disable the ADC peripheral
136 (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt
137 (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt
138 (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled
139 (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags
140 (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status
141 (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register
142
143 [..]
144 (@) You can refer to the ADC HAL driver header file for more useful macros
145
146 *** Deinitialization of ADC ***
147 ==============================================================================
148 [..]
149 (#) Disable the ADC interface
150 (++) ADC clock can be hard reset and disabled at RCC top level.
151 (++) Hard reset of ADC peripherals
152 using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET().
153 (++) ADC clock disable using the equivalent macro/functions as configuration step.
154 (+++) Example:
155 Into HAL_ADC_MspDeInit() (recommended code location) or with
156 other device clock parameters configuration:
157 (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);
158 (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
159 (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)
160 (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
161
162 (#) ADC pins configuration
163 (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE()
164
165 (#) Optionally, in case of usage of ADC with interruptions:
166 (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn)
167
168 (#) Optionally, in case of usage of DMA:
169 (++) Deinitialize the DMA using function HAL_DMA_DeInit().
170 (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)
171 *** Callback registration ***
172 ==============================================================================
173 [..]
174
175 The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
176 allows the user to configure dynamically the driver callbacks.
177 Use Functions HAL_ADC_RegisterCallback()
178 to register an interrupt callback.
179 [..]
180
181 Function HAL_ADC_RegisterCallback() allows to register following callbacks:
182 (+) ConvCpltCallback : ADC conversion complete callback
183 (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
184 (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
185 (+) ErrorCallback : ADC error callback
186 (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
187 (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
188 (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
189 (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
190 (+) EndOfSamplingCallback : ADC end of sampling callback
191 (+) MspInitCallback : ADC Msp Init callback
192 (+) MspDeInitCallback : ADC Msp DeInit callback
193 This function takes as parameters the HAL peripheral handle, the Callback ID
194 and a pointer to the user callback function.
195 [..]
196
197 Use function HAL_ADC_UnRegisterCallback to reset a callback to the default
198 weak function.
199 [..]
200
201 HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
202 and the Callback ID.
203 This function allows to reset following callbacks:
204 (+) ConvCpltCallback : ADC conversion complete callback
205 (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
206 (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
207 (+) ErrorCallback : ADC error callback
208 (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
209 (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
210 (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
211 (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
212 (+) EndOfSamplingCallback : ADC end of sampling callback
213 (+) MspInitCallback : ADC Msp Init callback
214 (+) MspDeInitCallback : ADC Msp DeInit callback
215 [..]
216
217 By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET
218 all callbacks are set to the corresponding weak functions:
219 examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback().
220 Exception done for MspInit and MspDeInit functions that are
221 reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when
222 these callbacks are null (not registered beforehand).
223 [..]
224
225 If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit()
226 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
227 [..]
228
229 Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only.
230 Exception done MspInit/MspDeInit functions that can be registered/unregistered
231 in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state,
232 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
233 [..]
234
235 Then, the user first registers the MspInit/MspDeInit user callbacks
236 using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit()
237 or HAL_ADC_Init() function.
238 [..]
239
240 When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
241 not defined, the callback registration feature is not available and all callbacks
242 are set to the corresponding weak functions.
243
244 @endverbatim
245 */
246
247 /* Includes ------------------------------------------------------------------*/
248 #include "stm32f4xx_hal.h"
249
250 /** @addtogroup STM32F4xx_HAL_Driver
251 * @{
252 */
253
254 /** @defgroup ADC ADC
255 * @brief ADC driver modules
256 * @{
257 */
258
259 #ifdef HAL_ADC_MODULE_ENABLED
260
261 /* Private typedef -----------------------------------------------------------*/
262 /* Private define ------------------------------------------------------------*/
263 /* Private macro -------------------------------------------------------------*/
264 /* Private variables ---------------------------------------------------------*/
265 /** @addtogroup ADC_Private_Functions
266 * @{
267 */
268 /* Private function prototypes -----------------------------------------------*/
269 static void ADC_Init(ADC_HandleTypeDef *hadc);
270 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
271 static void ADC_DMAError(DMA_HandleTypeDef *hdma);
272 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
273 /**
274 * @}
275 */
276 /* Exported functions --------------------------------------------------------*/
277 /** @defgroup ADC_Exported_Functions ADC Exported Functions
278 * @{
279 */
280
281 /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
282 * @brief Initialization and Configuration functions
283 *
284 @verbatim
285 ===============================================================================
286 ##### Initialization and de-initialization functions #####
287 ===============================================================================
288 [..] This section provides functions allowing to:
289 (+) Initialize and configure the ADC.
290 (+) De-initialize the ADC.
291
292 @endverbatim
293 * @{
294 */
295
296 /**
297 * @brief Initializes the ADCx peripheral according to the specified parameters
298 * in the ADC_InitStruct and initializes the ADC MSP.
299 *
300 * @note This function is used to configure the global features of the ADC (
301 * ClockPrescaler, Resolution, Data Alignment and number of conversion), however,
302 * the rest of the configuration parameters are specific to the regular
303 * channels group (scan mode activation, continuous mode activation,
304 * External trigger source and edge, DMA continuous request after the
305 * last transfer and End of conversion selection).
306 *
307 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
308 * the configuration information for the specified ADC.
309 * @retval HAL status
310 */
HAL_ADC_Init(ADC_HandleTypeDef * hadc)311 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
312 {
313 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
314
315 /* Check ADC handle */
316 if (hadc == NULL)
317 {
318 return HAL_ERROR;
319 }
320
321 /* Check the parameters */
322 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
323 assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
324 assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
325 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode));
326 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
327 assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv));
328 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
329 assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
330 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
331 assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
332 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
333
334 if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
335 {
336 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
337 }
338
339 if (hadc->State == HAL_ADC_STATE_RESET)
340 {
341 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
342 /* Init the ADC Callback settings */
343 hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */
344 hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
345 hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
346 hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
347 hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */
348 if (hadc->MspInitCallback == NULL)
349 {
350 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
351 }
352
353 /* Init the low level hardware */
354 hadc->MspInitCallback(hadc);
355 #else
356 /* Init the low level hardware */
357 HAL_ADC_MspInit(hadc);
358 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
359
360 /* Initialize ADC error code */
361 ADC_CLEAR_ERRORCODE(hadc);
362
363 /* Allocate lock resource and initialize it */
364 hadc->Lock = HAL_UNLOCKED;
365 }
366
367 /* Configuration of ADC parameters if previous preliminary actions are */
368 /* correctly completed. */
369 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
370 {
371 /* Set ADC state */
372 ADC_STATE_CLR_SET(hadc->State,
373 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
374 HAL_ADC_STATE_BUSY_INTERNAL);
375
376 /* Set ADC parameters */
377 ADC_Init(hadc);
378
379 /* Set ADC error code to none */
380 ADC_CLEAR_ERRORCODE(hadc);
381
382 /* Set the ADC state */
383 ADC_STATE_CLR_SET(hadc->State,
384 HAL_ADC_STATE_BUSY_INTERNAL,
385 HAL_ADC_STATE_READY);
386 }
387 else
388 {
389 tmp_hal_status = HAL_ERROR;
390 }
391
392 /* Release Lock */
393 __HAL_UNLOCK(hadc);
394
395 /* Return function status */
396 return tmp_hal_status;
397 }
398
399 /**
400 * @brief Deinitializes the ADCx peripheral registers to their default reset values.
401 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
402 * the configuration information for the specified ADC.
403 * @retval HAL status
404 */
HAL_ADC_DeInit(ADC_HandleTypeDef * hadc)405 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
406 {
407 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
408
409 /* Check ADC handle */
410 if (hadc == NULL)
411 {
412 return HAL_ERROR;
413 }
414
415 /* Check the parameters */
416 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
417
418 /* Set ADC state */
419 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
420
421 /* Stop potential conversion on going, on regular and injected groups */
422 /* Disable ADC peripheral */
423 __HAL_ADC_DISABLE(hadc);
424
425 /* Configuration of ADC parameters if previous preliminary actions are */
426 /* correctly completed. */
427 if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
428 {
429 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
430 if (hadc->MspDeInitCallback == NULL)
431 {
432 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
433 }
434
435 /* DeInit the low level hardware: RCC clock, NVIC */
436 hadc->MspDeInitCallback(hadc);
437 #else
438 /* DeInit the low level hardware: RCC clock, NVIC */
439 HAL_ADC_MspDeInit(hadc);
440 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
441
442 /* Set ADC error code to none */
443 ADC_CLEAR_ERRORCODE(hadc);
444
445 /* Set ADC state */
446 hadc->State = HAL_ADC_STATE_RESET;
447 }
448
449 /* Process unlocked */
450 __HAL_UNLOCK(hadc);
451
452 /* Return function status */
453 return tmp_hal_status;
454 }
455
456 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
457 /**
458 * @brief Register a User ADC Callback
459 * To be used instead of the weak predefined callback
460 * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
461 * the configuration information for the specified ADC.
462 * @param CallbackID ID of the callback to be registered
463 * This parameter can be one of the following values:
464 * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
465 * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
466 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
467 * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
468 * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
469 * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
470 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
471 * @param pCallback pointer to the Callback function
472 * @retval HAL status
473 */
HAL_ADC_RegisterCallback(ADC_HandleTypeDef * hadc,HAL_ADC_CallbackIDTypeDef CallbackID,pADC_CallbackTypeDef pCallback)474 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
475 {
476 HAL_StatusTypeDef status = HAL_OK;
477
478 if (pCallback == NULL)
479 {
480 /* Update the error code */
481 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
482
483 return HAL_ERROR;
484 }
485
486 if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
487 {
488 switch (CallbackID)
489 {
490 case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
491 hadc->ConvCpltCallback = pCallback;
492 break;
493
494 case HAL_ADC_CONVERSION_HALF_CB_ID :
495 hadc->ConvHalfCpltCallback = pCallback;
496 break;
497
498 case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
499 hadc->LevelOutOfWindowCallback = pCallback;
500 break;
501
502 case HAL_ADC_ERROR_CB_ID :
503 hadc->ErrorCallback = pCallback;
504 break;
505
506 case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
507 hadc->InjectedConvCpltCallback = pCallback;
508 break;
509
510 case HAL_ADC_MSPINIT_CB_ID :
511 hadc->MspInitCallback = pCallback;
512 break;
513
514 case HAL_ADC_MSPDEINIT_CB_ID :
515 hadc->MspDeInitCallback = pCallback;
516 break;
517
518 default :
519 /* Update the error code */
520 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
521
522 /* Return error status */
523 status = HAL_ERROR;
524 break;
525 }
526 }
527 else if (HAL_ADC_STATE_RESET == hadc->State)
528 {
529 switch (CallbackID)
530 {
531 case HAL_ADC_MSPINIT_CB_ID :
532 hadc->MspInitCallback = pCallback;
533 break;
534
535 case HAL_ADC_MSPDEINIT_CB_ID :
536 hadc->MspDeInitCallback = pCallback;
537 break;
538
539 default :
540 /* Update the error code */
541 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
542
543 /* Return error status */
544 status = HAL_ERROR;
545 break;
546 }
547 }
548 else
549 {
550 /* Update the error code */
551 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
552
553 /* Return error status */
554 status = HAL_ERROR;
555 }
556
557 return status;
558 }
559
560 /**
561 * @brief Unregister a ADC Callback
562 * ADC callback is redirected to the weak predefined callback
563 * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
564 * the configuration information for the specified ADC.
565 * @param CallbackID ID of the callback to be unregistered
566 * This parameter can be one of the following values:
567 * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
568 * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
569 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
570 * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
571 * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
572 * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
573 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
574 * @retval HAL status
575 */
HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef * hadc,HAL_ADC_CallbackIDTypeDef CallbackID)576 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
577 {
578 HAL_StatusTypeDef status = HAL_OK;
579
580 if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
581 {
582 switch (CallbackID)
583 {
584 case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
585 hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
586 break;
587
588 case HAL_ADC_CONVERSION_HALF_CB_ID :
589 hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
590 break;
591
592 case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
593 hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
594 break;
595
596 case HAL_ADC_ERROR_CB_ID :
597 hadc->ErrorCallback = HAL_ADC_ErrorCallback;
598 break;
599
600 case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
601 hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
602 break;
603
604 case HAL_ADC_MSPINIT_CB_ID :
605 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
606 break;
607
608 case HAL_ADC_MSPDEINIT_CB_ID :
609 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
610 break;
611
612 default :
613 /* Update the error code */
614 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
615
616 /* Return error status */
617 status = HAL_ERROR;
618 break;
619 }
620 }
621 else if (HAL_ADC_STATE_RESET == hadc->State)
622 {
623 switch (CallbackID)
624 {
625 case HAL_ADC_MSPINIT_CB_ID :
626 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
627 break;
628
629 case HAL_ADC_MSPDEINIT_CB_ID :
630 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
631 break;
632
633 default :
634 /* Update the error code */
635 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
636
637 /* Return error status */
638 status = HAL_ERROR;
639 break;
640 }
641 }
642 else
643 {
644 /* Update the error code */
645 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
646
647 /* Return error status */
648 status = HAL_ERROR;
649 }
650
651 return status;
652 }
653
654 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
655
656 /**
657 * @brief Initializes the ADC MSP.
658 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
659 * the configuration information for the specified ADC.
660 * @retval None
661 */
HAL_ADC_MspInit(ADC_HandleTypeDef * hadc)662 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
663 {
664 /* Prevent unused argument(s) compilation warning */
665 UNUSED(hadc);
666 /* NOTE : This function Should not be modified, when the callback is needed,
667 the HAL_ADC_MspInit could be implemented in the user file
668 */
669 }
670
671 /**
672 * @brief DeInitializes the ADC MSP.
673 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
674 * the configuration information for the specified ADC.
675 * @retval None
676 */
HAL_ADC_MspDeInit(ADC_HandleTypeDef * hadc)677 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
678 {
679 /* Prevent unused argument(s) compilation warning */
680 UNUSED(hadc);
681 /* NOTE : This function Should not be modified, when the callback is needed,
682 the HAL_ADC_MspDeInit could be implemented in the user file
683 */
684 }
685
686 /**
687 * @}
688 */
689
690 /** @defgroup ADC_Exported_Functions_Group2 IO operation functions
691 * @brief IO operation functions
692 *
693 @verbatim
694 ===============================================================================
695 ##### IO operation functions #####
696 ===============================================================================
697 [..] This section provides functions allowing to:
698 (+) Start conversion of regular channel.
699 (+) Stop conversion of regular channel.
700 (+) Start conversion of regular channel and enable interrupt.
701 (+) Stop conversion of regular channel and disable interrupt.
702 (+) Start conversion of regular channel and enable DMA transfer.
703 (+) Stop conversion of regular channel and disable DMA transfer.
704 (+) Handle ADC interrupt request.
705
706 @endverbatim
707 * @{
708 */
709
710 /**
711 * @brief Enables ADC and starts conversion of the regular channels.
712 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
713 * the configuration information for the specified ADC.
714 * @retval HAL status
715 */
HAL_ADC_Start(ADC_HandleTypeDef * hadc)716 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
717 {
718 __IO uint32_t counter = 0U;
719 ADC_Common_TypeDef *tmpADC_Common;
720
721 /* Check the parameters */
722 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
723 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
724
725 /* Process locked */
726 __HAL_LOCK(hadc);
727
728 /* Enable the ADC peripheral */
729 /* Check if ADC peripheral is disabled in order to enable it and wait during
730 Tstab time the ADC's stabilization */
731 if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
732 {
733 /* Enable the Peripheral */
734 __HAL_ADC_ENABLE(hadc);
735
736 /* Delay for ADC stabilization time */
737 /* Compute number of CPU cycles to wait for */
738 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
739 while (counter != 0U)
740 {
741 counter--;
742 }
743 }
744
745 /* Start conversion if ADC is effectively enabled */
746 if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
747 {
748 /* Set ADC state */
749 /* - Clear state bitfield related to regular group conversion results */
750 /* - Set state bitfield related to regular group operation */
751 ADC_STATE_CLR_SET(hadc->State,
752 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
753 HAL_ADC_STATE_REG_BUSY);
754
755 /* If conversions on group regular are also triggering group injected, */
756 /* update ADC state. */
757 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
758 {
759 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
760 }
761
762 /* State machine update: Check if an injected conversion is ongoing */
763 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
764 {
765 /* Reset ADC error code fields related to conversions on group regular */
766 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
767 }
768 else
769 {
770 /* Reset ADC all error code fields */
771 ADC_CLEAR_ERRORCODE(hadc);
772 }
773
774 /* Process unlocked */
775 /* Unlock before starting ADC conversions: in case of potential */
776 /* interruption, to let the process to ADC IRQ Handler. */
777 __HAL_UNLOCK(hadc);
778
779 /* Pointer to the common control register to which is belonging hadc */
780 /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
781 /* control register) */
782 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
783
784 /* Clear regular group conversion flag and overrun flag */
785 /* (To ensure of no unknown state from potential previous ADC operations) */
786 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
787
788 /* Check if Multimode enabled */
789 if (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
790 {
791 #if defined(ADC2) && defined(ADC3)
792 if ((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \
793 || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4)))
794 {
795 #endif /* ADC2 || ADC3 */
796 /* if no external trigger present enable software conversion of regular channels */
797 if ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
798 {
799 /* Enable the selected ADC software conversion for regular group */
800 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
801 }
802 #if defined(ADC2) && defined(ADC3)
803 }
804 #endif /* ADC2 || ADC3 */
805 }
806 else
807 {
808 /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
809 if ((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
810 {
811 /* Enable the selected ADC software conversion for regular group */
812 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
813 }
814 }
815 }
816 else
817 {
818 /* Update ADC state machine to error */
819 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
820
821 /* Set ADC error code to ADC IP internal error */
822 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
823 }
824
825 /* Return function status */
826 return HAL_OK;
827 }
828
829 /**
830 * @brief Disables ADC and stop conversion of regular channels.
831 *
832 * @note Caution: This function will stop also injected channels.
833 *
834 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
835 * the configuration information for the specified ADC.
836 *
837 * @retval HAL status.
838 */
HAL_ADC_Stop(ADC_HandleTypeDef * hadc)839 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
840 {
841 /* Check the parameters */
842 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
843
844 /* Process locked */
845 __HAL_LOCK(hadc);
846
847 /* Stop potential conversion on going, on regular and injected groups */
848 /* Disable ADC peripheral */
849 __HAL_ADC_DISABLE(hadc);
850
851 /* Check if ADC is effectively disabled */
852 if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
853 {
854 /* Set ADC state */
855 ADC_STATE_CLR_SET(hadc->State,
856 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
857 HAL_ADC_STATE_READY);
858 }
859
860 /* Process unlocked */
861 __HAL_UNLOCK(hadc);
862
863 /* Return function status */
864 return HAL_OK;
865 }
866
867 /**
868 * @brief Poll for regular conversion complete
869 * @note ADC conversion flags EOS (end of sequence) and EOC (end of
870 * conversion) are cleared by this function.
871 * @note This function cannot be used in a particular setup: ADC configured
872 * in DMA mode and polling for end of each conversion (ADC init
873 * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
874 * In this case, DMA resets the flag EOC and polling cannot be
875 * performed on each conversion. Nevertheless, polling can still
876 * be performed on the complete sequence.
877 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
878 * the configuration information for the specified ADC.
879 * @param Timeout Timeout value in millisecond.
880 * @retval HAL status
881 */
HAL_ADC_PollForConversion(ADC_HandleTypeDef * hadc,uint32_t Timeout)882 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
883 {
884 uint32_t tickstart = 0U;
885
886 /* Verification that ADC configuration is compliant with polling for */
887 /* each conversion: */
888 /* Particular case is ADC configured in DMA mode and ADC sequencer with */
889 /* several ranks and polling for end of each conversion. */
890 /* For code simplicity sake, this particular case is generalized to */
891 /* ADC configured in DMA mode and polling for end of each conversion. */
892 if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
893 HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA))
894 {
895 /* Update ADC state machine to error */
896 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
897
898 /* Process unlocked */
899 __HAL_UNLOCK(hadc);
900
901 return HAL_ERROR;
902 }
903
904 /* Get tick */
905 tickstart = HAL_GetTick();
906
907 /* Check End of conversion flag */
908 while (!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
909 {
910 /* Check if timeout is disabled (set to infinite wait) */
911 if (Timeout != HAL_MAX_DELAY)
912 {
913 if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
914 {
915 /* New check to avoid false timeout detection in case of preemption */
916 if (!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
917 {
918 /* Update ADC state machine to timeout */
919 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
920
921 /* Process unlocked */
922 __HAL_UNLOCK(hadc);
923
924 return HAL_TIMEOUT;
925 }
926 }
927 }
928 }
929
930 /* Clear regular group conversion flag */
931 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
932
933 /* Update ADC state machine */
934 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
935
936 /* Determine whether any further conversion upcoming on group regular */
937 /* by external trigger, continuous mode or scan sequence on going. */
938 /* Note: On STM32F4, there is no independent flag of end of sequence. */
939 /* The test of scan sequence on going is done either with scan */
940 /* sequence disabled or with end of conversion flag set to */
941 /* of end of sequence. */
942 if (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
943 (hadc->Init.ContinuousConvMode == DISABLE) &&
944 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
945 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)))
946 {
947 /* Set ADC state */
948 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
949
950 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
951 {
952 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
953 }
954 }
955
956 /* Return ADC state */
957 return HAL_OK;
958 }
959
960 /**
961 * @brief Poll for conversion event
962 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
963 * the configuration information for the specified ADC.
964 * @param EventType the ADC event type.
965 * This parameter can be one of the following values:
966 * @arg ADC_AWD_EVENT: ADC Analog watch Dog event.
967 * @arg ADC_OVR_EVENT: ADC Overrun event.
968 * @param Timeout Timeout value in millisecond.
969 * @retval HAL status
970 */
HAL_ADC_PollForEvent(ADC_HandleTypeDef * hadc,uint32_t EventType,uint32_t Timeout)971 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
972 {
973 uint32_t tickstart = 0U;
974
975 /* Check the parameters */
976 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
977 assert_param(IS_ADC_EVENT_TYPE(EventType));
978
979 /* Get tick */
980 tickstart = HAL_GetTick();
981
982 /* Check selected event flag */
983 while (!(__HAL_ADC_GET_FLAG(hadc, EventType)))
984 {
985 /* Check for the Timeout */
986 if (Timeout != HAL_MAX_DELAY)
987 {
988 if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
989 {
990 /* New check to avoid false timeout detection in case of preemption */
991 if (!(__HAL_ADC_GET_FLAG(hadc, EventType)))
992 {
993 /* Update ADC state machine to timeout */
994 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
995
996 /* Process unlocked */
997 __HAL_UNLOCK(hadc);
998
999 return HAL_TIMEOUT;
1000 }
1001 }
1002 }
1003 }
1004
1005 /* Analog watchdog (level out of window) event */
1006 if (EventType == ADC_AWD_EVENT)
1007 {
1008 /* Set ADC state */
1009 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
1010
1011 /* Clear ADC analog watchdog flag */
1012 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
1013 }
1014 /* Overrun event */
1015 else
1016 {
1017 /* Set ADC state */
1018 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
1019 /* Set ADC error code to overrun */
1020 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
1021
1022 /* Clear ADC overrun flag */
1023 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1024 }
1025
1026 /* Return ADC state */
1027 return HAL_OK;
1028 }
1029
1030
1031 /**
1032 * @brief Enables the interrupt and starts ADC conversion of regular channels.
1033 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1034 * the configuration information for the specified ADC.
1035 * @retval HAL status.
1036 */
HAL_ADC_Start_IT(ADC_HandleTypeDef * hadc)1037 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
1038 {
1039 __IO uint32_t counter = 0U;
1040 ADC_Common_TypeDef *tmpADC_Common;
1041
1042 /* Check the parameters */
1043 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
1044 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
1045
1046 /* Process locked */
1047 __HAL_LOCK(hadc);
1048
1049 /* Enable the ADC peripheral */
1050 /* Check if ADC peripheral is disabled in order to enable it and wait during
1051 Tstab time the ADC's stabilization */
1052 if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
1053 {
1054 /* Enable the Peripheral */
1055 __HAL_ADC_ENABLE(hadc);
1056
1057 /* Delay for ADC stabilization time */
1058 /* Compute number of CPU cycles to wait for */
1059 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
1060 while (counter != 0U)
1061 {
1062 counter--;
1063 }
1064 }
1065
1066 /* Start conversion if ADC is effectively enabled */
1067 if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
1068 {
1069 /* Set ADC state */
1070 /* - Clear state bitfield related to regular group conversion results */
1071 /* - Set state bitfield related to regular group operation */
1072 ADC_STATE_CLR_SET(hadc->State,
1073 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
1074 HAL_ADC_STATE_REG_BUSY);
1075
1076 /* If conversions on group regular are also triggering group injected, */
1077 /* update ADC state. */
1078 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
1079 {
1080 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1081 }
1082
1083 /* State machine update: Check if an injected conversion is ongoing */
1084 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1085 {
1086 /* Reset ADC error code fields related to conversions on group regular */
1087 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
1088 }
1089 else
1090 {
1091 /* Reset ADC all error code fields */
1092 ADC_CLEAR_ERRORCODE(hadc);
1093 }
1094
1095 /* Process unlocked */
1096 /* Unlock before starting ADC conversions: in case of potential */
1097 /* interruption, to let the process to ADC IRQ Handler. */
1098 __HAL_UNLOCK(hadc);
1099
1100 /* Pointer to the common control register to which is belonging hadc */
1101 /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
1102 /* control register) */
1103 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
1104
1105 /* Clear regular group conversion flag and overrun flag */
1106 /* (To ensure of no unknown state from potential previous ADC operations) */
1107 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
1108
1109 /* Enable end of conversion interrupt for regular group */
1110 __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
1111
1112 /* Check if Multimode enabled */
1113 if (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
1114 {
1115 #if defined(ADC2) && defined(ADC3)
1116 if ((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \
1117 || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4)))
1118 {
1119 #endif /* ADC2 || ADC3 */
1120 /* if no external trigger present enable software conversion of regular channels */
1121 if ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
1122 {
1123 /* Enable the selected ADC software conversion for regular group */
1124 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
1125 }
1126 #if defined(ADC2) && defined(ADC3)
1127 }
1128 #endif /* ADC2 || ADC3 */
1129 }
1130 else
1131 {
1132 /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
1133 if ((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
1134 {
1135 /* Enable the selected ADC software conversion for regular group */
1136 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
1137 }
1138 }
1139 }
1140 else
1141 {
1142 /* Update ADC state machine to error */
1143 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
1144
1145 /* Set ADC error code to ADC IP internal error */
1146 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
1147 }
1148
1149 /* Return function status */
1150 return HAL_OK;
1151 }
1152
1153 /**
1154 * @brief Disables the interrupt and stop ADC conversion of regular channels.
1155 *
1156 * @note Caution: This function will stop also injected channels.
1157 *
1158 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1159 * the configuration information for the specified ADC.
1160 * @retval HAL status.
1161 */
HAL_ADC_Stop_IT(ADC_HandleTypeDef * hadc)1162 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
1163 {
1164 /* Check the parameters */
1165 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1166
1167 /* Process locked */
1168 __HAL_LOCK(hadc);
1169
1170 /* Stop potential conversion on going, on regular and injected groups */
1171 /* Disable ADC peripheral */
1172 __HAL_ADC_DISABLE(hadc);
1173
1174 /* Check if ADC is effectively disabled */
1175 if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
1176 {
1177 /* Disable ADC end of conversion interrupt for regular group */
1178 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
1179
1180 /* Set ADC state */
1181 ADC_STATE_CLR_SET(hadc->State,
1182 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1183 HAL_ADC_STATE_READY);
1184 }
1185
1186 /* Process unlocked */
1187 __HAL_UNLOCK(hadc);
1188
1189 /* Return function status */
1190 return HAL_OK;
1191 }
1192
1193 /**
1194 * @brief Handles ADC interrupt request
1195 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1196 * the configuration information for the specified ADC.
1197 * @retval None
1198 */
HAL_ADC_IRQHandler(ADC_HandleTypeDef * hadc)1199 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
1200 {
1201 uint32_t tmp1 = 0U, tmp2 = 0U;
1202
1203 uint32_t tmp_sr = hadc->Instance->SR;
1204 uint32_t tmp_cr1 = hadc->Instance->CR1;
1205
1206 /* Check the parameters */
1207 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
1208 assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
1209 assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
1210
1211 tmp1 = tmp_sr & ADC_FLAG_EOC;
1212 tmp2 = tmp_cr1 & ADC_IT_EOC;
1213 /* Check End of conversion flag for regular channels */
1214 if (tmp1 && tmp2)
1215 {
1216 /* Update state machine on conversion status if not in error state */
1217 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
1218 {
1219 /* Set ADC state */
1220 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
1221 }
1222
1223 /* Determine whether any further conversion upcoming on group regular */
1224 /* by external trigger, continuous mode or scan sequence on going. */
1225 /* Note: On STM32F4, there is no independent flag of end of sequence. */
1226 /* The test of scan sequence on going is done either with scan */
1227 /* sequence disabled or with end of conversion flag set to */
1228 /* of end of sequence. */
1229 if (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
1230 (hadc->Init.ContinuousConvMode == DISABLE) &&
1231 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
1232 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)))
1233 {
1234 /* Disable ADC end of single conversion interrupt on group regular */
1235 /* Note: Overrun interrupt was enabled with EOC interrupt in */
1236 /* HAL_ADC_Start_IT(), but is not disabled here because can be used */
1237 /* by overrun IRQ process below. */
1238 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
1239
1240 /* Set ADC state */
1241 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1242
1243 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1244 {
1245 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
1246 }
1247 }
1248
1249 /* Conversion complete callback */
1250 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1251 hadc->ConvCpltCallback(hadc);
1252 #else
1253 HAL_ADC_ConvCpltCallback(hadc);
1254 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1255
1256 /* Clear regular group conversion flag */
1257 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
1258 }
1259
1260 tmp1 = tmp_sr & ADC_FLAG_JEOC;
1261 tmp2 = tmp_cr1 & ADC_IT_JEOC;
1262 /* Check End of conversion flag for injected channels */
1263 if (tmp1 && tmp2)
1264 {
1265 /* Update state machine on conversion status if not in error state */
1266 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
1267 {
1268 /* Set ADC state */
1269 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
1270 }
1271
1272 /* Determine whether any further conversion upcoming on group injected */
1273 /* by external trigger, scan sequence on going or by automatic injected */
1274 /* conversion from group regular (same conditions as group regular */
1275 /* interruption disabling above). */
1276 if (ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
1277 (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
1278 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) &&
1279 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
1280 (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
1281 (hadc->Init.ContinuousConvMode == DISABLE))))
1282 {
1283 /* Disable ADC end of single conversion interrupt on group injected */
1284 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
1285
1286 /* Set ADC state */
1287 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
1288
1289 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
1290 {
1291 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
1292 }
1293 }
1294
1295 /* Conversion complete callback */
1296 /* Conversion complete callback */
1297 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1298 hadc->InjectedConvCpltCallback(hadc);
1299 #else
1300 HAL_ADCEx_InjectedConvCpltCallback(hadc);
1301 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1302
1303 /* Clear injected group conversion flag */
1304 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
1305 }
1306
1307 tmp1 = tmp_sr & ADC_FLAG_AWD;
1308 tmp2 = tmp_cr1 & ADC_IT_AWD;
1309 /* Check Analog watchdog flag */
1310 if (tmp1 && tmp2)
1311 {
1312 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
1313 {
1314 /* Set ADC state */
1315 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
1316
1317 /* Level out of window callback */
1318 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1319 hadc->LevelOutOfWindowCallback(hadc);
1320 #else
1321 HAL_ADC_LevelOutOfWindowCallback(hadc);
1322 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1323
1324 /* Clear the ADC analog watchdog flag */
1325 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
1326 }
1327 }
1328
1329 tmp1 = tmp_sr & ADC_FLAG_OVR;
1330 tmp2 = tmp_cr1 & ADC_IT_OVR;
1331 /* Check Overrun flag */
1332 if (tmp1 && tmp2)
1333 {
1334 /* Note: On STM32F4, ADC overrun can be set through other parameters */
1335 /* refer to description of parameter "EOCSelection" for more */
1336 /* details. */
1337
1338 /* Set ADC error code to overrun */
1339 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
1340
1341 /* Clear ADC overrun flag */
1342 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1343
1344 /* Error callback */
1345 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1346 hadc->ErrorCallback(hadc);
1347 #else
1348 HAL_ADC_ErrorCallback(hadc);
1349 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1350
1351 /* Clear the Overrun flag */
1352 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1353 }
1354 }
1355
1356 /**
1357 * @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral
1358 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1359 * the configuration information for the specified ADC.
1360 * @param pData The destination Buffer address.
1361 * @param Length The length of data to be transferred from ADC peripheral to memory.
1362 * @retval HAL status
1363 */
HAL_ADC_Start_DMA(ADC_HandleTypeDef * hadc,uint32_t * pData,uint32_t Length)1364 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
1365 {
1366 __IO uint32_t counter = 0U;
1367 ADC_Common_TypeDef *tmpADC_Common;
1368
1369 /* Check the parameters */
1370 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
1371 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
1372
1373 /* Process locked */
1374 __HAL_LOCK(hadc);
1375
1376 /* Enable the ADC peripheral */
1377 /* Check if ADC peripheral is disabled in order to enable it and wait during
1378 Tstab time the ADC's stabilization */
1379 if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
1380 {
1381 /* Enable the Peripheral */
1382 __HAL_ADC_ENABLE(hadc);
1383
1384 /* Delay for ADC stabilization time */
1385 /* Compute number of CPU cycles to wait for */
1386 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
1387 while (counter != 0U)
1388 {
1389 counter--;
1390 }
1391 }
1392
1393 /* Check ADC DMA Mode */
1394 /* - disable the DMA Mode if it is already enabled */
1395 if ((hadc->Instance->CR2 & ADC_CR2_DMA) == ADC_CR2_DMA)
1396 {
1397 CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
1398 }
1399
1400 /* Start conversion if ADC is effectively enabled */
1401 if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
1402 {
1403 /* Set ADC state */
1404 /* - Clear state bitfield related to regular group conversion results */
1405 /* - Set state bitfield related to regular group operation */
1406 ADC_STATE_CLR_SET(hadc->State,
1407 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
1408 HAL_ADC_STATE_REG_BUSY);
1409
1410 /* If conversions on group regular are also triggering group injected, */
1411 /* update ADC state. */
1412 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
1413 {
1414 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1415 }
1416
1417 /* State machine update: Check if an injected conversion is ongoing */
1418 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1419 {
1420 /* Reset ADC error code fields related to conversions on group regular */
1421 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
1422 }
1423 else
1424 {
1425 /* Reset ADC all error code fields */
1426 ADC_CLEAR_ERRORCODE(hadc);
1427 }
1428
1429 /* Process unlocked */
1430 /* Unlock before starting ADC conversions: in case of potential */
1431 /* interruption, to let the process to ADC IRQ Handler. */
1432 __HAL_UNLOCK(hadc);
1433
1434 /* Pointer to the common control register to which is belonging hadc */
1435 /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
1436 /* control register) */
1437 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
1438
1439 /* Set the DMA transfer complete callback */
1440 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
1441
1442 /* Set the DMA half transfer complete callback */
1443 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
1444
1445 /* Set the DMA error callback */
1446 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
1447
1448
1449 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
1450 /* start (in case of SW start): */
1451
1452 /* Clear regular group conversion flag and overrun flag */
1453 /* (To ensure of no unknown state from potential previous ADC operations) */
1454 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
1455
1456 /* Enable ADC overrun interrupt */
1457 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
1458
1459 /* Enable ADC DMA mode */
1460 hadc->Instance->CR2 |= ADC_CR2_DMA;
1461
1462 /* Start the DMA channel */
1463 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
1464
1465 /* Check if Multimode enabled */
1466 if (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
1467 {
1468 #if defined(ADC2) && defined(ADC3)
1469 if ((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \
1470 || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4)))
1471 {
1472 #endif /* ADC2 || ADC3 */
1473 /* if no external trigger present enable software conversion of regular channels */
1474 if ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
1475 {
1476 /* Enable the selected ADC software conversion for regular group */
1477 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
1478 }
1479 #if defined(ADC2) && defined(ADC3)
1480 }
1481 #endif /* ADC2 || ADC3 */
1482 }
1483 else
1484 {
1485 /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
1486 if ((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
1487 {
1488 /* Enable the selected ADC software conversion for regular group */
1489 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
1490 }
1491 }
1492 }
1493 else
1494 {
1495 /* Update ADC state machine to error */
1496 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
1497
1498 /* Set ADC error code to ADC IP internal error */
1499 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
1500 }
1501
1502 /* Return function status */
1503 return HAL_OK;
1504 }
1505
1506 /**
1507 * @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral
1508 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1509 * the configuration information for the specified ADC.
1510 * @retval HAL status
1511 */
HAL_ADC_Stop_DMA(ADC_HandleTypeDef * hadc)1512 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
1513 {
1514 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1515
1516 /* Check the parameters */
1517 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1518
1519 /* Process locked */
1520 __HAL_LOCK(hadc);
1521
1522 /* Stop potential conversion on going, on regular and injected groups */
1523 /* Disable ADC peripheral */
1524 __HAL_ADC_DISABLE(hadc);
1525
1526 /* Check if ADC is effectively disabled */
1527 if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
1528 {
1529 /* Disable the selected ADC DMA mode */
1530 hadc->Instance->CR2 &= ~ADC_CR2_DMA;
1531
1532 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
1533 /* DMA transfer is on going) */
1534 if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
1535 {
1536 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
1537
1538 /* Check if DMA channel effectively disabled */
1539 if (tmp_hal_status != HAL_OK)
1540 {
1541 /* Update ADC state machine to error */
1542 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
1543 }
1544 }
1545
1546 /* Disable ADC overrun interrupt */
1547 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
1548
1549 /* Set ADC state */
1550 ADC_STATE_CLR_SET(hadc->State,
1551 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1552 HAL_ADC_STATE_READY);
1553 }
1554
1555 /* Process unlocked */
1556 __HAL_UNLOCK(hadc);
1557
1558 /* Return function status */
1559 return tmp_hal_status;
1560 }
1561
1562 /**
1563 * @brief Gets the converted value from data register of regular channel.
1564 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1565 * the configuration information for the specified ADC.
1566 * @retval Converted value
1567 */
HAL_ADC_GetValue(ADC_HandleTypeDef * hadc)1568 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc)
1569 {
1570 /* Return the selected ADC converted value */
1571 return hadc->Instance->DR;
1572 }
1573
1574 /**
1575 * @brief Regular conversion complete callback in non blocking mode
1576 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1577 * the configuration information for the specified ADC.
1578 * @retval None
1579 */
HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef * hadc)1580 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
1581 {
1582 /* Prevent unused argument(s) compilation warning */
1583 UNUSED(hadc);
1584 /* NOTE : This function Should not be modified, when the callback is needed,
1585 the HAL_ADC_ConvCpltCallback could be implemented in the user file
1586 */
1587 }
1588
1589 /**
1590 * @brief Regular conversion half DMA transfer callback in non blocking mode
1591 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1592 * the configuration information for the specified ADC.
1593 * @retval None
1594 */
HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef * hadc)1595 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
1596 {
1597 /* Prevent unused argument(s) compilation warning */
1598 UNUSED(hadc);
1599 /* NOTE : This function Should not be modified, when the callback is needed,
1600 the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file
1601 */
1602 }
1603
1604 /**
1605 * @brief Analog watchdog callback in non blocking mode
1606 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1607 * the configuration information for the specified ADC.
1608 * @retval None
1609 */
HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef * hadc)1610 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
1611 {
1612 /* Prevent unused argument(s) compilation warning */
1613 UNUSED(hadc);
1614 /* NOTE : This function Should not be modified, when the callback is needed,
1615 the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file
1616 */
1617 }
1618
1619 /**
1620 * @brief Error ADC callback.
1621 * @note In case of error due to overrun when using ADC with DMA transfer
1622 * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
1623 * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
1624 * - If needed, restart a new ADC conversion using function
1625 * "HAL_ADC_Start_DMA()"
1626 * (this function is also clearing overrun flag)
1627 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1628 * the configuration information for the specified ADC.
1629 * @retval None
1630 */
HAL_ADC_ErrorCallback(ADC_HandleTypeDef * hadc)1631 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
1632 {
1633 /* Prevent unused argument(s) compilation warning */
1634 UNUSED(hadc);
1635 /* NOTE : This function Should not be modified, when the callback is needed,
1636 the HAL_ADC_ErrorCallback could be implemented in the user file
1637 */
1638 }
1639
1640 /**
1641 * @}
1642 */
1643
1644 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
1645 * @brief Peripheral Control functions
1646 *
1647 @verbatim
1648 ===============================================================================
1649 ##### Peripheral Control functions #####
1650 ===============================================================================
1651 [..] This section provides functions allowing to:
1652 (+) Configure regular channels.
1653 (+) Configure injected channels.
1654 (+) Configure multimode.
1655 (+) Configure the analog watch dog.
1656
1657 @endverbatim
1658 * @{
1659 */
1660
1661 /**
1662 * @brief Configures for the selected ADC regular channel its corresponding
1663 * rank in the sequencer and its sample time.
1664 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1665 * the configuration information for the specified ADC.
1666 * @param sConfig ADC configuration structure.
1667 * @retval HAL status
1668 */
HAL_ADC_ConfigChannel(ADC_HandleTypeDef * hadc,ADC_ChannelConfTypeDef * sConfig)1669 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
1670 {
1671 __IO uint32_t counter = 0U;
1672 ADC_Common_TypeDef *tmpADC_Common;
1673
1674 /* Check the parameters */
1675 assert_param(IS_ADC_CHANNEL(sConfig->Channel));
1676 assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
1677 assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
1678
1679 /* Process locked */
1680 __HAL_LOCK(hadc);
1681
1682 /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
1683 if (sConfig->Channel > ADC_CHANNEL_9)
1684 {
1685 /* Clear the old sample time */
1686 hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
1687
1688 /* Set the new sample time */
1689 hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
1690 }
1691 else /* ADC_Channel include in ADC_Channel_[0..9] */
1692 {
1693 /* Clear the old sample time */
1694 hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
1695
1696 /* Set the new sample time */
1697 hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
1698 }
1699
1700 /* For Rank 1 to 6 */
1701 if (sConfig->Rank < 7U)
1702 {
1703 /* Clear the old SQx bits for the selected rank */
1704 hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
1705
1706 /* Set the SQx bits for the selected rank */
1707 hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
1708 }
1709 /* For Rank 7 to 12 */
1710 else if (sConfig->Rank < 13U)
1711 {
1712 /* Clear the old SQx bits for the selected rank */
1713 hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
1714
1715 /* Set the SQx bits for the selected rank */
1716 hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
1717 }
1718 /* For Rank 13 to 16 */
1719 else
1720 {
1721 /* Clear the old SQx bits for the selected rank */
1722 hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
1723
1724 /* Set the SQx bits for the selected rank */
1725 hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
1726 }
1727
1728 /* Pointer to the common control register to which is belonging hadc */
1729 /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
1730 /* control register) */
1731 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
1732
1733 /* if ADC1 Channel_18 is selected for VBAT Channel ennable VBATE */
1734 if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
1735 {
1736 /* Disable the TEMPSENSOR channel in case of using board with multiplixed ADC_CHANNEL_VBAT & ADC_CHANNEL_TEMPSENSOR*/
1737 if ((uint16_t)ADC_CHANNEL_TEMPSENSOR == (uint16_t)ADC_CHANNEL_VBAT)
1738 {
1739 tmpADC_Common->CCR &= ~ADC_CCR_TSVREFE;
1740 }
1741 /* Enable the VBAT channel*/
1742 tmpADC_Common->CCR |= ADC_CCR_VBATE;
1743 }
1744
1745 /* if ADC1 Channel_16 or Channel_18 is selected for Temperature sensor or
1746 Channel_17 is selected for VREFINT enable TSVREFE */
1747 if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
1748 {
1749 /* Disable the VBAT channel in case of using board with multiplixed ADC_CHANNEL_VBAT & ADC_CHANNEL_TEMPSENSOR*/
1750 if ((uint16_t)ADC_CHANNEL_TEMPSENSOR == (uint16_t)ADC_CHANNEL_VBAT)
1751 {
1752 tmpADC_Common->CCR &= ~ADC_CCR_VBATE;
1753 }
1754 /* Enable the Temperature sensor and VREFINT channel*/
1755 tmpADC_Common->CCR |= ADC_CCR_TSVREFE;
1756
1757 if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
1758 {
1759 /* Delay for temperature sensor stabilization time */
1760 /* Compute number of CPU cycles to wait for */
1761 counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
1762 while (counter != 0U)
1763 {
1764 counter--;
1765 }
1766 }
1767 }
1768
1769 /* Process unlocked */
1770 __HAL_UNLOCK(hadc);
1771
1772 /* Return function status */
1773 return HAL_OK;
1774 }
1775
1776 /**
1777 * @brief Configures the analog watchdog.
1778 * @note Analog watchdog thresholds can be modified while ADC conversion
1779 * is on going.
1780 * In this case, some constraints must be taken into account:
1781 * The programmed threshold values are effective from the next
1782 * ADC EOC (end of unitary conversion).
1783 * Considering that registers write delay may happen due to
1784 * bus activity, this might cause an uncertainty on the
1785 * effective timing of the new programmed threshold values.
1786 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1787 * the configuration information for the specified ADC.
1788 * @param AnalogWDGConfig pointer to an ADC_AnalogWDGConfTypeDef structure
1789 * that contains the configuration information of ADC analog watchdog.
1790 * @retval HAL status
1791 */
HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef * hadc,ADC_AnalogWDGConfTypeDef * AnalogWDGConfig)1792 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
1793 {
1794 #ifdef USE_FULL_ASSERT
1795 uint32_t tmp = 0U;
1796 #endif /* USE_FULL_ASSERT */
1797
1798 /* Check the parameters */
1799 assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode));
1800 assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
1801 assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
1802
1803 #ifdef USE_FULL_ASSERT
1804 tmp = ADC_GET_RESOLUTION(hadc);
1805 assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold));
1806 assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold));
1807 #endif /* USE_FULL_ASSERT */
1808
1809 /* Process locked */
1810 __HAL_LOCK(hadc);
1811
1812 if (AnalogWDGConfig->ITMode == ENABLE)
1813 {
1814 /* Enable the ADC Analog watchdog interrupt */
1815 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
1816 }
1817 else
1818 {
1819 /* Disable the ADC Analog watchdog interrupt */
1820 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
1821 }
1822
1823 /* Clear AWDEN, JAWDEN and AWDSGL bits */
1824 hadc->Instance->CR1 &= ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN);
1825
1826 /* Set the analog watchdog enable mode */
1827 hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode;
1828
1829 /* Set the high threshold */
1830 hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;
1831
1832 /* Set the low threshold */
1833 hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;
1834
1835 /* Clear the Analog watchdog channel select bits */
1836 hadc->Instance->CR1 &= ~ADC_CR1_AWDCH;
1837
1838 /* Set the Analog watchdog channel */
1839 hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel));
1840
1841 /* Process unlocked */
1842 __HAL_UNLOCK(hadc);
1843
1844 /* Return function status */
1845 return HAL_OK;
1846 }
1847
1848 /**
1849 * @}
1850 */
1851
1852 /** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions
1853 * @brief ADC Peripheral State functions
1854 *
1855 @verbatim
1856 ===============================================================================
1857 ##### Peripheral State and errors functions #####
1858 ===============================================================================
1859 [..]
1860 This subsection provides functions allowing to
1861 (+) Check the ADC state
1862 (+) Check the ADC Error
1863
1864 @endverbatim
1865 * @{
1866 */
1867
1868 /**
1869 * @brief return the ADC state
1870 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1871 * the configuration information for the specified ADC.
1872 * @retval HAL state
1873 */
HAL_ADC_GetState(ADC_HandleTypeDef * hadc)1874 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc)
1875 {
1876 /* Return ADC state */
1877 return hadc->State;
1878 }
1879
1880 /**
1881 * @brief Return the ADC error code
1882 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1883 * the configuration information for the specified ADC.
1884 * @retval ADC Error Code
1885 */
HAL_ADC_GetError(ADC_HandleTypeDef * hadc)1886 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
1887 {
1888 return hadc->ErrorCode;
1889 }
1890
1891 /**
1892 * @}
1893 */
1894
1895 /** @addtogroup ADC_Private_Functions
1896 * @{
1897 */
1898
1899 /**
1900 * @brief Initializes the ADCx peripheral according to the specified parameters
1901 * in the ADC_InitStruct without initializing the ADC MSP.
1902 * @param hadc pointer to a ADC_HandleTypeDef structure that contains
1903 * the configuration information for the specified ADC.
1904 * @retval None
1905 */
ADC_Init(ADC_HandleTypeDef * hadc)1906 static void ADC_Init(ADC_HandleTypeDef *hadc)
1907 {
1908 ADC_Common_TypeDef *tmpADC_Common;
1909
1910 /* Set ADC parameters */
1911 /* Pointer to the common control register to which is belonging hadc */
1912 /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
1913 /* control register) */
1914 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
1915
1916 /* Set the ADC clock prescaler */
1917 tmpADC_Common->CCR &= ~(ADC_CCR_ADCPRE);
1918 tmpADC_Common->CCR |= hadc->Init.ClockPrescaler;
1919
1920 /* Set ADC scan mode */
1921 hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
1922 hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
1923
1924 /* Set ADC resolution */
1925 hadc->Instance->CR1 &= ~(ADC_CR1_RES);
1926 hadc->Instance->CR1 |= hadc->Init.Resolution;
1927
1928 /* Set ADC data alignment */
1929 hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
1930 hadc->Instance->CR2 |= hadc->Init.DataAlign;
1931
1932 /* Enable external trigger if trigger selection is different of software */
1933 /* start. */
1934 /* Note: This configuration keeps the hardware feature of parameter */
1935 /* ExternalTrigConvEdge "trigger edge none" equivalent to */
1936 /* software start. */
1937 if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
1938 {
1939 /* Select external trigger to start conversion */
1940 hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
1941 hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
1942
1943 /* Select external trigger polarity */
1944 hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
1945 hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
1946 }
1947 else
1948 {
1949 /* Reset the external trigger */
1950 hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
1951 hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
1952 }
1953
1954 /* Enable or disable ADC continuous conversion mode */
1955 hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
1956 hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode);
1957
1958 if (hadc->Init.DiscontinuousConvMode != DISABLE)
1959 {
1960 assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
1961
1962 /* Enable the selected ADC regular discontinuous mode */
1963 hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;
1964
1965 /* Set the number of channels to be converted in discontinuous mode */
1966 hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
1967 hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
1968 }
1969 else
1970 {
1971 /* Disable the selected ADC regular discontinuous mode */
1972 hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);
1973 }
1974
1975 /* Set ADC number of conversion */
1976 hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
1977 hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion);
1978
1979 /* Enable or disable ADC DMA continuous request */
1980 hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
1981 hadc->Instance->CR2 |= ADC_CR2_DMAContReq((uint32_t)hadc->Init.DMAContinuousRequests);
1982
1983 /* Enable or disable ADC end of conversion selection */
1984 hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
1985 hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
1986 }
1987
1988 /**
1989 * @brief DMA transfer complete callback.
1990 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1991 * the configuration information for the specified DMA module.
1992 * @retval None
1993 */
ADC_DMAConvCplt(DMA_HandleTypeDef * hdma)1994 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
1995 {
1996 /* Retrieve ADC handle corresponding to current DMA handle */
1997 ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1998
1999 /* Update state machine on conversion status if not in error state */
2000 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
2001 {
2002 /* Update ADC state machine */
2003 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
2004
2005 /* Determine whether any further conversion upcoming on group regular */
2006 /* by external trigger, continuous mode or scan sequence on going. */
2007 /* Note: On STM32F4, there is no independent flag of end of sequence. */
2008 /* The test of scan sequence on going is done either with scan */
2009 /* sequence disabled or with end of conversion flag set to */
2010 /* of end of sequence. */
2011 if (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
2012 (hadc->Init.ContinuousConvMode == DISABLE) &&
2013 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
2014 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)))
2015 {
2016 /* Disable ADC end of single conversion interrupt on group regular */
2017 /* Note: Overrun interrupt was enabled with EOC interrupt in */
2018 /* HAL_ADC_Start_IT(), but is not disabled here because can be used */
2019 /* by overrun IRQ process below. */
2020 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
2021
2022 /* Set ADC state */
2023 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
2024
2025 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
2026 {
2027 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
2028 }
2029 }
2030
2031 /* Conversion complete callback */
2032 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2033 hadc->ConvCpltCallback(hadc);
2034 #else
2035 HAL_ADC_ConvCpltCallback(hadc);
2036 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2037 }
2038 else /* DMA and-or internal error occurred */
2039 {
2040 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
2041 {
2042 /* Call HAL ADC Error Callback function */
2043 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2044 hadc->ErrorCallback(hadc);
2045 #else
2046 HAL_ADC_ErrorCallback(hadc);
2047 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2048 }
2049 else
2050 {
2051 /* Call DMA error callback */
2052 hadc->DMA_Handle->XferErrorCallback(hdma);
2053 }
2054 }
2055 }
2056
2057 /**
2058 * @brief DMA half transfer complete callback.
2059 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2060 * the configuration information for the specified DMA module.
2061 * @retval None
2062 */
ADC_DMAHalfConvCplt(DMA_HandleTypeDef * hdma)2063 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
2064 {
2065 ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2066 /* Half conversion callback */
2067 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2068 hadc->ConvHalfCpltCallback(hadc);
2069 #else
2070 HAL_ADC_ConvHalfCpltCallback(hadc);
2071 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2072 }
2073
2074 /**
2075 * @brief DMA error callback
2076 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2077 * the configuration information for the specified DMA module.
2078 * @retval None
2079 */
ADC_DMAError(DMA_HandleTypeDef * hdma)2080 static void ADC_DMAError(DMA_HandleTypeDef *hdma)
2081 {
2082 ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2083 hadc->State = HAL_ADC_STATE_ERROR_DMA;
2084 /* Set ADC error code to DMA error */
2085 hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
2086 /* Error callback */
2087 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2088 hadc->ErrorCallback(hadc);
2089 #else
2090 HAL_ADC_ErrorCallback(hadc);
2091 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2092 }
2093
2094 /**
2095 * @}
2096 */
2097
2098 /**
2099 * @}
2100 */
2101
2102 #endif /* HAL_ADC_MODULE_ENABLED */
2103 /**
2104 * @}
2105 */
2106
2107 /**
2108 * @}
2109 */
2110
2111
