1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32f3xx_ll_tim.h"
22 #include "stm32f3xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32F3xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM18) || defined (TIM19) || defined (TIM20)
35
36 /** @addtogroup TIM_LL
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /** @addtogroup TIM_LL_Private_Macros
45 * @{
46 */
47 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
48 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
49 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
50 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
51 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
52
53 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
54 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
55 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
56
57 #if defined(TIM_CCMR1_OC1M_3)
58 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
59 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
60 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
61 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
62 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
63 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
64 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
65 || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
66 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
67 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
68 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
69 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
70 || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \
71 || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2))
72 #else
73 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
74 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
75 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
76 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
77 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
78 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
79 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
80 || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
81 #endif /* TIM_CCMR1_OC1M_3 */
82
83 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
84 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
85
86 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
87 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
88
89 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
90 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
91
92 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
93 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
94 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
95
96 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
97 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
98 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
99 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
100
101 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
102 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
103 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
104 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
105 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
106 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
107 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
108 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
109 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
110 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
111 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
112 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
113 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
114 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
115 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
116 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
117
118 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
119 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
120 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
121
122 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
123 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
124 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
125
126 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
127 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
128
129 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
130 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
131
132 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
133 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
134
135 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
136 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
137 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
138 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
139
140 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
141 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
142
143 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
144 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
145 #if defined(TIM_BDTR_BKF)
146
147 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
148 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
149 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
150 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
151 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
152 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
153 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
154 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
155 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
156 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
157 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
158 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
159 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
160 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
161 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
162 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
163 #endif /* TIM_BDTR_BKF */
164 #if defined(TIM_BDTR_BK2E)
165
166 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
167 || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
168
169 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
170 || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
171
172 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
173 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
174 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
175 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
176 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
177 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
178 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
179 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
180 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
181 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
182 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
183 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
184 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
185 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
186 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
187 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
188 #endif /* TIM_BDTR_BK2E */
189
190 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
191 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
192 /**
193 * @}
194 */
195
196
197 /* Private function prototypes -----------------------------------------------*/
198 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
199 * @{
200 */
201 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
202 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
203 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
204 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
205 #if defined(TIM_CCER_CC5E)
206 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
207 #endif /* TIM_CCER_CC5E */
208 #if defined(TIM_CCER_CC6E)
209 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
210 #endif /* TIM_CCER_CC6E */
211 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
212 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
213 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
214 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
215 /**
216 * @}
217 */
218
219 /* Exported functions --------------------------------------------------------*/
220 /** @addtogroup TIM_LL_Exported_Functions
221 * @{
222 */
223
224 /** @addtogroup TIM_LL_EF_Init
225 * @{
226 */
227
228 /**
229 * @brief Set TIMx registers to their reset values.
230 * @param TIMx Timer instance
231 * @retval An ErrorStatus enumeration value:
232 * - SUCCESS: TIMx registers are de-initialized
233 * - ERROR: invalid TIMx instance
234 */
LL_TIM_DeInit(const TIM_TypeDef * TIMx)235 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)
236 {
237 ErrorStatus result = SUCCESS;
238
239 /* Check the parameters */
240 assert_param(IS_TIM_INSTANCE(TIMx));
241
242
243 if (TIMx == TIM2)
244 {
245 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
246 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
247 }
248
249 #if defined(TIM1)
250 else if (TIMx == TIM1)
251 {
252 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
253 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
254 }
255 #endif /* TIM1 */
256 #if defined(TIM3)
257 else if (TIMx == TIM3)
258 {
259 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
260 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
261 }
262 #endif /* TIM3 */
263 #if defined(TIM4)
264 else if (TIMx == TIM4)
265 {
266 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
267 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
268 }
269 #endif /* TIM4 */
270 #if defined(TIM5)
271 else if (TIMx == TIM5)
272 {
273 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
274 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
275 }
276 #endif /* TIM5 */
277 #if defined(TIM6)
278 else if (TIMx == TIM6)
279 {
280 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
281 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
282 }
283 #endif /* TIM6 */
284 #if defined(TIM7)
285 else if (TIMx == TIM7)
286 {
287 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
288 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
289 }
290 #endif /* TIM7 */
291 #if defined(TIM8)
292 else if (TIMx == TIM8)
293 {
294 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
295 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
296 }
297 #endif /* TIM8 */
298 #if defined(TIM12)
299 else if (TIMx == TIM12)
300 {
301 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
302 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
303 }
304 #endif /* TIM12 */
305 #if defined(TIM13)
306 else if (TIMx == TIM13)
307 {
308 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
309 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
310 }
311 #endif /* TIM13 */
312 #if defined(TIM14)
313 else if (TIMx == TIM14)
314 {
315 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
316 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
317 }
318 #endif /* TIM14 */
319 #if defined(TIM15)
320 else if (TIMx == TIM15)
321 {
322 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
323 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
324 }
325 #endif /* TIM15 */
326 #if defined(TIM16)
327 else if (TIMx == TIM16)
328 {
329 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
330 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
331 }
332 #endif /* TIM16 */
333 #if defined(TIM17)
334 else if (TIMx == TIM17)
335 {
336 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
337 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
338 }
339 #endif /* TIM17 */
340 #if defined(TIM18)
341 else if (TIMx == TIM18)
342 {
343 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM18);
344 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM18);
345 }
346 #endif /* TIM18 */
347 #if defined(TIM19)
348 else if (TIMx == TIM19)
349 {
350 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM19);
351 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM19);
352 }
353 #endif /* TIM19 */
354 #if defined(TIM20)
355 else if (TIMx == TIM20)
356 {
357 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM20);
358 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM20);
359 }
360 #endif /* TIM20 */
361 else
362 {
363 result = ERROR;
364 }
365
366 return result;
367 }
368
369 /**
370 * @brief Set the fields of the time base unit configuration data structure
371 * to their default values.
372 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
373 * @retval None
374 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)375 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
376 {
377 /* Set the default configuration */
378 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
379 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
380 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
381 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
382 TIM_InitStruct->RepetitionCounter = 0x00000000U;
383 }
384
385 /**
386 * @brief Configure the TIMx time base unit.
387 * @param TIMx Timer Instance
388 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
389 * (TIMx time base unit configuration data structure)
390 * @retval An ErrorStatus enumeration value:
391 * - SUCCESS: TIMx registers are de-initialized
392 * - ERROR: not applicable
393 */
LL_TIM_Init(TIM_TypeDef * TIMx,const LL_TIM_InitTypeDef * TIM_InitStruct)394 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
395 {
396 uint32_t tmpcr1;
397
398 /* Check the parameters */
399 assert_param(IS_TIM_INSTANCE(TIMx));
400 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
401 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
402
403 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
404
405 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
406 {
407 /* Select the Counter Mode */
408 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
409 }
410
411 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
412 {
413 /* Set the clock division */
414 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
415 }
416
417 /* Write to TIMx CR1 */
418 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
419
420 /* Set the Autoreload value */
421 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
422
423 /* Set the Prescaler value */
424 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
425
426 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
427 {
428 /* Set the Repetition Counter value */
429 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
430 }
431
432 /* Generate an update event to reload the Prescaler
433 and the repetition counter value (if applicable) immediately */
434 LL_TIM_GenerateEvent_UPDATE(TIMx);
435
436 return SUCCESS;
437 }
438
439 /**
440 * @brief Set the fields of the TIMx output channel configuration data
441 * structure to their default values.
442 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
443 * (the output channel configuration data structure)
444 * @retval None
445 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)446 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
447 {
448 /* Set the default configuration */
449 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
450 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
451 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
452 TIM_OC_InitStruct->CompareValue = 0x00000000U;
453 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
454 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
455 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
456 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
457 }
458
459 /**
460 * @brief Configure the TIMx output channel.
461 * @param TIMx Timer Instance
462 * @param Channel This parameter can be one of the following values:
463 * @arg @ref LL_TIM_CHANNEL_CH1
464 * @arg @ref LL_TIM_CHANNEL_CH2
465 * @arg @ref LL_TIM_CHANNEL_CH3
466 * @arg @ref LL_TIM_CHANNEL_CH4
467 * @arg @ref LL_TIM_CHANNEL_CH5
468 * @arg @ref LL_TIM_CHANNEL_CH6
469 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
470 * data structure)
471 * @note OC5 and OC6 are not available for all F3 devices
472 * @retval An ErrorStatus enumeration value:
473 * - SUCCESS: TIMx output channel is initialized
474 * - ERROR: TIMx output channel is not initialized
475 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)476 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
477 {
478 ErrorStatus result = ERROR;
479
480 switch (Channel)
481 {
482 case LL_TIM_CHANNEL_CH1:
483 result = OC1Config(TIMx, TIM_OC_InitStruct);
484 break;
485 case LL_TIM_CHANNEL_CH2:
486 result = OC2Config(TIMx, TIM_OC_InitStruct);
487 break;
488 case LL_TIM_CHANNEL_CH3:
489 result = OC3Config(TIMx, TIM_OC_InitStruct);
490 break;
491 case LL_TIM_CHANNEL_CH4:
492 result = OC4Config(TIMx, TIM_OC_InitStruct);
493 break;
494 #if defined(TIM_CCER_CC5E)
495 case LL_TIM_CHANNEL_CH5:
496 result = OC5Config(TIMx, TIM_OC_InitStruct);
497 break;
498 #endif /* TIM_CCER_CC5E */
499 #if defined(TIM_CCER_CC6E)
500 case LL_TIM_CHANNEL_CH6:
501 result = OC6Config(TIMx, TIM_OC_InitStruct);
502 break;
503 #endif /* TIM_CCER_CC6E */
504 default:
505 break;
506 }
507
508 return result;
509 }
510
511 /**
512 * @brief Set the fields of the TIMx input channel configuration data
513 * structure to their default values.
514 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
515 * data structure)
516 * @retval None
517 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)518 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
519 {
520 /* Set the default configuration */
521 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
522 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
523 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
524 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
525 }
526
527 /**
528 * @brief Configure the TIMx input channel.
529 * @param TIMx Timer Instance
530 * @param Channel This parameter can be one of the following values:
531 * @arg @ref LL_TIM_CHANNEL_CH1
532 * @arg @ref LL_TIM_CHANNEL_CH2
533 * @arg @ref LL_TIM_CHANNEL_CH3
534 * @arg @ref LL_TIM_CHANNEL_CH4
535 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
536 * structure)
537 * @retval An ErrorStatus enumeration value:
538 * - SUCCESS: TIMx output channel is initialized
539 * - ERROR: TIMx output channel is not initialized
540 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)541 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
542 {
543 ErrorStatus result = ERROR;
544
545 switch (Channel)
546 {
547 case LL_TIM_CHANNEL_CH1:
548 result = IC1Config(TIMx, TIM_IC_InitStruct);
549 break;
550 case LL_TIM_CHANNEL_CH2:
551 result = IC2Config(TIMx, TIM_IC_InitStruct);
552 break;
553 case LL_TIM_CHANNEL_CH3:
554 result = IC3Config(TIMx, TIM_IC_InitStruct);
555 break;
556 case LL_TIM_CHANNEL_CH4:
557 result = IC4Config(TIMx, TIM_IC_InitStruct);
558 break;
559 default:
560 break;
561 }
562
563 return result;
564 }
565
566 /**
567 * @brief Fills each TIM_EncoderInitStruct field with its default value
568 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
569 * configuration data structure)
570 * @retval None
571 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)572 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
573 {
574 /* Set the default configuration */
575 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
576 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
577 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
578 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
579 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
580 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
581 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
582 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
583 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
584 }
585
586 /**
587 * @brief Configure the encoder interface of the timer instance.
588 * @param TIMx Timer Instance
589 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
590 * configuration data structure)
591 * @retval An ErrorStatus enumeration value:
592 * - SUCCESS: TIMx registers are de-initialized
593 * - ERROR: not applicable
594 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,const LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)595 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
596 {
597 uint32_t tmpccmr1;
598 uint32_t tmpccer;
599
600 /* Check the parameters */
601 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
602 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
603 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
604 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
605 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
606 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
607 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
608 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
609 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
610 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
611
612 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
613 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
614
615 /* Get the TIMx CCMR1 register value */
616 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
617
618 /* Get the TIMx CCER register value */
619 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
620
621 /* Configure TI1 */
622 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
623 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
624 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
625 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
626
627 /* Configure TI2 */
628 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
629 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
630 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
631 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
632
633 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
634 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
635 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
636 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
637 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
638
639 /* Set encoder mode */
640 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
641
642 /* Write to TIMx CCMR1 */
643 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
644
645 /* Write to TIMx CCER */
646 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
647
648 return SUCCESS;
649 }
650
651 #if defined TIM_CR2_MMS2
652 /**
653 * @brief Set the fields of the TIMx Hall sensor interface configuration data
654 * structure to their default values.
655 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
656 * configuration data structure)
657 * @retval None
658 */
LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)659 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
660 {
661 /* Set the default configuration */
662 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
663 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
664 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
665 TIM_HallSensorInitStruct->CommutationDelay = 0U;
666 }
667
668 /**
669 * @brief Configure the Hall sensor interface of the timer instance.
670 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
671 * to the TI1 input channel
672 * @note TIMx slave mode controller is configured in reset mode.
673 Selected internal trigger is TI1F_ED.
674 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
675 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
676 * between 2 changes on the inputs. It gives information about motor speed.
677 * @note Channel 2 is configured in output PWM 2 mode.
678 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
679 * @note OC2REF is selected as trigger output on TRGO.
680 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
681 * when TIMx operates in Hall sensor interface mode.
682 * @param TIMx Timer Instance
683 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
684 * interface configuration data structure)
685 * @retval An ErrorStatus enumeration value:
686 * - SUCCESS: TIMx registers are de-initialized
687 * - ERROR: not applicable
688 */
LL_TIM_HALLSENSOR_Init(TIM_TypeDef * TIMx,const LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)689 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
690 {
691 uint32_t tmpcr2;
692 uint32_t tmpccmr1;
693 uint32_t tmpccer;
694 uint32_t tmpsmcr;
695
696 /* Check the parameters */
697 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
698 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
699 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
700 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
701
702 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
703 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
704
705 /* Get the TIMx CR2 register value */
706 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
707
708 /* Get the TIMx CCMR1 register value */
709 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
710
711 /* Get the TIMx CCER register value */
712 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
713
714 /* Get the TIMx SMCR register value */
715 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
716
717 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
718 tmpcr2 |= TIM_CR2_TI1S;
719
720 /* OC2REF signal is used as trigger output (TRGO) */
721 tmpcr2 |= LL_TIM_TRGO_OC2REF;
722
723 /* Configure the slave mode controller */
724 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
725 tmpsmcr |= LL_TIM_TS_TI1F_ED;
726 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
727
728 /* Configure input channel 1 */
729 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
730 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
731 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
732 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
733
734 /* Configure input channel 2 */
735 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
736 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
737
738 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
739 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
740 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
741 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
742
743 /* Write to TIMx CR2 */
744 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
745
746 /* Write to TIMx SMCR */
747 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
748
749 /* Write to TIMx CCMR1 */
750 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
751
752 /* Write to TIMx CCER */
753 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
754
755 /* Write to TIMx CCR2 */
756 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
757
758 return SUCCESS;
759 }
760 #endif /* TIM_CR2_MMS2 */
761
762 /**
763 * @brief Set the fields of the Break and Dead Time configuration data structure
764 * to their default values.
765 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
766 * data structure)
767 * @retval None
768 */
LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)769 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
770 {
771 /* Set the default configuration */
772 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
773 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
774 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
775 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
776 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
777 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
778 #if defined(TIM_BDTR_BKF)
779 TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
780 #endif /* TIM_BDTR_BKF */
781 #if defined(TIM_BDTR_BK2E)
782 TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
783 TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
784 TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
785 #endif /* TIM_BDTR_BK2E */
786 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
787 }
788
789 /**
790 * @brief Configure the Break and Dead Time feature of the timer instance.
791 * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
792 * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
793 * can be necessary to configure all of them during the first write access to
794 * the TIMx_BDTR register.
795 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
796 * a timer instance provides a break input.
797 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
798 * a timer instance provides a second break input.
799 * @param TIMx Timer Instance
800 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
801 * data structure)
802 * @retval An ErrorStatus enumeration value:
803 * - SUCCESS: Break and Dead Time is initialized
804 * - ERROR: not applicable
805 */
LL_TIM_BDTR_Init(TIM_TypeDef * TIMx,const LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)806 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
807 {
808 uint32_t tmpbdtr = 0;
809
810 /* Check the parameters */
811 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
812 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
813 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
814 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
815 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
816 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
817 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
818 #if defined(TIM_BDTR_BKF)
819 assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
820 #endif /* TIM_BDTR_BKF */
821
822 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
823 the OSSI State, the dead time value and the Automatic Output Enable Bit */
824
825 /* Set the BDTR bits */
826 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
827 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
828 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
829 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
830 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
831 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
832 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
833 #if defined(TIM_BDTR_BKF)
834 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
835 #endif /* TIM_BDTR_BKF */
836 #if defined(TIM_BDTR_BK2E)
837
838 if (IS_TIM_BKIN2_INSTANCE(TIMx))
839 {
840 assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
841 assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
842 assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
843
844 /* Set the BREAK2 input related BDTR bit-fields */
845 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
846 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
847 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
848 }
849 #endif /* TIM_BDTR_BK2E */
850
851 /* Set TIMx_BDTR */
852 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
853
854 return SUCCESS;
855 }
856 /**
857 * @}
858 */
859
860 /**
861 * @}
862 */
863
864 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
865 * @brief Private functions
866 * @{
867 */
868 /**
869 * @brief Configure the TIMx output channel 1.
870 * @param TIMx Timer Instance
871 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
872 * @retval An ErrorStatus enumeration value:
873 * - SUCCESS: TIMx registers are de-initialized
874 * - ERROR: not applicable
875 */
OC1Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)876 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
877 {
878 uint32_t tmpccmr1;
879 uint32_t tmpccer;
880 uint32_t tmpcr2;
881
882 /* Check the parameters */
883 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
884 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
885 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
886 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
887
888 /* Disable the Channel 1: Reset the CC1E Bit */
889 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
890
891 /* Get the TIMx CCER register value */
892 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
893
894 /* Get the TIMx CR2 register value */
895 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
896
897 /* Get the TIMx CCMR1 register value */
898 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
899
900 /* Reset Capture/Compare selection Bits */
901 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
902
903 /* Set the Output Compare Mode */
904 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
905
906 /* Set the Output Compare Polarity */
907 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
908
909 /* Set the Output State */
910 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
911
912 if (IS_TIM_BREAK_INSTANCE(TIMx))
913 {
914 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
915 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
916 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
917 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
918
919 /* Set the complementary output Polarity */
920 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
921
922 /* Set the complementary output State */
923 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
924
925 /* Set the Output Idle state */
926 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
927
928 /* Set the complementary output Idle state */
929 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
930 }
931
932 /* Write to TIMx CR2 */
933 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
934
935 /* Write to TIMx CCMR1 */
936 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
937
938 /* Set the Capture Compare Register value */
939 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
940
941 /* Write to TIMx CCER */
942 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
943
944 return SUCCESS;
945 }
946
947 /**
948 * @brief Configure the TIMx output channel 2.
949 * @param TIMx Timer Instance
950 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
951 * @retval An ErrorStatus enumeration value:
952 * - SUCCESS: TIMx registers are de-initialized
953 * - ERROR: not applicable
954 */
OC2Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)955 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
956 {
957 uint32_t tmpccmr1;
958 uint32_t tmpccer;
959 uint32_t tmpcr2;
960
961 /* Check the parameters */
962 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
963 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
964 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
965 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
966
967 /* Disable the Channel 2: Reset the CC2E Bit */
968 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
969
970 /* Get the TIMx CCER register value */
971 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
972
973 /* Get the TIMx CR2 register value */
974 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
975
976 /* Get the TIMx CCMR1 register value */
977 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
978
979 /* Reset Capture/Compare selection Bits */
980 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
981
982 /* Select the Output Compare Mode */
983 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
984
985 /* Set the Output Compare Polarity */
986 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
987
988 /* Set the Output State */
989 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
990
991 if (IS_TIM_BREAK_INSTANCE(TIMx))
992 {
993 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
994 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
995 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
996 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
997
998 /* Set the complementary output Polarity */
999 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
1000
1001 /* Set the complementary output State */
1002 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
1003
1004 /* Set the Output Idle state */
1005 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
1006
1007 #if defined(STM32F373xC) || defined(STM32F378xx)
1008 #else
1009 /* Set the complementary output Idle state */
1010 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
1011 #endif
1012 }
1013
1014 /* Write to TIMx CR2 */
1015 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1016
1017 /* Write to TIMx CCMR1 */
1018 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
1019
1020 /* Set the Capture Compare Register value */
1021 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
1022
1023 /* Write to TIMx CCER */
1024 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1025
1026 return SUCCESS;
1027 }
1028
1029 /**
1030 * @brief Configure the TIMx output channel 3.
1031 * @param TIMx Timer Instance
1032 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
1033 * @retval An ErrorStatus enumeration value:
1034 * - SUCCESS: TIMx registers are de-initialized
1035 * - ERROR: not applicable
1036 */
OC3Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1037 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1038 {
1039 uint32_t tmpccmr2;
1040 uint32_t tmpccer;
1041 uint32_t tmpcr2;
1042
1043 /* Check the parameters */
1044 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1045 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1046 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1047 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1048
1049 /* Disable the Channel 3: Reset the CC3E Bit */
1050 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
1051
1052 /* Get the TIMx CCER register value */
1053 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1054
1055 /* Get the TIMx CR2 register value */
1056 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1057
1058 /* Get the TIMx CCMR2 register value */
1059 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1060
1061 /* Reset Capture/Compare selection Bits */
1062 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
1063
1064 /* Select the Output Compare Mode */
1065 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
1066
1067 /* Set the Output Compare Polarity */
1068 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
1069
1070 /* Set the Output State */
1071 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
1072
1073 if (IS_TIM_BREAK_INSTANCE(TIMx))
1074 {
1075 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1076 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1077 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1078 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1079
1080 /* Set the complementary output Polarity */
1081 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
1082
1083 /* Set the complementary output State */
1084 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
1085
1086 #if defined(STM32F373xC) || defined(STM32F378xx)
1087 #else
1088 /* Set the Output Idle state */
1089 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
1090
1091 /* Set the complementary output Idle state */
1092 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
1093 #endif
1094 }
1095
1096 /* Write to TIMx CR2 */
1097 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1098
1099 /* Write to TIMx CCMR2 */
1100 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1101
1102 /* Set the Capture Compare Register value */
1103 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
1104
1105 /* Write to TIMx CCER */
1106 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1107
1108 return SUCCESS;
1109 }
1110
1111 /**
1112 * @brief Configure the TIMx output channel 4.
1113 * @param TIMx Timer Instance
1114 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
1115 * @retval An ErrorStatus enumeration value:
1116 * - SUCCESS: TIMx registers are de-initialized
1117 * - ERROR: not applicable
1118 */
OC4Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1119 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1120 {
1121 uint32_t tmpccmr2;
1122 uint32_t tmpccer;
1123 uint32_t tmpcr2;
1124
1125 /* Check the parameters */
1126 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1127 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1128 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1129 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1130
1131 /* Disable the Channel 4: Reset the CC4E Bit */
1132 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1133
1134 /* Get the TIMx CCER register value */
1135 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1136
1137 /* Get the TIMx CR2 register value */
1138 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1139
1140 /* Get the TIMx CCMR2 register value */
1141 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1142
1143 /* Reset Capture/Compare selection Bits */
1144 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1145
1146 /* Select the Output Compare Mode */
1147 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1148
1149 /* Set the Output Compare Polarity */
1150 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1151
1152 /* Set the Output State */
1153 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1154
1155 if (IS_TIM_BREAK_INSTANCE(TIMx))
1156 {
1157 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1158
1159 #if defined(STM32F373xC) || defined(STM32F378xx)
1160 #else
1161 /* Set the Output Idle state */
1162 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1163 #endif
1164 }
1165
1166 /* Write to TIMx CR2 */
1167 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1168
1169 /* Write to TIMx CCMR2 */
1170 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1171
1172 /* Set the Capture Compare Register value */
1173 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1174
1175 /* Write to TIMx CCER */
1176 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1177
1178 return SUCCESS;
1179 }
1180
1181 #if defined(TIM_CCER_CC5E)
1182 /**
1183 * @brief Configure the TIMx output channel 5.
1184 * @param TIMx Timer Instance
1185 * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
1186 * @note OC5 is not available for all F3 devices
1187 * @retval An ErrorStatus enumeration value:
1188 * - SUCCESS: TIMx registers are de-initialized
1189 * - ERROR: not applicable
1190 */
OC5Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1191 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1192 {
1193 uint32_t tmpccmr3;
1194 uint32_t tmpccer;
1195
1196 /* Check the parameters */
1197 assert_param(IS_TIM_CC5_INSTANCE(TIMx));
1198 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1199 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1200 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1201 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1202 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1203
1204 /* Disable the Channel 5: Reset the CC5E Bit */
1205 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1206
1207 /* Get the TIMx CCER register value */
1208 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1209
1210 /* Get the TIMx CCMR3 register value */
1211 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1212
1213 /* Select the Output Compare Mode */
1214 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1215
1216 /* Set the Output Compare Polarity */
1217 MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1218
1219 /* Set the Output State */
1220 MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1221
1222 if (IS_TIM_BREAK_INSTANCE(TIMx))
1223 {
1224 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1225 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1226
1227 /* Set the Output Idle state */
1228 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1229
1230 }
1231
1232 /* Write to TIMx CCMR3 */
1233 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1234
1235 /* Set the Capture Compare Register value */
1236 LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1237
1238 /* Write to TIMx CCER */
1239 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1240
1241 return SUCCESS;
1242 }
1243 #endif /* TIM_CCER_CC5E */
1244
1245 #if defined(TIM_CCER_CC6E)
1246 /**
1247 * @brief Configure the TIMx output channel 6.
1248 * @param TIMx Timer Instance
1249 * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1250 * @note OC6 is not available for all F3 devices
1251 * @retval An ErrorStatus enumeration value:
1252 * - SUCCESS: TIMx registers are de-initialized
1253 * - ERROR: not applicable
1254 */
OC6Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1255 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1256 {
1257 uint32_t tmpccmr3;
1258 uint32_t tmpccer;
1259
1260 /* Check the parameters */
1261 assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1262 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1263 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1264 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1265 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1266 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1267
1268 /* Disable the Channel 5: Reset the CC6E Bit */
1269 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1270
1271 /* Get the TIMx CCER register value */
1272 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1273
1274 /* Get the TIMx CCMR3 register value */
1275 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1276
1277 /* Select the Output Compare Mode */
1278 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1279
1280 /* Set the Output Compare Polarity */
1281 MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1282
1283 /* Set the Output State */
1284 MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1285
1286 if (IS_TIM_BREAK_INSTANCE(TIMx))
1287 {
1288 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1289 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1290
1291 /* Set the Output Idle state */
1292 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1293 }
1294
1295 /* Write to TIMx CCMR3 */
1296 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1297
1298 /* Set the Capture Compare Register value */
1299 LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1300
1301 /* Write to TIMx CCER */
1302 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1303
1304 return SUCCESS;
1305 }
1306 #endif /* TIM_CCER_CC6E */
1307
1308 /**
1309 * @brief Configure the TIMx input channel 1.
1310 * @param TIMx Timer Instance
1311 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1312 * @retval An ErrorStatus enumeration value:
1313 * - SUCCESS: TIMx registers are de-initialized
1314 * - ERROR: not applicable
1315 */
IC1Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1316 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1317 {
1318 /* Check the parameters */
1319 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1320 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1321 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1322 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1323 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1324
1325 /* Disable the Channel 1: Reset the CC1E Bit */
1326 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1327
1328 /* Select the Input and set the filter and the prescaler value */
1329 MODIFY_REG(TIMx->CCMR1,
1330 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1331 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1332
1333 /* Select the Polarity and set the CC1E Bit */
1334 MODIFY_REG(TIMx->CCER,
1335 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1336 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1337
1338 return SUCCESS;
1339 }
1340
1341 /**
1342 * @brief Configure the TIMx input channel 2.
1343 * @param TIMx Timer Instance
1344 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1345 * @retval An ErrorStatus enumeration value:
1346 * - SUCCESS: TIMx registers are de-initialized
1347 * - ERROR: not applicable
1348 */
IC2Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1349 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1350 {
1351 /* Check the parameters */
1352 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1353 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1354 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1355 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1356 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1357
1358 /* Disable the Channel 2: Reset the CC2E Bit */
1359 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1360
1361 /* Select the Input and set the filter and the prescaler value */
1362 MODIFY_REG(TIMx->CCMR1,
1363 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1364 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1365
1366 /* Select the Polarity and set the CC2E Bit */
1367 MODIFY_REG(TIMx->CCER,
1368 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1369 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1370
1371 return SUCCESS;
1372 }
1373
1374 /**
1375 * @brief Configure the TIMx input channel 3.
1376 * @param TIMx Timer Instance
1377 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1378 * @retval An ErrorStatus enumeration value:
1379 * - SUCCESS: TIMx registers are de-initialized
1380 * - ERROR: not applicable
1381 */
IC3Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1382 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1383 {
1384 /* Check the parameters */
1385 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1386 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1387 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1388 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1389 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1390
1391 /* Disable the Channel 3: Reset the CC3E Bit */
1392 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1393
1394 /* Select the Input and set the filter and the prescaler value */
1395 MODIFY_REG(TIMx->CCMR2,
1396 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1397 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1398
1399 /* Select the Polarity and set the CC3E Bit */
1400 MODIFY_REG(TIMx->CCER,
1401 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1402 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1403
1404 return SUCCESS;
1405 }
1406
1407 /**
1408 * @brief Configure the TIMx input channel 4.
1409 * @param TIMx Timer Instance
1410 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1411 * @retval An ErrorStatus enumeration value:
1412 * - SUCCESS: TIMx registers are de-initialized
1413 * - ERROR: not applicable
1414 */
IC4Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1415 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1416 {
1417 /* Check the parameters */
1418 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1419 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1420 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1421 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1422 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1423
1424 /* Disable the Channel 4: Reset the CC4E Bit */
1425 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1426
1427 /* Select the Input and set the filter and the prescaler value */
1428 MODIFY_REG(TIMx->CCMR2,
1429 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1430 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1431
1432 /* Select the Polarity and set the CC4E Bit */
1433 MODIFY_REG(TIMx->CCER,
1434 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1435 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1436
1437 return SUCCESS;
1438 }
1439
1440
1441 /**
1442 * @}
1443 */
1444
1445 /**
1446 * @}
1447 */
1448
1449 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 || TIM18 || TIM19 || TIM20 */
1450
1451 /**
1452 * @}
1453 */
1454
1455 #endif /* USE_FULL_LL_DRIVER */
1456
1457
