1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_adc.c
4 * @author MCD Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32f3xx_ll_adc.h"
22 #include "stm32f3xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif
29
30 /** @addtogroup STM32F3xx_LL_Driver
31 * @{
32 */
33
34 /* Note: Devices of STM32F3 series embed 1 out of 2 different ADC IP. b */
35 /* - STM32F30x, STM32F31x, STM32F32x, STM32F33x, STM32F35x, STM32F39x: */
36 /* ADC IP 5Msamples/sec, from 1 to 4 ADC instances and other specific */
37 /* features (refer to reference manual). */
38 /* - STM32F37x: */
39 /* ADC IP 1Msamples/sec, 1 ADC instance */
40 /* This file contains the drivers of these ADC IP, located in 2 area */
41 /* delimited by compilation switches. */
42
43 #if defined(ADC5_V1_1)
44
45 #if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4)
46
47 /** @addtogroup ADC_LL ADC
48 * @{
49 */
50
51 /* Private types -------------------------------------------------------------*/
52 /* Private variables ---------------------------------------------------------*/
53 /* Private constants ---------------------------------------------------------*/
54 /** @addtogroup ADC_LL_Private_Constants
55 * @{
56 */
57
58 /* Definitions of ADC hardware constraints delays */
59 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
60 /* not timeout values: */
61 /* Timeout values for ADC operations are dependent to device clock */
62 /* configuration (system clock versus ADC clock), */
63 /* and therefore must be defined in user application. */
64 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
65 /* values definition. */
66 /* Note: ADC timeout values are defined here in CPU cycles to be independent */
67 /* of device clock setting. */
68 /* In user application, ADC timeout values should be defined with */
69 /* temporal values, in function of device clock settings. */
70 /* Highest ratio CPU clock frequency vs ADC clock frequency: */
71 /* - ADC clock from synchronous clock with AHB prescaler 512, */
72 /* APB prescaler 16, ADC prescaler 4. */
73 /* - ADC clock from asynchronous clock (PLL) with prescaler 1, */
74 /* with highest ratio CPU clock frequency vs HSI clock frequency: */
75 /* CPU clock frequency max 72MHz, PLL frequency 72MHz: ratio 1. */
76 /* Unit: CPU cycles. */
77 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U)
78 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
79 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
80
81 /**
82 * @}
83 */
84
85 /* Private macros ------------------------------------------------------------*/
86
87 /** @addtogroup ADC_LL_Private_Macros
88 * @{
89 */
90
91 /* Check of parameters for configuration of ADC hierarchical scope: */
92 /* common to several ADC instances. */
93 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
94 ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
95 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
96 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
97 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
98 )
99
100 /* Check of parameters for configuration of ADC hierarchical scope: */
101 /* ADC instance. */
102 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
103 ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
104 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
105 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
106 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
107 )
108
109 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
110 ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
111 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
112 )
113
114 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
115 ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
116 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
117 )
118
119 /* Check of parameters for configuration of ADC hierarchical scope: */
120 /* ADC group regular */
121 #if defined(STM32F303xE) || defined(STM32F398xx)
122 #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
123 ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
124 ? ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
125 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1_ADC12) \
126 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2_ADC12) \
127 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
128 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12) \
129 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO_ADC12) \
130 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12) \
131 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11_ADC12) \
132 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC12) \
133 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
134 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
135 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
136 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC12) \
137 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
138 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12) \
139 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
140 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12) \
141 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC12) \
142 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC12) \
143 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC12) \
144 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2_ADC12) \
145 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3_ADC12) \
146 ) \
147 : \
148 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
149 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1_ADC34) \
150 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3_ADC34) \
151 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
152 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1_ADC34) \
153 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO__ADC34) \
154 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34) \
155 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34) \
156 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO__ADC34) \
157 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
158 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
159 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
160 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO__ADC34) \
161 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
162 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO_ADC34) \
163 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
164 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34) \
165 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC34) \
166 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC34) \
167 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC34) \
168 ) \
169 )
170 #elif defined(STM32F303xC) || defined(STM32F358xx)
171 #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
172 ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
173 ? ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
174 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1_ADC12) \
175 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2_ADC12) \
176 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
177 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12) \
178 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO_ADC12) \
179 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12) \
180 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11_ADC12) \
181 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC12) \
182 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
183 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
184 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
185 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC12) \
186 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
187 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12) \
188 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
189 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12) \
190 ) \
191 : \
192 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
193 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1_ADC34) \
194 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3_ADC34) \
195 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
196 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1_ADC34) \
197 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO__ADC34) \
198 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34) \
199 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34) \
200 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO__ADC34) \
201 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
202 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
203 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
204 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO__ADC34) \
205 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
206 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO_ADC34) \
207 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
208 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34) \
209 ) \
210 )
211 #elif defined(STM32F303x8) || defined(STM32F328xx)
212 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
213 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
214 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
215 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
216 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
217 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
218 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
219 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
220 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
221 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
222 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
223 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
224 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
225 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
226 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
227 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
228 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
229 )
230 #elif defined(STM32F334x8)
231 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
232 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
233 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
234 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
235 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
236 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
237 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
238 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
239 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) \
240 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) \
241 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
242 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
243 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
244 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
245 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
246 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
247 )
248 #elif defined(STM32F302xC) || defined(STM32F302xE)
249 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
250 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
251 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
252 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
253 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
254 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
255 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
256 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
257 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
258 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
259 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
260 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
261 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
262 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
263 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
264 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
265 )
266 #elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
267 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
268 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
269 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
270 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
271 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
272 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
273 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
274 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
275 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
276 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
277 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
278 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
279 )
280 #endif
281
282 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
283 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
284 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
285 )
286
287 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
288 ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
289 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
290 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
291 )
292
293 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
294 ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
295 || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
296 )
297
298 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
299 ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
300 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
301 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
302 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
303 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
304 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
305 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
306 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
307 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
308 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
309 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
310 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
311 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
312 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
313 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
314 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
315 )
316
317 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
318 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
319 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
320 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
321 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
322 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
323 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
324 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
325 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
326 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
327 )
328
329 /* Check of parameters for configuration of ADC hierarchical scope: */
330 /* ADC group injected */
331 #if defined(STM32F303xE) || defined(STM32F398xx)
332 #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
333 ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
334 ? ( ((__INJ_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
335 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
336 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
337 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12) \
338 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12) \
339 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12) \
340 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12) \
341 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12) \
342 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12) \
343 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
344 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
345 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
346 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12) \
347 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
348 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12) \
349 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12) \
350 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
351 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO_ADC12) \
352 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2_ADC12) \
353 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4_ADC12) \
354 ) \
355 : \
356 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
357 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
358 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
359 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34) \
360 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34) \
361 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34) \
362 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34) \
363 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34) \
364 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
365 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
366 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
367 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34) \
368 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
369 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34) \
370 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34) \
371 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
372 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRG_ADC34) \
373 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRG2_ADC34) \
374 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2) \
375 ) \
376 )
377 #elif defined(STM32F303xC) || defined(STM32F358xx)
378 #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
379 ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
380 ? ( ((__INJ_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
381 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
382 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
383 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12) \
384 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12) \
385 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12) \
386 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12) \
387 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12) \
388 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12) \
389 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
390 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
391 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
392 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12) \
393 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
394 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12) \
395 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12) \
396 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
397 ) \
398 : \
399 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
400 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
401 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
402 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34) \
403 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34) \
404 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34) \
405 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34) \
406 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34) \
407 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
408 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
409 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
410 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34) \
411 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
412 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34) \
413 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34) \
414 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
415 ) \
416 )
417
418 #elif defined(STM32F303x8) || defined(STM32F328xx)
419 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
420 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
421 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
422 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
423 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
424 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
425 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
426 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
427 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
428 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
429 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
430 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
431 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
432 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
433 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
434 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
435 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
436 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
437 )
438 #elif defined(STM32F334x8)
439 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
440 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
441 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
442 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
443 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
444 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
445 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
446 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
447 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
448 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) \
449 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) \
450 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
451 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
452 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
453 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
454 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
455 )
456 #elif defined(STM32F302xC) || defined(STM32F302xE)
457 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
458 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
459 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
460 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
461 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
462 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
463 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
464 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
465 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
466 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
467 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
468 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
469 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
470 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
471 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
472 )
473 #elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
474 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
475 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
476 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
477 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
478 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
479 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
480 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
481 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
482 )
483 #endif
484
485 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
486 ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
487 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
488 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
489 )
490
491 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
492 ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
493 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
494 )
495
496 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
497 ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
498 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
499 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
500 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
501 )
502
503 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
504 ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
505 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
506 )
507
508 #if defined(ADC_MULTIMODE_SUPPORT)
509 /* Check of parameters for configuration of ADC hierarchical scope: */
510 /* multimode. */
511 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
512 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
513 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
514 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
515 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
516 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
517 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
518 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
519 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
520 )
521
522 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
523 ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
524 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B) \
525 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B) \
526 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B) \
527 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B) \
528 )
529
530 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
531 ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \
532 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) \
533 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) \
534 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) \
535 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \
536 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
537 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \
538 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
539 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
540 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \
541 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \
542 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \
543 )
544
545 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
546 ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
547 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
548 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
549 )
550
551 #endif /* ADC_MULTIMODE_SUPPORT */
552 /**
553 * @}
554 */
555
556
557 /* Private function prototypes -----------------------------------------------*/
558
559 /* Exported functions --------------------------------------------------------*/
560 /** @addtogroup ADC_LL_Exported_Functions
561 * @{
562 */
563
564 /** @addtogroup ADC_LL_EF_Init
565 * @{
566 */
567
568 /**
569 * @brief De-initialize registers of all ADC instances belonging to
570 * the same ADC common instance to their default reset values.
571 * @note This function is performing a hard reset, using high level
572 * clock source RCC ADC reset.
573 * Caution: On this STM32 series, if several ADC instances are available
574 * on the selected device, RCC ADC reset will reset
575 * all ADC instances belonging to the common ADC instance.
576 * To de-initialize only 1 ADC instance, use
577 * function @ref LL_ADC_DeInit().
578 * @param ADCxy_COMMON ADC common instance
579 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
580 * @retval An ErrorStatus enumeration value:
581 * - SUCCESS: ADC common registers are de-initialized
582 * - ERROR: not applicable
583 */
LL_ADC_CommonDeInit(ADC_Common_TypeDef * ADCxy_COMMON)584 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
585 {
586 /* Check the parameters */
587 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
588
589 /* Force reset of ADC clock (core clock) */
590 #if defined(ADC1) && defined(ADC2) && defined(ADC3) && defined(ADC4)
591 if(ADCxy_COMMON == ADC12_COMMON)
592 {
593 LL_AHB1_GRP1_ForceReset (LL_AHB1_GRP1_PERIPH_ADC12);
594 }
595 else
596 {
597 LL_AHB1_GRP1_ForceReset (LL_AHB1_GRP1_PERIPH_ADC34);
598 }
599 #elif defined(ADC1) && defined(ADC2)
600 LL_AHB1_GRP1_ForceReset (LL_AHB1_GRP1_PERIPH_ADC12);
601 #elif defined(ADC1)
602 LL_AHB1_GRP1_ForceReset (LL_AHB1_GRP1_PERIPH_ADC1);
603 #endif
604
605 /* Release reset of ADC clock (core clock) */
606 #if defined(ADC1) && defined(ADC2) && defined(ADC3) && defined(ADC4)
607 if(ADCxy_COMMON == ADC12_COMMON)
608 {
609 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC12);
610 }
611 else
612 {
613 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC34);
614 }
615 #elif defined(ADC1) && defined(ADC2)
616 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC12);
617 #elif defined(ADC1)
618 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC1);
619 #endif
620
621 return SUCCESS;
622 }
623
624 /**
625 * @brief Initialize some features of ADC common parameters
626 * (all ADC instances belonging to the same ADC common instance)
627 * and multimode (for devices with several ADC instances available).
628 * @note The setting of ADC common parameters is conditioned to
629 * ADC instances state:
630 * All ADC instances belonging to the same ADC common instance
631 * must be disabled.
632 * @param ADCxy_COMMON ADC common instance
633 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
634 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
635 * @retval An ErrorStatus enumeration value:
636 * - SUCCESS: ADC common registers are initialized
637 * - ERROR: ADC common registers are not initialized
638 */
LL_ADC_CommonInit(ADC_Common_TypeDef * ADCxy_COMMON,LL_ADC_CommonInitTypeDef * ADC_CommonInitStruct)639 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
640 {
641 ErrorStatus status = SUCCESS;
642
643 /* Check the parameters */
644 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
645 assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
646
647 #if defined(ADC_MULTIMODE_SUPPORT)
648 assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
649 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
650 {
651 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
652 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
653 }
654 #endif /* ADC_MULTIMODE_SUPPORT */
655
656 /* Note: Hardware constraint (refer to description of functions */
657 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
658 /* On this STM32 series, setting of these features is conditioned to */
659 /* ADC state: */
660 /* All ADC instances of the ADC common group must be disabled. */
661 if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
662 {
663 /* Configuration of ADC hierarchical scope: */
664 /* - common to several ADC */
665 /* (all ADC instances belonging to the same ADC common instance) */
666 /* - Set ADC clock (conversion clock) */
667 /* - multimode (if several ADC instances available on the */
668 /* selected device) */
669 /* - Set ADC multimode configuration */
670 /* - Set ADC multimode DMA transfer */
671 /* - Set ADC multimode: delay between 2 sampling phases */
672 #if defined(ADC_MULTIMODE_SUPPORT)
673 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
674 {
675 MODIFY_REG(ADCxy_COMMON->CCR,
676 ADC_CCR_CKMODE
677 | ADC_CCR_DUAL
678 | ADC_CCR_MDMA
679 | ADC_CCR_DELAY
680 ,
681 ADC_CommonInitStruct->CommonClock
682 | ADC_CommonInitStruct->Multimode
683 | ADC_CommonInitStruct->MultiDMATransfer
684 | ADC_CommonInitStruct->MultiTwoSamplingDelay
685 );
686 }
687 else
688 {
689 MODIFY_REG(ADCxy_COMMON->CCR,
690 ADC_CCR_CKMODE
691 | ADC_CCR_DUAL
692 | ADC_CCR_MDMA
693 | ADC_CCR_DELAY
694 ,
695 ADC_CommonInitStruct->CommonClock
696 | LL_ADC_MULTI_INDEPENDENT
697 );
698 }
699 #else
700 LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
701 #endif
702 }
703 else
704 {
705 /* Initialization error: One or several ADC instances belonging to */
706 /* the same ADC common instance are not disabled. */
707 status = ERROR;
708 }
709
710 return status;
711 }
712
713 /**
714 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
715 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
716 * whose fields will be set to default values.
717 * @retval None
718 */
LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef * ADC_CommonInitStruct)719 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
720 {
721 /* Set ADC_CommonInitStruct fields to default values */
722 /* Set fields of ADC common */
723 /* (all ADC instances belonging to the same ADC common instance) */
724 ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
725
726 #if defined(ADC_MULTIMODE_SUPPORT)
727 /* Set fields of ADC multimode */
728 ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
729 ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
730 ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE;
731 #endif /* ADC_MULTIMODE_SUPPORT */
732 }
733
734 /**
735 * @brief De-initialize registers of the selected ADC instance
736 * to their default reset values.
737 * @note To reset all ADC instances quickly (perform a hard reset),
738 * use function @ref LL_ADC_CommonDeInit().
739 * @note If this functions returns error status, it means that ADC instance
740 * is in an unknown state.
741 * In this case, perform a hard reset using high level
742 * clock source RCC ADC reset.
743 * Caution: On this STM32 series, if several ADC instances are available
744 * on the selected device, RCC ADC reset will reset
745 * all ADC instances belonging to the common ADC instance.
746 * Refer to function @ref LL_ADC_CommonDeInit().
747 * @param ADCx ADC instance
748 * @retval An ErrorStatus enumeration value:
749 * - SUCCESS: ADC registers are de-initialized
750 * - ERROR: ADC registers are not de-initialized
751 */
LL_ADC_DeInit(ADC_TypeDef * ADCx)752 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
753 {
754 ErrorStatus status = SUCCESS;
755
756 __IO uint32_t timeout_cpu_cycles = 0U;
757
758 /* Check the parameters */
759 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
760
761 /* Disable ADC instance if not already disabled. */
762 if(LL_ADC_IsEnabled(ADCx) == 1U)
763 {
764 /* Set ADC group regular trigger source to SW start to ensure to not */
765 /* have an external trigger event occurring during the conversion stop */
766 /* ADC disable process. */
767 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
768
769 /* Stop potential ADC conversion on going on ADC group regular. */
770 if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U)
771 {
772 if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U)
773 {
774 LL_ADC_REG_StopConversion(ADCx);
775 }
776 }
777
778 /* Set ADC group injected trigger source to SW start to ensure to not */
779 /* have an external trigger event occurring during the conversion stop */
780 /* ADC disable process. */
781 LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
782
783 /* Stop potential ADC conversion on going on ADC group injected. */
784 if(LL_ADC_INJ_IsConversionOngoing(ADCx) != 0U)
785 {
786 if(LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0U)
787 {
788 LL_ADC_INJ_StopConversion(ADCx);
789 }
790 }
791
792 /* Wait for ADC conversions are effectively stopped */
793 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
794 while (( LL_ADC_REG_IsStopConversionOngoing(ADCx)
795 | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1U)
796 {
797 timeout_cpu_cycles--;
798 if(timeout_cpu_cycles == 0U)
799 {
800 /* Time-out error */
801 status = ERROR;
802 }
803 }
804
805 /* Flush group injected contexts queue (register JSQR): */
806 /* Note: Bit JQM must be set to empty the contexts queue (otherwise */
807 /* contexts queue is maintained with the last active context). */
808 LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
809
810 /* Disable the ADC instance */
811 LL_ADC_Disable(ADCx);
812
813 /* Wait for ADC instance is effectively disabled */
814 timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
815 while (LL_ADC_IsDisableOngoing(ADCx) == 1U)
816 {
817 timeout_cpu_cycles--;
818 if(timeout_cpu_cycles == 0U)
819 {
820 /* Time-out error */
821 status = ERROR;
822 }
823 }
824 }
825
826 /* Check whether ADC state is compliant with expected state */
827 if(READ_BIT(ADCx->CR,
828 ( ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
829 | ADC_CR_ADDIS | ADC_CR_ADEN )
830 )
831 == 0U)
832 {
833 /* ========== Reset ADC registers ========== */
834 /* Reset register IER */
835 CLEAR_BIT(ADCx->IER,
836 ( LL_ADC_IT_ADRDY
837 | LL_ADC_IT_EOC
838 | LL_ADC_IT_EOS
839 | LL_ADC_IT_OVR
840 | LL_ADC_IT_EOSMP
841 | LL_ADC_IT_JEOC
842 | LL_ADC_IT_JEOS
843 | LL_ADC_IT_JQOVF
844 | LL_ADC_IT_AWD1
845 | LL_ADC_IT_AWD2
846 | LL_ADC_IT_AWD3 )
847 );
848
849 /* Reset register ISR */
850 SET_BIT(ADCx->ISR,
851 ( LL_ADC_FLAG_ADRDY
852 | LL_ADC_FLAG_EOC
853 | LL_ADC_FLAG_EOS
854 | LL_ADC_FLAG_OVR
855 | LL_ADC_FLAG_EOSMP
856 | LL_ADC_FLAG_JEOC
857 | LL_ADC_FLAG_JEOS
858 | LL_ADC_FLAG_JQOVF
859 | LL_ADC_FLAG_AWD1
860 | LL_ADC_FLAG_AWD2
861 | LL_ADC_FLAG_AWD3 )
862 );
863
864 /* Reset register CR */
865 /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */
866 /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */
867 /* access mode "read-set": no direct reset applicable. */
868 /* - Reset Calibration mode to default setting (single ended). */
869 /* - Disable ADC internal voltage regulator. */
870 /* Note: ADC internal voltage regulator disable is conditioned to */
871 /* ADC state disabled: already done above. */
872 /* Sequence to disable voltage regulator: */
873 /* 1. Set the intermediate state before moving the ADC voltage regulator */
874 /* to disable state. */
875 CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0 | ADC_CR_ADCALDIF);
876 /* 2. Set ADVREGEN bits to 0x10 */
877 SET_BIT(ADCx->CR, ADC_CR_ADVREGEN_1);
878
879 /* Reset register CFGR */
880 CLEAR_BIT(ADCx->CFGR,
881 ( ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN
882 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
883 | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
884 | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD
885 | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN
886 | ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN )
887 );
888
889 /* Reset register SMPR1 */
890 CLEAR_BIT(ADCx->SMPR1,
891 ( ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
892 | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
893 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
894 );
895
896 /* Reset register SMPR2 */
897 CLEAR_BIT(ADCx->SMPR2,
898 ( ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16
899 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13
900 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10)
901 );
902
903 /* Reset register TR1 */
904 MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
905
906 /* Reset register TR2 */
907 MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2);
908
909 /* Reset register TR3 */
910 MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3);
911
912 /* Reset register SQR1 */
913 CLEAR_BIT(ADCx->SQR1,
914 ( ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
915 | ADC_SQR1_SQ1 | ADC_SQR1_L)
916 );
917
918 /* Reset register SQR2 */
919 CLEAR_BIT(ADCx->SQR2,
920 ( ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
921 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
922 );
923
924 /* Reset register SQR3 */
925 CLEAR_BIT(ADCx->SQR3,
926 ( ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
927 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
928 );
929
930 /* Reset register SQR4 */
931 CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
932
933 /* Reset register JSQR */
934 CLEAR_BIT(ADCx->JSQR,
935 ( ADC_JSQR_JL
936 | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
937 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
938 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )
939 );
940
941 /* Flush ADC group injected contexts queue */
942 SET_BIT(ADCx->CFGR, ADC_CFGR_JQM);
943 CLEAR_BIT(ADCx->CFGR, ADC_CFGR_JQM);
944 /* Reset register ISR bit JQOVF (set by previous operation on JSQR) */
945 SET_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF);
946
947 /* Reset register DR */
948 /* Note: bits in access mode read only, no direct reset applicable */
949
950 /* Reset register OFR1 */
951 CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
952 /* Reset register OFR2 */
953 CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
954 /* Reset register OFR3 */
955 CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
956 /* Reset register OFR4 */
957 CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
958
959 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
960 /* Note: bits in access mode read only, no direct reset applicable */
961
962 /* Reset register AWD2CR */
963 CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
964
965 /* Reset register AWD3CR */
966 CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
967
968 /* Reset register DIFSEL */
969 CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
970
971 /* Reset register CALFACT */
972 CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
973 }
974 else
975 {
976 /* ADC instance is in an unknown state */
977 /* Need to performing a hard reset of ADC instance, using high level */
978 /* clock source RCC ADC reset. */
979 /* Caution: On this STM32 series, if several ADC instances are available */
980 /* on the selected device, RCC ADC reset will reset */
981 /* all ADC instances belonging to the common ADC instance. */
982 /* Caution: On this STM32 series, if several ADC instances are available */
983 /* on the selected device, RCC ADC reset will reset */
984 /* all ADC instances belonging to the common ADC instance. */
985 status = ERROR;
986 }
987
988 return status;
989 }
990
991 /**
992 * @brief Initialize some features of ADC instance.
993 * @note These parameters have an impact on ADC scope: ADC instance.
994 * Affects both group regular and group injected (availability
995 * of ADC group injected depends on STM32 families).
996 * Refer to corresponding unitary functions into
997 * @ref ADC_LL_EF_Configuration_ADC_Instance .
998 * @note The setting of these parameters by function @ref LL_ADC_Init()
999 * is conditioned to ADC state:
1000 * ADC instance must be disabled.
1001 * This condition is applied to all ADC features, for efficiency
1002 * and compatibility over all STM32 families. However, the different
1003 * features can be set under different ADC state conditions
1004 * (setting possible with ADC enabled without conversion on going,
1005 * ADC enabled with conversion on going, ...)
1006 * Each feature can be updated afterwards with a unitary function
1007 * and potentially with ADC in a different state than disabled,
1008 * refer to description of each function for setting
1009 * conditioned to ADC state.
1010 * @note After using this function, some other features must be configured
1011 * using LL unitary functions.
1012 * The minimum configuration remaining to be done is:
1013 * - Set ADC group regular or group injected sequencer:
1014 * map channel on the selected sequencer rank.
1015 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
1016 * - Set ADC channel sampling time
1017 * Refer to function LL_ADC_SetChannelSamplingTime();
1018 * @param ADCx ADC instance
1019 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
1020 * @retval An ErrorStatus enumeration value:
1021 * - SUCCESS: ADC registers are initialized
1022 * - ERROR: ADC registers are not initialized
1023 */
LL_ADC_Init(ADC_TypeDef * ADCx,LL_ADC_InitTypeDef * ADC_InitStruct)1024 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
1025 {
1026 ErrorStatus status = SUCCESS;
1027
1028 /* Check the parameters */
1029 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
1030
1031 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
1032 assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
1033 assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
1034
1035 /* Note: Hardware constraint (refer to description of this function): */
1036 /* ADC instance must be disabled. */
1037 if(LL_ADC_IsEnabled(ADCx) == 0U)
1038 {
1039 /* Configuration of ADC hierarchical scope: */
1040 /* - ADC instance */
1041 /* - Set ADC data resolution */
1042 /* - Set ADC conversion data alignment */
1043 /* - Set ADC low power mode */
1044 MODIFY_REG(ADCx->CFGR,
1045 ADC_CFGR_RES
1046 | ADC_CFGR_ALIGN
1047 | ADC_CFGR_AUTDLY
1048 ,
1049 ADC_InitStruct->Resolution
1050 | ADC_InitStruct->DataAlignment
1051 | ADC_InitStruct->LowPowerMode
1052 );
1053
1054 }
1055 else
1056 {
1057 /* Initialization error: ADC instance is not disabled. */
1058 status = ERROR;
1059 }
1060 return status;
1061 }
1062
1063 /**
1064 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
1065 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
1066 * whose fields will be set to default values.
1067 * @retval None
1068 */
LL_ADC_StructInit(LL_ADC_InitTypeDef * ADC_InitStruct)1069 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
1070 {
1071 /* Set ADC_InitStruct fields to default values */
1072 /* Set fields of ADC instance */
1073 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
1074 ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
1075 ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
1076
1077 }
1078
1079 /**
1080 * @brief Initialize some features of ADC group regular.
1081 * @note These parameters have an impact on ADC scope: ADC group regular.
1082 * Refer to corresponding unitary functions into
1083 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
1084 * (functions with prefix "REG").
1085 * @note The setting of these parameters by function @ref LL_ADC_Init()
1086 * is conditioned to ADC state:
1087 * ADC instance must be disabled.
1088 * This condition is applied to all ADC features, for efficiency
1089 * and compatibility over all STM32 families. However, the different
1090 * features can be set under different ADC state conditions
1091 * (setting possible with ADC enabled without conversion on going,
1092 * ADC enabled with conversion on going, ...)
1093 * Each feature can be updated afterwards with a unitary function
1094 * and potentially with ADC in a different state than disabled,
1095 * refer to description of each function for setting
1096 * conditioned to ADC state.
1097 * @note After using this function, other features must be configured
1098 * using LL unitary functions.
1099 * The minimum configuration remaining to be done is:
1100 * - Set ADC group regular or group injected sequencer:
1101 * map channel on the selected sequencer rank.
1102 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
1103 * - Set ADC channel sampling time
1104 * Refer to function LL_ADC_SetChannelSamplingTime();
1105 * @param ADCx ADC instance
1106 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
1107 * @retval An ErrorStatus enumeration value:
1108 * - SUCCESS: ADC registers are initialized
1109 * - ERROR: ADC registers are not initialized
1110 */
LL_ADC_REG_Init(ADC_TypeDef * ADCx,LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct)1111 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
1112 {
1113 ErrorStatus status = SUCCESS;
1114
1115 /* Check the parameters */
1116 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
1117 #if defined(ADC1) && defined(ADC2) && defined(ADC3) && defined(ADC4)
1118 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADCx, ADC_REG_InitStruct->TriggerSource));
1119 #else
1120 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
1121 #endif
1122 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
1123 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1124 {
1125 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
1126 }
1127 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
1128 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
1129 assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
1130
1131 /* Note: Hardware constraint (refer to description of this function): */
1132 /* ADC instance must be disabled. */
1133 if(LL_ADC_IsEnabled(ADCx) == 0U)
1134 {
1135 /* Configuration of ADC hierarchical scope: */
1136 /* - ADC group regular */
1137 /* - Set ADC group regular trigger source */
1138 /* - Set ADC group regular sequencer length */
1139 /* - Set ADC group regular sequencer discontinuous mode */
1140 /* - Set ADC group regular continuous mode */
1141 /* - Set ADC group regular conversion data transfer: no transfer or */
1142 /* transfer by DMA, and DMA requests mode */
1143 /* - Set ADC group regular overrun behavior */
1144 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
1145 /* setting of trigger source to SW start. */
1146 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1147 {
1148 MODIFY_REG(ADCx->CFGR,
1149 ADC_CFGR_EXTSEL
1150 | ADC_CFGR_EXTEN
1151 | ADC_CFGR_DISCEN
1152 | ADC_CFGR_DISCNUM
1153 | ADC_CFGR_CONT
1154 | ADC_CFGR_DMAEN
1155 | ADC_CFGR_DMACFG
1156 | ADC_CFGR_OVRMOD
1157 ,
1158 ADC_REG_InitStruct->TriggerSource
1159 | ADC_REG_InitStruct->SequencerDiscont
1160 | ADC_REG_InitStruct->ContinuousMode
1161 | ADC_REG_InitStruct->DMATransfer
1162 | ADC_REG_InitStruct->Overrun
1163 );
1164 }
1165 else
1166 {
1167 MODIFY_REG(ADCx->CFGR,
1168 ADC_CFGR_EXTSEL
1169 | ADC_CFGR_EXTEN
1170 | ADC_CFGR_DISCEN
1171 | ADC_CFGR_DISCNUM
1172 | ADC_CFGR_CONT
1173 | ADC_CFGR_DMAEN
1174 | ADC_CFGR_DMACFG
1175 | ADC_CFGR_OVRMOD
1176 ,
1177 ADC_REG_InitStruct->TriggerSource
1178 | LL_ADC_REG_SEQ_DISCONT_DISABLE
1179 | ADC_REG_InitStruct->ContinuousMode
1180 | ADC_REG_InitStruct->DMATransfer
1181 | ADC_REG_InitStruct->Overrun
1182 );
1183 }
1184
1185 /* Set ADC group regular sequencer length and scan direction */
1186 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
1187 }
1188 else
1189 {
1190 /* Initialization error: ADC instance is not disabled. */
1191 status = ERROR;
1192 }
1193 return status;
1194 }
1195
1196 /**
1197 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
1198 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
1199 * whose fields will be set to default values.
1200 * @retval None
1201 */
LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct)1202 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
1203 {
1204 /* Set ADC_REG_InitStruct fields to default values */
1205 /* Set fields of ADC group regular */
1206 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
1207 /* setting of trigger source to SW start. */
1208 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
1209 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
1210 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
1211 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
1212 ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
1213 ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
1214 }
1215
1216 /**
1217 * @brief Initialize some features of ADC group injected.
1218 * @note These parameters have an impact on ADC scope: ADC group injected.
1219 * Refer to corresponding unitary functions into
1220 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
1221 * (functions with prefix "INJ").
1222 * @note The setting of these parameters by function @ref LL_ADC_Init()
1223 * is conditioned to ADC state:
1224 * ADC instance must be disabled.
1225 * This condition is applied to all ADC features, for efficiency
1226 * and compatibility over all STM32 families. However, the different
1227 * features can be set under different ADC state conditions
1228 * (setting possible with ADC enabled without conversion on going,
1229 * ADC enabled with conversion on going, ...)
1230 * Each feature can be updated afterwards with a unitary function
1231 * and potentially with ADC in a different state than disabled,
1232 * refer to description of each function for setting
1233 * conditioned to ADC state.
1234 * @note After using this function, other features must be configured
1235 * using LL unitary functions.
1236 * The minimum configuration remaining to be done is:
1237 * - Set ADC group injected sequencer:
1238 * map channel on the selected sequencer rank.
1239 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
1240 * - Set ADC channel sampling time
1241 * Refer to function LL_ADC_SetChannelSamplingTime();
1242 * @note Caution to ADC group injected contexts queue: On this STM32 series,
1243 * using successively several times this function will appear has
1244 * having no effect.
1245 * This is due to ADC group injected contexts queue (this feature
1246 * cannot be disabled on this STM32 series).
1247 * To set several features of ADC group injected, use
1248 * function @ref LL_ADC_INJ_ConfigQueueContext().
1249 * @param ADCx ADC instance
1250 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1251 * @retval An ErrorStatus enumeration value:
1252 * - SUCCESS: ADC registers are initialized
1253 * - ERROR: ADC registers are not initialized
1254 */
LL_ADC_INJ_Init(ADC_TypeDef * ADCx,LL_ADC_INJ_InitTypeDef * ADC_INJ_InitStruct)1255 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
1256 {
1257 ErrorStatus status = SUCCESS;
1258
1259 /* Check the parameters */
1260 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
1261 #if defined(ADC1) && defined(ADC2) && defined(ADC3) && defined(ADC4)
1262 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, ADC_INJ_InitStruct->TriggerSource));
1263 #else
1264 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
1265 #endif
1266 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
1267 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
1268 {
1269 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
1270 }
1271 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
1272
1273 /* Note: Hardware constraint (refer to description of this function): */
1274 /* ADC instance must be disabled. */
1275 if(LL_ADC_IsEnabled(ADCx) == 0U)
1276 {
1277 /* Configuration of ADC hierarchical scope: */
1278 /* - ADC group injected */
1279 /* - Set ADC group injected trigger source */
1280 /* - Set ADC group injected sequencer length */
1281 /* - Set ADC group injected sequencer discontinuous mode */
1282 /* - Set ADC group injected conversion trigger: independent or */
1283 /* from ADC group regular */
1284 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
1285 /* setting of trigger source to SW start. */
1286 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1287 {
1288 MODIFY_REG(ADCx->CFGR,
1289 ADC_CFGR_JDISCEN
1290 | ADC_CFGR_JAUTO
1291 ,
1292 ADC_INJ_InitStruct->SequencerDiscont
1293 | ADC_INJ_InitStruct->TrigAuto
1294 );
1295 }
1296 else
1297 {
1298 MODIFY_REG(ADCx->CFGR,
1299 ADC_CFGR_JDISCEN
1300 | ADC_CFGR_JAUTO
1301 ,
1302 LL_ADC_REG_SEQ_DISCONT_DISABLE
1303 | ADC_INJ_InitStruct->TrigAuto
1304 );
1305 }
1306
1307 MODIFY_REG(ADCx->JSQR,
1308 ADC_JSQR_JEXTSEL
1309 | ADC_JSQR_JEXTEN
1310 | ADC_JSQR_JL
1311 ,
1312 ADC_INJ_InitStruct->TriggerSource
1313 | ADC_INJ_InitStruct->SequencerLength
1314 );
1315 }
1316 else
1317 {
1318 /* Initialization error: ADC instance is not disabled. */
1319 status = ERROR;
1320 }
1321 return status;
1322 }
1323
1324 /**
1325 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
1326 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1327 * whose fields will be set to default values.
1328 * @retval None
1329 */
LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef * ADC_INJ_InitStruct)1330 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
1331 {
1332 /* Set ADC_INJ_InitStruct fields to default values */
1333 /* Set fields of ADC group injected */
1334 ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
1335 ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
1336 ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
1337 ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
1338 }
1339
1340 /**
1341 * @}
1342 */
1343
1344 /**
1345 * @}
1346 */
1347
1348 /**
1349 * @}
1350 */
1351
1352 #endif /* ADC1 || ADC2 || ADC3 || ADC4 */
1353
1354
1355 #endif /* STM32F301x8 || STM32F302x8 || STM32F302xC || STM32F302xE || STM32F303x8 || STM32F303xC || STM32F303xE || STM32F318xx || STM32F328xx || STM32F334x8 || STM32F358xx || STM32F398xx */
1356
1357 #if defined (ADC1_V2_5)
1358
1359 #if defined (ADC1)
1360
1361 /** @addtogroup ADC_LL ADC
1362 * @{
1363 */
1364
1365 /* Private types -------------------------------------------------------------*/
1366 /* Private variables ---------------------------------------------------------*/
1367 /* Private constants ---------------------------------------------------------*/
1368 /* Private macros ------------------------------------------------------------*/
1369
1370 /** @addtogroup ADC_LL_Private_Macros
1371 * @{
1372 */
1373
1374 /* Check of parameters for configuration of ADC hierarchical scope: */
1375 /* common to several ADC instances. */
1376 /* Check of parameters for configuration of ADC hierarchical scope: */
1377 /* ADC instance. */
1378 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
1379 ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
1380 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) )
1381
1382 #define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \
1383 ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \
1384 || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) )
1385
1386 #define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \
1387 ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \
1388 || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) )
1389
1390 /* Check of parameters for configuration of ADC hierarchical scope: */
1391 /* ADC group regular */
1392 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
1393 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
1394 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
1395 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
1396 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH2) \
1397 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM19_TRGO) \
1398 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM19_CH3) \
1399 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM19_CH4) \
1400 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11))
1401
1402 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
1403 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
1404 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS))
1405
1406 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
1407 ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
1408 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED))
1409
1410 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
1411 ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
1412 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
1413 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
1414 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
1415 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
1416 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
1417 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
1418 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
1419 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
1420 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
1421 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
1422 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
1423 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
1424 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
1425 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
1426 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS))
1427
1428 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
1429 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
1430 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
1431 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
1432 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
1433 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
1434 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
1435 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
1436 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
1437 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) )
1438
1439 /* Check of parameters for configuration of ADC hierarchical scope: */
1440 /* ADC group injected */
1441 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
1442 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
1443 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
1444 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
1445 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
1446 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
1447 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM19_CH1) \
1448 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM19_CH2) \
1449 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15))
1450
1451 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
1452 ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
1453 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR))
1454
1455 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
1456 ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
1457 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
1458 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
1459 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS))
1460
1461 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
1462 ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
1463 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) )
1464
1465 /**
1466 * @}
1467 */
1468
1469
1470 /* Private function prototypes -----------------------------------------------*/
1471
1472 /* Exported functions --------------------------------------------------------*/
1473 /** @addtogroup ADC_LL_Exported_Functions
1474 * @{
1475 */
1476
1477 /** @addtogroup ADC_LL_EF_Init
1478 * @{
1479 */
1480
1481 /**
1482 * @brief De-initialize registers of all ADC instances belonging to
1483 * the same ADC common instance to their default reset values.
1484 * @param ADCxy_COMMON ADC common instance
1485 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1486 * @retval An ErrorStatus enumeration value:
1487 * - SUCCESS: ADC common registers are de-initialized
1488 * - ERROR: not applicable
1489 */
LL_ADC_CommonDeInit(ADC_Common_TypeDef * ADCxy_COMMON)1490 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
1491 {
1492 /* Check the parameters */
1493 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
1494
1495 /* Force reset of ADC clock (core clock) */
1496 LL_APB2_GRP1_ForceReset (LL_APB2_GRP1_PERIPH_ADC1);
1497
1498 /* Release reset of ADC clock (core clock) */
1499 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC1);
1500
1501 return SUCCESS;
1502 }
1503
1504 /**
1505 * @brief De-initialize registers of the selected ADC instance
1506 * to their default reset values.
1507 * @note To reset all ADC instances quickly (perform a hard reset),
1508 * use function @ref LL_ADC_CommonDeInit().
1509 * @param ADCx ADC instance
1510 * @retval An ErrorStatus enumeration value:
1511 * - SUCCESS: ADC registers are de-initialized
1512 * - ERROR: ADC registers are not de-initialized
1513 */
LL_ADC_DeInit(ADC_TypeDef * ADCx)1514 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
1515 {
1516 ErrorStatus status = SUCCESS;
1517
1518 /* Check the parameters */
1519 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
1520
1521 /* Disable ADC instance if not already disabled. */
1522 if(LL_ADC_IsEnabled(ADCx) == 1U)
1523 {
1524 /* Set ADC group regular trigger source to SW start to ensure to not */
1525 /* have an external trigger event occurring during the conversion stop */
1526 /* ADC disable process. */
1527 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
1528
1529 /* Set ADC group injected trigger source to SW start to ensure to not */
1530 /* have an external trigger event occurring during the conversion stop */
1531 /* ADC disable process. */
1532 LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
1533
1534 /* Disable the ADC instance */
1535 LL_ADC_Disable(ADCx);
1536 }
1537
1538 /* Check whether ADC state is compliant with expected state */
1539 /* (hardware requirements of bits state to reset registers below) */
1540 if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U)
1541 {
1542 /* ========== Reset ADC registers ========== */
1543 /* Reset register SR */
1544 CLEAR_BIT(ADCx->SR,
1545 ( LL_ADC_FLAG_STRT
1546 | LL_ADC_FLAG_JSTRT
1547 | LL_ADC_FLAG_EOS
1548 | LL_ADC_FLAG_JEOS
1549 | LL_ADC_FLAG_AWD1 )
1550 );
1551
1552 /* Reset register CR1 */
1553 CLEAR_BIT(ADCx->CR1,
1554 ( ADC_CR1_AWDEN | ADC_CR1_JAWDEN
1555 | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN
1556 | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN
1557 | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE
1558 | ADC_CR1_AWDCH )
1559 );
1560
1561 /* Reset register CR2 */
1562 CLEAR_BIT(ADCx->CR2,
1563 ( ADC_CR2_TSVREFE
1564 | ADC_CR2_SWSTART | ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL
1565 | ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL
1566 | ADC_CR2_ALIGN | ADC_CR2_DMA
1567 | ADC_CR2_RSTCAL | ADC_CR2_CAL
1568 | ADC_CR2_CONT | ADC_CR2_ADON )
1569 );
1570
1571 /* Reset register SMPR1 */
1572 CLEAR_BIT(ADCx->SMPR1,
1573 ( ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16
1574 | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13
1575 | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10)
1576 );
1577
1578 /* Reset register SMPR2 */
1579 CLEAR_BIT(ADCx->SMPR2,
1580 ( ADC_SMPR2_SMP9
1581 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6
1582 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3
1583 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0)
1584 );
1585
1586 /* Reset register JOFR1 */
1587 CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1);
1588 /* Reset register JOFR2 */
1589 CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2);
1590 /* Reset register JOFR3 */
1591 CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3);
1592 /* Reset register JOFR4 */
1593 CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4);
1594
1595 /* Reset register HTR */
1596 SET_BIT(ADCx->HTR, ADC_HTR_HT);
1597 /* Reset register LTR */
1598 CLEAR_BIT(ADCx->LTR, ADC_LTR_LT);
1599
1600 /* Reset register SQR1 */
1601 CLEAR_BIT(ADCx->SQR1,
1602 ( ADC_SQR1_L
1603 | ADC_SQR1_SQ16
1604 | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13)
1605 );
1606
1607 /* Reset register SQR2 */
1608 CLEAR_BIT(ADCx->SQR2,
1609 ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10
1610 | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7)
1611 );
1612
1613
1614 /* Reset register JSQR */
1615 CLEAR_BIT(ADCx->JSQR,
1616 ( ADC_JSQR_JL
1617 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
1618 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )
1619 );
1620
1621 /* Reset register DR */
1622 /* bits in access mode read only, no direct reset applicable */
1623
1624 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
1625 /* bits in access mode read only, no direct reset applicable */
1626
1627 }
1628
1629 return status;
1630 }
1631
1632 /**
1633 * @brief Initialize some features of ADC instance.
1634 * @note These parameters have an impact on ADC scope: ADC instance.
1635 * Affects both group regular and group injected (availability
1636 * of ADC group injected depends on STM32 families).
1637 * Refer to corresponding unitary functions into
1638 * @ref ADC_LL_EF_Configuration_ADC_Instance .
1639 * @note The setting of these parameters by function @ref LL_ADC_Init()
1640 * is conditioned to ADC state:
1641 * ADC instance must be disabled.
1642 * This condition is applied to all ADC features, for efficiency
1643 * and compatibility over all STM32 families. However, the different
1644 * features can be set under different ADC state conditions
1645 * (setting possible with ADC enabled without conversion on going,
1646 * ADC enabled with conversion on going, ...)
1647 * Each feature can be updated afterwards with a unitary function
1648 * and potentially with ADC in a different state than disabled,
1649 * refer to description of each function for setting
1650 * conditioned to ADC state.
1651 * @note After using this function, some other features must be configured
1652 * using LL unitary functions.
1653 * The minimum configuration remaining to be done is:
1654 * - Set ADC group regular or group injected sequencer:
1655 * map channel on the selected sequencer rank.
1656 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
1657 * - Set ADC channel sampling time
1658 * Refer to function LL_ADC_SetChannelSamplingTime();
1659 * @param ADCx ADC instance
1660 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
1661 * @retval An ErrorStatus enumeration value:
1662 * - SUCCESS: ADC registers are initialized
1663 * - ERROR: ADC registers are not initialized
1664 */
LL_ADC_Init(ADC_TypeDef * ADCx,LL_ADC_InitTypeDef * ADC_InitStruct)1665 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
1666 {
1667 ErrorStatus status = SUCCESS;
1668
1669 /* Check the parameters */
1670 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
1671
1672 assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
1673 assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode));
1674
1675 /* Note: Hardware constraint (refer to description of this function): */
1676 /* ADC instance must be disabled. */
1677 if(LL_ADC_IsEnabled(ADCx) == 0U)
1678 {
1679 /* Configuration of ADC hierarchical scope: */
1680 /* - ADC instance */
1681 /* - Set ADC conversion data alignment */
1682 MODIFY_REG(ADCx->CR1,
1683 ADC_CR1_SCAN
1684 ,
1685 ADC_InitStruct->SequencersScanMode
1686 );
1687
1688 MODIFY_REG(ADCx->CR2,
1689 ADC_CR2_ALIGN
1690 ,
1691 ADC_InitStruct->DataAlignment
1692 );
1693
1694 }
1695 else
1696 {
1697 /* Initialization error: ADC instance is not disabled. */
1698 status = ERROR;
1699 }
1700 return status;
1701 }
1702
1703 /**
1704 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
1705 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
1706 * whose fields will be set to default values.
1707 * @retval None
1708 */
LL_ADC_StructInit(LL_ADC_InitTypeDef * ADC_InitStruct)1709 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
1710 {
1711 /* Set ADC_InitStruct fields to default values */
1712 /* Set fields of ADC instance */
1713 ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
1714
1715 /* Enable scan mode to have a generic behavior with ADC of other */
1716 /* STM32 families, without this setting available: */
1717 /* ADC group regular sequencer and ADC group injected sequencer depend */
1718 /* only of their own configuration. */
1719 ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE;
1720
1721 }
1722
1723 /**
1724 * @brief Initialize some features of ADC group regular.
1725 * @note These parameters have an impact on ADC scope: ADC group regular.
1726 * Refer to corresponding unitary functions into
1727 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
1728 * (functions with prefix "REG").
1729 * @note The setting of these parameters by function @ref LL_ADC_Init()
1730 * is conditioned to ADC state:
1731 * ADC instance must be disabled.
1732 * This condition is applied to all ADC features, for efficiency
1733 * and compatibility over all STM32 families. However, the different
1734 * features can be set under different ADC state conditions
1735 * (setting possible with ADC enabled without conversion on going,
1736 * ADC enabled with conversion on going, ...)
1737 * Each feature can be updated afterwards with a unitary function
1738 * and potentially with ADC in a different state than disabled,
1739 * refer to description of each function for setting
1740 * conditioned to ADC state.
1741 * @note After using this function, other features must be configured
1742 * using LL unitary functions.
1743 * The minimum configuration remaining to be done is:
1744 * - Set ADC group regular or group injected sequencer:
1745 * map channel on the selected sequencer rank.
1746 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
1747 * - Set ADC channel sampling time
1748 * Refer to function LL_ADC_SetChannelSamplingTime();
1749 * @param ADCx ADC instance
1750 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
1751 * @retval An ErrorStatus enumeration value:
1752 * - SUCCESS: ADC registers are initialized
1753 * - ERROR: ADC registers are not initialized
1754 */
LL_ADC_REG_Init(ADC_TypeDef * ADCx,LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct)1755 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
1756 {
1757 ErrorStatus status = SUCCESS;
1758
1759 /* Check the parameters */
1760 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
1761 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
1762 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
1763 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1764 {
1765 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
1766 }
1767
1768 /* ADC group regular continuous mode and discontinuous mode */
1769 /* can not be enabled simultenaeously */
1770 assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
1771 || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
1772
1773 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
1774 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
1775
1776 /* Note: Hardware constraint (refer to description of this function): */
1777 /* ADC instance must be disabled. */
1778 if(LL_ADC_IsEnabled(ADCx) == 0U)
1779 {
1780 /* Configuration of ADC hierarchical scope: */
1781 /* - ADC group regular */
1782 /* - Set ADC group regular trigger source */
1783 /* - Set ADC group regular sequencer length */
1784 /* - Set ADC group regular sequencer discontinuous mode */
1785 /* - Set ADC group regular continuous mode */
1786 /* - Set ADC group regular conversion data transfer: no transfer or */
1787 /* transfer by DMA, and DMA requests mode */
1788 /* Note: On this STM32 series, ADC trigger edge is set when starting */
1789 /* ADC conversion. */
1790 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
1791 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1792 {
1793 MODIFY_REG(ADCx->CR1,
1794 ADC_CR1_DISCEN
1795 | ADC_CR1_DISCNUM
1796 ,
1797 ADC_REG_InitStruct->SequencerLength
1798 | ADC_REG_InitStruct->SequencerDiscont
1799 );
1800 }
1801 else
1802 {
1803 MODIFY_REG(ADCx->CR1,
1804 ADC_CR1_DISCEN
1805 | ADC_CR1_DISCNUM
1806 ,
1807 ADC_REG_InitStruct->SequencerLength
1808 | LL_ADC_REG_SEQ_DISCONT_DISABLE
1809 );
1810 }
1811
1812 MODIFY_REG(ADCx->CR2,
1813 ADC_CR2_EXTSEL
1814 | ADC_CR2_CONT
1815 | ADC_CR2_DMA
1816 ,
1817 ADC_REG_InitStruct->TriggerSource
1818 | ADC_REG_InitStruct->ContinuousMode
1819 | ADC_REG_InitStruct->DMATransfer
1820 );
1821
1822 /* Set ADC group regular sequencer length and scan direction */
1823 /* Note: Hardware constraint (refer to description of this function): */
1824 /* Note: If ADC instance feature scan mode is disabled */
1825 /* (refer to ADC instance initialization structure */
1826 /* parameter @ref SequencersScanMode */
1827 /* or function @ref LL_ADC_SetSequencersScanMode() ), */
1828 /* this parameter is discarded. */
1829 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
1830 }
1831 else
1832 {
1833 /* Initialization error: ADC instance is not disabled. */
1834 status = ERROR;
1835 }
1836 return status;
1837 }
1838
1839 /**
1840 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
1841 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
1842 * whose fields will be set to default values.
1843 * @retval None
1844 */
LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct)1845 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
1846 {
1847 /* Set ADC_REG_InitStruct fields to default values */
1848 /* Set fields of ADC group regular */
1849 /* Note: On this STM32 series, ADC trigger edge is set when starting */
1850 /* ADC conversion. */
1851 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
1852 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
1853 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
1854 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
1855 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
1856 ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
1857 }
1858
1859 /**
1860 * @brief Initialize some features of ADC group injected.
1861 * @note These parameters have an impact on ADC scope: ADC group injected.
1862 * Refer to corresponding unitary functions into
1863 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
1864 * (functions with prefix "INJ").
1865 * @note The setting of these parameters by function @ref LL_ADC_Init()
1866 * is conditioned to ADC state:
1867 * ADC instance must be disabled.
1868 * This condition is applied to all ADC features, for efficiency
1869 * and compatibility over all STM32 families. However, the different
1870 * features can be set under different ADC state conditions
1871 * (setting possible with ADC enabled without conversion on going,
1872 * ADC enabled with conversion on going, ...)
1873 * Each feature can be updated afterwards with a unitary function
1874 * and potentially with ADC in a different state than disabled,
1875 * refer to description of each function for setting
1876 * conditioned to ADC state.
1877 * @note After using this function, other features must be configured
1878 * using LL unitary functions.
1879 * The minimum configuration remaining to be done is:
1880 * - Set ADC group injected sequencer:
1881 * map channel on the selected sequencer rank.
1882 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
1883 * - Set ADC channel sampling time
1884 * Refer to function LL_ADC_SetChannelSamplingTime();
1885 * @param ADCx ADC instance
1886 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1887 * @retval An ErrorStatus enumeration value:
1888 * - SUCCESS: ADC registers are initialized
1889 * - ERROR: ADC registers are not initialized
1890 */
LL_ADC_INJ_Init(ADC_TypeDef * ADCx,LL_ADC_INJ_InitTypeDef * ADC_INJ_InitStruct)1891 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
1892 {
1893 ErrorStatus status = SUCCESS;
1894
1895 /* Check the parameters */
1896 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
1897 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
1898 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
1899 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
1900 {
1901 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
1902 }
1903 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
1904
1905 /* Note: Hardware constraint (refer to description of this function): */
1906 /* ADC instance must be disabled. */
1907 if(LL_ADC_IsEnabled(ADCx) == 0U)
1908 {
1909 /* Configuration of ADC hierarchical scope: */
1910 /* - ADC group injected */
1911 /* - Set ADC group injected trigger source */
1912 /* - Set ADC group injected sequencer length */
1913 /* - Set ADC group injected sequencer discontinuous mode */
1914 /* - Set ADC group injected conversion trigger: independent or */
1915 /* from ADC group regular */
1916 /* Note: On this STM32 series, ADC trigger edge is set when starting */
1917 /* ADC conversion. */
1918 /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */
1919 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1920 {
1921 MODIFY_REG(ADCx->CR1,
1922 ADC_CR1_JDISCEN
1923 | ADC_CR1_JAUTO
1924 ,
1925 ADC_INJ_InitStruct->SequencerDiscont
1926 | ADC_INJ_InitStruct->TrigAuto
1927 );
1928 }
1929 else
1930 {
1931 MODIFY_REG(ADCx->CR1,
1932 ADC_CR1_JDISCEN
1933 | ADC_CR1_JAUTO
1934 ,
1935 LL_ADC_REG_SEQ_DISCONT_DISABLE
1936 | ADC_INJ_InitStruct->TrigAuto
1937 );
1938 }
1939
1940 MODIFY_REG(ADCx->CR2,
1941 ADC_CR2_JEXTSEL
1942 ,
1943 ADC_INJ_InitStruct->TriggerSource
1944 );
1945
1946 /* Note: Hardware constraint (refer to description of this function): */
1947 /* Note: If ADC instance feature scan mode is disabled */
1948 /* (refer to ADC instance initialization structure */
1949 /* parameter @ref SequencersScanMode */
1950 /* or function @ref LL_ADC_SetSequencersScanMode() ), */
1951 /* this parameter is discarded. */
1952 LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength);
1953 }
1954 else
1955 {
1956 /* Initialization error: ADC instance is not disabled. */
1957 status = ERROR;
1958 }
1959 return status;
1960 }
1961
1962 /**
1963 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
1964 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1965 * whose fields will be set to default values.
1966 * @retval None
1967 */
LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef * ADC_INJ_InitStruct)1968 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
1969 {
1970 /* Set ADC_INJ_InitStruct fields to default values */
1971 /* Set fields of ADC group injected */
1972 ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
1973 ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
1974 ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
1975 ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
1976 }
1977
1978 /**
1979 * @}
1980 */
1981
1982 /**
1983 * @}
1984 */
1985
1986 /**
1987 * @}
1988 */
1989
1990 #endif /* ADC1 */
1991
1992
1993 #endif /* STM32F373xC || STM32F378xx */
1994
1995 /**
1996 * @}
1997 */
1998
1999 #endif /* USE_FULL_LL_DRIVER */
2000
2001
