1 /**
2 ******************************************************************************
3 * @file stm32f3xx_hal_tim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer (TIM) peripheral:
8 * + TIM Time Base Initialization
9 * + TIM Time Base Start
10 * + TIM Time Base Start Interruption
11 * + TIM Time Base Start DMA
12 * + TIM Output Compare/PWM Initialization
13 * + TIM Output Compare/PWM Channel Configuration
14 * + TIM Output Compare/PWM Start
15 * + TIM Output Compare/PWM Start Interruption
16 * + TIM Output Compare/PWM Start DMA
17 * + TIM Input Capture Initialization
18 * + TIM Input Capture Channel Configuration
19 * + TIM Input Capture Start
20 * + TIM Input Capture Start Interruption
21 * + TIM Input Capture Start DMA
22 * + TIM One Pulse Initialization
23 * + TIM One Pulse Channel Configuration
24 * + TIM One Pulse Start
25 * + TIM Encoder Interface Initialization
26 * + TIM Encoder Interface Start
27 * + TIM Encoder Interface Start Interruption
28 * + TIM Encoder Interface Start DMA
29 * + Commutation Event configuration with Interruption and DMA
30 * + TIM OCRef clear configuration
31 * + TIM External Clock configuration
32 ******************************************************************************
33 * @attention
34 *
35 * Copyright (c) 2016 STMicroelectronics.
36 * All rights reserved.
37 *
38 * This software is licensed under terms that can be found in the LICENSE file
39 * in the root directory of this software component.
40 * If no LICENSE file comes with this software, it is provided AS-IS.
41 *
42 ******************************************************************************
43 @verbatim
44 ==============================================================================
45 ##### TIMER Generic features #####
46 ==============================================================================
47 [..] The Timer features include:
48 (#) 16-bit up, down, up/down auto-reload counter.
49 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
50 counter clock frequency either by any factor between 1 and 65536.
51 (#) Up to 4 independent channels for:
52 (++) Input Capture
53 (++) Output Compare
54 (++) PWM generation (Edge and Center-aligned Mode)
55 (++) One-pulse mode output
56 (#) Synchronization circuit to control the timer with external signals and to interconnect
57 several timers together.
58 (#) Supports incremental encoder for positioning purposes
59
60 ##### How to use this driver #####
61 ==============================================================================
62 [..]
63 (#) Initialize the TIM low level resources by implementing the following functions
64 depending on the selected feature:
65 (++) Time Base : HAL_TIM_Base_MspInit()
66 (++) Input Capture : HAL_TIM_IC_MspInit()
67 (++) Output Compare : HAL_TIM_OC_MspInit()
68 (++) PWM generation : HAL_TIM_PWM_MspInit()
69 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
70 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
71
72 (#) Initialize the TIM low level resources :
73 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
74 (##) TIM pins configuration
75 (+++) Enable the clock for the TIM GPIOs using the following function:
76 __HAL_RCC_GPIOx_CLK_ENABLE();
77 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
78
79 (#) The external Clock can be configured, if needed (the default clock is the
80 internal clock from the APBx), using the following function:
81 HAL_TIM_ConfigClockSource, the clock configuration should be done before
82 any start function.
83
84 (#) Configure the TIM in the desired functioning mode using one of the
85 Initialization function of this driver:
86 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
87 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
88 Output Compare signal.
89 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
90 PWM signal.
91 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
92 external signal.
93 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
94 in One Pulse Mode.
95 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
96
97 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
98 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
99 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
100 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
101 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
102 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
103 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
104
105 (#) The DMA Burst is managed with the two following functions:
106 HAL_TIM_DMABurst_WriteStart()
107 HAL_TIM_DMABurst_ReadStart()
108
109 *** Callback registration ***
110 =============================================
111
112 [..]
113 The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
114 allows the user to configure dynamically the driver callbacks.
115
116 [..]
117 Use Function HAL_TIM_RegisterCallback() to register a callback.
118 HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
119 the Callback ID and a pointer to the user callback function.
120
121 [..]
122 Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
123 weak function.
124 HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
125 and the Callback ID.
126
127 [..]
128 These functions allow to register/unregister following callbacks:
129 (+) Base_MspInitCallback : TIM Base Msp Init Callback.
130 (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
131 (+) IC_MspInitCallback : TIM IC Msp Init Callback.
132 (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
133 (+) OC_MspInitCallback : TIM OC Msp Init Callback.
134 (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
135 (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
136 (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
137 (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
138 (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
139 (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
140 (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
141 (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
142 (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
143 (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
144 (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
145 (+) TriggerCallback : TIM Trigger Callback.
146 (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
147 (+) IC_CaptureCallback : TIM Input Capture Callback.
148 (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
149 (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
150 (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
151 (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
152 (+) ErrorCallback : TIM Error Callback.
153 (+) CommutationCallback : TIM Commutation Callback.
154 (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
155 (+) BreakCallback : TIM Break Callback.
156 (+) Break2Callback : TIM Break2 Callback (when supported).
157
158 [..]
159 By default, after the Init and when the state is HAL_TIM_STATE_RESET
160 all interrupt callbacks are set to the corresponding weak functions:
161 examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
162
163 [..]
164 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
165 functionalities in the Init / DeInit only when these callbacks are null
166 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
167 keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
168
169 [..]
170 Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
171 Exception done MspInit / MspDeInit that can be registered / unregistered
172 in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
173 thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
174 In that case first register the MspInit/MspDeInit user callbacks
175 using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
176
177 [..]
178 When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
179 not defined, the callback registration feature is not available and all callbacks
180 are set to the corresponding weak functions.
181
182 @endverbatim
183 ******************************************************************************
184 */
185
186 /* Includes ------------------------------------------------------------------*/
187 #include "stm32f3xx_hal.h"
188
189 /** @addtogroup STM32F3xx_HAL_Driver
190 * @{
191 */
192
193 /** @defgroup TIM TIM
194 * @brief TIM HAL module driver
195 * @{
196 */
197
198 #ifdef HAL_TIM_MODULE_ENABLED
199
200 /* Private typedef -----------------------------------------------------------*/
201 /* Private define ------------------------------------------------------------*/
202 /* Private macros ------------------------------------------------------------*/
203 /* Private variables ---------------------------------------------------------*/
204 /* Private function prototypes -----------------------------------------------*/
205 /** @addtogroup TIM_Private_Functions
206 * @{
207 */
208 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
209 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
210 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
211 #if defined(TIM_CCER_CC5E)
212 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
213 #endif /* TIM_CCER_CC5E */
214 #if defined(TIM_CCER_CC6E)
215 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
216 #endif /* TIM_CCER_CC6E */
217 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
218 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
219 uint32_t TIM_ICFilter);
220 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
221 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
222 uint32_t TIM_ICFilter);
223 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
224 uint32_t TIM_ICFilter);
225 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
226 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
227 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
228 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
229 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
230 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
231 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
232 const TIM_SlaveConfigTypeDef *sSlaveConfig);
233 /**
234 * @}
235 */
236 /* Exported functions --------------------------------------------------------*/
237
238 /** @defgroup TIM_Exported_Functions TIM Exported Functions
239 * @{
240 */
241
242 /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
243 * @brief Time Base functions
244 *
245 @verbatim
246 ==============================================================================
247 ##### Time Base functions #####
248 ==============================================================================
249 [..]
250 This section provides functions allowing to:
251 (+) Initialize and configure the TIM base.
252 (+) De-initialize the TIM base.
253 (+) Start the Time Base.
254 (+) Stop the Time Base.
255 (+) Start the Time Base and enable interrupt.
256 (+) Stop the Time Base and disable interrupt.
257 (+) Start the Time Base and enable DMA transfer.
258 (+) Stop the Time Base and disable DMA transfer.
259
260 @endverbatim
261 * @{
262 */
263 /**
264 * @brief Initializes the TIM Time base Unit according to the specified
265 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
266 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
267 * requires a timer reset to avoid unexpected direction
268 * due to DIR bit readonly in center aligned mode.
269 * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
270 * @param htim TIM Base handle
271 * @retval HAL status
272 */
HAL_TIM_Base_Init(TIM_HandleTypeDef * htim)273 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
274 {
275 /* Check the TIM handle allocation */
276 if (htim == NULL)
277 {
278 return HAL_ERROR;
279 }
280
281 /* Check the parameters */
282 assert_param(IS_TIM_INSTANCE(htim->Instance));
283 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
284 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
285 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
286 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
287
288 if (htim->State == HAL_TIM_STATE_RESET)
289 {
290 /* Allocate lock resource and initialize it */
291 htim->Lock = HAL_UNLOCKED;
292
293 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
294 /* Reset interrupt callbacks to legacy weak callbacks */
295 TIM_ResetCallback(htim);
296
297 if (htim->Base_MspInitCallback == NULL)
298 {
299 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
300 }
301 /* Init the low level hardware : GPIO, CLOCK, NVIC */
302 htim->Base_MspInitCallback(htim);
303 #else
304 /* Init the low level hardware : GPIO, CLOCK, NVIC */
305 HAL_TIM_Base_MspInit(htim);
306 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
307 }
308
309 /* Set the TIM state */
310 htim->State = HAL_TIM_STATE_BUSY;
311
312 /* Set the Time Base configuration */
313 TIM_Base_SetConfig(htim->Instance, &htim->Init);
314
315 /* Initialize the DMA burst operation state */
316 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
317
318 /* Initialize the TIM channels state */
319 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
320 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
321
322 /* Initialize the TIM state*/
323 htim->State = HAL_TIM_STATE_READY;
324
325 return HAL_OK;
326 }
327
328 /**
329 * @brief DeInitializes the TIM Base peripheral
330 * @param htim TIM Base handle
331 * @retval HAL status
332 */
HAL_TIM_Base_DeInit(TIM_HandleTypeDef * htim)333 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
334 {
335 /* Check the parameters */
336 assert_param(IS_TIM_INSTANCE(htim->Instance));
337
338 htim->State = HAL_TIM_STATE_BUSY;
339
340 /* Disable the TIM Peripheral Clock */
341 __HAL_TIM_DISABLE(htim);
342
343 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
344 if (htim->Base_MspDeInitCallback == NULL)
345 {
346 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
347 }
348 /* DeInit the low level hardware */
349 htim->Base_MspDeInitCallback(htim);
350 #else
351 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
352 HAL_TIM_Base_MspDeInit(htim);
353 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
354
355 /* Change the DMA burst operation state */
356 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
357
358 /* Change the TIM channels state */
359 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
360 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
361
362 /* Change TIM state */
363 htim->State = HAL_TIM_STATE_RESET;
364
365 /* Release Lock */
366 __HAL_UNLOCK(htim);
367
368 return HAL_OK;
369 }
370
371 /**
372 * @brief Initializes the TIM Base MSP.
373 * @param htim TIM Base handle
374 * @retval None
375 */
HAL_TIM_Base_MspInit(TIM_HandleTypeDef * htim)376 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
377 {
378 /* Prevent unused argument(s) compilation warning */
379 UNUSED(htim);
380
381 /* NOTE : This function should not be modified, when the callback is needed,
382 the HAL_TIM_Base_MspInit could be implemented in the user file
383 */
384 }
385
386 /**
387 * @brief DeInitializes TIM Base MSP.
388 * @param htim TIM Base handle
389 * @retval None
390 */
HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef * htim)391 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
392 {
393 /* Prevent unused argument(s) compilation warning */
394 UNUSED(htim);
395
396 /* NOTE : This function should not be modified, when the callback is needed,
397 the HAL_TIM_Base_MspDeInit could be implemented in the user file
398 */
399 }
400
401
402 /**
403 * @brief Starts the TIM Base generation.
404 * @param htim TIM Base handle
405 * @retval HAL status
406 */
HAL_TIM_Base_Start(TIM_HandleTypeDef * htim)407 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
408 {
409 uint32_t tmpsmcr;
410
411 /* Check the parameters */
412 assert_param(IS_TIM_INSTANCE(htim->Instance));
413
414 /* Check the TIM state */
415 if (htim->State != HAL_TIM_STATE_READY)
416 {
417 return HAL_ERROR;
418 }
419
420 /* Set the TIM state */
421 htim->State = HAL_TIM_STATE_BUSY;
422
423 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
424 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
425 {
426 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
427 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
428 {
429 __HAL_TIM_ENABLE(htim);
430 }
431 }
432 else
433 {
434 __HAL_TIM_ENABLE(htim);
435 }
436
437 /* Return function status */
438 return HAL_OK;
439 }
440
441 /**
442 * @brief Stops the TIM Base generation.
443 * @param htim TIM Base handle
444 * @retval HAL status
445 */
HAL_TIM_Base_Stop(TIM_HandleTypeDef * htim)446 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
447 {
448 /* Check the parameters */
449 assert_param(IS_TIM_INSTANCE(htim->Instance));
450
451 /* Disable the Peripheral */
452 __HAL_TIM_DISABLE(htim);
453
454 /* Set the TIM state */
455 htim->State = HAL_TIM_STATE_READY;
456
457 /* Return function status */
458 return HAL_OK;
459 }
460
461 /**
462 * @brief Starts the TIM Base generation in interrupt mode.
463 * @param htim TIM Base handle
464 * @retval HAL status
465 */
HAL_TIM_Base_Start_IT(TIM_HandleTypeDef * htim)466 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
467 {
468 uint32_t tmpsmcr;
469
470 /* Check the parameters */
471 assert_param(IS_TIM_INSTANCE(htim->Instance));
472
473 /* Check the TIM state */
474 if (htim->State != HAL_TIM_STATE_READY)
475 {
476 return HAL_ERROR;
477 }
478
479 /* Set the TIM state */
480 htim->State = HAL_TIM_STATE_BUSY;
481
482 /* Enable the TIM Update interrupt */
483 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
484
485 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
486 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
487 {
488 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
489 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
490 {
491 __HAL_TIM_ENABLE(htim);
492 }
493 }
494 else
495 {
496 __HAL_TIM_ENABLE(htim);
497 }
498
499 /* Return function status */
500 return HAL_OK;
501 }
502
503 /**
504 * @brief Stops the TIM Base generation in interrupt mode.
505 * @param htim TIM Base handle
506 * @retval HAL status
507 */
HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef * htim)508 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
509 {
510 /* Check the parameters */
511 assert_param(IS_TIM_INSTANCE(htim->Instance));
512
513 /* Disable the TIM Update interrupt */
514 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
515
516 /* Disable the Peripheral */
517 __HAL_TIM_DISABLE(htim);
518
519 /* Set the TIM state */
520 htim->State = HAL_TIM_STATE_READY;
521
522 /* Return function status */
523 return HAL_OK;
524 }
525
526 /**
527 * @brief Starts the TIM Base generation in DMA mode.
528 * @param htim TIM Base handle
529 * @param pData The source Buffer address.
530 * @param Length The length of data to be transferred from memory to peripheral.
531 * @retval HAL status
532 */
HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef * htim,const uint32_t * pData,uint16_t Length)533 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
534 {
535 uint32_t tmpsmcr;
536
537 /* Check the parameters */
538 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
539
540 /* Set the TIM state */
541 if (htim->State == HAL_TIM_STATE_BUSY)
542 {
543 return HAL_BUSY;
544 }
545 else if (htim->State == HAL_TIM_STATE_READY)
546 {
547 if ((pData == NULL) || (Length == 0U))
548 {
549 return HAL_ERROR;
550 }
551 else
552 {
553 htim->State = HAL_TIM_STATE_BUSY;
554 }
555 }
556 else
557 {
558 return HAL_ERROR;
559 }
560
561 /* Set the DMA Period elapsed callbacks */
562 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
563 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
564
565 /* Set the DMA error callback */
566 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
567
568 /* Enable the DMA channel */
569 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
570 Length) != HAL_OK)
571 {
572 /* Return error status */
573 return HAL_ERROR;
574 }
575
576 /* Enable the TIM Update DMA request */
577 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
578
579 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
580 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
581 {
582 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
583 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
584 {
585 __HAL_TIM_ENABLE(htim);
586 }
587 }
588 else
589 {
590 __HAL_TIM_ENABLE(htim);
591 }
592
593 /* Return function status */
594 return HAL_OK;
595 }
596
597 /**
598 * @brief Stops the TIM Base generation in DMA mode.
599 * @param htim TIM Base handle
600 * @retval HAL status
601 */
HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef * htim)602 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
603 {
604 /* Check the parameters */
605 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
606
607 /* Disable the TIM Update DMA request */
608 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
609
610 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
611
612 /* Disable the Peripheral */
613 __HAL_TIM_DISABLE(htim);
614
615 /* Set the TIM state */
616 htim->State = HAL_TIM_STATE_READY;
617
618 /* Return function status */
619 return HAL_OK;
620 }
621
622 /**
623 * @}
624 */
625
626 /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
627 * @brief TIM Output Compare functions
628 *
629 @verbatim
630 ==============================================================================
631 ##### TIM Output Compare functions #####
632 ==============================================================================
633 [..]
634 This section provides functions allowing to:
635 (+) Initialize and configure the TIM Output Compare.
636 (+) De-initialize the TIM Output Compare.
637 (+) Start the TIM Output Compare.
638 (+) Stop the TIM Output Compare.
639 (+) Start the TIM Output Compare and enable interrupt.
640 (+) Stop the TIM Output Compare and disable interrupt.
641 (+) Start the TIM Output Compare and enable DMA transfer.
642 (+) Stop the TIM Output Compare and disable DMA transfer.
643
644 @endverbatim
645 * @{
646 */
647 /**
648 * @brief Initializes the TIM Output Compare according to the specified
649 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
650 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
651 * requires a timer reset to avoid unexpected direction
652 * due to DIR bit readonly in center aligned mode.
653 * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
654 * @param htim TIM Output Compare handle
655 * @retval HAL status
656 */
HAL_TIM_OC_Init(TIM_HandleTypeDef * htim)657 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
658 {
659 /* Check the TIM handle allocation */
660 if (htim == NULL)
661 {
662 return HAL_ERROR;
663 }
664
665 /* Check the parameters */
666 assert_param(IS_TIM_INSTANCE(htim->Instance));
667 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
668 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
669 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
670 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
671
672 if (htim->State == HAL_TIM_STATE_RESET)
673 {
674 /* Allocate lock resource and initialize it */
675 htim->Lock = HAL_UNLOCKED;
676
677 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
678 /* Reset interrupt callbacks to legacy weak callbacks */
679 TIM_ResetCallback(htim);
680
681 if (htim->OC_MspInitCallback == NULL)
682 {
683 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
684 }
685 /* Init the low level hardware : GPIO, CLOCK, NVIC */
686 htim->OC_MspInitCallback(htim);
687 #else
688 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
689 HAL_TIM_OC_MspInit(htim);
690 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
691 }
692
693 /* Set the TIM state */
694 htim->State = HAL_TIM_STATE_BUSY;
695
696 /* Init the base time for the Output Compare */
697 TIM_Base_SetConfig(htim->Instance, &htim->Init);
698
699 /* Initialize the DMA burst operation state */
700 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
701
702 /* Initialize the TIM channels state */
703 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
704 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
705
706 /* Initialize the TIM state*/
707 htim->State = HAL_TIM_STATE_READY;
708
709 return HAL_OK;
710 }
711
712 /**
713 * @brief DeInitializes the TIM peripheral
714 * @param htim TIM Output Compare handle
715 * @retval HAL status
716 */
HAL_TIM_OC_DeInit(TIM_HandleTypeDef * htim)717 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
718 {
719 /* Check the parameters */
720 assert_param(IS_TIM_INSTANCE(htim->Instance));
721
722 htim->State = HAL_TIM_STATE_BUSY;
723
724 /* Disable the TIM Peripheral Clock */
725 __HAL_TIM_DISABLE(htim);
726
727 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
728 if (htim->OC_MspDeInitCallback == NULL)
729 {
730 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
731 }
732 /* DeInit the low level hardware */
733 htim->OC_MspDeInitCallback(htim);
734 #else
735 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
736 HAL_TIM_OC_MspDeInit(htim);
737 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
738
739 /* Change the DMA burst operation state */
740 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
741
742 /* Change the TIM channels state */
743 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
744 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
745
746 /* Change TIM state */
747 htim->State = HAL_TIM_STATE_RESET;
748
749 /* Release Lock */
750 __HAL_UNLOCK(htim);
751
752 return HAL_OK;
753 }
754
755 /**
756 * @brief Initializes the TIM Output Compare MSP.
757 * @param htim TIM Output Compare handle
758 * @retval None
759 */
HAL_TIM_OC_MspInit(TIM_HandleTypeDef * htim)760 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
761 {
762 /* Prevent unused argument(s) compilation warning */
763 UNUSED(htim);
764
765 /* NOTE : This function should not be modified, when the callback is needed,
766 the HAL_TIM_OC_MspInit could be implemented in the user file
767 */
768 }
769
770 /**
771 * @brief DeInitializes TIM Output Compare MSP.
772 * @param htim TIM Output Compare handle
773 * @retval None
774 */
HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef * htim)775 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
776 {
777 /* Prevent unused argument(s) compilation warning */
778 UNUSED(htim);
779
780 /* NOTE : This function should not be modified, when the callback is needed,
781 the HAL_TIM_OC_MspDeInit could be implemented in the user file
782 */
783 }
784
785 /**
786 * @brief Starts the TIM Output Compare signal generation.
787 * @param htim TIM Output Compare handle
788 * @param Channel TIM Channel to be enabled
789 * This parameter can be one of the following values:
790 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
791 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
792 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
793 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
794 * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*)
795 * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*)
796 * (*) Value not defined for all devices
797 * @retval HAL status
798 */
HAL_TIM_OC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)799 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
800 {
801 uint32_t tmpsmcr;
802
803 /* Check the parameters */
804 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
805
806 /* Check the TIM channel state */
807 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
808 {
809 return HAL_ERROR;
810 }
811
812 /* Set the TIM channel state */
813 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
814
815 /* Enable the Output compare channel */
816 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
817
818 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
819 {
820 /* Enable the main output */
821 __HAL_TIM_MOE_ENABLE(htim);
822 }
823
824 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
825 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
826 {
827 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
828 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
829 {
830 __HAL_TIM_ENABLE(htim);
831 }
832 }
833 else
834 {
835 __HAL_TIM_ENABLE(htim);
836 }
837
838 /* Return function status */
839 return HAL_OK;
840 }
841
842 /**
843 * @brief Stops the TIM Output Compare signal generation.
844 * @param htim TIM Output Compare handle
845 * @param Channel TIM Channel to be disabled
846 * This parameter can be one of the following values:
847 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
848 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
849 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
850 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
851 * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*)
852 * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*)
853 * (*) Value not defined for all devices
854 * @retval HAL status
855 */
HAL_TIM_OC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)856 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
857 {
858 /* Check the parameters */
859 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
860
861 /* Disable the Output compare channel */
862 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
863
864 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
865 {
866 /* Disable the Main Output */
867 __HAL_TIM_MOE_DISABLE(htim);
868 }
869
870 /* Disable the Peripheral */
871 __HAL_TIM_DISABLE(htim);
872
873 /* Set the TIM channel state */
874 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
875
876 /* Return function status */
877 return HAL_OK;
878 }
879
880 /**
881 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
882 * @param htim TIM Output Compare handle
883 * @param Channel TIM Channel to be enabled
884 * This parameter can be one of the following values:
885 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
886 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
887 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
888 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
889 * @retval HAL status
890 */
HAL_TIM_OC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)891 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
892 {
893 HAL_StatusTypeDef status = HAL_OK;
894 uint32_t tmpsmcr;
895
896 /* Check the parameters */
897 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
898
899 /* Check the TIM channel state */
900 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
901 {
902 return HAL_ERROR;
903 }
904
905 /* Set the TIM channel state */
906 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
907
908 switch (Channel)
909 {
910 case TIM_CHANNEL_1:
911 {
912 /* Enable the TIM Capture/Compare 1 interrupt */
913 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
914 break;
915 }
916
917 case TIM_CHANNEL_2:
918 {
919 /* Enable the TIM Capture/Compare 2 interrupt */
920 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
921 break;
922 }
923
924 case TIM_CHANNEL_3:
925 {
926 /* Enable the TIM Capture/Compare 3 interrupt */
927 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
928 break;
929 }
930
931 case TIM_CHANNEL_4:
932 {
933 /* Enable the TIM Capture/Compare 4 interrupt */
934 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
935 break;
936 }
937
938 default:
939 status = HAL_ERROR;
940 break;
941 }
942
943 if (status == HAL_OK)
944 {
945 /* Enable the Output compare channel */
946 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
947
948 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
949 {
950 /* Enable the main output */
951 __HAL_TIM_MOE_ENABLE(htim);
952 }
953
954 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
955 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
956 {
957 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
958 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
959 {
960 __HAL_TIM_ENABLE(htim);
961 }
962 }
963 else
964 {
965 __HAL_TIM_ENABLE(htim);
966 }
967 }
968
969 /* Return function status */
970 return status;
971 }
972
973 /**
974 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
975 * @param htim TIM Output Compare handle
976 * @param Channel TIM Channel to be disabled
977 * This parameter can be one of the following values:
978 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
979 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
980 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
981 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
982 * @retval HAL status
983 */
HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)984 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
985 {
986 HAL_StatusTypeDef status = HAL_OK;
987
988 /* Check the parameters */
989 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
990
991 switch (Channel)
992 {
993 case TIM_CHANNEL_1:
994 {
995 /* Disable the TIM Capture/Compare 1 interrupt */
996 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
997 break;
998 }
999
1000 case TIM_CHANNEL_2:
1001 {
1002 /* Disable the TIM Capture/Compare 2 interrupt */
1003 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1004 break;
1005 }
1006
1007 case TIM_CHANNEL_3:
1008 {
1009 /* Disable the TIM Capture/Compare 3 interrupt */
1010 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1011 break;
1012 }
1013
1014 case TIM_CHANNEL_4:
1015 {
1016 /* Disable the TIM Capture/Compare 4 interrupt */
1017 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1018 break;
1019 }
1020
1021 default:
1022 status = HAL_ERROR;
1023 break;
1024 }
1025
1026 if (status == HAL_OK)
1027 {
1028 /* Disable the Output compare channel */
1029 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1030
1031 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1032 {
1033 /* Disable the Main Output */
1034 __HAL_TIM_MOE_DISABLE(htim);
1035 }
1036
1037 /* Disable the Peripheral */
1038 __HAL_TIM_DISABLE(htim);
1039
1040 /* Set the TIM channel state */
1041 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1042 }
1043
1044 /* Return function status */
1045 return status;
1046 }
1047
1048 /**
1049 * @brief Starts the TIM Output Compare signal generation in DMA mode.
1050 * @param htim TIM Output Compare handle
1051 * @param Channel TIM Channel to be enabled
1052 * This parameter can be one of the following values:
1053 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1054 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1055 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1056 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1057 * @param pData The source Buffer address.
1058 * @param Length The length of data to be transferred from memory to TIM peripheral
1059 * @retval HAL status
1060 */
HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1061 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1062 uint16_t Length)
1063 {
1064 HAL_StatusTypeDef status = HAL_OK;
1065 uint32_t tmpsmcr;
1066
1067 /* Check the parameters */
1068 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1069
1070 /* Set the TIM channel state */
1071 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1072 {
1073 return HAL_BUSY;
1074 }
1075 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1076 {
1077 if ((pData == NULL) || (Length == 0U))
1078 {
1079 return HAL_ERROR;
1080 }
1081 else
1082 {
1083 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1084 }
1085 }
1086 else
1087 {
1088 return HAL_ERROR;
1089 }
1090
1091 switch (Channel)
1092 {
1093 case TIM_CHANNEL_1:
1094 {
1095 /* Set the DMA compare callbacks */
1096 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1097 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1098
1099 /* Set the DMA error callback */
1100 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1101
1102 /* Enable the DMA channel */
1103 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1104 Length) != HAL_OK)
1105 {
1106 /* Return error status */
1107 return HAL_ERROR;
1108 }
1109
1110 /* Enable the TIM Capture/Compare 1 DMA request */
1111 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1112 break;
1113 }
1114
1115 case TIM_CHANNEL_2:
1116 {
1117 /* Set the DMA compare callbacks */
1118 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1119 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1120
1121 /* Set the DMA error callback */
1122 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1123
1124 /* Enable the DMA channel */
1125 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1126 Length) != HAL_OK)
1127 {
1128 /* Return error status */
1129 return HAL_ERROR;
1130 }
1131
1132 /* Enable the TIM Capture/Compare 2 DMA request */
1133 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1134 break;
1135 }
1136
1137 case TIM_CHANNEL_3:
1138 {
1139 /* Set the DMA compare callbacks */
1140 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1141 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1142
1143 /* Set the DMA error callback */
1144 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1145
1146 /* Enable the DMA channel */
1147 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1148 Length) != HAL_OK)
1149 {
1150 /* Return error status */
1151 return HAL_ERROR;
1152 }
1153 /* Enable the TIM Capture/Compare 3 DMA request */
1154 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1155 break;
1156 }
1157
1158 case TIM_CHANNEL_4:
1159 {
1160 /* Set the DMA compare callbacks */
1161 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1162 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1163
1164 /* Set the DMA error callback */
1165 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1166
1167 /* Enable the DMA channel */
1168 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1169 Length) != HAL_OK)
1170 {
1171 /* Return error status */
1172 return HAL_ERROR;
1173 }
1174 /* Enable the TIM Capture/Compare 4 DMA request */
1175 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1176 break;
1177 }
1178
1179 default:
1180 status = HAL_ERROR;
1181 break;
1182 }
1183
1184 if (status == HAL_OK)
1185 {
1186 /* Enable the Output compare channel */
1187 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1188
1189 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1190 {
1191 /* Enable the main output */
1192 __HAL_TIM_MOE_ENABLE(htim);
1193 }
1194
1195 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1196 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1197 {
1198 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1199 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1200 {
1201 __HAL_TIM_ENABLE(htim);
1202 }
1203 }
1204 else
1205 {
1206 __HAL_TIM_ENABLE(htim);
1207 }
1208 }
1209
1210 /* Return function status */
1211 return status;
1212 }
1213
1214 /**
1215 * @brief Stops the TIM Output Compare signal generation in DMA mode.
1216 * @param htim TIM Output Compare handle
1217 * @param Channel TIM Channel to be disabled
1218 * This parameter can be one of the following values:
1219 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1220 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1221 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1222 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1223 * @retval HAL status
1224 */
HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1225 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1226 {
1227 HAL_StatusTypeDef status = HAL_OK;
1228
1229 /* Check the parameters */
1230 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1231
1232 switch (Channel)
1233 {
1234 case TIM_CHANNEL_1:
1235 {
1236 /* Disable the TIM Capture/Compare 1 DMA request */
1237 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1238 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1239 break;
1240 }
1241
1242 case TIM_CHANNEL_2:
1243 {
1244 /* Disable the TIM Capture/Compare 2 DMA request */
1245 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1246 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1247 break;
1248 }
1249
1250 case TIM_CHANNEL_3:
1251 {
1252 /* Disable the TIM Capture/Compare 3 DMA request */
1253 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1254 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1255 break;
1256 }
1257
1258 case TIM_CHANNEL_4:
1259 {
1260 /* Disable the TIM Capture/Compare 4 interrupt */
1261 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1262 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1263 break;
1264 }
1265
1266 default:
1267 status = HAL_ERROR;
1268 break;
1269 }
1270
1271 if (status == HAL_OK)
1272 {
1273 /* Disable the Output compare channel */
1274 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1275
1276 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1277 {
1278 /* Disable the Main Output */
1279 __HAL_TIM_MOE_DISABLE(htim);
1280 }
1281
1282 /* Disable the Peripheral */
1283 __HAL_TIM_DISABLE(htim);
1284
1285 /* Set the TIM channel state */
1286 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1287 }
1288
1289 /* Return function status */
1290 return status;
1291 }
1292
1293 /**
1294 * @}
1295 */
1296
1297 /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
1298 * @brief TIM PWM functions
1299 *
1300 @verbatim
1301 ==============================================================================
1302 ##### TIM PWM functions #####
1303 ==============================================================================
1304 [..]
1305 This section provides functions allowing to:
1306 (+) Initialize and configure the TIM PWM.
1307 (+) De-initialize the TIM PWM.
1308 (+) Start the TIM PWM.
1309 (+) Stop the TIM PWM.
1310 (+) Start the TIM PWM and enable interrupt.
1311 (+) Stop the TIM PWM and disable interrupt.
1312 (+) Start the TIM PWM and enable DMA transfer.
1313 (+) Stop the TIM PWM and disable DMA transfer.
1314
1315 @endverbatim
1316 * @{
1317 */
1318 /**
1319 * @brief Initializes the TIM PWM Time Base according to the specified
1320 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1321 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1322 * requires a timer reset to avoid unexpected direction
1323 * due to DIR bit readonly in center aligned mode.
1324 * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
1325 * @param htim TIM PWM handle
1326 * @retval HAL status
1327 */
HAL_TIM_PWM_Init(TIM_HandleTypeDef * htim)1328 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
1329 {
1330 /* Check the TIM handle allocation */
1331 if (htim == NULL)
1332 {
1333 return HAL_ERROR;
1334 }
1335
1336 /* Check the parameters */
1337 assert_param(IS_TIM_INSTANCE(htim->Instance));
1338 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1339 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1340 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
1341 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1342
1343 if (htim->State == HAL_TIM_STATE_RESET)
1344 {
1345 /* Allocate lock resource and initialize it */
1346 htim->Lock = HAL_UNLOCKED;
1347
1348 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1349 /* Reset interrupt callbacks to legacy weak callbacks */
1350 TIM_ResetCallback(htim);
1351
1352 if (htim->PWM_MspInitCallback == NULL)
1353 {
1354 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
1355 }
1356 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1357 htim->PWM_MspInitCallback(htim);
1358 #else
1359 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1360 HAL_TIM_PWM_MspInit(htim);
1361 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1362 }
1363
1364 /* Set the TIM state */
1365 htim->State = HAL_TIM_STATE_BUSY;
1366
1367 /* Init the base time for the PWM */
1368 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1369
1370 /* Initialize the DMA burst operation state */
1371 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
1372
1373 /* Initialize the TIM channels state */
1374 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1375 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1376
1377 /* Initialize the TIM state*/
1378 htim->State = HAL_TIM_STATE_READY;
1379
1380 return HAL_OK;
1381 }
1382
1383 /**
1384 * @brief DeInitializes the TIM peripheral
1385 * @param htim TIM PWM handle
1386 * @retval HAL status
1387 */
HAL_TIM_PWM_DeInit(TIM_HandleTypeDef * htim)1388 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1389 {
1390 /* Check the parameters */
1391 assert_param(IS_TIM_INSTANCE(htim->Instance));
1392
1393 htim->State = HAL_TIM_STATE_BUSY;
1394
1395 /* Disable the TIM Peripheral Clock */
1396 __HAL_TIM_DISABLE(htim);
1397
1398 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1399 if (htim->PWM_MspDeInitCallback == NULL)
1400 {
1401 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
1402 }
1403 /* DeInit the low level hardware */
1404 htim->PWM_MspDeInitCallback(htim);
1405 #else
1406 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1407 HAL_TIM_PWM_MspDeInit(htim);
1408 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1409
1410 /* Change the DMA burst operation state */
1411 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
1412
1413 /* Change the TIM channels state */
1414 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1415 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1416
1417 /* Change TIM state */
1418 htim->State = HAL_TIM_STATE_RESET;
1419
1420 /* Release Lock */
1421 __HAL_UNLOCK(htim);
1422
1423 return HAL_OK;
1424 }
1425
1426 /**
1427 * @brief Initializes the TIM PWM MSP.
1428 * @param htim TIM PWM handle
1429 * @retval None
1430 */
HAL_TIM_PWM_MspInit(TIM_HandleTypeDef * htim)1431 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1432 {
1433 /* Prevent unused argument(s) compilation warning */
1434 UNUSED(htim);
1435
1436 /* NOTE : This function should not be modified, when the callback is needed,
1437 the HAL_TIM_PWM_MspInit could be implemented in the user file
1438 */
1439 }
1440
1441 /**
1442 * @brief DeInitializes TIM PWM MSP.
1443 * @param htim TIM PWM handle
1444 * @retval None
1445 */
HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef * htim)1446 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1447 {
1448 /* Prevent unused argument(s) compilation warning */
1449 UNUSED(htim);
1450
1451 /* NOTE : This function should not be modified, when the callback is needed,
1452 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1453 */
1454 }
1455
1456 /**
1457 * @brief Starts the PWM signal generation.
1458 * @param htim TIM handle
1459 * @param Channel TIM Channels to be enabled
1460 * This parameter can be one of the following values:
1461 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1462 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1463 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1464 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1465 * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*)
1466 * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*)
1467 * (*) Value not defined for all devices
1468 * @retval HAL status
1469 */
HAL_TIM_PWM_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1470 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1471 {
1472 uint32_t tmpsmcr;
1473
1474 /* Check the parameters */
1475 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1476
1477 /* Check the TIM channel state */
1478 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1479 {
1480 return HAL_ERROR;
1481 }
1482
1483 /* Set the TIM channel state */
1484 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1485
1486 /* Enable the Capture compare channel */
1487 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1488
1489 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1490 {
1491 /* Enable the main output */
1492 __HAL_TIM_MOE_ENABLE(htim);
1493 }
1494
1495 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1496 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1497 {
1498 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1499 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1500 {
1501 __HAL_TIM_ENABLE(htim);
1502 }
1503 }
1504 else
1505 {
1506 __HAL_TIM_ENABLE(htim);
1507 }
1508
1509 /* Return function status */
1510 return HAL_OK;
1511 }
1512
1513 /**
1514 * @brief Stops the PWM signal generation.
1515 * @param htim TIM PWM handle
1516 * @param Channel TIM Channels to be disabled
1517 * This parameter can be one of the following values:
1518 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1519 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1520 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1521 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1522 * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*)
1523 * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*)
1524 * (*) Value not defined for all devices
1525 * @retval HAL status
1526 */
HAL_TIM_PWM_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1527 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1528 {
1529 /* Check the parameters */
1530 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1531
1532 /* Disable the Capture compare channel */
1533 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1534
1535 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1536 {
1537 /* Disable the Main Output */
1538 __HAL_TIM_MOE_DISABLE(htim);
1539 }
1540
1541 /* Disable the Peripheral */
1542 __HAL_TIM_DISABLE(htim);
1543
1544 /* Set the TIM channel state */
1545 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1546
1547 /* Return function status */
1548 return HAL_OK;
1549 }
1550
1551 /**
1552 * @brief Starts the PWM signal generation in interrupt mode.
1553 * @param htim TIM PWM handle
1554 * @param Channel TIM Channel to be enabled
1555 * This parameter can be one of the following values:
1556 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1557 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1558 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1559 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1560 * @retval HAL status
1561 */
HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1562 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1563 {
1564 HAL_StatusTypeDef status = HAL_OK;
1565 uint32_t tmpsmcr;
1566
1567 /* Check the parameters */
1568 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1569
1570 /* Check the TIM channel state */
1571 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1572 {
1573 return HAL_ERROR;
1574 }
1575
1576 /* Set the TIM channel state */
1577 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1578
1579 switch (Channel)
1580 {
1581 case TIM_CHANNEL_1:
1582 {
1583 /* Enable the TIM Capture/Compare 1 interrupt */
1584 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1585 break;
1586 }
1587
1588 case TIM_CHANNEL_2:
1589 {
1590 /* Enable the TIM Capture/Compare 2 interrupt */
1591 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1592 break;
1593 }
1594
1595 case TIM_CHANNEL_3:
1596 {
1597 /* Enable the TIM Capture/Compare 3 interrupt */
1598 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1599 break;
1600 }
1601
1602 case TIM_CHANNEL_4:
1603 {
1604 /* Enable the TIM Capture/Compare 4 interrupt */
1605 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1606 break;
1607 }
1608
1609 default:
1610 status = HAL_ERROR;
1611 break;
1612 }
1613
1614 if (status == HAL_OK)
1615 {
1616 /* Enable the Capture compare channel */
1617 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1618
1619 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1620 {
1621 /* Enable the main output */
1622 __HAL_TIM_MOE_ENABLE(htim);
1623 }
1624
1625 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1626 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1627 {
1628 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1629 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1630 {
1631 __HAL_TIM_ENABLE(htim);
1632 }
1633 }
1634 else
1635 {
1636 __HAL_TIM_ENABLE(htim);
1637 }
1638 }
1639
1640 /* Return function status */
1641 return status;
1642 }
1643
1644 /**
1645 * @brief Stops the PWM signal generation in interrupt mode.
1646 * @param htim TIM PWM handle
1647 * @param Channel TIM Channels to be disabled
1648 * This parameter can be one of the following values:
1649 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1650 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1651 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1652 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1653 * @retval HAL status
1654 */
HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1655 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1656 {
1657 HAL_StatusTypeDef status = HAL_OK;
1658
1659 /* Check the parameters */
1660 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1661
1662 switch (Channel)
1663 {
1664 case TIM_CHANNEL_1:
1665 {
1666 /* Disable the TIM Capture/Compare 1 interrupt */
1667 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1668 break;
1669 }
1670
1671 case TIM_CHANNEL_2:
1672 {
1673 /* Disable the TIM Capture/Compare 2 interrupt */
1674 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1675 break;
1676 }
1677
1678 case TIM_CHANNEL_3:
1679 {
1680 /* Disable the TIM Capture/Compare 3 interrupt */
1681 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1682 break;
1683 }
1684
1685 case TIM_CHANNEL_4:
1686 {
1687 /* Disable the TIM Capture/Compare 4 interrupt */
1688 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1689 break;
1690 }
1691
1692 default:
1693 status = HAL_ERROR;
1694 break;
1695 }
1696
1697 if (status == HAL_OK)
1698 {
1699 /* Disable the Capture compare channel */
1700 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1701
1702 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1703 {
1704 /* Disable the Main Output */
1705 __HAL_TIM_MOE_DISABLE(htim);
1706 }
1707
1708 /* Disable the Peripheral */
1709 __HAL_TIM_DISABLE(htim);
1710
1711 /* Set the TIM channel state */
1712 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1713 }
1714
1715 /* Return function status */
1716 return status;
1717 }
1718
1719 /**
1720 * @brief Starts the TIM PWM signal generation in DMA mode.
1721 * @param htim TIM PWM handle
1722 * @param Channel TIM Channels to be enabled
1723 * This parameter can be one of the following values:
1724 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1725 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1726 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1727 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1728 * @param pData The source Buffer address.
1729 * @param Length The length of data to be transferred from memory to TIM peripheral
1730 * @retval HAL status
1731 */
HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1732 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1733 uint16_t Length)
1734 {
1735 HAL_StatusTypeDef status = HAL_OK;
1736 uint32_t tmpsmcr;
1737
1738 /* Check the parameters */
1739 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1740
1741 /* Set the TIM channel state */
1742 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1743 {
1744 return HAL_BUSY;
1745 }
1746 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1747 {
1748 if ((pData == NULL) || (Length == 0U))
1749 {
1750 return HAL_ERROR;
1751 }
1752 else
1753 {
1754 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1755 }
1756 }
1757 else
1758 {
1759 return HAL_ERROR;
1760 }
1761
1762 switch (Channel)
1763 {
1764 case TIM_CHANNEL_1:
1765 {
1766 /* Set the DMA compare callbacks */
1767 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1768 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1769
1770 /* Set the DMA error callback */
1771 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1772
1773 /* Enable the DMA channel */
1774 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1775 Length) != HAL_OK)
1776 {
1777 /* Return error status */
1778 return HAL_ERROR;
1779 }
1780
1781 /* Enable the TIM Capture/Compare 1 DMA request */
1782 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1783 break;
1784 }
1785
1786 case TIM_CHANNEL_2:
1787 {
1788 /* Set the DMA compare callbacks */
1789 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1790 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1791
1792 /* Set the DMA error callback */
1793 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1794
1795 /* Enable the DMA channel */
1796 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1797 Length) != HAL_OK)
1798 {
1799 /* Return error status */
1800 return HAL_ERROR;
1801 }
1802 /* Enable the TIM Capture/Compare 2 DMA request */
1803 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1804 break;
1805 }
1806
1807 case TIM_CHANNEL_3:
1808 {
1809 /* Set the DMA compare callbacks */
1810 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1811 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1812
1813 /* Set the DMA error callback */
1814 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1815
1816 /* Enable the DMA channel */
1817 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1818 Length) != HAL_OK)
1819 {
1820 /* Return error status */
1821 return HAL_ERROR;
1822 }
1823 /* Enable the TIM Output Capture/Compare 3 request */
1824 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1825 break;
1826 }
1827
1828 case TIM_CHANNEL_4:
1829 {
1830 /* Set the DMA compare callbacks */
1831 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1832 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1833
1834 /* Set the DMA error callback */
1835 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1836
1837 /* Enable the DMA channel */
1838 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1839 Length) != HAL_OK)
1840 {
1841 /* Return error status */
1842 return HAL_ERROR;
1843 }
1844 /* Enable the TIM Capture/Compare 4 DMA request */
1845 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1846 break;
1847 }
1848
1849 default:
1850 status = HAL_ERROR;
1851 break;
1852 }
1853
1854 if (status == HAL_OK)
1855 {
1856 /* Enable the Capture compare channel */
1857 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1858
1859 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1860 {
1861 /* Enable the main output */
1862 __HAL_TIM_MOE_ENABLE(htim);
1863 }
1864
1865 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1866 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1867 {
1868 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1869 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1870 {
1871 __HAL_TIM_ENABLE(htim);
1872 }
1873 }
1874 else
1875 {
1876 __HAL_TIM_ENABLE(htim);
1877 }
1878 }
1879
1880 /* Return function status */
1881 return status;
1882 }
1883
1884 /**
1885 * @brief Stops the TIM PWM signal generation in DMA mode.
1886 * @param htim TIM PWM handle
1887 * @param Channel TIM Channels to be disabled
1888 * This parameter can be one of the following values:
1889 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1890 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1891 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1892 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1893 * @retval HAL status
1894 */
HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1895 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1896 {
1897 HAL_StatusTypeDef status = HAL_OK;
1898
1899 /* Check the parameters */
1900 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1901
1902 switch (Channel)
1903 {
1904 case TIM_CHANNEL_1:
1905 {
1906 /* Disable the TIM Capture/Compare 1 DMA request */
1907 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1908 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1909 break;
1910 }
1911
1912 case TIM_CHANNEL_2:
1913 {
1914 /* Disable the TIM Capture/Compare 2 DMA request */
1915 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1916 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1917 break;
1918 }
1919
1920 case TIM_CHANNEL_3:
1921 {
1922 /* Disable the TIM Capture/Compare 3 DMA request */
1923 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1924 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1925 break;
1926 }
1927
1928 case TIM_CHANNEL_4:
1929 {
1930 /* Disable the TIM Capture/Compare 4 interrupt */
1931 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1932 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1933 break;
1934 }
1935
1936 default:
1937 status = HAL_ERROR;
1938 break;
1939 }
1940
1941 if (status == HAL_OK)
1942 {
1943 /* Disable the Capture compare channel */
1944 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1945
1946 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1947 {
1948 /* Disable the Main Output */
1949 __HAL_TIM_MOE_DISABLE(htim);
1950 }
1951
1952 /* Disable the Peripheral */
1953 __HAL_TIM_DISABLE(htim);
1954
1955 /* Set the TIM channel state */
1956 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1957 }
1958
1959 /* Return function status */
1960 return status;
1961 }
1962
1963 /**
1964 * @}
1965 */
1966
1967 /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
1968 * @brief TIM Input Capture functions
1969 *
1970 @verbatim
1971 ==============================================================================
1972 ##### TIM Input Capture functions #####
1973 ==============================================================================
1974 [..]
1975 This section provides functions allowing to:
1976 (+) Initialize and configure the TIM Input Capture.
1977 (+) De-initialize the TIM Input Capture.
1978 (+) Start the TIM Input Capture.
1979 (+) Stop the TIM Input Capture.
1980 (+) Start the TIM Input Capture and enable interrupt.
1981 (+) Stop the TIM Input Capture and disable interrupt.
1982 (+) Start the TIM Input Capture and enable DMA transfer.
1983 (+) Stop the TIM Input Capture and disable DMA transfer.
1984
1985 @endverbatim
1986 * @{
1987 */
1988 /**
1989 * @brief Initializes the TIM Input Capture Time base according to the specified
1990 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1991 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1992 * requires a timer reset to avoid unexpected direction
1993 * due to DIR bit readonly in center aligned mode.
1994 * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
1995 * @param htim TIM Input Capture handle
1996 * @retval HAL status
1997 */
HAL_TIM_IC_Init(TIM_HandleTypeDef * htim)1998 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1999 {
2000 /* Check the TIM handle allocation */
2001 if (htim == NULL)
2002 {
2003 return HAL_ERROR;
2004 }
2005
2006 /* Check the parameters */
2007 assert_param(IS_TIM_INSTANCE(htim->Instance));
2008 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2009 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2010 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
2011 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2012
2013 if (htim->State == HAL_TIM_STATE_RESET)
2014 {
2015 /* Allocate lock resource and initialize it */
2016 htim->Lock = HAL_UNLOCKED;
2017
2018 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2019 /* Reset interrupt callbacks to legacy weak callbacks */
2020 TIM_ResetCallback(htim);
2021
2022 if (htim->IC_MspInitCallback == NULL)
2023 {
2024 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
2025 }
2026 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2027 htim->IC_MspInitCallback(htim);
2028 #else
2029 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2030 HAL_TIM_IC_MspInit(htim);
2031 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2032 }
2033
2034 /* Set the TIM state */
2035 htim->State = HAL_TIM_STATE_BUSY;
2036
2037 /* Init the base time for the input capture */
2038 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2039
2040 /* Initialize the DMA burst operation state */
2041 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2042
2043 /* Initialize the TIM channels state */
2044 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
2045 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
2046
2047 /* Initialize the TIM state*/
2048 htim->State = HAL_TIM_STATE_READY;
2049
2050 return HAL_OK;
2051 }
2052
2053 /**
2054 * @brief DeInitializes the TIM peripheral
2055 * @param htim TIM Input Capture handle
2056 * @retval HAL status
2057 */
HAL_TIM_IC_DeInit(TIM_HandleTypeDef * htim)2058 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
2059 {
2060 /* Check the parameters */
2061 assert_param(IS_TIM_INSTANCE(htim->Instance));
2062
2063 htim->State = HAL_TIM_STATE_BUSY;
2064
2065 /* Disable the TIM Peripheral Clock */
2066 __HAL_TIM_DISABLE(htim);
2067
2068 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2069 if (htim->IC_MspDeInitCallback == NULL)
2070 {
2071 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
2072 }
2073 /* DeInit the low level hardware */
2074 htim->IC_MspDeInitCallback(htim);
2075 #else
2076 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
2077 HAL_TIM_IC_MspDeInit(htim);
2078 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2079
2080 /* Change the DMA burst operation state */
2081 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2082
2083 /* Change the TIM channels state */
2084 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2085 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2086
2087 /* Change TIM state */
2088 htim->State = HAL_TIM_STATE_RESET;
2089
2090 /* Release Lock */
2091 __HAL_UNLOCK(htim);
2092
2093 return HAL_OK;
2094 }
2095
2096 /**
2097 * @brief Initializes the TIM Input Capture MSP.
2098 * @param htim TIM Input Capture handle
2099 * @retval None
2100 */
HAL_TIM_IC_MspInit(TIM_HandleTypeDef * htim)2101 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
2102 {
2103 /* Prevent unused argument(s) compilation warning */
2104 UNUSED(htim);
2105
2106 /* NOTE : This function should not be modified, when the callback is needed,
2107 the HAL_TIM_IC_MspInit could be implemented in the user file
2108 */
2109 }
2110
2111 /**
2112 * @brief DeInitializes TIM Input Capture MSP.
2113 * @param htim TIM handle
2114 * @retval None
2115 */
HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef * htim)2116 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
2117 {
2118 /* Prevent unused argument(s) compilation warning */
2119 UNUSED(htim);
2120
2121 /* NOTE : This function should not be modified, when the callback is needed,
2122 the HAL_TIM_IC_MspDeInit could be implemented in the user file
2123 */
2124 }
2125
2126 /**
2127 * @brief Starts the TIM Input Capture measurement.
2128 * @param htim TIM Input Capture handle
2129 * @param Channel TIM Channels to be enabled
2130 * This parameter can be one of the following values:
2131 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2132 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2133 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2134 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2135 * @retval HAL status
2136 */
HAL_TIM_IC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)2137 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2138 {
2139 uint32_t tmpsmcr;
2140 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2141 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2142
2143 /* Check the parameters */
2144 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2145
2146 /* Check the TIM channel state */
2147 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2148 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2149 {
2150 return HAL_ERROR;
2151 }
2152
2153 /* Set the TIM channel state */
2154 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2155 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2156
2157 /* Enable the Input Capture channel */
2158 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2159
2160 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2161 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2162 {
2163 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2164 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2165 {
2166 __HAL_TIM_ENABLE(htim);
2167 }
2168 }
2169 else
2170 {
2171 __HAL_TIM_ENABLE(htim);
2172 }
2173
2174 /* Return function status */
2175 return HAL_OK;
2176 }
2177
2178 /**
2179 * @brief Stops the TIM Input Capture measurement.
2180 * @param htim TIM Input Capture handle
2181 * @param Channel TIM Channels to be disabled
2182 * This parameter can be one of the following values:
2183 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2184 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2185 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2186 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2187 * @retval HAL status
2188 */
HAL_TIM_IC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)2189 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2190 {
2191 /* Check the parameters */
2192 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2193
2194 /* Disable the Input Capture channel */
2195 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2196
2197 /* Disable the Peripheral */
2198 __HAL_TIM_DISABLE(htim);
2199
2200 /* Set the TIM channel state */
2201 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2202 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2203
2204 /* Return function status */
2205 return HAL_OK;
2206 }
2207
2208 /**
2209 * @brief Starts the TIM Input Capture measurement in interrupt mode.
2210 * @param htim TIM Input Capture handle
2211 * @param Channel TIM Channels to be enabled
2212 * This parameter can be one of the following values:
2213 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2214 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2215 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2216 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2217 * @retval HAL status
2218 */
HAL_TIM_IC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2219 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2220 {
2221 HAL_StatusTypeDef status = HAL_OK;
2222 uint32_t tmpsmcr;
2223
2224 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2225 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2226
2227 /* Check the parameters */
2228 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2229
2230 /* Check the TIM channel state */
2231 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2232 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2233 {
2234 return HAL_ERROR;
2235 }
2236
2237 /* Set the TIM channel state */
2238 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2239 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2240
2241 switch (Channel)
2242 {
2243 case TIM_CHANNEL_1:
2244 {
2245 /* Enable the TIM Capture/Compare 1 interrupt */
2246 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2247 break;
2248 }
2249
2250 case TIM_CHANNEL_2:
2251 {
2252 /* Enable the TIM Capture/Compare 2 interrupt */
2253 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2254 break;
2255 }
2256
2257 case TIM_CHANNEL_3:
2258 {
2259 /* Enable the TIM Capture/Compare 3 interrupt */
2260 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
2261 break;
2262 }
2263
2264 case TIM_CHANNEL_4:
2265 {
2266 /* Enable the TIM Capture/Compare 4 interrupt */
2267 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
2268 break;
2269 }
2270
2271 default:
2272 status = HAL_ERROR;
2273 break;
2274 }
2275
2276 if (status == HAL_OK)
2277 {
2278 /* Enable the Input Capture channel */
2279 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2280
2281 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2282 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2283 {
2284 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2285 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2286 {
2287 __HAL_TIM_ENABLE(htim);
2288 }
2289 }
2290 else
2291 {
2292 __HAL_TIM_ENABLE(htim);
2293 }
2294 }
2295
2296 /* Return function status */
2297 return status;
2298 }
2299
2300 /**
2301 * @brief Stops the TIM Input Capture measurement in interrupt mode.
2302 * @param htim TIM Input Capture handle
2303 * @param Channel TIM Channels to be disabled
2304 * This parameter can be one of the following values:
2305 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2306 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2307 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2308 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2309 * @retval HAL status
2310 */
HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2311 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2312 {
2313 HAL_StatusTypeDef status = HAL_OK;
2314
2315 /* Check the parameters */
2316 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2317
2318 switch (Channel)
2319 {
2320 case TIM_CHANNEL_1:
2321 {
2322 /* Disable the TIM Capture/Compare 1 interrupt */
2323 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2324 break;
2325 }
2326
2327 case TIM_CHANNEL_2:
2328 {
2329 /* Disable the TIM Capture/Compare 2 interrupt */
2330 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2331 break;
2332 }
2333
2334 case TIM_CHANNEL_3:
2335 {
2336 /* Disable the TIM Capture/Compare 3 interrupt */
2337 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
2338 break;
2339 }
2340
2341 case TIM_CHANNEL_4:
2342 {
2343 /* Disable the TIM Capture/Compare 4 interrupt */
2344 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
2345 break;
2346 }
2347
2348 default:
2349 status = HAL_ERROR;
2350 break;
2351 }
2352
2353 if (status == HAL_OK)
2354 {
2355 /* Disable the Input Capture channel */
2356 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2357
2358 /* Disable the Peripheral */
2359 __HAL_TIM_DISABLE(htim);
2360
2361 /* Set the TIM channel state */
2362 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2363 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2364 }
2365
2366 /* Return function status */
2367 return status;
2368 }
2369
2370 /**
2371 * @brief Starts the TIM Input Capture measurement in DMA mode.
2372 * @param htim TIM Input Capture handle
2373 * @param Channel TIM Channels to be enabled
2374 * This parameter can be one of the following values:
2375 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2376 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2377 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2378 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2379 * @param pData The destination Buffer address.
2380 * @param Length The length of data to be transferred from TIM peripheral to memory.
2381 * @retval HAL status
2382 */
HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)2383 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
2384 {
2385 HAL_StatusTypeDef status = HAL_OK;
2386 uint32_t tmpsmcr;
2387
2388 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2389 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2390
2391 /* Check the parameters */
2392 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2393 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2394
2395 /* Set the TIM channel state */
2396 if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
2397 || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
2398 {
2399 return HAL_BUSY;
2400 }
2401 else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
2402 && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
2403 {
2404 if ((pData == NULL) || (Length == 0U))
2405 {
2406 return HAL_ERROR;
2407 }
2408 else
2409 {
2410 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2411 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2412 }
2413 }
2414 else
2415 {
2416 return HAL_ERROR;
2417 }
2418
2419 /* Enable the Input Capture channel */
2420 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2421
2422 switch (Channel)
2423 {
2424 case TIM_CHANNEL_1:
2425 {
2426 /* Set the DMA capture callbacks */
2427 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2428 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2429
2430 /* Set the DMA error callback */
2431 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2432
2433 /* Enable the DMA channel */
2434 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
2435 Length) != HAL_OK)
2436 {
2437 /* Return error status */
2438 return HAL_ERROR;
2439 }
2440 /* Enable the TIM Capture/Compare 1 DMA request */
2441 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2442 break;
2443 }
2444
2445 case TIM_CHANNEL_2:
2446 {
2447 /* Set the DMA capture callbacks */
2448 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2449 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2450
2451 /* Set the DMA error callback */
2452 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2453
2454 /* Enable the DMA channel */
2455 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
2456 Length) != HAL_OK)
2457 {
2458 /* Return error status */
2459 return HAL_ERROR;
2460 }
2461 /* Enable the TIM Capture/Compare 2 DMA request */
2462 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2463 break;
2464 }
2465
2466 case TIM_CHANNEL_3:
2467 {
2468 /* Set the DMA capture callbacks */
2469 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
2470 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2471
2472 /* Set the DMA error callback */
2473 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
2474
2475 /* Enable the DMA channel */
2476 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
2477 Length) != HAL_OK)
2478 {
2479 /* Return error status */
2480 return HAL_ERROR;
2481 }
2482 /* Enable the TIM Capture/Compare 3 DMA request */
2483 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
2484 break;
2485 }
2486
2487 case TIM_CHANNEL_4:
2488 {
2489 /* Set the DMA capture callbacks */
2490 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
2491 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2492
2493 /* Set the DMA error callback */
2494 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
2495
2496 /* Enable the DMA channel */
2497 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
2498 Length) != HAL_OK)
2499 {
2500 /* Return error status */
2501 return HAL_ERROR;
2502 }
2503 /* Enable the TIM Capture/Compare 4 DMA request */
2504 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
2505 break;
2506 }
2507
2508 default:
2509 status = HAL_ERROR;
2510 break;
2511 }
2512
2513 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2514 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2515 {
2516 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2517 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2518 {
2519 __HAL_TIM_ENABLE(htim);
2520 }
2521 }
2522 else
2523 {
2524 __HAL_TIM_ENABLE(htim);
2525 }
2526
2527 /* Return function status */
2528 return status;
2529 }
2530
2531 /**
2532 * @brief Stops the TIM Input Capture measurement in DMA mode.
2533 * @param htim TIM Input Capture handle
2534 * @param Channel TIM Channels to be disabled
2535 * This parameter can be one of the following values:
2536 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2537 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2538 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2539 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2540 * @retval HAL status
2541 */
HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)2542 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2543 {
2544 HAL_StatusTypeDef status = HAL_OK;
2545
2546 /* Check the parameters */
2547 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2548 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2549
2550 /* Disable the Input Capture channel */
2551 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2552
2553 switch (Channel)
2554 {
2555 case TIM_CHANNEL_1:
2556 {
2557 /* Disable the TIM Capture/Compare 1 DMA request */
2558 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2559 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
2560 break;
2561 }
2562
2563 case TIM_CHANNEL_2:
2564 {
2565 /* Disable the TIM Capture/Compare 2 DMA request */
2566 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2567 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
2568 break;
2569 }
2570
2571 case TIM_CHANNEL_3:
2572 {
2573 /* Disable the TIM Capture/Compare 3 DMA request */
2574 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
2575 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
2576 break;
2577 }
2578
2579 case TIM_CHANNEL_4:
2580 {
2581 /* Disable the TIM Capture/Compare 4 DMA request */
2582 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
2583 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
2584 break;
2585 }
2586
2587 default:
2588 status = HAL_ERROR;
2589 break;
2590 }
2591
2592 if (status == HAL_OK)
2593 {
2594 /* Disable the Peripheral */
2595 __HAL_TIM_DISABLE(htim);
2596
2597 /* Set the TIM channel state */
2598 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2599 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2600 }
2601
2602 /* Return function status */
2603 return status;
2604 }
2605 /**
2606 * @}
2607 */
2608
2609 /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2610 * @brief TIM One Pulse functions
2611 *
2612 @verbatim
2613 ==============================================================================
2614 ##### TIM One Pulse functions #####
2615 ==============================================================================
2616 [..]
2617 This section provides functions allowing to:
2618 (+) Initialize and configure the TIM One Pulse.
2619 (+) De-initialize the TIM One Pulse.
2620 (+) Start the TIM One Pulse.
2621 (+) Stop the TIM One Pulse.
2622 (+) Start the TIM One Pulse and enable interrupt.
2623 (+) Stop the TIM One Pulse and disable interrupt.
2624 (+) Start the TIM One Pulse and enable DMA transfer.
2625 (+) Stop the TIM One Pulse and disable DMA transfer.
2626
2627 @endverbatim
2628 * @{
2629 */
2630 /**
2631 * @brief Initializes the TIM One Pulse Time Base according to the specified
2632 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
2633 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2634 * requires a timer reset to avoid unexpected direction
2635 * due to DIR bit readonly in center aligned mode.
2636 * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
2637 * @note When the timer instance is initialized in One Pulse mode, timer
2638 * channels 1 and channel 2 are reserved and cannot be used for other
2639 * purpose.
2640 * @param htim TIM One Pulse handle
2641 * @param OnePulseMode Select the One pulse mode.
2642 * This parameter can be one of the following values:
2643 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
2644 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
2645 * @retval HAL status
2646 */
HAL_TIM_OnePulse_Init(TIM_HandleTypeDef * htim,uint32_t OnePulseMode)2647 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
2648 {
2649 /* Check the TIM handle allocation */
2650 if (htim == NULL)
2651 {
2652 return HAL_ERROR;
2653 }
2654
2655 /* Check the parameters */
2656 assert_param(IS_TIM_INSTANCE(htim->Instance));
2657 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2658 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2659 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
2660 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
2661 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2662
2663 if (htim->State == HAL_TIM_STATE_RESET)
2664 {
2665 /* Allocate lock resource and initialize it */
2666 htim->Lock = HAL_UNLOCKED;
2667
2668 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2669 /* Reset interrupt callbacks to legacy weak callbacks */
2670 TIM_ResetCallback(htim);
2671
2672 if (htim->OnePulse_MspInitCallback == NULL)
2673 {
2674 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
2675 }
2676 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2677 htim->OnePulse_MspInitCallback(htim);
2678 #else
2679 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2680 HAL_TIM_OnePulse_MspInit(htim);
2681 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2682 }
2683
2684 /* Set the TIM state */
2685 htim->State = HAL_TIM_STATE_BUSY;
2686
2687 /* Configure the Time base in the One Pulse Mode */
2688 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2689
2690 /* Reset the OPM Bit */
2691 htim->Instance->CR1 &= ~TIM_CR1_OPM;
2692
2693 /* Configure the OPM Mode */
2694 htim->Instance->CR1 |= OnePulseMode;
2695
2696 /* Initialize the DMA burst operation state */
2697 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2698
2699 /* Initialize the TIM channels state */
2700 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2701 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2702 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2703 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2704
2705 /* Initialize the TIM state*/
2706 htim->State = HAL_TIM_STATE_READY;
2707
2708 return HAL_OK;
2709 }
2710
2711 /**
2712 * @brief DeInitializes the TIM One Pulse
2713 * @param htim TIM One Pulse handle
2714 * @retval HAL status
2715 */
HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef * htim)2716 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
2717 {
2718 /* Check the parameters */
2719 assert_param(IS_TIM_INSTANCE(htim->Instance));
2720
2721 htim->State = HAL_TIM_STATE_BUSY;
2722
2723 /* Disable the TIM Peripheral Clock */
2724 __HAL_TIM_DISABLE(htim);
2725
2726 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2727 if (htim->OnePulse_MspDeInitCallback == NULL)
2728 {
2729 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
2730 }
2731 /* DeInit the low level hardware */
2732 htim->OnePulse_MspDeInitCallback(htim);
2733 #else
2734 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2735 HAL_TIM_OnePulse_MspDeInit(htim);
2736 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2737
2738 /* Change the DMA burst operation state */
2739 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2740
2741 /* Set the TIM channel state */
2742 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2743 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2744 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2745 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2746
2747 /* Change TIM state */
2748 htim->State = HAL_TIM_STATE_RESET;
2749
2750 /* Release Lock */
2751 __HAL_UNLOCK(htim);
2752
2753 return HAL_OK;
2754 }
2755
2756 /**
2757 * @brief Initializes the TIM One Pulse MSP.
2758 * @param htim TIM One Pulse handle
2759 * @retval None
2760 */
HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef * htim)2761 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2762 {
2763 /* Prevent unused argument(s) compilation warning */
2764 UNUSED(htim);
2765
2766 /* NOTE : This function should not be modified, when the callback is needed,
2767 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2768 */
2769 }
2770
2771 /**
2772 * @brief DeInitializes TIM One Pulse MSP.
2773 * @param htim TIM One Pulse handle
2774 * @retval None
2775 */
HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef * htim)2776 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2777 {
2778 /* Prevent unused argument(s) compilation warning */
2779 UNUSED(htim);
2780
2781 /* NOTE : This function should not be modified, when the callback is needed,
2782 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2783 */
2784 }
2785
2786 /**
2787 * @brief Starts the TIM One Pulse signal generation.
2788 * @note Though OutputChannel parameter is deprecated and ignored by the function
2789 * it has been kept to avoid HAL_TIM API compatibility break.
2790 * @note The pulse output channel is determined when calling
2791 * @ref HAL_TIM_OnePulse_ConfigChannel().
2792 * @param htim TIM One Pulse handle
2793 * @param OutputChannel See note above
2794 * @retval HAL status
2795 */
HAL_TIM_OnePulse_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2796 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2797 {
2798 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2799 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2800 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2801 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2802
2803 /* Prevent unused argument(s) compilation warning */
2804 UNUSED(OutputChannel);
2805
2806 /* Check the TIM channels state */
2807 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2808 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2809 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2810 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2811 {
2812 return HAL_ERROR;
2813 }
2814
2815 /* Set the TIM channels state */
2816 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2817 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2818 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2819 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2820
2821 /* Enable the Capture compare and the Input Capture channels
2822 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2823 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2824 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2825 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2826
2827 No need to enable the counter, it's enabled automatically by hardware
2828 (the counter starts in response to a stimulus and generate a pulse */
2829
2830 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2831 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2832
2833 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2834 {
2835 /* Enable the main output */
2836 __HAL_TIM_MOE_ENABLE(htim);
2837 }
2838
2839 /* Return function status */
2840 return HAL_OK;
2841 }
2842
2843 /**
2844 * @brief Stops the TIM One Pulse signal generation.
2845 * @note Though OutputChannel parameter is deprecated and ignored by the function
2846 * it has been kept to avoid HAL_TIM API compatibility break.
2847 * @note The pulse output channel is determined when calling
2848 * @ref HAL_TIM_OnePulse_ConfigChannel().
2849 * @param htim TIM One Pulse handle
2850 * @param OutputChannel See note above
2851 * @retval HAL status
2852 */
HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2853 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2854 {
2855 /* Prevent unused argument(s) compilation warning */
2856 UNUSED(OutputChannel);
2857
2858 /* Disable the Capture compare and the Input Capture channels
2859 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2860 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2861 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2862 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2863
2864 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2865 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2866
2867 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2868 {
2869 /* Disable the Main Output */
2870 __HAL_TIM_MOE_DISABLE(htim);
2871 }
2872
2873 /* Disable the Peripheral */
2874 __HAL_TIM_DISABLE(htim);
2875
2876 /* Set the TIM channels state */
2877 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2878 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2879 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2880 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2881
2882 /* Return function status */
2883 return HAL_OK;
2884 }
2885
2886 /**
2887 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2888 * @note Though OutputChannel parameter is deprecated and ignored by the function
2889 * it has been kept to avoid HAL_TIM API compatibility break.
2890 * @note The pulse output channel is determined when calling
2891 * @ref HAL_TIM_OnePulse_ConfigChannel().
2892 * @param htim TIM One Pulse handle
2893 * @param OutputChannel See note above
2894 * @retval HAL status
2895 */
HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2896 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2897 {
2898 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2899 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2900 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2901 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2902
2903 /* Prevent unused argument(s) compilation warning */
2904 UNUSED(OutputChannel);
2905
2906 /* Check the TIM channels state */
2907 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2908 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2909 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2910 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2911 {
2912 return HAL_ERROR;
2913 }
2914
2915 /* Set the TIM channels state */
2916 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2917 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2918 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2919 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2920
2921 /* Enable the Capture compare and the Input Capture channels
2922 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2923 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2924 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2925 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2926
2927 No need to enable the counter, it's enabled automatically by hardware
2928 (the counter starts in response to a stimulus and generate a pulse */
2929
2930 /* Enable the TIM Capture/Compare 1 interrupt */
2931 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2932
2933 /* Enable the TIM Capture/Compare 2 interrupt */
2934 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2935
2936 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2937 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2938
2939 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2940 {
2941 /* Enable the main output */
2942 __HAL_TIM_MOE_ENABLE(htim);
2943 }
2944
2945 /* Return function status */
2946 return HAL_OK;
2947 }
2948
2949 /**
2950 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2951 * @note Though OutputChannel parameter is deprecated and ignored by the function
2952 * it has been kept to avoid HAL_TIM API compatibility break.
2953 * @note The pulse output channel is determined when calling
2954 * @ref HAL_TIM_OnePulse_ConfigChannel().
2955 * @param htim TIM One Pulse handle
2956 * @param OutputChannel See note above
2957 * @retval HAL status
2958 */
HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2959 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2960 {
2961 /* Prevent unused argument(s) compilation warning */
2962 UNUSED(OutputChannel);
2963
2964 /* Disable the TIM Capture/Compare 1 interrupt */
2965 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2966
2967 /* Disable the TIM Capture/Compare 2 interrupt */
2968 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2969
2970 /* Disable the Capture compare and the Input Capture channels
2971 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2972 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2973 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2974 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2975 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2976 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2977
2978 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2979 {
2980 /* Disable the Main Output */
2981 __HAL_TIM_MOE_DISABLE(htim);
2982 }
2983
2984 /* Disable the Peripheral */
2985 __HAL_TIM_DISABLE(htim);
2986
2987 /* Set the TIM channels state */
2988 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2989 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2990 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2991 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2992
2993 /* Return function status */
2994 return HAL_OK;
2995 }
2996
2997 /**
2998 * @}
2999 */
3000
3001 /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
3002 * @brief TIM Encoder functions
3003 *
3004 @verbatim
3005 ==============================================================================
3006 ##### TIM Encoder functions #####
3007 ==============================================================================
3008 [..]
3009 This section provides functions allowing to:
3010 (+) Initialize and configure the TIM Encoder.
3011 (+) De-initialize the TIM Encoder.
3012 (+) Start the TIM Encoder.
3013 (+) Stop the TIM Encoder.
3014 (+) Start the TIM Encoder and enable interrupt.
3015 (+) Stop the TIM Encoder and disable interrupt.
3016 (+) Start the TIM Encoder and enable DMA transfer.
3017 (+) Stop the TIM Encoder and disable DMA transfer.
3018
3019 @endverbatim
3020 * @{
3021 */
3022 /**
3023 * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
3024 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
3025 * requires a timer reset to avoid unexpected direction
3026 * due to DIR bit readonly in center aligned mode.
3027 * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
3028 * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
3029 * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
3030 * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
3031 * @note When the timer instance is initialized in Encoder mode, timer
3032 * channels 1 and channel 2 are reserved and cannot be used for other
3033 * purpose.
3034 * @param htim TIM Encoder Interface handle
3035 * @param sConfig TIM Encoder Interface configuration structure
3036 * @retval HAL status
3037 */
HAL_TIM_Encoder_Init(TIM_HandleTypeDef * htim,const TIM_Encoder_InitTypeDef * sConfig)3038 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
3039 {
3040 uint32_t tmpsmcr;
3041 uint32_t tmpccmr1;
3042 uint32_t tmpccer;
3043
3044 /* Check the TIM handle allocation */
3045 if (htim == NULL)
3046 {
3047 return HAL_ERROR;
3048 }
3049
3050 /* Check the parameters */
3051 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3052 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
3053 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
3054 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
3055 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
3056 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
3057 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
3058 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
3059 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
3060 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
3061 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
3062 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
3063 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
3064 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
3065
3066 if (htim->State == HAL_TIM_STATE_RESET)
3067 {
3068 /* Allocate lock resource and initialize it */
3069 htim->Lock = HAL_UNLOCKED;
3070
3071 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3072 /* Reset interrupt callbacks to legacy weak callbacks */
3073 TIM_ResetCallback(htim);
3074
3075 if (htim->Encoder_MspInitCallback == NULL)
3076 {
3077 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
3078 }
3079 /* Init the low level hardware : GPIO, CLOCK, NVIC */
3080 htim->Encoder_MspInitCallback(htim);
3081 #else
3082 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
3083 HAL_TIM_Encoder_MspInit(htim);
3084 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3085 }
3086
3087 /* Set the TIM state */
3088 htim->State = HAL_TIM_STATE_BUSY;
3089
3090 /* Reset the SMS and ECE bits */
3091 htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
3092
3093 /* Configure the Time base in the Encoder Mode */
3094 TIM_Base_SetConfig(htim->Instance, &htim->Init);
3095
3096 /* Get the TIMx SMCR register value */
3097 tmpsmcr = htim->Instance->SMCR;
3098
3099 /* Get the TIMx CCMR1 register value */
3100 tmpccmr1 = htim->Instance->CCMR1;
3101
3102 /* Get the TIMx CCER register value */
3103 tmpccer = htim->Instance->CCER;
3104
3105 /* Set the encoder Mode */
3106 tmpsmcr |= sConfig->EncoderMode;
3107
3108 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
3109 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
3110 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
3111
3112 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
3113 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
3114 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
3115 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
3116 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
3117
3118 /* Set the TI1 and the TI2 Polarities */
3119 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
3120 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
3121 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
3122
3123 /* Write to TIMx SMCR */
3124 htim->Instance->SMCR = tmpsmcr;
3125
3126 /* Write to TIMx CCMR1 */
3127 htim->Instance->CCMR1 = tmpccmr1;
3128
3129 /* Write to TIMx CCER */
3130 htim->Instance->CCER = tmpccer;
3131
3132 /* Initialize the DMA burst operation state */
3133 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
3134
3135 /* Set the TIM channels state */
3136 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3137 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3138 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3139 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3140
3141 /* Initialize the TIM state*/
3142 htim->State = HAL_TIM_STATE_READY;
3143
3144 return HAL_OK;
3145 }
3146
3147
3148 /**
3149 * @brief DeInitializes the TIM Encoder interface
3150 * @param htim TIM Encoder Interface handle
3151 * @retval HAL status
3152 */
HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef * htim)3153 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
3154 {
3155 /* Check the parameters */
3156 assert_param(IS_TIM_INSTANCE(htim->Instance));
3157
3158 htim->State = HAL_TIM_STATE_BUSY;
3159
3160 /* Disable the TIM Peripheral Clock */
3161 __HAL_TIM_DISABLE(htim);
3162
3163 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3164 if (htim->Encoder_MspDeInitCallback == NULL)
3165 {
3166 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
3167 }
3168 /* DeInit the low level hardware */
3169 htim->Encoder_MspDeInitCallback(htim);
3170 #else
3171 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
3172 HAL_TIM_Encoder_MspDeInit(htim);
3173 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3174
3175 /* Change the DMA burst operation state */
3176 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
3177
3178 /* Set the TIM channels state */
3179 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3180 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3181 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3182 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3183
3184 /* Change TIM state */
3185 htim->State = HAL_TIM_STATE_RESET;
3186
3187 /* Release Lock */
3188 __HAL_UNLOCK(htim);
3189
3190 return HAL_OK;
3191 }
3192
3193 /**
3194 * @brief Initializes the TIM Encoder Interface MSP.
3195 * @param htim TIM Encoder Interface handle
3196 * @retval None
3197 */
HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef * htim)3198 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
3199 {
3200 /* Prevent unused argument(s) compilation warning */
3201 UNUSED(htim);
3202
3203 /* NOTE : This function should not be modified, when the callback is needed,
3204 the HAL_TIM_Encoder_MspInit could be implemented in the user file
3205 */
3206 }
3207
3208 /**
3209 * @brief DeInitializes TIM Encoder Interface MSP.
3210 * @param htim TIM Encoder Interface handle
3211 * @retval None
3212 */
HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef * htim)3213 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
3214 {
3215 /* Prevent unused argument(s) compilation warning */
3216 UNUSED(htim);
3217
3218 /* NOTE : This function should not be modified, when the callback is needed,
3219 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
3220 */
3221 }
3222
3223 /**
3224 * @brief Starts the TIM Encoder Interface.
3225 * @param htim TIM Encoder Interface handle
3226 * @param Channel TIM Channels to be enabled
3227 * This parameter can be one of the following values:
3228 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3229 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3230 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3231 * @retval HAL status
3232 */
HAL_TIM_Encoder_Start(TIM_HandleTypeDef * htim,uint32_t Channel)3233 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
3234 {
3235 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3236 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3237 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3238 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3239
3240 /* Check the parameters */
3241 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3242
3243 /* Set the TIM channel(s) state */
3244 if (Channel == TIM_CHANNEL_1)
3245 {
3246 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3247 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3248 {
3249 return HAL_ERROR;
3250 }
3251 else
3252 {
3253 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3254 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3255 }
3256 }
3257 else if (Channel == TIM_CHANNEL_2)
3258 {
3259 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3260 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3261 {
3262 return HAL_ERROR;
3263 }
3264 else
3265 {
3266 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3267 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3268 }
3269 }
3270 else
3271 {
3272 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3273 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3274 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3275 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3276 {
3277 return HAL_ERROR;
3278 }
3279 else
3280 {
3281 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3282 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3283 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3284 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3285 }
3286 }
3287
3288 /* Enable the encoder interface channels */
3289 switch (Channel)
3290 {
3291 case TIM_CHANNEL_1:
3292 {
3293 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3294 break;
3295 }
3296
3297 case TIM_CHANNEL_2:
3298 {
3299 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3300 break;
3301 }
3302
3303 default :
3304 {
3305 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3306 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3307 break;
3308 }
3309 }
3310 /* Enable the Peripheral */
3311 __HAL_TIM_ENABLE(htim);
3312
3313 /* Return function status */
3314 return HAL_OK;
3315 }
3316
3317 /**
3318 * @brief Stops the TIM Encoder Interface.
3319 * @param htim TIM Encoder Interface handle
3320 * @param Channel TIM Channels to be disabled
3321 * This parameter can be one of the following values:
3322 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3323 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3324 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3325 * @retval HAL status
3326 */
HAL_TIM_Encoder_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)3327 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
3328 {
3329 /* Check the parameters */
3330 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3331
3332 /* Disable the Input Capture channels 1 and 2
3333 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3334 switch (Channel)
3335 {
3336 case TIM_CHANNEL_1:
3337 {
3338 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3339 break;
3340 }
3341
3342 case TIM_CHANNEL_2:
3343 {
3344 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3345 break;
3346 }
3347
3348 default :
3349 {
3350 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3351 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3352 break;
3353 }
3354 }
3355
3356 /* Disable the Peripheral */
3357 __HAL_TIM_DISABLE(htim);
3358
3359 /* Set the TIM channel(s) state */
3360 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3361 {
3362 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3363 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3364 }
3365 else
3366 {
3367 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3368 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3369 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3370 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3371 }
3372
3373 /* Return function status */
3374 return HAL_OK;
3375 }
3376
3377 /**
3378 * @brief Starts the TIM Encoder Interface in interrupt mode.
3379 * @param htim TIM Encoder Interface handle
3380 * @param Channel TIM Channels to be enabled
3381 * This parameter can be one of the following values:
3382 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3383 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3384 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3385 * @retval HAL status
3386 */
HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3387 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3388 {
3389 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3390 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3391 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3392 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3393
3394 /* Check the parameters */
3395 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3396
3397 /* Set the TIM channel(s) state */
3398 if (Channel == TIM_CHANNEL_1)
3399 {
3400 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3401 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3402 {
3403 return HAL_ERROR;
3404 }
3405 else
3406 {
3407 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3408 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3409 }
3410 }
3411 else if (Channel == TIM_CHANNEL_2)
3412 {
3413 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3414 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3415 {
3416 return HAL_ERROR;
3417 }
3418 else
3419 {
3420 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3421 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3422 }
3423 }
3424 else
3425 {
3426 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3427 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3428 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3429 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3430 {
3431 return HAL_ERROR;
3432 }
3433 else
3434 {
3435 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3436 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3437 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3438 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3439 }
3440 }
3441
3442 /* Enable the encoder interface channels */
3443 /* Enable the capture compare Interrupts 1 and/or 2 */
3444 switch (Channel)
3445 {
3446 case TIM_CHANNEL_1:
3447 {
3448 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3449 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3450 break;
3451 }
3452
3453 case TIM_CHANNEL_2:
3454 {
3455 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3456 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3457 break;
3458 }
3459
3460 default :
3461 {
3462 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3463 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3464 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3465 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3466 break;
3467 }
3468 }
3469
3470 /* Enable the Peripheral */
3471 __HAL_TIM_ENABLE(htim);
3472
3473 /* Return function status */
3474 return HAL_OK;
3475 }
3476
3477 /**
3478 * @brief Stops the TIM Encoder Interface in interrupt mode.
3479 * @param htim TIM Encoder Interface handle
3480 * @param Channel TIM Channels to be disabled
3481 * This parameter can be one of the following values:
3482 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3483 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3484 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3485 * @retval HAL status
3486 */
HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3487 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3488 {
3489 /* Check the parameters */
3490 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3491
3492 /* Disable the Input Capture channels 1 and 2
3493 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3494 if (Channel == TIM_CHANNEL_1)
3495 {
3496 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3497
3498 /* Disable the capture compare Interrupts 1 */
3499 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3500 }
3501 else if (Channel == TIM_CHANNEL_2)
3502 {
3503 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3504
3505 /* Disable the capture compare Interrupts 2 */
3506 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3507 }
3508 else
3509 {
3510 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3511 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3512
3513 /* Disable the capture compare Interrupts 1 and 2 */
3514 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3515 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3516 }
3517
3518 /* Disable the Peripheral */
3519 __HAL_TIM_DISABLE(htim);
3520
3521 /* Set the TIM channel(s) state */
3522 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3523 {
3524 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3525 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3526 }
3527 else
3528 {
3529 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3530 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3531 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3532 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3533 }
3534
3535 /* Return function status */
3536 return HAL_OK;
3537 }
3538
3539 /**
3540 * @brief Starts the TIM Encoder Interface in DMA mode.
3541 * @param htim TIM Encoder Interface handle
3542 * @param Channel TIM Channels to be enabled
3543 * This parameter can be one of the following values:
3544 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3545 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3546 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3547 * @param pData1 The destination Buffer address for IC1.
3548 * @param pData2 The destination Buffer address for IC2.
3549 * @param Length The length of data to be transferred from TIM peripheral to memory.
3550 * @retval HAL status
3551 */
HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData1,uint32_t * pData2,uint16_t Length)3552 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
3553 uint32_t *pData2, uint16_t Length)
3554 {
3555 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3556 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3557 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3558 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3559
3560 /* Check the parameters */
3561 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3562
3563 /* Set the TIM channel(s) state */
3564 if (Channel == TIM_CHANNEL_1)
3565 {
3566 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3567 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
3568 {
3569 return HAL_BUSY;
3570 }
3571 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3572 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
3573 {
3574 if ((pData1 == NULL) || (Length == 0U))
3575 {
3576 return HAL_ERROR;
3577 }
3578 else
3579 {
3580 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3581 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3582 }
3583 }
3584 else
3585 {
3586 return HAL_ERROR;
3587 }
3588 }
3589 else if (Channel == TIM_CHANNEL_2)
3590 {
3591 if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3592 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3593 {
3594 return HAL_BUSY;
3595 }
3596 else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3597 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3598 {
3599 if ((pData2 == NULL) || (Length == 0U))
3600 {
3601 return HAL_ERROR;
3602 }
3603 else
3604 {
3605 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3606 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3607 }
3608 }
3609 else
3610 {
3611 return HAL_ERROR;
3612 }
3613 }
3614 else
3615 {
3616 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3617 || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3618 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3619 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3620 {
3621 return HAL_BUSY;
3622 }
3623 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3624 && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3625 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3626 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3627 {
3628 if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U))
3629 {
3630 return HAL_ERROR;
3631 }
3632 else
3633 {
3634 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3635 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3636 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3637 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3638 }
3639 }
3640 else
3641 {
3642 return HAL_ERROR;
3643 }
3644 }
3645
3646 switch (Channel)
3647 {
3648 case TIM_CHANNEL_1:
3649 {
3650 /* Set the DMA capture callbacks */
3651 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3652 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3653
3654 /* Set the DMA error callback */
3655 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3656
3657 /* Enable the DMA channel */
3658 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3659 Length) != HAL_OK)
3660 {
3661 /* Return error status */
3662 return HAL_ERROR;
3663 }
3664 /* Enable the TIM Input Capture DMA request */
3665 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3666
3667 /* Enable the Capture compare channel */
3668 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3669
3670 /* Enable the Peripheral */
3671 __HAL_TIM_ENABLE(htim);
3672
3673 break;
3674 }
3675
3676 case TIM_CHANNEL_2:
3677 {
3678 /* Set the DMA capture callbacks */
3679 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3680 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3681
3682 /* Set the DMA error callback */
3683 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
3684 /* Enable the DMA channel */
3685 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3686 Length) != HAL_OK)
3687 {
3688 /* Return error status */
3689 return HAL_ERROR;
3690 }
3691 /* Enable the TIM Input Capture DMA request */
3692 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3693
3694 /* Enable the Capture compare channel */
3695 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3696
3697 /* Enable the Peripheral */
3698 __HAL_TIM_ENABLE(htim);
3699
3700 break;
3701 }
3702
3703 default:
3704 {
3705 /* Set the DMA capture callbacks */
3706 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3707 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3708
3709 /* Set the DMA error callback */
3710 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3711
3712 /* Enable the DMA channel */
3713 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3714 Length) != HAL_OK)
3715 {
3716 /* Return error status */
3717 return HAL_ERROR;
3718 }
3719
3720 /* Set the DMA capture callbacks */
3721 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3722 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3723
3724 /* Set the DMA error callback */
3725 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3726
3727 /* Enable the DMA channel */
3728 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3729 Length) != HAL_OK)
3730 {
3731 /* Return error status */
3732 return HAL_ERROR;
3733 }
3734
3735 /* Enable the TIM Input Capture DMA request */
3736 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3737 /* Enable the TIM Input Capture DMA request */
3738 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3739
3740 /* Enable the Capture compare channel */
3741 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3742 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3743
3744 /* Enable the Peripheral */
3745 __HAL_TIM_ENABLE(htim);
3746
3747 break;
3748 }
3749 }
3750
3751 /* Return function status */
3752 return HAL_OK;
3753 }
3754
3755 /**
3756 * @brief Stops the TIM Encoder Interface in DMA mode.
3757 * @param htim TIM Encoder Interface handle
3758 * @param Channel TIM Channels to be enabled
3759 * This parameter can be one of the following values:
3760 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3761 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3762 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3763 * @retval HAL status
3764 */
HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)3765 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
3766 {
3767 /* Check the parameters */
3768 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3769
3770 /* Disable the Input Capture channels 1 and 2
3771 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3772 if (Channel == TIM_CHANNEL_1)
3773 {
3774 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3775
3776 /* Disable the capture compare DMA Request 1 */
3777 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3778 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3779 }
3780 else if (Channel == TIM_CHANNEL_2)
3781 {
3782 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3783
3784 /* Disable the capture compare DMA Request 2 */
3785 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3786 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3787 }
3788 else
3789 {
3790 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3791 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3792
3793 /* Disable the capture compare DMA Request 1 and 2 */
3794 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3795 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3796 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3797 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3798 }
3799
3800 /* Disable the Peripheral */
3801 __HAL_TIM_DISABLE(htim);
3802
3803 /* Set the TIM channel(s) state */
3804 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3805 {
3806 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3807 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3808 }
3809 else
3810 {
3811 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3812 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3813 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3814 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3815 }
3816
3817 /* Return function status */
3818 return HAL_OK;
3819 }
3820
3821 /**
3822 * @}
3823 */
3824 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
3825 * @brief TIM IRQ handler management
3826 *
3827 @verbatim
3828 ==============================================================================
3829 ##### IRQ handler management #####
3830 ==============================================================================
3831 [..]
3832 This section provides Timer IRQ handler function.
3833
3834 @endverbatim
3835 * @{
3836 */
3837 /**
3838 * @brief This function handles TIM interrupts requests.
3839 * @param htim TIM handle
3840 * @retval None
3841 */
HAL_TIM_IRQHandler(TIM_HandleTypeDef * htim)3842 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
3843 {
3844 uint32_t itsource = htim->Instance->DIER;
3845 uint32_t itflag = htim->Instance->SR;
3846
3847 /* Capture compare 1 event */
3848 if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
3849 {
3850 if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
3851 {
3852 {
3853 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
3854 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3855
3856 /* Input capture event */
3857 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
3858 {
3859 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3860 htim->IC_CaptureCallback(htim);
3861 #else
3862 HAL_TIM_IC_CaptureCallback(htim);
3863 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3864 }
3865 /* Output compare event */
3866 else
3867 {
3868 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3869 htim->OC_DelayElapsedCallback(htim);
3870 htim->PWM_PulseFinishedCallback(htim);
3871 #else
3872 HAL_TIM_OC_DelayElapsedCallback(htim);
3873 HAL_TIM_PWM_PulseFinishedCallback(htim);
3874 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3875 }
3876 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3877 }
3878 }
3879 }
3880 /* Capture compare 2 event */
3881 if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
3882 {
3883 if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
3884 {
3885 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
3886 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3887 /* Input capture event */
3888 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
3889 {
3890 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3891 htim->IC_CaptureCallback(htim);
3892 #else
3893 HAL_TIM_IC_CaptureCallback(htim);
3894 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3895 }
3896 /* Output compare event */
3897 else
3898 {
3899 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3900 htim->OC_DelayElapsedCallback(htim);
3901 htim->PWM_PulseFinishedCallback(htim);
3902 #else
3903 HAL_TIM_OC_DelayElapsedCallback(htim);
3904 HAL_TIM_PWM_PulseFinishedCallback(htim);
3905 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3906 }
3907 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3908 }
3909 }
3910 /* Capture compare 3 event */
3911 if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
3912 {
3913 if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
3914 {
3915 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
3916 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3917 /* Input capture event */
3918 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
3919 {
3920 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3921 htim->IC_CaptureCallback(htim);
3922 #else
3923 HAL_TIM_IC_CaptureCallback(htim);
3924 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3925 }
3926 /* Output compare event */
3927 else
3928 {
3929 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3930 htim->OC_DelayElapsedCallback(htim);
3931 htim->PWM_PulseFinishedCallback(htim);
3932 #else
3933 HAL_TIM_OC_DelayElapsedCallback(htim);
3934 HAL_TIM_PWM_PulseFinishedCallback(htim);
3935 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3936 }
3937 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3938 }
3939 }
3940 /* Capture compare 4 event */
3941 if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
3942 {
3943 if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
3944 {
3945 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
3946 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3947 /* Input capture event */
3948 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
3949 {
3950 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3951 htim->IC_CaptureCallback(htim);
3952 #else
3953 HAL_TIM_IC_CaptureCallback(htim);
3954 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3955 }
3956 /* Output compare event */
3957 else
3958 {
3959 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3960 htim->OC_DelayElapsedCallback(htim);
3961 htim->PWM_PulseFinishedCallback(htim);
3962 #else
3963 HAL_TIM_OC_DelayElapsedCallback(htim);
3964 HAL_TIM_PWM_PulseFinishedCallback(htim);
3965 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3966 }
3967 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3968 }
3969 }
3970 /* TIM Update event */
3971 if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
3972 {
3973 if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
3974 {
3975 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
3976 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3977 htim->PeriodElapsedCallback(htim);
3978 #else
3979 HAL_TIM_PeriodElapsedCallback(htim);
3980 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3981 }
3982 }
3983 /* TIM Break input event */
3984 if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK))
3985 {
3986 if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
3987 {
3988 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK);
3989 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3990 htim->BreakCallback(htim);
3991 #else
3992 HAL_TIMEx_BreakCallback(htim);
3993 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3994 }
3995 }
3996 #if defined(TIM_BDTR_BK2E)
3997 /* TIM Break2 input event */
3998 if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
3999 {
4000 if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
4001 {
4002 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
4003 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4004 htim->Break2Callback(htim);
4005 #else
4006 HAL_TIMEx_Break2Callback(htim);
4007 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4008 }
4009 }
4010 #endif /* TIM_BDTR_BK2E */
4011 /* TIM Trigger detection event */
4012 if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
4013 {
4014 if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
4015 {
4016 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
4017 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4018 htim->TriggerCallback(htim);
4019 #else
4020 HAL_TIM_TriggerCallback(htim);
4021 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4022 }
4023 }
4024 /* TIM commutation event */
4025 if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
4026 {
4027 if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
4028 {
4029 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
4030 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4031 htim->CommutationCallback(htim);
4032 #else
4033 HAL_TIMEx_CommutCallback(htim);
4034 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4035 }
4036 }
4037 }
4038
4039 /**
4040 * @}
4041 */
4042
4043 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
4044 * @brief TIM Peripheral Control functions
4045 *
4046 @verbatim
4047 ==============================================================================
4048 ##### Peripheral Control functions #####
4049 ==============================================================================
4050 [..]
4051 This section provides functions allowing to:
4052 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
4053 (+) Configure External Clock source.
4054 (+) Configure Complementary channels, break features and dead time.
4055 (+) Configure Master and the Slave synchronization.
4056 (+) Configure the DMA Burst Mode.
4057
4058 @endverbatim
4059 * @{
4060 */
4061
4062 /**
4063 * @brief Initializes the TIM Output Compare Channels according to the specified
4064 * parameters in the TIM_OC_InitTypeDef.
4065 * @param htim TIM Output Compare handle
4066 * @param sConfig TIM Output Compare configuration structure
4067 * @param Channel TIM Channels to configure
4068 * This parameter can be one of the following values:
4069 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4070 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4071 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4072 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4073 * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*)
4074 * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*)
4075 * (*) Value not defined for all devices
4076 * @retval HAL status
4077 */
HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4078 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
4079 const TIM_OC_InitTypeDef *sConfig,
4080 uint32_t Channel)
4081 {
4082 HAL_StatusTypeDef status = HAL_OK;
4083
4084 /* Check the parameters */
4085 assert_param(IS_TIM_CHANNELS(Channel));
4086 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
4087 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4088
4089 /* Process Locked */
4090 __HAL_LOCK(htim);
4091
4092 switch (Channel)
4093 {
4094 case TIM_CHANNEL_1:
4095 {
4096 /* Check the parameters */
4097 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4098
4099 /* Configure the TIM Channel 1 in Output Compare */
4100 TIM_OC1_SetConfig(htim->Instance, sConfig);
4101 break;
4102 }
4103
4104 case TIM_CHANNEL_2:
4105 {
4106 /* Check the parameters */
4107 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4108
4109 /* Configure the TIM Channel 2 in Output Compare */
4110 TIM_OC2_SetConfig(htim->Instance, sConfig);
4111 break;
4112 }
4113
4114 case TIM_CHANNEL_3:
4115 {
4116 /* Check the parameters */
4117 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4118
4119 /* Configure the TIM Channel 3 in Output Compare */
4120 TIM_OC3_SetConfig(htim->Instance, sConfig);
4121 break;
4122 }
4123
4124 case TIM_CHANNEL_4:
4125 {
4126 /* Check the parameters */
4127 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4128
4129 /* Configure the TIM Channel 4 in Output Compare */
4130 TIM_OC4_SetConfig(htim->Instance, sConfig);
4131 break;
4132 }
4133
4134 #if defined(TIM_CCER_CC5E)
4135 case TIM_CHANNEL_5:
4136 {
4137 /* Check the parameters */
4138 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
4139
4140 /* Configure the TIM Channel 5 in Output Compare */
4141 TIM_OC5_SetConfig(htim->Instance, sConfig);
4142 break;
4143 }
4144 #endif /* TIM_CCER_CC5E */
4145
4146 #if defined(TIM_CCER_CC6E)
4147 case TIM_CHANNEL_6:
4148 {
4149 /* Check the parameters */
4150 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
4151
4152 /* Configure the TIM Channel 6 in Output Compare */
4153 TIM_OC6_SetConfig(htim->Instance, sConfig);
4154 break;
4155 }
4156 #endif /* TIM_CCER_CC6E */
4157
4158 default:
4159 status = HAL_ERROR;
4160 break;
4161 }
4162
4163 __HAL_UNLOCK(htim);
4164
4165 return status;
4166 }
4167
4168 /**
4169 * @brief Initializes the TIM Input Capture Channels according to the specified
4170 * parameters in the TIM_IC_InitTypeDef.
4171 * @param htim TIM IC handle
4172 * @param sConfig TIM Input Capture configuration structure
4173 * @param Channel TIM Channel to configure
4174 * This parameter can be one of the following values:
4175 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4176 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4177 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4178 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4179 * @retval HAL status
4180 */
HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_IC_InitTypeDef * sConfig,uint32_t Channel)4181 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
4182 {
4183 HAL_StatusTypeDef status = HAL_OK;
4184
4185 /* Check the parameters */
4186 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4187 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
4188 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
4189 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
4190 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
4191
4192 /* Process Locked */
4193 __HAL_LOCK(htim);
4194
4195 if (Channel == TIM_CHANNEL_1)
4196 {
4197 /* TI1 Configuration */
4198 TIM_TI1_SetConfig(htim->Instance,
4199 sConfig->ICPolarity,
4200 sConfig->ICSelection,
4201 sConfig->ICFilter);
4202
4203 /* Reset the IC1PSC Bits */
4204 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4205
4206 /* Set the IC1PSC value */
4207 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
4208 }
4209 else if (Channel == TIM_CHANNEL_2)
4210 {
4211 /* TI2 Configuration */
4212 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4213
4214 TIM_TI2_SetConfig(htim->Instance,
4215 sConfig->ICPolarity,
4216 sConfig->ICSelection,
4217 sConfig->ICFilter);
4218
4219 /* Reset the IC2PSC Bits */
4220 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4221
4222 /* Set the IC2PSC value */
4223 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
4224 }
4225 else if (Channel == TIM_CHANNEL_3)
4226 {
4227 /* TI3 Configuration */
4228 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4229
4230 TIM_TI3_SetConfig(htim->Instance,
4231 sConfig->ICPolarity,
4232 sConfig->ICSelection,
4233 sConfig->ICFilter);
4234
4235 /* Reset the IC3PSC Bits */
4236 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
4237
4238 /* Set the IC3PSC value */
4239 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
4240 }
4241 else if (Channel == TIM_CHANNEL_4)
4242 {
4243 /* TI4 Configuration */
4244 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4245
4246 TIM_TI4_SetConfig(htim->Instance,
4247 sConfig->ICPolarity,
4248 sConfig->ICSelection,
4249 sConfig->ICFilter);
4250
4251 /* Reset the IC4PSC Bits */
4252 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
4253
4254 /* Set the IC4PSC value */
4255 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
4256 }
4257 else
4258 {
4259 status = HAL_ERROR;
4260 }
4261
4262 __HAL_UNLOCK(htim);
4263
4264 return status;
4265 }
4266
4267 /**
4268 * @brief Initializes the TIM PWM channels according to the specified
4269 * parameters in the TIM_OC_InitTypeDef.
4270 * @param htim TIM PWM handle
4271 * @param sConfig TIM PWM configuration structure
4272 * @param Channel TIM Channels to be configured
4273 * This parameter can be one of the following values:
4274 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4275 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4276 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4277 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4278 * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*)
4279 * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*)
4280 * (*) Value not defined for all devices
4281 * @retval HAL status
4282 */
HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4283 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
4284 const TIM_OC_InitTypeDef *sConfig,
4285 uint32_t Channel)
4286 {
4287 HAL_StatusTypeDef status = HAL_OK;
4288
4289 /* Check the parameters */
4290 assert_param(IS_TIM_CHANNELS(Channel));
4291 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
4292 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4293 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
4294
4295 /* Process Locked */
4296 __HAL_LOCK(htim);
4297
4298 switch (Channel)
4299 {
4300 case TIM_CHANNEL_1:
4301 {
4302 /* Check the parameters */
4303 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4304
4305 /* Configure the Channel 1 in PWM mode */
4306 TIM_OC1_SetConfig(htim->Instance, sConfig);
4307
4308 /* Set the Preload enable bit for channel1 */
4309 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
4310
4311 /* Configure the Output Fast mode */
4312 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
4313 htim->Instance->CCMR1 |= sConfig->OCFastMode;
4314 break;
4315 }
4316
4317 case TIM_CHANNEL_2:
4318 {
4319 /* Check the parameters */
4320 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4321
4322 /* Configure the Channel 2 in PWM mode */
4323 TIM_OC2_SetConfig(htim->Instance, sConfig);
4324
4325 /* Set the Preload enable bit for channel2 */
4326 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
4327
4328 /* Configure the Output Fast mode */
4329 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
4330 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
4331 break;
4332 }
4333
4334 case TIM_CHANNEL_3:
4335 {
4336 /* Check the parameters */
4337 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4338
4339 /* Configure the Channel 3 in PWM mode */
4340 TIM_OC3_SetConfig(htim->Instance, sConfig);
4341
4342 /* Set the Preload enable bit for channel3 */
4343 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
4344
4345 /* Configure the Output Fast mode */
4346 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
4347 htim->Instance->CCMR2 |= sConfig->OCFastMode;
4348 break;
4349 }
4350
4351 case TIM_CHANNEL_4:
4352 {
4353 /* Check the parameters */
4354 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4355
4356 /* Configure the Channel 4 in PWM mode */
4357 TIM_OC4_SetConfig(htim->Instance, sConfig);
4358
4359 /* Set the Preload enable bit for channel4 */
4360 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
4361
4362 /* Configure the Output Fast mode */
4363 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
4364 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
4365 break;
4366 }
4367
4368 #if defined(TIM_CCER_CC5E)
4369 case TIM_CHANNEL_5:
4370 {
4371 /* Check the parameters */
4372 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
4373
4374 /* Configure the Channel 5 in PWM mode */
4375 TIM_OC5_SetConfig(htim->Instance, sConfig);
4376
4377 /* Set the Preload enable bit for channel5*/
4378 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
4379
4380 /* Configure the Output Fast mode */
4381 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
4382 htim->Instance->CCMR3 |= sConfig->OCFastMode;
4383 break;
4384 }
4385 #endif /* TIM_CCER_CC5E */
4386
4387 #if defined(TIM_CCER_CC6E)
4388 case TIM_CHANNEL_6:
4389 {
4390 /* Check the parameters */
4391 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
4392
4393 /* Configure the Channel 6 in PWM mode */
4394 TIM_OC6_SetConfig(htim->Instance, sConfig);
4395
4396 /* Set the Preload enable bit for channel6 */
4397 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
4398
4399 /* Configure the Output Fast mode */
4400 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
4401 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
4402 break;
4403 }
4404 #endif /* TIM_CCER_CC6E */
4405
4406 default:
4407 status = HAL_ERROR;
4408 break;
4409 }
4410
4411 __HAL_UNLOCK(htim);
4412
4413 return status;
4414 }
4415
4416 /**
4417 * @brief Initializes the TIM One Pulse Channels according to the specified
4418 * parameters in the TIM_OnePulse_InitTypeDef.
4419 * @param htim TIM One Pulse handle
4420 * @param sConfig TIM One Pulse configuration structure
4421 * @param OutputChannel TIM output channel to configure
4422 * This parameter can be one of the following values:
4423 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4424 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4425 * @param InputChannel TIM input Channel to configure
4426 * This parameter can be one of the following values:
4427 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4428 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4429 * @note To output a waveform with a minimum delay user can enable the fast
4430 * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
4431 * output is forced in response to the edge detection on TIx input,
4432 * without taking in account the comparison.
4433 * @retval HAL status
4434 */
HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OnePulse_InitTypeDef * sConfig,uint32_t OutputChannel,uint32_t InputChannel)4435 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
4436 uint32_t OutputChannel, uint32_t InputChannel)
4437 {
4438 HAL_StatusTypeDef status = HAL_OK;
4439 TIM_OC_InitTypeDef temp1;
4440
4441 /* Check the parameters */
4442 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
4443 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
4444
4445 if (OutputChannel != InputChannel)
4446 {
4447 /* Process Locked */
4448 __HAL_LOCK(htim);
4449
4450 htim->State = HAL_TIM_STATE_BUSY;
4451
4452 /* Extract the Output compare configuration from sConfig structure */
4453 temp1.OCMode = sConfig->OCMode;
4454 temp1.Pulse = sConfig->Pulse;
4455 temp1.OCPolarity = sConfig->OCPolarity;
4456 temp1.OCNPolarity = sConfig->OCNPolarity;
4457 temp1.OCIdleState = sConfig->OCIdleState;
4458 temp1.OCNIdleState = sConfig->OCNIdleState;
4459
4460 switch (OutputChannel)
4461 {
4462 case TIM_CHANNEL_1:
4463 {
4464 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4465
4466 TIM_OC1_SetConfig(htim->Instance, &temp1);
4467 break;
4468 }
4469
4470 case TIM_CHANNEL_2:
4471 {
4472 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4473
4474 TIM_OC2_SetConfig(htim->Instance, &temp1);
4475 break;
4476 }
4477
4478 default:
4479 status = HAL_ERROR;
4480 break;
4481 }
4482
4483 if (status == HAL_OK)
4484 {
4485 switch (InputChannel)
4486 {
4487 case TIM_CHANNEL_1:
4488 {
4489 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4490
4491 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
4492 sConfig->ICSelection, sConfig->ICFilter);
4493
4494 /* Reset the IC1PSC Bits */
4495 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4496
4497 /* Select the Trigger source */
4498 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4499 htim->Instance->SMCR |= TIM_TS_TI1FP1;
4500
4501 /* Select the Slave Mode */
4502 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4503 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4504 break;
4505 }
4506
4507 case TIM_CHANNEL_2:
4508 {
4509 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4510
4511 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
4512 sConfig->ICSelection, sConfig->ICFilter);
4513
4514 /* Reset the IC2PSC Bits */
4515 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4516
4517 /* Select the Trigger source */
4518 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4519 htim->Instance->SMCR |= TIM_TS_TI2FP2;
4520
4521 /* Select the Slave Mode */
4522 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4523 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4524 break;
4525 }
4526
4527 default:
4528 status = HAL_ERROR;
4529 break;
4530 }
4531 }
4532
4533 htim->State = HAL_TIM_STATE_READY;
4534
4535 __HAL_UNLOCK(htim);
4536
4537 return status;
4538 }
4539 else
4540 {
4541 return HAL_ERROR;
4542 }
4543 }
4544
4545 /**
4546 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
4547 * @param htim TIM handle
4548 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4549 * This parameter can be one of the following values:
4550 * @arg TIM_DMABASE_CR1
4551 * @arg TIM_DMABASE_CR2
4552 * @arg TIM_DMABASE_SMCR
4553 * @arg TIM_DMABASE_DIER
4554 * @arg TIM_DMABASE_SR
4555 * @arg TIM_DMABASE_EGR
4556 * @arg TIM_DMABASE_CCMR1
4557 * @arg TIM_DMABASE_CCMR2
4558 * @arg TIM_DMABASE_CCER
4559 * @arg TIM_DMABASE_CNT
4560 * @arg TIM_DMABASE_PSC
4561 * @arg TIM_DMABASE_ARR
4562 * @arg TIM_DMABASE_RCR
4563 * @arg TIM_DMABASE_CCR1
4564 * @arg TIM_DMABASE_CCR2
4565 * @arg TIM_DMABASE_CCR3
4566 * @arg TIM_DMABASE_CCR4
4567 * @arg TIM_DMABASE_BDTR
4568 * @arg TIM_DMABASE_OR
4569 * @arg TIM_DMABASE_CCMR3 (*)
4570 * @arg TIM_DMABASE_CCR5 (*)
4571 * @arg TIM_DMABASE_CCR6 (*)
4572 * (*) value not defined in all devices
4573 * @param BurstRequestSrc TIM DMA Request sources
4574 * This parameter can be one of the following values:
4575 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4576 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4577 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4578 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4579 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4580 * @arg TIM_DMA_COM: TIM Commutation DMA source
4581 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4582 * @param BurstBuffer The Buffer address.
4583 * @param BurstLength DMA Burst length. This parameter can be one value
4584 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4585 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4586 * @retval HAL status
4587 */
HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,const uint32_t * BurstBuffer,uint32_t BurstLength)4588 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4589 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
4590 uint32_t BurstLength)
4591 {
4592 HAL_StatusTypeDef status;
4593
4594 status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4595 ((BurstLength) >> 8U) + 1U);
4596
4597
4598
4599 return status;
4600 }
4601
4602 /**
4603 * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
4604 * @param htim TIM handle
4605 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4606 * This parameter can be one of the following values:
4607 * @arg TIM_DMABASE_CR1
4608 * @arg TIM_DMABASE_CR2
4609 * @arg TIM_DMABASE_SMCR
4610 * @arg TIM_DMABASE_DIER
4611 * @arg TIM_DMABASE_SR
4612 * @arg TIM_DMABASE_EGR
4613 * @arg TIM_DMABASE_CCMR1
4614 * @arg TIM_DMABASE_CCMR2
4615 * @arg TIM_DMABASE_CCER
4616 * @arg TIM_DMABASE_CNT
4617 * @arg TIM_DMABASE_PSC
4618 * @arg TIM_DMABASE_ARR
4619 * @arg TIM_DMABASE_RCR
4620 * @arg TIM_DMABASE_CCR1
4621 * @arg TIM_DMABASE_CCR2
4622 * @arg TIM_DMABASE_CCR3
4623 * @arg TIM_DMABASE_CCR4
4624 * @arg TIM_DMABASE_BDTR
4625 * @arg TIM_DMABASE_OR
4626 * @arg TIM_DMABASE_CCMR3 (*)
4627 * @arg TIM_DMABASE_CCR5 (*)
4628 * @arg TIM_DMABASE_CCR6 (*)
4629 * (*) value not defined in all devices
4630 * @param BurstRequestSrc TIM DMA Request sources
4631 * This parameter can be one of the following values:
4632 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4633 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4634 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4635 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4636 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4637 * @arg TIM_DMA_COM: TIM Commutation DMA source
4638 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4639 * @param BurstBuffer The Buffer address.
4640 * @param BurstLength DMA Burst length. This parameter can be one value
4641 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4642 * @param DataLength Data length. This parameter can be one value
4643 * between 1 and 0xFFFF.
4644 * @retval HAL status
4645 */
HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,const uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4646 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4647 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
4648 uint32_t BurstLength, uint32_t DataLength)
4649 {
4650 HAL_StatusTypeDef status = HAL_OK;
4651
4652 /* Check the parameters */
4653 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4654 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4655 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4656 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4657 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4658
4659 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4660 {
4661 return HAL_BUSY;
4662 }
4663 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4664 {
4665 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4666 {
4667 return HAL_ERROR;
4668 }
4669 else
4670 {
4671 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4672 }
4673 }
4674 else
4675 {
4676 /* nothing to do */
4677 }
4678
4679 switch (BurstRequestSrc)
4680 {
4681 case TIM_DMA_UPDATE:
4682 {
4683 /* Set the DMA Period elapsed callbacks */
4684 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4685 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4686
4687 /* Set the DMA error callback */
4688 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4689
4690 /* Enable the DMA channel */
4691 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
4692 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4693 {
4694 /* Return error status */
4695 return HAL_ERROR;
4696 }
4697 break;
4698 }
4699 case TIM_DMA_CC1:
4700 {
4701 /* Set the DMA compare callbacks */
4702 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
4703 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4704
4705 /* Set the DMA error callback */
4706 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4707
4708 /* Enable the DMA channel */
4709 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
4710 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4711 {
4712 /* Return error status */
4713 return HAL_ERROR;
4714 }
4715 break;
4716 }
4717 case TIM_DMA_CC2:
4718 {
4719 /* Set the DMA compare callbacks */
4720 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
4721 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4722
4723 /* Set the DMA error callback */
4724 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4725
4726 /* Enable the DMA channel */
4727 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
4728 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4729 {
4730 /* Return error status */
4731 return HAL_ERROR;
4732 }
4733 break;
4734 }
4735 case TIM_DMA_CC3:
4736 {
4737 /* Set the DMA compare callbacks */
4738 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
4739 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4740
4741 /* Set the DMA error callback */
4742 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4743
4744 /* Enable the DMA channel */
4745 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
4746 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4747 {
4748 /* Return error status */
4749 return HAL_ERROR;
4750 }
4751 break;
4752 }
4753 case TIM_DMA_CC4:
4754 {
4755 /* Set the DMA compare callbacks */
4756 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
4757 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4758
4759 /* Set the DMA error callback */
4760 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4761
4762 /* Enable the DMA channel */
4763 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
4764 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4765 {
4766 /* Return error status */
4767 return HAL_ERROR;
4768 }
4769 break;
4770 }
4771 case TIM_DMA_COM:
4772 {
4773 /* Set the DMA commutation callbacks */
4774 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4775 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
4776
4777 /* Set the DMA error callback */
4778 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4779
4780 /* Enable the DMA channel */
4781 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
4782 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4783 {
4784 /* Return error status */
4785 return HAL_ERROR;
4786 }
4787 break;
4788 }
4789 case TIM_DMA_TRIGGER:
4790 {
4791 /* Set the DMA trigger callbacks */
4792 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4793 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4794
4795 /* Set the DMA error callback */
4796 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4797
4798 /* Enable the DMA channel */
4799 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
4800 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4801 {
4802 /* Return error status */
4803 return HAL_ERROR;
4804 }
4805 break;
4806 }
4807 default:
4808 status = HAL_ERROR;
4809 break;
4810 }
4811
4812 if (status == HAL_OK)
4813 {
4814 /* Configure the DMA Burst Mode */
4815 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4816 /* Enable the TIM DMA Request */
4817 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4818 }
4819
4820 /* Return function status */
4821 return status;
4822 }
4823
4824 /**
4825 * @brief Stops the TIM DMA Burst mode
4826 * @param htim TIM handle
4827 * @param BurstRequestSrc TIM DMA Request sources to disable
4828 * @retval HAL status
4829 */
HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4830 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4831 {
4832 HAL_StatusTypeDef status = HAL_OK;
4833
4834 /* Check the parameters */
4835 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4836
4837 /* Abort the DMA transfer (at least disable the DMA channel) */
4838 switch (BurstRequestSrc)
4839 {
4840 case TIM_DMA_UPDATE:
4841 {
4842 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4843 break;
4844 }
4845 case TIM_DMA_CC1:
4846 {
4847 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4848 break;
4849 }
4850 case TIM_DMA_CC2:
4851 {
4852 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
4853 break;
4854 }
4855 case TIM_DMA_CC3:
4856 {
4857 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
4858 break;
4859 }
4860 case TIM_DMA_CC4:
4861 {
4862 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
4863 break;
4864 }
4865 case TIM_DMA_COM:
4866 {
4867 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
4868 break;
4869 }
4870 case TIM_DMA_TRIGGER:
4871 {
4872 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
4873 break;
4874 }
4875 default:
4876 status = HAL_ERROR;
4877 break;
4878 }
4879
4880 if (status == HAL_OK)
4881 {
4882 /* Disable the TIM Update DMA request */
4883 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4884
4885 /* Change the DMA burst operation state */
4886 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
4887 }
4888
4889 /* Return function status */
4890 return status;
4891 }
4892
4893 /**
4894 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4895 * @param htim TIM handle
4896 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4897 * This parameter can be one of the following values:
4898 * @arg TIM_DMABASE_CR1
4899 * @arg TIM_DMABASE_CR2
4900 * @arg TIM_DMABASE_SMCR
4901 * @arg TIM_DMABASE_DIER
4902 * @arg TIM_DMABASE_SR
4903 * @arg TIM_DMABASE_EGR
4904 * @arg TIM_DMABASE_CCMR1
4905 * @arg TIM_DMABASE_CCMR2
4906 * @arg TIM_DMABASE_CCER
4907 * @arg TIM_DMABASE_CNT
4908 * @arg TIM_DMABASE_PSC
4909 * @arg TIM_DMABASE_ARR
4910 * @arg TIM_DMABASE_RCR
4911 * @arg TIM_DMABASE_CCR1
4912 * @arg TIM_DMABASE_CCR2
4913 * @arg TIM_DMABASE_CCR3
4914 * @arg TIM_DMABASE_CCR4
4915 * @arg TIM_DMABASE_BDTR
4916 * @arg TIM_DMABASE_OR
4917 * @arg TIM_DMABASE_CCMR3 (*)
4918 * @arg TIM_DMABASE_CCR5 (*)
4919 * @arg TIM_DMABASE_CCR6 (*)
4920 * (*) value not defined in all devices
4921 * @param BurstRequestSrc TIM DMA Request sources
4922 * This parameter can be one of the following values:
4923 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4924 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4925 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4926 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4927 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4928 * @arg TIM_DMA_COM: TIM Commutation DMA source
4929 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4930 * @param BurstBuffer The Buffer address.
4931 * @param BurstLength DMA Burst length. This parameter can be one value
4932 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4933 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4934 * @retval HAL status
4935 */
HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)4936 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4937 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
4938 {
4939 HAL_StatusTypeDef status;
4940
4941 status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4942 ((BurstLength) >> 8U) + 1U);
4943
4944
4945 return status;
4946 }
4947
4948 /**
4949 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4950 * @param htim TIM handle
4951 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4952 * This parameter can be one of the following values:
4953 * @arg TIM_DMABASE_CR1
4954 * @arg TIM_DMABASE_CR2
4955 * @arg TIM_DMABASE_SMCR
4956 * @arg TIM_DMABASE_DIER
4957 * @arg TIM_DMABASE_SR
4958 * @arg TIM_DMABASE_EGR
4959 * @arg TIM_DMABASE_CCMR1
4960 * @arg TIM_DMABASE_CCMR2
4961 * @arg TIM_DMABASE_CCER
4962 * @arg TIM_DMABASE_CNT
4963 * @arg TIM_DMABASE_PSC
4964 * @arg TIM_DMABASE_ARR
4965 * @arg TIM_DMABASE_RCR
4966 * @arg TIM_DMABASE_CCR1
4967 * @arg TIM_DMABASE_CCR2
4968 * @arg TIM_DMABASE_CCR3
4969 * @arg TIM_DMABASE_CCR4
4970 * @arg TIM_DMABASE_BDTR
4971 * @arg TIM_DMABASE_OR
4972 * @arg TIM_DMABASE_CCMR3 (*)
4973 * @arg TIM_DMABASE_CCR5 (*)
4974 * @arg TIM_DMABASE_CCR6 (*)
4975 * (*) value not defined in all devices
4976 * @param BurstRequestSrc TIM DMA Request sources
4977 * This parameter can be one of the following values:
4978 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4979 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4980 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4981 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4982 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4983 * @arg TIM_DMA_COM: TIM Commutation DMA source
4984 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4985 * @param BurstBuffer The Buffer address.
4986 * @param BurstLength DMA Burst length. This parameter can be one value
4987 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4988 * @param DataLength Data length. This parameter can be one value
4989 * between 1 and 0xFFFF.
4990 * @retval HAL status
4991 */
HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4992 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4993 uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
4994 uint32_t BurstLength, uint32_t DataLength)
4995 {
4996 HAL_StatusTypeDef status = HAL_OK;
4997
4998 /* Check the parameters */
4999 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
5000 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
5001 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
5002 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
5003 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
5004
5005 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
5006 {
5007 return HAL_BUSY;
5008 }
5009 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
5010 {
5011 if ((BurstBuffer == NULL) && (BurstLength > 0U))
5012 {
5013 return HAL_ERROR;
5014 }
5015 else
5016 {
5017 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
5018 }
5019 }
5020 else
5021 {
5022 /* nothing to do */
5023 }
5024 switch (BurstRequestSrc)
5025 {
5026 case TIM_DMA_UPDATE:
5027 {
5028 /* Set the DMA Period elapsed callbacks */
5029 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
5030 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
5031
5032 /* Set the DMA error callback */
5033 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
5034
5035 /* Enable the DMA channel */
5036 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5037 DataLength) != HAL_OK)
5038 {
5039 /* Return error status */
5040 return HAL_ERROR;
5041 }
5042 break;
5043 }
5044 case TIM_DMA_CC1:
5045 {
5046 /* Set the DMA capture callbacks */
5047 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
5048 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5049
5050 /* Set the DMA error callback */
5051 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
5052
5053 /* Enable the DMA channel */
5054 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5055 DataLength) != HAL_OK)
5056 {
5057 /* Return error status */
5058 return HAL_ERROR;
5059 }
5060 break;
5061 }
5062 case TIM_DMA_CC2:
5063 {
5064 /* Set the DMA capture callbacks */
5065 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
5066 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5067
5068 /* Set the DMA error callback */
5069 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
5070
5071 /* Enable the DMA channel */
5072 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5073 DataLength) != HAL_OK)
5074 {
5075 /* Return error status */
5076 return HAL_ERROR;
5077 }
5078 break;
5079 }
5080 case TIM_DMA_CC3:
5081 {
5082 /* Set the DMA capture callbacks */
5083 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
5084 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5085
5086 /* Set the DMA error callback */
5087 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
5088
5089 /* Enable the DMA channel */
5090 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5091 DataLength) != HAL_OK)
5092 {
5093 /* Return error status */
5094 return HAL_ERROR;
5095 }
5096 break;
5097 }
5098 case TIM_DMA_CC4:
5099 {
5100 /* Set the DMA capture callbacks */
5101 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
5102 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5103
5104 /* Set the DMA error callback */
5105 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
5106
5107 /* Enable the DMA channel */
5108 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5109 DataLength) != HAL_OK)
5110 {
5111 /* Return error status */
5112 return HAL_ERROR;
5113 }
5114 break;
5115 }
5116 case TIM_DMA_COM:
5117 {
5118 /* Set the DMA commutation callbacks */
5119 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
5120 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
5121
5122 /* Set the DMA error callback */
5123 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
5124
5125 /* Enable the DMA channel */
5126 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5127 DataLength) != HAL_OK)
5128 {
5129 /* Return error status */
5130 return HAL_ERROR;
5131 }
5132 break;
5133 }
5134 case TIM_DMA_TRIGGER:
5135 {
5136 /* Set the DMA trigger callbacks */
5137 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
5138 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
5139
5140 /* Set the DMA error callback */
5141 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
5142
5143 /* Enable the DMA channel */
5144 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5145 DataLength) != HAL_OK)
5146 {
5147 /* Return error status */
5148 return HAL_ERROR;
5149 }
5150 break;
5151 }
5152 default:
5153 status = HAL_ERROR;
5154 break;
5155 }
5156
5157 if (status == HAL_OK)
5158 {
5159 /* Configure the DMA Burst Mode */
5160 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
5161
5162 /* Enable the TIM DMA Request */
5163 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
5164 }
5165
5166 /* Return function status */
5167 return status;
5168 }
5169
5170 /**
5171 * @brief Stop the DMA burst reading
5172 * @param htim TIM handle
5173 * @param BurstRequestSrc TIM DMA Request sources to disable.
5174 * @retval HAL status
5175 */
HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)5176 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
5177 {
5178 HAL_StatusTypeDef status = HAL_OK;
5179
5180 /* Check the parameters */
5181 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
5182
5183 /* Abort the DMA transfer (at least disable the DMA channel) */
5184 switch (BurstRequestSrc)
5185 {
5186 case TIM_DMA_UPDATE:
5187 {
5188 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
5189 break;
5190 }
5191 case TIM_DMA_CC1:
5192 {
5193 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
5194 break;
5195 }
5196 case TIM_DMA_CC2:
5197 {
5198 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
5199 break;
5200 }
5201 case TIM_DMA_CC3:
5202 {
5203 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
5204 break;
5205 }
5206 case TIM_DMA_CC4:
5207 {
5208 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
5209 break;
5210 }
5211 case TIM_DMA_COM:
5212 {
5213 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
5214 break;
5215 }
5216 case TIM_DMA_TRIGGER:
5217 {
5218 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
5219 break;
5220 }
5221 default:
5222 status = HAL_ERROR;
5223 break;
5224 }
5225
5226 if (status == HAL_OK)
5227 {
5228 /* Disable the TIM Update DMA request */
5229 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
5230
5231 /* Change the DMA burst operation state */
5232 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
5233 }
5234
5235 /* Return function status */
5236 return status;
5237 }
5238
5239 /**
5240 * @brief Generate a software event
5241 * @param htim TIM handle
5242 * @param EventSource specifies the event source.
5243 * This parameter can be one of the following values:
5244 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
5245 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
5246 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
5247 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
5248 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
5249 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
5250 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
5251 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
5252 * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
5253 * @note Basic timers can only generate an update event.
5254 * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
5255 * @note TIM_EVENTSOURCE_BREAK are relevant only for timer instances
5256 * supporting a break input.
5257 * @retval HAL status
5258 */
5259
HAL_TIM_GenerateEvent(TIM_HandleTypeDef * htim,uint32_t EventSource)5260 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
5261 {
5262 /* Check the parameters */
5263 assert_param(IS_TIM_INSTANCE(htim->Instance));
5264 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
5265
5266 /* Process Locked */
5267 __HAL_LOCK(htim);
5268
5269 /* Change the TIM state */
5270 htim->State = HAL_TIM_STATE_BUSY;
5271
5272 /* Set the event sources */
5273 htim->Instance->EGR = EventSource;
5274
5275 /* Change the TIM state */
5276 htim->State = HAL_TIM_STATE_READY;
5277
5278 __HAL_UNLOCK(htim);
5279
5280 /* Return function status */
5281 return HAL_OK;
5282 }
5283
5284 /**
5285 * @brief Configures the OCRef clear feature
5286 * @param htim TIM handle
5287 * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
5288 * contains the OCREF clear feature and parameters for the TIM peripheral.
5289 * @param Channel specifies the TIM Channel
5290 * This parameter can be one of the following values:
5291 * @arg TIM_CHANNEL_1: TIM Channel 1
5292 * @arg TIM_CHANNEL_2: TIM Channel 2
5293 * @arg TIM_CHANNEL_3: TIM Channel 3
5294 * @arg TIM_CHANNEL_4: TIM Channel 4
5295 * @arg TIM_CHANNEL_5: TIM Channel 5 (*)
5296 * @arg TIM_CHANNEL_6: TIM Channel 6 (*)
5297 * (*) Value not defined for all devices
5298 * @retval HAL status
5299 */
HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef * htim,const TIM_ClearInputConfigTypeDef * sClearInputConfig,uint32_t Channel)5300 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
5301 const TIM_ClearInputConfigTypeDef *sClearInputConfig,
5302 uint32_t Channel)
5303 {
5304 HAL_StatusTypeDef status = HAL_OK;
5305
5306 /* Check the parameters */
5307 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
5308 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
5309
5310 /* Process Locked */
5311 __HAL_LOCK(htim);
5312
5313 htim->State = HAL_TIM_STATE_BUSY;
5314
5315 switch (sClearInputConfig->ClearInputSource)
5316 {
5317 case TIM_CLEARINPUTSOURCE_NONE:
5318 {
5319 /* Clear the OCREF clear selection bit and the the ETR Bits */
5320 #if defined(TIM_SMCR_OCCS)
5321 CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
5322 #else
5323 CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
5324 #endif /* TIM_SMCR_OCCS */
5325 break;
5326 }
5327 #if defined(TIM_SMCR_OCCS)
5328 case TIM_CLEARINPUTSOURCE_OCREFCLR:
5329 {
5330 /* Clear the OCREF clear selection bit */
5331 CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
5332 break;
5333 }
5334 #endif /* TIM_SMCR_OCCS */
5335
5336 case TIM_CLEARINPUTSOURCE_ETR:
5337 {
5338 /* Check the parameters */
5339 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
5340 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
5341 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
5342
5343 /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
5344 if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
5345 {
5346 htim->State = HAL_TIM_STATE_READY;
5347 __HAL_UNLOCK(htim);
5348 return HAL_ERROR;
5349 }
5350
5351 TIM_ETR_SetConfig(htim->Instance,
5352 sClearInputConfig->ClearInputPrescaler,
5353 sClearInputConfig->ClearInputPolarity,
5354 sClearInputConfig->ClearInputFilter);
5355 #if defined(TIM_SMCR_OCCS)
5356
5357 /* Set the OCREF clear selection bit */
5358 SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
5359 #endif /* TIM_SMCR_OCCS */
5360 break;
5361 }
5362
5363 default:
5364 status = HAL_ERROR;
5365 break;
5366 }
5367
5368 if (status == HAL_OK)
5369 {
5370 switch (Channel)
5371 {
5372 case TIM_CHANNEL_1:
5373 {
5374 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5375 {
5376 /* Enable the OCREF clear feature for Channel 1 */
5377 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5378 }
5379 else
5380 {
5381 /* Disable the OCREF clear feature for Channel 1 */
5382 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5383 }
5384 break;
5385 }
5386 case TIM_CHANNEL_2:
5387 {
5388 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5389 {
5390 /* Enable the OCREF clear feature for Channel 2 */
5391 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5392 }
5393 else
5394 {
5395 /* Disable the OCREF clear feature for Channel 2 */
5396 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5397 }
5398 break;
5399 }
5400 case TIM_CHANNEL_3:
5401 {
5402 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5403 {
5404 /* Enable the OCREF clear feature for Channel 3 */
5405 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5406 }
5407 else
5408 {
5409 /* Disable the OCREF clear feature for Channel 3 */
5410 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5411 }
5412 break;
5413 }
5414 case TIM_CHANNEL_4:
5415 {
5416 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5417 {
5418 /* Enable the OCREF clear feature for Channel 4 */
5419 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5420 }
5421 else
5422 {
5423 /* Disable the OCREF clear feature for Channel 4 */
5424 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5425 }
5426 break;
5427 }
5428 #if defined(TIM_CCER_CC5E)
5429 case TIM_CHANNEL_5:
5430 {
5431 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5432 {
5433 /* Enable the OCREF clear feature for Channel 5 */
5434 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
5435 }
5436 else
5437 {
5438 /* Disable the OCREF clear feature for Channel 5 */
5439 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
5440 }
5441 break;
5442 }
5443 #endif /* TIM_CCER_CC5E */
5444 #if defined(TIM_CCER_CC6E)
5445 case TIM_CHANNEL_6:
5446 {
5447 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5448 {
5449 /* Enable the OCREF clear feature for Channel 6 */
5450 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
5451 }
5452 else
5453 {
5454 /* Disable the OCREF clear feature for Channel 6 */
5455 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
5456 }
5457 break;
5458 }
5459 #endif /* TIM_CCER_CC6E */
5460 default:
5461 break;
5462 }
5463 }
5464
5465 htim->State = HAL_TIM_STATE_READY;
5466
5467 __HAL_UNLOCK(htim);
5468
5469 return status;
5470 }
5471
5472 /**
5473 * @brief Configures the clock source to be used
5474 * @param htim TIM handle
5475 * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
5476 * contains the clock source information for the TIM peripheral.
5477 * @retval HAL status
5478 */
HAL_TIM_ConfigClockSource(TIM_HandleTypeDef * htim,const TIM_ClockConfigTypeDef * sClockSourceConfig)5479 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
5480 {
5481 HAL_StatusTypeDef status = HAL_OK;
5482 uint32_t tmpsmcr;
5483
5484 /* Process Locked */
5485 __HAL_LOCK(htim);
5486
5487 htim->State = HAL_TIM_STATE_BUSY;
5488
5489 /* Check the parameters */
5490 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
5491
5492 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
5493 tmpsmcr = htim->Instance->SMCR;
5494 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
5495 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
5496 htim->Instance->SMCR = tmpsmcr;
5497
5498 switch (sClockSourceConfig->ClockSource)
5499 {
5500 case TIM_CLOCKSOURCE_INTERNAL:
5501 {
5502 assert_param(IS_TIM_INSTANCE(htim->Instance));
5503 break;
5504 }
5505
5506 case TIM_CLOCKSOURCE_ETRMODE1:
5507 {
5508 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
5509 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
5510
5511 /* Check ETR input conditioning related parameters */
5512 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5513 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5514 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5515
5516 /* Configure the ETR Clock source */
5517 TIM_ETR_SetConfig(htim->Instance,
5518 sClockSourceConfig->ClockPrescaler,
5519 sClockSourceConfig->ClockPolarity,
5520 sClockSourceConfig->ClockFilter);
5521
5522 /* Select the External clock mode1 and the ETRF trigger */
5523 tmpsmcr = htim->Instance->SMCR;
5524 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
5525 /* Write to TIMx SMCR */
5526 htim->Instance->SMCR = tmpsmcr;
5527 break;
5528 }
5529
5530 case TIM_CLOCKSOURCE_ETRMODE2:
5531 {
5532 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
5533 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
5534
5535 /* Check ETR input conditioning related parameters */
5536 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5537 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5538 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5539
5540 /* Configure the ETR Clock source */
5541 TIM_ETR_SetConfig(htim->Instance,
5542 sClockSourceConfig->ClockPrescaler,
5543 sClockSourceConfig->ClockPolarity,
5544 sClockSourceConfig->ClockFilter);
5545 /* Enable the External clock mode2 */
5546 htim->Instance->SMCR |= TIM_SMCR_ECE;
5547 break;
5548 }
5549
5550 case TIM_CLOCKSOURCE_TI1:
5551 {
5552 /* Check whether or not the timer instance supports external clock mode 1 */
5553 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5554
5555 /* Check TI1 input conditioning related parameters */
5556 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5557 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5558
5559 TIM_TI1_ConfigInputStage(htim->Instance,
5560 sClockSourceConfig->ClockPolarity,
5561 sClockSourceConfig->ClockFilter);
5562 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
5563 break;
5564 }
5565
5566 case TIM_CLOCKSOURCE_TI2:
5567 {
5568 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
5569 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5570
5571 /* Check TI2 input conditioning related parameters */
5572 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5573 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5574
5575 TIM_TI2_ConfigInputStage(htim->Instance,
5576 sClockSourceConfig->ClockPolarity,
5577 sClockSourceConfig->ClockFilter);
5578 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
5579 break;
5580 }
5581
5582 case TIM_CLOCKSOURCE_TI1ED:
5583 {
5584 /* Check whether or not the timer instance supports external clock mode 1 */
5585 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5586
5587 /* Check TI1 input conditioning related parameters */
5588 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5589 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5590
5591 TIM_TI1_ConfigInputStage(htim->Instance,
5592 sClockSourceConfig->ClockPolarity,
5593 sClockSourceConfig->ClockFilter);
5594 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
5595 break;
5596 }
5597
5598 case TIM_CLOCKSOURCE_ITR0:
5599 case TIM_CLOCKSOURCE_ITR1:
5600 case TIM_CLOCKSOURCE_ITR2:
5601 case TIM_CLOCKSOURCE_ITR3:
5602 {
5603 /* Check whether or not the timer instance supports internal trigger input */
5604 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
5605
5606 TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
5607 break;
5608 }
5609
5610 default:
5611 status = HAL_ERROR;
5612 break;
5613 }
5614 htim->State = HAL_TIM_STATE_READY;
5615
5616 __HAL_UNLOCK(htim);
5617
5618 return status;
5619 }
5620
5621 /**
5622 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
5623 * or a XOR combination between CH1_input, CH2_input & CH3_input
5624 * @param htim TIM handle.
5625 * @param TI1_Selection Indicate whether or not channel 1 is connected to the
5626 * output of a XOR gate.
5627 * This parameter can be one of the following values:
5628 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
5629 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
5630 * pins are connected to the TI1 input (XOR combination)
5631 * @retval HAL status
5632 */
HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef * htim,uint32_t TI1_Selection)5633 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
5634 {
5635 uint32_t tmpcr2;
5636
5637 /* Check the parameters */
5638 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
5639 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
5640
5641 /* Get the TIMx CR2 register value */
5642 tmpcr2 = htim->Instance->CR2;
5643
5644 /* Reset the TI1 selection */
5645 tmpcr2 &= ~TIM_CR2_TI1S;
5646
5647 /* Set the TI1 selection */
5648 tmpcr2 |= TI1_Selection;
5649
5650 /* Write to TIMxCR2 */
5651 htim->Instance->CR2 = tmpcr2;
5652
5653 return HAL_OK;
5654 }
5655
5656 /**
5657 * @brief Configures the TIM in Slave mode
5658 * @param htim TIM handle.
5659 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5660 * contains the selected trigger (internal trigger input, filtered
5661 * timer input or external trigger input) and the Slave mode
5662 * (Disable, Reset, Gated, Trigger, External clock mode 1).
5663 * @retval HAL status
5664 */
HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)5665 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
5666 {
5667 /* Check the parameters */
5668 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5669 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5670 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
5671
5672 __HAL_LOCK(htim);
5673
5674 htim->State = HAL_TIM_STATE_BUSY;
5675
5676 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5677 {
5678 htim->State = HAL_TIM_STATE_READY;
5679 __HAL_UNLOCK(htim);
5680 return HAL_ERROR;
5681 }
5682
5683 /* Disable Trigger Interrupt */
5684 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
5685
5686 /* Disable Trigger DMA request */
5687 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5688
5689 htim->State = HAL_TIM_STATE_READY;
5690
5691 __HAL_UNLOCK(htim);
5692
5693 return HAL_OK;
5694 }
5695
5696 /**
5697 * @brief Configures the TIM in Slave mode in interrupt mode
5698 * @param htim TIM handle.
5699 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5700 * contains the selected trigger (internal trigger input, filtered
5701 * timer input or external trigger input) and the Slave mode
5702 * (Disable, Reset, Gated, Trigger, External clock mode 1).
5703 * @retval HAL status
5704 */
HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)5705 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
5706 const TIM_SlaveConfigTypeDef *sSlaveConfig)
5707 {
5708 /* Check the parameters */
5709 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5710 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5711 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
5712
5713 __HAL_LOCK(htim);
5714
5715 htim->State = HAL_TIM_STATE_BUSY;
5716
5717 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5718 {
5719 htim->State = HAL_TIM_STATE_READY;
5720 __HAL_UNLOCK(htim);
5721 return HAL_ERROR;
5722 }
5723
5724 /* Enable Trigger Interrupt */
5725 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
5726
5727 /* Disable Trigger DMA request */
5728 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5729
5730 htim->State = HAL_TIM_STATE_READY;
5731
5732 __HAL_UNLOCK(htim);
5733
5734 return HAL_OK;
5735 }
5736
5737 /**
5738 * @brief Read the captured value from Capture Compare unit
5739 * @param htim TIM handle.
5740 * @param Channel TIM Channels to be enabled
5741 * This parameter can be one of the following values:
5742 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
5743 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
5744 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
5745 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
5746 * @retval Captured value
5747 */
HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef * htim,uint32_t Channel)5748 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)
5749 {
5750 uint32_t tmpreg = 0U;
5751
5752 switch (Channel)
5753 {
5754 case TIM_CHANNEL_1:
5755 {
5756 /* Check the parameters */
5757 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
5758
5759 /* Return the capture 1 value */
5760 tmpreg = htim->Instance->CCR1;
5761
5762 break;
5763 }
5764 case TIM_CHANNEL_2:
5765 {
5766 /* Check the parameters */
5767 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
5768
5769 /* Return the capture 2 value */
5770 tmpreg = htim->Instance->CCR2;
5771
5772 break;
5773 }
5774
5775 case TIM_CHANNEL_3:
5776 {
5777 /* Check the parameters */
5778 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
5779
5780 /* Return the capture 3 value */
5781 tmpreg = htim->Instance->CCR3;
5782
5783 break;
5784 }
5785
5786 case TIM_CHANNEL_4:
5787 {
5788 /* Check the parameters */
5789 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
5790
5791 /* Return the capture 4 value */
5792 tmpreg = htim->Instance->CCR4;
5793
5794 break;
5795 }
5796
5797 default:
5798 break;
5799 }
5800
5801 return tmpreg;
5802 }
5803
5804 /**
5805 * @}
5806 */
5807
5808 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
5809 * @brief TIM Callbacks functions
5810 *
5811 @verbatim
5812 ==============================================================================
5813 ##### TIM Callbacks functions #####
5814 ==============================================================================
5815 [..]
5816 This section provides TIM callback functions:
5817 (+) TIM Period elapsed callback
5818 (+) TIM Output Compare callback
5819 (+) TIM Input capture callback
5820 (+) TIM Trigger callback
5821 (+) TIM Error callback
5822
5823 @endverbatim
5824 * @{
5825 */
5826
5827 /**
5828 * @brief Period elapsed callback in non-blocking mode
5829 * @param htim TIM handle
5830 * @retval None
5831 */
HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef * htim)5832 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
5833 {
5834 /* Prevent unused argument(s) compilation warning */
5835 UNUSED(htim);
5836
5837 /* NOTE : This function should not be modified, when the callback is needed,
5838 the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
5839 */
5840 }
5841
5842 /**
5843 * @brief Period elapsed half complete callback in non-blocking mode
5844 * @param htim TIM handle
5845 * @retval None
5846 */
HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef * htim)5847 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
5848 {
5849 /* Prevent unused argument(s) compilation warning */
5850 UNUSED(htim);
5851
5852 /* NOTE : This function should not be modified, when the callback is needed,
5853 the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
5854 */
5855 }
5856
5857 /**
5858 * @brief Output Compare callback in non-blocking mode
5859 * @param htim TIM OC handle
5860 * @retval None
5861 */
HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef * htim)5862 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
5863 {
5864 /* Prevent unused argument(s) compilation warning */
5865 UNUSED(htim);
5866
5867 /* NOTE : This function should not be modified, when the callback is needed,
5868 the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
5869 */
5870 }
5871
5872 /**
5873 * @brief Input Capture callback in non-blocking mode
5874 * @param htim TIM IC handle
5875 * @retval None
5876 */
HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef * htim)5877 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
5878 {
5879 /* Prevent unused argument(s) compilation warning */
5880 UNUSED(htim);
5881
5882 /* NOTE : This function should not be modified, when the callback is needed,
5883 the HAL_TIM_IC_CaptureCallback could be implemented in the user file
5884 */
5885 }
5886
5887 /**
5888 * @brief Input Capture half complete callback in non-blocking mode
5889 * @param htim TIM IC handle
5890 * @retval None
5891 */
HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef * htim)5892 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
5893 {
5894 /* Prevent unused argument(s) compilation warning */
5895 UNUSED(htim);
5896
5897 /* NOTE : This function should not be modified, when the callback is needed,
5898 the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
5899 */
5900 }
5901
5902 /**
5903 * @brief PWM Pulse finished callback in non-blocking mode
5904 * @param htim TIM handle
5905 * @retval None
5906 */
HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef * htim)5907 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
5908 {
5909 /* Prevent unused argument(s) compilation warning */
5910 UNUSED(htim);
5911
5912 /* NOTE : This function should not be modified, when the callback is needed,
5913 the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
5914 */
5915 }
5916
5917 /**
5918 * @brief PWM Pulse finished half complete callback in non-blocking mode
5919 * @param htim TIM handle
5920 * @retval None
5921 */
HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef * htim)5922 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
5923 {
5924 /* Prevent unused argument(s) compilation warning */
5925 UNUSED(htim);
5926
5927 /* NOTE : This function should not be modified, when the callback is needed,
5928 the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
5929 */
5930 }
5931
5932 /**
5933 * @brief Hall Trigger detection callback in non-blocking mode
5934 * @param htim TIM handle
5935 * @retval None
5936 */
HAL_TIM_TriggerCallback(TIM_HandleTypeDef * htim)5937 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
5938 {
5939 /* Prevent unused argument(s) compilation warning */
5940 UNUSED(htim);
5941
5942 /* NOTE : This function should not be modified, when the callback is needed,
5943 the HAL_TIM_TriggerCallback could be implemented in the user file
5944 */
5945 }
5946
5947 /**
5948 * @brief Hall Trigger detection half complete callback in non-blocking mode
5949 * @param htim TIM handle
5950 * @retval None
5951 */
HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef * htim)5952 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
5953 {
5954 /* Prevent unused argument(s) compilation warning */
5955 UNUSED(htim);
5956
5957 /* NOTE : This function should not be modified, when the callback is needed,
5958 the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
5959 */
5960 }
5961
5962 /**
5963 * @brief Timer error callback in non-blocking mode
5964 * @param htim TIM handle
5965 * @retval None
5966 */
HAL_TIM_ErrorCallback(TIM_HandleTypeDef * htim)5967 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
5968 {
5969 /* Prevent unused argument(s) compilation warning */
5970 UNUSED(htim);
5971
5972 /* NOTE : This function should not be modified, when the callback is needed,
5973 the HAL_TIM_ErrorCallback could be implemented in the user file
5974 */
5975 }
5976
5977 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5978 /**
5979 * @brief Register a User TIM callback to be used instead of the weak predefined callback
5980 * @param htim tim handle
5981 * @param CallbackID ID of the callback to be registered
5982 * This parameter can be one of the following values:
5983 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
5984 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
5985 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
5986 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
5987 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
5988 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
5989 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
5990 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
5991 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
5992 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
5993 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
5994 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
5995 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
5996 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
5997 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
5998 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
5999 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
6000 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
6001 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
6002 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
6003 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
6004 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
6005 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
6006 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
6007 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
6008 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
6009 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
6010 #if defined(TIM_BDTR_BK2E)
6011 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
6012 #endif
6013 * @param pCallback pointer to the callback function
6014 * @retval status
6015 */
HAL_TIM_RegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID,pTIM_CallbackTypeDef pCallback)6016 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
6017 pTIM_CallbackTypeDef pCallback)
6018 {
6019 HAL_StatusTypeDef status = HAL_OK;
6020
6021 if (pCallback == NULL)
6022 {
6023 return HAL_ERROR;
6024 }
6025
6026 if (htim->State == HAL_TIM_STATE_READY)
6027 {
6028 switch (CallbackID)
6029 {
6030 case HAL_TIM_BASE_MSPINIT_CB_ID :
6031 htim->Base_MspInitCallback = pCallback;
6032 break;
6033
6034 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6035 htim->Base_MspDeInitCallback = pCallback;
6036 break;
6037
6038 case HAL_TIM_IC_MSPINIT_CB_ID :
6039 htim->IC_MspInitCallback = pCallback;
6040 break;
6041
6042 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6043 htim->IC_MspDeInitCallback = pCallback;
6044 break;
6045
6046 case HAL_TIM_OC_MSPINIT_CB_ID :
6047 htim->OC_MspInitCallback = pCallback;
6048 break;
6049
6050 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6051 htim->OC_MspDeInitCallback = pCallback;
6052 break;
6053
6054 case HAL_TIM_PWM_MSPINIT_CB_ID :
6055 htim->PWM_MspInitCallback = pCallback;
6056 break;
6057
6058 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6059 htim->PWM_MspDeInitCallback = pCallback;
6060 break;
6061
6062 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6063 htim->OnePulse_MspInitCallback = pCallback;
6064 break;
6065
6066 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6067 htim->OnePulse_MspDeInitCallback = pCallback;
6068 break;
6069
6070 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6071 htim->Encoder_MspInitCallback = pCallback;
6072 break;
6073
6074 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6075 htim->Encoder_MspDeInitCallback = pCallback;
6076 break;
6077
6078 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6079 htim->HallSensor_MspInitCallback = pCallback;
6080 break;
6081
6082 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6083 htim->HallSensor_MspDeInitCallback = pCallback;
6084 break;
6085
6086 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
6087 htim->PeriodElapsedCallback = pCallback;
6088 break;
6089
6090 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
6091 htim->PeriodElapsedHalfCpltCallback = pCallback;
6092 break;
6093
6094 case HAL_TIM_TRIGGER_CB_ID :
6095 htim->TriggerCallback = pCallback;
6096 break;
6097
6098 case HAL_TIM_TRIGGER_HALF_CB_ID :
6099 htim->TriggerHalfCpltCallback = pCallback;
6100 break;
6101
6102 case HAL_TIM_IC_CAPTURE_CB_ID :
6103 htim->IC_CaptureCallback = pCallback;
6104 break;
6105
6106 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
6107 htim->IC_CaptureHalfCpltCallback = pCallback;
6108 break;
6109
6110 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
6111 htim->OC_DelayElapsedCallback = pCallback;
6112 break;
6113
6114 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
6115 htim->PWM_PulseFinishedCallback = pCallback;
6116 break;
6117
6118 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
6119 htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
6120 break;
6121
6122 case HAL_TIM_ERROR_CB_ID :
6123 htim->ErrorCallback = pCallback;
6124 break;
6125
6126 case HAL_TIM_COMMUTATION_CB_ID :
6127 htim->CommutationCallback = pCallback;
6128 break;
6129
6130 case HAL_TIM_COMMUTATION_HALF_CB_ID :
6131 htim->CommutationHalfCpltCallback = pCallback;
6132 break;
6133
6134 case HAL_TIM_BREAK_CB_ID :
6135 htim->BreakCallback = pCallback;
6136 break;
6137 #if defined(TIM_BDTR_BK2E)
6138
6139 case HAL_TIM_BREAK2_CB_ID :
6140 htim->Break2Callback = pCallback;
6141 break;
6142 #endif /* TIM_BDTR_BK2E */
6143
6144 default :
6145 /* Return error status */
6146 status = HAL_ERROR;
6147 break;
6148 }
6149 }
6150 else if (htim->State == HAL_TIM_STATE_RESET)
6151 {
6152 switch (CallbackID)
6153 {
6154 case HAL_TIM_BASE_MSPINIT_CB_ID :
6155 htim->Base_MspInitCallback = pCallback;
6156 break;
6157
6158 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6159 htim->Base_MspDeInitCallback = pCallback;
6160 break;
6161
6162 case HAL_TIM_IC_MSPINIT_CB_ID :
6163 htim->IC_MspInitCallback = pCallback;
6164 break;
6165
6166 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6167 htim->IC_MspDeInitCallback = pCallback;
6168 break;
6169
6170 case HAL_TIM_OC_MSPINIT_CB_ID :
6171 htim->OC_MspInitCallback = pCallback;
6172 break;
6173
6174 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6175 htim->OC_MspDeInitCallback = pCallback;
6176 break;
6177
6178 case HAL_TIM_PWM_MSPINIT_CB_ID :
6179 htim->PWM_MspInitCallback = pCallback;
6180 break;
6181
6182 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6183 htim->PWM_MspDeInitCallback = pCallback;
6184 break;
6185
6186 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6187 htim->OnePulse_MspInitCallback = pCallback;
6188 break;
6189
6190 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6191 htim->OnePulse_MspDeInitCallback = pCallback;
6192 break;
6193
6194 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6195 htim->Encoder_MspInitCallback = pCallback;
6196 break;
6197
6198 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6199 htim->Encoder_MspDeInitCallback = pCallback;
6200 break;
6201
6202 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6203 htim->HallSensor_MspInitCallback = pCallback;
6204 break;
6205
6206 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6207 htim->HallSensor_MspDeInitCallback = pCallback;
6208 break;
6209
6210 default :
6211 /* Return error status */
6212 status = HAL_ERROR;
6213 break;
6214 }
6215 }
6216 else
6217 {
6218 /* Return error status */
6219 status = HAL_ERROR;
6220 }
6221
6222 return status;
6223 }
6224
6225 /**
6226 * @brief Unregister a TIM callback
6227 * TIM callback is redirected to the weak predefined callback
6228 * @param htim tim handle
6229 * @param CallbackID ID of the callback to be unregistered
6230 * This parameter can be one of the following values:
6231 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
6232 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
6233 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
6234 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
6235 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
6236 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
6237 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
6238 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
6239 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
6240 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
6241 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
6242 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
6243 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
6244 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
6245 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
6246 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
6247 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
6248 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
6249 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
6250 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
6251 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
6252 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
6253 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
6254 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
6255 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
6256 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
6257 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
6258 #if defined(TIM_BDTR_BK2E)
6259 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
6260 #endif
6261 * @retval status
6262 */
HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID)6263 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
6264 {
6265 HAL_StatusTypeDef status = HAL_OK;
6266
6267 if (htim->State == HAL_TIM_STATE_READY)
6268 {
6269 switch (CallbackID)
6270 {
6271 case HAL_TIM_BASE_MSPINIT_CB_ID :
6272 /* Legacy weak Base MspInit Callback */
6273 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
6274 break;
6275
6276 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6277 /* Legacy weak Base Msp DeInit Callback */
6278 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
6279 break;
6280
6281 case HAL_TIM_IC_MSPINIT_CB_ID :
6282 /* Legacy weak IC Msp Init Callback */
6283 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
6284 break;
6285
6286 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6287 /* Legacy weak IC Msp DeInit Callback */
6288 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
6289 break;
6290
6291 case HAL_TIM_OC_MSPINIT_CB_ID :
6292 /* Legacy weak OC Msp Init Callback */
6293 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
6294 break;
6295
6296 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6297 /* Legacy weak OC Msp DeInit Callback */
6298 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
6299 break;
6300
6301 case HAL_TIM_PWM_MSPINIT_CB_ID :
6302 /* Legacy weak PWM Msp Init Callback */
6303 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
6304 break;
6305
6306 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6307 /* Legacy weak PWM Msp DeInit Callback */
6308 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
6309 break;
6310
6311 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6312 /* Legacy weak One Pulse Msp Init Callback */
6313 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
6314 break;
6315
6316 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6317 /* Legacy weak One Pulse Msp DeInit Callback */
6318 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
6319 break;
6320
6321 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6322 /* Legacy weak Encoder Msp Init Callback */
6323 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
6324 break;
6325
6326 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6327 /* Legacy weak Encoder Msp DeInit Callback */
6328 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
6329 break;
6330
6331 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6332 /* Legacy weak Hall Sensor Msp Init Callback */
6333 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
6334 break;
6335
6336 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6337 /* Legacy weak Hall Sensor Msp DeInit Callback */
6338 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
6339 break;
6340
6341 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
6342 /* Legacy weak Period Elapsed Callback */
6343 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
6344 break;
6345
6346 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
6347 /* Legacy weak Period Elapsed half complete Callback */
6348 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
6349 break;
6350
6351 case HAL_TIM_TRIGGER_CB_ID :
6352 /* Legacy weak Trigger Callback */
6353 htim->TriggerCallback = HAL_TIM_TriggerCallback;
6354 break;
6355
6356 case HAL_TIM_TRIGGER_HALF_CB_ID :
6357 /* Legacy weak Trigger half complete Callback */
6358 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
6359 break;
6360
6361 case HAL_TIM_IC_CAPTURE_CB_ID :
6362 /* Legacy weak IC Capture Callback */
6363 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
6364 break;
6365
6366 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
6367 /* Legacy weak IC Capture half complete Callback */
6368 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
6369 break;
6370
6371 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
6372 /* Legacy weak OC Delay Elapsed Callback */
6373 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
6374 break;
6375
6376 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
6377 /* Legacy weak PWM Pulse Finished Callback */
6378 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
6379 break;
6380
6381 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
6382 /* Legacy weak PWM Pulse Finished half complete Callback */
6383 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
6384 break;
6385
6386 case HAL_TIM_ERROR_CB_ID :
6387 /* Legacy weak Error Callback */
6388 htim->ErrorCallback = HAL_TIM_ErrorCallback;
6389 break;
6390
6391 case HAL_TIM_COMMUTATION_CB_ID :
6392 /* Legacy weak Commutation Callback */
6393 htim->CommutationCallback = HAL_TIMEx_CommutCallback;
6394 break;
6395
6396 case HAL_TIM_COMMUTATION_HALF_CB_ID :
6397 /* Legacy weak Commutation half complete Callback */
6398 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
6399 break;
6400
6401 case HAL_TIM_BREAK_CB_ID :
6402 /* Legacy weak Break Callback */
6403 htim->BreakCallback = HAL_TIMEx_BreakCallback;
6404 break;
6405 #if defined(TIM_BDTR_BK2E)
6406
6407 case HAL_TIM_BREAK2_CB_ID :
6408 /* Legacy weak Break2 Callback */
6409 htim->Break2Callback = HAL_TIMEx_Break2Callback;
6410 break;
6411 #endif /* TIM_BDTR_BK2E */
6412
6413 default :
6414 /* Return error status */
6415 status = HAL_ERROR;
6416 break;
6417 }
6418 }
6419 else if (htim->State == HAL_TIM_STATE_RESET)
6420 {
6421 switch (CallbackID)
6422 {
6423 case HAL_TIM_BASE_MSPINIT_CB_ID :
6424 /* Legacy weak Base MspInit Callback */
6425 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
6426 break;
6427
6428 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6429 /* Legacy weak Base Msp DeInit Callback */
6430 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
6431 break;
6432
6433 case HAL_TIM_IC_MSPINIT_CB_ID :
6434 /* Legacy weak IC Msp Init Callback */
6435 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
6436 break;
6437
6438 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6439 /* Legacy weak IC Msp DeInit Callback */
6440 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
6441 break;
6442
6443 case HAL_TIM_OC_MSPINIT_CB_ID :
6444 /* Legacy weak OC Msp Init Callback */
6445 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
6446 break;
6447
6448 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6449 /* Legacy weak OC Msp DeInit Callback */
6450 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
6451 break;
6452
6453 case HAL_TIM_PWM_MSPINIT_CB_ID :
6454 /* Legacy weak PWM Msp Init Callback */
6455 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
6456 break;
6457
6458 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6459 /* Legacy weak PWM Msp DeInit Callback */
6460 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
6461 break;
6462
6463 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6464 /* Legacy weak One Pulse Msp Init Callback */
6465 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
6466 break;
6467
6468 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6469 /* Legacy weak One Pulse Msp DeInit Callback */
6470 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
6471 break;
6472
6473 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6474 /* Legacy weak Encoder Msp Init Callback */
6475 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
6476 break;
6477
6478 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6479 /* Legacy weak Encoder Msp DeInit Callback */
6480 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
6481 break;
6482
6483 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6484 /* Legacy weak Hall Sensor Msp Init Callback */
6485 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
6486 break;
6487
6488 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6489 /* Legacy weak Hall Sensor Msp DeInit Callback */
6490 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
6491 break;
6492
6493 default :
6494 /* Return error status */
6495 status = HAL_ERROR;
6496 break;
6497 }
6498 }
6499 else
6500 {
6501 /* Return error status */
6502 status = HAL_ERROR;
6503 }
6504
6505 return status;
6506 }
6507 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6508
6509 /**
6510 * @}
6511 */
6512
6513 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
6514 * @brief TIM Peripheral State functions
6515 *
6516 @verbatim
6517 ==============================================================================
6518 ##### Peripheral State functions #####
6519 ==============================================================================
6520 [..]
6521 This subsection permits to get in run-time the status of the peripheral
6522 and the data flow.
6523
6524 @endverbatim
6525 * @{
6526 */
6527
6528 /**
6529 * @brief Return the TIM Base handle state.
6530 * @param htim TIM Base handle
6531 * @retval HAL state
6532 */
HAL_TIM_Base_GetState(const TIM_HandleTypeDef * htim)6533 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim)
6534 {
6535 return htim->State;
6536 }
6537
6538 /**
6539 * @brief Return the TIM OC handle state.
6540 * @param htim TIM Output Compare handle
6541 * @retval HAL state
6542 */
HAL_TIM_OC_GetState(const TIM_HandleTypeDef * htim)6543 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim)
6544 {
6545 return htim->State;
6546 }
6547
6548 /**
6549 * @brief Return the TIM PWM handle state.
6550 * @param htim TIM handle
6551 * @retval HAL state
6552 */
HAL_TIM_PWM_GetState(const TIM_HandleTypeDef * htim)6553 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim)
6554 {
6555 return htim->State;
6556 }
6557
6558 /**
6559 * @brief Return the TIM Input Capture handle state.
6560 * @param htim TIM IC handle
6561 * @retval HAL state
6562 */
HAL_TIM_IC_GetState(const TIM_HandleTypeDef * htim)6563 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim)
6564 {
6565 return htim->State;
6566 }
6567
6568 /**
6569 * @brief Return the TIM One Pulse Mode handle state.
6570 * @param htim TIM OPM handle
6571 * @retval HAL state
6572 */
HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef * htim)6573 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim)
6574 {
6575 return htim->State;
6576 }
6577
6578 /**
6579 * @brief Return the TIM Encoder Mode handle state.
6580 * @param htim TIM Encoder Interface handle
6581 * @retval HAL state
6582 */
HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef * htim)6583 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim)
6584 {
6585 return htim->State;
6586 }
6587
6588 /**
6589 * @brief Return the TIM Encoder Mode handle state.
6590 * @param htim TIM handle
6591 * @retval Active channel
6592 */
HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef * htim)6593 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim)
6594 {
6595 return htim->Channel;
6596 }
6597
6598 /**
6599 * @brief Return actual state of the TIM channel.
6600 * @param htim TIM handle
6601 * @param Channel TIM Channel
6602 * This parameter can be one of the following values:
6603 * @arg TIM_CHANNEL_1: TIM Channel 1
6604 * @arg TIM_CHANNEL_2: TIM Channel 2
6605 * @arg TIM_CHANNEL_3: TIM Channel 3
6606 * @arg TIM_CHANNEL_4: TIM Channel 4
6607 * @arg TIM_CHANNEL_5: TIM Channel 5
6608 * @arg TIM_CHANNEL_6: TIM Channel 6
6609 * @retval TIM Channel state
6610 */
HAL_TIM_GetChannelState(const TIM_HandleTypeDef * htim,uint32_t Channel)6611 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel)
6612 {
6613 HAL_TIM_ChannelStateTypeDef channel_state;
6614
6615 /* Check the parameters */
6616 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
6617
6618 channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
6619
6620 return channel_state;
6621 }
6622
6623 /**
6624 * @brief Return actual state of a DMA burst operation.
6625 * @param htim TIM handle
6626 * @retval DMA burst state
6627 */
HAL_TIM_DMABurstState(const TIM_HandleTypeDef * htim)6628 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim)
6629 {
6630 /* Check the parameters */
6631 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
6632
6633 return htim->DMABurstState;
6634 }
6635
6636 /**
6637 * @}
6638 */
6639
6640 /**
6641 * @}
6642 */
6643
6644 /** @defgroup TIM_Private_Functions TIM Private Functions
6645 * @{
6646 */
6647
6648 /**
6649 * @brief TIM DMA error callback
6650 * @param hdma pointer to DMA handle.
6651 * @retval None
6652 */
TIM_DMAError(DMA_HandleTypeDef * hdma)6653 void TIM_DMAError(DMA_HandleTypeDef *hdma)
6654 {
6655 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6656
6657 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6658 {
6659 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6660 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6661 }
6662 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6663 {
6664 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6665 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6666 }
6667 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6668 {
6669 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6670 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6671 }
6672 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6673 {
6674 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6675 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6676 }
6677 else
6678 {
6679 htim->State = HAL_TIM_STATE_READY;
6680 }
6681
6682 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6683 htim->ErrorCallback(htim);
6684 #else
6685 HAL_TIM_ErrorCallback(htim);
6686 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6687
6688 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6689 }
6690
6691 /**
6692 * @brief TIM DMA Delay Pulse complete callback.
6693 * @param hdma pointer to DMA handle.
6694 * @retval None
6695 */
TIM_DMADelayPulseCplt(DMA_HandleTypeDef * hdma)6696 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
6697 {
6698 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6699
6700 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6701 {
6702 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6703
6704 if (hdma->Init.Mode == DMA_NORMAL)
6705 {
6706 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6707 }
6708 }
6709 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6710 {
6711 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6712
6713 if (hdma->Init.Mode == DMA_NORMAL)
6714 {
6715 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6716 }
6717 }
6718 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6719 {
6720 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6721
6722 if (hdma->Init.Mode == DMA_NORMAL)
6723 {
6724 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6725 }
6726 }
6727 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6728 {
6729 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6730
6731 if (hdma->Init.Mode == DMA_NORMAL)
6732 {
6733 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6734 }
6735 }
6736 else
6737 {
6738 /* nothing to do */
6739 }
6740
6741 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6742 htim->PWM_PulseFinishedCallback(htim);
6743 #else
6744 HAL_TIM_PWM_PulseFinishedCallback(htim);
6745 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6746
6747 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6748 }
6749
6750 /**
6751 * @brief TIM DMA Delay Pulse half complete callback.
6752 * @param hdma pointer to DMA handle.
6753 * @retval None
6754 */
TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef * hdma)6755 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
6756 {
6757 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6758
6759 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6760 {
6761 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6762 }
6763 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6764 {
6765 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6766 }
6767 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6768 {
6769 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6770 }
6771 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6772 {
6773 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6774 }
6775 else
6776 {
6777 /* nothing to do */
6778 }
6779
6780 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6781 htim->PWM_PulseFinishedHalfCpltCallback(htim);
6782 #else
6783 HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
6784 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6785
6786 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6787 }
6788
6789 /**
6790 * @brief TIM DMA Capture complete callback.
6791 * @param hdma pointer to DMA handle.
6792 * @retval None
6793 */
TIM_DMACaptureCplt(DMA_HandleTypeDef * hdma)6794 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
6795 {
6796 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6797
6798 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6799 {
6800 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6801
6802 if (hdma->Init.Mode == DMA_NORMAL)
6803 {
6804 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6805 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6806 }
6807 }
6808 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6809 {
6810 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6811
6812 if (hdma->Init.Mode == DMA_NORMAL)
6813 {
6814 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6815 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6816 }
6817 }
6818 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6819 {
6820 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6821
6822 if (hdma->Init.Mode == DMA_NORMAL)
6823 {
6824 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6825 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6826 }
6827 }
6828 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6829 {
6830 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6831
6832 if (hdma->Init.Mode == DMA_NORMAL)
6833 {
6834 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6835 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6836 }
6837 }
6838 else
6839 {
6840 /* nothing to do */
6841 }
6842
6843 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6844 htim->IC_CaptureCallback(htim);
6845 #else
6846 HAL_TIM_IC_CaptureCallback(htim);
6847 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6848
6849 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6850 }
6851
6852 /**
6853 * @brief TIM DMA Capture half complete callback.
6854 * @param hdma pointer to DMA handle.
6855 * @retval None
6856 */
TIM_DMACaptureHalfCplt(DMA_HandleTypeDef * hdma)6857 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
6858 {
6859 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6860
6861 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6862 {
6863 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6864 }
6865 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6866 {
6867 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6868 }
6869 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6870 {
6871 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6872 }
6873 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6874 {
6875 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6876 }
6877 else
6878 {
6879 /* nothing to do */
6880 }
6881
6882 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6883 htim->IC_CaptureHalfCpltCallback(htim);
6884 #else
6885 HAL_TIM_IC_CaptureHalfCpltCallback(htim);
6886 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6887
6888 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6889 }
6890
6891 /**
6892 * @brief TIM DMA Period Elapse complete callback.
6893 * @param hdma pointer to DMA handle.
6894 * @retval None
6895 */
TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef * hdma)6896 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
6897 {
6898 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6899
6900 if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
6901 {
6902 htim->State = HAL_TIM_STATE_READY;
6903 }
6904
6905 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6906 htim->PeriodElapsedCallback(htim);
6907 #else
6908 HAL_TIM_PeriodElapsedCallback(htim);
6909 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6910 }
6911
6912 /**
6913 * @brief TIM DMA Period Elapse half complete callback.
6914 * @param hdma pointer to DMA handle.
6915 * @retval None
6916 */
TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef * hdma)6917 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
6918 {
6919 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6920
6921 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6922 htim->PeriodElapsedHalfCpltCallback(htim);
6923 #else
6924 HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
6925 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6926 }
6927
6928 /**
6929 * @brief TIM DMA Trigger callback.
6930 * @param hdma pointer to DMA handle.
6931 * @retval None
6932 */
TIM_DMATriggerCplt(DMA_HandleTypeDef * hdma)6933 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
6934 {
6935 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6936
6937 if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
6938 {
6939 htim->State = HAL_TIM_STATE_READY;
6940 }
6941
6942 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6943 htim->TriggerCallback(htim);
6944 #else
6945 HAL_TIM_TriggerCallback(htim);
6946 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6947 }
6948
6949 /**
6950 * @brief TIM DMA Trigger half complete callback.
6951 * @param hdma pointer to DMA handle.
6952 * @retval None
6953 */
TIM_DMATriggerHalfCplt(DMA_HandleTypeDef * hdma)6954 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
6955 {
6956 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6957
6958 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6959 htim->TriggerHalfCpltCallback(htim);
6960 #else
6961 HAL_TIM_TriggerHalfCpltCallback(htim);
6962 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6963 }
6964
6965 /**
6966 * @brief Time Base configuration
6967 * @param TIMx TIM peripheral
6968 * @param Structure TIM Base configuration structure
6969 * @retval None
6970 */
TIM_Base_SetConfig(TIM_TypeDef * TIMx,const TIM_Base_InitTypeDef * Structure)6971 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
6972 {
6973 uint32_t tmpcr1;
6974 tmpcr1 = TIMx->CR1;
6975
6976 /* Set TIM Time Base Unit parameters ---------------------------------------*/
6977 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
6978 {
6979 /* Select the Counter Mode */
6980 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
6981 tmpcr1 |= Structure->CounterMode;
6982 }
6983
6984 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
6985 {
6986 /* Set the clock division */
6987 tmpcr1 &= ~TIM_CR1_CKD;
6988 tmpcr1 |= (uint32_t)Structure->ClockDivision;
6989 }
6990
6991 /* Set the auto-reload preload */
6992 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
6993
6994 TIMx->CR1 = tmpcr1;
6995
6996 /* Set the Autoreload value */
6997 TIMx->ARR = (uint32_t)Structure->Period ;
6998
6999 /* Set the Prescaler value */
7000 TIMx->PSC = Structure->Prescaler;
7001
7002 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
7003 {
7004 /* Set the Repetition Counter value */
7005 TIMx->RCR = Structure->RepetitionCounter;
7006 }
7007
7008 /* Generate an update event to reload the Prescaler
7009 and the repetition counter (only for advanced timer) value immediately */
7010 TIMx->EGR = TIM_EGR_UG;
7011
7012 /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
7013 if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
7014 {
7015 /* Clear the update flag */
7016 CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
7017 }
7018 }
7019
7020 /**
7021 * @brief Timer Output Compare 1 configuration
7022 * @param TIMx to select the TIM peripheral
7023 * @param OC_Config The output configuration structure
7024 * @retval None
7025 */
TIM_OC1_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7026 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7027 {
7028 uint32_t tmpccmrx;
7029 uint32_t tmpccer;
7030 uint32_t tmpcr2;
7031
7032 /* Get the TIMx CCER register value */
7033 tmpccer = TIMx->CCER;
7034
7035 /* Disable the Channel 1: Reset the CC1E Bit */
7036 TIMx->CCER &= ~TIM_CCER_CC1E;
7037
7038 /* Get the TIMx CR2 register value */
7039 tmpcr2 = TIMx->CR2;
7040
7041 /* Get the TIMx CCMR1 register value */
7042 tmpccmrx = TIMx->CCMR1;
7043
7044 /* Reset the Output Compare Mode Bits */
7045 tmpccmrx &= ~TIM_CCMR1_OC1M;
7046 tmpccmrx &= ~TIM_CCMR1_CC1S;
7047 /* Select the Output Compare Mode */
7048 tmpccmrx |= OC_Config->OCMode;
7049
7050 /* Reset the Output Polarity level */
7051 tmpccer &= ~TIM_CCER_CC1P;
7052 /* Set the Output Compare Polarity */
7053 tmpccer |= OC_Config->OCPolarity;
7054
7055 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
7056 {
7057 /* Check parameters */
7058 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7059
7060 /* Reset the Output N Polarity level */
7061 tmpccer &= ~TIM_CCER_CC1NP;
7062 /* Set the Output N Polarity */
7063 tmpccer |= OC_Config->OCNPolarity;
7064 /* Reset the Output N State */
7065 tmpccer &= ~TIM_CCER_CC1NE;
7066 }
7067
7068 if (IS_TIM_BREAK_INSTANCE(TIMx))
7069 {
7070 /* Check parameters */
7071 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7072 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7073
7074 /* Reset the Output Compare and Output Compare N IDLE State */
7075 tmpcr2 &= ~TIM_CR2_OIS1;
7076 tmpcr2 &= ~TIM_CR2_OIS1N;
7077 /* Set the Output Idle state */
7078 tmpcr2 |= OC_Config->OCIdleState;
7079 /* Set the Output N Idle state */
7080 tmpcr2 |= OC_Config->OCNIdleState;
7081 }
7082
7083 /* Write to TIMx CR2 */
7084 TIMx->CR2 = tmpcr2;
7085
7086 /* Write to TIMx CCMR1 */
7087 TIMx->CCMR1 = tmpccmrx;
7088
7089 /* Set the Capture Compare Register value */
7090 TIMx->CCR1 = OC_Config->Pulse;
7091
7092 /* Write to TIMx CCER */
7093 TIMx->CCER = tmpccer;
7094 }
7095
7096 /**
7097 * @brief Timer Output Compare 2 configuration
7098 * @param TIMx to select the TIM peripheral
7099 * @param OC_Config The output configuration structure
7100 * @retval None
7101 */
TIM_OC2_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7102 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7103 {
7104 uint32_t tmpccmrx;
7105 uint32_t tmpccer;
7106 uint32_t tmpcr2;
7107
7108 /* Get the TIMx CCER register value */
7109 tmpccer = TIMx->CCER;
7110
7111 /* Disable the Channel 2: Reset the CC2E Bit */
7112 TIMx->CCER &= ~TIM_CCER_CC2E;
7113
7114 /* Get the TIMx CR2 register value */
7115 tmpcr2 = TIMx->CR2;
7116
7117 /* Get the TIMx CCMR1 register value */
7118 tmpccmrx = TIMx->CCMR1;
7119
7120 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7121 tmpccmrx &= ~TIM_CCMR1_OC2M;
7122 tmpccmrx &= ~TIM_CCMR1_CC2S;
7123
7124 /* Select the Output Compare Mode */
7125 tmpccmrx |= (OC_Config->OCMode << 8U);
7126
7127 /* Reset the Output Polarity level */
7128 tmpccer &= ~TIM_CCER_CC2P;
7129 /* Set the Output Compare Polarity */
7130 tmpccer |= (OC_Config->OCPolarity << 4U);
7131
7132 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
7133 {
7134 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7135
7136 /* Reset the Output N Polarity level */
7137 tmpccer &= ~TIM_CCER_CC2NP;
7138 /* Set the Output N Polarity */
7139 tmpccer |= (OC_Config->OCNPolarity << 4U);
7140 /* Reset the Output N State */
7141 tmpccer &= ~TIM_CCER_CC2NE;
7142 }
7143
7144 if (IS_TIM_BREAK_INSTANCE(TIMx))
7145 {
7146 /* Check parameters */
7147 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7148 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7149
7150 /* Reset the Output Compare and Output Compare N IDLE State */
7151 tmpcr2 &= ~TIM_CR2_OIS2;
7152 #if defined(TIM_CR2_OIS2N)
7153 tmpcr2 &= ~TIM_CR2_OIS2N;
7154 #endif /* TIM_CR2_OIS2N */
7155 /* Set the Output Idle state */
7156 tmpcr2 |= (OC_Config->OCIdleState << 2U);
7157 /* Set the Output N Idle state */
7158 tmpcr2 |= (OC_Config->OCNIdleState << 2U);
7159 }
7160
7161 /* Write to TIMx CR2 */
7162 TIMx->CR2 = tmpcr2;
7163
7164 /* Write to TIMx CCMR1 */
7165 TIMx->CCMR1 = tmpccmrx;
7166
7167 /* Set the Capture Compare Register value */
7168 TIMx->CCR2 = OC_Config->Pulse;
7169
7170 /* Write to TIMx CCER */
7171 TIMx->CCER = tmpccer;
7172 }
7173
7174 /**
7175 * @brief Timer Output Compare 3 configuration
7176 * @param TIMx to select the TIM peripheral
7177 * @param OC_Config The output configuration structure
7178 * @retval None
7179 */
TIM_OC3_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7180 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7181 {
7182 uint32_t tmpccmrx;
7183 uint32_t tmpccer;
7184 uint32_t tmpcr2;
7185
7186 /* Get the TIMx CCER register value */
7187 tmpccer = TIMx->CCER;
7188
7189 /* Disable the Channel 3: Reset the CC2E Bit */
7190 TIMx->CCER &= ~TIM_CCER_CC3E;
7191
7192 /* Get the TIMx CR2 register value */
7193 tmpcr2 = TIMx->CR2;
7194
7195 /* Get the TIMx CCMR2 register value */
7196 tmpccmrx = TIMx->CCMR2;
7197
7198 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7199 tmpccmrx &= ~TIM_CCMR2_OC3M;
7200 tmpccmrx &= ~TIM_CCMR2_CC3S;
7201 /* Select the Output Compare Mode */
7202 tmpccmrx |= OC_Config->OCMode;
7203
7204 /* Reset the Output Polarity level */
7205 tmpccer &= ~TIM_CCER_CC3P;
7206 /* Set the Output Compare Polarity */
7207 tmpccer |= (OC_Config->OCPolarity << 8U);
7208
7209 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
7210 {
7211 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7212
7213 /* Reset the Output N Polarity level */
7214 tmpccer &= ~TIM_CCER_CC3NP;
7215 /* Set the Output N Polarity */
7216 tmpccer |= (OC_Config->OCNPolarity << 8U);
7217 /* Reset the Output N State */
7218 tmpccer &= ~TIM_CCER_CC3NE;
7219 }
7220
7221 #if defined(TIM_CR2_OIS3)
7222 if (IS_TIM_BREAK_INSTANCE(TIMx))
7223 {
7224 /* Check parameters */
7225 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7226 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7227
7228 /* Reset the Output Compare and Output Compare N IDLE State */
7229 tmpcr2 &= ~TIM_CR2_OIS3;
7230 tmpcr2 &= ~TIM_CR2_OIS3N;
7231 /* Set the Output Idle state */
7232 tmpcr2 |= (OC_Config->OCIdleState << 4U);
7233 /* Set the Output N Idle state */
7234 tmpcr2 |= (OC_Config->OCNIdleState << 4U);
7235 }
7236 #endif /* TIM_CR2_OIS3 */
7237
7238 /* Write to TIMx CR2 */
7239 TIMx->CR2 = tmpcr2;
7240
7241 /* Write to TIMx CCMR2 */
7242 TIMx->CCMR2 = tmpccmrx;
7243
7244 /* Set the Capture Compare Register value */
7245 TIMx->CCR3 = OC_Config->Pulse;
7246
7247 /* Write to TIMx CCER */
7248 TIMx->CCER = tmpccer;
7249 }
7250
7251 /**
7252 * @brief Timer Output Compare 4 configuration
7253 * @param TIMx to select the TIM peripheral
7254 * @param OC_Config The output configuration structure
7255 * @retval None
7256 */
TIM_OC4_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7257 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7258 {
7259 uint32_t tmpccmrx;
7260 uint32_t tmpccer;
7261 uint32_t tmpcr2;
7262
7263 /* Get the TIMx CCER register value */
7264 tmpccer = TIMx->CCER;
7265
7266 /* Disable the Channel 4: Reset the CC4E Bit */
7267 TIMx->CCER &= ~TIM_CCER_CC4E;
7268
7269 /* Get the TIMx CR2 register value */
7270 tmpcr2 = TIMx->CR2;
7271
7272 /* Get the TIMx CCMR2 register value */
7273 tmpccmrx = TIMx->CCMR2;
7274
7275 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7276 tmpccmrx &= ~TIM_CCMR2_OC4M;
7277 tmpccmrx &= ~TIM_CCMR2_CC4S;
7278
7279 /* Select the Output Compare Mode */
7280 tmpccmrx |= (OC_Config->OCMode << 8U);
7281
7282 /* Reset the Output Polarity level */
7283 tmpccer &= ~TIM_CCER_CC4P;
7284 /* Set the Output Compare Polarity */
7285 tmpccer |= (OC_Config->OCPolarity << 12U);
7286
7287 #if defined(TIM_CR2_OIS4)
7288 if (IS_TIM_BREAK_INSTANCE(TIMx))
7289 {
7290 /* Check parameters */
7291 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7292
7293 /* Reset the Output Compare IDLE State */
7294 tmpcr2 &= ~TIM_CR2_OIS4;
7295
7296 /* Set the Output Idle state */
7297 tmpcr2 |= (OC_Config->OCIdleState << 6U);
7298 }
7299 #endif /* TIM_CR2_OIS4 */
7300
7301 /* Write to TIMx CR2 */
7302 TIMx->CR2 = tmpcr2;
7303
7304 /* Write to TIMx CCMR2 */
7305 TIMx->CCMR2 = tmpccmrx;
7306
7307 /* Set the Capture Compare Register value */
7308 TIMx->CCR4 = OC_Config->Pulse;
7309
7310 /* Write to TIMx CCER */
7311 TIMx->CCER = tmpccer;
7312 }
7313
7314 #if defined(TIM_CCER_CC5E)
7315 /**
7316 * @brief Timer Output Compare 5 configuration
7317 * @param TIMx to select the TIM peripheral
7318 * @param OC_Config The output configuration structure
7319 * @retval None
7320 */
TIM_OC5_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7321 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
7322 const TIM_OC_InitTypeDef *OC_Config)
7323 {
7324 uint32_t tmpccmrx;
7325 uint32_t tmpccer;
7326 uint32_t tmpcr2;
7327
7328 /* Get the TIMx CCER register value */
7329 tmpccer = TIMx->CCER;
7330
7331 /* Disable the output: Reset the CCxE Bit */
7332 TIMx->CCER &= ~TIM_CCER_CC5E;
7333
7334 /* Get the TIMx CR2 register value */
7335 tmpcr2 = TIMx->CR2;
7336 /* Get the TIMx CCMR1 register value */
7337 tmpccmrx = TIMx->CCMR3;
7338
7339 /* Reset the Output Compare Mode Bits */
7340 tmpccmrx &= ~(TIM_CCMR3_OC5M);
7341 /* Select the Output Compare Mode */
7342 tmpccmrx |= OC_Config->OCMode;
7343
7344 /* Reset the Output Polarity level */
7345 tmpccer &= ~TIM_CCER_CC5P;
7346 /* Set the Output Compare Polarity */
7347 tmpccer |= (OC_Config->OCPolarity << 16U);
7348
7349 if (IS_TIM_BREAK_INSTANCE(TIMx))
7350 {
7351 /* Reset the Output Compare IDLE State */
7352 tmpcr2 &= ~TIM_CR2_OIS5;
7353 /* Set the Output Idle state */
7354 tmpcr2 |= (OC_Config->OCIdleState << 8U);
7355 }
7356 /* Write to TIMx CR2 */
7357 TIMx->CR2 = tmpcr2;
7358
7359 /* Write to TIMx CCMR3 */
7360 TIMx->CCMR3 = tmpccmrx;
7361
7362 /* Set the Capture Compare Register value */
7363 TIMx->CCR5 = OC_Config->Pulse;
7364
7365 /* Write to TIMx CCER */
7366 TIMx->CCER = tmpccer;
7367 }
7368 #endif /* TIM_CCER_CC5E */
7369
7370 #if defined(TIM_CCER_CC6E)
7371 /**
7372 * @brief Timer Output Compare 6 configuration
7373 * @param TIMx to select the TIM peripheral
7374 * @param OC_Config The output configuration structure
7375 * @retval None
7376 */
TIM_OC6_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7377 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
7378 const TIM_OC_InitTypeDef *OC_Config)
7379 {
7380 uint32_t tmpccmrx;
7381 uint32_t tmpccer;
7382 uint32_t tmpcr2;
7383
7384 /* Get the TIMx CCER register value */
7385 tmpccer = TIMx->CCER;
7386
7387 /* Disable the output: Reset the CCxE Bit */
7388 TIMx->CCER &= ~TIM_CCER_CC6E;
7389
7390 /* Get the TIMx CR2 register value */
7391 tmpcr2 = TIMx->CR2;
7392 /* Get the TIMx CCMR1 register value */
7393 tmpccmrx = TIMx->CCMR3;
7394
7395 /* Reset the Output Compare Mode Bits */
7396 tmpccmrx &= ~(TIM_CCMR3_OC6M);
7397 /* Select the Output Compare Mode */
7398 tmpccmrx |= (OC_Config->OCMode << 8U);
7399
7400 /* Reset the Output Polarity level */
7401 tmpccer &= (uint32_t)~TIM_CCER_CC6P;
7402 /* Set the Output Compare Polarity */
7403 tmpccer |= (OC_Config->OCPolarity << 20U);
7404
7405 if (IS_TIM_BREAK_INSTANCE(TIMx))
7406 {
7407 /* Reset the Output Compare IDLE State */
7408 tmpcr2 &= ~TIM_CR2_OIS6;
7409 /* Set the Output Idle state */
7410 tmpcr2 |= (OC_Config->OCIdleState << 10U);
7411 }
7412
7413 /* Write to TIMx CR2 */
7414 TIMx->CR2 = tmpcr2;
7415
7416 /* Write to TIMx CCMR3 */
7417 TIMx->CCMR3 = tmpccmrx;
7418
7419 /* Set the Capture Compare Register value */
7420 TIMx->CCR6 = OC_Config->Pulse;
7421
7422 /* Write to TIMx CCER */
7423 TIMx->CCER = tmpccer;
7424 }
7425 #endif /* TIM_CCER_CC6E */
7426
7427 /**
7428 * @brief Slave Timer configuration function
7429 * @param htim TIM handle
7430 * @param sSlaveConfig Slave timer configuration
7431 * @retval None
7432 */
TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)7433 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
7434 const TIM_SlaveConfigTypeDef *sSlaveConfig)
7435 {
7436 HAL_StatusTypeDef status = HAL_OK;
7437 uint32_t tmpsmcr;
7438 uint32_t tmpccmr1;
7439 uint32_t tmpccer;
7440
7441 /* Get the TIMx SMCR register value */
7442 tmpsmcr = htim->Instance->SMCR;
7443
7444 /* Reset the Trigger Selection Bits */
7445 tmpsmcr &= ~TIM_SMCR_TS;
7446 /* Set the Input Trigger source */
7447 tmpsmcr |= sSlaveConfig->InputTrigger;
7448
7449 /* Reset the slave mode Bits */
7450 tmpsmcr &= ~TIM_SMCR_SMS;
7451 /* Set the slave mode */
7452 tmpsmcr |= sSlaveConfig->SlaveMode;
7453
7454 /* Write to TIMx SMCR */
7455 htim->Instance->SMCR = tmpsmcr;
7456
7457 /* Configure the trigger prescaler, filter, and polarity */
7458 switch (sSlaveConfig->InputTrigger)
7459 {
7460 case TIM_TS_ETRF:
7461 {
7462 /* Check the parameters */
7463 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
7464 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
7465 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7466 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7467 /* Configure the ETR Trigger source */
7468 TIM_ETR_SetConfig(htim->Instance,
7469 sSlaveConfig->TriggerPrescaler,
7470 sSlaveConfig->TriggerPolarity,
7471 sSlaveConfig->TriggerFilter);
7472 break;
7473 }
7474
7475 case TIM_TS_TI1F_ED:
7476 {
7477 /* Check the parameters */
7478 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7479 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7480
7481 if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
7482 {
7483 return HAL_ERROR;
7484 }
7485
7486 /* Disable the Channel 1: Reset the CC1E Bit */
7487 tmpccer = htim->Instance->CCER;
7488 htim->Instance->CCER &= ~TIM_CCER_CC1E;
7489 tmpccmr1 = htim->Instance->CCMR1;
7490
7491 /* Set the filter */
7492 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7493 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
7494
7495 /* Write to TIMx CCMR1 and CCER registers */
7496 htim->Instance->CCMR1 = tmpccmr1;
7497 htim->Instance->CCER = tmpccer;
7498 break;
7499 }
7500
7501 case TIM_TS_TI1FP1:
7502 {
7503 /* Check the parameters */
7504 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7505 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7506 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7507
7508 /* Configure TI1 Filter and Polarity */
7509 TIM_TI1_ConfigInputStage(htim->Instance,
7510 sSlaveConfig->TriggerPolarity,
7511 sSlaveConfig->TriggerFilter);
7512 break;
7513 }
7514
7515 case TIM_TS_TI2FP2:
7516 {
7517 /* Check the parameters */
7518 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
7519 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7520 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7521
7522 /* Configure TI2 Filter and Polarity */
7523 TIM_TI2_ConfigInputStage(htim->Instance,
7524 sSlaveConfig->TriggerPolarity,
7525 sSlaveConfig->TriggerFilter);
7526 break;
7527 }
7528
7529 case TIM_TS_ITR0:
7530 case TIM_TS_ITR1:
7531 case TIM_TS_ITR2:
7532 case TIM_TS_ITR3:
7533 {
7534 /* Check the parameter */
7535 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
7536 break;
7537 }
7538
7539 default:
7540 status = HAL_ERROR;
7541 break;
7542 }
7543
7544 return status;
7545 }
7546
7547 /**
7548 * @brief Configure the TI1 as Input.
7549 * @param TIMx to select the TIM peripheral.
7550 * @param TIM_ICPolarity The Input Polarity.
7551 * This parameter can be one of the following values:
7552 * @arg TIM_ICPOLARITY_RISING
7553 * @arg TIM_ICPOLARITY_FALLING
7554 * @arg TIM_ICPOLARITY_BOTHEDGE
7555 * @param TIM_ICSelection specifies the input to be used.
7556 * This parameter can be one of the following values:
7557 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
7558 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
7559 * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
7560 * @param TIM_ICFilter Specifies the Input Capture Filter.
7561 * This parameter must be a value between 0x00 and 0x0F.
7562 * @retval None
7563 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
7564 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
7565 * protected against un-initialized filter and polarity values.
7566 */
TIM_TI1_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7567 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7568 uint32_t TIM_ICFilter)
7569 {
7570 uint32_t tmpccmr1;
7571 uint32_t tmpccer;
7572
7573 /* Disable the Channel 1: Reset the CC1E Bit */
7574 tmpccer = TIMx->CCER;
7575 TIMx->CCER &= ~TIM_CCER_CC1E;
7576 tmpccmr1 = TIMx->CCMR1;
7577
7578 /* Select the Input */
7579 if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
7580 {
7581 tmpccmr1 &= ~TIM_CCMR1_CC1S;
7582 tmpccmr1 |= TIM_ICSelection;
7583 }
7584 else
7585 {
7586 tmpccmr1 |= TIM_CCMR1_CC1S_0;
7587 }
7588
7589 /* Set the filter */
7590 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7591 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
7592
7593 /* Select the Polarity and set the CC1E Bit */
7594 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7595 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
7596
7597 /* Write to TIMx CCMR1 and CCER registers */
7598 TIMx->CCMR1 = tmpccmr1;
7599 TIMx->CCER = tmpccer;
7600 }
7601
7602 /**
7603 * @brief Configure the Polarity and Filter for TI1.
7604 * @param TIMx to select the TIM peripheral.
7605 * @param TIM_ICPolarity The Input Polarity.
7606 * This parameter can be one of the following values:
7607 * @arg TIM_ICPOLARITY_RISING
7608 * @arg TIM_ICPOLARITY_FALLING
7609 * @arg TIM_ICPOLARITY_BOTHEDGE
7610 * @param TIM_ICFilter Specifies the Input Capture Filter.
7611 * This parameter must be a value between 0x00 and 0x0F.
7612 * @retval None
7613 */
TIM_TI1_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7614 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7615 {
7616 uint32_t tmpccmr1;
7617 uint32_t tmpccer;
7618
7619 /* Disable the Channel 1: Reset the CC1E Bit */
7620 tmpccer = TIMx->CCER;
7621 TIMx->CCER &= ~TIM_CCER_CC1E;
7622 tmpccmr1 = TIMx->CCMR1;
7623
7624 /* Set the filter */
7625 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7626 tmpccmr1 |= (TIM_ICFilter << 4U);
7627
7628 /* Select the Polarity and set the CC1E Bit */
7629 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7630 tmpccer |= TIM_ICPolarity;
7631
7632 /* Write to TIMx CCMR1 and CCER registers */
7633 TIMx->CCMR1 = tmpccmr1;
7634 TIMx->CCER = tmpccer;
7635 }
7636
7637 /**
7638 * @brief Configure the TI2 as Input.
7639 * @param TIMx to select the TIM peripheral
7640 * @param TIM_ICPolarity The Input Polarity.
7641 * This parameter can be one of the following values:
7642 * @arg TIM_ICPOLARITY_RISING
7643 * @arg TIM_ICPOLARITY_FALLING
7644 * @arg TIM_ICPOLARITY_BOTHEDGE
7645 * @param TIM_ICSelection specifies the input to be used.
7646 * This parameter can be one of the following values:
7647 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
7648 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
7649 * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
7650 * @param TIM_ICFilter Specifies the Input Capture Filter.
7651 * This parameter must be a value between 0x00 and 0x0F.
7652 * @retval None
7653 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
7654 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
7655 * protected against un-initialized filter and polarity values.
7656 */
TIM_TI2_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7657 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7658 uint32_t TIM_ICFilter)
7659 {
7660 uint32_t tmpccmr1;
7661 uint32_t tmpccer;
7662
7663 /* Disable the Channel 2: Reset the CC2E Bit */
7664 tmpccer = TIMx->CCER;
7665 TIMx->CCER &= ~TIM_CCER_CC2E;
7666 tmpccmr1 = TIMx->CCMR1;
7667
7668 /* Select the Input */
7669 tmpccmr1 &= ~TIM_CCMR1_CC2S;
7670 tmpccmr1 |= (TIM_ICSelection << 8U);
7671
7672 /* Set the filter */
7673 tmpccmr1 &= ~TIM_CCMR1_IC2F;
7674 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
7675
7676 /* Select the Polarity and set the CC2E Bit */
7677 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7678 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
7679
7680 /* Write to TIMx CCMR1 and CCER registers */
7681 TIMx->CCMR1 = tmpccmr1 ;
7682 TIMx->CCER = tmpccer;
7683 }
7684
7685 /**
7686 * @brief Configure the Polarity and Filter for TI2.
7687 * @param TIMx to select the TIM peripheral.
7688 * @param TIM_ICPolarity The Input Polarity.
7689 * This parameter can be one of the following values:
7690 * @arg TIM_ICPOLARITY_RISING
7691 * @arg TIM_ICPOLARITY_FALLING
7692 * @arg TIM_ICPOLARITY_BOTHEDGE
7693 * @param TIM_ICFilter Specifies the Input Capture Filter.
7694 * This parameter must be a value between 0x00 and 0x0F.
7695 * @retval None
7696 */
TIM_TI2_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7697 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7698 {
7699 uint32_t tmpccmr1;
7700 uint32_t tmpccer;
7701
7702 /* Disable the Channel 2: Reset the CC2E Bit */
7703 tmpccer = TIMx->CCER;
7704 TIMx->CCER &= ~TIM_CCER_CC2E;
7705 tmpccmr1 = TIMx->CCMR1;
7706
7707 /* Set the filter */
7708 tmpccmr1 &= ~TIM_CCMR1_IC2F;
7709 tmpccmr1 |= (TIM_ICFilter << 12U);
7710
7711 /* Select the Polarity and set the CC2E Bit */
7712 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7713 tmpccer |= (TIM_ICPolarity << 4U);
7714
7715 /* Write to TIMx CCMR1 and CCER registers */
7716 TIMx->CCMR1 = tmpccmr1 ;
7717 TIMx->CCER = tmpccer;
7718 }
7719
7720 /**
7721 * @brief Configure the TI3 as Input.
7722 * @param TIMx to select the TIM peripheral
7723 * @param TIM_ICPolarity The Input Polarity.
7724 * This parameter can be one of the following values:
7725 * @arg TIM_ICPOLARITY_RISING
7726 * @arg TIM_ICPOLARITY_FALLING
7727 * @arg TIM_ICPOLARITY_BOTHEDGE
7728 * @param TIM_ICSelection specifies the input to be used.
7729 * This parameter can be one of the following values:
7730 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
7731 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
7732 * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
7733 * @param TIM_ICFilter Specifies the Input Capture Filter.
7734 * This parameter must be a value between 0x00 and 0x0F.
7735 * @retval None
7736 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
7737 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7738 * protected against un-initialized filter and polarity values.
7739 */
TIM_TI3_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7740 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7741 uint32_t TIM_ICFilter)
7742 {
7743 uint32_t tmpccmr2;
7744 uint32_t tmpccer;
7745
7746 /* Disable the Channel 3: Reset the CC3E Bit */
7747 tmpccer = TIMx->CCER;
7748 TIMx->CCER &= ~TIM_CCER_CC3E;
7749 tmpccmr2 = TIMx->CCMR2;
7750
7751 /* Select the Input */
7752 tmpccmr2 &= ~TIM_CCMR2_CC3S;
7753 tmpccmr2 |= TIM_ICSelection;
7754
7755 /* Set the filter */
7756 tmpccmr2 &= ~TIM_CCMR2_IC3F;
7757 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
7758
7759 /* Select the Polarity and set the CC3E Bit */
7760 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
7761 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
7762
7763 /* Write to TIMx CCMR2 and CCER registers */
7764 TIMx->CCMR2 = tmpccmr2;
7765 TIMx->CCER = tmpccer;
7766 }
7767
7768 /**
7769 * @brief Configure the TI4 as Input.
7770 * @param TIMx to select the TIM peripheral
7771 * @param TIM_ICPolarity The Input Polarity.
7772 * This parameter can be one of the following values:
7773 * @arg TIM_ICPOLARITY_RISING
7774 * @arg TIM_ICPOLARITY_FALLING
7775 * @arg TIM_ICPOLARITY_BOTHEDGE
7776 * @param TIM_ICSelection specifies the input to be used.
7777 * This parameter can be one of the following values:
7778 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
7779 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
7780 * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
7781 * @param TIM_ICFilter Specifies the Input Capture Filter.
7782 * This parameter must be a value between 0x00 and 0x0F.
7783 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
7784 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7785 * protected against un-initialized filter and polarity values.
7786 * @retval None
7787 */
TIM_TI4_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7788 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7789 uint32_t TIM_ICFilter)
7790 {
7791 uint32_t tmpccmr2;
7792 uint32_t tmpccer;
7793
7794 /* Disable the Channel 4: Reset the CC4E Bit */
7795 tmpccer = TIMx->CCER;
7796 TIMx->CCER &= ~TIM_CCER_CC4E;
7797 tmpccmr2 = TIMx->CCMR2;
7798
7799 /* Select the Input */
7800 tmpccmr2 &= ~TIM_CCMR2_CC4S;
7801 tmpccmr2 |= (TIM_ICSelection << 8U);
7802
7803 /* Set the filter */
7804 tmpccmr2 &= ~TIM_CCMR2_IC4F;
7805 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
7806
7807 /* Select the Polarity and set the CC4E Bit */
7808 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
7809 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
7810
7811 /* Write to TIMx CCMR2 and CCER registers */
7812 TIMx->CCMR2 = tmpccmr2;
7813 TIMx->CCER = tmpccer ;
7814 }
7815
7816 /**
7817 * @brief Selects the Input Trigger source
7818 * @param TIMx to select the TIM peripheral
7819 * @param InputTriggerSource The Input Trigger source.
7820 * This parameter can be one of the following values:
7821 * @arg TIM_TS_ITR0: Internal Trigger 0
7822 * @arg TIM_TS_ITR1: Internal Trigger 1
7823 * @arg TIM_TS_ITR2: Internal Trigger 2
7824 * @arg TIM_TS_ITR3: Internal Trigger 3
7825 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
7826 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
7827 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
7828 * @arg TIM_TS_ETRF: External Trigger input
7829 * @retval None
7830 */
TIM_ITRx_SetConfig(TIM_TypeDef * TIMx,uint32_t InputTriggerSource)7831 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
7832 {
7833 uint32_t tmpsmcr;
7834
7835 /* Get the TIMx SMCR register value */
7836 tmpsmcr = TIMx->SMCR;
7837 /* Reset the TS Bits */
7838 tmpsmcr &= ~TIM_SMCR_TS;
7839 /* Set the Input Trigger source and the slave mode*/
7840 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
7841 /* Write to TIMx SMCR */
7842 TIMx->SMCR = tmpsmcr;
7843 }
7844 /**
7845 * @brief Configures the TIMx External Trigger (ETR).
7846 * @param TIMx to select the TIM peripheral
7847 * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
7848 * This parameter can be one of the following values:
7849 * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
7850 * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
7851 * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
7852 * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
7853 * @param TIM_ExtTRGPolarity The external Trigger Polarity.
7854 * This parameter can be one of the following values:
7855 * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
7856 * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
7857 * @param ExtTRGFilter External Trigger Filter.
7858 * This parameter must be a value between 0x00 and 0x0F
7859 * @retval None
7860 */
TIM_ETR_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ExtTRGPrescaler,uint32_t TIM_ExtTRGPolarity,uint32_t ExtTRGFilter)7861 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
7862 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
7863 {
7864 uint32_t tmpsmcr;
7865
7866 tmpsmcr = TIMx->SMCR;
7867
7868 /* Reset the ETR Bits */
7869 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
7870
7871 /* Set the Prescaler, the Filter value and the Polarity */
7872 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
7873
7874 /* Write to TIMx SMCR */
7875 TIMx->SMCR = tmpsmcr;
7876 }
7877
7878 /**
7879 * @brief Enables or disables the TIM Capture Compare Channel x.
7880 * @param TIMx to select the TIM peripheral
7881 * @param Channel specifies the TIM Channel
7882 * This parameter can be one of the following values:
7883 * @arg TIM_CHANNEL_1: TIM Channel 1
7884 * @arg TIM_CHANNEL_2: TIM Channel 2
7885 * @arg TIM_CHANNEL_3: TIM Channel 3
7886 * @arg TIM_CHANNEL_4: TIM Channel 4
7887 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
7888 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
7889 * @param ChannelState specifies the TIM Channel CCxE bit new state.
7890 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
7891 * @retval None
7892 */
TIM_CCxChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelState)7893 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
7894 {
7895 uint32_t tmp;
7896
7897 /* Check the parameters */
7898 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
7899 assert_param(IS_TIM_CHANNELS(Channel));
7900
7901 tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
7902
7903 /* Reset the CCxE Bit */
7904 TIMx->CCER &= ~tmp;
7905
7906 /* Set or reset the CCxE Bit */
7907 TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
7908 }
7909
7910 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7911 /**
7912 * @brief Reset interrupt callbacks to the legacy weak callbacks.
7913 * @param htim pointer to a TIM_HandleTypeDef structure that contains
7914 * the configuration information for TIM module.
7915 * @retval None
7916 */
TIM_ResetCallback(TIM_HandleTypeDef * htim)7917 void TIM_ResetCallback(TIM_HandleTypeDef *htim)
7918 {
7919 /* Reset the TIM callback to the legacy weak callbacks */
7920 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
7921 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
7922 htim->TriggerCallback = HAL_TIM_TriggerCallback;
7923 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
7924 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
7925 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
7926 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
7927 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
7928 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
7929 htim->ErrorCallback = HAL_TIM_ErrorCallback;
7930 htim->CommutationCallback = HAL_TIMEx_CommutCallback;
7931 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
7932 htim->BreakCallback = HAL_TIMEx_BreakCallback;
7933 #if defined(TIM_BDTR_BK2E)
7934 htim->Break2Callback = HAL_TIMEx_Break2Callback;
7935 #endif /* TIM_BDTR_BK2E */
7936 }
7937 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7938
7939 /**
7940 * @}
7941 */
7942
7943 #endif /* HAL_TIM_MODULE_ENABLED */
7944 /**
7945 * @}
7946 */
7947
7948 /**
7949 * @}
7950 */
7951
