1 /**
2 ******************************************************************************
3 * @file stm32f3xx_hal_adc_ex.c
4 * @author MCD Application Team
5 * @brief This file provides firmware functions to manage the following
6 * functionalities of the Analog to Digital Convertor (ADC)
7 * peripheral:
8 * + Peripheral Control functions
9 * Other functions (generic functions) are available in file
10 * "stm32f3xx_hal_adc.c".
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2016 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 [..]
25 (@) Sections "ADC peripheral features" and "How to use this driver" are
26 available in file of generic functions "stm32f3xx_hal_adc.c".
27 [..]
28 @endverbatim
29 */
30
31 /* Includes ------------------------------------------------------------------*/
32 #include "stm32f3xx_hal.h"
33
34 /** @addtogroup STM32F3xx_HAL_Driver
35 * @{
36 */
37
38 /** @defgroup ADCEx ADCEx
39 * @brief ADC Extended HAL module driver
40 * @{
41 */
42
43 #ifdef HAL_ADC_MODULE_ENABLED
44
45 /* Private typedef -----------------------------------------------------------*/
46 /* Private define ------------------------------------------------------------*/
47 /** @defgroup ADCEx_Private_Constants ADCEx Private Constants
48 * @{
49 */
50 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
51 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
52 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
53 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
54 /* Fixed timeout values for ADC calibration, enable settling time, disable */
55 /* settling time. */
56 /* Values defined to be higher than worst cases: low clock frequency, */
57 /* maximum prescalers. */
58 /* Ex of profile low frequency : Clock source at 0.5 MHz, ADC clock */
59 /* prescaler 256 (devices STM32F30xx), sampling time 7.5 ADC clock cycles, */
60 /* resolution 12 bits. */
61 /* Unit: ms */
62 #define ADC_CALIBRATION_TIMEOUT ( 10U)
63 #define ADC_ENABLE_TIMEOUT ( 2U)
64 #define ADC_DISABLE_TIMEOUT ( 2U)
65 #define ADC_STOP_CONVERSION_TIMEOUT ( 11U)
66
67 /* Timeout to wait for current conversion on going to be completed. */
68 /* Timeout fixed to worst case, for 1 channel. */
69 /* - maximum sampling time (601.5 adc_clk) */
70 /* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */
71 /* - ADC clock (from PLL with prescaler 256 (devices STM32F30xx)) */
72 /* Unit: cycles of CPU clock. */
73 #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ( 156928U)
74
75 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
76 /* Maximum delay is 10us (refer to device datasheet, param. TADCVREG_STUP). */
77 /* Unit: us */
78 #define ADC_STAB_DELAY_US ( 10U)
79
80 /* Delay for temperature sensor stabilization time. */
81 /* Maximum delay is 10us (refer device datasheet, parameter tSTART). */
82 /* Unit: us */
83 #define ADC_TEMPSENSOR_DELAY_US ( 10U)
84
85 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
86 /* STM32F302xC || STM32F303xC || STM32F358xx || */
87 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
88 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
89
90 #if defined(STM32F373xC) || defined(STM32F378xx)
91 /* Timeout values for ADC enable and disable settling time. */
92 /* Values defined to be higher than worst cases: low clocks freq, */
93 /* maximum prescaler. */
94 /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
95 /* prescaler 4U, sampling time 12.5 ADC clock cycles, resolution 12 bits. */
96 /* Unit: ms */
97 #define ADC_ENABLE_TIMEOUT ( 2U)
98 #define ADC_DISABLE_TIMEOUT ( 2U)
99
100 /* Delay for ADC calibration: */
101 /* Hardware prerequisite before starting a calibration: the ADC must have */
102 /* been in power-on state for at least two ADC clock cycles. */
103 /* Unit: ADC clock cycles */
104 #define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ( 2U)
105
106 /* Timeout value for ADC calibration */
107 /* Value defined to be higher than worst cases: low clocks freq, */
108 /* maximum prescaler. */
109 /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
110 /* prescaler 4U, sampling time 12.5 ADC clock cycles, resolution 12 bits. */
111 /* Unit: ms */
112 #define ADC_CALIBRATION_TIMEOUT ( 10U)
113
114 /* Delay for ADC stabilization time. */
115 /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
116 /* Unit: us */
117 #define ADC_STAB_DELAY_US ( 1U)
118
119 /* Delay for temperature sensor stabilization time. */
120 /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
121 /* Unit: us */
122 #define ADC_TEMPSENSOR_DELAY_US ( 10U)
123
124 /* Maximum number of CPU cycles corresponding to 1 ADC cycle */
125 /* Value fixed to worst case: clock prescalers slowing down ADC clock to */
126 /* minimum frequency */
127 /* - AHB prescaler: 16 */
128 /* - ADC prescaler: 8 */
129 /* Unit: cycles of CPU clock. */
130 #define ADC_CYCLE_WORST_CASE_CPU_CYCLES ( 128U)
131
132 /* ADC conversion cycles (unit: ADC clock cycles) */
133 /* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */
134 /* resolution 12 bits) */
135 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 ( 14U)
136 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 ( 20U)
137 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 ( 26U)
138 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 ( 41U)
139 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 ( 54U)
140 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 ( 68U)
141 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 ( 84U)
142 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 (252U)
143 #endif /* STM32F373xC || STM32F378xx */
144 /**
145 * @}
146 */
147
148 /* Private macro -------------------------------------------------------------*/
149 /* Private variables ---------------------------------------------------------*/
150 /* Private function prototypes -----------------------------------------------*/
151 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
152 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
153 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
154 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
155 static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
156 static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc);
157 static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup);
158 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
159 /* STM32F302xC || STM32F303xC || STM32F358xx || */
160 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
161 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
162
163 #if defined(STM32F373xC) || defined(STM32F378xx)
164 static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
165 static HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc);
166 #endif /* STM32F373xC || STM32F378xx */
167
168 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
169 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
170 static void ADC_DMAError(DMA_HandleTypeDef *hdma);
171
172 /* Exported functions --------------------------------------------------------*/
173
174 /** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions
175 * @{
176 */
177
178 /** @defgroup ADCEx_Exported_Functions_Group1 ADCEx Initialization and de-initialization functions
179 * @brief ADC Extended Initialization and Configuration functions
180 *
181 @verbatim
182 ===============================================================================
183 ##### Initialization and de-initialization functions #####
184 ===============================================================================
185 [..] This section provides functions allowing to:
186 (+) Initialize and configure the ADC.
187 (+) De-initialize the ADC.
188
189 @endverbatim
190 * @{
191 */
192
193 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
194 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
195 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
196 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
197 /**
198 * @brief Initializes the ADC peripheral and regular group according to
199 * parameters specified in structure "ADC_InitTypeDef".
200 * @note As prerequisite, ADC clock must be configured at RCC top level
201 * depending on possible clock sources: AHB clock or PLL clock.
202 * See commented example code below that can be copied and uncommented
203 * into HAL_ADC_MspInit().
204 * @note Possibility to update parameters on the fly:
205 * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
206 * coming from ADC state reset. Following calls to this function can
207 * be used to reconfigure some parameters of ADC_InitTypeDef
208 * structure on the fly, without modifying MSP configuration. If ADC
209 * MSP has to be modified again, HAL_ADC_DeInit() must be called
210 * before HAL_ADC_Init().
211 * The setting of these parameters is conditioned by ADC state.
212 * For parameters constraints, see comments of structure
213 * "ADC_InitTypeDef".
214 * @note This function configures the ADC within 2 scopes: scope of entire
215 * ADC and scope of regular group. For parameters details, see comments
216 * of structure "ADC_InitTypeDef".
217 * @note For devices with several ADCs: parameters related to common ADC
218 * registers (ADC clock mode) are set only if all ADCs sharing the
219 * same common group are disabled.
220 * If this is not the case, these common parameters setting are
221 * bypassed without error reporting: it can be the intended behaviour in
222 * case of update of a parameter of ADC_InitTypeDef on the fly,
223 * without disabling the other ADCs sharing the same common group.
224 * @param hadc ADC handle
225 * @retval HAL status
226 */
HAL_ADC_Init(ADC_HandleTypeDef * hadc)227 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
228 {
229 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
230 ADC_Common_TypeDef *tmpADC_Common;
231 ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
232 uint32_t tmpCFGR = 0U;
233 __IO uint32_t wait_loop_index = 0U;
234
235 /* Check ADC handle */
236 if(hadc == NULL)
237 {
238 return HAL_ERROR;
239 }
240
241 /* Check the parameters */
242 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
243 assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
244 assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
245 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
246 assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
247 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
248 assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
249 assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
250 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
251 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
252 assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
253 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
254
255 if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
256 {
257 assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
258 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
259 if(hadc->Init.DiscontinuousConvMode != DISABLE)
260 {
261 assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
262 }
263 }
264
265 /* Configuration of ADC core parameters and ADC MSP related parameters */
266 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
267 {
268 /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */
269 /* at RCC top level. */
270 /* Refer to header of this file for more details on clock enabling */
271 /* procedure. */
272
273 /* Actions performed only if ADC is coming from state reset: */
274 /* - Initialization of ADC MSP */
275 /* - ADC voltage regulator enable */
276 if (hadc->State == HAL_ADC_STATE_RESET)
277 {
278 /* Initialize ADC error code */
279 ADC_CLEAR_ERRORCODE(hadc);
280
281 /* Initialize HAL ADC API internal variables */
282 hadc->InjectionConfig.ChannelCount = 0U;
283 hadc->InjectionConfig.ContextQueue = 0U;
284
285 /* Allocate lock resource and initialize it */
286 hadc->Lock = HAL_UNLOCKED;
287
288 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
289 /* Init the ADC Callback settings */
290 hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */
291 hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
292 hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
293 hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
294 hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */
295
296 if (hadc->MspInitCallback == NULL)
297 {
298 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
299 }
300
301 /* Init the low level hardware */
302 hadc->MspInitCallback(hadc);
303 #else
304 /* Init the low level hardware */
305 HAL_ADC_MspInit(hadc);
306 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
307
308 /* Enable voltage regulator (if disabled at this step) */
309 if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0))
310 {
311 /* Note: The software must wait for the startup time of the ADC */
312 /* voltage regulator before launching a calibration or */
313 /* enabling the ADC. This temporization must be implemented by */
314 /* software and is equal to 10 us in the worst case */
315 /* process/temperature/power supply. */
316
317 /* Disable the ADC (if not already disabled) */
318 tmp_hal_status = ADC_Disable(hadc);
319
320 /* Check if ADC is effectively disabled */
321 /* Configuration of ADC parameters if previous preliminary actions */
322 /* are correctly completed. */
323 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
324 (tmp_hal_status == HAL_OK) )
325 {
326 /* Set ADC state */
327 ADC_STATE_CLR_SET(hadc->State,
328 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
329 HAL_ADC_STATE_BUSY_INTERNAL);
330
331 /* Set the intermediate state before moving the ADC voltage */
332 /* regulator to state enable. */
333 CLEAR_BIT(hadc->Instance->CR, (ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0));
334 /* Set ADVREGEN bits to 0x01U */
335 SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_0);
336
337 /* Delay for ADC stabilization time. */
338 /* Compute number of CPU cycles to wait for */
339 wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
340 while(wait_loop_index != 0U)
341 {
342 wait_loop_index--;
343 }
344 }
345 }
346 }
347
348 /* Verification that ADC voltage regulator is correctly enabled, whether */
349 /* or not ADC is coming from state reset (if any potential problem of */
350 /* clocking, voltage regulator would not be enabled). */
351 if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0) ||
352 HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADVREGEN_1) )
353 {
354 /* Update ADC state machine to error */
355 ADC_STATE_CLR_SET(hadc->State,
356 HAL_ADC_STATE_BUSY_INTERNAL,
357 HAL_ADC_STATE_ERROR_INTERNAL);
358
359 /* Set ADC error code to ADC IP internal error */
360 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
361
362 tmp_hal_status = HAL_ERROR;
363 }
364 }
365
366
367 /* Configuration of ADC parameters if previous preliminary actions are */
368 /* correctly completed and if there is no conversion on going on regular */
369 /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
370 /* called to update a parameter on the fly). */
371 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
372 (tmp_hal_status == HAL_OK) &&
373 (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) )
374 {
375 /* Set ADC state */
376 ADC_STATE_CLR_SET(hadc->State,
377 HAL_ADC_STATE_REG_BUSY,
378 HAL_ADC_STATE_BUSY_INTERNAL);
379
380 /* Configuration of common ADC parameters */
381
382 /* Pointer to the common control register to which is belonging hadc */
383 /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
384 /* control registers) */
385 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
386
387 /* Set handle of the other ADC sharing the same common register */
388 ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
389
390
391 /* Parameters update conditioned to ADC state: */
392 /* Parameters that can be updated only when ADC is disabled: */
393 /* - Multimode clock configuration */
394 if ((ADC_IS_ENABLE(hadc) == RESET) &&
395 ((tmphadcSharingSameCommonRegister.Instance == NULL) ||
396 (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) )
397 {
398 /* Reset configuration of ADC common register CCR: */
399 /* - ADC clock mode: CKMODE */
400 /* Some parameters of this register are not reset, since they are set */
401 /* by other functions and must be kept in case of usage of this */
402 /* function on the fly (update of a parameter of ADC_InitTypeDef */
403 /* without needing to reconfigure all other ADC groups/channels */
404 /* parameters): */
405 /* - multimode related parameters: MDMA, DMACFG, DELAY, MULTI (set */
406 /* into HAL_ADCEx_MultiModeConfigChannel() ) */
407 /* - internal measurement paths: Vbat, temperature sensor, Vref */
408 /* (set into HAL_ADC_ConfigChannel() or */
409 /* HAL_ADCEx_InjectedConfigChannel() ) */
410
411 MODIFY_REG(tmpADC_Common->CCR ,
412 ADC_CCR_CKMODE ,
413 hadc->Init.ClockPrescaler );
414 }
415
416
417 /* Configuration of ADC: */
418 /* - resolution */
419 /* - data alignment */
420 /* - external trigger to start conversion */
421 /* - external trigger polarity */
422 /* - continuous conversion mode */
423 /* - overrun */
424 /* - discontinuous mode */
425 SET_BIT(tmpCFGR, ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
426 ADC_CFGR_OVERRUN(hadc->Init.Overrun) |
427 hadc->Init.DataAlign |
428 hadc->Init.Resolution );
429
430 /* Enable discontinuous mode only if continuous mode is disabled */
431 if (hadc->Init.DiscontinuousConvMode == ENABLE)
432 {
433 if (hadc->Init.ContinuousConvMode == DISABLE)
434 {
435 /* Enable the selected ADC regular discontinuous mode */
436 /* Set the number of channels to be converted in discontinuous mode */
437 SET_BIT(tmpCFGR, ADC_CFGR_DISCEN |
438 ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) );
439 }
440 else
441 {
442 /* ADC regular group discontinuous was intended to be enabled, */
443 /* but ADC regular group modes continuous and sequencer discontinuous */
444 /* cannot be enabled simultaneously. */
445
446 /* Update ADC state machine to error */
447 ADC_STATE_CLR_SET(hadc->State,
448 HAL_ADC_STATE_BUSY_INTERNAL,
449 HAL_ADC_STATE_ERROR_CONFIG);
450
451 /* Set ADC error code to ADC IP internal error */
452 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
453 }
454 }
455
456 /* Enable external trigger if trigger selection is different of software */
457 /* start. */
458 /* Note: This configuration keeps the hardware feature of parameter */
459 /* ExternalTrigConvEdge "trigger edge none" equivalent to */
460 /* software start. */
461 if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
462 {
463 SET_BIT(tmpCFGR, ADC_CFGR_EXTSEL_SET(hadc, hadc->Init.ExternalTrigConv) |
464 hadc->Init.ExternalTrigConvEdge );
465 }
466
467 /* Parameters update conditioned to ADC state: */
468 /* Parameters that can be updated when ADC is disabled or enabled without */
469 /* conversion on going on regular and injected groups: */
470 /* - DMA continuous request */
471 /* - LowPowerAutoWait feature */
472 if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
473 {
474 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AUTDLY |
475 ADC_CFGR_DMACFG );
476
477 SET_BIT(tmpCFGR, ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
478 ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) );
479 }
480
481 /* Update ADC configuration register with previous settings */
482 MODIFY_REG(hadc->Instance->CFGR,
483 ADC_CFGR_DISCNUM |
484 ADC_CFGR_DISCEN |
485 ADC_CFGR_CONT |
486 ADC_CFGR_OVRMOD |
487 ADC_CFGR_EXTSEL |
488 ADC_CFGR_EXTEN |
489 ADC_CFGR_ALIGN |
490 ADC_CFGR_RES ,
491 tmpCFGR );
492
493
494 /* Configuration of regular group sequencer: */
495 /* - if scan mode is disabled, regular channels sequence length is set to */
496 /* 0x00: 1 channel converted (channel on regular rank 1U) */
497 /* Parameter "NbrOfConversion" is discarded. */
498 /* Note: Scan mode is not present by hardware on this device, but */
499 /* emulated by software for alignment over all STM32 devices. */
500 /* - if scan mode is enabled, regular channels sequence length is set to */
501 /* parameter "NbrOfConversion" */
502 if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
503 {
504 /* Set number of ranks in regular group sequencer */
505 MODIFY_REG(hadc->Instance->SQR1 ,
506 ADC_SQR1_L ,
507 (hadc->Init.NbrOfConversion - (uint8_t)1U) );
508 }
509 else
510 {
511 CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
512 }
513
514 /* Set ADC error code to none */
515 ADC_CLEAR_ERRORCODE(hadc);
516
517 /* Set the ADC state */
518 ADC_STATE_CLR_SET(hadc->State,
519 HAL_ADC_STATE_BUSY_INTERNAL,
520 HAL_ADC_STATE_READY);
521 }
522 else
523 {
524 /* Update ADC state machine to error */
525 ADC_STATE_CLR_SET(hadc->State,
526 HAL_ADC_STATE_BUSY_INTERNAL,
527 HAL_ADC_STATE_ERROR_INTERNAL);
528
529 tmp_hal_status = HAL_ERROR;
530 }
531
532
533 /* Return function status */
534 return tmp_hal_status;
535 }
536 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
537 /* STM32F302xC || STM32F303xC || STM32F358xx || */
538 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
539 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
540
541 #if defined(STM32F373xC) || defined(STM32F378xx)
542 /**
543 * @brief Initializes the ADC peripheral and regular group according to
544 * parameters specified in structure "ADC_InitTypeDef".
545 * @note As prerequisite, ADC clock must be configured at RCC top level
546 * (clock source APB2).
547 * See commented example code below that can be copied and uncommented
548 * into HAL_ADC_MspInit().
549 * @note Possibility to update parameters on the fly:
550 * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
551 * coming from ADC state reset. Following calls to this function can
552 * be used to reconfigure some parameters of ADC_InitTypeDef
553 * structure on the fly, without modifying MSP configuration. If ADC
554 * MSP has to be modified again, HAL_ADC_DeInit() must be called
555 * before HAL_ADC_Init().
556 * The setting of these parameters is conditioned to ADC state.
557 * For parameters constraints, see comments of structure
558 * "ADC_InitTypeDef".
559 * @note This function configures the ADC within 2 scopes: scope of entire
560 * ADC and scope of regular group. For parameters details, see comments
561 * of structure "ADC_InitTypeDef".
562 * @param hadc ADC handle
563 * @retval HAL status
564 */
HAL_ADC_Init(ADC_HandleTypeDef * hadc)565 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
566 {
567 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
568 uint32_t tmp_cr1 = 0U;
569 uint32_t tmp_cr2 = 0U;
570 uint32_t tmp_sqr1 = 0U;
571
572 /* Check ADC handle */
573 if(hadc == NULL)
574 {
575 return HAL_ERROR;
576 }
577
578 /* Check the parameters */
579 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
580 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
581 assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
582 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
583 assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
584
585 if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
586 {
587 assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
588 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
589 if(hadc->Init.DiscontinuousConvMode != DISABLE)
590 {
591 assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
592 }
593 }
594
595 /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */
596 /* at RCC top level. */
597 /* Refer to header of this file for more details on clock enabling */
598 /* procedure. */
599
600 /* Actions performed only if ADC is coming from state reset: */
601 /* - Initialization of ADC MSP */
602 if (hadc->State == HAL_ADC_STATE_RESET)
603 {
604 /* Initialize ADC error code */
605 ADC_CLEAR_ERRORCODE(hadc);
606
607 /* Allocate lock resource and initialize it */
608 hadc->Lock = HAL_UNLOCKED;
609
610 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
611 /* Init the ADC Callback settings */
612 hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */
613 hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
614 hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
615 hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
616 hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */
617
618 if (hadc->MspInitCallback == NULL)
619 {
620 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
621 }
622
623 /* Init the low level hardware */
624 hadc->MspInitCallback(hadc);
625 #else
626 /* Init the low level hardware */
627 HAL_ADC_MspInit(hadc);
628 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
629 }
630
631 /* Stop potential conversion on going, on regular and injected groups */
632 /* Disable ADC peripheral */
633 /* Note: In case of ADC already enabled, precaution to not launch an */
634 /* unwanted conversion while modifying register CR2 by writing 1 to */
635 /* bit ADON. */
636 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
637
638
639 /* Configuration of ADC parameters if previous preliminary actions are */
640 /* correctly completed. */
641 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
642 (tmp_hal_status == HAL_OK) )
643 {
644 /* Set ADC state */
645 ADC_STATE_CLR_SET(hadc->State,
646 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
647 HAL_ADC_STATE_BUSY_INTERNAL);
648
649 /* Set ADC parameters */
650
651 /* Configuration of ADC: */
652 /* - data alignment */
653 /* - external trigger to start conversion */
654 /* - external trigger polarity (always set to 1U, because needed for all */
655 /* triggers: external trigger of SW start) */
656 /* - continuous conversion mode */
657 /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */
658 /* HAL_ADC_Start_xxx functions because if set in this function, */
659 /* a conversion on injected group would start a conversion also on */
660 /* regular group after ADC enabling. */
661 tmp_cr2 |= (hadc->Init.DataAlign |
662 hadc->Init.ExternalTrigConv |
663 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) );
664
665 /* Configuration of ADC: */
666 /* - scan mode */
667 /* - discontinuous mode disable/enable */
668 /* - discontinuous mode number of conversions */
669 tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
670
671 /* Enable discontinuous mode only if continuous mode is disabled */
672 /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */
673 /* discontinuous is set anyway, but will have no effect on ADC HW. */
674 if (hadc->Init.DiscontinuousConvMode == ENABLE)
675 {
676 if (hadc->Init.ContinuousConvMode == DISABLE)
677 {
678 /* Enable the selected ADC regular discontinuous mode */
679 /* Set the number of channels to be converted in discontinuous mode */
680 tmp_cr1 |= (ADC_CR1_DISCEN |
681 ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) );
682 }
683 else
684 {
685 /* ADC regular group discontinuous was intended to be enabled, */
686 /* but ADC regular group modes continuous and sequencer discontinuous */
687 /* cannot be enabled simultaneously. */
688
689 /* Update ADC state machine to error */
690 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
691
692 /* Set ADC error code to ADC IP internal error */
693 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
694 }
695 }
696
697 /* Update ADC configuration register CR1 with previous settings */
698 MODIFY_REG(hadc->Instance->CR1,
699 ADC_CR1_SCAN |
700 ADC_CR1_DISCEN |
701 ADC_CR1_DISCNUM ,
702 tmp_cr1 );
703
704 /* Update ADC configuration register CR2 with previous settings */
705 MODIFY_REG(hadc->Instance->CR2,
706 ADC_CR2_ALIGN |
707 ADC_CR2_EXTSEL |
708 ADC_CR2_EXTTRIG |
709 ADC_CR2_CONT ,
710 tmp_cr2 );
711
712 /* Configuration of regular group sequencer: */
713 /* - if scan mode is disabled, regular channels sequence length is set to */
714 /* 0x00: 1 channel converted (channel on regular rank 1U) */
715 /* Parameter "NbrOfConversion" is discarded. */
716 /* Note: Scan mode is present by hardware on this device and, if */
717 /* disabled, discards automatically nb of conversions. Anyway, nb of */
718 /* conversions is forced to 0x00 for alignment over all STM32 devices. */
719 /* - if scan mode is enabled, regular channels sequence length is set to */
720 /* parameter "NbrOfConversion" */
721 if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
722 {
723 tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
724 }
725
726 MODIFY_REG(hadc->Instance->SQR1,
727 ADC_SQR1_L ,
728 tmp_sqr1 );
729
730 /* Check back that ADC registers have effectively been configured to */
731 /* ensure of no potential problem of ADC core IP clocking. */
732 /* Check through register CR2 (excluding bits set in other functions: */
733 /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */
734 /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */
735 /* measurement path bit (TSVREFE). */
736 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
737 ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
738 ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL |
739 ADC_CR2_TSVREFE ))
740 == tmp_cr2)
741 {
742 /* Set ADC error code to none */
743 ADC_CLEAR_ERRORCODE(hadc);
744
745 /* Set the ADC state */
746 ADC_STATE_CLR_SET(hadc->State,
747 HAL_ADC_STATE_BUSY_INTERNAL,
748 HAL_ADC_STATE_READY);
749 }
750 else
751 {
752 /* Update ADC state machine to error */
753 ADC_STATE_CLR_SET(hadc->State,
754 HAL_ADC_STATE_BUSY_INTERNAL,
755 HAL_ADC_STATE_ERROR_INTERNAL);
756
757 /* Set ADC error code to ADC IP internal error */
758 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
759
760 tmp_hal_status = HAL_ERROR;
761 }
762
763 }
764 else
765 {
766 /* Update ADC state machine to error */
767 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
768
769 tmp_hal_status = HAL_ERROR;
770 }
771
772 /* Return function status */
773 return tmp_hal_status;
774 }
775 #endif /* STM32F373xC || STM32F378xx */
776
777 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
778 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
779 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
780 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
781 /**
782 * @brief Deinitialize the ADC peripheral registers to their default reset
783 * values, with deinitialization of the ADC MSP.
784 * @note For devices with several ADCs: reset of ADC common registers is done
785 * only if all ADCs sharing the same common group are disabled.
786 * If this is not the case, reset of these common parameters reset is
787 * bypassed without error reporting: it can be the intended behaviour in
788 * case of reset of a single ADC while the other ADCs sharing the same
789 * common group is still running.
790 * @note For devices with several ADCs: Global reset of all ADCs sharing a
791 * common group is possible.
792 * As this function is intended to reset a single ADC, to not impact
793 * other ADCs, instructions for global reset of multiple ADCs have been
794 * let commented below.
795 * If needed, the example code can be copied and uncommented into
796 * function HAL_ADC_MspDeInit().
797 * @param hadc ADC handle
798 * @retval HAL status
799 */
HAL_ADC_DeInit(ADC_HandleTypeDef * hadc)800 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
801 {
802 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
803 ADC_Common_TypeDef *tmpADC_Common;
804 ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
805
806 /* Check ADC handle */
807 if(hadc == NULL)
808 {
809 return HAL_ERROR;
810 }
811
812 /* Check the parameters */
813 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
814
815 /* Set ADC state */
816 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
817
818 /* Stop potential conversion on going, on regular and injected groups */
819 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
820
821 /* Disable ADC peripheral if conversions are effectively stopped */
822 if (tmp_hal_status == HAL_OK)
823 {
824 /* Flush register JSQR: queue sequencer reset when injected queue */
825 /* sequencer is enabled and ADC disabled. */
826 /* Enable injected queue sequencer after injected conversion stop */
827 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
828
829 /* Disable the ADC peripheral */
830 tmp_hal_status = ADC_Disable(hadc);
831
832 /* Check if ADC is effectively disabled */
833 if (tmp_hal_status == HAL_OK)
834 {
835 /* Change ADC state */
836 hadc->State = HAL_ADC_STATE_READY;
837 }
838 else
839 {
840 tmp_hal_status = HAL_ERROR;
841 }
842 }
843
844
845 /* Configuration of ADC parameters if previous preliminary actions are */
846 /* correctly completed. */
847 if (tmp_hal_status == HAL_OK)
848 {
849 /* ========== Reset ADC registers ========== */
850 /* Reset register IER */
851 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 |
852 ADC_IT_JQOVF | ADC_IT_OVR |
853 ADC_IT_JEOS | ADC_IT_JEOC |
854 ADC_IT_EOS | ADC_IT_EOC |
855 ADC_IT_EOSMP | ADC_IT_RDY ) );
856
857 /* Reset register ISR */
858 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
859 ADC_FLAG_JQOVF | ADC_FLAG_OVR |
860 ADC_FLAG_JEOS | ADC_FLAG_JEOC |
861 ADC_FLAG_EOS | ADC_FLAG_EOC |
862 ADC_FLAG_EOSMP | ADC_FLAG_RDY ) );
863
864 /* Reset register CR */
865 /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART are */
866 /* in access mode "read-set": no direct reset applicable. */
867 /* Reset Calibration mode to default setting (single ended): */
868 /* Disable voltage regulator: */
869 /* Note: Voltage regulator disable is conditioned to ADC state disabled: */
870 /* already done above. */
871 /* Note: Voltage regulator disable is intended for power saving. */
872 /* Sequence to disable voltage regulator: */
873 /* 1. Set the intermediate state before moving the ADC voltage regulator */
874 /* to disable state. */
875 CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0 | ADC_CR_ADCALDIF);
876 /* 2. Set ADVREGEN bits to 0x10U */
877 SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_1);
878
879 /* Reset register CFGR */
880 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |
881 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |
882 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |
883 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |
884 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |
885 ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN );
886
887 /* Reset register SMPR1 */
888 CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |
889 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |
890 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 );
891
892 /* Reset register SMPR2 */
893 CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
894 ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
895 ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10 );
896
897 /* Reset register TR1 */
898 CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 | ADC_TR1_LT1);
899
900 /* Reset register TR2 */
901 CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2);
902
903 /* Reset register TR3 */
904 CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3);
905
906 /* Reset register SQR1 */
907 CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
908 ADC_SQR1_SQ1 | ADC_SQR1_L);
909
910 /* Reset register SQR2 */
911 CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
912 ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
913
914 /* Reset register SQR3 */
915 CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
916 ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
917
918 /* Reset register SQR4 */
919 CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
920
921 /* Reset register DR */
922 /* bits in access mode read only, no direct reset applicable*/
923
924 /* Reset register OFR1 */
925 CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
926 /* Reset register OFR2 */
927 CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
928 /* Reset register OFR3 */
929 CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
930 /* Reset register OFR4 */
931 CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
932
933 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
934 /* bits in access mode read only, no direct reset applicable*/
935
936 /* Reset register AWD2CR */
937 CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
938
939 /* Reset register AWD3CR */
940 CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
941
942 /* Reset register DIFSEL */
943 CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
944
945 /* Reset register CALFACT */
946 CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
947
948
949
950
951
952
953 /* ========== Reset common ADC registers ========== */
954
955 /* Pointer to the common control register to which is belonging hadc */
956 /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
957 /* control registers) */
958 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
959
960 /* Set handle of the other ADC sharing the same common register */
961 ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
962
963 /* Software is allowed to change common parameters only when all ADCs of */
964 /* the common group are disabled. */
965 if ((ADC_IS_ENABLE(hadc) == RESET) &&
966 ( (tmphadcSharingSameCommonRegister.Instance == NULL) ||
967 (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) )
968 {
969 /* Reset configuration of ADC common register CCR:
970 - clock mode: CKMODE
971 - multimode related parameters: MDMA, DMACFG, DELAY, MULTI (set into
972 HAL_ADCEx_MultiModeConfigChannel() )
973 - internal measurement paths: Vbat, temperature sensor, Vref (set into
974 HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
975 */
976 CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_CKMODE |
977 ADC_CCR_VBATEN |
978 ADC_CCR_TSEN |
979 ADC_CCR_VREFEN |
980 ADC_CCR_MDMA |
981 ADC_CCR_DMACFG |
982 ADC_CCR_DELAY |
983 ADC_CCR_MULTI );
984
985 /* Other ADC common registers (CSR, CDR) are in access mode read only,
986 no direct reset applicable */
987 }
988
989
990 /* ========== Hard reset and clock disable of ADC peripheral ========== */
991 /* Into HAL_ADC_MspDeInit(), ADC clock can be hard reset and disabled */
992 /* at RCC top level. */
993 /* Refer to header of this file for more details on clock disabling */
994 /* procedure. */
995
996
997 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
998 if (hadc->MspDeInitCallback == NULL)
999 {
1000 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
1001 }
1002
1003 /* DeInit the low level hardware */
1004 hadc->MspDeInitCallback(hadc);
1005 #else
1006 /* DeInit the low level hardware */
1007 HAL_ADC_MspDeInit(hadc);
1008 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1009
1010 /* Set ADC error code to none */
1011 ADC_CLEAR_ERRORCODE(hadc);
1012
1013 /* Set ADC state */
1014 hadc->State = HAL_ADC_STATE_RESET;
1015 }
1016
1017 /* Process unlocked */
1018 __HAL_UNLOCK(hadc);
1019
1020
1021 /* Return function status */
1022 return tmp_hal_status;
1023 }
1024 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
1025 /* STM32F302xC || STM32F303xC || STM32F358xx || */
1026 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
1027 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
1028
1029 #if defined(STM32F373xC) || defined(STM32F378xx)
1030 /**
1031 * @brief Deinitialize the ADC peripheral registers to its default reset values.
1032 * @param hadc ADC handle
1033 * @retval HAL status
1034 */
HAL_ADC_DeInit(ADC_HandleTypeDef * hadc)1035 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
1036 {
1037 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1038
1039 /* Check ADC handle */
1040 if(hadc == NULL)
1041 {
1042 return HAL_ERROR;
1043 }
1044
1045 /* Check the parameters */
1046 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1047
1048 /* Set ADC state */
1049 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
1050
1051 /* Stop potential conversion on going, on regular and injected groups */
1052 /* Disable ADC peripheral */
1053 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
1054
1055
1056 /* Configuration of ADC parameters if previous preliminary actions are */
1057 /* correctly completed. */
1058 if (tmp_hal_status == HAL_OK)
1059 {
1060 /* ========== Reset ADC registers ========== */
1061 /* Reset register SR */
1062 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC |
1063 ADC_FLAG_JSTRT | ADC_FLAG_STRT));
1064
1065 /* Reset register CR1 */
1066 CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM |
1067 ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO |
1068 ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE |
1069 ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_AWDCH ));
1070
1071 /* Reset register CR2 */
1072 CLEAR_BIT(hadc->Instance->CR2, (ADC_CR2_TSVREFE | ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
1073 ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL | ADC_CR2_JEXTTRIG |
1074 ADC_CR2_JEXTSEL | ADC_CR2_ALIGN | ADC_CR2_DMA |
1075 ADC_CR2_RSTCAL | ADC_CR2_CAL | ADC_CR2_CONT |
1076 ADC_CR2_ADON ));
1077
1078 /* Reset register SMPR1 */
1079 CLEAR_BIT(hadc->Instance->SMPR1, (ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP15 |
1080 ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 |
1081 ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10 ));
1082
1083 /* Reset register SMPR2 */
1084 CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP9 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 |
1085 ADC_SMPR2_SMP6 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 |
1086 ADC_SMPR2_SMP3 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 |
1087 ADC_SMPR2_SMP0 ));
1088
1089 /* Reset register JOFR1 */
1090 CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1);
1091 /* Reset register JOFR2 */
1092 CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2);
1093 /* Reset register JOFR3 */
1094 CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3);
1095 /* Reset register JOFR4 */
1096 CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4);
1097
1098 /* Reset register HTR */
1099 CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT);
1100 /* Reset register LTR */
1101 CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT);
1102
1103 /* Reset register SQR1 */
1104 CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L |
1105 ADC_SQR1_SQ16 | ADC_SQR1_SQ15 |
1106 ADC_SQR1_SQ14 | ADC_SQR1_SQ13 );
1107
1108 /* Reset register SQR1 */
1109 CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L |
1110 ADC_SQR1_SQ16 | ADC_SQR1_SQ15 |
1111 ADC_SQR1_SQ14 | ADC_SQR1_SQ13 );
1112
1113 /* Reset register SQR2 */
1114 CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 |
1115 ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 );
1116
1117 /* Reset register SQR3 */
1118 CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 |
1119 ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1 );
1120
1121 /* Reset register JSQR */
1122 CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL |
1123 ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
1124 ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 );
1125
1126 /* Reset register JSQR */
1127 CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL |
1128 ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
1129 ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 );
1130
1131 /* Reset register DR */
1132 /* bits in access mode read only, no direct reset applicable*/
1133
1134 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
1135 /* bits in access mode read only, no direct reset applicable*/
1136
1137 /* Reset VBAT measurement path, in case of enabled before by selecting */
1138 /* channel ADC_CHANNEL_VBAT. */
1139 SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT);
1140
1141
1142 /* ========== Hard reset ADC peripheral ========== */
1143 /* Performs a global reset of the entire ADC peripheral: ADC state is */
1144 /* forced to a similar state after device power-on. */
1145 /* If needed, copy-paste and uncomment the following reset code into */
1146 /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */
1147 /* */
1148 /* __HAL_RCC_ADC1_FORCE_RESET() */
1149 /* __HAL_RCC_ADC1_RELEASE_RESET() */
1150
1151 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1152 if (hadc->MspDeInitCallback == NULL)
1153 {
1154 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
1155 }
1156
1157 /* DeInit the low level hardware */
1158 hadc->MspDeInitCallback(hadc);
1159 #else
1160 /* DeInit the low level hardware */
1161 HAL_ADC_MspDeInit(hadc);
1162 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1163
1164 /* Set ADC error code to none */
1165 ADC_CLEAR_ERRORCODE(hadc);
1166
1167 /* Set ADC state */
1168 hadc->State = HAL_ADC_STATE_RESET;
1169
1170 }
1171
1172 /* Process unlocked */
1173 __HAL_UNLOCK(hadc);
1174
1175 /* Return function status */
1176 return tmp_hal_status;
1177 }
1178 #endif /* STM32F373xC || STM32F378xx */
1179
1180 /**
1181 * @}
1182 */
1183
1184 /** @defgroup ADCEx_Exported_Functions_Group2 ADCEx Input and Output operation functions
1185 * @brief ADC Extended IO operation functions
1186 *
1187 @verbatim
1188 ===============================================================================
1189 ##### IO operation functions #####
1190 ===============================================================================
1191 [..] This section provides functions allowing to:
1192 (+) Start conversion of regular group.
1193 (+) Stop conversion of regular group.
1194 (+) Poll for conversion complete on regular group.
1195 (+) Poll for conversion event.
1196 (+) Get result of regular channel conversion.
1197 (+) Start conversion of regular group and enable interruptions.
1198 (+) Stop conversion of regular group and disable interruptions.
1199 (+) Handle ADC interrupt request
1200 (+) Start conversion of regular group and enable DMA transfer.
1201 (+) Stop conversion of regular group and disable ADC DMA transfer.
1202
1203 (+) Start conversion of injected group.
1204 (+) Stop conversion of injected group.
1205 (+) Poll for conversion complete on injected group.
1206 (+) Get result of injected channel conversion.
1207 (+) Start conversion of injected group and enable interruptions.
1208 (+) Stop conversion of injected group and disable interruptions.
1209
1210 (+) Start multimode and enable DMA transfer.
1211 (+) Stop multimode and disable ADC DMA transfer.
1212 (+) Get result of multimode conversion.
1213
1214 (+) Perform the ADC self-calibration for single or differential ending.
1215 (+) Get calibration factors for single or differential ending.
1216 (+) Set calibration factors for single or differential ending.
1217
1218 @endverbatim
1219 * @{
1220 */
1221
1222 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
1223 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
1224 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
1225 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
1226 /**
1227 * @brief Enables ADC, starts conversion of regular group.
1228 * Interruptions enabled in this function: None.
1229 * @note Case of multimode enabled (for devices with several ADCs):
1230 * if ADC is slave, ADC is enabled only (conversion is not started).
1231 * if ADC is master, ADC is enabled and multimode conversion is started.
1232 * @param hadc ADC handle
1233 * @retval HAL status
1234 */
HAL_ADC_Start(ADC_HandleTypeDef * hadc)1235 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
1236 {
1237 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1238
1239 /* Check the parameters */
1240 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1241
1242 /* Perform ADC enable and conversion start if no conversion is on going */
1243 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
1244 {
1245 /* Process locked */
1246 __HAL_LOCK(hadc);
1247
1248 /* Enable the ADC peripheral */
1249 tmp_hal_status = ADC_Enable(hadc);
1250
1251 /* Start conversion if ADC is effectively enabled */
1252 if (tmp_hal_status == HAL_OK)
1253 {
1254 /* Set ADC state */
1255 /* - Clear state bitfield related to regular group conversion results */
1256 /* - Set state bitfield related to regular operation */
1257 ADC_STATE_CLR_SET(hadc->State,
1258 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
1259 HAL_ADC_STATE_REG_BUSY);
1260
1261 /* Set group injected state (from auto-injection) and multimode state */
1262 /* for all cases of multimode: independent mode, multimode ADC master */
1263 /* or multimode ADC slave (for devices with several ADCs): */
1264 if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
1265 {
1266 /* Set ADC state (ADC independent or master) */
1267 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
1268
1269 /* If conversions on group regular are also triggering group injected,*/
1270 /* update ADC state. */
1271 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
1272 {
1273 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1274 }
1275 }
1276 else
1277 {
1278 /* Set ADC state (ADC slave) */
1279 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
1280
1281 /* If conversions on group regular are also triggering group injected,*/
1282 /* update ADC state. */
1283 if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
1284 {
1285 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1286 }
1287 }
1288
1289 /* State machine update: Check if an injected conversion is ongoing */
1290 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1291 {
1292 /* Reset ADC error code fields related to conversions on group regular*/
1293 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
1294 }
1295 else
1296 {
1297 /* Reset ADC all error code fields */
1298 ADC_CLEAR_ERRORCODE(hadc);
1299 }
1300
1301 /* Process unlocked */
1302 /* Unlock before starting ADC conversions: in case of potential */
1303 /* interruption, to let the process to ADC IRQ Handler. */
1304 __HAL_UNLOCK(hadc);
1305
1306 /* Clear regular group conversion flag and overrun flag */
1307 /* (To ensure of no unknown state from potential previous ADC */
1308 /* operations) */
1309 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
1310
1311 /* Enable conversion of regular group. */
1312 /* If software start has been selected, conversion starts immediately. */
1313 /* If external trigger has been selected, conversion will start at next */
1314 /* trigger event. */
1315 /* Case of multimode enabled (for devices with several ADCs): */
1316 /* - if ADC is slave, ADC is enabled only (conversion is not started). */
1317 /* - if ADC is master, ADC is enabled and conversion is started. */
1318 if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc))
1319 {
1320 SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
1321 }
1322 }
1323 else
1324 {
1325 /* Process unlocked */
1326 __HAL_UNLOCK(hadc);
1327 }
1328 }
1329 else
1330 {
1331 tmp_hal_status = HAL_BUSY;
1332 }
1333
1334 /* Return function status */
1335 return tmp_hal_status;
1336 }
1337 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
1338 /* STM32F302xC || STM32F303xC || STM32F358xx || */
1339 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
1340 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
1341
1342 #if defined(STM32F373xC) || defined(STM32F378xx)
1343 /**
1344 * @brief Enables ADC, starts conversion of regular group.
1345 * Interruptions enabled in this function: None.
1346 * @param hadc ADC handle
1347 * @retval HAL status
1348 */
HAL_ADC_Start(ADC_HandleTypeDef * hadc)1349 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
1350 {
1351 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1352
1353 /* Check the parameters */
1354 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1355
1356 /* Process locked */
1357 __HAL_LOCK(hadc);
1358
1359 /* Enable the ADC peripheral */
1360 tmp_hal_status = ADC_Enable(hadc);
1361
1362 /* Start conversion if ADC is effectively enabled */
1363 if (tmp_hal_status == HAL_OK)
1364 {
1365 /* Set ADC state */
1366 /* - Clear state bitfield related to regular group conversion results */
1367 /* - Set state bitfield related to regular operation */
1368 ADC_STATE_CLR_SET(hadc->State,
1369 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC,
1370 HAL_ADC_STATE_REG_BUSY);
1371
1372 /* Set group injected state (from auto-injection) */
1373 /* If conversions on group regular are also triggering group injected, */
1374 /* update ADC state. */
1375 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
1376 {
1377 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1378 }
1379
1380 /* State machine update: Check if an injected conversion is ongoing */
1381 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1382 {
1383 /* Reset ADC error code fields related to conversions on group regular */
1384 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
1385 }
1386 else
1387 {
1388 /* Reset ADC all error code fields */
1389 ADC_CLEAR_ERRORCODE(hadc);
1390 }
1391
1392 /* Process unlocked */
1393 /* Unlock before starting ADC conversions: in case of potential */
1394 /* interruption, to let the process to ADC IRQ Handler. */
1395 __HAL_UNLOCK(hadc);
1396
1397 /* Clear regular group conversion flag and overrun flag */
1398 /* (To ensure of no unknown state from potential previous ADC operations) */
1399 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
1400
1401 /* Enable conversion of regular group. */
1402 /* If software start has been selected, conversion starts immediately. */
1403 /* If external trigger has been selected, conversion will start at next */
1404 /* trigger event. */
1405 /* Note: Alternate trigger for single conversion could be to force an */
1406 /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
1407 if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
1408 {
1409 /* Start ADC conversion on regular group with SW start */
1410 SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
1411 }
1412 else
1413 {
1414 /* Start ADC conversion on regular group with external trigger */
1415 SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
1416 }
1417 }
1418
1419 /* Return function status */
1420 return tmp_hal_status;
1421 }
1422 #endif /* STM32F373xC || STM32F378xx */
1423
1424 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
1425 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
1426 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
1427 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
1428 /**
1429 * @brief Stop ADC conversion of both groups regular and injected,
1430 * disable ADC peripheral.
1431 * @note ADC peripheral disable is forcing interruption of potential
1432 * conversion on injected group. If injected group is under use,
1433 * it should be preliminarily stopped using function
1434 * @ref HAL_ADCEx_InjectedStop().
1435 * To stop ADC conversion only on ADC group regular
1436 * while letting ADC group injected conversions running,
1437 * use function @ref HAL_ADCEx_RegularStop().
1438 * @param hadc ADC handle
1439 * @retval HAL status.
1440 */
HAL_ADC_Stop(ADC_HandleTypeDef * hadc)1441 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
1442 {
1443 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1444
1445 /* Check the parameters */
1446 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1447
1448 /* Process locked */
1449 __HAL_LOCK(hadc);
1450
1451 /* 1. Stop potential conversion on going, on regular and injected groups */
1452 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
1453
1454 /* Disable ADC peripheral if conversions are effectively stopped */
1455 if (tmp_hal_status == HAL_OK)
1456 {
1457 /* 2. Disable the ADC peripheral */
1458 tmp_hal_status = ADC_Disable(hadc);
1459
1460 /* Check if ADC is effectively disabled */
1461 if (tmp_hal_status == HAL_OK)
1462 {
1463 /* Set ADC state */
1464 ADC_STATE_CLR_SET(hadc->State,
1465 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1466 HAL_ADC_STATE_READY);
1467 }
1468 }
1469
1470 /* Process unlocked */
1471 __HAL_UNLOCK(hadc);
1472
1473 /* Return function status */
1474 return tmp_hal_status;
1475 }
1476 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
1477 /* STM32F302xC || STM32F303xC || STM32F358xx || */
1478 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
1479 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
1480
1481 #if defined(STM32F373xC) || defined(STM32F378xx)
1482 /**
1483 * @brief Stop ADC conversion of regular group (and injected channels in
1484 * case of auto_injection mode), disable ADC peripheral.
1485 * @note ADC peripheral disable is forcing interruption of potential
1486 * conversion on injected group. If injected group is under use, it
1487 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
1488 * @param hadc ADC handle
1489 * @retval HAL status.
1490 */
HAL_ADC_Stop(ADC_HandleTypeDef * hadc)1491 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
1492 {
1493 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1494
1495 /* Check the parameters */
1496 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1497
1498 /* Process locked */
1499 __HAL_LOCK(hadc);
1500
1501 /* Stop potential conversion on going, on regular and injected groups */
1502 /* Disable ADC peripheral */
1503 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
1504
1505 /* Check if ADC is effectively disabled */
1506 if (tmp_hal_status == HAL_OK)
1507 {
1508 /* Set ADC state */
1509 ADC_STATE_CLR_SET(hadc->State,
1510 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1511 HAL_ADC_STATE_READY);
1512 }
1513
1514 /* Process unlocked */
1515 __HAL_UNLOCK(hadc);
1516
1517 /* Return function status */
1518 return tmp_hal_status;
1519 }
1520 #endif /* STM32F373xC || STM32F378xx */
1521
1522 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
1523 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
1524 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
1525 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
1526 /**
1527 * @brief Wait for regular group conversion to be completed.
1528 * @note ADC conversion flags EOS (end of sequence) and EOC (end of
1529 * conversion) are cleared by this function, with an exception:
1530 * if low power feature "LowPowerAutoWait" is enabled, flags are
1531 * not cleared to not interfere with this feature until data register
1532 * is read using function HAL_ADC_GetValue().
1533 * @note This function cannot be used in a particular setup: ADC configured
1534 * in DMA mode and polling for end of each conversion (ADC init
1535 * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
1536 * In this case, DMA resets the flag EOC and polling cannot be
1537 * performed on each conversion. Nevertheless, polling can still
1538 * be performed on the complete sequence (ADC init
1539 * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
1540 * @param hadc ADC handle
1541 * @param Timeout Timeout value in millisecond.
1542 * @note Depending on init parameter "EOCSelection", flags EOS or EOC is
1543 * checked and cleared depending on autodelay status (bit AUTDLY).
1544 * @retval HAL status
1545 */
HAL_ADC_PollForConversion(ADC_HandleTypeDef * hadc,uint32_t Timeout)1546 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
1547 {
1548 uint32_t tickstart;
1549 uint32_t tmp_Flag_EOC;
1550 ADC_Common_TypeDef *tmpADC_Common;
1551 uint32_t tmp_cfgr = 0x0U;
1552
1553 /* Check the parameters */
1554 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1555
1556 /* If end of conversion selected to end of sequence */
1557 if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
1558 {
1559 tmp_Flag_EOC = ADC_FLAG_EOS;
1560 }
1561 /* If end of conversion selected to end of each conversion */
1562 else /* ADC_EOC_SINGLE_CONV */
1563 {
1564 /* Verification that ADC configuration is compliant with polling for */
1565 /* each conversion: */
1566 /* Particular case is ADC configured in DMA mode and ADC sequencer with */
1567 /* several ranks and polling for end of each conversion. */
1568 /* For code simplicity sake, this particular case is generalized to */
1569 /* ADC configured in DMA mode and and polling for end of each conversion. */
1570
1571 /* Pointer to the common control register to which is belonging hadc */
1572 /* (Depending on STM32F3 product, there may have up to 4 ADC and 2 common */
1573 /* control registers) */
1574 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
1575
1576 /* Check DMA configuration, depending on MultiMode set or not */
1577 if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI) == ADC_MODE_INDEPENDENT)
1578 {
1579 if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN))
1580 {
1581 /* Update ADC state machine to error */
1582 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1583
1584 /* Process unlocked */
1585 __HAL_UNLOCK(hadc);
1586
1587 return HAL_ERROR;
1588 }
1589 }
1590 else
1591 {
1592 /* MultiMode is enabled, Common Control Register MDMA bits must be checked */
1593 if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA) != RESET)
1594 {
1595 /* Update ADC state machine to error */
1596 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1597
1598 /* Process unlocked */
1599 __HAL_UNLOCK(hadc);
1600
1601 return HAL_ERROR;
1602 }
1603 }
1604
1605 tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS);
1606
1607 }
1608
1609 /* Get relevant register CFGR in ADC instance of ADC master or slave */
1610 /* in function of multimode state (for devices with multimode */
1611 /* available). */
1612 if(ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
1613 {
1614 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
1615 }
1616 else
1617 {
1618 tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
1619 }
1620
1621 /* Get tick count */
1622 tickstart = HAL_GetTick();
1623
1624 /* Wait until End of Conversion or End of Sequence flag is raised */
1625 while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
1626 {
1627 /* Check if timeout is disabled (set to infinite wait) */
1628 if(Timeout != HAL_MAX_DELAY)
1629 {
1630 if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
1631 {
1632 /* New check to avoid false timeout detection in case of preemption */
1633 if(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
1634 {
1635 /* Update ADC state machine to timeout */
1636 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
1637
1638 /* Process unlocked */
1639 __HAL_UNLOCK(hadc);
1640
1641 return HAL_TIMEOUT;
1642 }
1643 }
1644 }
1645 }
1646
1647 /* Update ADC state machine */
1648 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
1649
1650 /* Determine whether any further conversion upcoming on group regular */
1651 /* by external trigger, continuous mode or scan sequence on going. */
1652 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
1653 (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) )
1654 {
1655 /* If End of Sequence is reached, disable interrupts */
1656 if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
1657 {
1658 /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
1659 /* ADSTART==0 (no conversion on going) */
1660 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
1661 {
1662 /* Set ADC state */
1663 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1664
1665 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1666 {
1667 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
1668 }
1669 }
1670 else
1671 {
1672 /* Change ADC state to error state */
1673 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1674
1675 /* Set ADC error code to ADC IP internal error */
1676 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
1677 }
1678 }
1679 }
1680
1681 /* Clear end of conversion flag of regular group if low power feature */
1682 /* "LowPowerAutoWait " is disabled, to not interfere with this feature */
1683 /* until data register is read using function HAL_ADC_GetValue(). */
1684 if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET)
1685 {
1686 /* Clear regular group conversion flag */
1687 /* (EOC or EOS depending on HAL ADC initialization parameter) */
1688 __HAL_ADC_CLEAR_FLAG(hadc, tmp_Flag_EOC);
1689 }
1690
1691 /* Return ADC state */
1692 return HAL_OK;
1693 }
1694 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
1695 /* STM32F302xC || STM32F303xC || STM32F358xx || */
1696 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
1697 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
1698
1699 #if defined(STM32F373xC) || defined(STM32F378xx)
1700 /**
1701 * @brief Wait for regular group conversion to be completed.
1702 * @note This function cannot be used in a particular setup: ADC configured
1703 * in DMA mode.
1704 * In this case, DMA resets the flag EOC and polling cannot be
1705 * performed on each conversion.
1706 * @note On STM32F37x devices, limitation in case of sequencer enabled
1707 * (several ranks selected): polling cannot be done on each
1708 * conversion inside the sequence. In this case, polling is replaced by
1709 * wait for maximum conversion time.
1710 * @param hadc ADC handle
1711 * @param Timeout Timeout value in millisecond.
1712 * @retval HAL status
1713 */
HAL_ADC_PollForConversion(ADC_HandleTypeDef * hadc,uint32_t Timeout)1714 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
1715 {
1716 uint32_t tickstart;
1717
1718 /* Variables for polling in case of scan mode enabled */
1719 uint32_t Conversion_Timeout_CPU_cycles_max = 0U;
1720 uint32_t Conversion_Timeout_CPU_cycles = 0U;
1721
1722 /* Check the parameters */
1723 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1724
1725 /* Verification that ADC configuration is compliant with polling for */
1726 /* each conversion: */
1727 /* Particular case is ADC configured in DMA mode */
1728 if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA))
1729 {
1730 /* Update ADC state machine to error */
1731 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1732
1733 /* Process unlocked */
1734 __HAL_UNLOCK(hadc);
1735
1736 return HAL_ERROR;
1737 }
1738
1739 /* Get tick count */
1740 tickstart = HAL_GetTick();
1741
1742 /* Polling for end of conversion: differentiation if single/sequence */
1743 /* conversion. */
1744 /* - If single conversion for regular group (Scan mode disabled or enabled */
1745 /* with NbrOfConversion =1U), flag EOC is used to determine the */
1746 /* conversion completion. */
1747 /* - If sequence conversion for regular group (scan mode enabled and */
1748 /* NbrOfConversion >=2U), flag EOC is set only at the end of the */
1749 /* sequence. */
1750 /* To poll for each conversion, the maximum conversion time is computed */
1751 /* from ADC conversion time (selected sampling time + conversion time of */
1752 /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */
1753 /* settings, conversion time range can be from 28 to 32256 CPU cycles). */
1754 /* As flag EOC is not set after each conversion, no timeout status can */
1755 /* be set. */
1756 if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) &&
1757 HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) )
1758 {
1759 /* Wait until End of Conversion flag is raised */
1760 while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
1761 {
1762 /* Check if timeout is disabled (set to infinite wait) */
1763 if(Timeout != HAL_MAX_DELAY)
1764 {
1765 if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
1766 {
1767 /* New check to avoid false timeout detection in case of preemption */
1768 if(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
1769 {
1770 /* Update ADC state machine to timeout */
1771 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
1772
1773 /* Process unlocked */
1774 __HAL_UNLOCK(hadc);
1775
1776 return HAL_TIMEOUT;
1777 }
1778 }
1779 }
1780 }
1781 }
1782 else
1783 {
1784 /* Replace polling by wait for maximum conversion time */
1785 /* Calculation of CPU cycles corresponding to ADC conversion cycles. */
1786 /* Retrieve ADC clock prescaler and ADC maximum conversion cycles on all */
1787 /* channels. */
1788 Conversion_Timeout_CPU_cycles_max = ADC_CLOCK_PRESCALER_RANGE() ;
1789 Conversion_Timeout_CPU_cycles_max *= ADC_CONVCYCLES_MAX_RANGE(hadc);
1790
1791 /* Poll with maximum conversion time */
1792 while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
1793 {
1794 /* Check if timeout is disabled (set to infinite wait) */
1795 if(Timeout != HAL_MAX_DELAY)
1796 {
1797 if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
1798 {
1799 /* New check to avoid false timeout detection in case of preemption */
1800 if(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
1801 {
1802 /* Update ADC state machine to timeout */
1803 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
1804
1805 /* Process unlocked */
1806 __HAL_UNLOCK(hadc);
1807
1808 return HAL_TIMEOUT;
1809 }
1810 }
1811 }
1812 Conversion_Timeout_CPU_cycles ++;
1813 }
1814 }
1815
1816 /* Clear regular group conversion flag */
1817 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
1818
1819 /* Update ADC state machine */
1820 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
1821
1822 /* Determine whether any further conversion upcoming on group regular */
1823 /* by external trigger, continuous mode or scan sequence on going. */
1824 /* Note: On STM32F37x devices, in case of sequencer enabled */
1825 /* (several ranks selected), end of conversion flag is raised */
1826 /* at the end of the sequence. */
1827 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
1828 (hadc->Init.ContinuousConvMode == DISABLE) )
1829 {
1830 /* Set ADC state */
1831 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1832
1833 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1834 {
1835 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
1836 }
1837 }
1838
1839 /* Return ADC state */
1840 return HAL_OK;
1841 }
1842 #endif /* STM32F373xC || STM32F378xx */
1843
1844 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
1845 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
1846 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
1847 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
1848 /**
1849 * @brief Poll for conversion event.
1850 * @param hadc ADC handle
1851 * @param EventType the ADC event type.
1852 * This parameter can be one of the following values:
1853 * @arg ADC_AWD1_EVENT: ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
1854 * @arg ADC_AWD2_EVENT: ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
1855 * @arg ADC_AWD3_EVENT: ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
1856 * @arg ADC_OVR_EVENT: ADC Overrun event
1857 * @arg ADC_JQOVF_EVENT: ADC Injected context queue overflow event
1858 * @param Timeout Timeout value in millisecond.
1859 * @retval HAL status
1860 */
HAL_ADC_PollForEvent(ADC_HandleTypeDef * hadc,uint32_t EventType,uint32_t Timeout)1861 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
1862 {
1863 uint32_t tickstart;
1864
1865 /* Check the parameters */
1866 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1867 assert_param(IS_ADC_EVENT_TYPE(EventType));
1868
1869 /* Get start tick count */
1870 tickstart = HAL_GetTick();
1871
1872 /* Check selected event flag */
1873 while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
1874 {
1875 /* Check if timeout is disabled (set to infinite wait) */
1876 if(Timeout != HAL_MAX_DELAY)
1877 {
1878 if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
1879 {
1880 /* New check to avoid false timeout detection in case of preemption */
1881 if(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
1882 {
1883 /* Update ADC state machine to timeout */
1884 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
1885
1886 /* Process unlocked */
1887 __HAL_UNLOCK(hadc);
1888
1889 return HAL_TIMEOUT;
1890 }
1891 }
1892 }
1893 }
1894
1895
1896 switch(EventType)
1897 {
1898 /* Analog watchdog (level out of window) event */
1899 /* Note: In case of several analog watchdog enabled, if needed to know */
1900 /* which one triggered and on which ADCx, test ADC state of analog watchdog */
1901 /* flags HAL_ADC_STATE_AWD1/2U/3 using function "HAL_ADC_GetState()". */
1902 /* For example: */
1903 /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)) " */
1904 /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD2)) " */
1905 /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD3)) " */
1906 /* Check analog watchdog 1 flag */
1907 case ADC_AWD_EVENT:
1908 /* Set ADC state */
1909 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
1910
1911 /* Clear ADC analog watchdog flag */
1912 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
1913 break;
1914
1915 /* Check analog watchdog 2 flag */
1916 case ADC_AWD2_EVENT:
1917 /* Set ADC state */
1918 SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
1919
1920 /* Clear ADC analog watchdog flag */
1921 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
1922 break;
1923
1924 /* Check analog watchdog 3 flag */
1925 case ADC_AWD3_EVENT:
1926 /* Set ADC state */
1927 SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
1928
1929 /* Clear ADC analog watchdog flag */
1930 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
1931 break;
1932
1933 /* Injected context queue overflow event */
1934 case ADC_JQOVF_EVENT:
1935 /* Set ADC state */
1936 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
1937
1938 /* Set ADC error code to Injected context queue overflow */
1939 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
1940
1941 /* Clear ADC Injected context queue overflow flag */
1942 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
1943 break;
1944
1945 /* Overrun event */
1946 default: /* Case ADC_OVR_EVENT */
1947 /* If overrun is set to overwrite previous data, overrun event is not */
1948 /* considered as an error. */
1949 /* (cf ref manual "Managing conversions without using the DMA and without */
1950 /* overrun ") */
1951 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
1952 {
1953 /* Set ADC state */
1954 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
1955
1956 /* Set ADC error code to overrun */
1957 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
1958 }
1959
1960 /* Clear ADC Overrun flag */
1961 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1962 break;
1963 }
1964
1965 /* Return ADC state */
1966 return HAL_OK;
1967 }
1968 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
1969 /* STM32F302xC || STM32F303xC || STM32F358xx || */
1970 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
1971 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
1972
1973 #if defined(STM32F373xC) || defined(STM32F378xx)
1974 /**
1975 * @brief Poll for conversion event.
1976 * @param hadc ADC handle
1977 * @param EventType the ADC event type.
1978 * This parameter can be one of the following values:
1979 * @arg ADC_AWD_EVENT: ADC Analog watchdog event.
1980 * @param Timeout Timeout value in millisecond.
1981 * @retval HAL status
1982 */
HAL_ADC_PollForEvent(ADC_HandleTypeDef * hadc,uint32_t EventType,uint32_t Timeout)1983 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
1984 {
1985 uint32_t tickstart;
1986
1987 /* Check the parameters */
1988 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1989 assert_param(IS_ADC_EVENT_TYPE(EventType));
1990
1991 tickstart = HAL_GetTick();
1992
1993 /* Check selected event flag */
1994 while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
1995 {
1996 /* Check if timeout is disabled (set to infinite wait) */
1997 if(Timeout != HAL_MAX_DELAY)
1998 {
1999 if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
2000 {
2001 /* New check to avoid false timeout detection in case of preemption */
2002 if(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
2003 {
2004 /* Update ADC state machine to timeout */
2005 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
2006
2007 /* Process unlocked */
2008 __HAL_UNLOCK(hadc);
2009
2010 return HAL_ERROR;
2011 }
2012 }
2013 }
2014 }
2015
2016 /* Analog watchdog (level out of window) event */
2017 /* Set ADC state */
2018 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
2019
2020 /* Clear ADC analog watchdog flag */
2021 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
2022
2023 /* Return ADC state */
2024 return HAL_OK;
2025 }
2026 #endif /* STM32F373xC || STM32F378xx */
2027
2028 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
2029 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
2030 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
2031 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2032 /**
2033 * @brief Enables ADC, starts conversion of regular group with interruption.
2034 * Interruptions enabled in this function:
2035 * - EOC (end of conversion of regular group) or EOS (end of
2036 * sequence of regular group) depending on ADC initialization
2037 * parameter "EOCSelection"
2038 * - overrun, depending on ADC initialization parameter "Overrun"
2039 * Each of these interruptions has its dedicated callback function.
2040 * @note Case of multimode enabled (for devices with several ADCs): This
2041 * function must be called for ADC slave first, then ADC master.
2042 * For ADC slave, ADC is enabled only (conversion is not started).
2043 * For ADC master, ADC is enabled and multimode conversion is started.
2044 * @param hadc ADC handle
2045 * @retval HAL status
2046 */
HAL_ADC_Start_IT(ADC_HandleTypeDef * hadc)2047 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
2048 {
2049 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
2050
2051 /* Check the parameters */
2052 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2053
2054 /* Perform ADC enable and conversion start if no conversion is on going */
2055 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
2056 {
2057 /* Process locked */
2058 __HAL_LOCK(hadc);
2059
2060 /* Enable the ADC peripheral */
2061 tmp_hal_status = ADC_Enable(hadc);
2062
2063 /* Start conversion if ADC is effectively enabled */
2064 if (tmp_hal_status == HAL_OK)
2065 {
2066 /* Set ADC state */
2067 /* - Clear state bitfield related to regular group conversion results */
2068 /* - Set state bitfield related to regular operation */
2069 ADC_STATE_CLR_SET(hadc->State,
2070 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
2071 HAL_ADC_STATE_REG_BUSY);
2072
2073 /* Set group injected state (from auto-injection) and multimode state */
2074 /* for all cases of multimode: independent mode, multimode ADC master */
2075 /* or multimode ADC slave (for devices with several ADCs): */
2076 if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
2077 {
2078 /* Set ADC state (ADC independent or master) */
2079 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
2080
2081 /* If conversions on group regular are also triggering group injected,*/
2082 /* update ADC state. */
2083 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
2084 {
2085 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
2086 }
2087 }
2088 else
2089 {
2090 /* Set ADC state (ADC slave) */
2091 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
2092
2093 /* If conversions on group regular are also triggering group injected,*/
2094 /* update ADC state. */
2095 if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
2096 {
2097 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
2098 }
2099 }
2100
2101 /* State machine update: Check if an injected conversion is ongoing */
2102 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
2103 {
2104 /* Reset ADC error code fields related to conversions on group regular*/
2105 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
2106 }
2107 else
2108 {
2109 /* Reset ADC all error code fields */
2110 ADC_CLEAR_ERRORCODE(hadc);
2111 }
2112
2113 /* Process unlocked */
2114 /* Unlock before starting ADC conversions: in case of potential */
2115 /* interruption, to let the process to ADC IRQ Handler. */
2116 __HAL_UNLOCK(hadc);
2117
2118 /* Clear regular group conversion flag and overrun flag */
2119 /* (To ensure of no unknown state from potential previous ADC */
2120 /* operations) */
2121 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
2122
2123 /* Enable ADC end of conversion interrupt */
2124 /* Enable ADC overrun interrupt */
2125 switch(hadc->Init.EOCSelection)
2126 {
2127 case ADC_EOC_SEQ_CONV:
2128 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
2129 __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOS));
2130 break;
2131 /* case ADC_EOC_SINGLE_CONV */
2132 default:
2133 __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS));
2134 break;
2135 }
2136
2137 /* If overrun is set to overwrite previous data (default setting), */
2138 /* overrun interrupt is not activated (overrun event is not considered */
2139 /* as an error). */
2140 /* (cf ref manual "Managing conversions without using the DMA and */
2141 /* without overrun ") */
2142 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
2143 {
2144 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
2145 }
2146
2147 /* Enable conversion of regular group. */
2148 /* If software start has been selected, conversion starts immediately. */
2149 /* If external trigger has been selected, conversion will start at next */
2150 /* trigger event. */
2151 /* Case of multimode enabled (for devices with several ADCs): */
2152 /* - if ADC is slave, ADC is enabled only (conversion is not started). */
2153 /* - if ADC is master, ADC is enabled and conversion is started. */
2154 if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc))
2155 {
2156 SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
2157 }
2158 }
2159 else
2160 {
2161 /* Process unlocked */
2162 __HAL_UNLOCK(hadc);
2163 }
2164 }
2165 else
2166 {
2167 tmp_hal_status = HAL_BUSY;
2168 }
2169
2170 /* Return function status */
2171 return tmp_hal_status;
2172 }
2173 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2174 /* STM32F302xC || STM32F303xC || STM32F358xx || */
2175 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2176 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2177
2178 #if defined(STM32F373xC) || defined(STM32F378xx)
2179 /**
2180 * @brief Enables ADC, starts conversion of regular group with interruption.
2181 * Interruptions enabled in this function:
2182 * - EOC (end of conversion of regular group)
2183 * Each of these interruptions has its dedicated callback function.
2184 * @param hadc ADC handle
2185 * @retval HAL status
2186 */
HAL_ADC_Start_IT(ADC_HandleTypeDef * hadc)2187 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
2188 {
2189 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
2190
2191 /* Check the parameters */
2192 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2193
2194 /* Process locked */
2195 __HAL_LOCK(hadc);
2196
2197 /* Enable the ADC peripheral */
2198 tmp_hal_status = ADC_Enable(hadc);
2199
2200 /* Start conversion if ADC is effectively enabled */
2201 if (tmp_hal_status == HAL_OK)
2202 {
2203 /* Set ADC state */
2204 /* - Clear state bitfield related to regular group conversion results */
2205 /* - Set state bitfield related to regular operation */
2206 ADC_STATE_CLR_SET(hadc->State,
2207 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC,
2208 HAL_ADC_STATE_REG_BUSY);
2209
2210 /* Set group injected state (from auto-injection) */
2211 /* If conversions on group regular are also triggering group injected, */
2212 /* update ADC state. */
2213 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
2214 {
2215 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
2216 }
2217
2218 /* State machine update: Check if an injected conversion is ongoing */
2219 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
2220 {
2221 /* Reset ADC error code fields related to conversions on group regular */
2222 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
2223 }
2224 else
2225 {
2226 /* Reset ADC all error code fields */
2227 ADC_CLEAR_ERRORCODE(hadc);
2228 }
2229
2230 /* Process unlocked */
2231 /* Unlock before starting ADC conversions: in case of potential */
2232 /* interruption, to let the process to ADC IRQ Handler. */
2233 __HAL_UNLOCK(hadc);
2234
2235 /* Clear regular group conversion flag and overrun flag */
2236 /* (To ensure of no unknown state from potential previous ADC operations) */
2237 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
2238
2239 /* Enable end of conversion interrupt for regular group */
2240 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
2241
2242 /* Enable conversion of regular group. */
2243 /* If software start has been selected, conversion starts immediately. */
2244 /* If external trigger has been selected, conversion will start at next */
2245 /* trigger event. */
2246 if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
2247 {
2248 /* Start ADC conversion on regular group with SW start */
2249 SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
2250 }
2251 else
2252 {
2253 /* Start ADC conversion on regular group with external trigger */
2254 SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
2255 }
2256 }
2257
2258 /* Return function status */
2259 return tmp_hal_status;
2260 }
2261 #endif /* STM32F373xC || STM32F378xx */
2262
2263 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
2264 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
2265 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
2266 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2267 /**
2268 * @brief Stop ADC conversion of both groups regular and injected,
2269 * disable ADC peripheral.
2270 * Interruptions disabled in this function:
2271 * - EOC (end of conversion of regular group) and EOS (end of
2272 * sequence of regular group)
2273 * - overrun
2274 * @note ADC peripheral disable is forcing interruption of potential
2275 * conversion on injected group. If injected group is under use,
2276 * it should be preliminarily stopped using function
2277 * @ref HAL_ADCEx_InjectedStop().
2278 * To stop ADC conversion only on ADC group regular
2279 * while letting ADC group injected conversions running,
2280 * use function @ref HAL_ADCEx_RegularStop_IT().
2281 * @param hadc ADC handle
2282 * @retval HAL status.
2283 */
HAL_ADC_Stop_IT(ADC_HandleTypeDef * hadc)2284 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
2285 {
2286 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
2287
2288 /* Check the parameters */
2289 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2290
2291 /* Process locked */
2292 __HAL_LOCK(hadc);
2293
2294 /* 1. Stop potential conversion on going, on regular and injected groups */
2295 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
2296
2297 /* Disable ADC peripheral if conversions are effectively stopped */
2298 if (tmp_hal_status == HAL_OK)
2299 {
2300 /* Disable ADC end of conversion interrupt for regular group */
2301 /* Disable ADC overrun interrupt */
2302 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
2303
2304 /* 2. Disable the ADC peripheral */
2305 tmp_hal_status = ADC_Disable(hadc);
2306
2307 /* Check if ADC is effectively disabled */
2308 if (tmp_hal_status == HAL_OK)
2309 {
2310 /* Set ADC state */
2311 ADC_STATE_CLR_SET(hadc->State,
2312 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
2313 HAL_ADC_STATE_READY);
2314 }
2315 }
2316
2317 /* Process unlocked */
2318 __HAL_UNLOCK(hadc);
2319
2320 /* Return function status */
2321 return tmp_hal_status;
2322 }
2323 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2324 /* STM32F302xC || STM32F303xC || STM32F358xx || */
2325 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2326 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2327
2328 #if defined(STM32F373xC) || defined(STM32F378xx)
2329 /**
2330 * @brief Stop ADC conversion of regular group (and injected group in
2331 * case of auto_injection mode), disable interrution of
2332 * end-of-conversion, disable ADC peripheral.
2333 * @param hadc ADC handle
2334 * @retval None
2335 */
HAL_ADC_Stop_IT(ADC_HandleTypeDef * hadc)2336 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
2337 {
2338 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
2339
2340 /* Check the parameters */
2341 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2342
2343 /* Process locked */
2344 __HAL_LOCK(hadc);
2345
2346 /* Stop potential conversion on going, on regular and injected groups */
2347 /* Disable ADC peripheral */
2348 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
2349
2350 /* Check if ADC is effectively disabled */
2351 if (tmp_hal_status == HAL_OK)
2352 {
2353 /* Disable ADC end of conversion interrupt for regular group */
2354 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
2355
2356 /* Set ADC state */
2357 ADC_STATE_CLR_SET(hadc->State,
2358 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
2359 HAL_ADC_STATE_READY);
2360 }
2361
2362 /* Process unlocked */
2363 __HAL_UNLOCK(hadc);
2364
2365 /* Return function status */
2366 return tmp_hal_status;
2367 }
2368 #endif /* STM32F373xC || STM32F378xx */
2369
2370 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
2371 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
2372 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
2373 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2374 /**
2375 * @brief Enables ADC, starts conversion of regular group and transfers result
2376 * through DMA.
2377 * Interruptions enabled in this function:
2378 * - DMA transfer complete
2379 * - DMA half transfer
2380 * - overrun
2381 * Each of these interruptions has its dedicated callback function.
2382 * @note Case of multimode enabled (for devices with several ADCs): This
2383 * function is for single-ADC mode only. For multimode, use the
2384 * dedicated MultimodeStart function.
2385 * @param hadc ADC handle
2386 * @param pData The destination Buffer address.
2387 * @param Length The length of data to be transferred from ADC peripheral to memory.
2388 * @retval None
2389 */
HAL_ADC_Start_DMA(ADC_HandleTypeDef * hadc,uint32_t * pData,uint32_t Length)2390 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
2391 {
2392 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
2393
2394 /* Check the parameters */
2395 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2396
2397 /* Perform ADC enable and conversion start if no conversion is on going */
2398 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
2399 {
2400 /* Process locked */
2401 __HAL_LOCK(hadc);
2402
2403 /* Verification if multimode is disabled (for devices with several ADC) */
2404 /* If multimode is enabled, dedicated function multimode conversion */
2405 /* start DMA must be used. */
2406 if(ADC_COMMON_CCR_MULTI(hadc) == RESET)
2407 {
2408 /* Enable the ADC peripheral */
2409 tmp_hal_status = ADC_Enable(hadc);
2410
2411 /* Start conversion if ADC is effectively enabled */
2412 if (tmp_hal_status == HAL_OK)
2413 {
2414 /* Set ADC state */
2415 /* - Clear state bitfield related to regular group conversion results */
2416 /* - Set state bitfield related to regular operation */
2417 ADC_STATE_CLR_SET(hadc->State,
2418 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
2419 HAL_ADC_STATE_REG_BUSY);
2420
2421 /* Set group injected state (from auto-injection) and multimode state */
2422 /* for all cases of multimode: independent mode, multimode ADC master */
2423 /* or multimode ADC slave (for devices with several ADCs): */
2424 if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
2425 {
2426 /* Set ADC state (ADC independent or master) */
2427 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
2428
2429 /* If conversions on group regular are also triggering group injected,*/
2430 /* update ADC state. */
2431 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
2432 {
2433 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
2434 }
2435 }
2436 else
2437 {
2438 /* Set ADC state (ADC slave) */
2439 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
2440
2441 /* If conversions on group regular are also triggering group injected,*/
2442 /* update ADC state. */
2443 if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
2444 {
2445 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
2446 }
2447 }
2448
2449 /* State machine update: Check if an injected conversion is ongoing */
2450 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
2451 {
2452 /* Reset ADC error code fields related to conversions on group regular*/
2453 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
2454 }
2455 else
2456 {
2457 /* Reset ADC all error code fields */
2458 ADC_CLEAR_ERRORCODE(hadc);
2459 }
2460
2461 /* Process unlocked */
2462 /* Unlock before starting ADC conversions: in case of potential */
2463 /* interruption, to let the process to ADC IRQ Handler. */
2464 __HAL_UNLOCK(hadc);
2465
2466
2467 /* Set the DMA transfer complete callback */
2468 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
2469
2470 /* Set the DMA half transfer complete callback */
2471 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
2472
2473 /* Set the DMA error callback */
2474 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
2475
2476
2477 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
2478 /* start (in case of SW start): */
2479
2480 /* Clear regular group conversion flag and overrun flag */
2481 /* (To ensure of no unknown state from potential previous ADC */
2482 /* operations) */
2483 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
2484
2485 /* Enable ADC overrun interrupt */
2486 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
2487
2488 /* Enable ADC DMA mode */
2489 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
2490
2491 /* Start the DMA channel */
2492 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
2493
2494 /* Enable conversion of regular group. */
2495 /* If software start has been selected, conversion starts immediately.*/
2496 /* If external trigger has been selected, conversion will start at */
2497 /* next trigger event. */
2498 SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
2499
2500 }
2501 else
2502 {
2503 /* Process unlocked */
2504 __HAL_UNLOCK(hadc);
2505 }
2506 }
2507 else
2508 {
2509 tmp_hal_status = HAL_ERROR;
2510
2511 /* Process unlocked */
2512 __HAL_UNLOCK(hadc);
2513 }
2514 }
2515 else
2516 {
2517 tmp_hal_status = HAL_BUSY;
2518 }
2519
2520 /* Return function status */
2521 return tmp_hal_status;
2522 }
2523 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2524 /* STM32F302xC || STM32F303xC || STM32F358xx || */
2525 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2526 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2527
2528 #if defined(STM32F373xC) || defined(STM32F378xx)
2529 /**
2530 * @brief Enables ADC, starts conversion of regular group and transfers result
2531 * through DMA.
2532 * Interruptions enabled in this function:
2533 * - DMA transfer complete
2534 * - DMA half transfer
2535 * Each of these interruptions has its dedicated callback function.
2536 * @note For devices with several ADCs: This function is for single-ADC mode
2537 * only. For multimode, use the dedicated MultimodeStart function.
2538 * @param hadc ADC handle
2539 * @param pData The destination Buffer address.
2540 * @param Length The length of data to be transferred from ADC peripheral to memory.
2541 * @retval None
2542 */
HAL_ADC_Start_DMA(ADC_HandleTypeDef * hadc,uint32_t * pData,uint32_t Length)2543 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
2544 {
2545 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
2546
2547 /* Check the parameters */
2548 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2549
2550 /* Process locked */
2551 __HAL_LOCK(hadc);
2552
2553 /* Enable the ADC peripheral */
2554 tmp_hal_status = ADC_Enable(hadc);
2555
2556 /* Start conversion if ADC is effectively enabled */
2557 if (tmp_hal_status == HAL_OK)
2558 {
2559 /* Set ADC state */
2560 /* - Clear state bitfield related to regular group conversion results */
2561 /* - Set state bitfield related to regular operation */
2562 ADC_STATE_CLR_SET(hadc->State,
2563 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC,
2564 HAL_ADC_STATE_REG_BUSY);
2565
2566 /* Set group injected state (from auto-injection) */
2567 /* If conversions on group regular are also triggering group injected, */
2568 /* update ADC state. */
2569 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
2570 {
2571 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
2572 }
2573
2574 /* State machine update: Check if an injected conversion is ongoing */
2575 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
2576 {
2577 /* Reset ADC error code fields related to conversions on group regular */
2578 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
2579 }
2580 else
2581 {
2582 /* Reset ADC all error code fields */
2583 ADC_CLEAR_ERRORCODE(hadc);
2584 }
2585
2586 /* Process unlocked */
2587 /* Unlock before starting ADC conversions: in case of potential */
2588 /* interruption, to let the process to ADC IRQ Handler. */
2589 __HAL_UNLOCK(hadc);
2590
2591 /* Set the DMA transfer complete callback */
2592 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
2593
2594 /* Set the DMA half transfer complete callback */
2595 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
2596
2597 /* Set the DMA error callback */
2598 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
2599
2600
2601 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
2602 /* start (in case of SW start): */
2603
2604 /* Clear regular group conversion flag and overrun flag */
2605 /* (To ensure of no unknown state from potential previous ADC operations) */
2606 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
2607
2608 /* Enable ADC DMA mode */
2609 hadc->Instance->CR2 |= ADC_CR2_DMA;
2610
2611 /* Start the DMA channel */
2612 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
2613
2614 /* Enable conversion of regular group. */
2615 /* If software start has been selected, conversion starts immediately. */
2616 /* If external trigger has been selected, conversion will start at next */
2617 /* trigger event. */
2618 /* Note: Alternate trigger for single conversion could be to force an */
2619 /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
2620 if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
2621 {
2622 /* Start ADC conversion on regular group with SW start */
2623 SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
2624 }
2625 else
2626 {
2627 /* Start ADC conversion on regular group with external trigger */
2628 SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
2629 }
2630 }
2631
2632 /* Return function status */
2633 return tmp_hal_status;
2634 }
2635 #endif /* STM32F373xC || STM32F378xx */
2636
2637 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
2638 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
2639 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
2640 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2641 /**
2642 * @brief Stop ADC conversion of both groups regular and injected,
2643 * disable ADC DMA transfer, disable ADC peripheral.
2644 * Interruptions disabled in this function:
2645 * - DMA transfer complete
2646 * - DMA half transfer
2647 * - overrun
2648 * @note ADC peripheral disable is forcing interruption of potential
2649 * conversion on injected group. If injected group is under use,
2650 * it should be preliminarily stopped using function
2651 * @ref HAL_ADCEx_InjectedStop().
2652 * To stop ADC conversion only on ADC group regular
2653 * while letting ADC group injected conversions running,
2654 * use function @ref HAL_ADCEx_RegularStop_DMA().
2655 * @note Case of multimode enabled (for devices with several ADCs): This
2656 * function is for single-ADC mode only. For multimode, use the
2657 * dedicated MultimodeStop function.
2658 * @param hadc ADC handle
2659 * @retval HAL status.
2660 */
HAL_ADC_Stop_DMA(ADC_HandleTypeDef * hadc)2661 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
2662 {
2663 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
2664
2665 /* Check the parameters */
2666 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2667
2668 /* Process locked */
2669 __HAL_LOCK(hadc);
2670
2671 /* 1. Stop potential conversion on going, on regular and injected groups */
2672 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
2673
2674 /* Disable ADC peripheral if conversions are effectively stopped */
2675 if (tmp_hal_status == HAL_OK)
2676 {
2677 /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
2678 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
2679
2680 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
2681 /* while DMA transfer is on going) */
2682 if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
2683 {
2684 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
2685
2686 /* Check if DMA channel effectively disabled */
2687 if (tmp_hal_status != HAL_OK)
2688 {
2689 /* Update ADC state machine to error */
2690 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
2691 }
2692 }
2693
2694 /* Disable ADC overrun interrupt */
2695 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
2696
2697 /* 2. Disable the ADC peripheral */
2698 /* Update "tmp_hal_status" only if DMA channel disabling passed, */
2699 /* to retain a potential failing status. */
2700 if (tmp_hal_status == HAL_OK)
2701 {
2702 tmp_hal_status = ADC_Disable(hadc);
2703 }
2704 else
2705 {
2706 ADC_Disable(hadc);
2707 }
2708
2709 /* Check if ADC is effectively disabled */
2710 if (tmp_hal_status == HAL_OK)
2711 {
2712 /* Set ADC state */
2713 ADC_STATE_CLR_SET(hadc->State,
2714 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
2715 HAL_ADC_STATE_READY);
2716 }
2717
2718 }
2719
2720 /* Process unlocked */
2721 __HAL_UNLOCK(hadc);
2722
2723 /* Return function status */
2724 return tmp_hal_status;
2725 }
2726 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2727 /* STM32F302xC || STM32F303xC || STM32F358xx || */
2728 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2729 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2730
2731 #if defined(STM32F373xC) || defined(STM32F378xx)
2732 /**
2733 * @brief Stop ADC conversion of regular group (and injected group in
2734 * case of auto_injection mode), disable ADC DMA transfer, disable
2735 * ADC peripheral.
2736 * @note ADC peripheral disable is forcing interruption of potential
2737 * conversion on injected group. If injected group is under use, it
2738 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
2739 * @note For devices with several ADCs: This function is for single-ADC mode
2740 * only. For multimode, use the dedicated MultimodeStop function.
2741 * @param hadc ADC handle
2742 * @retval HAL status.
2743 */
HAL_ADC_Stop_DMA(ADC_HandleTypeDef * hadc)2744 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
2745 {
2746 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
2747
2748 /* Check the parameters */
2749 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2750
2751 /* Process locked */
2752 __HAL_LOCK(hadc);
2753
2754 /* Stop potential conversion on going, on regular and injected groups */
2755 /* Disable ADC peripheral */
2756 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
2757
2758 /* Check if ADC is effectively disabled */
2759 if (tmp_hal_status == HAL_OK)
2760 {
2761 /* Disable ADC DMA mode */
2762 hadc->Instance->CR2 &= ~ADC_CR2_DMA;
2763
2764 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
2765 /* while DMA transfer is on going) */
2766 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
2767
2768 /* Check if DMA channel effectively disabled */
2769 if (tmp_hal_status == HAL_OK)
2770 {
2771 /* Set ADC state */
2772 ADC_STATE_CLR_SET(hadc->State,
2773 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
2774 HAL_ADC_STATE_READY);
2775 }
2776 else
2777 {
2778 /* Update ADC state machine to error */
2779 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
2780 }
2781 }
2782
2783 /* Process unlocked */
2784 __HAL_UNLOCK(hadc);
2785
2786 /* Return function status */
2787 return tmp_hal_status;
2788 }
2789 #endif /* STM32F373xC || STM32F378xx */
2790
2791 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
2792 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
2793 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
2794 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2795 /**
2796 * @brief Get ADC regular group conversion result.
2797 * @note Reading register DR automatically clears ADC flag EOC
2798 * (ADC group regular end of unitary conversion).
2799 * @note This function does not clear ADC flag EOS
2800 * (ADC group regular end of sequence conversion).
2801 * Occurrence of flag EOS rising:
2802 * - If sequencer is composed of 1 rank, flag EOS is equivalent
2803 * to flag EOC.
2804 * - If sequencer is composed of several ranks, during the scan
2805 * sequence flag EOC only is raised, at the end of the scan sequence
2806 * both flags EOC and EOS are raised.
2807 * To clear this flag, either use function:
2808 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
2809 * model polling: @ref HAL_ADC_PollForConversion()
2810 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
2811 * @param hadc ADC handle
2812 * @retval ADC group regular conversion data
2813 */
HAL_ADC_GetValue(ADC_HandleTypeDef * hadc)2814 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
2815 {
2816 /* Check the parameters */
2817 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2818
2819 /* Note: ADC flag EOC is not cleared here by software because */
2820 /* automatically cleared by hardware when reading register DR. */
2821
2822 /* Return ADC converted value */
2823 return hadc->Instance->DR;
2824 }
2825 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2826 /* STM32F302xC || STM32F303xC || STM32F358xx || */
2827 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2828 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2829
2830 #if defined(STM32F373xC) || defined(STM32F378xx)
2831 /**
2832 * @brief Get ADC regular group conversion result.
2833 * @note Reading register DR automatically clears ADC flag EOC
2834 * (ADC group regular end of unitary conversion).
2835 * @note This function does not clear ADC flag EOS
2836 * (ADC group regular end of sequence conversion).
2837 * Occurrence of flag EOS rising:
2838 * - If sequencer is composed of 1 rank, flag EOS is equivalent
2839 * to flag EOC.
2840 * - If sequencer is composed of several ranks, during the scan
2841 * sequence flag EOC only is raised, at the end of the scan sequence
2842 * both flags EOC and EOS are raised.
2843 * To clear this flag, either use function:
2844 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
2845 * model polling: @ref HAL_ADC_PollForConversion()
2846 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
2847 * @param hadc ADC handle
2848 * @retval ADC group regular conversion data
2849 */
HAL_ADC_GetValue(ADC_HandleTypeDef * hadc)2850 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
2851 {
2852 /* Check the parameters */
2853 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2854
2855 /* Note: EOC flag is not cleared here by software because automatically */
2856 /* cleared by hardware when reading register DR. */
2857
2858 /* Return ADC converted value */
2859 return hadc->Instance->DR;
2860 }
2861 #endif /* STM32F373xC || STM32F378xx */
2862
2863 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
2864 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
2865 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
2866 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2867 /**
2868 * @brief Handles ADC interrupt request.
2869 * @param hadc ADC handle
2870 * @retval None
2871 */
HAL_ADC_IRQHandler(ADC_HandleTypeDef * hadc)2872 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
2873 {
2874 uint32_t overrun_error = 0U; /* flag set if overrun occurrence has to be considered as an error */
2875 ADC_Common_TypeDef *tmpADC_Common;
2876 uint32_t tmp_cfgr = 0x0U;
2877 uint32_t tmp_cfgr_jqm = 0x0U;
2878 uint32_t tmp_isr = hadc->Instance->ISR;
2879 uint32_t tmp_ier = hadc->Instance->IER;
2880
2881 /* Check the parameters */
2882 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2883 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
2884 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
2885
2886 /* ========== Check End of Conversion flag for regular group ========== */
2887 if( (((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
2888 (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)) )
2889 {
2890 /* Update state machine on conversion status if not in error state */
2891 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
2892 {
2893 /* Set ADC state */
2894 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
2895 }
2896
2897 /* Get relevant register CFGR in ADC instance of ADC master or slave */
2898 /* in function of multimode state (for devices with multimode */
2899 /* available). */
2900 if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc))
2901 {
2902 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
2903 }
2904 else
2905 {
2906 tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
2907 }
2908
2909 /* Disable interruption if no further conversion upcoming by regular */
2910 /* external trigger or by continuous mode, */
2911 /* and if scan sequence if completed. */
2912 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
2913 (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == RESET) )
2914 {
2915 /* If End of Sequence is reached, disable interrupts */
2916 if((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS)
2917 {
2918 /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
2919 /* ADSTART==0 (no conversion on going) */
2920 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
2921 {
2922 /* Disable ADC end of sequence conversion interrupt */
2923 /* Note: Overrun interrupt was enabled with EOC interrupt in */
2924 /* HAL_Start_IT(), but is not disabled here because can be used */
2925 /* by overrun IRQ process below. */
2926 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
2927
2928 /* Set ADC state */
2929 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
2930
2931 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
2932 {
2933 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
2934 }
2935 }
2936 else
2937 {
2938 /* Update ADC state machine to error */
2939 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
2940
2941 /* Set ADC error code to ADC IP internal error */
2942 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
2943 }
2944 }
2945 }
2946
2947 /* Conversion complete callback */
2948 /* Note: into callback, to determine if conversion has been triggered */
2949 /* from EOC or EOS, possibility to use: */
2950 /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
2951 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2952 hadc->ConvCpltCallback(hadc);
2953 #else
2954 HAL_ADC_ConvCpltCallback(hadc);
2955 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2956
2957
2958 /* Clear regular group conversion flag */
2959 /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
2960 /* conversion flags clear induces the release of the preserved */
2961 /* data. */
2962 /* Therefore, if the preserved data value is needed, it must be */
2963 /* read preliminarily into HAL_ADC_ConvCpltCallback(). */
2964 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) );
2965 }
2966
2967
2968 /* ========== Check End of Conversion flag for injected group ========== */
2969 if( (((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
2970 (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)) )
2971 {
2972 /* Set ADC state */
2973 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
2974
2975 /* Get relevant register CFGR in ADC instance of ADC master or slave */
2976 /* in function of multimode state (for devices with multimode */
2977 /* available). */
2978 if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc))
2979 {
2980 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
2981 }
2982 else
2983 {
2984 tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
2985 }
2986
2987 /* Disable interruption if no further conversion upcoming by injected */
2988 /* external trigger or by automatic injected conversion with regular */
2989 /* group having no further conversion upcoming (same conditions as */
2990 /* regular group interruption disabling above), */
2991 /* and if injected scan sequence is completed. */
2992 if(ADC_IS_SOFTWARE_START_INJECTED(hadc))
2993 {
2994 if((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) ||
2995 (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
2996 (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) )
2997 {
2998 /* If End of Sequence is reached, disable interrupts */
2999 if((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS)
3000 {
3001
3002 /* Get relevant register CFGR in ADC instance of ADC master or slave */
3003 /* in function of multimode state (for devices with multimode */
3004 /* available). */
3005 if (ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(hadc))
3006 {
3007 tmp_cfgr_jqm = READ_REG(hadc->Instance->CFGR);
3008 }
3009 else
3010 {
3011 tmp_cfgr_jqm = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
3012 }
3013
3014 /* Particular case if injected contexts queue is enabled: */
3015 /* when the last context has been fully processed, JSQR is reset */
3016 /* by the hardware. Even if no injected conversion is planned to come */
3017 /* (queue empty, triggers are ignored), it can start again */
3018 /* immediately after setting a new context (JADSTART is still set). */
3019 /* Therefore, state of HAL ADC injected group is kept to busy. */
3020 if(READ_BIT(tmp_cfgr_jqm, ADC_CFGR_JQM) == RESET)
3021 {
3022 /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
3023 /* JADSTART==0 (no conversion on going) */
3024 if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
3025 {
3026 /* Disable ADC end of sequence conversion interrupt */
3027 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
3028
3029 /* Set ADC state */
3030 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
3031
3032 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
3033 {
3034 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
3035 }
3036 }
3037 else
3038 {
3039 /* Update ADC state machine to error */
3040 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3041
3042 /* Set ADC error code to ADC IP internal error */
3043 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3044 }
3045 }
3046 }
3047 }
3048 }
3049
3050 /* Conversion complete callback */
3051 /* Note: into callback, to determine if conversion has been triggered */
3052 /* from JEOC or JEOS, possibility to use: */
3053 /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) " */
3054 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3055 hadc->InjectedConvCpltCallback(hadc);
3056 #else
3057 HAL_ADCEx_InjectedConvCpltCallback(hadc);
3058 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3059
3060 /* Clear injected group conversion flag */
3061 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
3062 }
3063
3064 /* ========== Check analog watchdog 1 flag ========== */
3065 if(((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
3066 {
3067 /* Set ADC state */
3068 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
3069
3070 /* Level out of window 1 callback */
3071 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3072 hadc->LevelOutOfWindowCallback(hadc);
3073 #else
3074 HAL_ADC_LevelOutOfWindowCallback(hadc);
3075 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3076 /* Clear ADC analog watchdog flag */
3077 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
3078 }
3079
3080 /* ========== Check analog watchdog 2 flag ========== */
3081 if(((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
3082 {
3083 /* Set ADC state */
3084 SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
3085
3086 /* Level out of window 2 callback */
3087 HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
3088 /* Clear ADC analog watchdog flag */
3089 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
3090 }
3091
3092 /* ========== Check analog watchdog 3 flag ========== */
3093 if(((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
3094 {
3095 /* Set ADC state */
3096 SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
3097
3098 /* Level out of window 3 callback */
3099 HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
3100 /* Clear ADC analog watchdog flag */
3101 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
3102 }
3103
3104 /* ========== Check Overrun flag ========== */
3105 if(((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
3106 {
3107 /* If overrun is set to overwrite previous data (default setting), */
3108 /* overrun event is not considered as an error. */
3109 /* (cf ref manual "Managing conversions without using the DMA and */
3110 /* without overrun ") */
3111 /* Exception for usage with DMA overrun event always considered as an */
3112 /* error. */
3113 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
3114 {
3115 overrun_error = 1U;
3116 }
3117 else
3118 {
3119 /* Pointer to the common control register to which is belonging hadc */
3120 /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
3121 /* control registers) */
3122 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
3123
3124 /* Check DMA configuration, depending on MultiMode set or not */
3125 if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI) == ADC_MODE_INDEPENDENT)
3126 {
3127 if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN))
3128 {
3129 overrun_error = 1U;
3130 }
3131 }
3132 else
3133 {
3134 /* MultiMode is enabled, Common Control Register MDMA bits must be checked */
3135 if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA) != RESET)
3136 {
3137 overrun_error = 1U;
3138 }
3139 }
3140 }
3141
3142 if (overrun_error == 1U)
3143 {
3144 /* Update ADC state machine to error */
3145 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
3146
3147 /* Set ADC error code to ADC IP internal error */
3148 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
3149
3150 /* Error callback */
3151 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3152 hadc->ErrorCallback(hadc);
3153 #else
3154 HAL_ADC_ErrorCallback(hadc);
3155 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3156 }
3157
3158 /* Clear the Overrun flag */
3159 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
3160
3161 }
3162
3163
3164 /* ========== Check Injected context queue overflow flag ========== */
3165 if(((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF))
3166 {
3167 /* Update ADC state machine to error */
3168 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
3169
3170 /* Set ADC error code to ADC IP internal error */
3171 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
3172
3173 /* Clear the Injected context queue overflow flag */
3174 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
3175
3176 /* Error callback */
3177 HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
3178 }
3179
3180 }
3181 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
3182 /* STM32F302xC || STM32F303xC || STM32F358xx || */
3183 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
3184 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
3185
3186 #if defined(STM32F373xC) || defined(STM32F378xx)
3187 /**
3188 * @brief Handles ADC interrupt request
3189 * @param hadc ADC handle
3190 * @retval None
3191 */
HAL_ADC_IRQHandler(ADC_HandleTypeDef * hadc)3192 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
3193 {
3194 uint32_t tmp_sr = hadc->Instance->SR;
3195 uint32_t tmp_cr1 = hadc->Instance->CR1;
3196
3197 /* Check the parameters */
3198 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3199 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
3200 assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
3201
3202
3203 /* ========== Check End of Conversion flag for regular group ========== */
3204 if((tmp_cr1 & ADC_IT_EOC) == ADC_IT_EOC)
3205 {
3206 if((tmp_sr & ADC_FLAG_EOC) == ADC_FLAG_EOC)
3207 {
3208 /* Update state machine on conversion status if not in error state */
3209 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
3210 {
3211 /* Set ADC state */
3212 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
3213 }
3214
3215 /* Determine whether any further conversion upcoming on group regular */
3216 /* by external trigger, continuous mode or scan sequence on going. */
3217 /* Note: On STM32F37x devices, in case of sequencer enabled */
3218 /* (several ranks selected), end of conversion flag is raised */
3219 /* at the end of the sequence. */
3220 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
3221 (hadc->Init.ContinuousConvMode == DISABLE) )
3222 {
3223 /* Disable ADC end of single conversion interrupt */
3224 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
3225
3226 /* Set ADC state */
3227 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
3228
3229 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
3230 {
3231 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
3232 }
3233 }
3234
3235 /* Conversion complete callback */
3236 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3237 hadc->ConvCpltCallback(hadc);
3238 #else
3239 HAL_ADC_ConvCpltCallback(hadc);
3240 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3241
3242 /* Clear regular group conversion flag */
3243 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
3244 }
3245 }
3246
3247 /* ========== Check End of Conversion flag for injected group ========== */
3248 if((tmp_cr1 & ADC_IT_JEOC) == ADC_IT_JEOC)
3249 {
3250 if((tmp_sr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC)
3251 {
3252 /* Update state machine on conversion status if not in error state */
3253 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
3254 {
3255 /* Set ADC state */
3256 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
3257 }
3258
3259 /* Determine whether any further conversion upcoming on group injected */
3260 /* by external trigger, scan sequence on going or by automatic injected */
3261 /* conversion from group regular (same conditions as group regular */
3262 /* interruption disabling above). */
3263 /* Note: On STM32F37x devices, in case of sequencer enabled */
3264 /* (several ranks selected), end of conversion flag is raised */
3265 /* at the end of the sequence. */
3266 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) ||
3267 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
3268 (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
3269 (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
3270 {
3271 /* Disable ADC end of single conversion interrupt */
3272 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
3273
3274 /* Set ADC state */
3275 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
3276
3277 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
3278 {
3279 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
3280 }
3281 }
3282
3283 /* Conversion complete callback */
3284 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3285 hadc->InjectedConvCpltCallback(hadc);
3286 #else
3287 HAL_ADCEx_InjectedConvCpltCallback(hadc);
3288 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3289
3290 /* Clear injected group conversion flag */
3291 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
3292 }
3293 }
3294
3295 /* ========== Check Analog watchdog flags ========== */
3296 if((tmp_cr1 & ADC_IT_AWD) == ADC_IT_AWD)
3297 {
3298 if((tmp_sr & ADC_FLAG_AWD) == ADC_FLAG_AWD)
3299 {
3300 /* Set ADC state */
3301 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
3302
3303 /* Level out of window callback */
3304 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3305 hadc->LevelOutOfWindowCallback(hadc);
3306 #else
3307 HAL_ADC_LevelOutOfWindowCallback(hadc);
3308 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3309
3310 /* Clear the ADC analog watchdog flag */
3311 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
3312 }
3313 }
3314
3315 }
3316 #endif /* STM32F373xC || STM32F378xx */
3317
3318
3319 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
3320 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
3321 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
3322 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
3323 /**
3324 * @brief Perform an ADC automatic self-calibration
3325 * Calibration prerequisite: ADC must be disabled (execute this
3326 * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
3327 * @param hadc ADC handle
3328 * @param SingleDiff Selection of single-ended or differential input
3329 * This parameter can be one of the following values:
3330 * @arg ADC_SINGLE_ENDED: Channel in mode input single ended
3331 * @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
3332 * @retval HAL status
3333 */
HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef * hadc,uint32_t SingleDiff)3334 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
3335 {
3336 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
3337 uint32_t tickstart;
3338
3339 /* Check the parameters */
3340 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3341 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
3342
3343 /* Process locked */
3344 __HAL_LOCK(hadc);
3345
3346 /* Calibration prerequisite: ADC must be disabled. */
3347
3348 /* Disable the ADC (if not already disabled) */
3349 tmp_hal_status = ADC_Disable(hadc);
3350
3351 /* Check if ADC is effectively disabled */
3352 if (tmp_hal_status == HAL_OK)
3353 {
3354 /* Change ADC state */
3355 hadc->State = HAL_ADC_STATE_READY;
3356
3357 /* Select calibration mode single ended or differential ended */
3358 hadc->Instance->CR &= (~ADC_CR_ADCALDIF);
3359 if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
3360 {
3361 hadc->Instance->CR |= ADC_CR_ADCALDIF;
3362 }
3363
3364 /* Start ADC calibration */
3365 hadc->Instance->CR |= ADC_CR_ADCAL;
3366
3367 tickstart = HAL_GetTick();
3368
3369 /* Wait for calibration completion */
3370 while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL))
3371 {
3372 if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
3373 {
3374 /* New check to avoid false timeout detection in case of preemption */
3375 if(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL))
3376 {
3377 /* Update ADC state machine to error */
3378 ADC_STATE_CLR_SET(hadc->State,
3379 HAL_ADC_STATE_BUSY_INTERNAL,
3380 HAL_ADC_STATE_ERROR_INTERNAL);
3381
3382 /* Process unlocked */
3383 __HAL_UNLOCK(hadc);
3384
3385 return HAL_ERROR;
3386 }
3387 }
3388 }
3389
3390 /* Set ADC state */
3391 ADC_STATE_CLR_SET(hadc->State,
3392 HAL_ADC_STATE_BUSY_INTERNAL,
3393 HAL_ADC_STATE_READY);
3394 }
3395
3396 /* Process unlocked */
3397 __HAL_UNLOCK(hadc);
3398
3399 /* Return function status */
3400 return tmp_hal_status;
3401 }
3402 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
3403 /* STM32F302xC || STM32F303xC || STM32F358xx || */
3404 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
3405 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
3406
3407 #if defined(STM32F373xC) || defined(STM32F378xx)
3408 /**
3409 * @brief Perform an ADC automatic self-calibration
3410 * Calibration prerequisite: ADC must be disabled (execute this
3411 * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
3412 * During calibration process, ADC is enabled. ADC is let enabled at
3413 * the completion of this function.
3414 * @param hadc ADC handle
3415 * @retval HAL status
3416 */
HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef * hadc)3417 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
3418 {
3419 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
3420 uint32_t tickstart;
3421 __IO uint32_t wait_loop_index = 0U;
3422
3423 /* Check the parameters */
3424 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3425
3426 /* Process locked */
3427 __HAL_LOCK(hadc);
3428
3429 /* 1. Calibration prerequisite: */
3430 /* - ADC must be disabled for at least two ADC clock cycles in disable */
3431 /* mode before ADC enable */
3432 /* Stop potential conversion on going, on regular and injected groups */
3433 /* Disable ADC peripheral */
3434 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
3435
3436 /* Check if ADC is effectively disabled */
3437 if (tmp_hal_status == HAL_OK)
3438 {
3439 /* Set ADC state */
3440 ADC_STATE_CLR_SET(hadc->State,
3441 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
3442 HAL_ADC_STATE_BUSY_INTERNAL);
3443
3444 /* Wait two ADC clock cycles */
3445 while(wait_loop_index < ADC_CYCLE_WORST_CASE_CPU_CYCLES *2U)
3446 {
3447 wait_loop_index++;
3448 }
3449
3450 /* 2. Enable the ADC peripheral */
3451 ADC_Enable(hadc);
3452
3453
3454 /* 3. Resets ADC calibration registers */
3455 SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL);
3456
3457 tickstart = HAL_GetTick();
3458
3459 /* Wait for calibration reset completion */
3460 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL))
3461 {
3462 if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
3463 {
3464 /* New check to avoid false timeout detection in case of preemption */
3465 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL))
3466 {
3467 /* Update ADC state machine to error */
3468 ADC_STATE_CLR_SET(hadc->State,
3469 HAL_ADC_STATE_BUSY_INTERNAL,
3470 HAL_ADC_STATE_ERROR_INTERNAL);
3471
3472 /* Process unlocked */
3473 __HAL_UNLOCK(hadc);
3474
3475 return HAL_ERROR;
3476 }
3477 }
3478 }
3479
3480
3481 /* 4. Start ADC calibration */
3482 SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL);
3483
3484 tickstart = HAL_GetTick();
3485
3486 /* Wait for calibration completion */
3487 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL))
3488 {
3489 if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
3490 {
3491 /* New check to avoid false timeout detection in case of preemption */
3492 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL))
3493 {
3494 /* Update ADC state machine to error */
3495 ADC_STATE_CLR_SET(hadc->State,
3496 HAL_ADC_STATE_BUSY_INTERNAL,
3497 HAL_ADC_STATE_ERROR_INTERNAL);
3498
3499 /* Process unlocked */
3500 __HAL_UNLOCK(hadc);
3501
3502 return HAL_ERROR;
3503 }
3504 }
3505 }
3506
3507 /* Set ADC state */
3508 ADC_STATE_CLR_SET(hadc->State,
3509 HAL_ADC_STATE_BUSY_INTERNAL,
3510 HAL_ADC_STATE_READY);
3511 }
3512
3513 /* Process unlocked */
3514 __HAL_UNLOCK(hadc);
3515
3516 /* Return function status */
3517 return tmp_hal_status;
3518 }
3519
3520 #endif /* STM32F373xC || STM32F378xx */
3521
3522 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
3523 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
3524 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
3525 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
3526 /**
3527 * @brief Get the calibration factor from automatic conversion result
3528 * @param hadc ADC handle
3529 * @param SingleDiff Selection of single-ended or differential input
3530 * This parameter can be one of the following values:
3531 * @arg ADC_SINGLE_ENDED: Channel in mode input single ended
3532 * @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
3533 * @retval Converted value
3534 */
HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef * hadc,uint32_t SingleDiff)3535 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
3536 {
3537 /* Check the parameters */
3538 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3539 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
3540
3541 /* Return the selected ADC calibration value */
3542 if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
3543 {
3544 return ADC_CALFACT_DIFF_GET(hadc->Instance->CALFACT);
3545 }
3546 else
3547 {
3548 return ((hadc->Instance->CALFACT) & ADC_CALFACT_CALFACT_S);
3549 }
3550 }
3551 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
3552 /* STM32F302xC || STM32F303xC || STM32F358xx || */
3553 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
3554 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
3555
3556 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
3557 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
3558 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
3559 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
3560 /**
3561 * @brief Set the calibration factor to overwrite automatic conversion result. ADC must be enabled and no conversion on going.
3562 * @param hadc ADC handle
3563 * @param SingleDiff Selection of single-ended or differential input
3564 * This parameter can be one of the following values:
3565 * @arg ADC_SINGLE_ENDED: Channel in mode input single ended
3566 * @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
3567 * @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
3568 * @retval HAL state
3569 */
HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef * hadc,uint32_t SingleDiff,uint32_t CalibrationFactor)3570 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
3571 {
3572 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
3573
3574 /* Check the parameters */
3575 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3576 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
3577 assert_param(IS_ADC_CALFACT(CalibrationFactor));
3578
3579 /* Process locked */
3580 __HAL_LOCK(hadc);
3581
3582 /* Verification of hardware constraints before modifying the calibration */
3583 /* factors register: ADC must be enabled, no conversion on going. */
3584 if ( (ADC_IS_ENABLE(hadc) != RESET) &&
3585 (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) )
3586 {
3587 /* Set the selected ADC calibration value */
3588 if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
3589 {
3590 MODIFY_REG(hadc->Instance->CALFACT ,
3591 ADC_CALFACT_CALFACT_D ,
3592 ADC_CALFACT_DIFF_SET(CalibrationFactor) );
3593 }
3594 else
3595 {
3596 MODIFY_REG(hadc->Instance->CALFACT,
3597 ADC_CALFACT_CALFACT_S ,
3598 CalibrationFactor );
3599 }
3600 }
3601 else
3602 {
3603 /* Update ADC state machine to error */
3604 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
3605
3606 /* Set ADC error code to ADC IP internal error */
3607 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3608 }
3609
3610 /* Process unlocked */
3611 __HAL_UNLOCK(hadc);
3612
3613 /* Return function status */
3614 return tmp_hal_status;
3615 }
3616 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
3617 /* STM32F302xC || STM32F303xC || STM32F358xx || */
3618 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
3619 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
3620
3621 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
3622 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
3623 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
3624 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
3625 /**
3626 * @brief Enables ADC, starts conversion of injected group.
3627 * Interruptions enabled in this function: None.
3628 * @note Case of multimode enabled (for devices with several ADCs): This
3629 * function must be called for ADC slave first, then ADC master.
3630 * For ADC slave, ADC is enabled only (conversion is not started).
3631 * For ADC master, ADC is enabled and multimode conversion is started.
3632 * @param hadc ADC handle
3633 * @retval HAL status
3634 */
HAL_ADCEx_InjectedStart(ADC_HandleTypeDef * hadc)3635 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
3636 {
3637 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
3638
3639 /* Check the parameters */
3640 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3641
3642 /* Perform ADC enable and conversion start if no conversion is on going */
3643 if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
3644 {
3645 /* Process locked */
3646 __HAL_LOCK(hadc);
3647
3648 /* Enable the ADC peripheral */
3649 tmp_hal_status = ADC_Enable(hadc);
3650
3651 /* Start conversion if ADC is effectively enabled */
3652 if (tmp_hal_status == HAL_OK)
3653 {
3654 /* Set ADC state */
3655 /* - Clear state bitfield related to injected group conversion results */
3656 /* - Set state bitfield related to injected operation */
3657 ADC_STATE_CLR_SET(hadc->State,
3658 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
3659 HAL_ADC_STATE_INJ_BUSY);
3660
3661 /* Case of independent mode or multimode(for devices with several ADCs):*/
3662 /* Set multimode state. */
3663 if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
3664 {
3665 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
3666 }
3667 else
3668 {
3669 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
3670 }
3671
3672 /* Check if a regular conversion is ongoing */
3673 /* Note: On this device, there is no ADC error code fields related to */
3674 /* conversions on group injected only. In case of conversion on */
3675 /* going on group regular, no error code is reset. */
3676 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
3677 {
3678 /* Reset ADC all error code fields */
3679 ADC_CLEAR_ERRORCODE(hadc);
3680 }
3681
3682 /* Process unlocked */
3683 /* Unlock before starting ADC conversions: in case of potential */
3684 /* interruption, to let the process to ADC IRQ Handler. */
3685 __HAL_UNLOCK(hadc);
3686
3687 /* Clear injected group conversion flag */
3688 /* (To ensure of no unknown state from potential previous ADC */
3689 /* operations) */
3690 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
3691
3692 /* Enable conversion of injected group, if automatic injected */
3693 /* conversion is disabled. */
3694 /* If software start has been selected, conversion starts immediately. */
3695 /* If external trigger has been selected, conversion will start at next */
3696 /* trigger event. */
3697 /* Case of multimode enabled (for devices with several ADCs): */
3698 /* - if ADC is slave, ADC is enabled only (conversion is not started). */
3699 /* - if ADC is master, ADC is enabled and conversion is started. */
3700 if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO) &&
3701 ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(hadc) )
3702 {
3703 SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART);
3704 }
3705 }
3706 else
3707 {
3708 /* Process unlocked */
3709 __HAL_UNLOCK(hadc);
3710 }
3711 }
3712 else
3713 {
3714 tmp_hal_status = HAL_BUSY;
3715 }
3716
3717 /* Return function status */
3718 return tmp_hal_status;
3719 }
3720 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
3721 /* STM32F302xC || STM32F303xC || STM32F358xx || */
3722 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
3723 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
3724
3725 #if defined(STM32F373xC) || defined(STM32F378xx)
3726 /**
3727 * @brief Enables ADC, starts conversion of injected group.
3728 * Interruptions enabled in this function: None.
3729 * @param hadc ADC handle
3730 * @retval HAL status
3731 */
HAL_ADCEx_InjectedStart(ADC_HandleTypeDef * hadc)3732 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
3733 {
3734 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
3735
3736 /* Check the parameters */
3737 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3738
3739 /* Process locked */
3740 __HAL_LOCK(hadc);
3741
3742 /* Enable the ADC peripheral */
3743 tmp_hal_status = ADC_Enable(hadc);
3744
3745 /* Start conversion if ADC is effectively enabled */
3746 if (tmp_hal_status == HAL_OK)
3747 {
3748 /* Set ADC state */
3749 /* - Clear state bitfield related to injected group conversion results */
3750 /* - Set state bitfield related to injected operation */
3751 ADC_STATE_CLR_SET(hadc->State,
3752 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
3753 HAL_ADC_STATE_INJ_BUSY);
3754
3755 /* Check if a regular conversion is ongoing */
3756 /* Note: On this device, there is no ADC error code fields related to */
3757 /* conversions on group injected only. In case of conversion on */
3758 /* going on group regular, no error code is reset. */
3759 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
3760 {
3761 /* Reset ADC all error code fields */
3762 ADC_CLEAR_ERRORCODE(hadc);
3763 }
3764
3765 /* Process unlocked */
3766 /* Unlock before starting ADC conversions: in case of potential */
3767 /* interruption, to let the process to ADC IRQ Handler. */
3768 __HAL_UNLOCK(hadc);
3769
3770 /* Clear injected group conversion flag */
3771 /* (To ensure of no unknown state from potential previous ADC operations) */
3772 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
3773
3774 /* Enable conversion of injected group. */
3775 /* If software start has been selected, conversion starts immediately. */
3776 /* If external trigger has been selected, conversion will start at next */
3777 /* trigger event. */
3778 /* If external trigger has been selected, conversion will start at next */
3779 /* trigger event. */
3780 /* If automatic injected conversion is enabled, conversion will start */
3781 /* after next regular group conversion. */
3782 if (ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
3783 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
3784 {
3785 /* Start ADC conversion on injected group with SW start */
3786 SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
3787 }
3788 else
3789 {
3790 /* Start ADC conversion on injected group with external trigger */
3791 SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
3792 }
3793 }
3794
3795 /* Return function status */
3796 return tmp_hal_status;
3797 }
3798 #endif /* STM32F373xC || STM32F378xx */
3799
3800 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
3801 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
3802 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
3803 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
3804 /**
3805 * @brief Stop ADC group injected conversion (potential conversion on going
3806 * on ADC group regular is not impacted), disable ADC peripheral
3807 * if no conversion is on going on group regular.
3808 * @note To stop ADC conversion of both groups regular and injected and to
3809 * to disable ADC peripheral, instead of using 2 functions
3810 * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
3811 * use function @ref HAL_ADC_Stop().
3812 * @note If injected group mode auto-injection is enabled,
3813 * function HAL_ADC_Stop must be used.
3814 * @note Case of multimode enabled (for devices with several ADCs): This
3815 * function must be called for ADC master first, then ADC slave.
3816 * For ADC master, conversion is stopped and ADC is disabled.
3817 * For ADC slave, ADC is disabled only (conversion stop of ADC master
3818 * has already stopped conversion of ADC slave).
3819 * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
3820 * @param hadc ADC handle
3821 * @retval None
3822 */
HAL_ADCEx_InjectedStop(ADC_HandleTypeDef * hadc)3823 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
3824 {
3825 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
3826
3827 /* Check the parameters */
3828 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3829
3830 /* Process locked */
3831 __HAL_LOCK(hadc);
3832
3833 /* Stop potential ADC conversion on going and disable ADC peripheral */
3834 /* conditioned to: */
3835 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
3836 /* - For ADC injected group conversion stop: */
3837 /* On this STM32 family, conversion on the other group */
3838 /* (group regular) can continue (groups regular and injected */
3839 /* conversion stop commands are independent) */
3840 /* - For ADC disable: */
3841 /* No conversion on the other group (group regular) must be intended to */
3842 /* continue (groups regular and injected are both impacted by */
3843 /* ADC disable) */
3844 if(HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
3845 {
3846 /* 1. Stop potential conversion on going on injected group only. */
3847 tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
3848
3849 /* Disable ADC peripheral if conversion on ADC group injected is */
3850 /* effectively stopped and if no conversion on the other group */
3851 /* (ADC group regular) is intended to continue. */
3852 if (tmp_hal_status == HAL_OK)
3853 {
3854 if((ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) &&
3855 ((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) )
3856 {
3857 /* 2. Disable the ADC peripheral */
3858 tmp_hal_status = ADC_Disable(hadc);
3859
3860 /* Check if ADC is effectively disabled */
3861 if (tmp_hal_status == HAL_OK)
3862 {
3863 /* Set ADC state */
3864 ADC_STATE_CLR_SET(hadc->State,
3865 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
3866 HAL_ADC_STATE_READY);
3867 }
3868 }
3869 /* Conversion on ADC group injected group is stopped, but ADC is not */
3870 /* disabled since conversion on ADC group regular is still on going. */
3871 else
3872 {
3873 /* Set ADC state */
3874 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
3875 }
3876 }
3877 }
3878 else
3879 {
3880 /* Update ADC state machine to error */
3881 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
3882
3883 tmp_hal_status = HAL_ERROR;
3884 }
3885
3886 /* Process unlocked */
3887 __HAL_UNLOCK(hadc);
3888
3889 /* Return function status */
3890 return tmp_hal_status;
3891 }
3892 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
3893 /* STM32F302xC || STM32F303xC || STM32F358xx || */
3894 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
3895 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
3896
3897 #if defined(STM32F373xC) || defined(STM32F378xx)
3898 /**
3899 * @brief Stop conversion of injected channels. Disable ADC peripheral if
3900 * no regular conversion is on going.
3901 * @note If ADC must be disabled and if conversion is on going on
3902 * regular group, function HAL_ADC_Stop must be used to stop both
3903 * injected and regular groups, and disable the ADC.
3904 * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
3905 * @param hadc ADC handle
3906 * @retval None
3907 */
HAL_ADCEx_InjectedStop(ADC_HandleTypeDef * hadc)3908 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
3909 {
3910 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
3911
3912 /* Check the parameters */
3913 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3914
3915 /* Process locked */
3916 __HAL_LOCK(hadc);
3917
3918 /* Stop potential conversion and disable ADC peripheral */
3919 /* Conditioned to: */
3920 /* - No conversion on the other group (regular group) is intended to */
3921 /* continue (injected and regular groups stop conversion and ADC disable */
3922 /* are common) */
3923 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
3924 if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
3925 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
3926 {
3927 /* Stop potential conversion on going, on regular and injected groups */
3928 /* Disable ADC peripheral */
3929 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
3930
3931 /* Check if ADC is effectively disabled */
3932 if (tmp_hal_status == HAL_OK)
3933 {
3934 /* Set ADC state */
3935 ADC_STATE_CLR_SET(hadc->State,
3936 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
3937 HAL_ADC_STATE_READY);
3938 }
3939 }
3940 else
3941 {
3942 /* Update ADC state machine to error */
3943 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
3944
3945 tmp_hal_status = HAL_ERROR;
3946 }
3947
3948 /* Process unlocked */
3949 __HAL_UNLOCK(hadc);
3950
3951 /* Return function status */
3952 return tmp_hal_status;
3953 }
3954 #endif /* STM32F373xC || STM32F378xx */
3955
3956 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
3957 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
3958 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
3959 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
3960 /**
3961 * @brief Wait for injected group conversion to be completed.
3962 * @param hadc ADC handle
3963 * @param Timeout Timeout value in millisecond.
3964 * @retval HAL status
3965 */
HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef * hadc,uint32_t Timeout)3966 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
3967 {
3968 uint32_t tickstart;
3969 uint32_t tmp_Flag_EOC;
3970 uint32_t tmp_cfgr = 0x00000000U;
3971
3972 /* Check the parameters */
3973 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3974
3975 /* If end of conversion selected to end of sequence */
3976 if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
3977 {
3978 tmp_Flag_EOC = ADC_FLAG_JEOS;
3979 }
3980 /* If end of conversion selected to end of each conversion */
3981 else /* ADC_EOC_SINGLE_CONV */
3982 {
3983 tmp_Flag_EOC = (ADC_FLAG_JEOC | ADC_FLAG_JEOS);
3984 }
3985
3986 /* Get relevant register CFGR in ADC instance of ADC master or slave */
3987 /* in function of multimode state (for devices with multimode */
3988 /* available). */
3989 if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
3990 {
3991 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
3992 }
3993 else
3994 {
3995 tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
3996 }
3997
3998 /* Get tick count */
3999 tickstart = HAL_GetTick();
4000
4001 /* Wait until End of Conversion flag is raised */
4002 while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
4003 {
4004 /* Check if timeout is disabled (set to infinite wait) */
4005 if(Timeout != HAL_MAX_DELAY)
4006 {
4007 if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
4008 {
4009 /* New check to avoid false timeout detection in case of preemption */
4010 if(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
4011 {
4012 /* Update ADC state machine to timeout */
4013 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
4014
4015 /* Process unlocked */
4016 __HAL_UNLOCK(hadc);
4017
4018 return HAL_TIMEOUT;
4019 }
4020 }
4021 }
4022 }
4023
4024 /* Update ADC state machine */
4025 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
4026
4027 /* Determine whether any further conversion upcoming on group injected */
4028 /* by external trigger or by automatic injected conversion */
4029 /* from group regular. */
4030 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) ||
4031 ((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) &&
4032 (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
4033 (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) ) )
4034 {
4035 /* Set ADC state */
4036 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
4037
4038 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
4039 {
4040 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
4041 }
4042 }
4043
4044 /* Clear end of conversion flag of injected group if low power feature */
4045 /* "Auto Wait" is disabled, to not interfere with this feature until data */
4046 /* register is read using function HAL_ADC_GetValue(). */
4047 if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET)
4048 {
4049 /* Clear injected group conversion flag */
4050 /* (JEOC or JEOS depending on HAL ADC initialization parameter) */
4051 __HAL_ADC_CLEAR_FLAG(hadc, tmp_Flag_EOC);
4052 }
4053
4054 /* Return ADC state */
4055 return HAL_OK;
4056 }
4057 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
4058 /* STM32F302xC || STM32F303xC || STM32F358xx || */
4059 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
4060 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
4061
4062 #if defined(STM32F373xC) || defined(STM32F378xx)
4063 /**
4064 * @brief Wait for injected group conversion to be completed.
4065 * @param hadc ADC handle
4066 * @param Timeout Timeout value in millisecond.
4067 * @retval HAL status
4068 */
HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef * hadc,uint32_t Timeout)4069 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
4070 {
4071 uint32_t tickstart = 0U;
4072
4073 /* Variables for polling in case of scan mode enabled */
4074 uint32_t Conversion_Timeout_CPU_cycles_max =0U;
4075 uint32_t Conversion_Timeout_CPU_cycles =0U;
4076
4077 /* Check the parameters */
4078 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
4079
4080 /* Get tick count */
4081 tickstart = HAL_GetTick();
4082
4083 /* Polling for end of conversion: differentiation if single/sequence */
4084 /* conversion. */
4085 /* For injected group, flag JEOC is set only at the end of the sequence, */
4086 /* not for each conversion within the sequence. */
4087 /* - If single conversion for injected group (scan mode disabled or */
4088 /* InjectedNbrOfConversion ==1U), flag JEOC is used to determine the */
4089 /* conversion completion. */
4090 /* - If sequence conversion for injected group (scan mode enabled and */
4091 /* InjectedNbrOfConversion >=2U), flag JEOC is set only at the end of the */
4092 /* sequence. */
4093 /* To poll for each conversion, the maximum conversion time is computed */
4094 /* from ADC conversion time (selected sampling time + conversion time of */
4095 /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */
4096 /* settings, conversion time range can be from 28 to 32256 CPU cycles). */
4097 /* As flag JEOC is not set after each conversion, no timeout status can */
4098 /* be set. */
4099 if ((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET)
4100 {
4101 /* Wait until End of Conversion flag is raised */
4102 while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC))
4103 {
4104 /* Check if timeout is disabled (set to infinite wait) */
4105 if(Timeout != HAL_MAX_DELAY)
4106 {
4107 if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
4108 {
4109 /* New check to avoid false timeout detection in case of preemption */
4110 if(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC))
4111 {
4112 /* Update ADC state machine to timeout */
4113 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
4114
4115 /* Process unlocked */
4116 __HAL_UNLOCK(hadc);
4117
4118 return HAL_TIMEOUT;
4119 }
4120 }
4121 }
4122 }
4123 }
4124 else
4125 {
4126 /* Replace polling by wait for maximum conversion time */
4127 /* Calculation of CPU cycles corresponding to ADC conversion cycles. */
4128 /* Retrieve ADC clock prescaler and ADC maximum conversion cycles on all */
4129 /* channels. */
4130 Conversion_Timeout_CPU_cycles_max = ADC_CLOCK_PRESCALER_RANGE();
4131 Conversion_Timeout_CPU_cycles_max *= ADC_CONVCYCLES_MAX_RANGE(hadc);
4132
4133 /* Poll with maximum conversion time */
4134 while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
4135 {
4136 /* Check if timeout is disabled (set to infinite wait) */
4137 if(Timeout != HAL_MAX_DELAY)
4138 {
4139 if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
4140 {
4141 /* New check to avoid false timeout detection in case of preemption */
4142 if(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
4143 {
4144 /* Update ADC state machine to timeout */
4145 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
4146
4147 /* Process unlocked */
4148 __HAL_UNLOCK(hadc);
4149
4150 return HAL_TIMEOUT;
4151 }
4152 }
4153 }
4154 Conversion_Timeout_CPU_cycles ++;
4155 }
4156 }
4157
4158
4159 /* Clear injected group conversion flag (and regular conversion flag raised simultaneously) */
4160 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC | ADC_FLAG_EOC);
4161
4162 /* Update ADC state machine */
4163 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
4164
4165 /* Determine whether any further conversion upcoming on group injected */
4166 /* by external trigger or by automatic injected conversion */
4167 /* from group regular. */
4168 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) ||
4169 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
4170 (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
4171 (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
4172 {
4173 /* Set ADC state */
4174 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
4175
4176 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
4177 {
4178 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
4179 }
4180 }
4181
4182 /* Return ADC state */
4183 return HAL_OK;
4184 }
4185 #endif /* STM32F373xC || STM32F378xx */
4186
4187 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
4188 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
4189 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
4190 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
4191 /**
4192 * @brief Enables ADC, starts conversion of injected group with interruption.
4193 * Interruptions enabled in this function:
4194 * - JEOC (end of conversion of injected group) or JEOS (end of
4195 * sequence of injected group) depending on ADC initialization
4196 * parameter "EOCSelection"
4197 * Each of these interruptions has its dedicated callback function.
4198 * @note Case of multimode enabled (for devices with several ADCs): This
4199 * function must be called for ADC slave first, then ADC master.
4200 * For ADC slave, ADC is enabled only (conversion is not started).
4201 * For ADC master, ADC is enabled and multimode conversion is started.
4202 * @param hadc ADC handle
4203 * @retval HAL status.
4204 */
HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef * hadc)4205 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
4206 {
4207 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
4208
4209 /* Check the parameters */
4210 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
4211
4212 /* Perform ADC enable and conversion start if no conversion is on going */
4213 if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
4214 {
4215 /* Process locked */
4216 __HAL_LOCK(hadc);
4217
4218 /* Enable the ADC peripheral */
4219 tmp_hal_status = ADC_Enable(hadc);
4220
4221 /* Start conversion if ADC is effectively enabled */
4222 /* Start conversion if ADC is effectively enabled */
4223 if (tmp_hal_status == HAL_OK)
4224 {
4225 /* Set ADC state */
4226 /* - Clear state bitfield related to injected group conversion results */
4227 /* - Set state bitfield related to injected operation */
4228 ADC_STATE_CLR_SET(hadc->State,
4229 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
4230 HAL_ADC_STATE_INJ_BUSY);
4231
4232 /* Case of independent mode or multimode(for devices with several ADCs):*/
4233 /* Set multimode state. */
4234 if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
4235 {
4236 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
4237 }
4238 else
4239 {
4240 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
4241 }
4242
4243 /* Check if a regular conversion is ongoing */
4244 /* Note: On this device, there is no ADC error code fields related to */
4245 /* conversions on group injected only. In case of conversion on */
4246 /* going on group regular, no error code is reset. */
4247 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
4248 {
4249 /* Reset ADC all error code fields */
4250 ADC_CLEAR_ERRORCODE(hadc);
4251 }
4252
4253 /* Process unlocked */
4254 /* Unlock before starting ADC conversions: in case of potential */
4255 /* interruption, to let the process to ADC IRQ Handler. */
4256 __HAL_UNLOCK(hadc);
4257
4258 /* Clear injected group conversion flag */
4259 /* (To ensure of no unknown state from potential previous ADC */
4260 /* operations) */
4261 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
4262
4263 /* Enable ADC Injected context queue overflow interrupt if this feature */
4264 /* is enabled. */
4265 if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != RESET)
4266 {
4267 __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
4268 }
4269
4270 /* Enable ADC end of conversion interrupt */
4271 switch(hadc->Init.EOCSelection)
4272 {
4273 case ADC_EOC_SEQ_CONV:
4274 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
4275 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
4276 break;
4277 /* case ADC_EOC_SINGLE_CONV */
4278 default:
4279 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
4280 break;
4281 }
4282
4283 /* Enable conversion of injected group, if automatic injected */
4284 /* conversion is disabled. */
4285 /* If software start has been selected, conversion starts immediately. */
4286 /* If external trigger has been selected, conversion will start at next */
4287 /* trigger event. */
4288 /* Case of multimode enabled (for devices with several ADCs): */
4289 /* - if ADC is slave, ADC is enabled only (conversion is not started). */
4290 /* - if ADC is master, ADC is enabled and conversion is started. */
4291 if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO) &&
4292 ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(hadc) )
4293 {
4294 SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART);
4295 }
4296 }
4297 else
4298 {
4299 /* Process unlocked */
4300 __HAL_UNLOCK(hadc);
4301 }
4302 }
4303 else
4304 {
4305 tmp_hal_status = HAL_BUSY;
4306 }
4307
4308 /* Return function status */
4309 return tmp_hal_status;
4310 }
4311 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
4312 /* STM32F302xC || STM32F303xC || STM32F358xx || */
4313 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
4314 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
4315
4316 #if defined(STM32F373xC) || defined(STM32F378xx)
4317 /**
4318 * @brief Enables ADC, starts conversion of injected group with interruption.
4319 * Interruptions enabled in this function:
4320 * - JEOC (end of conversion of injected group)
4321 * Each of these interruptions has its dedicated callback function.
4322 * @param hadc ADC handle
4323 * @retval HAL status.
4324 */
HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef * hadc)4325 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
4326 {
4327 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
4328
4329 /* Check the parameters */
4330 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
4331
4332 /* Process locked */
4333 __HAL_LOCK(hadc);
4334
4335 /* Enable the ADC peripheral */
4336 tmp_hal_status = ADC_Enable(hadc);
4337
4338 /* Start conversion if ADC is effectively enabled */
4339 if (tmp_hal_status == HAL_OK)
4340 {
4341 /* Set ADC state */
4342 /* - Clear state bitfield related to injected group conversion results */
4343 /* - Set state bitfield related to injected operation */
4344 ADC_STATE_CLR_SET(hadc->State,
4345 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
4346 HAL_ADC_STATE_INJ_BUSY);
4347
4348 /* Check if a regular conversion is ongoing */
4349 /* Note: On this device, there is no ADC error code fields related to */
4350 /* conversions on group injected only. In case of conversion on */
4351 /* going on group regular, no error code is reset. */
4352 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
4353 {
4354 /* Reset ADC all error code fields */
4355 ADC_CLEAR_ERRORCODE(hadc);
4356 }
4357
4358 /* Process unlocked */
4359 /* Unlock before starting ADC conversions: in case of potential */
4360 /* interruption, to let the process to ADC IRQ Handler. */
4361 __HAL_UNLOCK(hadc);
4362
4363 /* Set ADC error code to none */
4364 ADC_CLEAR_ERRORCODE(hadc);
4365
4366 /* Clear injected group conversion flag */
4367 /* (To ensure of no unknown state from potential previous ADC operations) */
4368 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
4369
4370 /* Enable end of conversion interrupt for injected channels */
4371 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
4372
4373 /* Enable conversion of injected group. */
4374 /* If software start has been selected, conversion starts immediately. */
4375 /* If external trigger has been selected, conversion will start at next */
4376 /* trigger event. */
4377 /* If external trigger has been selected, conversion will start at next */
4378 /* trigger event. */
4379 /* If automatic injected conversion is enabled, conversion will start */
4380 /* after next regular group conversion. */
4381 if (ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
4382 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
4383 {
4384 /* Start ADC conversion on injected group with SW start */
4385 SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
4386 }
4387 else
4388 {
4389 /* Start ADC conversion on injected group with external trigger */
4390 SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
4391 }
4392 }
4393
4394 /* Return function status */
4395 return tmp_hal_status;
4396 }
4397 #endif /* STM32F373xC || STM32F378xx */
4398
4399 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
4400 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
4401 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
4402 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
4403 /**
4404 * @brief Stop ADC group injected conversion (potential conversion on going
4405 * on ADC group regular is not impacted), disable ADC peripheral
4406 * if no conversion is on going on group regular.
4407 * Interruptions disabled in this function:
4408 * - JEOC (end of conversion of injected group) and JEOS (end of
4409 * sequence of injected group)
4410 * @note To stop ADC conversion of both groups regular and injected and to
4411 * to disable ADC peripheral, instead of using 2 functions
4412 * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
4413 * use function @ref HAL_ADC_Stop().
4414 * @note If injected group mode auto-injection is enabled,
4415 * function HAL_ADC_Stop must be used.
4416 * @note Case of multimode enabled (for devices with several ADCs): This
4417 * function must be called for ADC master first, then ADC slave.
4418 * For ADC master, conversion is stopped and ADC is disabled.
4419 * For ADC slave, ADC is disabled only (conversion stop of ADC master
4420 * has already stopped conversion of ADC slave).
4421 * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
4422 * @param hadc ADC handle
4423 * @retval None
4424 */
HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef * hadc)4425 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
4426 {
4427 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
4428
4429 /* Check the parameters */
4430 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
4431
4432 /* Process locked */
4433 __HAL_LOCK(hadc);
4434
4435 /* Stop potential ADC conversion on going and disable ADC peripheral */
4436 /* conditioned to: */
4437 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
4438 /* - For ADC injected group conversion stop: */
4439 /* On this STM32 family, conversion on the other group */
4440 /* (group regular) can continue (groups regular and injected */
4441 /* conversion stop commands are independent) */
4442 /* - For ADC disable: */
4443 /* No conversion on the other group (group regular) must be intended to */
4444 /* continue (groups regular and injected are both impacted by */
4445 /* ADC disable) */
4446 if(HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
4447 {
4448 /* 1. Stop potential conversion on going on injected group only. */
4449 tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
4450
4451 /* Disable ADC peripheral if conversion on ADC group injected is */
4452 /* effectively stopped and if no conversion on the other group */
4453 /* (ADC group regular) is intended to continue. */
4454 if (tmp_hal_status == HAL_OK)
4455 {
4456 /* Disable ADC end of conversion interrupt for injected channels */
4457 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_IT_JQOVF));
4458
4459 if((ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) &&
4460 ((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) )
4461 {
4462 /* 2. Disable the ADC peripheral */
4463 tmp_hal_status = ADC_Disable(hadc);
4464
4465 /* Check if ADC is effectively disabled */
4466 if (tmp_hal_status == HAL_OK)
4467 {
4468 /* Set ADC state */
4469 ADC_STATE_CLR_SET(hadc->State,
4470 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
4471 HAL_ADC_STATE_READY);
4472 }
4473 }
4474 /* Conversion on ADC group injected group is stopped, but ADC is not */
4475 /* disabled since conversion on ADC group regular is still on going. */
4476 else
4477 {
4478 /* Set ADC state */
4479 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
4480 }
4481 }
4482 }
4483 else
4484 {
4485 /* Update ADC state machine to error */
4486 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
4487
4488 tmp_hal_status = HAL_ERROR;
4489 }
4490
4491 /* Process unlocked */
4492 __HAL_UNLOCK(hadc);
4493
4494 /* Return function status */
4495 return tmp_hal_status;
4496 }
4497 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
4498 /* STM32F302xC || STM32F303xC || STM32F358xx || */
4499 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
4500 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
4501
4502 #if defined(STM32F373xC) || defined(STM32F378xx)
4503 /**
4504 * @brief Stop conversion of injected channels, disable interruption of
4505 * end-of-conversion. Disable ADC peripheral if no regular conversion
4506 * is on going.
4507 * @note If ADC must be disabled and if conversion is on going on
4508 * regular group, function HAL_ADC_Stop must be used to stop both
4509 * injected and regular groups, and disable the ADC.
4510 * @param hadc ADC handle
4511 * @retval None
4512 */
HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef * hadc)4513 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
4514 {
4515 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
4516
4517 /* Check the parameters */
4518 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
4519
4520 /* Process locked */
4521 __HAL_LOCK(hadc);
4522
4523 /* Stop potential conversion and disable ADC peripheral */
4524 /* Conditioned to: */
4525 /* - No conversion on the other group (regular group) is intended to */
4526 /* continue (injected and regular groups stop conversion and ADC disable */
4527 /* are common) */
4528 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
4529 if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
4530 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
4531 {
4532 /* Stop potential conversion on going, on regular and injected groups */
4533 /* Disable ADC peripheral */
4534 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
4535
4536 /* Check if ADC is effectively disabled */
4537 if (tmp_hal_status == HAL_OK)
4538 {
4539 /* Disable ADC end of conversion interrupt for injected channels */
4540 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
4541
4542 /* Set ADC state */
4543 ADC_STATE_CLR_SET(hadc->State,
4544 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
4545 HAL_ADC_STATE_READY);
4546 }
4547 }
4548 else
4549 {
4550 /* Update ADC state machine to error */
4551 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
4552
4553 tmp_hal_status = HAL_ERROR;
4554 }
4555
4556 /* Process unlocked */
4557 __HAL_UNLOCK(hadc);
4558
4559 /* Return function status */
4560 return tmp_hal_status;
4561 }
4562 #endif /* STM32F373xC || STM32F378xx */
4563
4564 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
4565 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
4566 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
4567 /**
4568 * @brief With ADC configured in multimode, for ADC master:
4569 * Enables ADC, starts conversion of regular group and transfers result
4570 * through DMA.
4571 * Multimode must have been previously configured using
4572 * HAL_ADCEx_MultiModeConfigChannel() function.
4573 * Interruptions enabled in this function:
4574 * - DMA transfer complete
4575 * - DMA half transfer
4576 * - overrun
4577 * Each of these interruptions has its dedicated callback function.
4578 * @note ADC slave must be preliminarily enabled using single-mode
4579 * HAL_ADC_Start() function.
4580 * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
4581 * @param pData The destination Buffer address.
4582 * @param Length The length of data to be transferred from ADC peripheral to memory.
4583 * @retval None
4584 */
HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef * hadc,uint32_t * pData,uint32_t Length)4585 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
4586 {
4587 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
4588 ADC_HandleTypeDef tmphadcSlave = {0};
4589 ADC_Common_TypeDef *tmpADC_Common;
4590
4591 /* Check the parameters */
4592 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
4593 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
4594 assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
4595 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
4596
4597 /* Process locked */
4598 __HAL_LOCK(hadc);
4599
4600 /* Perform ADC enable and conversion start if no conversion is on going */
4601 /* (check on ADC master only) */
4602 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
4603 {
4604 /* Set a temporary handle of the ADC slave associated to the ADC master */
4605 /* (Depending on STM32F3 product, there may be up to 2 ADC slaves) */
4606 ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
4607
4608 if (tmphadcSlave.Instance == NULL)
4609 {
4610 /* Update ADC state machine to error */
4611 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
4612
4613 /* Process unlocked */
4614 __HAL_UNLOCK(hadc);
4615
4616 return HAL_ERROR;
4617 }
4618
4619
4620 /* Enable the ADC peripherals: master and slave (in case if not already */
4621 /* enabled previously) */
4622 tmp_hal_status = ADC_Enable(hadc);
4623 if (tmp_hal_status == HAL_OK)
4624 {
4625 tmp_hal_status = ADC_Enable(&tmphadcSlave);
4626 }
4627
4628 /* Start conversion all ADCs of multimode are effectively enabled */
4629 if (tmp_hal_status == HAL_OK)
4630 {
4631 /* Set ADC state (ADC master) */
4632 /* - Clear state bitfield related to regular group conversion results */
4633 /* - Set state bitfield related to regular operation */
4634 ADC_STATE_CLR_SET(hadc->State,
4635 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP | HAL_ADC_STATE_MULTIMODE_SLAVE,
4636 HAL_ADC_STATE_REG_BUSY);
4637
4638 /* If conversions on group regular are also triggering group injected, */
4639 /* update ADC state. */
4640 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
4641 {
4642 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
4643 }
4644
4645 /* Process unlocked */
4646 /* Unlock before starting ADC conversions: in case of potential */
4647 /* interruption, to let the process to ADC IRQ Handler. */
4648 __HAL_UNLOCK(hadc);
4649
4650 /* Set ADC error code to none */
4651 ADC_CLEAR_ERRORCODE(hadc);
4652
4653
4654 /* Set the DMA transfer complete callback */
4655 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
4656
4657 /* Set the DMA half transfer complete callback */
4658 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
4659
4660 /* Set the DMA error callback */
4661 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
4662
4663 /* Pointer to the common control register to which is belonging hadc */
4664 /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
4665 /* control registers) */
4666 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
4667
4668
4669 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
4670 /* start (in case of SW start): */
4671
4672 /* Clear regular group conversion flag and overrun flag */
4673 /* (To ensure of no unknown state from potential previous ADC operations) */
4674 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
4675
4676 /* Enable ADC overrun interrupt */
4677 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
4678
4679 /* Start the DMA channel */
4680 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
4681
4682 /* Enable conversion of regular group. */
4683 /* If software start has been selected, conversion starts immediately. */
4684 /* If external trigger has been selected, conversion will start at next */
4685 /* trigger event. */
4686 SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
4687
4688 }
4689 else
4690 {
4691 /* Process unlocked */
4692 __HAL_UNLOCK(hadc);
4693 }
4694 }
4695 else
4696 {
4697 tmp_hal_status = HAL_BUSY;
4698 }
4699
4700 /* Return function status */
4701 return tmp_hal_status;
4702 }
4703
4704 /**
4705 * @brief With ADC configured in multimode, for ADC master:
4706 * Stop ADC group regular conversion (potential conversion on going
4707 * on ADC group injected is not impacted),
4708 * disable ADC DMA transfer, disable ADC peripheral
4709 * if no conversion is on going on group injected.
4710 * Interruptions disabled in this function:
4711 * - DMA transfer complete
4712 * - DMA half transfer
4713 * - overrun
4714 * @note In case of auto-injection mode, this function also stop conversion
4715 * on ADC group injected.
4716 * @note Multimode is kept enabled after this function. To disable multimode
4717 * (set with HAL_ADCEx_MultiModeConfigChannel() ), ADC must be
4718 * reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit().
4719 * @note In case of DMA configured in circular mode, function
4720 * HAL_ADC_Stop_DMA must be called after this function with handle of
4721 * ADC slave, to properly disable the DMA channel of ADC slave.
4722 * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
4723 * @retval None
4724 */
HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef * hadc)4725 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
4726 {
4727 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
4728 uint32_t tickstart;
4729 ADC_HandleTypeDef tmphadcSlave = {0};
4730
4731 /* Check the parameters */
4732 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
4733
4734 /* Process locked */
4735 __HAL_LOCK(hadc);
4736
4737 /* 1. Stop potential multimode conversion on going, on regular and */
4738 /* injected groups. */
4739 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
4740
4741 /* Disable ADC peripheral if conversions are effectively stopped */
4742 if (tmp_hal_status == HAL_OK)
4743 {
4744 /* Set a temporary handle of the ADC slave associated to the ADC master */
4745 /* (Depending on STM32F3 product, there may be up to 2 ADC slaves) */
4746 ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
4747
4748 if (tmphadcSlave.Instance == NULL)
4749 {
4750 /* Update ADC state machine (ADC master) to error */
4751 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
4752
4753 /* Process unlocked */
4754 __HAL_UNLOCK(hadc);
4755
4756 return HAL_ERROR;
4757 }
4758
4759 /* Procedure to disable the ADC peripheral: wait for conversions */
4760 /* effectively stopped (ADC master and ADC slave), then disable ADC */
4761
4762 /* 1. Wait until ADSTP=0 for ADC master and ADC slave */
4763 tickstart = HAL_GetTick();
4764
4765 while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) ||
4766 ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) )
4767 {
4768 if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
4769 {
4770 /* New check to avoid false timeout detection in case of preemption */
4771 if(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) ||
4772 ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) )
4773 {
4774 /* Update ADC state machine (ADC master) to error */
4775 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
4776
4777 /* Process unlocked */
4778 __HAL_UNLOCK(hadc);
4779
4780 return HAL_ERROR;
4781 }
4782 }
4783 }
4784
4785 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
4786 /* while DMA transfer is on going) */
4787 /* Note: In case of ADC slave using its own DMA channel (multimode */
4788 /* parameter "DMAAccessMode" set to disabled): */
4789 /* DMA channel of ADC slave should stopped after this function with */
4790 /* function HAL_ADC_Stop_DMA. */
4791 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
4792
4793 /* Check if DMA channel effectively disabled */
4794 if (tmp_hal_status != HAL_OK)
4795 {
4796 /* Update ADC state machine to error */
4797 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
4798 }
4799
4800 /* Disable ADC overrun interrupt */
4801 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
4802
4803
4804
4805 /* 2. Disable the ADC peripherals: master and slave */
4806 /* Update "tmp_hal_status" only if DMA channel disabling passed, */
4807 /* to retain a potential failing status. */
4808 if (tmp_hal_status == HAL_OK)
4809 {
4810 /* Check if ADC are effectively disabled */
4811 if ((ADC_Disable(hadc) != HAL_ERROR) &&
4812 (ADC_Disable(&tmphadcSlave) != HAL_ERROR) )
4813 {
4814 tmp_hal_status = HAL_OK;
4815
4816 /* Change ADC state (ADC master) */
4817 ADC_STATE_CLR_SET(hadc->State,
4818 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
4819 HAL_ADC_STATE_READY);
4820 }
4821 }
4822 else
4823 {
4824 /* In case of error, attempt to disable ADC instances anyway */
4825 ADC_Disable(hadc);
4826 ADC_Disable(&tmphadcSlave);
4827
4828 /* Update ADC state machine (ADC master) to error */
4829 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
4830 }
4831
4832 }
4833
4834 /* Process unlocked */
4835 __HAL_UNLOCK(hadc);
4836
4837 /* Return function status */
4838 return tmp_hal_status;
4839 }
4840
4841 /**
4842 * @brief Returns the last ADC Master&Slave regular conversions results data
4843 * in the selected multi mode.
4844 * @note Reading register CDR does not clear flag ADC flag EOC
4845 * (ADC group regular end of unitary conversion),
4846 * as it is the case for independent mode data register.
4847 * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
4848 * @retval The converted data value.
4849 */
HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef * hadc)4850 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
4851 {
4852 ADC_Common_TypeDef *tmpADC_Common;
4853
4854 /* Check the parameters */
4855 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
4856
4857 /* Prevent unused argument(s) compilation warning */
4858 UNUSED(hadc);
4859
4860 /* Pointer to the common control register to which is belonging hadc */
4861 /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
4862 /* control registers) */
4863 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
4864
4865 /* Return the multi mode conversion value */
4866 return tmpADC_Common->CDR;
4867 }
4868 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
4869 /* STM32F302xC || STM32F303xC || STM32F358xx || */
4870 /* STM32F303x8 || STM32F334x8 || STM32F328xx */
4871
4872 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
4873 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
4874 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
4875 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
4876 /**
4877 * @brief Get ADC injected group conversion result.
4878 * @note Reading register JDRx automatically clears ADC flag JEOC
4879 * (ADC group injected end of unitary conversion).
4880 * @note This function does not clear ADC flag JEOS
4881 * (ADC group injected end of sequence conversion)
4882 * Occurrence of flag JEOS rising:
4883 * - If sequencer is composed of 1 rank, flag JEOS is equivalent
4884 * to flag JEOC.
4885 * - If sequencer is composed of several ranks, during the scan
4886 * sequence flag JEOC only is raised, at the end of the scan sequence
4887 * both flags JEOC and EOS are raised.
4888 * Flag JEOS must not be cleared by this function because
4889 * it would not be compliant with low power features
4890 * (feature low power auto-wait, not available on all STM32 families).
4891 * To clear this flag, either use function:
4892 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
4893 * model polling: @ref HAL_ADCEx_InjectedPollForConversion()
4894 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
4895 * @param hadc ADC handle
4896 * @param InjectedRank the converted ADC injected rank.
4897 * This parameter can be one of the following values:
4898 * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
4899 * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
4900 * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
4901 * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
4902 * @retval ADC group injected conversion data
4903 */
HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef * hadc,uint32_t InjectedRank)4904 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
4905 {
4906 uint32_t tmp_jdr = 0U;
4907
4908 /* Check the parameters */
4909 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
4910 assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
4911
4912 /* Note: ADC flag JEOC is not cleared here by software because */
4913 /* automatically cleared by hardware when reading register JDRx. */
4914
4915 /* Get ADC converted value */
4916 switch(InjectedRank)
4917 {
4918 case ADC_INJECTED_RANK_4:
4919 tmp_jdr = hadc->Instance->JDR4;
4920 break;
4921 case ADC_INJECTED_RANK_3:
4922 tmp_jdr = hadc->Instance->JDR3;
4923 break;
4924 case ADC_INJECTED_RANK_2:
4925 tmp_jdr = hadc->Instance->JDR2;
4926 break;
4927 case ADC_INJECTED_RANK_1:
4928 default:
4929 tmp_jdr = hadc->Instance->JDR1;
4930 break;
4931 }
4932
4933 /* Return ADC converted value */
4934 return tmp_jdr;
4935 }
4936 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
4937 /* STM32F302xC || STM32F303xC || STM32F358xx || */
4938 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
4939 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
4940
4941 #if defined(STM32F373xC) || defined(STM32F378xx)
4942 /**
4943 * @brief Get ADC injected group conversion result.
4944 * @note Reading register JDRx automatically clears ADC flag JEOC
4945 * (ADC group injected end of unitary conversion).
4946 * @note This function does not clear ADC flag JEOS
4947 * (ADC group injected end of sequence conversion)
4948 * Occurrence of flag JEOS rising:
4949 * - If sequencer is composed of 1 rank, flag JEOS is equivalent
4950 * to flag JEOC.
4951 * - If sequencer is composed of several ranks, during the scan
4952 * sequence flag JEOC only is raised, at the end of the scan sequence
4953 * both flags JEOC and EOS are raised.
4954 * Flag JEOS must not be cleared by this function because
4955 * it would not be compliant with low power features
4956 * (feature low power auto-wait, not available on all STM32 families).
4957 * To clear this flag, either use function:
4958 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
4959 * model polling: @ref HAL_ADCEx_InjectedPollForConversion()
4960 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
4961 * @param hadc ADC handle
4962 * @param InjectedRank the converted ADC injected rank.
4963 * This parameter can be one of the following values:
4964 * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
4965 * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
4966 * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
4967 * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
4968 * @retval ADC group injected conversion data
4969 */
HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef * hadc,uint32_t InjectedRank)4970 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
4971 {
4972 uint32_t tmp_jdr = 0U;
4973
4974 /* Check the parameters */
4975 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
4976 assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
4977
4978 /* Get ADC converted value */
4979 switch(InjectedRank)
4980 {
4981 case ADC_INJECTED_RANK_4:
4982 tmp_jdr = hadc->Instance->JDR4;
4983 break;
4984 case ADC_INJECTED_RANK_3:
4985 tmp_jdr = hadc->Instance->JDR3;
4986 break;
4987 case ADC_INJECTED_RANK_2:
4988 tmp_jdr = hadc->Instance->JDR2;
4989 break;
4990 case ADC_INJECTED_RANK_1:
4991 default:
4992 tmp_jdr = hadc->Instance->JDR1;
4993 break;
4994 }
4995
4996 /* Return ADC converted value */
4997 return tmp_jdr;
4998 }
4999 #endif /* STM32F373xC || STM32F378xx */
5000
5001 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
5002 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
5003 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
5004 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
5005 /**
5006 * @brief Stop ADC group regular conversion (potential conversion on going
5007 * on ADC group injected is not impacted), disable ADC peripheral
5008 * if no conversion is on going on group injected.
5009 * @note To stop ADC conversion of both groups regular and injected and to
5010 * to disable ADC peripheral, instead of using 2 functions
5011 * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
5012 * use function @ref HAL_ADC_Stop().
5013 * @note In case of auto-injection mode, this function also stop conversion
5014 * on ADC group injected.
5015 * @param hadc ADC handle
5016 * @retval HAL status.
5017 */
HAL_ADCEx_RegularStop(ADC_HandleTypeDef * hadc)5018 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc)
5019 {
5020 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
5021
5022 /* Check the parameters */
5023 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
5024
5025 /* Process locked */
5026 __HAL_LOCK(hadc);
5027
5028 /* Stop potential ADC conversion on going and disable ADC peripheral */
5029 /* conditioned to: */
5030 /* - For ADC regular group conversion stop: */
5031 /* On this STM32 family, conversion on the other group */
5032 /* (group injected) can continue (groups regular and injected */
5033 /* conversion stop commands are independent) */
5034 /* - For ADC disable: */
5035 /* No conversion on the other group (group injected) must be intended to */
5036 /* continue (groups regular and injected are both impacted by */
5037 /* ADC disable) */
5038
5039 /* 1. Stop potential conversion on going, on regular group only */
5040 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
5041
5042 /* Disable ADC peripheral if conversion on ADC group regular is */
5043 /* effectively stopped and if no conversion on the other group */
5044 /* (ADC group injected) is intended to continue. */
5045 if((ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) &&
5046 ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == RESET) )
5047 {
5048 /* 2. Disable the ADC peripheral */
5049 tmp_hal_status = ADC_Disable(hadc);
5050
5051 /* Check if ADC is effectively disabled */
5052 if (tmp_hal_status == HAL_OK)
5053 {
5054 /* Set ADC state */
5055 ADC_STATE_CLR_SET(hadc->State,
5056 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
5057 HAL_ADC_STATE_READY);
5058 }
5059 }
5060 /* Conversion on ADC group regular group is stopped, but ADC is not */
5061 /* disabled since conversion on ADC group injected is still on going. */
5062 else
5063 {
5064 /* Set ADC state */
5065 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
5066 }
5067
5068 /* Process unlocked */
5069 __HAL_UNLOCK(hadc);
5070
5071 /* Return function status */
5072 return tmp_hal_status;
5073 }
5074
5075 /**
5076 * @brief Stop ADC group regular conversion (potential conversion on going
5077 * on ADC group injected is not impacted), disable ADC peripheral
5078 * if no conversion is on going on group injected.
5079 * Interruptions disabled in this function:
5080 * - EOC (end of conversion of regular group) and EOS (end of
5081 * sequence of regular group)
5082 * - overrun
5083 * @note To stop ADC conversion of both groups regular and injected and to
5084 * to disable ADC peripheral, instead of using 2 functions
5085 * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
5086 * use function @ref HAL_ADC_Stop().
5087 * @note In case of auto-injection mode, this function also stop conversion
5088 * on ADC group injected.
5089 * @param hadc ADC handle
5090 * @retval HAL status.
5091 */
HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef * hadc)5092 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc)
5093 {
5094 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
5095
5096 /* Check the parameters */
5097 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
5098
5099 /* Process locked */
5100 __HAL_LOCK(hadc);
5101
5102 /* Stop potential ADC conversion on going and disable ADC peripheral */
5103 /* conditioned to: */
5104 /* - For ADC regular group conversion stop: */
5105 /* On this STM32 family, conversion on the other group */
5106 /* (group injected) can continue (groups regular and injected */
5107 /* conversion stop commands are independent) */
5108 /* - For ADC disable: */
5109 /* No conversion on the other group (group injected) must be intended to */
5110 /* continue (groups regular and injected are both impacted by */
5111 /* ADC disable) */
5112
5113 /* 1. Stop potential conversion on going, on regular group only */
5114 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
5115
5116 /* Disable ADC peripheral if conversion on ADC group regular is */
5117 /* effectively stopped and if no conversion on the other group */
5118 /* (ADC group injected) is intended to continue. */
5119 if((ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) &&
5120 ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == RESET) )
5121 {
5122 /* Disable ADC end of conversion interrupt for regular group */
5123 /* Disable ADC overrun interrupt */
5124 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
5125
5126 /* 2. Disable the ADC peripheral */
5127 tmp_hal_status = ADC_Disable(hadc);
5128
5129 /* Check if ADC is effectively disabled */
5130 if (tmp_hal_status == HAL_OK)
5131 {
5132 /* Set ADC state */
5133 ADC_STATE_CLR_SET(hadc->State,
5134 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
5135 HAL_ADC_STATE_READY);
5136 }
5137 }
5138 /* Conversion on ADC group regular group is stopped, but ADC is not */
5139 /* disabled since conversion on ADC group injected is still on going. */
5140 else
5141 {
5142 /* Set ADC state */
5143 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
5144 }
5145
5146 /* Process unlocked */
5147 __HAL_UNLOCK(hadc);
5148
5149 /* Return function status */
5150 return tmp_hal_status;
5151 }
5152
5153 /**
5154 * @brief Stop ADC group regular conversion (potential conversion on going
5155 * on ADC group injected is not impacted),
5156 * disable ADC DMA transfer, disable ADC peripheral
5157 * if no conversion is on going on group injected.
5158 * Interruptions disabled in this function:
5159 * - DMA transfer complete
5160 * - DMA half transfer
5161 * - overrun
5162 * @note To stop ADC conversion of both groups regular and injected and to
5163 * to disable ADC peripheral, instead of using 2 functions
5164 * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
5165 * use function @ref HAL_ADC_Stop().
5166 * @note Case of multimode enabled (for devices with several ADCs): This
5167 * function is for single-ADC mode only. For multimode, use the
5168 * dedicated MultimodeStop function.
5169 * @param hadc ADC handle
5170 * @retval HAL status.
5171 */
HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef * hadc)5172 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc)
5173 {
5174 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
5175
5176 /* Check the parameters */
5177 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
5178
5179 /* Process locked */
5180 __HAL_LOCK(hadc);
5181
5182 /* Stop potential ADC conversion on going and disable ADC peripheral */
5183 /* conditioned to: */
5184 /* - For ADC regular group conversion stop: */
5185 /* On this STM32 family, conversion on the other group */
5186 /* (group injected) can continue (groups regular and injected */
5187 /* conversion stop commands are independent) */
5188 /* - For ADC disable: */
5189 /* No conversion on the other group (group injected) must be intended to */
5190 /* continue (groups regular and injected are both impacted by */
5191 /* ADC disable) */
5192
5193 /* 1. Stop potential conversion on going, on regular group only */
5194 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
5195
5196 /* Disable ADC peripheral if conversion on ADC group regular is */
5197 /* effectively stopped and if no conversion on the other group */
5198 /* (ADC group injected) is intended to continue. */
5199 if((ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) &&
5200 ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == RESET) )
5201 {
5202 /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
5203 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
5204
5205 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
5206 /* while DMA transfer is on going) */
5207 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
5208
5209 /* Check if DMA channel effectively disabled */
5210 if (tmp_hal_status != HAL_OK)
5211 {
5212 /* Update ADC state machine to error */
5213 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
5214 }
5215
5216 /* Disable ADC overrun interrupt */
5217 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
5218
5219 /* 2. Disable the ADC peripheral */
5220 /* Update "tmp_hal_status" only if DMA channel disabling passed, */
5221 /* to retain a potential failing status. */
5222 if (tmp_hal_status == HAL_OK)
5223 {
5224 tmp_hal_status = ADC_Disable(hadc);
5225 }
5226 else
5227 {
5228 ADC_Disable(hadc);
5229 }
5230
5231 /* Check if ADC is effectively disabled */
5232 if (tmp_hal_status == HAL_OK)
5233 {
5234 /* Set ADC state */
5235 ADC_STATE_CLR_SET(hadc->State,
5236 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
5237 HAL_ADC_STATE_READY);
5238 }
5239 }
5240 /* Conversion on ADC group regular group is stopped, but ADC is not */
5241 /* disabled since conversion on ADC group injected is still on going. */
5242 else
5243 {
5244 /* Set ADC state */
5245 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
5246 }
5247
5248 /* Process unlocked */
5249 __HAL_UNLOCK(hadc);
5250
5251 /* Return function status */
5252 return tmp_hal_status;
5253 }
5254
5255 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
5256 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
5257 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
5258 /**
5259 * @brief With ADC configured in multimode, for ADC master:
5260 * Stop ADC group regular conversion (potential conversion on going
5261 * on ADC group injected is not impacted),
5262 * disable ADC DMA transfer, disable ADC peripheral
5263 * if no conversion is on going on group injected.
5264 * Interruptions disabled in this function:
5265 * - DMA transfer complete
5266 * - DMA half transfer
5267 * - overrun
5268 * @note To stop ADC conversion of both groups regular and injected and to
5269 * to disable ADC peripheral, instead of using 2 functions
5270 * @ref HAL_ADCEx_RegularMultiModeStop_DMA() and
5271 * @ref HAL_ADCEx_InjectedStop(), use function
5272 * @ref HAL_ADCEx_MultiModeStop_DMA.
5273 * @note In case of auto-injection mode, this function also stop conversion
5274 * on ADC group injected.
5275 * @note Multimode is kept enabled after this function. To disable multimode
5276 * (set with HAL_ADCEx_MultiModeConfigChannel() ), ADC must be
5277 * reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit().
5278 * @note In case of DMA configured in circular mode, function
5279 * HAL_ADC_Stop_DMA must be called after this function with handle of
5280 * ADC slave, to properly disable the DMA channel of ADC slave.
5281 * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
5282 * @retval None
5283 */
HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef * hadc)5284 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc)
5285 {
5286 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
5287 uint32_t tickstart;
5288 ADC_HandleTypeDef tmphadcSlave = {0};
5289
5290 /* Check the parameters */
5291 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
5292
5293 /* Process locked */
5294 __HAL_LOCK(hadc);
5295
5296 /* Stop potential ADC conversion on going and disable ADC peripheral */
5297 /* conditioned to: */
5298 /* - For ADC regular group conversion stop: */
5299 /* On this STM32 family, conversion on the other group */
5300 /* (group injected) can continue (groups regular and injected */
5301 /* conversion stop commands are independent) */
5302 /* - For ADC disable: */
5303 /* No conversion on the other group (group injected) must be intended to */
5304 /* continue (groups regular and injected are both impacted by */
5305 /* ADC disable) */
5306
5307 /* 1. Stop potential conversion on going, on regular group only */
5308 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
5309
5310 /* Disable ADC peripheral if conversion on ADC group regular is */
5311 /* effectively stopped and if no conversion on the other group */
5312 /* (ADC group injected) is intended to continue. */
5313 if((ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) &&
5314 ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == RESET) )
5315 {
5316 /* Set a temporary handle of the ADC slave associated to the ADC master */
5317 /* (Depending on STM32F3 product, there may be up to 2 ADC slaves) */
5318 ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
5319
5320 if (tmphadcSlave.Instance == NULL)
5321 {
5322 /* Update ADC state machine (ADC master) to error */
5323 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
5324
5325 /* Process unlocked */
5326 __HAL_UNLOCK(hadc);
5327
5328 return HAL_ERROR;
5329 }
5330
5331 /* Procedure to disable the ADC peripheral: wait for conversions */
5332 /* effectively stopped (ADC master and ADC slave), then disable ADC */
5333
5334 /* 1. Wait until ADSTP=0 for ADC master and ADC slave*/
5335 tickstart = HAL_GetTick();
5336
5337 while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) ||
5338 ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) )
5339 {
5340 if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
5341 {
5342 /* New check to avoid false timeout detection in case of preemption */
5343 if(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) ||
5344 ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) )
5345 {
5346 /* Update ADC state machine (ADC master) to error */
5347 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
5348
5349 /* Process unlocked */
5350 __HAL_UNLOCK(hadc);
5351
5352 return HAL_ERROR;
5353 }
5354 }
5355 }
5356
5357 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
5358 /* while DMA transfer is on going) */
5359 /* Note: In case of ADC slave using its own DMA channel (multimode */
5360 /* parameter "DMAAccessMode" set to disabled): */
5361 /* DMA channel of ADC slave should stopped after this function with */
5362 /* function HAL_ADC_Stop_DMA. */
5363 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
5364
5365 /* Check if DMA channel effectively disabled */
5366 if (tmp_hal_status != HAL_OK)
5367 {
5368 /* Update ADC state machine to error */
5369 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
5370 }
5371
5372 /* Disable ADC overrun interrupt */
5373 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
5374
5375
5376
5377 /* 2. Disable the ADC peripherals: master and slave */
5378 /* Update "tmp_hal_status" only if DMA channel disabling passed, */
5379 /* to retain a potential failing status. */
5380 if (tmp_hal_status == HAL_OK)
5381 {
5382 /* Check if ADC are effectively disabled */
5383 if ((ADC_Disable(hadc) != HAL_ERROR) &&
5384 (ADC_Disable(&tmphadcSlave) != HAL_ERROR) )
5385 {
5386 tmp_hal_status = HAL_OK;
5387
5388 /* Change ADC state (ADC master) */
5389 ADC_STATE_CLR_SET(hadc->State,
5390 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
5391 HAL_ADC_STATE_READY);
5392 }
5393 }
5394 else
5395 {
5396 /* In case of error, attempt to disable ADC instances anyway */
5397 ADC_Disable(hadc);
5398 ADC_Disable(&tmphadcSlave);
5399
5400 /* Update ADC state machine (ADC master) to error */
5401 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
5402 }
5403
5404 }
5405 /* Conversion on ADC group regular group is stopped, but ADC is not */
5406 /* disabled since conversion on ADC group injected is still on going. */
5407 else
5408 {
5409 /* Set ADC state */
5410 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
5411 }
5412
5413 /* Process unlocked */
5414 __HAL_UNLOCK(hadc);
5415
5416 /* Return function status */
5417 return tmp_hal_status;
5418 }
5419 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
5420 /* STM32F302xC || STM32F303xC || STM32F358xx || */
5421 /* STM32F303x8 || STM32F334x8 || STM32F328xx */
5422
5423
5424 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
5425 /* STM32F302xC || STM32F303xC || STM32F358xx || */
5426 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
5427 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
5428
5429 /**
5430 * @brief Injected conversion complete callback in non blocking mode
5431 * @param hadc ADC handle
5432 * @retval None
5433 */
HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef * hadc)5434 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
5435 {
5436 /* Prevent unused argument(s) compilation warning */
5437 UNUSED(hadc);
5438
5439 /* NOTE : This function Should not be modified, when the callback is needed,
5440 the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file
5441 */
5442 }
5443
5444 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
5445 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
5446 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
5447 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
5448 /**
5449 * @brief Injected context queue overflow flag callback.
5450 * @note This callback is called if injected context queue is enabled
5451 (parameter "QueueInjectedContext" in injected channel configuration)
5452 and if a new injected context is set when queue is full (maximum 2
5453 contexts).
5454 * @param hadc ADC handle
5455 * @retval None
5456 */
HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef * hadc)5457 __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc)
5458 {
5459 /* Prevent unused argument(s) compilation warning */
5460 UNUSED(hadc);
5461
5462 /* NOTE : This function should not be modified. When the callback is needed,
5463 function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented
5464 in the user file.
5465 */
5466 }
5467
5468 /**
5469 * @brief Analog watchdog 2 callback in non blocking mode.
5470 * @param hadc ADC handle
5471 * @retval None
5472 */
HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef * hadc)5473 __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc)
5474 {
5475 /* Prevent unused argument(s) compilation warning */
5476 UNUSED(hadc);
5477
5478 /* NOTE : This function should not be modified. When the callback is needed,
5479 function HAL_ADC_LevelOoutOfWindow2Callback must be implemented in the user file.
5480 */
5481 }
5482
5483 /**
5484 * @brief Analog watchdog 3 callback in non blocking mode.
5485 * @param hadc ADC handle
5486 * @retval None
5487 */
HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef * hadc)5488 __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc)
5489 {
5490 /* Prevent unused argument(s) compilation warning */
5491 UNUSED(hadc);
5492
5493 /* NOTE : This function should not be modified. When the callback is needed,
5494 function HAL_ADC_LevelOoutOfWindow3Callback must be implemented in the user file.
5495 */
5496 }
5497 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
5498 /* STM32F302xC || STM32F303xC || STM32F358xx || */
5499 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
5500 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
5501
5502 /**
5503 * @}
5504 */
5505
5506 /** @defgroup ADCEx_Exported_Functions_Group3 ADCEx Peripheral Control functions
5507 * @brief ADC Extended Peripheral Control functions
5508 *
5509 @verbatim
5510 ===============================================================================
5511 ##### Peripheral Control functions #####
5512 ===============================================================================
5513 [..] This section provides functions allowing to:
5514 (+) Configure channels on regular group
5515 (+) Configure channels on injected group
5516 (+) Configure multimode
5517 (+) Configure the analog watchdog
5518
5519 @endverbatim
5520 * @{
5521 */
5522
5523
5524 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
5525 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
5526 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
5527 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
5528 /**
5529 * @brief Configures the the selected channel to be linked to the regular
5530 * group.
5531 * @note In case of usage of internal measurement channels:
5532 * Vbat/VrefInt/TempSensor.
5533 * The recommended sampling time is at least:
5534 * - For devices STM32F37x: 17.1us for temperature sensor
5535 * - For the other STM32F3 devices: 2.2us for each of channels
5536 * Vbat/VrefInt/TempSensor.
5537 * These internal paths can be be disabled using function
5538 * HAL_ADC_DeInit().
5539 * @note Possibility to update parameters on the fly:
5540 * This function initializes channel into regular group, following
5541 * calls to this function can be used to reconfigure some parameters
5542 * of structure "ADC_ChannelConfTypeDef" on the fly, without resetting
5543 * the ADC.
5544 * The setting of these parameters is conditioned to ADC state.
5545 * For parameters constraints, see comments of structure
5546 * "ADC_ChannelConfTypeDef".
5547 * @param hadc ADC handle
5548 * @param sConfig Structure ADC channel for regular group.
5549 * @retval HAL status
5550 */
HAL_ADC_ConfigChannel(ADC_HandleTypeDef * hadc,ADC_ChannelConfTypeDef * sConfig)5551 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
5552 {
5553 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
5554 ADC_Common_TypeDef *tmpADC_Common;
5555 ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
5556 uint32_t tmpOffsetShifted;
5557 __IO uint32_t wait_loop_index = 0U;
5558
5559 /* Check the parameters */
5560 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
5561 assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
5562 assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
5563 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
5564 assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
5565 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
5566
5567
5568 /* Verification of channel number: Channels 1 to 14 are available in */
5569 /* differential mode. Channels 15U, 16U, 17U, 18 can be used only in */
5570 /* single-ended mode. */
5571 if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
5572 {
5573 assert_param(IS_ADC_CHANNEL(sConfig->Channel));
5574 }
5575 else
5576 {
5577 assert_param(IS_ADC_DIFF_CHANNEL(sConfig->Channel));
5578 }
5579
5580 /* Process locked */
5581 __HAL_LOCK(hadc);
5582
5583
5584 /* Parameters update conditioned to ADC state: */
5585 /* Parameters that can be updated when ADC is disabled or enabled without */
5586 /* conversion on going on regular group: */
5587 /* - Channel number */
5588 /* - Channel rank */
5589 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
5590 {
5591 /* Regular sequence configuration */
5592 /* For Rank 1 to 4U */
5593 if (sConfig->Rank < 5U)
5594 {
5595 MODIFY_REG(hadc->Instance->SQR1,
5596 ADC_SQR1_RK(ADC_SQR2_SQ5, sConfig->Rank) ,
5597 ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) );
5598 }
5599 /* For Rank 5 to 9U */
5600 else if (sConfig->Rank < 10U)
5601 {
5602 MODIFY_REG(hadc->Instance->SQR2,
5603 ADC_SQR2_RK(ADC_SQR2_SQ5, sConfig->Rank) ,
5604 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
5605 }
5606 /* For Rank 10 to 14U */
5607 else if (sConfig->Rank < 15U)
5608 {
5609 MODIFY_REG(hadc->Instance->SQR3 ,
5610 ADC_SQR3_RK(ADC_SQR3_SQ10, sConfig->Rank) ,
5611 ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
5612 }
5613 /* For Rank 15 to 16U */
5614 else
5615 {
5616 MODIFY_REG(hadc->Instance->SQR4 ,
5617 ADC_SQR4_RK(ADC_SQR4_SQ15, sConfig->Rank) ,
5618 ADC_SQR4_RK(sConfig->Channel, sConfig->Rank) );
5619 }
5620
5621
5622 /* Parameters update conditioned to ADC state: */
5623 /* Parameters that can be updated when ADC is disabled or enabled without */
5624 /* conversion on going on regular group: */
5625 /* - Channel sampling time */
5626 /* - Channel offset */
5627 if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
5628 {
5629 /* Channel sampling time configuration */
5630 /* For channels 10 to 18U */
5631 if (sConfig->Channel >= ADC_CHANNEL_10)
5632 {
5633 MODIFY_REG(hadc->Instance->SMPR2 ,
5634 ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel) ,
5635 ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
5636 }
5637 else /* For channels 1 to 9U */
5638 {
5639 MODIFY_REG(hadc->Instance->SMPR1 ,
5640 ADC_SMPR1(ADC_SMPR1_SMP0, sConfig->Channel) ,
5641 ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
5642 }
5643
5644
5645 /* Configure the offset: offset enable/disable, channel, offset value */
5646
5647 /* Shift the offset in function of the selected ADC resolution. */
5648 /* Offset has to be left-aligned on bit 11U, the LSB (right bits) are set */
5649 /* to 0. */
5650 tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset);
5651
5652 /* Configure the selected offset register: */
5653 /* - Enable offset */
5654 /* - Set channel number */
5655 /* - Set offset value */
5656 switch (sConfig->OffsetNumber)
5657 {
5658 case ADC_OFFSET_1:
5659 /* Configure offset register 1U */
5660 MODIFY_REG(hadc->Instance->OFR1 ,
5661 ADC_OFR1_OFFSET1_CH |
5662 ADC_OFR1_OFFSET1 ,
5663 ADC_OFR1_OFFSET1_EN |
5664 ADC_OFR_CHANNEL(sConfig->Channel) |
5665 tmpOffsetShifted );
5666 break;
5667
5668 case ADC_OFFSET_2:
5669 /* Configure offset register 2U */
5670 MODIFY_REG(hadc->Instance->OFR2 ,
5671 ADC_OFR2_OFFSET2_CH |
5672 ADC_OFR2_OFFSET2 ,
5673 ADC_OFR2_OFFSET2_EN |
5674 ADC_OFR_CHANNEL(sConfig->Channel) |
5675 tmpOffsetShifted );
5676 break;
5677
5678 case ADC_OFFSET_3:
5679 /* Configure offset register 3U */
5680 MODIFY_REG(hadc->Instance->OFR3 ,
5681 ADC_OFR3_OFFSET3_CH |
5682 ADC_OFR3_OFFSET3 ,
5683 ADC_OFR3_OFFSET3_EN |
5684 ADC_OFR_CHANNEL(sConfig->Channel) |
5685 tmpOffsetShifted );
5686 break;
5687
5688 case ADC_OFFSET_4:
5689 /* Configure offset register 4U */
5690 MODIFY_REG(hadc->Instance->OFR4 ,
5691 ADC_OFR4_OFFSET4_CH |
5692 ADC_OFR4_OFFSET4 ,
5693 ADC_OFR4_OFFSET4_EN |
5694 ADC_OFR_CHANNEL(sConfig->Channel) |
5695 tmpOffsetShifted );
5696 break;
5697
5698 /* Case ADC_OFFSET_NONE */
5699 default :
5700 /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is */
5701 /* enabled. If this is the case, offset OFRx is disabled. */
5702 if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
5703 {
5704 /* Disable offset OFR1*/
5705 CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
5706 }
5707 if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
5708 {
5709 /* Disable offset OFR2*/
5710 CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN);
5711 }
5712 if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
5713 {
5714 /* Disable offset OFR3*/
5715 CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN);
5716 }
5717 if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
5718 {
5719 /* Disable offset OFR4*/
5720 CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN);
5721 }
5722 break;
5723 }
5724
5725 }
5726
5727
5728 /* Parameters update conditioned to ADC state: */
5729 /* Parameters that can be updated only when ADC is disabled: */
5730 /* - Single or differential mode */
5731 /* - Internal measurement channels: Vbat/VrefInt/TempSensor */
5732 if (ADC_IS_ENABLE(hadc) == RESET)
5733 {
5734 /* Configuration of differential mode */
5735 if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
5736 {
5737 /* Disable differential mode (default mode: single-ended) */
5738 CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
5739 }
5740 else
5741 {
5742 /* Enable differential mode */
5743 SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
5744
5745 /* Channel sampling time configuration (channel ADC_INx +1 */
5746 /* corresponding to differential negative input). */
5747 /* For channels 10 to 18U */
5748 if (sConfig->Channel >= ADC_CHANNEL_10)
5749 {
5750 MODIFY_REG(hadc->Instance->SMPR2,
5751 ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel +1U) ,
5752 ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel +1U) );
5753 }
5754 else /* For channels 1 to 9U */
5755 {
5756 MODIFY_REG(hadc->Instance->SMPR1,
5757 ADC_SMPR1(ADC_SMPR1_SMP0, sConfig->Channel +1U) ,
5758 ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel +1U) );
5759 }
5760 }
5761
5762
5763 /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
5764 /* internal measurement paths enable: If internal channel selected, */
5765 /* enable dedicated internal buffers and path. */
5766 /* Note: these internal measurement paths can be disabled using */
5767 /* HAL_ADC_DeInit(). */
5768
5769 /* Configuration of common ADC parameters */
5770 /* Pointer to the common control register to which is belonging hadc */
5771 /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
5772 /* control registers) */
5773 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
5774
5775 /* If the requested internal measurement path has already been enabled, */
5776 /* bypass the configuration processing. */
5777 if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
5778 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) ||
5779 ( (sConfig->Channel == ADC_CHANNEL_VBAT) &&
5780 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) ||
5781 ( (sConfig->Channel == ADC_CHANNEL_VREFINT) &&
5782 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
5783 )
5784 {
5785 /* Configuration of common ADC parameters (continuation) */
5786 /* Set handle of the other ADC sharing the same common register */
5787 ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
5788
5789 /* Software is allowed to change common parameters only when all ADCs */
5790 /* of the common group are disabled. */
5791 if ((ADC_IS_ENABLE(hadc) == RESET) &&
5792 ( (tmphadcSharingSameCommonRegister.Instance == NULL) ||
5793 (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) )
5794 {
5795 /* If Channel_16 is selected, enable Temp. sensor measurement path */
5796 /* Note: Temp. sensor internal channels available on ADC1 only */
5797 if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1))
5798 {
5799 SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
5800
5801 /* Delay for temperature sensor stabilization time */
5802 /* Compute number of CPU cycles to wait for */
5803 wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
5804 while(wait_loop_index != 0U)
5805 {
5806 wait_loop_index--;
5807 }
5808 }
5809 /* If Channel_17 is selected, enable VBAT measurement path */
5810 /* Note: VBAT internal channels available on ADC1 only */
5811 else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && (hadc->Instance == ADC1))
5812 {
5813 SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
5814 }
5815 /* If Channel_18 is selected, enable VREFINT measurement path */
5816 /* Note: VrefInt internal channels available on all ADCs, but only */
5817 /* one ADC is allowed to be connected to VrefInt at the same */
5818 /* time. */
5819 else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
5820 {
5821 SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
5822 }
5823 }
5824 /* If the requested internal measurement path has already been */
5825 /* enabled and other ADC of the common group are enabled, internal */
5826 /* measurement paths cannot be enabled. */
5827 else
5828 {
5829 /* Update ADC state machine to error */
5830 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
5831
5832 tmp_hal_status = HAL_ERROR;
5833 }
5834 }
5835
5836 }
5837
5838 }
5839 /* If a conversion is on going on regular group, no update on regular */
5840 /* channel could be done on neither of the channel configuration structure */
5841 /* parameters. */
5842 else
5843 {
5844 /* Update ADC state machine to error */
5845 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
5846
5847 tmp_hal_status = HAL_ERROR;
5848 }
5849
5850 /* Process unlocked */
5851 __HAL_UNLOCK(hadc);
5852
5853 /* Return function status */
5854 return tmp_hal_status;
5855 }
5856 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
5857 /* STM32F302xC || STM32F303xC || STM32F358xx || */
5858 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
5859 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
5860
5861 #if defined(STM32F373xC) || defined(STM32F378xx)
5862 /**
5863 * @brief Configures the the selected channel to be linked to the regular
5864 * group.
5865 * @note In case of usage of internal measurement channels:
5866 * Vbat/VrefInt/TempSensor.
5867 * The recommended sampling time is at least:
5868 * - For devices STM32F37x: 17.1us for temperature sensor
5869 * - For the other STM32F3 devices: 2.2us for each of channels
5870 * Vbat/VrefInt/TempSensor.
5871 * These internal paths can be be disabled using function
5872 * HAL_ADC_DeInit().
5873 * @note Possibility to update parameters on the fly:
5874 * This function initializes channel into regular group, following
5875 * calls to this function can be used to reconfigure some parameters
5876 * of structure "ADC_ChannelConfTypeDef" on the fly, without resetting
5877 * the ADC.
5878 * The setting of these parameters is conditioned to ADC state.
5879 * For parameters constraints, see comments of structure
5880 * "ADC_ChannelConfTypeDef".
5881 * @param hadc ADC handle
5882 * @param sConfig Structure of ADC channel for regular group.
5883 * @retval HAL status
5884 */
HAL_ADC_ConfigChannel(ADC_HandleTypeDef * hadc,ADC_ChannelConfTypeDef * sConfig)5885 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
5886 {
5887 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
5888 __IO uint32_t wait_loop_index = 0U;
5889
5890 /* Check the parameters */
5891 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
5892 assert_param(IS_ADC_CHANNEL(sConfig->Channel));
5893 assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
5894 assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
5895
5896 /* Process locked */
5897 __HAL_LOCK(hadc);
5898
5899
5900 /* Regular sequence configuration */
5901 /* For Rank 1 to 6U */
5902 if (sConfig->Rank < 7U)
5903 {
5904 MODIFY_REG(hadc->Instance->SQR3 ,
5905 ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) ,
5906 ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
5907 }
5908 /* For Rank 7 to 12U */
5909 else if (sConfig->Rank < 13U)
5910 {
5911 MODIFY_REG(hadc->Instance->SQR2 ,
5912 ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank) ,
5913 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
5914 }
5915 /* For Rank 13 to 16U */
5916 else
5917 {
5918 MODIFY_REG(hadc->Instance->SQR1 ,
5919 ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank) ,
5920 ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) );
5921 }
5922
5923
5924 /* Channel sampling time configuration */
5925 /* For channels 10 to 18U */
5926 if (sConfig->Channel > ADC_CHANNEL_10)
5927 {
5928 MODIFY_REG(hadc->Instance->SMPR1 ,
5929 ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) ,
5930 ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
5931 }
5932 else /* For channels 0 to 9U */
5933 {
5934 MODIFY_REG(hadc->Instance->SMPR2 ,
5935 ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel) ,
5936 ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
5937 }
5938
5939 /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
5940 /* and VREFINT measurement path. */
5941 if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
5942 (sConfig->Channel == ADC_CHANNEL_VREFINT) )
5943 {
5944 SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
5945
5946 if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
5947 {
5948 /* Delay for temperature sensor stabilization time */
5949 /* Compute number of CPU cycles to wait for */
5950 wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
5951 while(wait_loop_index != 0U)
5952 {
5953 wait_loop_index--;
5954 }
5955 }
5956 }
5957 /* if ADC1 Channel_18 is selected, enable VBAT measurement path */
5958 else if (sConfig->Channel == ADC_CHANNEL_VBAT)
5959 {
5960 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
5961 }
5962
5963
5964 /* Process unlocked */
5965 __HAL_UNLOCK(hadc);
5966
5967 /* Return function status */
5968 return tmp_hal_status;
5969 }
5970 #endif /* STM32F373xC || STM32F378xx */
5971
5972 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
5973 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
5974 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
5975 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
5976 /**
5977 * @brief Configures the ADC injected group and the selected channel to be
5978 * linked to the injected group.
5979 * @note Possibility to update parameters on the fly:
5980 * This function initializes injected group, following calls to this
5981 * function can be used to reconfigure some parameters of structure
5982 * "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
5983 * The setting of these parameters is conditioned to ADC state.
5984 * For parameters constraints, see comments of structure
5985 * "ADC_InjectionConfTypeDef".
5986 * @note In case of usage of internal measurement channels:
5987 * Vbat/VrefInt/TempSensor.
5988 * The recommended sampling time is at least:
5989 * - For devices STM32F37x: 17.1us for temperature sensor
5990 * - For the other STM32F3 devices: 2.2us for each of channels
5991 * Vbat/VrefInt/TempSensor.
5992 * These internal paths can be be disabled using function
5993 * HAL_ADC_DeInit().
5994 * @note To reset injected sequencer, function HAL_ADCEx_InjectedStop() can
5995 * be used.
5996 * @note Caution: For Injected Context Queue use: a context must be fully
5997 * defined before start of injected conversion: all channels configured
5998 * consecutively for the same ADC instance. Therefore, Number of calls of
5999 * HAL_ADCEx_InjectedConfigChannel() must correspond to value of parameter
6000 * InjectedNbrOfConversion for each context.
6001 * - Example 1: If 1 context intended to be used (or not use of this feature:
6002 * QueueInjectedContext=DISABLE) and usage of the 3 first injected ranks
6003 * (InjectedNbrOfConversion=3), HAL_ADCEx_InjectedConfigChannel() must be
6004 * called once for each channel (3 times) before launching a conversion.
6005 * This function must not be called to configure the 4th injected channel:
6006 * it would start a new context into context queue.
6007 * - Example 2: If 2 contexts intended to be used and usage of the 3 first
6008 * injected ranks (InjectedNbrOfConversion=3),
6009 * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
6010 * for each context (3 channels x 2 contexts = 6 calls). Conversion can
6011 * start once the 1st context is set. The 2nd context can be set on the fly.
6012 * @param hadc ADC handle
6013 * @param sConfigInjected Structure of ADC injected group and ADC channel for
6014 * injected group.
6015 * @retval None
6016 */
HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef * hadc,ADC_InjectionConfTypeDef * sConfigInjected)6017 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
6018 {
6019 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
6020 ADC_Common_TypeDef *tmpADC_Common;
6021 ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
6022 uint32_t tmpOffsetShifted;
6023 __IO uint32_t wait_loop_index = 0U;
6024
6025 /* Injected context queue feature: temporary JSQR variables defined in */
6026 /* static to be passed over calls of this function */
6027 uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U;
6028
6029 /* Check the parameters */
6030 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
6031 assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
6032 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff));
6033 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
6034 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext));
6035 assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
6036 assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
6037 assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber));
6038 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
6039
6040 if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
6041 {
6042 assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
6043 assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
6044 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
6045 }
6046
6047 /* Verification of channel number: Channels 1 to 14 are available in */
6048 /* differential mode. Channels 15U, 16U, 17U, 18 can be used only in */
6049 /* single-ended mode. */
6050 if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
6051 {
6052 assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
6053 }
6054 else
6055 {
6056 assert_param(IS_ADC_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
6057 }
6058
6059 /* Process locked */
6060 __HAL_LOCK(hadc);
6061
6062 /* Configuration of Injected group sequencer. */
6063 /* Hardware constraint: Must fully define injected context register JSQR */
6064 /* before make it entering into injected sequencer queue. */
6065 /* */
6066 /* - if scan mode is disabled: */
6067 /* * Injected channels sequence length is set to 0x00: 1 channel */
6068 /* converted (channel on injected rank 1U) */
6069 /* Parameter "InjectedNbrOfConversion" is discarded. */
6070 /* * Injected context register JSQR setting is simple: register is fully */
6071 /* defined on one call of this function (for injected rank 1U) and can */
6072 /* be entered into queue directly. */
6073 /* - if scan mode is enabled: */
6074 /* * Injected channels sequence length is set to parameter */
6075 /* "InjectedNbrOfConversion". */
6076 /* * Injected context register JSQR setting more complex: register is */
6077 /* fully defined over successive calls of this function, for each */
6078 /* injected channel rank. It is entered into queue only when all */
6079 /* injected ranks have been set. */
6080 /* Note: Scan mode is not present by hardware on this device, but used */
6081 /* by software for alignment over all STM32 devices. */
6082
6083 if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) ||
6084 (sConfigInjected->InjectedNbrOfConversion == 1U) )
6085 {
6086 /* Configuration of context register JSQR: */
6087 /* - number of ranks in injected group sequencer: fixed to 1st rank */
6088 /* (scan mode disabled, only rank 1 used) */
6089 /* - external trigger to start conversion */
6090 /* - external trigger polarity */
6091 /* - channel set to rank 1 (scan mode disabled, only rank 1 used) */
6092
6093 if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
6094 {
6095 /* Enable external trigger if trigger selection is different of */
6096 /* software start. */
6097 /* Note: This configuration keeps the hardware feature of parameter */
6098 /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
6099 /* software start. */
6100 if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
6101 {
6102 SET_BIT(tmp_JSQR_ContextQueueBeingBuilt, ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) |
6103 ADC_JSQR_JEXTSEL_SET(hadc, sConfigInjected->ExternalTrigInjecConv) |
6104 sConfigInjected->ExternalTrigInjecConvEdge );
6105 }
6106 else
6107 {
6108 SET_BIT(tmp_JSQR_ContextQueueBeingBuilt, ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) );
6109 }
6110
6111 /* Update ADC register JSQR */
6112 MODIFY_REG(hadc->Instance->JSQR ,
6113 ADC_JSQR_JSQ4 |
6114 ADC_JSQR_JSQ3 |
6115 ADC_JSQR_JSQ2 |
6116 ADC_JSQR_JSQ1 |
6117 ADC_JSQR_JEXTEN |
6118 ADC_JSQR_JEXTSEL |
6119 ADC_JSQR_JL ,
6120 tmp_JSQR_ContextQueueBeingBuilt );
6121
6122 /* For debug and informative reasons, hadc handle saves JSQR setting */
6123 hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt;
6124 }
6125 /* If another injected rank than rank1 was intended to be set, and could */
6126 /* not due to ScanConvMode disabled, error is reported. */
6127 else
6128 {
6129 /* Update ADC state machine to error */
6130 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
6131
6132 tmp_hal_status = HAL_ERROR;
6133 }
6134
6135 }
6136 else
6137 {
6138 /* Case of scan mode enabled, several channels to set into injected group */
6139 /* sequencer. */
6140 /* Procedure to define injected context register JSQR over successive */
6141 /* calls of this function, for each injected channel rank: */
6142
6143 /* 1. Start new context and set parameters related to all injected */
6144 /* channels: injected sequence length and trigger */
6145 if (hadc->InjectionConfig.ChannelCount == 0U)
6146 {
6147 /* Initialize number of channels that will be configured on the context */
6148 /* being built */
6149 hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion;
6150 /* Initialize value that will be set into register JSQR */
6151 hadc->InjectionConfig.ContextQueue = 0x00000000U;
6152
6153 /* Configuration of context register JSQR: */
6154 /* - number of ranks in injected group sequencer */
6155 /* - external trigger to start conversion */
6156 /* - external trigger polarity */
6157
6158 /* Enable external trigger if trigger selection is different of */
6159 /* software start. */
6160 /* Note: This configuration keeps the hardware feature of parameter */
6161 /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
6162 /* software start. */
6163 if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
6164 {
6165 SET_BIT(hadc->InjectionConfig.ContextQueue, (sConfigInjected->InjectedNbrOfConversion - 1U) |
6166 ADC_JSQR_JEXTSEL_SET(hadc, sConfigInjected->ExternalTrigInjecConv) |
6167 sConfigInjected->ExternalTrigInjecConvEdge );
6168 }
6169 else
6170 {
6171 SET_BIT(hadc->InjectionConfig.ContextQueue, (sConfigInjected->InjectedNbrOfConversion - 1U) );
6172 }
6173
6174 }
6175
6176 /* 2. Continue setting of context under definition with parameter */
6177 /* related to each channel: channel rank sequence */
6178
6179 /* Set the JSQx bits for the selected rank */
6180 MODIFY_REG(hadc->InjectionConfig.ContextQueue ,
6181 ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank) ,
6182 ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank) );
6183
6184 /* Decrease channel count after setting into temporary JSQR variable */
6185 hadc->InjectionConfig.ChannelCount --;
6186
6187 /* 3. End of context setting: If last channel set, then write context */
6188 /* into register JSQR and make it enter into queue */
6189 if (hadc->InjectionConfig.ChannelCount == 0U)
6190 {
6191 /* Update ADC register JSQR */
6192 MODIFY_REG(hadc->Instance->JSQR ,
6193 ADC_JSQR_JSQ4 |
6194 ADC_JSQR_JSQ3 |
6195 ADC_JSQR_JSQ2 |
6196 ADC_JSQR_JSQ1 |
6197 ADC_JSQR_JEXTEN |
6198 ADC_JSQR_JEXTSEL |
6199 ADC_JSQR_JL ,
6200 hadc->InjectionConfig.ContextQueue );
6201 }
6202
6203 }
6204
6205
6206 /* Parameters update conditioned to ADC state: */
6207 /* Parameters that can be updated when ADC is disabled or enabled without */
6208 /* conversion on going on injected group: */
6209 /* - Injected context queue: Queue disable (active context is kept) or */
6210 /* enable (context decremented, up to 2 contexts queued) */
6211 /* - Injected discontinuous mode: can be enabled only if auto-injected */
6212 /* mode is disabled. */
6213 if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
6214 {
6215 /* If auto-injected mode is disabled: no constraint */
6216 if (sConfigInjected->AutoInjectedConv == DISABLE)
6217 {
6218 MODIFY_REG(hadc->Instance->CFGR ,
6219 ADC_CFGR_JQM |
6220 ADC_CFGR_JDISCEN ,
6221 ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext) |
6222 ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)sConfigInjected->InjectedDiscontinuousConvMode) );
6223 }
6224 /* If auto-injected mode is enabled: Injected discontinuous setting is */
6225 /* discarded. */
6226 else
6227 {
6228 MODIFY_REG(hadc->Instance->CFGR ,
6229 ADC_CFGR_JQM |
6230 ADC_CFGR_JDISCEN ,
6231 ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext) );
6232
6233 /* If injected discontinuous mode was intended to be set and could not */
6234 /* due to auto-injected enabled, error is reported. */
6235 if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
6236 {
6237 /* Update ADC state machine to error */
6238 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
6239
6240 tmp_hal_status = HAL_ERROR;
6241 }
6242 }
6243
6244 }
6245
6246
6247 /* Parameters update conditioned to ADC state: */
6248 /* Parameters that can be updated when ADC is disabled or enabled without */
6249 /* conversion on going on regular and injected groups: */
6250 /* - Automatic injected conversion: can be enabled if injected group */
6251 /* external triggers are disabled. */
6252 /* - Channel sampling time */
6253 /* - Channel offset */
6254 if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
6255 {
6256 /* If injected group external triggers are disabled (set to injected */
6257 /* software start): no constraint */
6258 if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
6259 {
6260 MODIFY_REG(hadc->Instance->CFGR ,
6261 ADC_CFGR_JAUTO ,
6262 ADC_CFGR_INJECT_AUTO_CONVERSION((uint32_t)sConfigInjected->AutoInjectedConv) );
6263 }
6264 /* If Automatic injected conversion was intended to be set and could not */
6265 /* due to injected group external triggers enabled, error is reported. */
6266 else
6267 {
6268 /* Disable Automatic injected conversion */
6269 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
6270
6271 if (sConfigInjected->AutoInjectedConv == ENABLE)
6272 {
6273 /* Update ADC state machine to error */
6274 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
6275
6276 tmp_hal_status = HAL_ERROR;
6277 }
6278 }
6279
6280
6281 /* Channel sampling time configuration */
6282 /* For channels 10 to 18U */
6283 if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
6284 {
6285 MODIFY_REG(hadc->Instance->SMPR2 ,
6286 ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel) ,
6287 ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
6288 }
6289 else /* For channels 1 to 9U */
6290 {
6291 MODIFY_REG(hadc->Instance->SMPR1 ,
6292 ADC_SMPR1(ADC_SMPR1_SMP0, sConfigInjected->InjectedChannel) ,
6293 ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
6294 }
6295
6296 /* Configure the offset: offset enable/disable, channel, offset value */
6297
6298 /* Shift the offset in function of the selected ADC resolution. */
6299 /* Offset has to be left-aligned on bit 11U, the LSB (right bits) are set */
6300 /* to 0. */
6301 tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
6302
6303 /* Configure the selected offset register: */
6304 /* - Enable offset */
6305 /* - Set channel number */
6306 /* - Set offset value */
6307 switch (sConfigInjected->InjectedOffsetNumber)
6308 {
6309 case ADC_OFFSET_1:
6310 /* Configure offset register 1U */
6311 MODIFY_REG(hadc->Instance->OFR1 ,
6312 ADC_OFR1_OFFSET1_CH |
6313 ADC_OFR1_OFFSET1 ,
6314 ADC_OFR1_OFFSET1_EN |
6315 ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) |
6316 tmpOffsetShifted );
6317 break;
6318
6319 case ADC_OFFSET_2:
6320 /* Configure offset register 2U */
6321 MODIFY_REG(hadc->Instance->OFR2 ,
6322 ADC_OFR2_OFFSET2_CH |
6323 ADC_OFR2_OFFSET2 ,
6324 ADC_OFR2_OFFSET2_EN |
6325 ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) |
6326 tmpOffsetShifted );
6327 break;
6328
6329 case ADC_OFFSET_3:
6330 /* Configure offset register 3U */
6331 MODIFY_REG(hadc->Instance->OFR3 ,
6332 ADC_OFR3_OFFSET3_CH |
6333 ADC_OFR3_OFFSET3 ,
6334 ADC_OFR3_OFFSET3_EN |
6335 ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) |
6336 tmpOffsetShifted );
6337 break;
6338
6339 case ADC_OFFSET_4:
6340 /* Configure offset register 4U */
6341 MODIFY_REG(hadc->Instance->OFR4 ,
6342 ADC_OFR4_OFFSET4_CH |
6343 ADC_OFR4_OFFSET4 ,
6344 ADC_OFR4_OFFSET4_EN |
6345 ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) |
6346 tmpOffsetShifted );
6347 break;
6348
6349 /* Case ADC_OFFSET_NONE */
6350 default :
6351 /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is */
6352 /* enabled. If this is the case, offset OFRx is disabled. */
6353 if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
6354 {
6355 /* Disable offset OFR1*/
6356 CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
6357 }
6358 if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
6359 {
6360 /* Disable offset OFR2*/
6361 CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN);
6362 }
6363 if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
6364 {
6365 /* Disable offset OFR3*/
6366 CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN);
6367 }
6368 if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
6369 {
6370 /* Disable offset OFR4*/
6371 CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN);
6372 }
6373 break;
6374 }
6375
6376 }
6377
6378
6379 /* Parameters update conditioned to ADC state: */
6380 /* Parameters that can be updated only when ADC is disabled: */
6381 /* - Single or differential mode */
6382 /* - Internal measurement channels: Vbat/VrefInt/TempSensor */
6383 if (ADC_IS_ENABLE(hadc) == RESET)
6384 {
6385 /* Configuration of differential mode */
6386 if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
6387 {
6388 /* Disable differential mode (default mode: single-ended) */
6389 CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
6390 }
6391 else
6392 {
6393 /* Enable differential mode */
6394 SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
6395
6396 /* Channel sampling time configuration (channel ADC_INx +1 */
6397 /* corresponding to differential negative input). */
6398 /* For channels 10 to 18U */
6399 if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
6400 {
6401 MODIFY_REG(hadc->Instance->SMPR2,
6402 ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel +1U),
6403 ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel +1U) );
6404 }
6405 else /* For channels 1 to 9U */
6406 {
6407 MODIFY_REG(hadc->Instance->SMPR1,
6408 ADC_SMPR1(ADC_SMPR1_SMP0, sConfigInjected->InjectedChannel +1U),
6409 ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel +1U) );
6410 }
6411 }
6412
6413
6414 /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
6415 /* internal measurement paths enable: If internal channel selected, */
6416 /* enable dedicated internal buffers and path. */
6417 /* Note: these internal measurement paths can be disabled using */
6418 /* HAL_ADC_deInit(). */
6419
6420 /* Configuration of common ADC parameters */
6421 /* Pointer to the common control register to which is belonging hadc */
6422 /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
6423 /* control registers) */
6424 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
6425
6426 /* If the requested internal measurement path has already been enabled, */
6427 /* bypass the configuration processing. */
6428 if (( (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) &&
6429 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) ||
6430 ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) &&
6431 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) ||
6432 ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) &&
6433 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
6434 )
6435 {
6436 /* Configuration of common ADC parameters (continuation) */
6437 /* Set handle of the other ADC sharing the same common register */
6438 ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
6439
6440 /* Software is allowed to change common parameters only when all ADCs */
6441 /* of the common group are disabled. */
6442 if ((ADC_IS_ENABLE(hadc) == RESET) &&
6443 ( (tmphadcSharingSameCommonRegister.Instance == NULL) ||
6444 (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) )
6445 {
6446 /* If Channel_16 is selected, enable Temp. sensor measurement path */
6447 /* Note: Temp. sensor internal channels available on ADC1 only */
6448 if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1))
6449 {
6450 SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
6451
6452 /* Delay for temperature sensor stabilization time */
6453 /* Compute number of CPU cycles to wait for */
6454 wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
6455 while(wait_loop_index != 0U)
6456 {
6457 wait_loop_index--;
6458 }
6459 }
6460 /* If Channel_17 is selected, enable VBAT measurement path */
6461 /* Note: VBAT internal channels available on ADC1 only */
6462 else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && (hadc->Instance == ADC1))
6463 {
6464 SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
6465 }
6466 /* If Channel_18 is selected, enable VREFINT measurement path */
6467 /* Note: VrefInt internal channels available on all ADCs, but only */
6468 /* one ADC is allowed to be connected to VrefInt at the same */
6469 /* time. */
6470 else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
6471 {
6472 SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
6473 }
6474 }
6475 /* If the requested internal measurement path has already been enabled */
6476 /* and other ADC of the common group are enabled, internal */
6477 /* measurement paths cannot be enabled. */
6478 else
6479 {
6480 /* Update ADC state machine to error */
6481 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
6482
6483 tmp_hal_status = HAL_ERROR;
6484 }
6485 }
6486
6487 }
6488
6489 /* Process unlocked */
6490 __HAL_UNLOCK(hadc);
6491
6492 /* Return function status */
6493 return tmp_hal_status;
6494 }
6495 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
6496 /* STM32F302xC || STM32F303xC || STM32F358xx || */
6497 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
6498 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
6499
6500 #if defined(STM32F373xC) || defined(STM32F378xx)
6501 /**
6502 * @brief Configures the ADC injected group and the selected channel to be
6503 * linked to the injected group.
6504 * @note Possibility to update parameters on the fly:
6505 * This function initializes injected group, following calls to this
6506 * function can be used to reconfigure some parameters of structure
6507 * "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
6508 * The setting of these parameters is conditioned to ADC state:
6509 * this function must be called when ADC is not under conversion.
6510 * @note In case of usage of internal measurement channels:
6511 * Vbat/VrefInt/TempSensor.
6512 * The recommended sampling time is at least:
6513 * - For devices STM32F37x: 17.1us for temperature sensor
6514 * - For the other STM32F3 devices: 2.2us for each of channels
6515 * Vbat/VrefInt/TempSensor.
6516 * These internal paths can be be disabled using function
6517 * HAL_ADC_DeInit().
6518 * @param hadc ADC handle
6519 * @param sConfigInjected Structure of ADC injected group and ADC channel for
6520 * injected group.
6521 * @retval None
6522 */
HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef * hadc,ADC_InjectionConfTypeDef * sConfigInjected)6523 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
6524 {
6525 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
6526 __IO uint32_t wait_loop_index = 0U;
6527
6528 /* Check the parameters */
6529 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
6530 assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
6531 assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
6532 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
6533 assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
6534 assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset));
6535
6536 if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
6537 {
6538 assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
6539 assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
6540 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
6541 }
6542
6543 /* Process locked */
6544 __HAL_LOCK(hadc);
6545
6546 /* Configuration of injected group sequencer: */
6547 /* - if scan mode is disabled, injected channels sequence length is set to */
6548 /* 0x00: 1 channel converted (channel on regular rank 1U) */
6549 /* Parameter "InjectedNbrOfConversion" is discarded. */
6550 /* Note: Scan mode is present by hardware on this device and, if */
6551 /* disabled, discards automatically nb of conversions. Anyway, nb of */
6552 /* conversions is forced to 0x00 for alignment over all STM32 devices. */
6553 /* - if scan mode is enabled, injected channels sequence length is set to */
6554 /* parameter "InjectedNbrOfConversion". */
6555 if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
6556 {
6557 if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
6558 {
6559 /* Clear the old SQx bits for all injected ranks */
6560 MODIFY_REG(hadc->Instance->JSQR ,
6561 ADC_JSQR_JL |
6562 ADC_JSQR_JSQ4 |
6563 ADC_JSQR_JSQ3 |
6564 ADC_JSQR_JSQ2 |
6565 ADC_JSQR_JSQ1 ,
6566 ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
6567 ADC_INJECTED_RANK_1,
6568 0x01U) );
6569 }
6570 /* If another injected rank than rank1 was intended to be set, and could */
6571 /* not due to ScanConvMode disabled, error is reported. */
6572 else
6573 {
6574 /* Update ADC state machine to error */
6575 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
6576
6577 tmp_hal_status = HAL_ERROR;
6578 }
6579 }
6580 else
6581 {
6582 /* Since injected channels rank conv. order depends on total number of */
6583 /* injected conversions, selected rank must be below or equal to total */
6584 /* number of injected conversions to be updated. */
6585 if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion)
6586 {
6587 /* Clear the old SQx bits for the selected rank */
6588 /* Set the SQx bits for the selected rank */
6589 MODIFY_REG(hadc->Instance->JSQR ,
6590
6591 ADC_JSQR_JL |
6592 ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,
6593 sConfigInjected->InjectedRank,
6594 sConfigInjected->InjectedNbrOfConversion) ,
6595
6596 ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion) |
6597 ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
6598 sConfigInjected->InjectedRank,
6599 sConfigInjected->InjectedNbrOfConversion) );
6600 }
6601 else
6602 {
6603 /* Clear the old SQx bits for the selected rank */
6604 MODIFY_REG(hadc->Instance->JSQR ,
6605
6606 ADC_JSQR_JL |
6607 ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,
6608 sConfigInjected->InjectedRank,
6609 sConfigInjected->InjectedNbrOfConversion) ,
6610
6611 0x00000000 );
6612 }
6613 }
6614
6615 /* Configuration of injected group */
6616 /* Parameters update conditioned to ADC state: */
6617 /* Parameters that can be updated only when ADC is disabled: */
6618 /* - external trigger to start conversion */
6619 /* Parameters update not conditioned to ADC state: */
6620 /* - Automatic injected conversion */
6621 /* - Injected discontinuous mode */
6622 /* Note: In case of ADC already enabled, caution to not launch an unwanted */
6623 /* conversion while modifying register CR2 by writing 1 to bit ADON. */
6624 if (ADC_IS_ENABLE(hadc) == RESET)
6625 {
6626 MODIFY_REG(hadc->Instance->CR2 ,
6627 ADC_CR2_JEXTSEL |
6628 ADC_CR2_ADON ,
6629 sConfigInjected->ExternalTrigInjecConv );
6630 }
6631
6632 /* Configuration of injected group */
6633 /* - Automatic injected conversion */
6634 /* - Injected discontinuous mode */
6635
6636 /* Automatic injected conversion can be enabled if injected group */
6637 /* external triggers are disabled. */
6638 if (sConfigInjected->AutoInjectedConv == ENABLE)
6639 {
6640 if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
6641 {
6642 SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO);
6643 }
6644 else
6645 {
6646 /* Update ADC state machine to error */
6647 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
6648
6649 tmp_hal_status = HAL_ERROR;
6650 }
6651 }
6652
6653 /* Injected discontinuous can be enabled only if auto-injected mode is */
6654 /* disabled. */
6655 if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
6656 {
6657 if (sConfigInjected->AutoInjectedConv == DISABLE)
6658 {
6659 SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN);
6660 }
6661 else
6662 {
6663 /* Update ADC state machine to error */
6664 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
6665
6666 tmp_hal_status = HAL_ERROR;
6667 }
6668 }
6669
6670
6671 /* InjectedChannel sampling time configuration */
6672 /* For channels 10 to 18 */
6673 if (sConfigInjected->InjectedChannel > ADC_CHANNEL_10)
6674 {
6675 MODIFY_REG(hadc->Instance->SMPR1,
6676 ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel),
6677 ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
6678 }
6679 else /* For channels 1 to 9 */
6680 {
6681 MODIFY_REG(hadc->Instance->SMPR2,
6682 ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel),
6683 ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
6684 }
6685
6686
6687 /* Configure the offset: offset enable/disable, InjectedChannel, offset value */
6688 switch(sConfigInjected->InjectedRank)
6689 {
6690 case 1:
6691 /* Set injected channel 1 offset */
6692 MODIFY_REG(hadc->Instance->JOFR1,
6693 ADC_JOFR1_JOFFSET1,
6694 sConfigInjected->InjectedOffset);
6695 break;
6696 case 2:
6697 /* Set injected channel 2 offset */
6698 MODIFY_REG(hadc->Instance->JOFR2,
6699 ADC_JOFR2_JOFFSET2,
6700 sConfigInjected->InjectedOffset);
6701 break;
6702 case 3:
6703 /* Set injected channel 3 offset */
6704 MODIFY_REG(hadc->Instance->JOFR3,
6705 ADC_JOFR3_JOFFSET3,
6706 sConfigInjected->InjectedOffset);
6707 break;
6708 case 4:
6709 default:
6710 MODIFY_REG(hadc->Instance->JOFR4,
6711 ADC_JOFR4_JOFFSET4,
6712 sConfigInjected->InjectedOffset);
6713 break;
6714 }
6715
6716 /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
6717 /* and VREFINT measurement path. */
6718 if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) ||
6719 (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) )
6720 {
6721 if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
6722 {
6723 SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
6724
6725 if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR))
6726 {
6727 /* Delay for temperature sensor stabilization time */
6728 /* Compute number of CPU cycles to wait for */
6729 wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
6730 while(wait_loop_index != 0U)
6731 {
6732 wait_loop_index--;
6733 }
6734 }
6735 }
6736 }
6737 /* if ADC1 Channel_18 is selected, enable VBAT measurement path */
6738 else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
6739 {
6740 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
6741 }
6742
6743 /* Process unlocked */
6744 __HAL_UNLOCK(hadc);
6745
6746 /* Return function status */
6747 return tmp_hal_status;
6748 }
6749 #endif /* STM32F373xC || STM32F378xx */
6750
6751 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
6752 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
6753 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
6754 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
6755 /**
6756 * @brief Configures the analog watchdog.
6757 * @note Possibility to update parameters on the fly:
6758 * This function initializes the selected analog watchdog, following
6759 * calls to this function can be used to reconfigure some parameters
6760 * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
6761 * the ADC.
6762 * The setting of these parameters is conditioned to ADC state.
6763 * For parameters constraints, see comments of structure
6764 * "ADC_AnalogWDGConfTypeDef".
6765 * @param hadc ADC handle
6766 * @param AnalogWDGConfig Structure of ADC analog watchdog configuration
6767 * @retval HAL status
6768 */
HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef * hadc,ADC_AnalogWDGConfTypeDef * AnalogWDGConfig)6769 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
6770 {
6771 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
6772
6773 uint32_t tmpAWDHighThresholdShifted;
6774 uint32_t tmpAWDLowThresholdShifted;
6775
6776 uint32_t tmpADCFlagAWD2orAWD3;
6777 uint32_t tmpADCITAWD2orAWD3;
6778
6779 /* Check the parameters */
6780 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
6781 assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
6782 assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
6783 assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
6784
6785 /* Verify if threshold is within the selected ADC resolution */
6786 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
6787 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
6788
6789 if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
6790 (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
6791 (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) )
6792 {
6793 assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
6794 }
6795
6796 /* Process locked */
6797 __HAL_LOCK(hadc);
6798
6799 /* Parameters update conditioned to ADC state: */
6800 /* Parameters that can be updated when ADC is disabled or enabled without */
6801 /* conversion on going on regular and injected groups: */
6802 /* - Analog watchdog channels */
6803 /* - Analog watchdog thresholds */
6804 if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
6805 {
6806
6807 /* Analog watchdogs configuration */
6808 if(AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
6809 {
6810 /* Configuration of analog watchdog: */
6811 /* - Set the analog watchdog enable mode: regular and/or injected */
6812 /* groups, one or overall group of channels. */
6813 /* - Set the Analog watchdog channel (is not used if watchdog */
6814 /* mode "all channels": ADC_CFGR_AWD1SGL=0U). */
6815 MODIFY_REG(hadc->Instance->CFGR ,
6816 ADC_CFGR_AWD1SGL |
6817 ADC_CFGR_JAWD1EN |
6818 ADC_CFGR_AWD1EN |
6819 ADC_CFGR_AWD1CH ,
6820 AnalogWDGConfig->WatchdogMode |
6821 ADC_CFGR_AWD1CH_SHIFT(AnalogWDGConfig->Channel) );
6822
6823 /* Shift the offset in function of the selected ADC resolution: */
6824 /* Thresholds have to be left-aligned on bit 11U, the LSB (right bits) */
6825 /* are set to 0 */
6826 tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
6827 tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
6828
6829 /* Set the high and low thresholds */
6830 MODIFY_REG(hadc->Instance->TR1 ,
6831 ADC_TR1_HT1 |
6832 ADC_TR1_LT1 ,
6833 ADC_TRX_HIGHTHRESHOLD(tmpAWDHighThresholdShifted) |
6834 tmpAWDLowThresholdShifted );
6835
6836 /* Clear the ADC Analog watchdog flag (in case of left enabled by */
6837 /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
6838 /* or HAL_ADC_PollForEvent(). */
6839 __HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD1);
6840
6841 /* Configure ADC Analog watchdog interrupt */
6842 if(AnalogWDGConfig->ITMode == ENABLE)
6843 {
6844 /* Enable the ADC Analog watchdog interrupt */
6845 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD1);
6846 }
6847 else
6848 {
6849 /* Disable the ADC Analog watchdog interrupt */
6850 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD1);
6851 }
6852
6853 }
6854 /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
6855 else
6856 {
6857 /* Shift the threshold in function of the selected ADC resolution */
6858 /* have to be left-aligned on bit 7U, the LSB (right bits) are set to 0 */
6859 tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
6860 tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
6861
6862 if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
6863 {
6864 /* Set the Analog watchdog channel or group of channels. This also */
6865 /* enables the watchdog. */
6866 /* Note: Conditional register reset, because several channels can be */
6867 /* set by successive calls of this function. */
6868 if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
6869 {
6870 /* Set the high and low thresholds */
6871 MODIFY_REG(hadc->Instance->TR2 ,
6872 ADC_TR2_HT2 |
6873 ADC_TR2_LT2 ,
6874 ADC_TRX_HIGHTHRESHOLD(tmpAWDHighThresholdShifted) |
6875 tmpAWDLowThresholdShifted );
6876
6877 SET_BIT(hadc->Instance->AWD2CR, ADC_CFGR_AWD23CR(AnalogWDGConfig->Channel));
6878 }
6879 else
6880 {
6881 CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2);
6882 CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
6883 }
6884
6885 /* Set temporary variable to flag and IT of AWD2 or AWD3 for further */
6886 /* settings. */
6887 tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD2;
6888 tmpADCITAWD2orAWD3 = ADC_IT_AWD2;
6889 }
6890 /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
6891 else
6892 {
6893 /* Set the Analog watchdog channel or group of channels. This also */
6894 /* enables the watchdog. */
6895 /* Note: Conditional register reset, because several channels can be */
6896 /* set by successive calls of this function. */
6897 if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
6898 {
6899 /* Set the high and low thresholds */
6900 MODIFY_REG(hadc->Instance->TR3 ,
6901 ADC_TR3_HT3 |
6902 ADC_TR3_LT3 ,
6903 ADC_TRX_HIGHTHRESHOLD(tmpAWDHighThresholdShifted) |
6904 tmpAWDLowThresholdShifted );
6905
6906 SET_BIT(hadc->Instance->AWD3CR, ADC_CFGR_AWD23CR(AnalogWDGConfig->Channel));
6907 }
6908 else
6909 {
6910 CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3);
6911 CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
6912 }
6913
6914 /* Set temporary variable to flag and IT of AWD2 or AWD3 for further */
6915 /* settings. */
6916 tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD3;
6917 tmpADCITAWD2orAWD3 = ADC_IT_AWD3;
6918 }
6919
6920 /* Clear the ADC Analog watchdog flag (in case of left enabled by */
6921 /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
6922 /* or HAL_ADC_PollForEvent(). */
6923 __HAL_ADC_CLEAR_FLAG(hadc, tmpADCFlagAWD2orAWD3);
6924
6925 /* Configure ADC Analog watchdog interrupt */
6926 if(AnalogWDGConfig->ITMode == ENABLE)
6927 {
6928 __HAL_ADC_ENABLE_IT(hadc, tmpADCITAWD2orAWD3);
6929 }
6930 else
6931 {
6932 __HAL_ADC_DISABLE_IT(hadc, tmpADCITAWD2orAWD3);
6933 }
6934 }
6935
6936 }
6937 /* If a conversion is on going on regular or injected groups, no update */
6938 /* could be done on neither of the AWD configuration structure parameters. */
6939 else
6940 {
6941 /* Update ADC state machine to error */
6942 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
6943
6944 tmp_hal_status = HAL_ERROR;
6945 }
6946
6947
6948 /* Process unlocked */
6949 __HAL_UNLOCK(hadc);
6950
6951 /* Return function status */
6952 return tmp_hal_status;
6953 }
6954 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
6955 /* STM32F302xC || STM32F303xC || STM32F358xx || */
6956 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
6957 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
6958
6959 #if defined(STM32F373xC) || defined(STM32F378xx)
6960 /**
6961 * @brief Configures the analog watchdog.
6962 * @note Analog watchdog thresholds can be modified while ADC conversion
6963 * is on going.
6964 * In this case, some constraints must be taken into account:
6965 * the programmed threshold values are effective from the next
6966 * ADC EOC (end of unitary conversion).
6967 * Considering that registers write delay may happen due to
6968 * bus activity, this might cause an uncertainty on the
6969 * effective timing of the new programmed threshold values.
6970 * @param hadc ADC handle
6971 * @param AnalogWDGConfig Structure of ADC analog watchdog configuration
6972 * @retval HAL status
6973 */
HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef * hadc,ADC_AnalogWDGConfTypeDef * AnalogWDGConfig)6974 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
6975 {
6976 /* Check the parameters */
6977 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
6978 assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
6979 assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
6980 assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold));
6981 assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold));
6982
6983 if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
6984 (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
6985 (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) )
6986 {
6987 assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
6988 }
6989
6990 /* Process locked */
6991 __HAL_LOCK(hadc);
6992
6993 /* Analog watchdog configuration */
6994
6995 /* Configure ADC Analog watchdog interrupt */
6996 if(AnalogWDGConfig->ITMode == ENABLE)
6997 {
6998 /* Enable the ADC Analog watchdog interrupt */
6999 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
7000 }
7001 else
7002 {
7003 /* Disable the ADC Analog watchdog interrupt */
7004 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
7005 }
7006
7007 /* Configuration of analog watchdog: */
7008 /* - Set the analog watchdog enable mode: regular and/or injected groups, */
7009 /* one or all channels. */
7010 /* - Set the Analog watchdog channel (is not used if watchdog */
7011 /* mode "all channels": ADC_CFGR_AWD1SGL=0U). */
7012 MODIFY_REG(hadc->Instance->CR1 ,
7013 ADC_CR1_AWDSGL |
7014 ADC_CR1_JAWDEN |
7015 ADC_CR1_AWDEN |
7016 ADC_CR1_AWDCH ,
7017 AnalogWDGConfig->WatchdogMode |
7018 AnalogWDGConfig->Channel );
7019
7020 /* Set the high threshold */
7021 WRITE_REG(hadc->Instance->HTR, AnalogWDGConfig->HighThreshold);
7022
7023 /* Set the low threshold */
7024 WRITE_REG(hadc->Instance->LTR, AnalogWDGConfig->LowThreshold);
7025
7026 /* Process unlocked */
7027 __HAL_UNLOCK(hadc);
7028
7029 /* Return function status */
7030 return HAL_OK;
7031 }
7032 #endif /* STM32F373xC || STM32F378xx */
7033
7034
7035 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
7036 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
7037 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
7038 /**
7039 * @brief Enable ADC multimode and configure multimode parameters
7040 * @note Possibility to update parameters on the fly:
7041 * This function initializes multimode parameters, following
7042 * calls to this function can be used to reconfigure some parameters
7043 * of structure "ADC_MultiModeTypeDef" on the fly, without resetting
7044 * the ADCs (both ADCs of the common group).
7045 * The setting of these parameters is conditioned to ADC state.
7046 * For parameters constraints, see comments of structure
7047 * "ADC_MultiModeTypeDef".
7048 * @note To change back configuration from multimode to single mode, ADC must
7049 * be reset (using function HAL_ADC_Init() ).
7050 * @param hadc ADC handle
7051 * @param multimode Structure of ADC multimode configuration
7052 * @retval HAL status
7053 */
HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef * hadc,ADC_MultiModeTypeDef * multimode)7054 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
7055 {
7056 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
7057 ADC_Common_TypeDef *tmpADC_Common;
7058 ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
7059
7060 /* Check the parameters */
7061 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
7062 assert_param(IS_ADC_MODE(multimode->Mode));
7063 if(multimode->Mode != ADC_MODE_INDEPENDENT)
7064 {
7065 assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));
7066 assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
7067 }
7068
7069 /* Set handle of the other ADC sharing the same common register */
7070 ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
7071 if (tmphadcSharingSameCommonRegister.Instance == NULL)
7072 {
7073 /* Return function status */
7074 return HAL_ERROR;
7075 }
7076
7077 /* Process locked */
7078 __HAL_LOCK(hadc);
7079
7080 /* Parameters update conditioned to ADC state: */
7081 /* Parameters that can be updated when ADC is disabled or enabled without */
7082 /* conversion on going on regular group: */
7083 /* - Multimode DMA configuration */
7084 /* - Multimode DMA mode */
7085 if ( (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
7086 && (ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSharingSameCommonRegister) == RESET) )
7087 {
7088 /* Pointer to the common control register to which is belonging hadc */
7089 /* (Depending on STM32F3 product, there may have up to 4 ADC and 2 common */
7090 /* control registers) */
7091 tmpADC_Common = ADC_COMMON_REGISTER(hadc);
7092
7093 /* If multimode is selected, configure all multimode parameters. */
7094 /* Otherwise, reset multimode parameters (can be used in case of */
7095 /* transition from multimode to independent mode). */
7096 if(multimode->Mode != ADC_MODE_INDEPENDENT)
7097 {
7098 /* Configuration of ADC common group ADC1&ADC2, ADC3&ADC4 if available */
7099 /* (ADC2, ADC3, ADC4 availability depends on STM32 product) */
7100 /* - DMA access mode */
7101 MODIFY_REG(tmpADC_Common->CCR ,
7102 ADC_CCR_MDMA |
7103 ADC_CCR_DMACFG ,
7104 multimode->DMAAccessMode |
7105 ADC_CCR_MULTI_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) );
7106
7107 /* Parameters that can be updated only when ADC is disabled: */
7108 /* - Multimode mode selection */
7109 /* - Set delay between two sampling phases */
7110 /* Note: Delay range depends on selected resolution: */
7111 /* from 1 to 12 clock cycles for 12 bits */
7112 /* from 1 to 10 clock cycles for 10 bits, */
7113 /* from 1 to 8 clock cycles for 8 bits */
7114 /* from 1 to 6 clock cycles for 6 bits */
7115 /* If a higher delay is selected, it will be clamped to maximum delay */
7116 /* range */
7117 /* Note: If ADC is not in the appropriate state to modify these */
7118 /* parameters, their setting is bypassed without error reporting */
7119 /* (as it can be the expected behaviour in case of intended action */
7120 /* to update parameter above (which fulfills the ADC state */
7121 /* condition: no conversion on going on group regular) */
7122 /* on the fly). */
7123 if ((ADC_IS_ENABLE(hadc) == RESET) &&
7124 (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) )
7125 {
7126 MODIFY_REG(tmpADC_Common->CCR ,
7127 ADC_CCR_MULTI |
7128 ADC_CCR_DELAY ,
7129 multimode->Mode |
7130 multimode->TwoSamplingDelay );
7131 }
7132 }
7133 else /* ADC_MODE_INDEPENDENT */
7134 {
7135 CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
7136
7137 /* Parameters that can be updated only when ADC is disabled: */
7138 /* - Multimode mode selection */
7139 /* - Multimode delay */
7140 if ((ADC_IS_ENABLE(hadc) == RESET) &&
7141 (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) )
7142 {
7143 CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI | ADC_CCR_DELAY);
7144 }
7145 }
7146 }
7147 /* If one of the ADC sharing the same common group is enabled, no update */
7148 /* could be done on neither of the multimode structure parameters. */
7149 else
7150 {
7151 /* Update ADC state machine to error */
7152 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
7153
7154 tmp_hal_status = HAL_ERROR;
7155 }
7156
7157
7158 /* Process unlocked */
7159 __HAL_UNLOCK(hadc);
7160
7161 /* Return function status */
7162 return tmp_hal_status;
7163 }
7164 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
7165 /* STM32F302xC || STM32F303xC || STM32F358xx || */
7166 /* STM32F303x8 || STM32F328xx || STM32F334x8 */
7167
7168 /**
7169 * @}
7170 */
7171
7172 /**
7173 * @}
7174 */
7175
7176 /** @defgroup ADCEx_Private_Functions ADCEx Private Functions
7177 * @{
7178 */
7179 /**
7180 * @brief DMA transfer complete callback.
7181 * @param hdma pointer to DMA handle.
7182 * @retval None
7183 */
ADC_DMAConvCplt(DMA_HandleTypeDef * hdma)7184 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
7185 {
7186 /* Retrieve ADC handle corresponding to current DMA handle */
7187 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
7188
7189 /* Update state machine on conversion status if not in error state */
7190 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
7191 {
7192 /* Update ADC state machine */
7193 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
7194
7195 /* Determine whether any further conversion upcoming on group regular */
7196 /* by external trigger, continuous mode or scan sequence on going. */
7197 /* Note: On STM32F3 devices, in case of sequencer enabled */
7198 /* (several ranks selected), end of conversion flag is raised */
7199 /* at the end of the sequence. */
7200 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
7201 (hadc->Init.ContinuousConvMode == DISABLE) )
7202 {
7203 /* Set ADC state */
7204 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
7205
7206 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
7207 {
7208 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
7209 }
7210 }
7211
7212 /* Conversion complete callback */
7213 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
7214 hadc->ConvCpltCallback(hadc);
7215 #else
7216 HAL_ADC_ConvCpltCallback(hadc);
7217 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
7218 }
7219 else
7220 {
7221 /* Call DMA error callback */
7222 hadc->DMA_Handle->XferErrorCallback(hdma);
7223 }
7224 }
7225
7226 /**
7227 * @brief DMA half transfer complete callback.
7228 * @param hdma pointer to DMA handle.
7229 * @retval None
7230 */
ADC_DMAHalfConvCplt(DMA_HandleTypeDef * hdma)7231 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
7232 {
7233 /* Retrieve ADC handle corresponding to current DMA handle */
7234 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
7235
7236 /* Half conversion callback */
7237 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
7238 hadc->ConvHalfCpltCallback(hadc);
7239 #else
7240 HAL_ADC_ConvHalfCpltCallback(hadc);
7241 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
7242 }
7243
7244 /**
7245 * @brief DMA error callback
7246 * @param hdma pointer to DMA handle.
7247 * @retval None
7248 */
ADC_DMAError(DMA_HandleTypeDef * hdma)7249 static void ADC_DMAError(DMA_HandleTypeDef *hdma)
7250 {
7251 /* Retrieve ADC handle corresponding to current DMA handle */
7252 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
7253
7254 /* Set ADC state */
7255 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
7256
7257 /* Set ADC error code to DMA error */
7258 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
7259
7260 /* Error callback */
7261 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
7262 hadc->ErrorCallback(hadc);
7263 #else
7264 HAL_ADC_ErrorCallback(hadc);
7265 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
7266 }
7267
7268 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
7269 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
7270 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
7271 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
7272 /**
7273 * @brief Enable the selected ADC.
7274 * @note Prerequisite condition to use this function: ADC must be disabled
7275 * and voltage regulator must be enabled (done into HAL_ADC_Init()).
7276 * @param hadc ADC handle
7277 * @retval HAL status.
7278 */
ADC_Enable(ADC_HandleTypeDef * hadc)7279 static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
7280 {
7281 uint32_t tickstart = 0U;
7282
7283 /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
7284 /* enabling phase not yet completed: flag ADC ready not yet set). */
7285 /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
7286 /* causes: ADC clock not running, ...). */
7287 if (ADC_IS_ENABLE(hadc) == RESET)
7288 {
7289 /* Check if conditions to enable the ADC are fulfilled */
7290 if (ADC_ENABLING_CONDITIONS(hadc) == RESET)
7291 {
7292 /* Update ADC state machine to error */
7293 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
7294
7295 /* Set ADC error code to ADC IP internal error */
7296 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
7297
7298 return HAL_ERROR;
7299 }
7300
7301 /* Enable the ADC peripheral */
7302 __HAL_ADC_ENABLE(hadc);
7303
7304 /* Wait for ADC effectively enabled */
7305 tickstart = HAL_GetTick();
7306
7307 while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
7308 {
7309 if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
7310 {
7311 /* New check to avoid false timeout detection in case of preemption */
7312 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
7313 {
7314 /* Update ADC state machine to error */
7315 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
7316
7317 /* Set ADC error code to ADC IP internal error */
7318 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
7319
7320 return HAL_ERROR;
7321 }
7322 }
7323 }
7324 }
7325
7326 /* Return HAL status */
7327 return HAL_OK;
7328 }
7329
7330 /**
7331 * @brief Disable the selected ADC.
7332 * @note Prerequisite condition to use this function: ADC conversions must be
7333 * stopped.
7334 * @param hadc ADC handle
7335 * @retval HAL status.
7336 */
ADC_Disable(ADC_HandleTypeDef * hadc)7337 static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
7338 {
7339 uint32_t tickstart = 0U;
7340
7341 /* Verification if ADC is not already disabled: */
7342 /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
7343 /* disabled. */
7344 if (ADC_IS_ENABLE(hadc) != RESET )
7345 {
7346 /* Check if conditions to disable the ADC are fulfilled */
7347 if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
7348 {
7349 /* Disable the ADC peripheral */
7350 __HAL_ADC_DISABLE(hadc);
7351 }
7352 else
7353 {
7354 /* Update ADC state machine to error */
7355 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
7356
7357 /* Set ADC error code to ADC IP internal error */
7358 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
7359
7360 return HAL_ERROR;
7361 }
7362
7363 /* Wait for ADC effectively disabled */
7364 tickstart = HAL_GetTick();
7365
7366 while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
7367 {
7368 if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
7369 {
7370 /* New check to avoid false timeout detection in case of preemption */
7371 if(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
7372 {
7373 /* Update ADC state machine to error */
7374 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
7375
7376 /* Set ADC error code to ADC IP internal error */
7377 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
7378
7379 return HAL_ERROR;
7380 }
7381 }
7382 }
7383 }
7384
7385 /* Return HAL status */
7386 return HAL_OK;
7387 }
7388
7389
7390 /**
7391 * @brief Stop ADC conversion.
7392 * @param hadc ADC handle
7393 * @param ConversionGroup ADC group regular and/or injected.
7394 * This parameter can be one of the following values:
7395 * @arg ADC_REGULAR_GROUP: ADC regular conversion type.
7396 * @arg ADC_INJECTED_GROUP: ADC injected conversion type.
7397 * @arg ADC_REGULAR_INJECTED_GROUP: ADC regular and injected conversion type.
7398 * @retval HAL status.
7399 */
ADC_ConversionStop(ADC_HandleTypeDef * hadc,uint32_t ConversionGroup)7400 static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup)
7401 {
7402 uint32_t tmp_ADC_CR_ADSTART_JADSTART = 0U;
7403 uint32_t tickstart = 0U;
7404 uint32_t Conversion_Timeout_CPU_cycles = 0U;
7405
7406 /* Check the parameters */
7407 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
7408 assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
7409
7410 /* Verification if ADC is not already stopped (on regular and injected */
7411 /* groups) to bypass this function if not needed. */
7412 if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc))
7413 {
7414 /* Particular case of continuous auto-injection mode combined with */
7415 /* auto-delay mode. */
7416 /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */
7417 /* injected group stop ADC_CR_JADSTP). */
7418 /* Procedure to be followed: Wait until JEOS=1U, clear JEOS, set ADSTP=1 */
7419 /* (see reference manual). */
7420 if ((HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_JAUTO)) &&
7421 (hadc->Init.ContinuousConvMode==ENABLE) &&
7422 (hadc->Init.LowPowerAutoWait==ENABLE) )
7423 {
7424 /* Use stop of regular group */
7425 ConversionGroup = ADC_REGULAR_GROUP;
7426
7427 /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
7428 while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == RESET)
7429 {
7430 if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES *4U))
7431 {
7432 /* Update ADC state machine to error */
7433 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
7434
7435 /* Set ADC error code to ADC IP internal error */
7436 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
7437
7438 return HAL_ERROR;
7439 }
7440 Conversion_Timeout_CPU_cycles ++;
7441 }
7442
7443 /* Clear JEOS */
7444 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
7445 }
7446
7447 /* Stop potential conversion on going on regular group */
7448 if (ConversionGroup != ADC_INJECTED_GROUP)
7449 {
7450 /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0U */
7451 if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) &&
7452 HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
7453 {
7454 /* Stop conversions on regular group */
7455 hadc->Instance->CR |= ADC_CR_ADSTP;
7456 }
7457 }
7458
7459 /* Stop potential conversion on going on injected group */
7460 if (ConversionGroup != ADC_REGULAR_GROUP)
7461 {
7462 /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0U */
7463 if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_JADSTART) &&
7464 HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
7465 {
7466 /* Stop conversions on injected group */
7467 hadc->Instance->CR |= ADC_CR_JADSTP;
7468 }
7469 }
7470
7471 /* Selection of start and stop bits in function of regular or injected group */
7472 switch(ConversionGroup)
7473 {
7474 case ADC_REGULAR_INJECTED_GROUP:
7475 tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
7476 break;
7477 case ADC_INJECTED_GROUP:
7478 tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
7479 break;
7480 /* Case ADC_REGULAR_GROUP */
7481 default:
7482 tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
7483 break;
7484 }
7485
7486 /* Wait for conversion effectively stopped */
7487 tickstart = HAL_GetTick();
7488
7489 while((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != RESET)
7490 {
7491 if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
7492 {
7493 /* New check to avoid false timeout detection in case of preemption */
7494 if((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != RESET)
7495 {
7496 /* Update ADC state machine to error */
7497 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
7498
7499 /* Set ADC error code to ADC IP internal error */
7500 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
7501
7502 return HAL_ERROR;
7503 }
7504 }
7505 }
7506 }
7507
7508 /* Return HAL status */
7509 return HAL_OK;
7510 }
7511 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
7512 /* STM32F302xC || STM32F303xC || STM32F358xx || */
7513 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
7514 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
7515
7516 #if defined(STM32F373xC) || defined(STM32F378xx)
7517 /**
7518 * @brief Enable the selected ADC.
7519 * @note Prerequisite condition to use this function: ADC must be disabled
7520 * and voltage regulator must be enabled (done into HAL_ADC_Init()).
7521 * @param hadc ADC handle
7522 * @retval HAL status.
7523 */
ADC_Enable(ADC_HandleTypeDef * hadc)7524 static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
7525 {
7526 uint32_t tickstart = 0U;
7527 __IO uint32_t wait_loop_index = 0U;
7528
7529 /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
7530 /* enabling phase not yet completed: flag ADC ready not yet set). */
7531 /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
7532 /* causes: ADC clock not running, ...). */
7533 if (ADC_IS_ENABLE(hadc) == RESET)
7534 {
7535 /* Enable the Peripheral */
7536 __HAL_ADC_ENABLE(hadc);
7537
7538 /* Delay for ADC stabilization time */
7539 /* Compute number of CPU cycles to wait for */
7540 wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
7541 while(wait_loop_index != 0U)
7542 {
7543 wait_loop_index--;
7544 }
7545
7546 /* Get tick count */
7547 tickstart = HAL_GetTick();
7548
7549 /* Wait for ADC effectively enabled */
7550 while(ADC_IS_ENABLE(hadc) == RESET)
7551 {
7552 if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
7553 {
7554 /* New check to avoid false timeout detection in case of preemption */
7555 if(ADC_IS_ENABLE(hadc) == RESET)
7556 {
7557 /* Update ADC state machine to error */
7558 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
7559
7560 /* Set ADC error code to ADC IP internal error */
7561 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
7562
7563 /* Process unlocked */
7564 __HAL_UNLOCK(hadc);
7565
7566 return HAL_ERROR;
7567 }
7568 }
7569 }
7570 }
7571
7572 /* Return HAL status */
7573 return HAL_OK;
7574 }
7575
7576 /**
7577 * @brief Stop ADC conversion and disable the selected ADC
7578 * @param hadc ADC handle
7579 * @retval HAL status.
7580 */
ADC_ConversionStop_Disable(ADC_HandleTypeDef * hadc)7581 static HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
7582 {
7583 uint32_t tickstart = 0U;
7584
7585 /* Verification if ADC is not already disabled: */
7586 if (ADC_IS_ENABLE(hadc) != RESET)
7587 {
7588 /* Disable the ADC peripheral */
7589 __HAL_ADC_DISABLE(hadc);
7590
7591 /* Get tick count */
7592 tickstart = HAL_GetTick();
7593
7594 /* Wait for ADC effectively disabled */
7595 while(ADC_IS_ENABLE(hadc) != RESET)
7596 {
7597 if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
7598 {
7599 /* New check to avoid false timeout detection in case of preemption */
7600 if(ADC_IS_ENABLE(hadc) != RESET)
7601 {
7602 /* Update ADC state machine to error */
7603 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
7604
7605 /* Set ADC error code to ADC IP internal error */
7606 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
7607
7608 return HAL_ERROR;
7609 }
7610 }
7611 }
7612 }
7613
7614 /* Return HAL status */
7615 return HAL_OK;
7616 }
7617 #endif /* STM32F373xC || STM32F378xx */
7618 /**
7619 * @}
7620 */
7621
7622 #endif /* HAL_ADC_MODULE_ENABLED */
7623 /**
7624 * @}
7625 */
7626
7627 /**
7628 * @}
7629 */
7630
7631
