1 /**
2 ******************************************************************************
3 * @file stm32f1xx_ll_rcc.c
4 * @author MCD Application Team
5 * @brief RCC LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 ******************************************************************************
16 */
17
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32f1xx_ll_rcc.h"
22 #ifdef USE_FULL_ASSERT
23 #include "stm32_assert.h"
24 #else
25 #define assert_param(expr) ((void)0U)
26 #endif /* USE_FULL_ASSERT */
27 /** @addtogroup STM32F1xx_LL_Driver
28 * @{
29 */
30
31 #if defined(RCC)
32
33 /** @defgroup RCC_LL RCC
34 * @{
35 */
36
37 /* Private types -------------------------------------------------------------*/
38 /* Private variables ---------------------------------------------------------*/
39 /* Private constants ---------------------------------------------------------*/
40 /* Private macros ------------------------------------------------------------*/
41 /** @addtogroup RCC_LL_Private_Macros
42 * @{
43 */
44 #if defined(RCC_PLLI2S_SUPPORT)
45 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S2_CLKSOURCE) \
46 || ((__VALUE__) == LL_RCC_I2S3_CLKSOURCE))
47 #endif /* RCC_PLLI2S_SUPPORT */
48
49 #if defined(USB) || defined(USB_OTG_FS)
50 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
51 #endif /* USB */
52
53 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
54 /**
55 * @}
56 */
57
58 /* Private function prototypes -----------------------------------------------*/
59 /** @defgroup RCC_LL_Private_Functions RCC Private functions
60 * @{
61 */
62 uint32_t RCC_GetSystemClockFreq(void);
63 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
64 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
65 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
66 uint32_t RCC_PLL_GetFreqDomain_SYS(void);
67 #if defined(RCC_PLLI2S_SUPPORT)
68 uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);
69 #endif /* RCC_PLLI2S_SUPPORT */
70 #if defined(RCC_PLL2_SUPPORT)
71 uint32_t RCC_PLL2_GetFreqClockFreq(void);
72 #endif /* RCC_PLL2_SUPPORT */
73 /**
74 * @}
75 */
76
77 /* Exported functions --------------------------------------------------------*/
78 /** @addtogroup RCC_LL_Exported_Functions
79 * @{
80 */
81
82 /** @addtogroup RCC_LL_EF_Init
83 * @{
84 */
85
86 /**
87 * @brief Reset the RCC clock configuration to the default reset state.
88 * @note The default reset state of the clock configuration is given below:
89 * - HSI ON and used as system clock source
90 * - HSE PLL, PLL2 & PLL3 are OFF
91 * - AHB, APB1 and APB2 prescaler set to 1.
92 * - CSS, MCO OFF
93 * - All interrupts disabled
94 * @note This function doesn't modify the configuration of the
95 * - Peripheral clocks
96 * - LSI, LSE and RTC clocks
97 * @retval An ErrorStatus enumeration value:
98 * - SUCCESS: RCC registers are de-initialized
99 * - ERROR: not applicable
100 */
LL_RCC_DeInit(void)101 ErrorStatus LL_RCC_DeInit(void)
102 {
103 /* Set HSION bit */
104 LL_RCC_HSI_Enable();
105
106 /* Wait for HSI READY bit */
107 while (LL_RCC_HSI_IsReady() != 1U)
108 {}
109
110 /* Configure HSI as system clock source */
111 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
112
113 /* Wait till clock switch is ready */
114 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
115 {}
116
117 /* Reset PLLON bit */
118 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
119
120 /* Wait for PLL READY bit to be reset */
121 while (LL_RCC_PLL_IsReady() != 0U)
122 {}
123
124 /* Reset CFGR register */
125 LL_RCC_WriteReg(CFGR, 0x00000000U);
126
127 /* Reset HSEON, HSEBYP & CSSON bits */
128 CLEAR_BIT(RCC->CR, (RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSEBYP));
129
130 #if defined(RCC_CR_PLL2ON)
131 /* Reset PLL2ON bit */
132 CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
133 #endif /* RCC_CR_PLL2ON */
134
135 #if defined(RCC_CR_PLL3ON)
136 /* Reset PLL3ON bit */
137 CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
138 #endif /* RCC_CR_PLL3ON */
139
140 /* Set HSITRIM bits to the reset value */
141 LL_RCC_HSI_SetCalibTrimming(0x10U);
142
143 #if defined(RCC_CFGR2_PREDIV1)
144 /* Reset CFGR2 register */
145 LL_RCC_WriteReg(CFGR2, 0x00000000U);
146 #endif /* RCC_CFGR2_PREDIV1 */
147
148 /* Disable all interrupts */
149 LL_RCC_WriteReg(CIR, 0x00000000U);
150
151 /* Clear reset flags */
152 LL_RCC_ClearResetFlags();
153
154 return SUCCESS;
155 }
156
157 /**
158 * @}
159 */
160
161 /** @addtogroup RCC_LL_EF_Get_Freq
162 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
163 * and different peripheral clocks available on the device.
164 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
165 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
166 * @note If SYSCLK source is PLL, function returns values based on
167 * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
168 * @note (**) HSI_VALUE is a defined constant but the real value may vary
169 * depending on the variations in voltage and temperature.
170 * @note (***) HSE_VALUE is a defined constant, user has to ensure that
171 * HSE_VALUE is same as the real frequency of the crystal used.
172 * Otherwise, this function may have wrong result.
173 * @note The result of this function could be incorrect when using fractional
174 * value for HSE crystal.
175 * @note This function can be used by the user application to compute the
176 * baud-rate for the communication peripherals or configure other parameters.
177 * @{
178 */
179
180 /**
181 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
182 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
183 * must be called to update structure fields. Otherwise, any
184 * configuration based on this function will be incorrect.
185 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
186 * @retval None
187 */
LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef * RCC_Clocks)188 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
189 {
190 /* Get SYSCLK frequency */
191 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
192
193 /* HCLK clock frequency */
194 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
195
196 /* PCLK1 clock frequency */
197 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
198
199 /* PCLK2 clock frequency */
200 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
201 }
202
203 #if defined(RCC_CFGR2_I2S2SRC)
204 /**
205 * @brief Return I2Sx clock frequency
206 * @param I2SxSource This parameter can be one of the following values:
207 * @arg @ref LL_RCC_I2S2_CLKSOURCE
208 * @arg @ref LL_RCC_I2S3_CLKSOURCE
209 * @retval I2S clock frequency (in Hz)
210 */
LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)211 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
212 {
213 uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
214
215 /* Check parameter */
216 assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
217
218 /* I2S1CLK clock frequency */
219 switch (LL_RCC_GetI2SClockSource(I2SxSource))
220 {
221 case LL_RCC_I2S2_CLKSOURCE_SYSCLK: /*!< System clock selected as I2S clock source */
222 case LL_RCC_I2S3_CLKSOURCE_SYSCLK:
223 i2s_frequency = RCC_GetSystemClockFreq();
224 break;
225
226 case LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO: /*!< PLLI2S oscillator clock selected as I2S clock source */
227 case LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO:
228 default:
229 i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S() * 2U;
230 break;
231 }
232
233 return i2s_frequency;
234 }
235 #endif /* RCC_CFGR2_I2S2SRC */
236
237 #if defined(USB) || defined(USB_OTG_FS)
238 /**
239 * @brief Return USBx clock frequency
240 * @param USBxSource This parameter can be one of the following values:
241 * @arg @ref LL_RCC_USB_CLKSOURCE
242 * @retval USB clock frequency (in Hz)
243 * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI), HSE or PLL is not ready
244 */
LL_RCC_GetUSBClockFreq(uint32_t USBxSource)245 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
246 {
247 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
248
249 /* Check parameter */
250 assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
251
252 /* USBCLK clock frequency */
253 switch (LL_RCC_GetUSBClockSource(USBxSource))
254 {
255 #if defined(RCC_CFGR_USBPRE)
256 case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
257 if (LL_RCC_PLL_IsReady())
258 {
259 usb_frequency = RCC_PLL_GetFreqDomain_SYS();
260 }
261 break;
262
263 case LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5: /* PLL clock divided by 1.5 used as USB clock source */
264 default:
265 if (LL_RCC_PLL_IsReady())
266 {
267 usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 3U) / 2U;
268 }
269 break;
270 #endif /* RCC_CFGR_USBPRE */
271 #if defined(RCC_CFGR_OTGFSPRE)
272 /* USBCLK = PLLVCO/2
273 = (2 x PLLCLK) / 2
274 = PLLCLK */
275 case LL_RCC_USB_CLKSOURCE_PLL_DIV_2: /* PLL clock used as USB clock source */
276 if (LL_RCC_PLL_IsReady())
277 {
278 usb_frequency = RCC_PLL_GetFreqDomain_SYS();
279 }
280 break;
281
282 /* USBCLK = PLLVCO/3
283 = (2 x PLLCLK) / 3 */
284 case LL_RCC_USB_CLKSOURCE_PLL_DIV_3: /* PLL clock divided by 3 used as USB clock source */
285 default:
286 if (LL_RCC_PLL_IsReady())
287 {
288 usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 2U) / 3U;
289 }
290 break;
291 #endif /* RCC_CFGR_OTGFSPRE */
292 }
293
294 return usb_frequency;
295 }
296 #endif /* USB */
297
298 /**
299 * @brief Return ADCx clock frequency
300 * @param ADCxSource This parameter can be one of the following values:
301 * @arg @ref LL_RCC_ADC_CLKSOURCE
302 * @retval ADC clock frequency (in Hz)
303 */
LL_RCC_GetADCClockFreq(uint32_t ADCxSource)304 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
305 {
306 uint32_t adc_prescaler = 0U;
307 uint32_t adc_frequency = 0U;
308
309 /* Check parameter */
310 assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
311
312 /* Get ADC prescaler */
313 adc_prescaler = LL_RCC_GetADCClockSource(ADCxSource);
314
315 /* ADC frequency = PCLK2 frequency / ADC prescaler (2, 4, 6 or 8) */
316 adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()))
317 / (((adc_prescaler >> POSITION_VAL(ADCxSource)) + 1U) * 2U);
318
319 return adc_frequency;
320 }
321
322 /**
323 * @}
324 */
325
326 /**
327 * @}
328 */
329
330 /** @addtogroup RCC_LL_Private_Functions
331 * @{
332 */
333
334 /**
335 * @brief Return SYSTEM clock frequency
336 * @retval SYSTEM clock frequency (in Hz)
337 */
RCC_GetSystemClockFreq(void)338 uint32_t RCC_GetSystemClockFreq(void)
339 {
340 uint32_t frequency = 0U;
341
342 /* Get SYSCLK source -------------------------------------------------------*/
343 switch (LL_RCC_GetSysClkSource())
344 {
345 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
346 frequency = HSI_VALUE;
347 break;
348
349 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
350 frequency = HSE_VALUE;
351 break;
352
353 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
354 frequency = RCC_PLL_GetFreqDomain_SYS();
355 break;
356
357 default:
358 frequency = HSI_VALUE;
359 break;
360 }
361
362 return frequency;
363 }
364
365 /**
366 * @brief Return HCLK clock frequency
367 * @param SYSCLK_Frequency SYSCLK clock frequency
368 * @retval HCLK clock frequency (in Hz)
369 */
RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)370 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
371 {
372 /* HCLK clock frequency */
373 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
374 }
375
376 /**
377 * @brief Return PCLK1 clock frequency
378 * @param HCLK_Frequency HCLK clock frequency
379 * @retval PCLK1 clock frequency (in Hz)
380 */
RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)381 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
382 {
383 /* PCLK1 clock frequency */
384 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
385 }
386
387 /**
388 * @brief Return PCLK2 clock frequency
389 * @param HCLK_Frequency HCLK clock frequency
390 * @retval PCLK2 clock frequency (in Hz)
391 */
RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)392 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
393 {
394 /* PCLK2 clock frequency */
395 return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
396 }
397
398 /**
399 * @brief Return PLL clock frequency used for system domain
400 * @retval PLL clock frequency (in Hz)
401 */
RCC_PLL_GetFreqDomain_SYS(void)402 uint32_t RCC_PLL_GetFreqDomain_SYS(void)
403 {
404 uint32_t pllinputfreq = 0U, pllsource = 0U;
405
406 /* PLL_VCO = (HSE_VALUE, HSI_VALUE or PLL2 / PLL Predivider) * PLL Multiplicator */
407
408 /* Get PLL source */
409 pllsource = LL_RCC_PLL_GetMainSource();
410
411 switch (pllsource)
412 {
413 case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */
414 pllinputfreq = HSI_VALUE / 2U;
415 break;
416
417 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
418 pllinputfreq = HSE_VALUE / (LL_RCC_PLL_GetPrediv() + 1U);
419 break;
420
421 #if defined(RCC_PLL2_SUPPORT)
422 case LL_RCC_PLLSOURCE_PLL2: /* PLL2 used as PLL clock source */
423 pllinputfreq = RCC_PLL2_GetFreqClockFreq() / (LL_RCC_PLL_GetPrediv() + 1U);
424 break;
425 #endif /* RCC_PLL2_SUPPORT */
426
427 default:
428 pllinputfreq = HSI_VALUE / 2U;
429 break;
430 }
431 return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator());
432 }
433
434 #if defined(RCC_PLL2_SUPPORT)
435 /**
436 * @brief Return PLL clock frequency used for system domain
437 * @retval PLL clock frequency (in Hz)
438 */
RCC_PLL2_GetFreqClockFreq(void)439 uint32_t RCC_PLL2_GetFreqClockFreq(void)
440 {
441 return __LL_RCC_CALC_PLL2CLK_FREQ(HSE_VALUE, LL_RCC_PLL2_GetMultiplicator(), LL_RCC_HSE_GetPrediv2());
442 }
443 #endif /* RCC_PLL2_SUPPORT */
444
445 #if defined(RCC_PLLI2S_SUPPORT)
446 /**
447 * @brief Return PLL clock frequency used for system domain
448 * @retval PLL clock frequency (in Hz)
449 */
RCC_PLLI2S_GetFreqDomain_I2S(void)450 uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)
451 {
452 return __LL_RCC_CALC_PLLI2SCLK_FREQ(HSE_VALUE, LL_RCC_PLLI2S_GetMultiplicator(), LL_RCC_HSE_GetPrediv2());
453 }
454 #endif /* RCC_PLLI2S_SUPPORT */
455
456 /**
457 * @}
458 */
459
460 /**
461 * @}
462 */
463
464 #endif /* defined(RCC) */
465
466 /**
467 * @}
468 */
469
470 #endif /* USE_FULL_LL_DRIVER */
471
472
