1 /**
2 ******************************************************************************
3 * @file stm32f1xx_hal_tim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer (TIM) peripheral:
8 * + TIM Time Base Initialization
9 * + TIM Time Base Start
10 * + TIM Time Base Start Interruption
11 * + TIM Time Base Start DMA
12 * + TIM Output Compare/PWM Initialization
13 * + TIM Output Compare/PWM Channel Configuration
14 * + TIM Output Compare/PWM Start
15 * + TIM Output Compare/PWM Start Interruption
16 * + TIM Output Compare/PWM Start DMA
17 * + TIM Input Capture Initialization
18 * + TIM Input Capture Channel Configuration
19 * + TIM Input Capture Start
20 * + TIM Input Capture Start Interruption
21 * + TIM Input Capture Start DMA
22 * + TIM One Pulse Initialization
23 * + TIM One Pulse Channel Configuration
24 * + TIM One Pulse Start
25 * + TIM Encoder Interface Initialization
26 * + TIM Encoder Interface Start
27 * + TIM Encoder Interface Start Interruption
28 * + TIM Encoder Interface Start DMA
29 * + Commutation Event configuration with Interruption and DMA
30 * + TIM OCRef clear configuration
31 * + TIM External Clock configuration
32 ******************************************************************************
33 * @attention
34 *
35 * Copyright (c) 2016 STMicroelectronics.
36 * All rights reserved.
37 *
38 * This software is licensed under terms that can be found in the LICENSE file
39 * in the root directory of this software component.
40 * If no LICENSE file comes with this software, it is provided AS-IS.
41 *
42 ******************************************************************************
43 @verbatim
44 ==============================================================================
45 ##### TIMER Generic features #####
46 ==============================================================================
47 [..] The Timer features include:
48 (#) 16-bit up, down, up/down auto-reload counter.
49 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
50 counter clock frequency either by any factor between 1 and 65536.
51 (#) Up to 4 independent channels for:
52 (++) Input Capture
53 (++) Output Compare
54 (++) PWM generation (Edge and Center-aligned Mode)
55 (++) One-pulse mode output
56 (#) Synchronization circuit to control the timer with external signals and to interconnect
57 several timers together.
58 (#) Supports incremental encoder for positioning purposes
59
60 ##### How to use this driver #####
61 ==============================================================================
62 [..]
63 (#) Initialize the TIM low level resources by implementing the following functions
64 depending on the selected feature:
65 (++) Time Base : HAL_TIM_Base_MspInit()
66 (++) Input Capture : HAL_TIM_IC_MspInit()
67 (++) Output Compare : HAL_TIM_OC_MspInit()
68 (++) PWM generation : HAL_TIM_PWM_MspInit()
69 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
70 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
71
72 (#) Initialize the TIM low level resources :
73 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
74 (##) TIM pins configuration
75 (+++) Enable the clock for the TIM GPIOs using the following function:
76 __HAL_RCC_GPIOx_CLK_ENABLE();
77 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
78
79 (#) The external Clock can be configured, if needed (the default clock is the
80 internal clock from the APBx), using the following function:
81 HAL_TIM_ConfigClockSource, the clock configuration should be done before
82 any start function.
83
84 (#) Configure the TIM in the desired functioning mode using one of the
85 Initialization function of this driver:
86 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
87 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
88 Output Compare signal.
89 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
90 PWM signal.
91 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
92 external signal.
93 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
94 in One Pulse Mode.
95 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
96
97 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
98 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
99 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
100 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
101 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
102 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
103 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
104
105 (#) The DMA Burst is managed with the two following functions:
106 HAL_TIM_DMABurst_WriteStart()
107 HAL_TIM_DMABurst_ReadStart()
108
109 *** Callback registration ***
110 =============================================
111
112 [..]
113 The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
114 allows the user to configure dynamically the driver callbacks.
115
116 [..]
117 Use Function HAL_TIM_RegisterCallback() to register a callback.
118 HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
119 the Callback ID and a pointer to the user callback function.
120
121 [..]
122 Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
123 weak function.
124 HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
125 and the Callback ID.
126
127 [..]
128 These functions allow to register/unregister following callbacks:
129 (+) Base_MspInitCallback : TIM Base Msp Init Callback.
130 (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
131 (+) IC_MspInitCallback : TIM IC Msp Init Callback.
132 (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
133 (+) OC_MspInitCallback : TIM OC Msp Init Callback.
134 (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
135 (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
136 (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
137 (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
138 (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
139 (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
140 (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
141 (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
142 (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
143 (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
144 (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
145 (+) TriggerCallback : TIM Trigger Callback.
146 (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
147 (+) IC_CaptureCallback : TIM Input Capture Callback.
148 (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
149 (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
150 (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
151 (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
152 (+) ErrorCallback : TIM Error Callback.
153 (+) CommutationCallback : TIM Commutation Callback.
154 (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
155 (+) BreakCallback : TIM Break Callback.
156
157 [..]
158 By default, after the Init and when the state is HAL_TIM_STATE_RESET
159 all interrupt callbacks are set to the corresponding weak functions:
160 examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
161
162 [..]
163 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
164 functionalities in the Init / DeInit only when these callbacks are null
165 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
166 keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
167
168 [..]
169 Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
170 Exception done MspInit / MspDeInit that can be registered / unregistered
171 in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
172 thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
173 In that case first register the MspInit/MspDeInit user callbacks
174 using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
175
176 [..]
177 When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
178 not defined, the callback registration feature is not available and all callbacks
179 are set to the corresponding weak functions.
180
181 @endverbatim
182 ******************************************************************************
183 */
184
185 /* Includes ------------------------------------------------------------------*/
186 #include "stm32f1xx_hal.h"
187
188 /** @addtogroup STM32F1xx_HAL_Driver
189 * @{
190 */
191
192 /** @defgroup TIM TIM
193 * @brief TIM HAL module driver
194 * @{
195 */
196
197 #ifdef HAL_TIM_MODULE_ENABLED
198
199 /* Private typedef -----------------------------------------------------------*/
200 /* Private define ------------------------------------------------------------*/
201 /* Private macros ------------------------------------------------------------*/
202 /* Private variables ---------------------------------------------------------*/
203 /* Private function prototypes -----------------------------------------------*/
204 /** @addtogroup TIM_Private_Functions
205 * @{
206 */
207 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
208 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
209 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
210 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
211 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
212 uint32_t TIM_ICFilter);
213 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
214 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
215 uint32_t TIM_ICFilter);
216 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
217 uint32_t TIM_ICFilter);
218 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
219 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
220 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
221 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
222 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
223 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
224 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
225 const TIM_SlaveConfigTypeDef *sSlaveConfig);
226 /**
227 * @}
228 */
229 /* Exported functions --------------------------------------------------------*/
230
231 /** @defgroup TIM_Exported_Functions TIM Exported Functions
232 * @{
233 */
234
235 /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
236 * @brief Time Base functions
237 *
238 @verbatim
239 ==============================================================================
240 ##### Time Base functions #####
241 ==============================================================================
242 [..]
243 This section provides functions allowing to:
244 (+) Initialize and configure the TIM base.
245 (+) De-initialize the TIM base.
246 (+) Start the Time Base.
247 (+) Stop the Time Base.
248 (+) Start the Time Base and enable interrupt.
249 (+) Stop the Time Base and disable interrupt.
250 (+) Start the Time Base and enable DMA transfer.
251 (+) Stop the Time Base and disable DMA transfer.
252
253 @endverbatim
254 * @{
255 */
256 /**
257 * @brief Initializes the TIM Time base Unit according to the specified
258 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
259 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
260 * requires a timer reset to avoid unexpected direction
261 * due to DIR bit readonly in center aligned mode.
262 * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
263 * @param htim TIM Base handle
264 * @retval HAL status
265 */
HAL_TIM_Base_Init(TIM_HandleTypeDef * htim)266 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
267 {
268 /* Check the TIM handle allocation */
269 if (htim == NULL)
270 {
271 return HAL_ERROR;
272 }
273
274 /* Check the parameters */
275 assert_param(IS_TIM_INSTANCE(htim->Instance));
276 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
277 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
278 assert_param(IS_TIM_PERIOD(htim->Init.Period));
279 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
280
281 if (htim->State == HAL_TIM_STATE_RESET)
282 {
283 /* Allocate lock resource and initialize it */
284 htim->Lock = HAL_UNLOCKED;
285
286 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
287 /* Reset interrupt callbacks to legacy weak callbacks */
288 TIM_ResetCallback(htim);
289
290 if (htim->Base_MspInitCallback == NULL)
291 {
292 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
293 }
294 /* Init the low level hardware : GPIO, CLOCK, NVIC */
295 htim->Base_MspInitCallback(htim);
296 #else
297 /* Init the low level hardware : GPIO, CLOCK, NVIC */
298 HAL_TIM_Base_MspInit(htim);
299 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
300 }
301
302 /* Set the TIM state */
303 htim->State = HAL_TIM_STATE_BUSY;
304
305 /* Set the Time Base configuration */
306 TIM_Base_SetConfig(htim->Instance, &htim->Init);
307
308 /* Initialize the DMA burst operation state */
309 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
310
311 /* Initialize the TIM channels state */
312 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
313 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
314
315 /* Initialize the TIM state*/
316 htim->State = HAL_TIM_STATE_READY;
317
318 return HAL_OK;
319 }
320
321 /**
322 * @brief DeInitializes the TIM Base peripheral
323 * @param htim TIM Base handle
324 * @retval HAL status
325 */
HAL_TIM_Base_DeInit(TIM_HandleTypeDef * htim)326 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
327 {
328 /* Check the parameters */
329 assert_param(IS_TIM_INSTANCE(htim->Instance));
330
331 htim->State = HAL_TIM_STATE_BUSY;
332
333 /* Disable the TIM Peripheral Clock */
334 __HAL_TIM_DISABLE(htim);
335
336 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
337 if (htim->Base_MspDeInitCallback == NULL)
338 {
339 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
340 }
341 /* DeInit the low level hardware */
342 htim->Base_MspDeInitCallback(htim);
343 #else
344 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
345 HAL_TIM_Base_MspDeInit(htim);
346 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
347
348 /* Change the DMA burst operation state */
349 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
350
351 /* Change the TIM channels state */
352 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
353 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
354
355 /* Change TIM state */
356 htim->State = HAL_TIM_STATE_RESET;
357
358 /* Release Lock */
359 __HAL_UNLOCK(htim);
360
361 return HAL_OK;
362 }
363
364 /**
365 * @brief Initializes the TIM Base MSP.
366 * @param htim TIM Base handle
367 * @retval None
368 */
HAL_TIM_Base_MspInit(TIM_HandleTypeDef * htim)369 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
370 {
371 /* Prevent unused argument(s) compilation warning */
372 UNUSED(htim);
373
374 /* NOTE : This function should not be modified, when the callback is needed,
375 the HAL_TIM_Base_MspInit could be implemented in the user file
376 */
377 }
378
379 /**
380 * @brief DeInitializes TIM Base MSP.
381 * @param htim TIM Base handle
382 * @retval None
383 */
HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef * htim)384 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
385 {
386 /* Prevent unused argument(s) compilation warning */
387 UNUSED(htim);
388
389 /* NOTE : This function should not be modified, when the callback is needed,
390 the HAL_TIM_Base_MspDeInit could be implemented in the user file
391 */
392 }
393
394
395 /**
396 * @brief Starts the TIM Base generation.
397 * @param htim TIM Base handle
398 * @retval HAL status
399 */
HAL_TIM_Base_Start(TIM_HandleTypeDef * htim)400 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
401 {
402 uint32_t tmpsmcr;
403
404 /* Check the parameters */
405 assert_param(IS_TIM_INSTANCE(htim->Instance));
406
407 /* Check the TIM state */
408 if (htim->State != HAL_TIM_STATE_READY)
409 {
410 return HAL_ERROR;
411 }
412
413 /* Set the TIM state */
414 htim->State = HAL_TIM_STATE_BUSY;
415
416 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
417 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
418 {
419 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
420 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
421 {
422 __HAL_TIM_ENABLE(htim);
423 }
424 }
425 else
426 {
427 __HAL_TIM_ENABLE(htim);
428 }
429
430 /* Return function status */
431 return HAL_OK;
432 }
433
434 /**
435 * @brief Stops the TIM Base generation.
436 * @param htim TIM Base handle
437 * @retval HAL status
438 */
HAL_TIM_Base_Stop(TIM_HandleTypeDef * htim)439 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
440 {
441 /* Check the parameters */
442 assert_param(IS_TIM_INSTANCE(htim->Instance));
443
444 /* Disable the Peripheral */
445 __HAL_TIM_DISABLE(htim);
446
447 /* Set the TIM state */
448 htim->State = HAL_TIM_STATE_READY;
449
450 /* Return function status */
451 return HAL_OK;
452 }
453
454 /**
455 * @brief Starts the TIM Base generation in interrupt mode.
456 * @param htim TIM Base handle
457 * @retval HAL status
458 */
HAL_TIM_Base_Start_IT(TIM_HandleTypeDef * htim)459 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
460 {
461 uint32_t tmpsmcr;
462
463 /* Check the parameters */
464 assert_param(IS_TIM_INSTANCE(htim->Instance));
465
466 /* Check the TIM state */
467 if (htim->State != HAL_TIM_STATE_READY)
468 {
469 return HAL_ERROR;
470 }
471
472 /* Set the TIM state */
473 htim->State = HAL_TIM_STATE_BUSY;
474
475 /* Enable the TIM Update interrupt */
476 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
477
478 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
479 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
480 {
481 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
482 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
483 {
484 __HAL_TIM_ENABLE(htim);
485 }
486 }
487 else
488 {
489 __HAL_TIM_ENABLE(htim);
490 }
491
492 /* Return function status */
493 return HAL_OK;
494 }
495
496 /**
497 * @brief Stops the TIM Base generation in interrupt mode.
498 * @param htim TIM Base handle
499 * @retval HAL status
500 */
HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef * htim)501 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
502 {
503 /* Check the parameters */
504 assert_param(IS_TIM_INSTANCE(htim->Instance));
505
506 /* Disable the TIM Update interrupt */
507 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
508
509 /* Disable the Peripheral */
510 __HAL_TIM_DISABLE(htim);
511
512 /* Set the TIM state */
513 htim->State = HAL_TIM_STATE_READY;
514
515 /* Return function status */
516 return HAL_OK;
517 }
518
519 /**
520 * @brief Starts the TIM Base generation in DMA mode.
521 * @param htim TIM Base handle
522 * @param pData The source Buffer address.
523 * @param Length The length of data to be transferred from memory to peripheral.
524 * @retval HAL status
525 */
HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef * htim,const uint32_t * pData,uint16_t Length)526 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
527 {
528 uint32_t tmpsmcr;
529
530 /* Check the parameters */
531 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
532
533 /* Set the TIM state */
534 if (htim->State == HAL_TIM_STATE_BUSY)
535 {
536 return HAL_BUSY;
537 }
538 else if (htim->State == HAL_TIM_STATE_READY)
539 {
540 if ((pData == NULL) || (Length == 0U))
541 {
542 return HAL_ERROR;
543 }
544 else
545 {
546 htim->State = HAL_TIM_STATE_BUSY;
547 }
548 }
549 else
550 {
551 return HAL_ERROR;
552 }
553
554 /* Set the DMA Period elapsed callbacks */
555 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
556 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
557
558 /* Set the DMA error callback */
559 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
560
561 /* Enable the DMA channel */
562 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
563 Length) != HAL_OK)
564 {
565 /* Return error status */
566 return HAL_ERROR;
567 }
568
569 /* Enable the TIM Update DMA request */
570 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
571
572 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
573 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
574 {
575 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
576 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
577 {
578 __HAL_TIM_ENABLE(htim);
579 }
580 }
581 else
582 {
583 __HAL_TIM_ENABLE(htim);
584 }
585
586 /* Return function status */
587 return HAL_OK;
588 }
589
590 /**
591 * @brief Stops the TIM Base generation in DMA mode.
592 * @param htim TIM Base handle
593 * @retval HAL status
594 */
HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef * htim)595 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
596 {
597 /* Check the parameters */
598 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
599
600 /* Disable the TIM Update DMA request */
601 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
602
603 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
604
605 /* Disable the Peripheral */
606 __HAL_TIM_DISABLE(htim);
607
608 /* Set the TIM state */
609 htim->State = HAL_TIM_STATE_READY;
610
611 /* Return function status */
612 return HAL_OK;
613 }
614
615 /**
616 * @}
617 */
618
619 /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
620 * @brief TIM Output Compare functions
621 *
622 @verbatim
623 ==============================================================================
624 ##### TIM Output Compare functions #####
625 ==============================================================================
626 [..]
627 This section provides functions allowing to:
628 (+) Initialize and configure the TIM Output Compare.
629 (+) De-initialize the TIM Output Compare.
630 (+) Start the TIM Output Compare.
631 (+) Stop the TIM Output Compare.
632 (+) Start the TIM Output Compare and enable interrupt.
633 (+) Stop the TIM Output Compare and disable interrupt.
634 (+) Start the TIM Output Compare and enable DMA transfer.
635 (+) Stop the TIM Output Compare and disable DMA transfer.
636
637 @endverbatim
638 * @{
639 */
640 /**
641 * @brief Initializes the TIM Output Compare according to the specified
642 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
643 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
644 * requires a timer reset to avoid unexpected direction
645 * due to DIR bit readonly in center aligned mode.
646 * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
647 * @param htim TIM Output Compare handle
648 * @retval HAL status
649 */
HAL_TIM_OC_Init(TIM_HandleTypeDef * htim)650 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
651 {
652 /* Check the TIM handle allocation */
653 if (htim == NULL)
654 {
655 return HAL_ERROR;
656 }
657
658 /* Check the parameters */
659 assert_param(IS_TIM_INSTANCE(htim->Instance));
660 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
661 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
662 assert_param(IS_TIM_PERIOD(htim->Init.Period));
663 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
664
665 if (htim->State == HAL_TIM_STATE_RESET)
666 {
667 /* Allocate lock resource and initialize it */
668 htim->Lock = HAL_UNLOCKED;
669
670 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
671 /* Reset interrupt callbacks to legacy weak callbacks */
672 TIM_ResetCallback(htim);
673
674 if (htim->OC_MspInitCallback == NULL)
675 {
676 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
677 }
678 /* Init the low level hardware : GPIO, CLOCK, NVIC */
679 htim->OC_MspInitCallback(htim);
680 #else
681 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
682 HAL_TIM_OC_MspInit(htim);
683 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
684 }
685
686 /* Set the TIM state */
687 htim->State = HAL_TIM_STATE_BUSY;
688
689 /* Init the base time for the Output Compare */
690 TIM_Base_SetConfig(htim->Instance, &htim->Init);
691
692 /* Initialize the DMA burst operation state */
693 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
694
695 /* Initialize the TIM channels state */
696 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
697 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
698
699 /* Initialize the TIM state*/
700 htim->State = HAL_TIM_STATE_READY;
701
702 return HAL_OK;
703 }
704
705 /**
706 * @brief DeInitializes the TIM peripheral
707 * @param htim TIM Output Compare handle
708 * @retval HAL status
709 */
HAL_TIM_OC_DeInit(TIM_HandleTypeDef * htim)710 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
711 {
712 /* Check the parameters */
713 assert_param(IS_TIM_INSTANCE(htim->Instance));
714
715 htim->State = HAL_TIM_STATE_BUSY;
716
717 /* Disable the TIM Peripheral Clock */
718 __HAL_TIM_DISABLE(htim);
719
720 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
721 if (htim->OC_MspDeInitCallback == NULL)
722 {
723 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
724 }
725 /* DeInit the low level hardware */
726 htim->OC_MspDeInitCallback(htim);
727 #else
728 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
729 HAL_TIM_OC_MspDeInit(htim);
730 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
731
732 /* Change the DMA burst operation state */
733 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
734
735 /* Change the TIM channels state */
736 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
737 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
738
739 /* Change TIM state */
740 htim->State = HAL_TIM_STATE_RESET;
741
742 /* Release Lock */
743 __HAL_UNLOCK(htim);
744
745 return HAL_OK;
746 }
747
748 /**
749 * @brief Initializes the TIM Output Compare MSP.
750 * @param htim TIM Output Compare handle
751 * @retval None
752 */
HAL_TIM_OC_MspInit(TIM_HandleTypeDef * htim)753 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
754 {
755 /* Prevent unused argument(s) compilation warning */
756 UNUSED(htim);
757
758 /* NOTE : This function should not be modified, when the callback is needed,
759 the HAL_TIM_OC_MspInit could be implemented in the user file
760 */
761 }
762
763 /**
764 * @brief DeInitializes TIM Output Compare MSP.
765 * @param htim TIM Output Compare handle
766 * @retval None
767 */
HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef * htim)768 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
769 {
770 /* Prevent unused argument(s) compilation warning */
771 UNUSED(htim);
772
773 /* NOTE : This function should not be modified, when the callback is needed,
774 the HAL_TIM_OC_MspDeInit could be implemented in the user file
775 */
776 }
777
778 /**
779 * @brief Starts the TIM Output Compare signal generation.
780 * @param htim TIM Output Compare handle
781 * @param Channel TIM Channel to be enabled
782 * This parameter can be one of the following values:
783 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
784 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
785 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
786 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
787 * @retval HAL status
788 */
HAL_TIM_OC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)789 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
790 {
791 uint32_t tmpsmcr;
792
793 /* Check the parameters */
794 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
795
796 /* Check the TIM channel state */
797 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
798 {
799 return HAL_ERROR;
800 }
801
802 /* Set the TIM channel state */
803 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
804
805 /* Enable the Output compare channel */
806 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
807
808 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
809 {
810 /* Enable the main output */
811 __HAL_TIM_MOE_ENABLE(htim);
812 }
813
814 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
815 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
816 {
817 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
818 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
819 {
820 __HAL_TIM_ENABLE(htim);
821 }
822 }
823 else
824 {
825 __HAL_TIM_ENABLE(htim);
826 }
827
828 /* Return function status */
829 return HAL_OK;
830 }
831
832 /**
833 * @brief Stops the TIM Output Compare signal generation.
834 * @param htim TIM Output Compare handle
835 * @param Channel TIM Channel to be disabled
836 * This parameter can be one of the following values:
837 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
838 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
839 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
840 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
841 * @retval HAL status
842 */
HAL_TIM_OC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)843 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
844 {
845 /* Check the parameters */
846 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
847
848 /* Disable the Output compare channel */
849 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
850
851 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
852 {
853 /* Disable the Main Output */
854 __HAL_TIM_MOE_DISABLE(htim);
855 }
856
857 /* Disable the Peripheral */
858 __HAL_TIM_DISABLE(htim);
859
860 /* Set the TIM channel state */
861 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
862
863 /* Return function status */
864 return HAL_OK;
865 }
866
867 /**
868 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
869 * @param htim TIM Output Compare handle
870 * @param Channel TIM Channel to be enabled
871 * This parameter can be one of the following values:
872 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
873 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
874 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
875 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
876 * @retval HAL status
877 */
HAL_TIM_OC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)878 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
879 {
880 HAL_StatusTypeDef status = HAL_OK;
881 uint32_t tmpsmcr;
882
883 /* Check the parameters */
884 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
885
886 /* Check the TIM channel state */
887 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
888 {
889 return HAL_ERROR;
890 }
891
892 /* Set the TIM channel state */
893 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
894
895 switch (Channel)
896 {
897 case TIM_CHANNEL_1:
898 {
899 /* Enable the TIM Capture/Compare 1 interrupt */
900 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
901 break;
902 }
903
904 case TIM_CHANNEL_2:
905 {
906 /* Enable the TIM Capture/Compare 2 interrupt */
907 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
908 break;
909 }
910
911 case TIM_CHANNEL_3:
912 {
913 /* Enable the TIM Capture/Compare 3 interrupt */
914 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
915 break;
916 }
917
918 case TIM_CHANNEL_4:
919 {
920 /* Enable the TIM Capture/Compare 4 interrupt */
921 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
922 break;
923 }
924
925 default:
926 status = HAL_ERROR;
927 break;
928 }
929
930 if (status == HAL_OK)
931 {
932 /* Enable the Output compare channel */
933 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
934
935 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
936 {
937 /* Enable the main output */
938 __HAL_TIM_MOE_ENABLE(htim);
939 }
940
941 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
942 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
943 {
944 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
945 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
946 {
947 __HAL_TIM_ENABLE(htim);
948 }
949 }
950 else
951 {
952 __HAL_TIM_ENABLE(htim);
953 }
954 }
955
956 /* Return function status */
957 return status;
958 }
959
960 /**
961 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
962 * @param htim TIM Output Compare handle
963 * @param Channel TIM Channel to be disabled
964 * This parameter can be one of the following values:
965 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
966 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
967 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
968 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
969 * @retval HAL status
970 */
HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)971 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
972 {
973 HAL_StatusTypeDef status = HAL_OK;
974
975 /* Check the parameters */
976 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
977
978 switch (Channel)
979 {
980 case TIM_CHANNEL_1:
981 {
982 /* Disable the TIM Capture/Compare 1 interrupt */
983 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
984 break;
985 }
986
987 case TIM_CHANNEL_2:
988 {
989 /* Disable the TIM Capture/Compare 2 interrupt */
990 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
991 break;
992 }
993
994 case TIM_CHANNEL_3:
995 {
996 /* Disable the TIM Capture/Compare 3 interrupt */
997 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
998 break;
999 }
1000
1001 case TIM_CHANNEL_4:
1002 {
1003 /* Disable the TIM Capture/Compare 4 interrupt */
1004 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1005 break;
1006 }
1007
1008 default:
1009 status = HAL_ERROR;
1010 break;
1011 }
1012
1013 if (status == HAL_OK)
1014 {
1015 /* Disable the Output compare channel */
1016 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1017
1018 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1019 {
1020 /* Disable the Main Output */
1021 __HAL_TIM_MOE_DISABLE(htim);
1022 }
1023
1024 /* Disable the Peripheral */
1025 __HAL_TIM_DISABLE(htim);
1026
1027 /* Set the TIM channel state */
1028 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1029 }
1030
1031 /* Return function status */
1032 return status;
1033 }
1034
1035 /**
1036 * @brief Starts the TIM Output Compare signal generation in DMA mode.
1037 * @param htim TIM Output Compare handle
1038 * @param Channel TIM Channel to be enabled
1039 * This parameter can be one of the following values:
1040 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1041 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1042 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1043 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1044 * @param pData The source Buffer address.
1045 * @param Length The length of data to be transferred from memory to TIM peripheral
1046 * @retval HAL status
1047 */
HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1048 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1049 uint16_t Length)
1050 {
1051 HAL_StatusTypeDef status = HAL_OK;
1052 uint32_t tmpsmcr;
1053
1054 /* Check the parameters */
1055 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1056
1057 /* Set the TIM channel state */
1058 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1059 {
1060 return HAL_BUSY;
1061 }
1062 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1063 {
1064 if ((pData == NULL) || (Length == 0U))
1065 {
1066 return HAL_ERROR;
1067 }
1068 else
1069 {
1070 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1071 }
1072 }
1073 else
1074 {
1075 return HAL_ERROR;
1076 }
1077
1078 switch (Channel)
1079 {
1080 case TIM_CHANNEL_1:
1081 {
1082 /* Set the DMA compare callbacks */
1083 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1084 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1085
1086 /* Set the DMA error callback */
1087 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1088
1089 /* Enable the DMA channel */
1090 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1091 Length) != HAL_OK)
1092 {
1093 /* Return error status */
1094 return HAL_ERROR;
1095 }
1096
1097 /* Enable the TIM Capture/Compare 1 DMA request */
1098 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1099 break;
1100 }
1101
1102 case TIM_CHANNEL_2:
1103 {
1104 /* Set the DMA compare callbacks */
1105 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1106 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1107
1108 /* Set the DMA error callback */
1109 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1110
1111 /* Enable the DMA channel */
1112 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1113 Length) != HAL_OK)
1114 {
1115 /* Return error status */
1116 return HAL_ERROR;
1117 }
1118
1119 /* Enable the TIM Capture/Compare 2 DMA request */
1120 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1121 break;
1122 }
1123
1124 case TIM_CHANNEL_3:
1125 {
1126 /* Set the DMA compare callbacks */
1127 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1128 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1129
1130 /* Set the DMA error callback */
1131 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1132
1133 /* Enable the DMA channel */
1134 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1135 Length) != HAL_OK)
1136 {
1137 /* Return error status */
1138 return HAL_ERROR;
1139 }
1140 /* Enable the TIM Capture/Compare 3 DMA request */
1141 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1142 break;
1143 }
1144
1145 case TIM_CHANNEL_4:
1146 {
1147 /* Set the DMA compare callbacks */
1148 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1149 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1150
1151 /* Set the DMA error callback */
1152 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1153
1154 /* Enable the DMA channel */
1155 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1156 Length) != HAL_OK)
1157 {
1158 /* Return error status */
1159 return HAL_ERROR;
1160 }
1161 /* Enable the TIM Capture/Compare 4 DMA request */
1162 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1163 break;
1164 }
1165
1166 default:
1167 status = HAL_ERROR;
1168 break;
1169 }
1170
1171 if (status == HAL_OK)
1172 {
1173 /* Enable the Output compare channel */
1174 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1175
1176 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1177 {
1178 /* Enable the main output */
1179 __HAL_TIM_MOE_ENABLE(htim);
1180 }
1181
1182 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1183 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1184 {
1185 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1186 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1187 {
1188 __HAL_TIM_ENABLE(htim);
1189 }
1190 }
1191 else
1192 {
1193 __HAL_TIM_ENABLE(htim);
1194 }
1195 }
1196
1197 /* Return function status */
1198 return status;
1199 }
1200
1201 /**
1202 * @brief Stops the TIM Output Compare signal generation in DMA mode.
1203 * @param htim TIM Output Compare handle
1204 * @param Channel TIM Channel to be disabled
1205 * This parameter can be one of the following values:
1206 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1207 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1208 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1209 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1210 * @retval HAL status
1211 */
HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1212 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1213 {
1214 HAL_StatusTypeDef status = HAL_OK;
1215
1216 /* Check the parameters */
1217 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1218
1219 switch (Channel)
1220 {
1221 case TIM_CHANNEL_1:
1222 {
1223 /* Disable the TIM Capture/Compare 1 DMA request */
1224 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1225 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1226 break;
1227 }
1228
1229 case TIM_CHANNEL_2:
1230 {
1231 /* Disable the TIM Capture/Compare 2 DMA request */
1232 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1233 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1234 break;
1235 }
1236
1237 case TIM_CHANNEL_3:
1238 {
1239 /* Disable the TIM Capture/Compare 3 DMA request */
1240 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1241 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1242 break;
1243 }
1244
1245 case TIM_CHANNEL_4:
1246 {
1247 /* Disable the TIM Capture/Compare 4 interrupt */
1248 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1249 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1250 break;
1251 }
1252
1253 default:
1254 status = HAL_ERROR;
1255 break;
1256 }
1257
1258 if (status == HAL_OK)
1259 {
1260 /* Disable the Output compare channel */
1261 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1262
1263 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1264 {
1265 /* Disable the Main Output */
1266 __HAL_TIM_MOE_DISABLE(htim);
1267 }
1268
1269 /* Disable the Peripheral */
1270 __HAL_TIM_DISABLE(htim);
1271
1272 /* Set the TIM channel state */
1273 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1274 }
1275
1276 /* Return function status */
1277 return status;
1278 }
1279
1280 /**
1281 * @}
1282 */
1283
1284 /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
1285 * @brief TIM PWM functions
1286 *
1287 @verbatim
1288 ==============================================================================
1289 ##### TIM PWM functions #####
1290 ==============================================================================
1291 [..]
1292 This section provides functions allowing to:
1293 (+) Initialize and configure the TIM PWM.
1294 (+) De-initialize the TIM PWM.
1295 (+) Start the TIM PWM.
1296 (+) Stop the TIM PWM.
1297 (+) Start the TIM PWM and enable interrupt.
1298 (+) Stop the TIM PWM and disable interrupt.
1299 (+) Start the TIM PWM and enable DMA transfer.
1300 (+) Stop the TIM PWM and disable DMA transfer.
1301
1302 @endverbatim
1303 * @{
1304 */
1305 /**
1306 * @brief Initializes the TIM PWM Time Base according to the specified
1307 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1308 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1309 * requires a timer reset to avoid unexpected direction
1310 * due to DIR bit readonly in center aligned mode.
1311 * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
1312 * @param htim TIM PWM handle
1313 * @retval HAL status
1314 */
HAL_TIM_PWM_Init(TIM_HandleTypeDef * htim)1315 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
1316 {
1317 /* Check the TIM handle allocation */
1318 if (htim == NULL)
1319 {
1320 return HAL_ERROR;
1321 }
1322
1323 /* Check the parameters */
1324 assert_param(IS_TIM_INSTANCE(htim->Instance));
1325 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1326 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1327 assert_param(IS_TIM_PERIOD(htim->Init.Period));
1328 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1329
1330 if (htim->State == HAL_TIM_STATE_RESET)
1331 {
1332 /* Allocate lock resource and initialize it */
1333 htim->Lock = HAL_UNLOCKED;
1334
1335 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1336 /* Reset interrupt callbacks to legacy weak callbacks */
1337 TIM_ResetCallback(htim);
1338
1339 if (htim->PWM_MspInitCallback == NULL)
1340 {
1341 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
1342 }
1343 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1344 htim->PWM_MspInitCallback(htim);
1345 #else
1346 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1347 HAL_TIM_PWM_MspInit(htim);
1348 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1349 }
1350
1351 /* Set the TIM state */
1352 htim->State = HAL_TIM_STATE_BUSY;
1353
1354 /* Init the base time for the PWM */
1355 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1356
1357 /* Initialize the DMA burst operation state */
1358 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
1359
1360 /* Initialize the TIM channels state */
1361 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1362 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1363
1364 /* Initialize the TIM state*/
1365 htim->State = HAL_TIM_STATE_READY;
1366
1367 return HAL_OK;
1368 }
1369
1370 /**
1371 * @brief DeInitializes the TIM peripheral
1372 * @param htim TIM PWM handle
1373 * @retval HAL status
1374 */
HAL_TIM_PWM_DeInit(TIM_HandleTypeDef * htim)1375 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1376 {
1377 /* Check the parameters */
1378 assert_param(IS_TIM_INSTANCE(htim->Instance));
1379
1380 htim->State = HAL_TIM_STATE_BUSY;
1381
1382 /* Disable the TIM Peripheral Clock */
1383 __HAL_TIM_DISABLE(htim);
1384
1385 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1386 if (htim->PWM_MspDeInitCallback == NULL)
1387 {
1388 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
1389 }
1390 /* DeInit the low level hardware */
1391 htim->PWM_MspDeInitCallback(htim);
1392 #else
1393 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1394 HAL_TIM_PWM_MspDeInit(htim);
1395 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1396
1397 /* Change the DMA burst operation state */
1398 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
1399
1400 /* Change the TIM channels state */
1401 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1402 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1403
1404 /* Change TIM state */
1405 htim->State = HAL_TIM_STATE_RESET;
1406
1407 /* Release Lock */
1408 __HAL_UNLOCK(htim);
1409
1410 return HAL_OK;
1411 }
1412
1413 /**
1414 * @brief Initializes the TIM PWM MSP.
1415 * @param htim TIM PWM handle
1416 * @retval None
1417 */
HAL_TIM_PWM_MspInit(TIM_HandleTypeDef * htim)1418 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1419 {
1420 /* Prevent unused argument(s) compilation warning */
1421 UNUSED(htim);
1422
1423 /* NOTE : This function should not be modified, when the callback is needed,
1424 the HAL_TIM_PWM_MspInit could be implemented in the user file
1425 */
1426 }
1427
1428 /**
1429 * @brief DeInitializes TIM PWM MSP.
1430 * @param htim TIM PWM handle
1431 * @retval None
1432 */
HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef * htim)1433 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1434 {
1435 /* Prevent unused argument(s) compilation warning */
1436 UNUSED(htim);
1437
1438 /* NOTE : This function should not be modified, when the callback is needed,
1439 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1440 */
1441 }
1442
1443 /**
1444 * @brief Starts the PWM signal generation.
1445 * @param htim TIM handle
1446 * @param Channel TIM Channels to be enabled
1447 * This parameter can be one of the following values:
1448 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1449 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1450 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1451 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1452 * @retval HAL status
1453 */
HAL_TIM_PWM_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1454 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1455 {
1456 uint32_t tmpsmcr;
1457
1458 /* Check the parameters */
1459 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1460
1461 /* Check the TIM channel state */
1462 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1463 {
1464 return HAL_ERROR;
1465 }
1466
1467 /* Set the TIM channel state */
1468 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1469
1470 /* Enable the Capture compare channel */
1471 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1472
1473 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1474 {
1475 /* Enable the main output */
1476 __HAL_TIM_MOE_ENABLE(htim);
1477 }
1478
1479 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1480 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1481 {
1482 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1483 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1484 {
1485 __HAL_TIM_ENABLE(htim);
1486 }
1487 }
1488 else
1489 {
1490 __HAL_TIM_ENABLE(htim);
1491 }
1492
1493 /* Return function status */
1494 return HAL_OK;
1495 }
1496
1497 /**
1498 * @brief Stops the PWM signal generation.
1499 * @param htim TIM PWM handle
1500 * @param Channel TIM Channels to be disabled
1501 * This parameter can be one of the following values:
1502 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1503 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1504 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1505 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1506 * @retval HAL status
1507 */
HAL_TIM_PWM_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1508 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1509 {
1510 /* Check the parameters */
1511 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1512
1513 /* Disable the Capture compare channel */
1514 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1515
1516 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1517 {
1518 /* Disable the Main Output */
1519 __HAL_TIM_MOE_DISABLE(htim);
1520 }
1521
1522 /* Disable the Peripheral */
1523 __HAL_TIM_DISABLE(htim);
1524
1525 /* Set the TIM channel state */
1526 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1527
1528 /* Return function status */
1529 return HAL_OK;
1530 }
1531
1532 /**
1533 * @brief Starts the PWM signal generation in interrupt mode.
1534 * @param htim TIM PWM handle
1535 * @param Channel TIM Channel to be enabled
1536 * This parameter can be one of the following values:
1537 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1538 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1539 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1540 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1541 * @retval HAL status
1542 */
HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1543 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1544 {
1545 HAL_StatusTypeDef status = HAL_OK;
1546 uint32_t tmpsmcr;
1547
1548 /* Check the parameters */
1549 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1550
1551 /* Check the TIM channel state */
1552 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1553 {
1554 return HAL_ERROR;
1555 }
1556
1557 /* Set the TIM channel state */
1558 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1559
1560 switch (Channel)
1561 {
1562 case TIM_CHANNEL_1:
1563 {
1564 /* Enable the TIM Capture/Compare 1 interrupt */
1565 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1566 break;
1567 }
1568
1569 case TIM_CHANNEL_2:
1570 {
1571 /* Enable the TIM Capture/Compare 2 interrupt */
1572 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1573 break;
1574 }
1575
1576 case TIM_CHANNEL_3:
1577 {
1578 /* Enable the TIM Capture/Compare 3 interrupt */
1579 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1580 break;
1581 }
1582
1583 case TIM_CHANNEL_4:
1584 {
1585 /* Enable the TIM Capture/Compare 4 interrupt */
1586 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1587 break;
1588 }
1589
1590 default:
1591 status = HAL_ERROR;
1592 break;
1593 }
1594
1595 if (status == HAL_OK)
1596 {
1597 /* Enable the Capture compare channel */
1598 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1599
1600 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1601 {
1602 /* Enable the main output */
1603 __HAL_TIM_MOE_ENABLE(htim);
1604 }
1605
1606 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1607 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1608 {
1609 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1610 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1611 {
1612 __HAL_TIM_ENABLE(htim);
1613 }
1614 }
1615 else
1616 {
1617 __HAL_TIM_ENABLE(htim);
1618 }
1619 }
1620
1621 /* Return function status */
1622 return status;
1623 }
1624
1625 /**
1626 * @brief Stops the PWM signal generation in interrupt mode.
1627 * @param htim TIM PWM handle
1628 * @param Channel TIM Channels to be disabled
1629 * This parameter can be one of the following values:
1630 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1631 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1632 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1633 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1634 * @retval HAL status
1635 */
HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1636 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1637 {
1638 HAL_StatusTypeDef status = HAL_OK;
1639
1640 /* Check the parameters */
1641 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1642
1643 switch (Channel)
1644 {
1645 case TIM_CHANNEL_1:
1646 {
1647 /* Disable the TIM Capture/Compare 1 interrupt */
1648 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1649 break;
1650 }
1651
1652 case TIM_CHANNEL_2:
1653 {
1654 /* Disable the TIM Capture/Compare 2 interrupt */
1655 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1656 break;
1657 }
1658
1659 case TIM_CHANNEL_3:
1660 {
1661 /* Disable the TIM Capture/Compare 3 interrupt */
1662 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1663 break;
1664 }
1665
1666 case TIM_CHANNEL_4:
1667 {
1668 /* Disable the TIM Capture/Compare 4 interrupt */
1669 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1670 break;
1671 }
1672
1673 default:
1674 status = HAL_ERROR;
1675 break;
1676 }
1677
1678 if (status == HAL_OK)
1679 {
1680 /* Disable the Capture compare channel */
1681 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1682
1683 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1684 {
1685 /* Disable the Main Output */
1686 __HAL_TIM_MOE_DISABLE(htim);
1687 }
1688
1689 /* Disable the Peripheral */
1690 __HAL_TIM_DISABLE(htim);
1691
1692 /* Set the TIM channel state */
1693 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1694 }
1695
1696 /* Return function status */
1697 return status;
1698 }
1699
1700 /**
1701 * @brief Starts the TIM PWM signal generation in DMA mode.
1702 * @param htim TIM PWM handle
1703 * @param Channel TIM Channels to be enabled
1704 * This parameter can be one of the following values:
1705 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1706 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1707 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1708 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1709 * @param pData The source Buffer address.
1710 * @param Length The length of data to be transferred from memory to TIM peripheral
1711 * @retval HAL status
1712 */
HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1713 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1714 uint16_t Length)
1715 {
1716 HAL_StatusTypeDef status = HAL_OK;
1717 uint32_t tmpsmcr;
1718
1719 /* Check the parameters */
1720 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1721
1722 /* Set the TIM channel state */
1723 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1724 {
1725 return HAL_BUSY;
1726 }
1727 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1728 {
1729 if ((pData == NULL) || (Length == 0U))
1730 {
1731 return HAL_ERROR;
1732 }
1733 else
1734 {
1735 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1736 }
1737 }
1738 else
1739 {
1740 return HAL_ERROR;
1741 }
1742
1743 switch (Channel)
1744 {
1745 case TIM_CHANNEL_1:
1746 {
1747 /* Set the DMA compare callbacks */
1748 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1749 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1750
1751 /* Set the DMA error callback */
1752 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1753
1754 /* Enable the DMA channel */
1755 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1756 Length) != HAL_OK)
1757 {
1758 /* Return error status */
1759 return HAL_ERROR;
1760 }
1761
1762 /* Enable the TIM Capture/Compare 1 DMA request */
1763 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1764 break;
1765 }
1766
1767 case TIM_CHANNEL_2:
1768 {
1769 /* Set the DMA compare callbacks */
1770 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1771 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1772
1773 /* Set the DMA error callback */
1774 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1775
1776 /* Enable the DMA channel */
1777 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1778 Length) != HAL_OK)
1779 {
1780 /* Return error status */
1781 return HAL_ERROR;
1782 }
1783 /* Enable the TIM Capture/Compare 2 DMA request */
1784 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1785 break;
1786 }
1787
1788 case TIM_CHANNEL_3:
1789 {
1790 /* Set the DMA compare callbacks */
1791 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1792 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1793
1794 /* Set the DMA error callback */
1795 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1796
1797 /* Enable the DMA channel */
1798 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1799 Length) != HAL_OK)
1800 {
1801 /* Return error status */
1802 return HAL_ERROR;
1803 }
1804 /* Enable the TIM Output Capture/Compare 3 request */
1805 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1806 break;
1807 }
1808
1809 case TIM_CHANNEL_4:
1810 {
1811 /* Set the DMA compare callbacks */
1812 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1813 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1814
1815 /* Set the DMA error callback */
1816 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1817
1818 /* Enable the DMA channel */
1819 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1820 Length) != HAL_OK)
1821 {
1822 /* Return error status */
1823 return HAL_ERROR;
1824 }
1825 /* Enable the TIM Capture/Compare 4 DMA request */
1826 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1827 break;
1828 }
1829
1830 default:
1831 status = HAL_ERROR;
1832 break;
1833 }
1834
1835 if (status == HAL_OK)
1836 {
1837 /* Enable the Capture compare channel */
1838 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1839
1840 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1841 {
1842 /* Enable the main output */
1843 __HAL_TIM_MOE_ENABLE(htim);
1844 }
1845
1846 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1847 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1848 {
1849 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1850 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1851 {
1852 __HAL_TIM_ENABLE(htim);
1853 }
1854 }
1855 else
1856 {
1857 __HAL_TIM_ENABLE(htim);
1858 }
1859 }
1860
1861 /* Return function status */
1862 return status;
1863 }
1864
1865 /**
1866 * @brief Stops the TIM PWM signal generation in DMA mode.
1867 * @param htim TIM PWM handle
1868 * @param Channel TIM Channels to be disabled
1869 * This parameter can be one of the following values:
1870 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1871 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1872 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1873 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1874 * @retval HAL status
1875 */
HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1876 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1877 {
1878 HAL_StatusTypeDef status = HAL_OK;
1879
1880 /* Check the parameters */
1881 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1882
1883 switch (Channel)
1884 {
1885 case TIM_CHANNEL_1:
1886 {
1887 /* Disable the TIM Capture/Compare 1 DMA request */
1888 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1889 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1890 break;
1891 }
1892
1893 case TIM_CHANNEL_2:
1894 {
1895 /* Disable the TIM Capture/Compare 2 DMA request */
1896 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1897 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1898 break;
1899 }
1900
1901 case TIM_CHANNEL_3:
1902 {
1903 /* Disable the TIM Capture/Compare 3 DMA request */
1904 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1905 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1906 break;
1907 }
1908
1909 case TIM_CHANNEL_4:
1910 {
1911 /* Disable the TIM Capture/Compare 4 interrupt */
1912 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1913 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1914 break;
1915 }
1916
1917 default:
1918 status = HAL_ERROR;
1919 break;
1920 }
1921
1922 if (status == HAL_OK)
1923 {
1924 /* Disable the Capture compare channel */
1925 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1926
1927 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1928 {
1929 /* Disable the Main Output */
1930 __HAL_TIM_MOE_DISABLE(htim);
1931 }
1932
1933 /* Disable the Peripheral */
1934 __HAL_TIM_DISABLE(htim);
1935
1936 /* Set the TIM channel state */
1937 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1938 }
1939
1940 /* Return function status */
1941 return status;
1942 }
1943
1944 /**
1945 * @}
1946 */
1947
1948 /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
1949 * @brief TIM Input Capture functions
1950 *
1951 @verbatim
1952 ==============================================================================
1953 ##### TIM Input Capture functions #####
1954 ==============================================================================
1955 [..]
1956 This section provides functions allowing to:
1957 (+) Initialize and configure the TIM Input Capture.
1958 (+) De-initialize the TIM Input Capture.
1959 (+) Start the TIM Input Capture.
1960 (+) Stop the TIM Input Capture.
1961 (+) Start the TIM Input Capture and enable interrupt.
1962 (+) Stop the TIM Input Capture and disable interrupt.
1963 (+) Start the TIM Input Capture and enable DMA transfer.
1964 (+) Stop the TIM Input Capture and disable DMA transfer.
1965
1966 @endverbatim
1967 * @{
1968 */
1969 /**
1970 * @brief Initializes the TIM Input Capture Time base according to the specified
1971 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1972 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1973 * requires a timer reset to avoid unexpected direction
1974 * due to DIR bit readonly in center aligned mode.
1975 * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
1976 * @param htim TIM Input Capture handle
1977 * @retval HAL status
1978 */
HAL_TIM_IC_Init(TIM_HandleTypeDef * htim)1979 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1980 {
1981 /* Check the TIM handle allocation */
1982 if (htim == NULL)
1983 {
1984 return HAL_ERROR;
1985 }
1986
1987 /* Check the parameters */
1988 assert_param(IS_TIM_INSTANCE(htim->Instance));
1989 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1990 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1991 assert_param(IS_TIM_PERIOD(htim->Init.Period));
1992 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1993
1994 if (htim->State == HAL_TIM_STATE_RESET)
1995 {
1996 /* Allocate lock resource and initialize it */
1997 htim->Lock = HAL_UNLOCKED;
1998
1999 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2000 /* Reset interrupt callbacks to legacy weak callbacks */
2001 TIM_ResetCallback(htim);
2002
2003 if (htim->IC_MspInitCallback == NULL)
2004 {
2005 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
2006 }
2007 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2008 htim->IC_MspInitCallback(htim);
2009 #else
2010 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2011 HAL_TIM_IC_MspInit(htim);
2012 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2013 }
2014
2015 /* Set the TIM state */
2016 htim->State = HAL_TIM_STATE_BUSY;
2017
2018 /* Init the base time for the input capture */
2019 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2020
2021 /* Initialize the DMA burst operation state */
2022 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2023
2024 /* Initialize the TIM channels state */
2025 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
2026 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
2027
2028 /* Initialize the TIM state*/
2029 htim->State = HAL_TIM_STATE_READY;
2030
2031 return HAL_OK;
2032 }
2033
2034 /**
2035 * @brief DeInitializes the TIM peripheral
2036 * @param htim TIM Input Capture handle
2037 * @retval HAL status
2038 */
HAL_TIM_IC_DeInit(TIM_HandleTypeDef * htim)2039 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
2040 {
2041 /* Check the parameters */
2042 assert_param(IS_TIM_INSTANCE(htim->Instance));
2043
2044 htim->State = HAL_TIM_STATE_BUSY;
2045
2046 /* Disable the TIM Peripheral Clock */
2047 __HAL_TIM_DISABLE(htim);
2048
2049 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2050 if (htim->IC_MspDeInitCallback == NULL)
2051 {
2052 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
2053 }
2054 /* DeInit the low level hardware */
2055 htim->IC_MspDeInitCallback(htim);
2056 #else
2057 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
2058 HAL_TIM_IC_MspDeInit(htim);
2059 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2060
2061 /* Change the DMA burst operation state */
2062 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2063
2064 /* Change the TIM channels state */
2065 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2066 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2067
2068 /* Change TIM state */
2069 htim->State = HAL_TIM_STATE_RESET;
2070
2071 /* Release Lock */
2072 __HAL_UNLOCK(htim);
2073
2074 return HAL_OK;
2075 }
2076
2077 /**
2078 * @brief Initializes the TIM Input Capture MSP.
2079 * @param htim TIM Input Capture handle
2080 * @retval None
2081 */
HAL_TIM_IC_MspInit(TIM_HandleTypeDef * htim)2082 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
2083 {
2084 /* Prevent unused argument(s) compilation warning */
2085 UNUSED(htim);
2086
2087 /* NOTE : This function should not be modified, when the callback is needed,
2088 the HAL_TIM_IC_MspInit could be implemented in the user file
2089 */
2090 }
2091
2092 /**
2093 * @brief DeInitializes TIM Input Capture MSP.
2094 * @param htim TIM handle
2095 * @retval None
2096 */
HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef * htim)2097 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
2098 {
2099 /* Prevent unused argument(s) compilation warning */
2100 UNUSED(htim);
2101
2102 /* NOTE : This function should not be modified, when the callback is needed,
2103 the HAL_TIM_IC_MspDeInit could be implemented in the user file
2104 */
2105 }
2106
2107 /**
2108 * @brief Starts the TIM Input Capture measurement.
2109 * @param htim TIM Input Capture handle
2110 * @param Channel TIM Channels to be enabled
2111 * This parameter can be one of the following values:
2112 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2113 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2114 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2115 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2116 * @retval HAL status
2117 */
HAL_TIM_IC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)2118 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2119 {
2120 uint32_t tmpsmcr;
2121 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2122 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2123
2124 /* Check the parameters */
2125 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2126
2127 /* Check the TIM channel state */
2128 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2129 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2130 {
2131 return HAL_ERROR;
2132 }
2133
2134 /* Set the TIM channel state */
2135 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2136 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2137
2138 /* Enable the Input Capture channel */
2139 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2140
2141 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2142 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2143 {
2144 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2145 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2146 {
2147 __HAL_TIM_ENABLE(htim);
2148 }
2149 }
2150 else
2151 {
2152 __HAL_TIM_ENABLE(htim);
2153 }
2154
2155 /* Return function status */
2156 return HAL_OK;
2157 }
2158
2159 /**
2160 * @brief Stops the TIM Input Capture measurement.
2161 * @param htim TIM Input Capture handle
2162 * @param Channel TIM Channels to be disabled
2163 * This parameter can be one of the following values:
2164 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2165 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2166 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2167 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2168 * @retval HAL status
2169 */
HAL_TIM_IC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)2170 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2171 {
2172 /* Check the parameters */
2173 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2174
2175 /* Disable the Input Capture channel */
2176 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2177
2178 /* Disable the Peripheral */
2179 __HAL_TIM_DISABLE(htim);
2180
2181 /* Set the TIM channel state */
2182 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2183 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2184
2185 /* Return function status */
2186 return HAL_OK;
2187 }
2188
2189 /**
2190 * @brief Starts the TIM Input Capture measurement in interrupt mode.
2191 * @param htim TIM Input Capture handle
2192 * @param Channel TIM Channels to be enabled
2193 * This parameter can be one of the following values:
2194 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2195 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2196 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2197 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2198 * @retval HAL status
2199 */
HAL_TIM_IC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2200 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2201 {
2202 HAL_StatusTypeDef status = HAL_OK;
2203 uint32_t tmpsmcr;
2204
2205 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2206 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2207
2208 /* Check the parameters */
2209 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2210
2211 /* Check the TIM channel state */
2212 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2213 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2214 {
2215 return HAL_ERROR;
2216 }
2217
2218 /* Set the TIM channel state */
2219 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2220 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2221
2222 switch (Channel)
2223 {
2224 case TIM_CHANNEL_1:
2225 {
2226 /* Enable the TIM Capture/Compare 1 interrupt */
2227 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2228 break;
2229 }
2230
2231 case TIM_CHANNEL_2:
2232 {
2233 /* Enable the TIM Capture/Compare 2 interrupt */
2234 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2235 break;
2236 }
2237
2238 case TIM_CHANNEL_3:
2239 {
2240 /* Enable the TIM Capture/Compare 3 interrupt */
2241 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
2242 break;
2243 }
2244
2245 case TIM_CHANNEL_4:
2246 {
2247 /* Enable the TIM Capture/Compare 4 interrupt */
2248 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
2249 break;
2250 }
2251
2252 default:
2253 status = HAL_ERROR;
2254 break;
2255 }
2256
2257 if (status == HAL_OK)
2258 {
2259 /* Enable the Input Capture channel */
2260 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2261
2262 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2263 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2264 {
2265 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2266 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2267 {
2268 __HAL_TIM_ENABLE(htim);
2269 }
2270 }
2271 else
2272 {
2273 __HAL_TIM_ENABLE(htim);
2274 }
2275 }
2276
2277 /* Return function status */
2278 return status;
2279 }
2280
2281 /**
2282 * @brief Stops the TIM Input Capture measurement in interrupt mode.
2283 * @param htim TIM Input Capture handle
2284 * @param Channel TIM Channels to be disabled
2285 * This parameter can be one of the following values:
2286 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2287 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2288 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2289 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2290 * @retval HAL status
2291 */
HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2292 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2293 {
2294 HAL_StatusTypeDef status = HAL_OK;
2295
2296 /* Check the parameters */
2297 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2298
2299 switch (Channel)
2300 {
2301 case TIM_CHANNEL_1:
2302 {
2303 /* Disable the TIM Capture/Compare 1 interrupt */
2304 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2305 break;
2306 }
2307
2308 case TIM_CHANNEL_2:
2309 {
2310 /* Disable the TIM Capture/Compare 2 interrupt */
2311 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2312 break;
2313 }
2314
2315 case TIM_CHANNEL_3:
2316 {
2317 /* Disable the TIM Capture/Compare 3 interrupt */
2318 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
2319 break;
2320 }
2321
2322 case TIM_CHANNEL_4:
2323 {
2324 /* Disable the TIM Capture/Compare 4 interrupt */
2325 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
2326 break;
2327 }
2328
2329 default:
2330 status = HAL_ERROR;
2331 break;
2332 }
2333
2334 if (status == HAL_OK)
2335 {
2336 /* Disable the Input Capture channel */
2337 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2338
2339 /* Disable the Peripheral */
2340 __HAL_TIM_DISABLE(htim);
2341
2342 /* Set the TIM channel state */
2343 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2344 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2345 }
2346
2347 /* Return function status */
2348 return status;
2349 }
2350
2351 /**
2352 * @brief Starts the TIM Input Capture measurement in DMA mode.
2353 * @param htim TIM Input Capture handle
2354 * @param Channel TIM Channels to be enabled
2355 * This parameter can be one of the following values:
2356 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2357 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2358 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2359 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2360 * @param pData The destination Buffer address.
2361 * @param Length The length of data to be transferred from TIM peripheral to memory.
2362 * @retval HAL status
2363 */
HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)2364 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
2365 {
2366 HAL_StatusTypeDef status = HAL_OK;
2367 uint32_t tmpsmcr;
2368
2369 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2370 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2371
2372 /* Check the parameters */
2373 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2374 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2375
2376 /* Set the TIM channel state */
2377 if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
2378 || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
2379 {
2380 return HAL_BUSY;
2381 }
2382 else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
2383 && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
2384 {
2385 if ((pData == NULL) || (Length == 0U))
2386 {
2387 return HAL_ERROR;
2388 }
2389 else
2390 {
2391 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2392 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2393 }
2394 }
2395 else
2396 {
2397 return HAL_ERROR;
2398 }
2399
2400 /* Enable the Input Capture channel */
2401 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2402
2403 switch (Channel)
2404 {
2405 case TIM_CHANNEL_1:
2406 {
2407 /* Set the DMA capture callbacks */
2408 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2409 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2410
2411 /* Set the DMA error callback */
2412 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2413
2414 /* Enable the DMA channel */
2415 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
2416 Length) != HAL_OK)
2417 {
2418 /* Return error status */
2419 return HAL_ERROR;
2420 }
2421 /* Enable the TIM Capture/Compare 1 DMA request */
2422 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2423 break;
2424 }
2425
2426 case TIM_CHANNEL_2:
2427 {
2428 /* Set the DMA capture callbacks */
2429 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2430 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2431
2432 /* Set the DMA error callback */
2433 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2434
2435 /* Enable the DMA channel */
2436 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
2437 Length) != HAL_OK)
2438 {
2439 /* Return error status */
2440 return HAL_ERROR;
2441 }
2442 /* Enable the TIM Capture/Compare 2 DMA request */
2443 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2444 break;
2445 }
2446
2447 case TIM_CHANNEL_3:
2448 {
2449 /* Set the DMA capture callbacks */
2450 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
2451 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2452
2453 /* Set the DMA error callback */
2454 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
2455
2456 /* Enable the DMA channel */
2457 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
2458 Length) != HAL_OK)
2459 {
2460 /* Return error status */
2461 return HAL_ERROR;
2462 }
2463 /* Enable the TIM Capture/Compare 3 DMA request */
2464 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
2465 break;
2466 }
2467
2468 case TIM_CHANNEL_4:
2469 {
2470 /* Set the DMA capture callbacks */
2471 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
2472 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2473
2474 /* Set the DMA error callback */
2475 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
2476
2477 /* Enable the DMA channel */
2478 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
2479 Length) != HAL_OK)
2480 {
2481 /* Return error status */
2482 return HAL_ERROR;
2483 }
2484 /* Enable the TIM Capture/Compare 4 DMA request */
2485 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
2486 break;
2487 }
2488
2489 default:
2490 status = HAL_ERROR;
2491 break;
2492 }
2493
2494 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2495 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2496 {
2497 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2498 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2499 {
2500 __HAL_TIM_ENABLE(htim);
2501 }
2502 }
2503 else
2504 {
2505 __HAL_TIM_ENABLE(htim);
2506 }
2507
2508 /* Return function status */
2509 return status;
2510 }
2511
2512 /**
2513 * @brief Stops the TIM Input Capture measurement in DMA mode.
2514 * @param htim TIM Input Capture handle
2515 * @param Channel TIM Channels to be disabled
2516 * This parameter can be one of the following values:
2517 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2518 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2519 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2520 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2521 * @retval HAL status
2522 */
HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)2523 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2524 {
2525 HAL_StatusTypeDef status = HAL_OK;
2526
2527 /* Check the parameters */
2528 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2529 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2530
2531 /* Disable the Input Capture channel */
2532 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2533
2534 switch (Channel)
2535 {
2536 case TIM_CHANNEL_1:
2537 {
2538 /* Disable the TIM Capture/Compare 1 DMA request */
2539 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2540 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
2541 break;
2542 }
2543
2544 case TIM_CHANNEL_2:
2545 {
2546 /* Disable the TIM Capture/Compare 2 DMA request */
2547 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2548 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
2549 break;
2550 }
2551
2552 case TIM_CHANNEL_3:
2553 {
2554 /* Disable the TIM Capture/Compare 3 DMA request */
2555 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
2556 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
2557 break;
2558 }
2559
2560 case TIM_CHANNEL_4:
2561 {
2562 /* Disable the TIM Capture/Compare 4 DMA request */
2563 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
2564 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
2565 break;
2566 }
2567
2568 default:
2569 status = HAL_ERROR;
2570 break;
2571 }
2572
2573 if (status == HAL_OK)
2574 {
2575 /* Disable the Peripheral */
2576 __HAL_TIM_DISABLE(htim);
2577
2578 /* Set the TIM channel state */
2579 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2580 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2581 }
2582
2583 /* Return function status */
2584 return status;
2585 }
2586 /**
2587 * @}
2588 */
2589
2590 /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2591 * @brief TIM One Pulse functions
2592 *
2593 @verbatim
2594 ==============================================================================
2595 ##### TIM One Pulse functions #####
2596 ==============================================================================
2597 [..]
2598 This section provides functions allowing to:
2599 (+) Initialize and configure the TIM One Pulse.
2600 (+) De-initialize the TIM One Pulse.
2601 (+) Start the TIM One Pulse.
2602 (+) Stop the TIM One Pulse.
2603 (+) Start the TIM One Pulse and enable interrupt.
2604 (+) Stop the TIM One Pulse and disable interrupt.
2605 (+) Start the TIM One Pulse and enable DMA transfer.
2606 (+) Stop the TIM One Pulse and disable DMA transfer.
2607
2608 @endverbatim
2609 * @{
2610 */
2611 /**
2612 * @brief Initializes the TIM One Pulse Time Base according to the specified
2613 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
2614 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2615 * requires a timer reset to avoid unexpected direction
2616 * due to DIR bit readonly in center aligned mode.
2617 * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
2618 * @note When the timer instance is initialized in One Pulse mode, timer
2619 * channels 1 and channel 2 are reserved and cannot be used for other
2620 * purpose.
2621 * @param htim TIM One Pulse handle
2622 * @param OnePulseMode Select the One pulse mode.
2623 * This parameter can be one of the following values:
2624 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
2625 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
2626 * @retval HAL status
2627 */
HAL_TIM_OnePulse_Init(TIM_HandleTypeDef * htim,uint32_t OnePulseMode)2628 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
2629 {
2630 /* Check the TIM handle allocation */
2631 if (htim == NULL)
2632 {
2633 return HAL_ERROR;
2634 }
2635
2636 /* Check the parameters */
2637 assert_param(IS_TIM_INSTANCE(htim->Instance));
2638 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2639 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2640 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
2641 assert_param(IS_TIM_PERIOD(htim->Init.Period));
2642 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2643
2644 if (htim->State == HAL_TIM_STATE_RESET)
2645 {
2646 /* Allocate lock resource and initialize it */
2647 htim->Lock = HAL_UNLOCKED;
2648
2649 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2650 /* Reset interrupt callbacks to legacy weak callbacks */
2651 TIM_ResetCallback(htim);
2652
2653 if (htim->OnePulse_MspInitCallback == NULL)
2654 {
2655 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
2656 }
2657 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2658 htim->OnePulse_MspInitCallback(htim);
2659 #else
2660 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2661 HAL_TIM_OnePulse_MspInit(htim);
2662 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2663 }
2664
2665 /* Set the TIM state */
2666 htim->State = HAL_TIM_STATE_BUSY;
2667
2668 /* Configure the Time base in the One Pulse Mode */
2669 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2670
2671 /* Reset the OPM Bit */
2672 htim->Instance->CR1 &= ~TIM_CR1_OPM;
2673
2674 /* Configure the OPM Mode */
2675 htim->Instance->CR1 |= OnePulseMode;
2676
2677 /* Initialize the DMA burst operation state */
2678 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2679
2680 /* Initialize the TIM channels state */
2681 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2682 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2683 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2684 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2685
2686 /* Initialize the TIM state*/
2687 htim->State = HAL_TIM_STATE_READY;
2688
2689 return HAL_OK;
2690 }
2691
2692 /**
2693 * @brief DeInitializes the TIM One Pulse
2694 * @param htim TIM One Pulse handle
2695 * @retval HAL status
2696 */
HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef * htim)2697 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
2698 {
2699 /* Check the parameters */
2700 assert_param(IS_TIM_INSTANCE(htim->Instance));
2701
2702 htim->State = HAL_TIM_STATE_BUSY;
2703
2704 /* Disable the TIM Peripheral Clock */
2705 __HAL_TIM_DISABLE(htim);
2706
2707 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2708 if (htim->OnePulse_MspDeInitCallback == NULL)
2709 {
2710 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
2711 }
2712 /* DeInit the low level hardware */
2713 htim->OnePulse_MspDeInitCallback(htim);
2714 #else
2715 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2716 HAL_TIM_OnePulse_MspDeInit(htim);
2717 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2718
2719 /* Change the DMA burst operation state */
2720 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2721
2722 /* Set the TIM channel state */
2723 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2724 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2725 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2726 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2727
2728 /* Change TIM state */
2729 htim->State = HAL_TIM_STATE_RESET;
2730
2731 /* Release Lock */
2732 __HAL_UNLOCK(htim);
2733
2734 return HAL_OK;
2735 }
2736
2737 /**
2738 * @brief Initializes the TIM One Pulse MSP.
2739 * @param htim TIM One Pulse handle
2740 * @retval None
2741 */
HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef * htim)2742 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2743 {
2744 /* Prevent unused argument(s) compilation warning */
2745 UNUSED(htim);
2746
2747 /* NOTE : This function should not be modified, when the callback is needed,
2748 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2749 */
2750 }
2751
2752 /**
2753 * @brief DeInitializes TIM One Pulse MSP.
2754 * @param htim TIM One Pulse handle
2755 * @retval None
2756 */
HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef * htim)2757 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2758 {
2759 /* Prevent unused argument(s) compilation warning */
2760 UNUSED(htim);
2761
2762 /* NOTE : This function should not be modified, when the callback is needed,
2763 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2764 */
2765 }
2766
2767 /**
2768 * @brief Starts the TIM One Pulse signal generation.
2769 * @note Though OutputChannel parameter is deprecated and ignored by the function
2770 * it has been kept to avoid HAL_TIM API compatibility break.
2771 * @note The pulse output channel is determined when calling
2772 * @ref HAL_TIM_OnePulse_ConfigChannel().
2773 * @param htim TIM One Pulse handle
2774 * @param OutputChannel See note above
2775 * @retval HAL status
2776 */
HAL_TIM_OnePulse_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2777 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2778 {
2779 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2780 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2781 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2782 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2783
2784 /* Prevent unused argument(s) compilation warning */
2785 UNUSED(OutputChannel);
2786
2787 /* Check the TIM channels state */
2788 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2789 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2790 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2791 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2792 {
2793 return HAL_ERROR;
2794 }
2795
2796 /* Set the TIM channels state */
2797 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2798 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2799 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2800 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2801
2802 /* Enable the Capture compare and the Input Capture channels
2803 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2804 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2805 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2806 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2807
2808 No need to enable the counter, it's enabled automatically by hardware
2809 (the counter starts in response to a stimulus and generate a pulse */
2810
2811 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2812 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2813
2814 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2815 {
2816 /* Enable the main output */
2817 __HAL_TIM_MOE_ENABLE(htim);
2818 }
2819
2820 /* Return function status */
2821 return HAL_OK;
2822 }
2823
2824 /**
2825 * @brief Stops the TIM One Pulse signal generation.
2826 * @note Though OutputChannel parameter is deprecated and ignored by the function
2827 * it has been kept to avoid HAL_TIM API compatibility break.
2828 * @note The pulse output channel is determined when calling
2829 * @ref HAL_TIM_OnePulse_ConfigChannel().
2830 * @param htim TIM One Pulse handle
2831 * @param OutputChannel See note above
2832 * @retval HAL status
2833 */
HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2834 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2835 {
2836 /* Prevent unused argument(s) compilation warning */
2837 UNUSED(OutputChannel);
2838
2839 /* Disable the Capture compare and the Input Capture channels
2840 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2841 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2842 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2843 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2844
2845 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2846 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2847
2848 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2849 {
2850 /* Disable the Main Output */
2851 __HAL_TIM_MOE_DISABLE(htim);
2852 }
2853
2854 /* Disable the Peripheral */
2855 __HAL_TIM_DISABLE(htim);
2856
2857 /* Set the TIM channels state */
2858 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2859 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2860 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2861 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2862
2863 /* Return function status */
2864 return HAL_OK;
2865 }
2866
2867 /**
2868 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2869 * @note Though OutputChannel parameter is deprecated and ignored by the function
2870 * it has been kept to avoid HAL_TIM API compatibility break.
2871 * @note The pulse output channel is determined when calling
2872 * @ref HAL_TIM_OnePulse_ConfigChannel().
2873 * @param htim TIM One Pulse handle
2874 * @param OutputChannel See note above
2875 * @retval HAL status
2876 */
HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2877 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2878 {
2879 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2880 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2881 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2882 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2883
2884 /* Prevent unused argument(s) compilation warning */
2885 UNUSED(OutputChannel);
2886
2887 /* Check the TIM channels state */
2888 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2889 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2890 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2891 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2892 {
2893 return HAL_ERROR;
2894 }
2895
2896 /* Set the TIM channels state */
2897 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2898 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2899 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2900 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2901
2902 /* Enable the Capture compare and the Input Capture channels
2903 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2904 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2905 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2906 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2907
2908 No need to enable the counter, it's enabled automatically by hardware
2909 (the counter starts in response to a stimulus and generate a pulse */
2910
2911 /* Enable the TIM Capture/Compare 1 interrupt */
2912 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2913
2914 /* Enable the TIM Capture/Compare 2 interrupt */
2915 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2916
2917 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2918 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2919
2920 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2921 {
2922 /* Enable the main output */
2923 __HAL_TIM_MOE_ENABLE(htim);
2924 }
2925
2926 /* Return function status */
2927 return HAL_OK;
2928 }
2929
2930 /**
2931 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2932 * @note Though OutputChannel parameter is deprecated and ignored by the function
2933 * it has been kept to avoid HAL_TIM API compatibility break.
2934 * @note The pulse output channel is determined when calling
2935 * @ref HAL_TIM_OnePulse_ConfigChannel().
2936 * @param htim TIM One Pulse handle
2937 * @param OutputChannel See note above
2938 * @retval HAL status
2939 */
HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2940 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2941 {
2942 /* Prevent unused argument(s) compilation warning */
2943 UNUSED(OutputChannel);
2944
2945 /* Disable the TIM Capture/Compare 1 interrupt */
2946 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2947
2948 /* Disable the TIM Capture/Compare 2 interrupt */
2949 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2950
2951 /* Disable the Capture compare and the Input Capture channels
2952 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2953 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2954 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2955 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2956 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2957 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2958
2959 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2960 {
2961 /* Disable the Main Output */
2962 __HAL_TIM_MOE_DISABLE(htim);
2963 }
2964
2965 /* Disable the Peripheral */
2966 __HAL_TIM_DISABLE(htim);
2967
2968 /* Set the TIM channels state */
2969 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2970 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2971 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2972 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2973
2974 /* Return function status */
2975 return HAL_OK;
2976 }
2977
2978 /**
2979 * @}
2980 */
2981
2982 /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
2983 * @brief TIM Encoder functions
2984 *
2985 @verbatim
2986 ==============================================================================
2987 ##### TIM Encoder functions #####
2988 ==============================================================================
2989 [..]
2990 This section provides functions allowing to:
2991 (+) Initialize and configure the TIM Encoder.
2992 (+) De-initialize the TIM Encoder.
2993 (+) Start the TIM Encoder.
2994 (+) Stop the TIM Encoder.
2995 (+) Start the TIM Encoder and enable interrupt.
2996 (+) Stop the TIM Encoder and disable interrupt.
2997 (+) Start the TIM Encoder and enable DMA transfer.
2998 (+) Stop the TIM Encoder and disable DMA transfer.
2999
3000 @endverbatim
3001 * @{
3002 */
3003 /**
3004 * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
3005 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
3006 * requires a timer reset to avoid unexpected direction
3007 * due to DIR bit readonly in center aligned mode.
3008 * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
3009 * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
3010 * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
3011 * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
3012 * @note When the timer instance is initialized in Encoder mode, timer
3013 * channels 1 and channel 2 are reserved and cannot be used for other
3014 * purpose.
3015 * @param htim TIM Encoder Interface handle
3016 * @param sConfig TIM Encoder Interface configuration structure
3017 * @retval HAL status
3018 */
HAL_TIM_Encoder_Init(TIM_HandleTypeDef * htim,const TIM_Encoder_InitTypeDef * sConfig)3019 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
3020 {
3021 uint32_t tmpsmcr;
3022 uint32_t tmpccmr1;
3023 uint32_t tmpccer;
3024
3025 /* Check the TIM handle allocation */
3026 if (htim == NULL)
3027 {
3028 return HAL_ERROR;
3029 }
3030
3031 /* Check the parameters */
3032 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3033 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
3034 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
3035 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
3036 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
3037 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
3038 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
3039 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
3040 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
3041 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
3042 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
3043 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
3044 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
3045 assert_param(IS_TIM_PERIOD(htim->Init.Period));
3046
3047 if (htim->State == HAL_TIM_STATE_RESET)
3048 {
3049 /* Allocate lock resource and initialize it */
3050 htim->Lock = HAL_UNLOCKED;
3051
3052 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3053 /* Reset interrupt callbacks to legacy weak callbacks */
3054 TIM_ResetCallback(htim);
3055
3056 if (htim->Encoder_MspInitCallback == NULL)
3057 {
3058 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
3059 }
3060 /* Init the low level hardware : GPIO, CLOCK, NVIC */
3061 htim->Encoder_MspInitCallback(htim);
3062 #else
3063 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
3064 HAL_TIM_Encoder_MspInit(htim);
3065 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3066 }
3067
3068 /* Set the TIM state */
3069 htim->State = HAL_TIM_STATE_BUSY;
3070
3071 /* Reset the SMS and ECE bits */
3072 htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
3073
3074 /* Configure the Time base in the Encoder Mode */
3075 TIM_Base_SetConfig(htim->Instance, &htim->Init);
3076
3077 /* Get the TIMx SMCR register value */
3078 tmpsmcr = htim->Instance->SMCR;
3079
3080 /* Get the TIMx CCMR1 register value */
3081 tmpccmr1 = htim->Instance->CCMR1;
3082
3083 /* Get the TIMx CCER register value */
3084 tmpccer = htim->Instance->CCER;
3085
3086 /* Set the encoder Mode */
3087 tmpsmcr |= sConfig->EncoderMode;
3088
3089 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
3090 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
3091 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
3092
3093 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
3094 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
3095 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
3096 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
3097 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
3098
3099 /* Set the TI1 and the TI2 Polarities */
3100 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
3101 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
3102
3103 /* Write to TIMx SMCR */
3104 htim->Instance->SMCR = tmpsmcr;
3105
3106 /* Write to TIMx CCMR1 */
3107 htim->Instance->CCMR1 = tmpccmr1;
3108
3109 /* Write to TIMx CCER */
3110 htim->Instance->CCER = tmpccer;
3111
3112 /* Initialize the DMA burst operation state */
3113 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
3114
3115 /* Set the TIM channels state */
3116 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3117 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3118 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3119 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3120
3121 /* Initialize the TIM state*/
3122 htim->State = HAL_TIM_STATE_READY;
3123
3124 return HAL_OK;
3125 }
3126
3127
3128 /**
3129 * @brief DeInitializes the TIM Encoder interface
3130 * @param htim TIM Encoder Interface handle
3131 * @retval HAL status
3132 */
HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef * htim)3133 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
3134 {
3135 /* Check the parameters */
3136 assert_param(IS_TIM_INSTANCE(htim->Instance));
3137
3138 htim->State = HAL_TIM_STATE_BUSY;
3139
3140 /* Disable the TIM Peripheral Clock */
3141 __HAL_TIM_DISABLE(htim);
3142
3143 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3144 if (htim->Encoder_MspDeInitCallback == NULL)
3145 {
3146 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
3147 }
3148 /* DeInit the low level hardware */
3149 htim->Encoder_MspDeInitCallback(htim);
3150 #else
3151 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
3152 HAL_TIM_Encoder_MspDeInit(htim);
3153 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3154
3155 /* Change the DMA burst operation state */
3156 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
3157
3158 /* Set the TIM channels state */
3159 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3160 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3161 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3162 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3163
3164 /* Change TIM state */
3165 htim->State = HAL_TIM_STATE_RESET;
3166
3167 /* Release Lock */
3168 __HAL_UNLOCK(htim);
3169
3170 return HAL_OK;
3171 }
3172
3173 /**
3174 * @brief Initializes the TIM Encoder Interface MSP.
3175 * @param htim TIM Encoder Interface handle
3176 * @retval None
3177 */
HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef * htim)3178 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
3179 {
3180 /* Prevent unused argument(s) compilation warning */
3181 UNUSED(htim);
3182
3183 /* NOTE : This function should not be modified, when the callback is needed,
3184 the HAL_TIM_Encoder_MspInit could be implemented in the user file
3185 */
3186 }
3187
3188 /**
3189 * @brief DeInitializes TIM Encoder Interface MSP.
3190 * @param htim TIM Encoder Interface handle
3191 * @retval None
3192 */
HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef * htim)3193 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
3194 {
3195 /* Prevent unused argument(s) compilation warning */
3196 UNUSED(htim);
3197
3198 /* NOTE : This function should not be modified, when the callback is needed,
3199 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
3200 */
3201 }
3202
3203 /**
3204 * @brief Starts the TIM Encoder Interface.
3205 * @param htim TIM Encoder Interface handle
3206 * @param Channel TIM Channels to be enabled
3207 * This parameter can be one of the following values:
3208 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3209 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3210 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3211 * @retval HAL status
3212 */
HAL_TIM_Encoder_Start(TIM_HandleTypeDef * htim,uint32_t Channel)3213 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
3214 {
3215 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3216 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3217 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3218 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3219
3220 /* Check the parameters */
3221 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3222
3223 /* Set the TIM channel(s) state */
3224 if (Channel == TIM_CHANNEL_1)
3225 {
3226 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3227 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3228 {
3229 return HAL_ERROR;
3230 }
3231 else
3232 {
3233 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3234 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3235 }
3236 }
3237 else if (Channel == TIM_CHANNEL_2)
3238 {
3239 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3240 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3241 {
3242 return HAL_ERROR;
3243 }
3244 else
3245 {
3246 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3247 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3248 }
3249 }
3250 else
3251 {
3252 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3253 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3254 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3255 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3256 {
3257 return HAL_ERROR;
3258 }
3259 else
3260 {
3261 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3262 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3263 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3264 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3265 }
3266 }
3267
3268 /* Enable the encoder interface channels */
3269 switch (Channel)
3270 {
3271 case TIM_CHANNEL_1:
3272 {
3273 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3274 break;
3275 }
3276
3277 case TIM_CHANNEL_2:
3278 {
3279 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3280 break;
3281 }
3282
3283 default :
3284 {
3285 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3286 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3287 break;
3288 }
3289 }
3290 /* Enable the Peripheral */
3291 __HAL_TIM_ENABLE(htim);
3292
3293 /* Return function status */
3294 return HAL_OK;
3295 }
3296
3297 /**
3298 * @brief Stops the TIM Encoder Interface.
3299 * @param htim TIM Encoder Interface handle
3300 * @param Channel TIM Channels to be disabled
3301 * This parameter can be one of the following values:
3302 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3303 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3304 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3305 * @retval HAL status
3306 */
HAL_TIM_Encoder_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)3307 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
3308 {
3309 /* Check the parameters */
3310 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3311
3312 /* Disable the Input Capture channels 1 and 2
3313 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3314 switch (Channel)
3315 {
3316 case TIM_CHANNEL_1:
3317 {
3318 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3319 break;
3320 }
3321
3322 case TIM_CHANNEL_2:
3323 {
3324 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3325 break;
3326 }
3327
3328 default :
3329 {
3330 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3331 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3332 break;
3333 }
3334 }
3335
3336 /* Disable the Peripheral */
3337 __HAL_TIM_DISABLE(htim);
3338
3339 /* Set the TIM channel(s) state */
3340 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3341 {
3342 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3343 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3344 }
3345 else
3346 {
3347 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3348 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3349 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3350 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3351 }
3352
3353 /* Return function status */
3354 return HAL_OK;
3355 }
3356
3357 /**
3358 * @brief Starts the TIM Encoder Interface in interrupt mode.
3359 * @param htim TIM Encoder Interface handle
3360 * @param Channel TIM Channels to be enabled
3361 * This parameter can be one of the following values:
3362 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3363 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3364 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3365 * @retval HAL status
3366 */
HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3367 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3368 {
3369 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3370 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3371 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3372 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3373
3374 /* Check the parameters */
3375 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3376
3377 /* Set the TIM channel(s) state */
3378 if (Channel == TIM_CHANNEL_1)
3379 {
3380 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3381 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3382 {
3383 return HAL_ERROR;
3384 }
3385 else
3386 {
3387 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3388 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3389 }
3390 }
3391 else if (Channel == TIM_CHANNEL_2)
3392 {
3393 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3394 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3395 {
3396 return HAL_ERROR;
3397 }
3398 else
3399 {
3400 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3401 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3402 }
3403 }
3404 else
3405 {
3406 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3407 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3408 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3409 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3410 {
3411 return HAL_ERROR;
3412 }
3413 else
3414 {
3415 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3416 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3417 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3418 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3419 }
3420 }
3421
3422 /* Enable the encoder interface channels */
3423 /* Enable the capture compare Interrupts 1 and/or 2 */
3424 switch (Channel)
3425 {
3426 case TIM_CHANNEL_1:
3427 {
3428 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3429 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3430 break;
3431 }
3432
3433 case TIM_CHANNEL_2:
3434 {
3435 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3436 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3437 break;
3438 }
3439
3440 default :
3441 {
3442 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3443 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3444 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3445 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3446 break;
3447 }
3448 }
3449
3450 /* Enable the Peripheral */
3451 __HAL_TIM_ENABLE(htim);
3452
3453 /* Return function status */
3454 return HAL_OK;
3455 }
3456
3457 /**
3458 * @brief Stops the TIM Encoder Interface in interrupt mode.
3459 * @param htim TIM Encoder Interface handle
3460 * @param Channel TIM Channels to be disabled
3461 * This parameter can be one of the following values:
3462 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3463 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3464 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3465 * @retval HAL status
3466 */
HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3467 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3468 {
3469 /* Check the parameters */
3470 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3471
3472 /* Disable the Input Capture channels 1 and 2
3473 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3474 if (Channel == TIM_CHANNEL_1)
3475 {
3476 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3477
3478 /* Disable the capture compare Interrupts 1 */
3479 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3480 }
3481 else if (Channel == TIM_CHANNEL_2)
3482 {
3483 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3484
3485 /* Disable the capture compare Interrupts 2 */
3486 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3487 }
3488 else
3489 {
3490 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3491 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3492
3493 /* Disable the capture compare Interrupts 1 and 2 */
3494 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3495 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3496 }
3497
3498 /* Disable the Peripheral */
3499 __HAL_TIM_DISABLE(htim);
3500
3501 /* Set the TIM channel(s) state */
3502 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3503 {
3504 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3505 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3506 }
3507 else
3508 {
3509 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3510 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3511 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3512 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3513 }
3514
3515 /* Return function status */
3516 return HAL_OK;
3517 }
3518
3519 /**
3520 * @brief Starts the TIM Encoder Interface in DMA mode.
3521 * @param htim TIM Encoder Interface handle
3522 * @param Channel TIM Channels to be enabled
3523 * This parameter can be one of the following values:
3524 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3525 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3526 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3527 * @param pData1 The destination Buffer address for IC1.
3528 * @param pData2 The destination Buffer address for IC2.
3529 * @param Length The length of data to be transferred from TIM peripheral to memory.
3530 * @retval HAL status
3531 */
HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData1,uint32_t * pData2,uint16_t Length)3532 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
3533 uint32_t *pData2, uint16_t Length)
3534 {
3535 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3536 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3537 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3538 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3539
3540 /* Check the parameters */
3541 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3542
3543 /* Set the TIM channel(s) state */
3544 if (Channel == TIM_CHANNEL_1)
3545 {
3546 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3547 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
3548 {
3549 return HAL_BUSY;
3550 }
3551 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3552 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
3553 {
3554 if ((pData1 == NULL) || (Length == 0U))
3555 {
3556 return HAL_ERROR;
3557 }
3558 else
3559 {
3560 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3561 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3562 }
3563 }
3564 else
3565 {
3566 return HAL_ERROR;
3567 }
3568 }
3569 else if (Channel == TIM_CHANNEL_2)
3570 {
3571 if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3572 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3573 {
3574 return HAL_BUSY;
3575 }
3576 else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3577 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3578 {
3579 if ((pData2 == NULL) || (Length == 0U))
3580 {
3581 return HAL_ERROR;
3582 }
3583 else
3584 {
3585 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3586 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3587 }
3588 }
3589 else
3590 {
3591 return HAL_ERROR;
3592 }
3593 }
3594 else
3595 {
3596 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3597 || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3598 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3599 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3600 {
3601 return HAL_BUSY;
3602 }
3603 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3604 && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3605 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3606 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3607 {
3608 if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U))
3609 {
3610 return HAL_ERROR;
3611 }
3612 else
3613 {
3614 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3615 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3616 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3617 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3618 }
3619 }
3620 else
3621 {
3622 return HAL_ERROR;
3623 }
3624 }
3625
3626 switch (Channel)
3627 {
3628 case TIM_CHANNEL_1:
3629 {
3630 /* Set the DMA capture callbacks */
3631 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3632 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3633
3634 /* Set the DMA error callback */
3635 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3636
3637 /* Enable the DMA channel */
3638 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3639 Length) != HAL_OK)
3640 {
3641 /* Return error status */
3642 return HAL_ERROR;
3643 }
3644 /* Enable the TIM Input Capture DMA request */
3645 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3646
3647 /* Enable the Capture compare channel */
3648 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3649
3650 /* Enable the Peripheral */
3651 __HAL_TIM_ENABLE(htim);
3652
3653 break;
3654 }
3655
3656 case TIM_CHANNEL_2:
3657 {
3658 /* Set the DMA capture callbacks */
3659 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3660 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3661
3662 /* Set the DMA error callback */
3663 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
3664 /* Enable the DMA channel */
3665 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3666 Length) != HAL_OK)
3667 {
3668 /* Return error status */
3669 return HAL_ERROR;
3670 }
3671 /* Enable the TIM Input Capture DMA request */
3672 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3673
3674 /* Enable the Capture compare channel */
3675 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3676
3677 /* Enable the Peripheral */
3678 __HAL_TIM_ENABLE(htim);
3679
3680 break;
3681 }
3682
3683 default:
3684 {
3685 /* Set the DMA capture callbacks */
3686 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3687 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3688
3689 /* Set the DMA error callback */
3690 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3691
3692 /* Enable the DMA channel */
3693 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3694 Length) != HAL_OK)
3695 {
3696 /* Return error status */
3697 return HAL_ERROR;
3698 }
3699
3700 /* Set the DMA capture callbacks */
3701 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3702 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3703
3704 /* Set the DMA error callback */
3705 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3706
3707 /* Enable the DMA channel */
3708 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3709 Length) != HAL_OK)
3710 {
3711 /* Return error status */
3712 return HAL_ERROR;
3713 }
3714
3715 /* Enable the TIM Input Capture DMA request */
3716 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3717 /* Enable the TIM Input Capture DMA request */
3718 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3719
3720 /* Enable the Capture compare channel */
3721 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3722 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3723
3724 /* Enable the Peripheral */
3725 __HAL_TIM_ENABLE(htim);
3726
3727 break;
3728 }
3729 }
3730
3731 /* Return function status */
3732 return HAL_OK;
3733 }
3734
3735 /**
3736 * @brief Stops the TIM Encoder Interface in DMA mode.
3737 * @param htim TIM Encoder Interface handle
3738 * @param Channel TIM Channels to be enabled
3739 * This parameter can be one of the following values:
3740 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3741 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3742 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3743 * @retval HAL status
3744 */
HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)3745 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
3746 {
3747 /* Check the parameters */
3748 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3749
3750 /* Disable the Input Capture channels 1 and 2
3751 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3752 if (Channel == TIM_CHANNEL_1)
3753 {
3754 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3755
3756 /* Disable the capture compare DMA Request 1 */
3757 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3758 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3759 }
3760 else if (Channel == TIM_CHANNEL_2)
3761 {
3762 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3763
3764 /* Disable the capture compare DMA Request 2 */
3765 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3766 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3767 }
3768 else
3769 {
3770 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3771 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3772
3773 /* Disable the capture compare DMA Request 1 and 2 */
3774 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3775 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3776 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3777 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3778 }
3779
3780 /* Disable the Peripheral */
3781 __HAL_TIM_DISABLE(htim);
3782
3783 /* Set the TIM channel(s) state */
3784 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3785 {
3786 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3787 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3788 }
3789 else
3790 {
3791 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3792 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3793 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3794 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3795 }
3796
3797 /* Return function status */
3798 return HAL_OK;
3799 }
3800
3801 /**
3802 * @}
3803 */
3804 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
3805 * @brief TIM IRQ handler management
3806 *
3807 @verbatim
3808 ==============================================================================
3809 ##### IRQ handler management #####
3810 ==============================================================================
3811 [..]
3812 This section provides Timer IRQ handler function.
3813
3814 @endverbatim
3815 * @{
3816 */
3817 /**
3818 * @brief This function handles TIM interrupts requests.
3819 * @param htim TIM handle
3820 * @retval None
3821 */
HAL_TIM_IRQHandler(TIM_HandleTypeDef * htim)3822 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
3823 {
3824 uint32_t itsource = htim->Instance->DIER;
3825 uint32_t itflag = htim->Instance->SR;
3826
3827 /* Capture compare 1 event */
3828 if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
3829 {
3830 if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
3831 {
3832 {
3833 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
3834 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3835
3836 /* Input capture event */
3837 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
3838 {
3839 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3840 htim->IC_CaptureCallback(htim);
3841 #else
3842 HAL_TIM_IC_CaptureCallback(htim);
3843 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3844 }
3845 /* Output compare event */
3846 else
3847 {
3848 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3849 htim->OC_DelayElapsedCallback(htim);
3850 htim->PWM_PulseFinishedCallback(htim);
3851 #else
3852 HAL_TIM_OC_DelayElapsedCallback(htim);
3853 HAL_TIM_PWM_PulseFinishedCallback(htim);
3854 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3855 }
3856 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3857 }
3858 }
3859 }
3860 /* Capture compare 2 event */
3861 if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
3862 {
3863 if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
3864 {
3865 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
3866 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3867 /* Input capture event */
3868 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
3869 {
3870 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3871 htim->IC_CaptureCallback(htim);
3872 #else
3873 HAL_TIM_IC_CaptureCallback(htim);
3874 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3875 }
3876 /* Output compare event */
3877 else
3878 {
3879 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3880 htim->OC_DelayElapsedCallback(htim);
3881 htim->PWM_PulseFinishedCallback(htim);
3882 #else
3883 HAL_TIM_OC_DelayElapsedCallback(htim);
3884 HAL_TIM_PWM_PulseFinishedCallback(htim);
3885 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3886 }
3887 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3888 }
3889 }
3890 /* Capture compare 3 event */
3891 if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
3892 {
3893 if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
3894 {
3895 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
3896 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3897 /* Input capture event */
3898 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
3899 {
3900 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3901 htim->IC_CaptureCallback(htim);
3902 #else
3903 HAL_TIM_IC_CaptureCallback(htim);
3904 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3905 }
3906 /* Output compare event */
3907 else
3908 {
3909 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3910 htim->OC_DelayElapsedCallback(htim);
3911 htim->PWM_PulseFinishedCallback(htim);
3912 #else
3913 HAL_TIM_OC_DelayElapsedCallback(htim);
3914 HAL_TIM_PWM_PulseFinishedCallback(htim);
3915 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3916 }
3917 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3918 }
3919 }
3920 /* Capture compare 4 event */
3921 if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
3922 {
3923 if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
3924 {
3925 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
3926 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3927 /* Input capture event */
3928 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
3929 {
3930 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3931 htim->IC_CaptureCallback(htim);
3932 #else
3933 HAL_TIM_IC_CaptureCallback(htim);
3934 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3935 }
3936 /* Output compare event */
3937 else
3938 {
3939 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3940 htim->OC_DelayElapsedCallback(htim);
3941 htim->PWM_PulseFinishedCallback(htim);
3942 #else
3943 HAL_TIM_OC_DelayElapsedCallback(htim);
3944 HAL_TIM_PWM_PulseFinishedCallback(htim);
3945 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3946 }
3947 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3948 }
3949 }
3950 /* TIM Update event */
3951 if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
3952 {
3953 if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
3954 {
3955 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
3956 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3957 htim->PeriodElapsedCallback(htim);
3958 #else
3959 HAL_TIM_PeriodElapsedCallback(htim);
3960 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3961 }
3962 }
3963 /* TIM Break input event */
3964 if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK))
3965 {
3966 if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
3967 {
3968 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK);
3969 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3970 htim->BreakCallback(htim);
3971 #else
3972 HAL_TIMEx_BreakCallback(htim);
3973 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3974 }
3975 }
3976 /* TIM Trigger detection event */
3977 if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
3978 {
3979 if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
3980 {
3981 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
3982 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3983 htim->TriggerCallback(htim);
3984 #else
3985 HAL_TIM_TriggerCallback(htim);
3986 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3987 }
3988 }
3989 /* TIM commutation event */
3990 if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
3991 {
3992 if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
3993 {
3994 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
3995 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3996 htim->CommutationCallback(htim);
3997 #else
3998 HAL_TIMEx_CommutCallback(htim);
3999 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4000 }
4001 }
4002 }
4003
4004 /**
4005 * @}
4006 */
4007
4008 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
4009 * @brief TIM Peripheral Control functions
4010 *
4011 @verbatim
4012 ==============================================================================
4013 ##### Peripheral Control functions #####
4014 ==============================================================================
4015 [..]
4016 This section provides functions allowing to:
4017 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
4018 (+) Configure External Clock source.
4019 (+) Configure Complementary channels, break features and dead time.
4020 (+) Configure Master and the Slave synchronization.
4021 (+) Configure the DMA Burst Mode.
4022
4023 @endverbatim
4024 * @{
4025 */
4026
4027 /**
4028 * @brief Initializes the TIM Output Compare Channels according to the specified
4029 * parameters in the TIM_OC_InitTypeDef.
4030 * @param htim TIM Output Compare handle
4031 * @param sConfig TIM Output Compare configuration structure
4032 * @param Channel TIM Channels to configure
4033 * This parameter can be one of the following values:
4034 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4035 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4036 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4037 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4038 * @retval HAL status
4039 */
HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4040 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
4041 const TIM_OC_InitTypeDef *sConfig,
4042 uint32_t Channel)
4043 {
4044 HAL_StatusTypeDef status = HAL_OK;
4045
4046 /* Check the parameters */
4047 assert_param(IS_TIM_CHANNELS(Channel));
4048 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
4049 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4050
4051 /* Process Locked */
4052 __HAL_LOCK(htim);
4053
4054 switch (Channel)
4055 {
4056 case TIM_CHANNEL_1:
4057 {
4058 /* Check the parameters */
4059 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4060
4061 /* Configure the TIM Channel 1 in Output Compare */
4062 TIM_OC1_SetConfig(htim->Instance, sConfig);
4063 break;
4064 }
4065
4066 case TIM_CHANNEL_2:
4067 {
4068 /* Check the parameters */
4069 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4070
4071 /* Configure the TIM Channel 2 in Output Compare */
4072 TIM_OC2_SetConfig(htim->Instance, sConfig);
4073 break;
4074 }
4075
4076 case TIM_CHANNEL_3:
4077 {
4078 /* Check the parameters */
4079 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4080
4081 /* Configure the TIM Channel 3 in Output Compare */
4082 TIM_OC3_SetConfig(htim->Instance, sConfig);
4083 break;
4084 }
4085
4086 case TIM_CHANNEL_4:
4087 {
4088 /* Check the parameters */
4089 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4090
4091 /* Configure the TIM Channel 4 in Output Compare */
4092 TIM_OC4_SetConfig(htim->Instance, sConfig);
4093 break;
4094 }
4095
4096 default:
4097 status = HAL_ERROR;
4098 break;
4099 }
4100
4101 __HAL_UNLOCK(htim);
4102
4103 return status;
4104 }
4105
4106 /**
4107 * @brief Initializes the TIM Input Capture Channels according to the specified
4108 * parameters in the TIM_IC_InitTypeDef.
4109 * @param htim TIM IC handle
4110 * @param sConfig TIM Input Capture configuration structure
4111 * @param Channel TIM Channel to configure
4112 * This parameter can be one of the following values:
4113 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4114 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4115 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4116 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4117 * @retval HAL status
4118 */
HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_IC_InitTypeDef * sConfig,uint32_t Channel)4119 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
4120 {
4121 HAL_StatusTypeDef status = HAL_OK;
4122
4123 /* Check the parameters */
4124 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4125 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
4126 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
4127 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
4128 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
4129
4130 /* Process Locked */
4131 __HAL_LOCK(htim);
4132
4133 if (Channel == TIM_CHANNEL_1)
4134 {
4135 /* TI1 Configuration */
4136 TIM_TI1_SetConfig(htim->Instance,
4137 sConfig->ICPolarity,
4138 sConfig->ICSelection,
4139 sConfig->ICFilter);
4140
4141 /* Reset the IC1PSC Bits */
4142 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4143
4144 /* Set the IC1PSC value */
4145 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
4146 }
4147 else if (Channel == TIM_CHANNEL_2)
4148 {
4149 /* TI2 Configuration */
4150 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4151
4152 TIM_TI2_SetConfig(htim->Instance,
4153 sConfig->ICPolarity,
4154 sConfig->ICSelection,
4155 sConfig->ICFilter);
4156
4157 /* Reset the IC2PSC Bits */
4158 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4159
4160 /* Set the IC2PSC value */
4161 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
4162 }
4163 else if (Channel == TIM_CHANNEL_3)
4164 {
4165 /* TI3 Configuration */
4166 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4167
4168 TIM_TI3_SetConfig(htim->Instance,
4169 sConfig->ICPolarity,
4170 sConfig->ICSelection,
4171 sConfig->ICFilter);
4172
4173 /* Reset the IC3PSC Bits */
4174 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
4175
4176 /* Set the IC3PSC value */
4177 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
4178 }
4179 else if (Channel == TIM_CHANNEL_4)
4180 {
4181 /* TI4 Configuration */
4182 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4183
4184 TIM_TI4_SetConfig(htim->Instance,
4185 sConfig->ICPolarity,
4186 sConfig->ICSelection,
4187 sConfig->ICFilter);
4188
4189 /* Reset the IC4PSC Bits */
4190 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
4191
4192 /* Set the IC4PSC value */
4193 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
4194 }
4195 else
4196 {
4197 status = HAL_ERROR;
4198 }
4199
4200 __HAL_UNLOCK(htim);
4201
4202 return status;
4203 }
4204
4205 /**
4206 * @brief Initializes the TIM PWM channels according to the specified
4207 * parameters in the TIM_OC_InitTypeDef.
4208 * @param htim TIM PWM handle
4209 * @param sConfig TIM PWM configuration structure
4210 * @param Channel TIM Channels to be configured
4211 * This parameter can be one of the following values:
4212 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4213 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4214 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4215 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4216 * @retval HAL status
4217 */
HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4218 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
4219 const TIM_OC_InitTypeDef *sConfig,
4220 uint32_t Channel)
4221 {
4222 HAL_StatusTypeDef status = HAL_OK;
4223
4224 /* Check the parameters */
4225 assert_param(IS_TIM_CHANNELS(Channel));
4226 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
4227 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4228 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
4229
4230 /* Process Locked */
4231 __HAL_LOCK(htim);
4232
4233 switch (Channel)
4234 {
4235 case TIM_CHANNEL_1:
4236 {
4237 /* Check the parameters */
4238 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4239
4240 /* Configure the Channel 1 in PWM mode */
4241 TIM_OC1_SetConfig(htim->Instance, sConfig);
4242
4243 /* Set the Preload enable bit for channel1 */
4244 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
4245
4246 /* Configure the Output Fast mode */
4247 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
4248 htim->Instance->CCMR1 |= sConfig->OCFastMode;
4249 break;
4250 }
4251
4252 case TIM_CHANNEL_2:
4253 {
4254 /* Check the parameters */
4255 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4256
4257 /* Configure the Channel 2 in PWM mode */
4258 TIM_OC2_SetConfig(htim->Instance, sConfig);
4259
4260 /* Set the Preload enable bit for channel2 */
4261 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
4262
4263 /* Configure the Output Fast mode */
4264 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
4265 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
4266 break;
4267 }
4268
4269 case TIM_CHANNEL_3:
4270 {
4271 /* Check the parameters */
4272 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4273
4274 /* Configure the Channel 3 in PWM mode */
4275 TIM_OC3_SetConfig(htim->Instance, sConfig);
4276
4277 /* Set the Preload enable bit for channel3 */
4278 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
4279
4280 /* Configure the Output Fast mode */
4281 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
4282 htim->Instance->CCMR2 |= sConfig->OCFastMode;
4283 break;
4284 }
4285
4286 case TIM_CHANNEL_4:
4287 {
4288 /* Check the parameters */
4289 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4290
4291 /* Configure the Channel 4 in PWM mode */
4292 TIM_OC4_SetConfig(htim->Instance, sConfig);
4293
4294 /* Set the Preload enable bit for channel4 */
4295 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
4296
4297 /* Configure the Output Fast mode */
4298 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
4299 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
4300 break;
4301 }
4302
4303 default:
4304 status = HAL_ERROR;
4305 break;
4306 }
4307
4308 __HAL_UNLOCK(htim);
4309
4310 return status;
4311 }
4312
4313 /**
4314 * @brief Initializes the TIM One Pulse Channels according to the specified
4315 * parameters in the TIM_OnePulse_InitTypeDef.
4316 * @param htim TIM One Pulse handle
4317 * @param sConfig TIM One Pulse configuration structure
4318 * @param OutputChannel TIM output channel to configure
4319 * This parameter can be one of the following values:
4320 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4321 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4322 * @param InputChannel TIM input Channel to configure
4323 * This parameter can be one of the following values:
4324 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4325 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4326 * @note To output a waveform with a minimum delay user can enable the fast
4327 * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
4328 * output is forced in response to the edge detection on TIx input,
4329 * without taking in account the comparison.
4330 * @retval HAL status
4331 */
HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OnePulse_InitTypeDef * sConfig,uint32_t OutputChannel,uint32_t InputChannel)4332 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
4333 uint32_t OutputChannel, uint32_t InputChannel)
4334 {
4335 HAL_StatusTypeDef status = HAL_OK;
4336 TIM_OC_InitTypeDef temp1;
4337
4338 /* Check the parameters */
4339 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
4340 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
4341
4342 if (OutputChannel != InputChannel)
4343 {
4344 /* Process Locked */
4345 __HAL_LOCK(htim);
4346
4347 htim->State = HAL_TIM_STATE_BUSY;
4348
4349 /* Extract the Output compare configuration from sConfig structure */
4350 temp1.OCMode = sConfig->OCMode;
4351 temp1.Pulse = sConfig->Pulse;
4352 temp1.OCPolarity = sConfig->OCPolarity;
4353 temp1.OCNPolarity = sConfig->OCNPolarity;
4354 temp1.OCIdleState = sConfig->OCIdleState;
4355 temp1.OCNIdleState = sConfig->OCNIdleState;
4356
4357 switch (OutputChannel)
4358 {
4359 case TIM_CHANNEL_1:
4360 {
4361 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4362
4363 TIM_OC1_SetConfig(htim->Instance, &temp1);
4364 break;
4365 }
4366
4367 case TIM_CHANNEL_2:
4368 {
4369 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4370
4371 TIM_OC2_SetConfig(htim->Instance, &temp1);
4372 break;
4373 }
4374
4375 default:
4376 status = HAL_ERROR;
4377 break;
4378 }
4379
4380 if (status == HAL_OK)
4381 {
4382 switch (InputChannel)
4383 {
4384 case TIM_CHANNEL_1:
4385 {
4386 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4387
4388 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
4389 sConfig->ICSelection, sConfig->ICFilter);
4390
4391 /* Reset the IC1PSC Bits */
4392 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4393
4394 /* Select the Trigger source */
4395 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4396 htim->Instance->SMCR |= TIM_TS_TI1FP1;
4397
4398 /* Select the Slave Mode */
4399 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4400 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4401 break;
4402 }
4403
4404 case TIM_CHANNEL_2:
4405 {
4406 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4407
4408 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
4409 sConfig->ICSelection, sConfig->ICFilter);
4410
4411 /* Reset the IC2PSC Bits */
4412 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4413
4414 /* Select the Trigger source */
4415 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4416 htim->Instance->SMCR |= TIM_TS_TI2FP2;
4417
4418 /* Select the Slave Mode */
4419 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4420 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4421 break;
4422 }
4423
4424 default:
4425 status = HAL_ERROR;
4426 break;
4427 }
4428 }
4429
4430 htim->State = HAL_TIM_STATE_READY;
4431
4432 __HAL_UNLOCK(htim);
4433
4434 return status;
4435 }
4436 else
4437 {
4438 return HAL_ERROR;
4439 }
4440 }
4441
4442 /**
4443 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
4444 * @param htim TIM handle
4445 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4446 * This parameter can be one of the following values:
4447 * @arg TIM_DMABASE_CR1
4448 * @arg TIM_DMABASE_CR2
4449 * @arg TIM_DMABASE_SMCR
4450 * @arg TIM_DMABASE_DIER
4451 * @arg TIM_DMABASE_SR
4452 * @arg TIM_DMABASE_EGR
4453 * @arg TIM_DMABASE_CCMR1
4454 * @arg TIM_DMABASE_CCMR2
4455 * @arg TIM_DMABASE_CCER
4456 * @arg TIM_DMABASE_CNT
4457 * @arg TIM_DMABASE_PSC
4458 * @arg TIM_DMABASE_ARR
4459 * @arg TIM_DMABASE_RCR
4460 * @arg TIM_DMABASE_CCR1
4461 * @arg TIM_DMABASE_CCR2
4462 * @arg TIM_DMABASE_CCR3
4463 * @arg TIM_DMABASE_CCR4
4464 * @arg TIM_DMABASE_BDTR
4465 * @param BurstRequestSrc TIM DMA Request sources
4466 * This parameter can be one of the following values:
4467 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4468 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4469 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4470 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4471 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4472 * @arg TIM_DMA_COM: TIM Commutation DMA source
4473 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4474 * @param BurstBuffer The Buffer address.
4475 * @param BurstLength DMA Burst length. This parameter can be one value
4476 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4477 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4478 * @retval HAL status
4479 */
HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,const uint32_t * BurstBuffer,uint32_t BurstLength)4480 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4481 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
4482 uint32_t BurstLength)
4483 {
4484 HAL_StatusTypeDef status;
4485
4486 status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4487 ((BurstLength) >> 8U) + 1U);
4488
4489
4490
4491 return status;
4492 }
4493
4494 /**
4495 * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
4496 * @param htim TIM handle
4497 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4498 * This parameter can be one of the following values:
4499 * @arg TIM_DMABASE_CR1
4500 * @arg TIM_DMABASE_CR2
4501 * @arg TIM_DMABASE_SMCR
4502 * @arg TIM_DMABASE_DIER
4503 * @arg TIM_DMABASE_SR
4504 * @arg TIM_DMABASE_EGR
4505 * @arg TIM_DMABASE_CCMR1
4506 * @arg TIM_DMABASE_CCMR2
4507 * @arg TIM_DMABASE_CCER
4508 * @arg TIM_DMABASE_CNT
4509 * @arg TIM_DMABASE_PSC
4510 * @arg TIM_DMABASE_ARR
4511 * @arg TIM_DMABASE_RCR
4512 * @arg TIM_DMABASE_CCR1
4513 * @arg TIM_DMABASE_CCR2
4514 * @arg TIM_DMABASE_CCR3
4515 * @arg TIM_DMABASE_CCR4
4516 * @arg TIM_DMABASE_BDTR
4517 * @param BurstRequestSrc TIM DMA Request sources
4518 * This parameter can be one of the following values:
4519 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4520 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4521 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4522 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4523 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4524 * @arg TIM_DMA_COM: TIM Commutation DMA source
4525 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4526 * @param BurstBuffer The Buffer address.
4527 * @param BurstLength DMA Burst length. This parameter can be one value
4528 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4529 * @param DataLength Data length. This parameter can be one value
4530 * between 1 and 0xFFFF.
4531 * @retval HAL status
4532 */
HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,const uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4533 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4534 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
4535 uint32_t BurstLength, uint32_t DataLength)
4536 {
4537 HAL_StatusTypeDef status = HAL_OK;
4538
4539 /* Check the parameters */
4540 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4541 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4542 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4543 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4544 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4545
4546 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4547 {
4548 return HAL_BUSY;
4549 }
4550 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4551 {
4552 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4553 {
4554 return HAL_ERROR;
4555 }
4556 else
4557 {
4558 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4559 }
4560 }
4561 else
4562 {
4563 /* nothing to do */
4564 }
4565
4566 switch (BurstRequestSrc)
4567 {
4568 case TIM_DMA_UPDATE:
4569 {
4570 /* Set the DMA Period elapsed callbacks */
4571 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4572 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4573
4574 /* Set the DMA error callback */
4575 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4576
4577 /* Enable the DMA channel */
4578 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
4579 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4580 {
4581 /* Return error status */
4582 return HAL_ERROR;
4583 }
4584 break;
4585 }
4586 case TIM_DMA_CC1:
4587 {
4588 /* Set the DMA compare callbacks */
4589 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
4590 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4591
4592 /* Set the DMA error callback */
4593 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4594
4595 /* Enable the DMA channel */
4596 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
4597 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4598 {
4599 /* Return error status */
4600 return HAL_ERROR;
4601 }
4602 break;
4603 }
4604 case TIM_DMA_CC2:
4605 {
4606 /* Set the DMA compare callbacks */
4607 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
4608 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4609
4610 /* Set the DMA error callback */
4611 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4612
4613 /* Enable the DMA channel */
4614 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
4615 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4616 {
4617 /* Return error status */
4618 return HAL_ERROR;
4619 }
4620 break;
4621 }
4622 case TIM_DMA_CC3:
4623 {
4624 /* Set the DMA compare callbacks */
4625 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
4626 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4627
4628 /* Set the DMA error callback */
4629 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4630
4631 /* Enable the DMA channel */
4632 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
4633 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4634 {
4635 /* Return error status */
4636 return HAL_ERROR;
4637 }
4638 break;
4639 }
4640 case TIM_DMA_CC4:
4641 {
4642 /* Set the DMA compare callbacks */
4643 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
4644 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4645
4646 /* Set the DMA error callback */
4647 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4648
4649 /* Enable the DMA channel */
4650 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
4651 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4652 {
4653 /* Return error status */
4654 return HAL_ERROR;
4655 }
4656 break;
4657 }
4658 case TIM_DMA_COM:
4659 {
4660 /* Set the DMA commutation callbacks */
4661 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4662 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
4663
4664 /* Set the DMA error callback */
4665 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4666
4667 /* Enable the DMA channel */
4668 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
4669 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4670 {
4671 /* Return error status */
4672 return HAL_ERROR;
4673 }
4674 break;
4675 }
4676 case TIM_DMA_TRIGGER:
4677 {
4678 /* Set the DMA trigger callbacks */
4679 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4680 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4681
4682 /* Set the DMA error callback */
4683 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4684
4685 /* Enable the DMA channel */
4686 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
4687 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4688 {
4689 /* Return error status */
4690 return HAL_ERROR;
4691 }
4692 break;
4693 }
4694 default:
4695 status = HAL_ERROR;
4696 break;
4697 }
4698
4699 if (status == HAL_OK)
4700 {
4701 /* Configure the DMA Burst Mode */
4702 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4703 /* Enable the TIM DMA Request */
4704 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4705 }
4706
4707 /* Return function status */
4708 return status;
4709 }
4710
4711 /**
4712 * @brief Stops the TIM DMA Burst mode
4713 * @param htim TIM handle
4714 * @param BurstRequestSrc TIM DMA Request sources to disable
4715 * @retval HAL status
4716 */
HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4717 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4718 {
4719 HAL_StatusTypeDef status = HAL_OK;
4720
4721 /* Check the parameters */
4722 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4723
4724 /* Abort the DMA transfer (at least disable the DMA channel) */
4725 switch (BurstRequestSrc)
4726 {
4727 case TIM_DMA_UPDATE:
4728 {
4729 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4730 break;
4731 }
4732 case TIM_DMA_CC1:
4733 {
4734 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4735 break;
4736 }
4737 case TIM_DMA_CC2:
4738 {
4739 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
4740 break;
4741 }
4742 case TIM_DMA_CC3:
4743 {
4744 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
4745 break;
4746 }
4747 case TIM_DMA_CC4:
4748 {
4749 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
4750 break;
4751 }
4752 case TIM_DMA_COM:
4753 {
4754 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
4755 break;
4756 }
4757 case TIM_DMA_TRIGGER:
4758 {
4759 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
4760 break;
4761 }
4762 default:
4763 status = HAL_ERROR;
4764 break;
4765 }
4766
4767 if (status == HAL_OK)
4768 {
4769 /* Disable the TIM Update DMA request */
4770 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4771
4772 /* Change the DMA burst operation state */
4773 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
4774 }
4775
4776 /* Return function status */
4777 return status;
4778 }
4779
4780 /**
4781 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4782 * @param htim TIM handle
4783 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4784 * This parameter can be one of the following values:
4785 * @arg TIM_DMABASE_CR1
4786 * @arg TIM_DMABASE_CR2
4787 * @arg TIM_DMABASE_SMCR
4788 * @arg TIM_DMABASE_DIER
4789 * @arg TIM_DMABASE_SR
4790 * @arg TIM_DMABASE_EGR
4791 * @arg TIM_DMABASE_CCMR1
4792 * @arg TIM_DMABASE_CCMR2
4793 * @arg TIM_DMABASE_CCER
4794 * @arg TIM_DMABASE_CNT
4795 * @arg TIM_DMABASE_PSC
4796 * @arg TIM_DMABASE_ARR
4797 * @arg TIM_DMABASE_RCR
4798 * @arg TIM_DMABASE_CCR1
4799 * @arg TIM_DMABASE_CCR2
4800 * @arg TIM_DMABASE_CCR3
4801 * @arg TIM_DMABASE_CCR4
4802 * @arg TIM_DMABASE_BDTR
4803 * @param BurstRequestSrc TIM DMA Request sources
4804 * This parameter can be one of the following values:
4805 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4806 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4807 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4808 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4809 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4810 * @arg TIM_DMA_COM: TIM Commutation DMA source
4811 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4812 * @param BurstBuffer The Buffer address.
4813 * @param BurstLength DMA Burst length. This parameter can be one value
4814 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4815 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4816 * @retval HAL status
4817 */
HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)4818 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4819 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
4820 {
4821 HAL_StatusTypeDef status;
4822
4823 status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4824 ((BurstLength) >> 8U) + 1U);
4825
4826
4827 return status;
4828 }
4829
4830 /**
4831 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4832 * @param htim TIM handle
4833 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4834 * This parameter can be one of the following values:
4835 * @arg TIM_DMABASE_CR1
4836 * @arg TIM_DMABASE_CR2
4837 * @arg TIM_DMABASE_SMCR
4838 * @arg TIM_DMABASE_DIER
4839 * @arg TIM_DMABASE_SR
4840 * @arg TIM_DMABASE_EGR
4841 * @arg TIM_DMABASE_CCMR1
4842 * @arg TIM_DMABASE_CCMR2
4843 * @arg TIM_DMABASE_CCER
4844 * @arg TIM_DMABASE_CNT
4845 * @arg TIM_DMABASE_PSC
4846 * @arg TIM_DMABASE_ARR
4847 * @arg TIM_DMABASE_RCR
4848 * @arg TIM_DMABASE_CCR1
4849 * @arg TIM_DMABASE_CCR2
4850 * @arg TIM_DMABASE_CCR3
4851 * @arg TIM_DMABASE_CCR4
4852 * @arg TIM_DMABASE_BDTR
4853 * @param BurstRequestSrc TIM DMA Request sources
4854 * This parameter can be one of the following values:
4855 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4856 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4857 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4858 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4859 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4860 * @arg TIM_DMA_COM: TIM Commutation DMA source
4861 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4862 * @param BurstBuffer The Buffer address.
4863 * @param BurstLength DMA Burst length. This parameter can be one value
4864 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4865 * @param DataLength Data length. This parameter can be one value
4866 * between 1 and 0xFFFF.
4867 * @retval HAL status
4868 */
HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4869 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4870 uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
4871 uint32_t BurstLength, uint32_t DataLength)
4872 {
4873 HAL_StatusTypeDef status = HAL_OK;
4874
4875 /* Check the parameters */
4876 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4877 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4878 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4879 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4880 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4881
4882 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4883 {
4884 return HAL_BUSY;
4885 }
4886 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4887 {
4888 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4889 {
4890 return HAL_ERROR;
4891 }
4892 else
4893 {
4894 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4895 }
4896 }
4897 else
4898 {
4899 /* nothing to do */
4900 }
4901 switch (BurstRequestSrc)
4902 {
4903 case TIM_DMA_UPDATE:
4904 {
4905 /* Set the DMA Period elapsed callbacks */
4906 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4907 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4908
4909 /* Set the DMA error callback */
4910 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4911
4912 /* Enable the DMA channel */
4913 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4914 DataLength) != HAL_OK)
4915 {
4916 /* Return error status */
4917 return HAL_ERROR;
4918 }
4919 break;
4920 }
4921 case TIM_DMA_CC1:
4922 {
4923 /* Set the DMA capture callbacks */
4924 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
4925 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4926
4927 /* Set the DMA error callback */
4928 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4929
4930 /* Enable the DMA channel */
4931 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4932 DataLength) != HAL_OK)
4933 {
4934 /* Return error status */
4935 return HAL_ERROR;
4936 }
4937 break;
4938 }
4939 case TIM_DMA_CC2:
4940 {
4941 /* Set the DMA capture callbacks */
4942 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
4943 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4944
4945 /* Set the DMA error callback */
4946 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4947
4948 /* Enable the DMA channel */
4949 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4950 DataLength) != HAL_OK)
4951 {
4952 /* Return error status */
4953 return HAL_ERROR;
4954 }
4955 break;
4956 }
4957 case TIM_DMA_CC3:
4958 {
4959 /* Set the DMA capture callbacks */
4960 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
4961 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4962
4963 /* Set the DMA error callback */
4964 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4965
4966 /* Enable the DMA channel */
4967 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4968 DataLength) != HAL_OK)
4969 {
4970 /* Return error status */
4971 return HAL_ERROR;
4972 }
4973 break;
4974 }
4975 case TIM_DMA_CC4:
4976 {
4977 /* Set the DMA capture callbacks */
4978 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
4979 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4980
4981 /* Set the DMA error callback */
4982 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4983
4984 /* Enable the DMA channel */
4985 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4986 DataLength) != HAL_OK)
4987 {
4988 /* Return error status */
4989 return HAL_ERROR;
4990 }
4991 break;
4992 }
4993 case TIM_DMA_COM:
4994 {
4995 /* Set the DMA commutation callbacks */
4996 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4997 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
4998
4999 /* Set the DMA error callback */
5000 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
5001
5002 /* Enable the DMA channel */
5003 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5004 DataLength) != HAL_OK)
5005 {
5006 /* Return error status */
5007 return HAL_ERROR;
5008 }
5009 break;
5010 }
5011 case TIM_DMA_TRIGGER:
5012 {
5013 /* Set the DMA trigger callbacks */
5014 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
5015 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
5016
5017 /* Set the DMA error callback */
5018 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
5019
5020 /* Enable the DMA channel */
5021 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5022 DataLength) != HAL_OK)
5023 {
5024 /* Return error status */
5025 return HAL_ERROR;
5026 }
5027 break;
5028 }
5029 default:
5030 status = HAL_ERROR;
5031 break;
5032 }
5033
5034 if (status == HAL_OK)
5035 {
5036 /* Configure the DMA Burst Mode */
5037 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
5038
5039 /* Enable the TIM DMA Request */
5040 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
5041 }
5042
5043 /* Return function status */
5044 return status;
5045 }
5046
5047 /**
5048 * @brief Stop the DMA burst reading
5049 * @param htim TIM handle
5050 * @param BurstRequestSrc TIM DMA Request sources to disable.
5051 * @retval HAL status
5052 */
HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)5053 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
5054 {
5055 HAL_StatusTypeDef status = HAL_OK;
5056
5057 /* Check the parameters */
5058 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
5059
5060 /* Abort the DMA transfer (at least disable the DMA channel) */
5061 switch (BurstRequestSrc)
5062 {
5063 case TIM_DMA_UPDATE:
5064 {
5065 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
5066 break;
5067 }
5068 case TIM_DMA_CC1:
5069 {
5070 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
5071 break;
5072 }
5073 case TIM_DMA_CC2:
5074 {
5075 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
5076 break;
5077 }
5078 case TIM_DMA_CC3:
5079 {
5080 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
5081 break;
5082 }
5083 case TIM_DMA_CC4:
5084 {
5085 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
5086 break;
5087 }
5088 case TIM_DMA_COM:
5089 {
5090 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
5091 break;
5092 }
5093 case TIM_DMA_TRIGGER:
5094 {
5095 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
5096 break;
5097 }
5098 default:
5099 status = HAL_ERROR;
5100 break;
5101 }
5102
5103 if (status == HAL_OK)
5104 {
5105 /* Disable the TIM Update DMA request */
5106 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
5107
5108 /* Change the DMA burst operation state */
5109 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
5110 }
5111
5112 /* Return function status */
5113 return status;
5114 }
5115
5116 /**
5117 * @brief Generate a software event
5118 * @param htim TIM handle
5119 * @param EventSource specifies the event source.
5120 * This parameter can be one of the following values:
5121 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
5122 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
5123 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
5124 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
5125 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
5126 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
5127 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
5128 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
5129 * @note Basic timers can only generate an update event.
5130 * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
5131 * @note TIM_EVENTSOURCE_BREAK are relevant only for timer instances
5132 * supporting a break input.
5133 * @retval HAL status
5134 */
5135
HAL_TIM_GenerateEvent(TIM_HandleTypeDef * htim,uint32_t EventSource)5136 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
5137 {
5138 /* Check the parameters */
5139 assert_param(IS_TIM_INSTANCE(htim->Instance));
5140 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
5141
5142 /* Process Locked */
5143 __HAL_LOCK(htim);
5144
5145 /* Change the TIM state */
5146 htim->State = HAL_TIM_STATE_BUSY;
5147
5148 /* Set the event sources */
5149 htim->Instance->EGR = EventSource;
5150
5151 /* Change the TIM state */
5152 htim->State = HAL_TIM_STATE_READY;
5153
5154 __HAL_UNLOCK(htim);
5155
5156 /* Return function status */
5157 return HAL_OK;
5158 }
5159
5160 /**
5161 * @brief Configures the OCRef clear feature
5162 * @param htim TIM handle
5163 * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
5164 * contains the OCREF clear feature and parameters for the TIM peripheral.
5165 * @param Channel specifies the TIM Channel
5166 * This parameter can be one of the following values:
5167 * @arg TIM_CHANNEL_1: TIM Channel 1
5168 * @arg TIM_CHANNEL_2: TIM Channel 2
5169 * @arg TIM_CHANNEL_3: TIM Channel 3
5170 * @arg TIM_CHANNEL_4: TIM Channel 4
5171 * @retval HAL status
5172 */
HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef * htim,const TIM_ClearInputConfigTypeDef * sClearInputConfig,uint32_t Channel)5173 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
5174 const TIM_ClearInputConfigTypeDef *sClearInputConfig,
5175 uint32_t Channel)
5176 {
5177 HAL_StatusTypeDef status = HAL_OK;
5178
5179 /* Check the parameters */
5180 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
5181 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
5182
5183 /* Process Locked */
5184 __HAL_LOCK(htim);
5185
5186 htim->State = HAL_TIM_STATE_BUSY;
5187
5188 switch (sClearInputConfig->ClearInputSource)
5189 {
5190 case TIM_CLEARINPUTSOURCE_NONE:
5191 {
5192 /* Clear the OCREF clear selection bit and the the ETR Bits */
5193 CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
5194 break;
5195 }
5196
5197 case TIM_CLEARINPUTSOURCE_ETR:
5198 {
5199 /* Check the parameters */
5200 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
5201 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
5202 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
5203
5204 /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
5205 if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
5206 {
5207 htim->State = HAL_TIM_STATE_READY;
5208 __HAL_UNLOCK(htim);
5209 return HAL_ERROR;
5210 }
5211
5212 TIM_ETR_SetConfig(htim->Instance,
5213 sClearInputConfig->ClearInputPrescaler,
5214 sClearInputConfig->ClearInputPolarity,
5215 sClearInputConfig->ClearInputFilter);
5216 break;
5217 }
5218
5219 default:
5220 status = HAL_ERROR;
5221 break;
5222 }
5223
5224 if (status == HAL_OK)
5225 {
5226 switch (Channel)
5227 {
5228 case TIM_CHANNEL_1:
5229 {
5230 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5231 {
5232 /* Enable the OCREF clear feature for Channel 1 */
5233 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5234 }
5235 else
5236 {
5237 /* Disable the OCREF clear feature for Channel 1 */
5238 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5239 }
5240 break;
5241 }
5242 case TIM_CHANNEL_2:
5243 {
5244 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5245 {
5246 /* Enable the OCREF clear feature for Channel 2 */
5247 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5248 }
5249 else
5250 {
5251 /* Disable the OCREF clear feature for Channel 2 */
5252 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5253 }
5254 break;
5255 }
5256 case TIM_CHANNEL_3:
5257 {
5258 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5259 {
5260 /* Enable the OCREF clear feature for Channel 3 */
5261 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5262 }
5263 else
5264 {
5265 /* Disable the OCREF clear feature for Channel 3 */
5266 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5267 }
5268 break;
5269 }
5270 case TIM_CHANNEL_4:
5271 {
5272 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5273 {
5274 /* Enable the OCREF clear feature for Channel 4 */
5275 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5276 }
5277 else
5278 {
5279 /* Disable the OCREF clear feature for Channel 4 */
5280 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5281 }
5282 break;
5283 }
5284 default:
5285 break;
5286 }
5287 }
5288
5289 htim->State = HAL_TIM_STATE_READY;
5290
5291 __HAL_UNLOCK(htim);
5292
5293 return status;
5294 }
5295
5296 /**
5297 * @brief Configures the clock source to be used
5298 * @param htim TIM handle
5299 * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
5300 * contains the clock source information for the TIM peripheral.
5301 * @retval HAL status
5302 */
HAL_TIM_ConfigClockSource(TIM_HandleTypeDef * htim,const TIM_ClockConfigTypeDef * sClockSourceConfig)5303 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
5304 {
5305 HAL_StatusTypeDef status = HAL_OK;
5306 uint32_t tmpsmcr;
5307
5308 /* Process Locked */
5309 __HAL_LOCK(htim);
5310
5311 htim->State = HAL_TIM_STATE_BUSY;
5312
5313 /* Check the parameters */
5314 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
5315
5316 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
5317 tmpsmcr = htim->Instance->SMCR;
5318 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
5319 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
5320 htim->Instance->SMCR = tmpsmcr;
5321
5322 switch (sClockSourceConfig->ClockSource)
5323 {
5324 case TIM_CLOCKSOURCE_INTERNAL:
5325 {
5326 assert_param(IS_TIM_INSTANCE(htim->Instance));
5327 break;
5328 }
5329
5330 case TIM_CLOCKSOURCE_ETRMODE1:
5331 {
5332 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
5333 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
5334
5335 /* Check ETR input conditioning related parameters */
5336 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5337 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5338 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5339
5340 /* Configure the ETR Clock source */
5341 TIM_ETR_SetConfig(htim->Instance,
5342 sClockSourceConfig->ClockPrescaler,
5343 sClockSourceConfig->ClockPolarity,
5344 sClockSourceConfig->ClockFilter);
5345
5346 /* Select the External clock mode1 and the ETRF trigger */
5347 tmpsmcr = htim->Instance->SMCR;
5348 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
5349 /* Write to TIMx SMCR */
5350 htim->Instance->SMCR = tmpsmcr;
5351 break;
5352 }
5353
5354 case TIM_CLOCKSOURCE_ETRMODE2:
5355 {
5356 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
5357 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
5358
5359 /* Check ETR input conditioning related parameters */
5360 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5361 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5362 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5363
5364 /* Configure the ETR Clock source */
5365 TIM_ETR_SetConfig(htim->Instance,
5366 sClockSourceConfig->ClockPrescaler,
5367 sClockSourceConfig->ClockPolarity,
5368 sClockSourceConfig->ClockFilter);
5369 /* Enable the External clock mode2 */
5370 htim->Instance->SMCR |= TIM_SMCR_ECE;
5371 break;
5372 }
5373
5374 case TIM_CLOCKSOURCE_TI1:
5375 {
5376 /* Check whether or not the timer instance supports external clock mode 1 */
5377 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5378
5379 /* Check TI1 input conditioning related parameters */
5380 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5381 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5382
5383 TIM_TI1_ConfigInputStage(htim->Instance,
5384 sClockSourceConfig->ClockPolarity,
5385 sClockSourceConfig->ClockFilter);
5386 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
5387 break;
5388 }
5389
5390 case TIM_CLOCKSOURCE_TI2:
5391 {
5392 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
5393 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5394
5395 /* Check TI2 input conditioning related parameters */
5396 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5397 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5398
5399 TIM_TI2_ConfigInputStage(htim->Instance,
5400 sClockSourceConfig->ClockPolarity,
5401 sClockSourceConfig->ClockFilter);
5402 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
5403 break;
5404 }
5405
5406 case TIM_CLOCKSOURCE_TI1ED:
5407 {
5408 /* Check whether or not the timer instance supports external clock mode 1 */
5409 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5410
5411 /* Check TI1 input conditioning related parameters */
5412 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5413 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5414
5415 TIM_TI1_ConfigInputStage(htim->Instance,
5416 sClockSourceConfig->ClockPolarity,
5417 sClockSourceConfig->ClockFilter);
5418 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
5419 break;
5420 }
5421
5422 case TIM_CLOCKSOURCE_ITR0:
5423 case TIM_CLOCKSOURCE_ITR1:
5424 case TIM_CLOCKSOURCE_ITR2:
5425 case TIM_CLOCKSOURCE_ITR3:
5426 {
5427 /* Check whether or not the timer instance supports internal trigger input */
5428 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
5429
5430 TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
5431 break;
5432 }
5433
5434 default:
5435 status = HAL_ERROR;
5436 break;
5437 }
5438 htim->State = HAL_TIM_STATE_READY;
5439
5440 __HAL_UNLOCK(htim);
5441
5442 return status;
5443 }
5444
5445 /**
5446 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
5447 * or a XOR combination between CH1_input, CH2_input & CH3_input
5448 * @param htim TIM handle.
5449 * @param TI1_Selection Indicate whether or not channel 1 is connected to the
5450 * output of a XOR gate.
5451 * This parameter can be one of the following values:
5452 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
5453 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
5454 * pins are connected to the TI1 input (XOR combination)
5455 * @retval HAL status
5456 */
HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef * htim,uint32_t TI1_Selection)5457 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
5458 {
5459 uint32_t tmpcr2;
5460
5461 /* Check the parameters */
5462 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
5463 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
5464
5465 /* Get the TIMx CR2 register value */
5466 tmpcr2 = htim->Instance->CR2;
5467
5468 /* Reset the TI1 selection */
5469 tmpcr2 &= ~TIM_CR2_TI1S;
5470
5471 /* Set the TI1 selection */
5472 tmpcr2 |= TI1_Selection;
5473
5474 /* Write to TIMxCR2 */
5475 htim->Instance->CR2 = tmpcr2;
5476
5477 return HAL_OK;
5478 }
5479
5480 /**
5481 * @brief Configures the TIM in Slave mode
5482 * @param htim TIM handle.
5483 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5484 * contains the selected trigger (internal trigger input, filtered
5485 * timer input or external trigger input) and the Slave mode
5486 * (Disable, Reset, Gated, Trigger, External clock mode 1).
5487 * @retval HAL status
5488 */
HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)5489 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
5490 {
5491 /* Check the parameters */
5492 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5493 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5494 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
5495
5496 __HAL_LOCK(htim);
5497
5498 htim->State = HAL_TIM_STATE_BUSY;
5499
5500 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5501 {
5502 htim->State = HAL_TIM_STATE_READY;
5503 __HAL_UNLOCK(htim);
5504 return HAL_ERROR;
5505 }
5506
5507 /* Disable Trigger Interrupt */
5508 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
5509
5510 /* Disable Trigger DMA request */
5511 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5512
5513 htim->State = HAL_TIM_STATE_READY;
5514
5515 __HAL_UNLOCK(htim);
5516
5517 return HAL_OK;
5518 }
5519
5520 /**
5521 * @brief Configures the TIM in Slave mode in interrupt mode
5522 * @param htim TIM handle.
5523 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5524 * contains the selected trigger (internal trigger input, filtered
5525 * timer input or external trigger input) and the Slave mode
5526 * (Disable, Reset, Gated, Trigger, External clock mode 1).
5527 * @retval HAL status
5528 */
HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)5529 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
5530 const TIM_SlaveConfigTypeDef *sSlaveConfig)
5531 {
5532 /* Check the parameters */
5533 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5534 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5535 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
5536
5537 __HAL_LOCK(htim);
5538
5539 htim->State = HAL_TIM_STATE_BUSY;
5540
5541 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5542 {
5543 htim->State = HAL_TIM_STATE_READY;
5544 __HAL_UNLOCK(htim);
5545 return HAL_ERROR;
5546 }
5547
5548 /* Enable Trigger Interrupt */
5549 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
5550
5551 /* Disable Trigger DMA request */
5552 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5553
5554 htim->State = HAL_TIM_STATE_READY;
5555
5556 __HAL_UNLOCK(htim);
5557
5558 return HAL_OK;
5559 }
5560
5561 /**
5562 * @brief Read the captured value from Capture Compare unit
5563 * @param htim TIM handle.
5564 * @param Channel TIM Channels to be enabled
5565 * This parameter can be one of the following values:
5566 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
5567 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
5568 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
5569 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
5570 * @retval Captured value
5571 */
HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef * htim,uint32_t Channel)5572 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)
5573 {
5574 uint32_t tmpreg = 0U;
5575
5576 switch (Channel)
5577 {
5578 case TIM_CHANNEL_1:
5579 {
5580 /* Check the parameters */
5581 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
5582
5583 /* Return the capture 1 value */
5584 tmpreg = htim->Instance->CCR1;
5585
5586 break;
5587 }
5588 case TIM_CHANNEL_2:
5589 {
5590 /* Check the parameters */
5591 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
5592
5593 /* Return the capture 2 value */
5594 tmpreg = htim->Instance->CCR2;
5595
5596 break;
5597 }
5598
5599 case TIM_CHANNEL_3:
5600 {
5601 /* Check the parameters */
5602 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
5603
5604 /* Return the capture 3 value */
5605 tmpreg = htim->Instance->CCR3;
5606
5607 break;
5608 }
5609
5610 case TIM_CHANNEL_4:
5611 {
5612 /* Check the parameters */
5613 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
5614
5615 /* Return the capture 4 value */
5616 tmpreg = htim->Instance->CCR4;
5617
5618 break;
5619 }
5620
5621 default:
5622 break;
5623 }
5624
5625 return tmpreg;
5626 }
5627
5628 /**
5629 * @}
5630 */
5631
5632 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
5633 * @brief TIM Callbacks functions
5634 *
5635 @verbatim
5636 ==============================================================================
5637 ##### TIM Callbacks functions #####
5638 ==============================================================================
5639 [..]
5640 This section provides TIM callback functions:
5641 (+) TIM Period elapsed callback
5642 (+) TIM Output Compare callback
5643 (+) TIM Input capture callback
5644 (+) TIM Trigger callback
5645 (+) TIM Error callback
5646
5647 @endverbatim
5648 * @{
5649 */
5650
5651 /**
5652 * @brief Period elapsed callback in non-blocking mode
5653 * @param htim TIM handle
5654 * @retval None
5655 */
HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef * htim)5656 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
5657 {
5658 /* Prevent unused argument(s) compilation warning */
5659 UNUSED(htim);
5660
5661 /* NOTE : This function should not be modified, when the callback is needed,
5662 the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
5663 */
5664 }
5665
5666 /**
5667 * @brief Period elapsed half complete callback in non-blocking mode
5668 * @param htim TIM handle
5669 * @retval None
5670 */
HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef * htim)5671 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
5672 {
5673 /* Prevent unused argument(s) compilation warning */
5674 UNUSED(htim);
5675
5676 /* NOTE : This function should not be modified, when the callback is needed,
5677 the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
5678 */
5679 }
5680
5681 /**
5682 * @brief Output Compare callback in non-blocking mode
5683 * @param htim TIM OC handle
5684 * @retval None
5685 */
HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef * htim)5686 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
5687 {
5688 /* Prevent unused argument(s) compilation warning */
5689 UNUSED(htim);
5690
5691 /* NOTE : This function should not be modified, when the callback is needed,
5692 the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
5693 */
5694 }
5695
5696 /**
5697 * @brief Input Capture callback in non-blocking mode
5698 * @param htim TIM IC handle
5699 * @retval None
5700 */
HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef * htim)5701 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
5702 {
5703 /* Prevent unused argument(s) compilation warning */
5704 UNUSED(htim);
5705
5706 /* NOTE : This function should not be modified, when the callback is needed,
5707 the HAL_TIM_IC_CaptureCallback could be implemented in the user file
5708 */
5709 }
5710
5711 /**
5712 * @brief Input Capture half complete callback in non-blocking mode
5713 * @param htim TIM IC handle
5714 * @retval None
5715 */
HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef * htim)5716 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
5717 {
5718 /* Prevent unused argument(s) compilation warning */
5719 UNUSED(htim);
5720
5721 /* NOTE : This function should not be modified, when the callback is needed,
5722 the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
5723 */
5724 }
5725
5726 /**
5727 * @brief PWM Pulse finished callback in non-blocking mode
5728 * @param htim TIM handle
5729 * @retval None
5730 */
HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef * htim)5731 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
5732 {
5733 /* Prevent unused argument(s) compilation warning */
5734 UNUSED(htim);
5735
5736 /* NOTE : This function should not be modified, when the callback is needed,
5737 the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
5738 */
5739 }
5740
5741 /**
5742 * @brief PWM Pulse finished half complete callback in non-blocking mode
5743 * @param htim TIM handle
5744 * @retval None
5745 */
HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef * htim)5746 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
5747 {
5748 /* Prevent unused argument(s) compilation warning */
5749 UNUSED(htim);
5750
5751 /* NOTE : This function should not be modified, when the callback is needed,
5752 the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
5753 */
5754 }
5755
5756 /**
5757 * @brief Hall Trigger detection callback in non-blocking mode
5758 * @param htim TIM handle
5759 * @retval None
5760 */
HAL_TIM_TriggerCallback(TIM_HandleTypeDef * htim)5761 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
5762 {
5763 /* Prevent unused argument(s) compilation warning */
5764 UNUSED(htim);
5765
5766 /* NOTE : This function should not be modified, when the callback is needed,
5767 the HAL_TIM_TriggerCallback could be implemented in the user file
5768 */
5769 }
5770
5771 /**
5772 * @brief Hall Trigger detection half complete callback in non-blocking mode
5773 * @param htim TIM handle
5774 * @retval None
5775 */
HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef * htim)5776 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
5777 {
5778 /* Prevent unused argument(s) compilation warning */
5779 UNUSED(htim);
5780
5781 /* NOTE : This function should not be modified, when the callback is needed,
5782 the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
5783 */
5784 }
5785
5786 /**
5787 * @brief Timer error callback in non-blocking mode
5788 * @param htim TIM handle
5789 * @retval None
5790 */
HAL_TIM_ErrorCallback(TIM_HandleTypeDef * htim)5791 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
5792 {
5793 /* Prevent unused argument(s) compilation warning */
5794 UNUSED(htim);
5795
5796 /* NOTE : This function should not be modified, when the callback is needed,
5797 the HAL_TIM_ErrorCallback could be implemented in the user file
5798 */
5799 }
5800
5801 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5802 /**
5803 * @brief Register a User TIM callback to be used instead of the weak predefined callback
5804 * @param htim tim handle
5805 * @param CallbackID ID of the callback to be registered
5806 * This parameter can be one of the following values:
5807 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
5808 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
5809 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
5810 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
5811 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
5812 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
5813 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
5814 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
5815 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
5816 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
5817 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
5818 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
5819 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
5820 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
5821 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
5822 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
5823 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
5824 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
5825 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
5826 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
5827 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
5828 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
5829 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
5830 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
5831 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
5832 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
5833 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
5834 * @param pCallback pointer to the callback function
5835 * @retval status
5836 */
HAL_TIM_RegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID,pTIM_CallbackTypeDef pCallback)5837 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
5838 pTIM_CallbackTypeDef pCallback)
5839 {
5840 HAL_StatusTypeDef status = HAL_OK;
5841
5842 if (pCallback == NULL)
5843 {
5844 return HAL_ERROR;
5845 }
5846
5847 if (htim->State == HAL_TIM_STATE_READY)
5848 {
5849 switch (CallbackID)
5850 {
5851 case HAL_TIM_BASE_MSPINIT_CB_ID :
5852 htim->Base_MspInitCallback = pCallback;
5853 break;
5854
5855 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5856 htim->Base_MspDeInitCallback = pCallback;
5857 break;
5858
5859 case HAL_TIM_IC_MSPINIT_CB_ID :
5860 htim->IC_MspInitCallback = pCallback;
5861 break;
5862
5863 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5864 htim->IC_MspDeInitCallback = pCallback;
5865 break;
5866
5867 case HAL_TIM_OC_MSPINIT_CB_ID :
5868 htim->OC_MspInitCallback = pCallback;
5869 break;
5870
5871 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5872 htim->OC_MspDeInitCallback = pCallback;
5873 break;
5874
5875 case HAL_TIM_PWM_MSPINIT_CB_ID :
5876 htim->PWM_MspInitCallback = pCallback;
5877 break;
5878
5879 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5880 htim->PWM_MspDeInitCallback = pCallback;
5881 break;
5882
5883 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5884 htim->OnePulse_MspInitCallback = pCallback;
5885 break;
5886
5887 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5888 htim->OnePulse_MspDeInitCallback = pCallback;
5889 break;
5890
5891 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5892 htim->Encoder_MspInitCallback = pCallback;
5893 break;
5894
5895 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5896 htim->Encoder_MspDeInitCallback = pCallback;
5897 break;
5898
5899 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5900 htim->HallSensor_MspInitCallback = pCallback;
5901 break;
5902
5903 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5904 htim->HallSensor_MspDeInitCallback = pCallback;
5905 break;
5906
5907 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
5908 htim->PeriodElapsedCallback = pCallback;
5909 break;
5910
5911 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
5912 htim->PeriodElapsedHalfCpltCallback = pCallback;
5913 break;
5914
5915 case HAL_TIM_TRIGGER_CB_ID :
5916 htim->TriggerCallback = pCallback;
5917 break;
5918
5919 case HAL_TIM_TRIGGER_HALF_CB_ID :
5920 htim->TriggerHalfCpltCallback = pCallback;
5921 break;
5922
5923 case HAL_TIM_IC_CAPTURE_CB_ID :
5924 htim->IC_CaptureCallback = pCallback;
5925 break;
5926
5927 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
5928 htim->IC_CaptureHalfCpltCallback = pCallback;
5929 break;
5930
5931 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
5932 htim->OC_DelayElapsedCallback = pCallback;
5933 break;
5934
5935 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
5936 htim->PWM_PulseFinishedCallback = pCallback;
5937 break;
5938
5939 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
5940 htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
5941 break;
5942
5943 case HAL_TIM_ERROR_CB_ID :
5944 htim->ErrorCallback = pCallback;
5945 break;
5946
5947 case HAL_TIM_COMMUTATION_CB_ID :
5948 htim->CommutationCallback = pCallback;
5949 break;
5950
5951 case HAL_TIM_COMMUTATION_HALF_CB_ID :
5952 htim->CommutationHalfCpltCallback = pCallback;
5953 break;
5954
5955 case HAL_TIM_BREAK_CB_ID :
5956 htim->BreakCallback = pCallback;
5957 break;
5958
5959 default :
5960 /* Return error status */
5961 status = HAL_ERROR;
5962 break;
5963 }
5964 }
5965 else if (htim->State == HAL_TIM_STATE_RESET)
5966 {
5967 switch (CallbackID)
5968 {
5969 case HAL_TIM_BASE_MSPINIT_CB_ID :
5970 htim->Base_MspInitCallback = pCallback;
5971 break;
5972
5973 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5974 htim->Base_MspDeInitCallback = pCallback;
5975 break;
5976
5977 case HAL_TIM_IC_MSPINIT_CB_ID :
5978 htim->IC_MspInitCallback = pCallback;
5979 break;
5980
5981 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5982 htim->IC_MspDeInitCallback = pCallback;
5983 break;
5984
5985 case HAL_TIM_OC_MSPINIT_CB_ID :
5986 htim->OC_MspInitCallback = pCallback;
5987 break;
5988
5989 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5990 htim->OC_MspDeInitCallback = pCallback;
5991 break;
5992
5993 case HAL_TIM_PWM_MSPINIT_CB_ID :
5994 htim->PWM_MspInitCallback = pCallback;
5995 break;
5996
5997 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5998 htim->PWM_MspDeInitCallback = pCallback;
5999 break;
6000
6001 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6002 htim->OnePulse_MspInitCallback = pCallback;
6003 break;
6004
6005 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6006 htim->OnePulse_MspDeInitCallback = pCallback;
6007 break;
6008
6009 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6010 htim->Encoder_MspInitCallback = pCallback;
6011 break;
6012
6013 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6014 htim->Encoder_MspDeInitCallback = pCallback;
6015 break;
6016
6017 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6018 htim->HallSensor_MspInitCallback = pCallback;
6019 break;
6020
6021 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6022 htim->HallSensor_MspDeInitCallback = pCallback;
6023 break;
6024
6025 default :
6026 /* Return error status */
6027 status = HAL_ERROR;
6028 break;
6029 }
6030 }
6031 else
6032 {
6033 /* Return error status */
6034 status = HAL_ERROR;
6035 }
6036
6037 return status;
6038 }
6039
6040 /**
6041 * @brief Unregister a TIM callback
6042 * TIM callback is redirected to the weak predefined callback
6043 * @param htim tim handle
6044 * @param CallbackID ID of the callback to be unregistered
6045 * This parameter can be one of the following values:
6046 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
6047 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
6048 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
6049 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
6050 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
6051 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
6052 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
6053 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
6054 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
6055 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
6056 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
6057 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
6058 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
6059 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
6060 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
6061 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
6062 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
6063 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
6064 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
6065 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
6066 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
6067 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
6068 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
6069 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
6070 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
6071 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
6072 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
6073 * @retval status
6074 */
HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID)6075 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
6076 {
6077 HAL_StatusTypeDef status = HAL_OK;
6078
6079 if (htim->State == HAL_TIM_STATE_READY)
6080 {
6081 switch (CallbackID)
6082 {
6083 case HAL_TIM_BASE_MSPINIT_CB_ID :
6084 /* Legacy weak Base MspInit Callback */
6085 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
6086 break;
6087
6088 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6089 /* Legacy weak Base Msp DeInit Callback */
6090 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
6091 break;
6092
6093 case HAL_TIM_IC_MSPINIT_CB_ID :
6094 /* Legacy weak IC Msp Init Callback */
6095 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
6096 break;
6097
6098 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6099 /* Legacy weak IC Msp DeInit Callback */
6100 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
6101 break;
6102
6103 case HAL_TIM_OC_MSPINIT_CB_ID :
6104 /* Legacy weak OC Msp Init Callback */
6105 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
6106 break;
6107
6108 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6109 /* Legacy weak OC Msp DeInit Callback */
6110 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
6111 break;
6112
6113 case HAL_TIM_PWM_MSPINIT_CB_ID :
6114 /* Legacy weak PWM Msp Init Callback */
6115 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
6116 break;
6117
6118 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6119 /* Legacy weak PWM Msp DeInit Callback */
6120 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
6121 break;
6122
6123 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6124 /* Legacy weak One Pulse Msp Init Callback */
6125 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
6126 break;
6127
6128 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6129 /* Legacy weak One Pulse Msp DeInit Callback */
6130 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
6131 break;
6132
6133 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6134 /* Legacy weak Encoder Msp Init Callback */
6135 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
6136 break;
6137
6138 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6139 /* Legacy weak Encoder Msp DeInit Callback */
6140 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
6141 break;
6142
6143 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6144 /* Legacy weak Hall Sensor Msp Init Callback */
6145 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
6146 break;
6147
6148 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6149 /* Legacy weak Hall Sensor Msp DeInit Callback */
6150 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
6151 break;
6152
6153 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
6154 /* Legacy weak Period Elapsed Callback */
6155 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
6156 break;
6157
6158 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
6159 /* Legacy weak Period Elapsed half complete Callback */
6160 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
6161 break;
6162
6163 case HAL_TIM_TRIGGER_CB_ID :
6164 /* Legacy weak Trigger Callback */
6165 htim->TriggerCallback = HAL_TIM_TriggerCallback;
6166 break;
6167
6168 case HAL_TIM_TRIGGER_HALF_CB_ID :
6169 /* Legacy weak Trigger half complete Callback */
6170 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
6171 break;
6172
6173 case HAL_TIM_IC_CAPTURE_CB_ID :
6174 /* Legacy weak IC Capture Callback */
6175 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
6176 break;
6177
6178 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
6179 /* Legacy weak IC Capture half complete Callback */
6180 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
6181 break;
6182
6183 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
6184 /* Legacy weak OC Delay Elapsed Callback */
6185 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
6186 break;
6187
6188 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
6189 /* Legacy weak PWM Pulse Finished Callback */
6190 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
6191 break;
6192
6193 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
6194 /* Legacy weak PWM Pulse Finished half complete Callback */
6195 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
6196 break;
6197
6198 case HAL_TIM_ERROR_CB_ID :
6199 /* Legacy weak Error Callback */
6200 htim->ErrorCallback = HAL_TIM_ErrorCallback;
6201 break;
6202
6203 case HAL_TIM_COMMUTATION_CB_ID :
6204 /* Legacy weak Commutation Callback */
6205 htim->CommutationCallback = HAL_TIMEx_CommutCallback;
6206 break;
6207
6208 case HAL_TIM_COMMUTATION_HALF_CB_ID :
6209 /* Legacy weak Commutation half complete Callback */
6210 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
6211 break;
6212
6213 case HAL_TIM_BREAK_CB_ID :
6214 /* Legacy weak Break Callback */
6215 htim->BreakCallback = HAL_TIMEx_BreakCallback;
6216 break;
6217
6218 default :
6219 /* Return error status */
6220 status = HAL_ERROR;
6221 break;
6222 }
6223 }
6224 else if (htim->State == HAL_TIM_STATE_RESET)
6225 {
6226 switch (CallbackID)
6227 {
6228 case HAL_TIM_BASE_MSPINIT_CB_ID :
6229 /* Legacy weak Base MspInit Callback */
6230 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
6231 break;
6232
6233 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6234 /* Legacy weak Base Msp DeInit Callback */
6235 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
6236 break;
6237
6238 case HAL_TIM_IC_MSPINIT_CB_ID :
6239 /* Legacy weak IC Msp Init Callback */
6240 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
6241 break;
6242
6243 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6244 /* Legacy weak IC Msp DeInit Callback */
6245 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
6246 break;
6247
6248 case HAL_TIM_OC_MSPINIT_CB_ID :
6249 /* Legacy weak OC Msp Init Callback */
6250 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
6251 break;
6252
6253 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6254 /* Legacy weak OC Msp DeInit Callback */
6255 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
6256 break;
6257
6258 case HAL_TIM_PWM_MSPINIT_CB_ID :
6259 /* Legacy weak PWM Msp Init Callback */
6260 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
6261 break;
6262
6263 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6264 /* Legacy weak PWM Msp DeInit Callback */
6265 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
6266 break;
6267
6268 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6269 /* Legacy weak One Pulse Msp Init Callback */
6270 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
6271 break;
6272
6273 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6274 /* Legacy weak One Pulse Msp DeInit Callback */
6275 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
6276 break;
6277
6278 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6279 /* Legacy weak Encoder Msp Init Callback */
6280 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
6281 break;
6282
6283 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6284 /* Legacy weak Encoder Msp DeInit Callback */
6285 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
6286 break;
6287
6288 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6289 /* Legacy weak Hall Sensor Msp Init Callback */
6290 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
6291 break;
6292
6293 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6294 /* Legacy weak Hall Sensor Msp DeInit Callback */
6295 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
6296 break;
6297
6298 default :
6299 /* Return error status */
6300 status = HAL_ERROR;
6301 break;
6302 }
6303 }
6304 else
6305 {
6306 /* Return error status */
6307 status = HAL_ERROR;
6308 }
6309
6310 return status;
6311 }
6312 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6313
6314 /**
6315 * @}
6316 */
6317
6318 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
6319 * @brief TIM Peripheral State functions
6320 *
6321 @verbatim
6322 ==============================================================================
6323 ##### Peripheral State functions #####
6324 ==============================================================================
6325 [..]
6326 This subsection permits to get in run-time the status of the peripheral
6327 and the data flow.
6328
6329 @endverbatim
6330 * @{
6331 */
6332
6333 /**
6334 * @brief Return the TIM Base handle state.
6335 * @param htim TIM Base handle
6336 * @retval HAL state
6337 */
HAL_TIM_Base_GetState(const TIM_HandleTypeDef * htim)6338 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim)
6339 {
6340 return htim->State;
6341 }
6342
6343 /**
6344 * @brief Return the TIM OC handle state.
6345 * @param htim TIM Output Compare handle
6346 * @retval HAL state
6347 */
HAL_TIM_OC_GetState(const TIM_HandleTypeDef * htim)6348 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim)
6349 {
6350 return htim->State;
6351 }
6352
6353 /**
6354 * @brief Return the TIM PWM handle state.
6355 * @param htim TIM handle
6356 * @retval HAL state
6357 */
HAL_TIM_PWM_GetState(const TIM_HandleTypeDef * htim)6358 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim)
6359 {
6360 return htim->State;
6361 }
6362
6363 /**
6364 * @brief Return the TIM Input Capture handle state.
6365 * @param htim TIM IC handle
6366 * @retval HAL state
6367 */
HAL_TIM_IC_GetState(const TIM_HandleTypeDef * htim)6368 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim)
6369 {
6370 return htim->State;
6371 }
6372
6373 /**
6374 * @brief Return the TIM One Pulse Mode handle state.
6375 * @param htim TIM OPM handle
6376 * @retval HAL state
6377 */
HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef * htim)6378 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim)
6379 {
6380 return htim->State;
6381 }
6382
6383 /**
6384 * @brief Return the TIM Encoder Mode handle state.
6385 * @param htim TIM Encoder Interface handle
6386 * @retval HAL state
6387 */
HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef * htim)6388 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim)
6389 {
6390 return htim->State;
6391 }
6392
6393 /**
6394 * @brief Return the TIM Encoder Mode handle state.
6395 * @param htim TIM handle
6396 * @retval Active channel
6397 */
HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef * htim)6398 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim)
6399 {
6400 return htim->Channel;
6401 }
6402
6403 /**
6404 * @brief Return actual state of the TIM channel.
6405 * @param htim TIM handle
6406 * @param Channel TIM Channel
6407 * This parameter can be one of the following values:
6408 * @arg TIM_CHANNEL_1: TIM Channel 1
6409 * @arg TIM_CHANNEL_2: TIM Channel 2
6410 * @arg TIM_CHANNEL_3: TIM Channel 3
6411 * @arg TIM_CHANNEL_4: TIM Channel 4
6412 * @arg TIM_CHANNEL_5: TIM Channel 5
6413 * @arg TIM_CHANNEL_6: TIM Channel 6
6414 * @retval TIM Channel state
6415 */
HAL_TIM_GetChannelState(const TIM_HandleTypeDef * htim,uint32_t Channel)6416 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel)
6417 {
6418 HAL_TIM_ChannelStateTypeDef channel_state;
6419
6420 /* Check the parameters */
6421 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
6422
6423 channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
6424
6425 return channel_state;
6426 }
6427
6428 /**
6429 * @brief Return actual state of a DMA burst operation.
6430 * @param htim TIM handle
6431 * @retval DMA burst state
6432 */
HAL_TIM_DMABurstState(const TIM_HandleTypeDef * htim)6433 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim)
6434 {
6435 /* Check the parameters */
6436 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
6437
6438 return htim->DMABurstState;
6439 }
6440
6441 /**
6442 * @}
6443 */
6444
6445 /**
6446 * @}
6447 */
6448
6449 /** @defgroup TIM_Private_Functions TIM Private Functions
6450 * @{
6451 */
6452
6453 /**
6454 * @brief TIM DMA error callback
6455 * @param hdma pointer to DMA handle.
6456 * @retval None
6457 */
TIM_DMAError(DMA_HandleTypeDef * hdma)6458 void TIM_DMAError(DMA_HandleTypeDef *hdma)
6459 {
6460 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6461
6462 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6463 {
6464 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6465 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6466 }
6467 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6468 {
6469 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6470 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6471 }
6472 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6473 {
6474 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6475 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6476 }
6477 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6478 {
6479 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6480 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6481 }
6482 else
6483 {
6484 htim->State = HAL_TIM_STATE_READY;
6485 }
6486
6487 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6488 htim->ErrorCallback(htim);
6489 #else
6490 HAL_TIM_ErrorCallback(htim);
6491 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6492
6493 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6494 }
6495
6496 /**
6497 * @brief TIM DMA Delay Pulse complete callback.
6498 * @param hdma pointer to DMA handle.
6499 * @retval None
6500 */
TIM_DMADelayPulseCplt(DMA_HandleTypeDef * hdma)6501 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
6502 {
6503 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6504
6505 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6506 {
6507 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6508
6509 if (hdma->Init.Mode == DMA_NORMAL)
6510 {
6511 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6512 }
6513 }
6514 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6515 {
6516 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6517
6518 if (hdma->Init.Mode == DMA_NORMAL)
6519 {
6520 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6521 }
6522 }
6523 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6524 {
6525 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6526
6527 if (hdma->Init.Mode == DMA_NORMAL)
6528 {
6529 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6530 }
6531 }
6532 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6533 {
6534 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6535
6536 if (hdma->Init.Mode == DMA_NORMAL)
6537 {
6538 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6539 }
6540 }
6541 else
6542 {
6543 /* nothing to do */
6544 }
6545
6546 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6547 htim->PWM_PulseFinishedCallback(htim);
6548 #else
6549 HAL_TIM_PWM_PulseFinishedCallback(htim);
6550 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6551
6552 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6553 }
6554
6555 /**
6556 * @brief TIM DMA Delay Pulse half complete callback.
6557 * @param hdma pointer to DMA handle.
6558 * @retval None
6559 */
TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef * hdma)6560 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
6561 {
6562 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6563
6564 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6565 {
6566 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6567 }
6568 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6569 {
6570 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6571 }
6572 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6573 {
6574 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6575 }
6576 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6577 {
6578 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6579 }
6580 else
6581 {
6582 /* nothing to do */
6583 }
6584
6585 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6586 htim->PWM_PulseFinishedHalfCpltCallback(htim);
6587 #else
6588 HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
6589 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6590
6591 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6592 }
6593
6594 /**
6595 * @brief TIM DMA Capture complete callback.
6596 * @param hdma pointer to DMA handle.
6597 * @retval None
6598 */
TIM_DMACaptureCplt(DMA_HandleTypeDef * hdma)6599 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
6600 {
6601 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6602
6603 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6604 {
6605 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6606
6607 if (hdma->Init.Mode == DMA_NORMAL)
6608 {
6609 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6610 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6611 }
6612 }
6613 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6614 {
6615 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6616
6617 if (hdma->Init.Mode == DMA_NORMAL)
6618 {
6619 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6620 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6621 }
6622 }
6623 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6624 {
6625 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6626
6627 if (hdma->Init.Mode == DMA_NORMAL)
6628 {
6629 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6630 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6631 }
6632 }
6633 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6634 {
6635 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6636
6637 if (hdma->Init.Mode == DMA_NORMAL)
6638 {
6639 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6640 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6641 }
6642 }
6643 else
6644 {
6645 /* nothing to do */
6646 }
6647
6648 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6649 htim->IC_CaptureCallback(htim);
6650 #else
6651 HAL_TIM_IC_CaptureCallback(htim);
6652 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6653
6654 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6655 }
6656
6657 /**
6658 * @brief TIM DMA Capture half complete callback.
6659 * @param hdma pointer to DMA handle.
6660 * @retval None
6661 */
TIM_DMACaptureHalfCplt(DMA_HandleTypeDef * hdma)6662 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
6663 {
6664 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6665
6666 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6667 {
6668 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6669 }
6670 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6671 {
6672 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6673 }
6674 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6675 {
6676 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6677 }
6678 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6679 {
6680 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6681 }
6682 else
6683 {
6684 /* nothing to do */
6685 }
6686
6687 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6688 htim->IC_CaptureHalfCpltCallback(htim);
6689 #else
6690 HAL_TIM_IC_CaptureHalfCpltCallback(htim);
6691 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6692
6693 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6694 }
6695
6696 /**
6697 * @brief TIM DMA Period Elapse complete callback.
6698 * @param hdma pointer to DMA handle.
6699 * @retval None
6700 */
TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef * hdma)6701 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
6702 {
6703 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6704
6705 if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
6706 {
6707 htim->State = HAL_TIM_STATE_READY;
6708 }
6709
6710 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6711 htim->PeriodElapsedCallback(htim);
6712 #else
6713 HAL_TIM_PeriodElapsedCallback(htim);
6714 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6715 }
6716
6717 /**
6718 * @brief TIM DMA Period Elapse half complete callback.
6719 * @param hdma pointer to DMA handle.
6720 * @retval None
6721 */
TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef * hdma)6722 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
6723 {
6724 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6725
6726 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6727 htim->PeriodElapsedHalfCpltCallback(htim);
6728 #else
6729 HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
6730 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6731 }
6732
6733 /**
6734 * @brief TIM DMA Trigger callback.
6735 * @param hdma pointer to DMA handle.
6736 * @retval None
6737 */
TIM_DMATriggerCplt(DMA_HandleTypeDef * hdma)6738 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
6739 {
6740 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6741
6742 if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
6743 {
6744 htim->State = HAL_TIM_STATE_READY;
6745 }
6746
6747 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6748 htim->TriggerCallback(htim);
6749 #else
6750 HAL_TIM_TriggerCallback(htim);
6751 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6752 }
6753
6754 /**
6755 * @brief TIM DMA Trigger half complete callback.
6756 * @param hdma pointer to DMA handle.
6757 * @retval None
6758 */
TIM_DMATriggerHalfCplt(DMA_HandleTypeDef * hdma)6759 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
6760 {
6761 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6762
6763 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6764 htim->TriggerHalfCpltCallback(htim);
6765 #else
6766 HAL_TIM_TriggerHalfCpltCallback(htim);
6767 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6768 }
6769
6770 /**
6771 * @brief Time Base configuration
6772 * @param TIMx TIM peripheral
6773 * @param Structure TIM Base configuration structure
6774 * @retval None
6775 */
TIM_Base_SetConfig(TIM_TypeDef * TIMx,const TIM_Base_InitTypeDef * Structure)6776 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
6777 {
6778 uint32_t tmpcr1;
6779 tmpcr1 = TIMx->CR1;
6780
6781 /* Set TIM Time Base Unit parameters ---------------------------------------*/
6782 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
6783 {
6784 /* Select the Counter Mode */
6785 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
6786 tmpcr1 |= Structure->CounterMode;
6787 }
6788
6789 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
6790 {
6791 /* Set the clock division */
6792 tmpcr1 &= ~TIM_CR1_CKD;
6793 tmpcr1 |= (uint32_t)Structure->ClockDivision;
6794 }
6795
6796 /* Set the auto-reload preload */
6797 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
6798
6799 TIMx->CR1 = tmpcr1;
6800
6801 /* Set the Autoreload value */
6802 TIMx->ARR = (uint32_t)Structure->Period ;
6803
6804 /* Set the Prescaler value */
6805 TIMx->PSC = Structure->Prescaler;
6806
6807 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
6808 {
6809 /* Set the Repetition Counter value */
6810 TIMx->RCR = Structure->RepetitionCounter;
6811 }
6812
6813 /* Generate an update event to reload the Prescaler
6814 and the repetition counter (only for advanced timer) value immediately */
6815 TIMx->EGR = TIM_EGR_UG;
6816
6817 /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
6818 if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
6819 {
6820 /* Clear the update flag */
6821 CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
6822 }
6823 }
6824
6825 /**
6826 * @brief Timer Output Compare 1 configuration
6827 * @param TIMx to select the TIM peripheral
6828 * @param OC_Config The output configuration structure
6829 * @retval None
6830 */
TIM_OC1_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)6831 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
6832 {
6833 uint32_t tmpccmrx;
6834 uint32_t tmpccer;
6835 uint32_t tmpcr2;
6836
6837 /* Get the TIMx CCER register value */
6838 tmpccer = TIMx->CCER;
6839
6840 /* Disable the Channel 1: Reset the CC1E Bit */
6841 TIMx->CCER &= ~TIM_CCER_CC1E;
6842
6843 /* Get the TIMx CR2 register value */
6844 tmpcr2 = TIMx->CR2;
6845
6846 /* Get the TIMx CCMR1 register value */
6847 tmpccmrx = TIMx->CCMR1;
6848
6849 /* Reset the Output Compare Mode Bits */
6850 tmpccmrx &= ~TIM_CCMR1_OC1M;
6851 tmpccmrx &= ~TIM_CCMR1_CC1S;
6852 /* Select the Output Compare Mode */
6853 tmpccmrx |= OC_Config->OCMode;
6854
6855 /* Reset the Output Polarity level */
6856 tmpccer &= ~TIM_CCER_CC1P;
6857 /* Set the Output Compare Polarity */
6858 tmpccer |= OC_Config->OCPolarity;
6859
6860 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
6861 {
6862 /* Check parameters */
6863 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
6864
6865 /* Reset the Output N Polarity level */
6866 tmpccer &= ~TIM_CCER_CC1NP;
6867 /* Set the Output N Polarity */
6868 tmpccer |= OC_Config->OCNPolarity;
6869 /* Reset the Output N State */
6870 tmpccer &= ~TIM_CCER_CC1NE;
6871 }
6872
6873 if (IS_TIM_BREAK_INSTANCE(TIMx))
6874 {
6875 /* Check parameters */
6876 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
6877 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6878
6879 /* Reset the Output Compare and Output Compare N IDLE State */
6880 tmpcr2 &= ~TIM_CR2_OIS1;
6881 tmpcr2 &= ~TIM_CR2_OIS1N;
6882 /* Set the Output Idle state */
6883 tmpcr2 |= OC_Config->OCIdleState;
6884 /* Set the Output N Idle state */
6885 tmpcr2 |= OC_Config->OCNIdleState;
6886 }
6887
6888 /* Write to TIMx CR2 */
6889 TIMx->CR2 = tmpcr2;
6890
6891 /* Write to TIMx CCMR1 */
6892 TIMx->CCMR1 = tmpccmrx;
6893
6894 /* Set the Capture Compare Register value */
6895 TIMx->CCR1 = OC_Config->Pulse;
6896
6897 /* Write to TIMx CCER */
6898 TIMx->CCER = tmpccer;
6899 }
6900
6901 /**
6902 * @brief Timer Output Compare 2 configuration
6903 * @param TIMx to select the TIM peripheral
6904 * @param OC_Config The output configuration structure
6905 * @retval None
6906 */
TIM_OC2_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)6907 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
6908 {
6909 uint32_t tmpccmrx;
6910 uint32_t tmpccer;
6911 uint32_t tmpcr2;
6912
6913 /* Get the TIMx CCER register value */
6914 tmpccer = TIMx->CCER;
6915
6916 /* Disable the Channel 2: Reset the CC2E Bit */
6917 TIMx->CCER &= ~TIM_CCER_CC2E;
6918
6919 /* Get the TIMx CR2 register value */
6920 tmpcr2 = TIMx->CR2;
6921
6922 /* Get the TIMx CCMR1 register value */
6923 tmpccmrx = TIMx->CCMR1;
6924
6925 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6926 tmpccmrx &= ~TIM_CCMR1_OC2M;
6927 tmpccmrx &= ~TIM_CCMR1_CC2S;
6928
6929 /* Select the Output Compare Mode */
6930 tmpccmrx |= (OC_Config->OCMode << 8U);
6931
6932 /* Reset the Output Polarity level */
6933 tmpccer &= ~TIM_CCER_CC2P;
6934 /* Set the Output Compare Polarity */
6935 tmpccer |= (OC_Config->OCPolarity << 4U);
6936
6937 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
6938 {
6939 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
6940
6941 /* Reset the Output N Polarity level */
6942 tmpccer &= ~TIM_CCER_CC2NP;
6943 /* Set the Output N Polarity */
6944 tmpccer |= (OC_Config->OCNPolarity << 4U);
6945 /* Reset the Output N State */
6946 tmpccer &= ~TIM_CCER_CC2NE;
6947 }
6948
6949 if (IS_TIM_BREAK_INSTANCE(TIMx))
6950 {
6951 /* Check parameters */
6952 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
6953 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6954
6955 /* Reset the Output Compare and Output Compare N IDLE State */
6956 tmpcr2 &= ~TIM_CR2_OIS2;
6957 tmpcr2 &= ~TIM_CR2_OIS2N;
6958 /* Set the Output Idle state */
6959 tmpcr2 |= (OC_Config->OCIdleState << 2U);
6960 /* Set the Output N Idle state */
6961 tmpcr2 |= (OC_Config->OCNIdleState << 2U);
6962 }
6963
6964 /* Write to TIMx CR2 */
6965 TIMx->CR2 = tmpcr2;
6966
6967 /* Write to TIMx CCMR1 */
6968 TIMx->CCMR1 = tmpccmrx;
6969
6970 /* Set the Capture Compare Register value */
6971 TIMx->CCR2 = OC_Config->Pulse;
6972
6973 /* Write to TIMx CCER */
6974 TIMx->CCER = tmpccer;
6975 }
6976
6977 /**
6978 * @brief Timer Output Compare 3 configuration
6979 * @param TIMx to select the TIM peripheral
6980 * @param OC_Config The output configuration structure
6981 * @retval None
6982 */
TIM_OC3_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)6983 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
6984 {
6985 uint32_t tmpccmrx;
6986 uint32_t tmpccer;
6987 uint32_t tmpcr2;
6988
6989 /* Get the TIMx CCER register value */
6990 tmpccer = TIMx->CCER;
6991
6992 /* Disable the Channel 3: Reset the CC2E Bit */
6993 TIMx->CCER &= ~TIM_CCER_CC3E;
6994
6995 /* Get the TIMx CR2 register value */
6996 tmpcr2 = TIMx->CR2;
6997
6998 /* Get the TIMx CCMR2 register value */
6999 tmpccmrx = TIMx->CCMR2;
7000
7001 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7002 tmpccmrx &= ~TIM_CCMR2_OC3M;
7003 tmpccmrx &= ~TIM_CCMR2_CC3S;
7004 /* Select the Output Compare Mode */
7005 tmpccmrx |= OC_Config->OCMode;
7006
7007 /* Reset the Output Polarity level */
7008 tmpccer &= ~TIM_CCER_CC3P;
7009 /* Set the Output Compare Polarity */
7010 tmpccer |= (OC_Config->OCPolarity << 8U);
7011
7012 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
7013 {
7014 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7015
7016 /* Reset the Output N Polarity level */
7017 tmpccer &= ~TIM_CCER_CC3NP;
7018 /* Set the Output N Polarity */
7019 tmpccer |= (OC_Config->OCNPolarity << 8U);
7020 /* Reset the Output N State */
7021 tmpccer &= ~TIM_CCER_CC3NE;
7022 }
7023
7024 if (IS_TIM_BREAK_INSTANCE(TIMx))
7025 {
7026 /* Check parameters */
7027 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7028 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7029
7030 /* Reset the Output Compare and Output Compare N IDLE State */
7031 tmpcr2 &= ~TIM_CR2_OIS3;
7032 tmpcr2 &= ~TIM_CR2_OIS3N;
7033 /* Set the Output Idle state */
7034 tmpcr2 |= (OC_Config->OCIdleState << 4U);
7035 /* Set the Output N Idle state */
7036 tmpcr2 |= (OC_Config->OCNIdleState << 4U);
7037 }
7038
7039 /* Write to TIMx CR2 */
7040 TIMx->CR2 = tmpcr2;
7041
7042 /* Write to TIMx CCMR2 */
7043 TIMx->CCMR2 = tmpccmrx;
7044
7045 /* Set the Capture Compare Register value */
7046 TIMx->CCR3 = OC_Config->Pulse;
7047
7048 /* Write to TIMx CCER */
7049 TIMx->CCER = tmpccer;
7050 }
7051
7052 /**
7053 * @brief Timer Output Compare 4 configuration
7054 * @param TIMx to select the TIM peripheral
7055 * @param OC_Config The output configuration structure
7056 * @retval None
7057 */
TIM_OC4_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7058 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7059 {
7060 uint32_t tmpccmrx;
7061 uint32_t tmpccer;
7062 uint32_t tmpcr2;
7063
7064 /* Get the TIMx CCER register value */
7065 tmpccer = TIMx->CCER;
7066
7067 /* Disable the Channel 4: Reset the CC4E Bit */
7068 TIMx->CCER &= ~TIM_CCER_CC4E;
7069
7070 /* Get the TIMx CR2 register value */
7071 tmpcr2 = TIMx->CR2;
7072
7073 /* Get the TIMx CCMR2 register value */
7074 tmpccmrx = TIMx->CCMR2;
7075
7076 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7077 tmpccmrx &= ~TIM_CCMR2_OC4M;
7078 tmpccmrx &= ~TIM_CCMR2_CC4S;
7079
7080 /* Select the Output Compare Mode */
7081 tmpccmrx |= (OC_Config->OCMode << 8U);
7082
7083 /* Reset the Output Polarity level */
7084 tmpccer &= ~TIM_CCER_CC4P;
7085 /* Set the Output Compare Polarity */
7086 tmpccer |= (OC_Config->OCPolarity << 12U);
7087
7088 if (IS_TIM_BREAK_INSTANCE(TIMx))
7089 {
7090 /* Check parameters */
7091 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7092
7093 /* Reset the Output Compare IDLE State */
7094 tmpcr2 &= ~TIM_CR2_OIS4;
7095
7096 /* Set the Output Idle state */
7097 tmpcr2 |= (OC_Config->OCIdleState << 6U);
7098 }
7099
7100 /* Write to TIMx CR2 */
7101 TIMx->CR2 = tmpcr2;
7102
7103 /* Write to TIMx CCMR2 */
7104 TIMx->CCMR2 = tmpccmrx;
7105
7106 /* Set the Capture Compare Register value */
7107 TIMx->CCR4 = OC_Config->Pulse;
7108
7109 /* Write to TIMx CCER */
7110 TIMx->CCER = tmpccer;
7111 }
7112
7113 /**
7114 * @brief Slave Timer configuration function
7115 * @param htim TIM handle
7116 * @param sSlaveConfig Slave timer configuration
7117 * @retval None
7118 */
TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)7119 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
7120 const TIM_SlaveConfigTypeDef *sSlaveConfig)
7121 {
7122 HAL_StatusTypeDef status = HAL_OK;
7123 uint32_t tmpsmcr;
7124 uint32_t tmpccmr1;
7125 uint32_t tmpccer;
7126
7127 /* Get the TIMx SMCR register value */
7128 tmpsmcr = htim->Instance->SMCR;
7129
7130 /* Reset the Trigger Selection Bits */
7131 tmpsmcr &= ~TIM_SMCR_TS;
7132 /* Set the Input Trigger source */
7133 tmpsmcr |= sSlaveConfig->InputTrigger;
7134
7135 /* Reset the slave mode Bits */
7136 tmpsmcr &= ~TIM_SMCR_SMS;
7137 /* Set the slave mode */
7138 tmpsmcr |= sSlaveConfig->SlaveMode;
7139
7140 /* Write to TIMx SMCR */
7141 htim->Instance->SMCR = tmpsmcr;
7142
7143 /* Configure the trigger prescaler, filter, and polarity */
7144 switch (sSlaveConfig->InputTrigger)
7145 {
7146 case TIM_TS_ETRF:
7147 {
7148 /* Check the parameters */
7149 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
7150 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
7151 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7152 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7153 /* Configure the ETR Trigger source */
7154 TIM_ETR_SetConfig(htim->Instance,
7155 sSlaveConfig->TriggerPrescaler,
7156 sSlaveConfig->TriggerPolarity,
7157 sSlaveConfig->TriggerFilter);
7158 break;
7159 }
7160
7161 case TIM_TS_TI1F_ED:
7162 {
7163 /* Check the parameters */
7164 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7165 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7166
7167 if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
7168 {
7169 return HAL_ERROR;
7170 }
7171
7172 /* Disable the Channel 1: Reset the CC1E Bit */
7173 tmpccer = htim->Instance->CCER;
7174 htim->Instance->CCER &= ~TIM_CCER_CC1E;
7175 tmpccmr1 = htim->Instance->CCMR1;
7176
7177 /* Set the filter */
7178 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7179 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
7180
7181 /* Write to TIMx CCMR1 and CCER registers */
7182 htim->Instance->CCMR1 = tmpccmr1;
7183 htim->Instance->CCER = tmpccer;
7184 break;
7185 }
7186
7187 case TIM_TS_TI1FP1:
7188 {
7189 /* Check the parameters */
7190 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7191 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7192 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7193
7194 /* Configure TI1 Filter and Polarity */
7195 TIM_TI1_ConfigInputStage(htim->Instance,
7196 sSlaveConfig->TriggerPolarity,
7197 sSlaveConfig->TriggerFilter);
7198 break;
7199 }
7200
7201 case TIM_TS_TI2FP2:
7202 {
7203 /* Check the parameters */
7204 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
7205 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7206 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7207
7208 /* Configure TI2 Filter and Polarity */
7209 TIM_TI2_ConfigInputStage(htim->Instance,
7210 sSlaveConfig->TriggerPolarity,
7211 sSlaveConfig->TriggerFilter);
7212 break;
7213 }
7214
7215 case TIM_TS_ITR0:
7216 case TIM_TS_ITR1:
7217 case TIM_TS_ITR2:
7218 case TIM_TS_ITR3:
7219 {
7220 /* Check the parameter */
7221 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
7222 break;
7223 }
7224
7225 default:
7226 status = HAL_ERROR;
7227 break;
7228 }
7229
7230 return status;
7231 }
7232
7233 /**
7234 * @brief Configure the TI1 as Input.
7235 * @param TIMx to select the TIM peripheral.
7236 * @param TIM_ICPolarity The Input Polarity.
7237 * This parameter can be one of the following values:
7238 * @arg TIM_ICPOLARITY_RISING
7239 * @arg TIM_ICPOLARITY_FALLING
7240 * @arg TIM_ICPOLARITY_BOTHEDGE
7241 * @param TIM_ICSelection specifies the input to be used.
7242 * This parameter can be one of the following values:
7243 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
7244 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
7245 * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
7246 * @param TIM_ICFilter Specifies the Input Capture Filter.
7247 * This parameter must be a value between 0x00 and 0x0F.
7248 * @retval None
7249 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
7250 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
7251 * protected against un-initialized filter and polarity values.
7252 */
TIM_TI1_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7253 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7254 uint32_t TIM_ICFilter)
7255 {
7256 uint32_t tmpccmr1;
7257 uint32_t tmpccer;
7258
7259 /* Disable the Channel 1: Reset the CC1E Bit */
7260 tmpccer = TIMx->CCER;
7261 TIMx->CCER &= ~TIM_CCER_CC1E;
7262 tmpccmr1 = TIMx->CCMR1;
7263
7264 /* Select the Input */
7265 if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
7266 {
7267 tmpccmr1 &= ~TIM_CCMR1_CC1S;
7268 tmpccmr1 |= TIM_ICSelection;
7269 }
7270 else
7271 {
7272 tmpccmr1 |= TIM_CCMR1_CC1S_0;
7273 }
7274
7275 /* Set the filter */
7276 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7277 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
7278
7279 /* Select the Polarity and set the CC1E Bit */
7280 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7281 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
7282
7283 /* Write to TIMx CCMR1 and CCER registers */
7284 TIMx->CCMR1 = tmpccmr1;
7285 TIMx->CCER = tmpccer;
7286 }
7287
7288 /**
7289 * @brief Configure the Polarity and Filter for TI1.
7290 * @param TIMx to select the TIM peripheral.
7291 * @param TIM_ICPolarity The Input Polarity.
7292 * This parameter can be one of the following values:
7293 * @arg TIM_ICPOLARITY_RISING
7294 * @arg TIM_ICPOLARITY_FALLING
7295 * @arg TIM_ICPOLARITY_BOTHEDGE
7296 * @param TIM_ICFilter Specifies the Input Capture Filter.
7297 * This parameter must be a value between 0x00 and 0x0F.
7298 * @retval None
7299 */
TIM_TI1_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7300 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7301 {
7302 uint32_t tmpccmr1;
7303 uint32_t tmpccer;
7304
7305 /* Disable the Channel 1: Reset the CC1E Bit */
7306 tmpccer = TIMx->CCER;
7307 TIMx->CCER &= ~TIM_CCER_CC1E;
7308 tmpccmr1 = TIMx->CCMR1;
7309
7310 /* Set the filter */
7311 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7312 tmpccmr1 |= (TIM_ICFilter << 4U);
7313
7314 /* Select the Polarity and set the CC1E Bit */
7315 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7316 tmpccer |= TIM_ICPolarity;
7317
7318 /* Write to TIMx CCMR1 and CCER registers */
7319 TIMx->CCMR1 = tmpccmr1;
7320 TIMx->CCER = tmpccer;
7321 }
7322
7323 /**
7324 * @brief Configure the TI2 as Input.
7325 * @param TIMx to select the TIM peripheral
7326 * @param TIM_ICPolarity The Input Polarity.
7327 * This parameter can be one of the following values:
7328 * @arg TIM_ICPOLARITY_RISING
7329 * @arg TIM_ICPOLARITY_FALLING
7330 * @arg TIM_ICPOLARITY_BOTHEDGE
7331 * @param TIM_ICSelection specifies the input to be used.
7332 * This parameter can be one of the following values:
7333 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
7334 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
7335 * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
7336 * @param TIM_ICFilter Specifies the Input Capture Filter.
7337 * This parameter must be a value between 0x00 and 0x0F.
7338 * @retval None
7339 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
7340 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
7341 * protected against un-initialized filter and polarity values.
7342 */
TIM_TI2_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7343 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7344 uint32_t TIM_ICFilter)
7345 {
7346 uint32_t tmpccmr1;
7347 uint32_t tmpccer;
7348
7349 /* Disable the Channel 2: Reset the CC2E Bit */
7350 tmpccer = TIMx->CCER;
7351 TIMx->CCER &= ~TIM_CCER_CC2E;
7352 tmpccmr1 = TIMx->CCMR1;
7353
7354 /* Select the Input */
7355 tmpccmr1 &= ~TIM_CCMR1_CC2S;
7356 tmpccmr1 |= (TIM_ICSelection << 8U);
7357
7358 /* Set the filter */
7359 tmpccmr1 &= ~TIM_CCMR1_IC2F;
7360 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
7361
7362 /* Select the Polarity and set the CC2E Bit */
7363 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7364 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
7365
7366 /* Write to TIMx CCMR1 and CCER registers */
7367 TIMx->CCMR1 = tmpccmr1 ;
7368 TIMx->CCER = tmpccer;
7369 }
7370
7371 /**
7372 * @brief Configure the Polarity and Filter for TI2.
7373 * @param TIMx to select the TIM peripheral.
7374 * @param TIM_ICPolarity The Input Polarity.
7375 * This parameter can be one of the following values:
7376 * @arg TIM_ICPOLARITY_RISING
7377 * @arg TIM_ICPOLARITY_FALLING
7378 * @arg TIM_ICPOLARITY_BOTHEDGE
7379 * @param TIM_ICFilter Specifies the Input Capture Filter.
7380 * This parameter must be a value between 0x00 and 0x0F.
7381 * @retval None
7382 */
TIM_TI2_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7383 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7384 {
7385 uint32_t tmpccmr1;
7386 uint32_t tmpccer;
7387
7388 /* Disable the Channel 2: Reset the CC2E Bit */
7389 tmpccer = TIMx->CCER;
7390 TIMx->CCER &= ~TIM_CCER_CC2E;
7391 tmpccmr1 = TIMx->CCMR1;
7392
7393 /* Set the filter */
7394 tmpccmr1 &= ~TIM_CCMR1_IC2F;
7395 tmpccmr1 |= (TIM_ICFilter << 12U);
7396
7397 /* Select the Polarity and set the CC2E Bit */
7398 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7399 tmpccer |= (TIM_ICPolarity << 4U);
7400
7401 /* Write to TIMx CCMR1 and CCER registers */
7402 TIMx->CCMR1 = tmpccmr1 ;
7403 TIMx->CCER = tmpccer;
7404 }
7405
7406 /**
7407 * @brief Configure the TI3 as Input.
7408 * @param TIMx to select the TIM peripheral
7409 * @param TIM_ICPolarity The Input Polarity.
7410 * This parameter can be one of the following values:
7411 * @arg TIM_ICPOLARITY_RISING
7412 * @arg TIM_ICPOLARITY_FALLING
7413 * @param TIM_ICSelection specifies the input to be used.
7414 * This parameter can be one of the following values:
7415 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
7416 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
7417 * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
7418 * @param TIM_ICFilter Specifies the Input Capture Filter.
7419 * This parameter must be a value between 0x00 and 0x0F.
7420 * @retval None
7421 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
7422 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7423 * protected against un-initialized filter and polarity values.
7424 */
TIM_TI3_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7425 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7426 uint32_t TIM_ICFilter)
7427 {
7428 uint32_t tmpccmr2;
7429 uint32_t tmpccer;
7430
7431 /* Disable the Channel 3: Reset the CC3E Bit */
7432 tmpccer = TIMx->CCER;
7433 TIMx->CCER &= ~TIM_CCER_CC3E;
7434 tmpccmr2 = TIMx->CCMR2;
7435
7436 /* Select the Input */
7437 tmpccmr2 &= ~TIM_CCMR2_CC3S;
7438 tmpccmr2 |= TIM_ICSelection;
7439
7440 /* Set the filter */
7441 tmpccmr2 &= ~TIM_CCMR2_IC3F;
7442 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
7443
7444 /* Select the Polarity and set the CC3E Bit */
7445 tmpccer &= ~(TIM_CCER_CC3P);
7446 tmpccer |= ((TIM_ICPolarity << 8U) & TIM_CCER_CC3P);
7447
7448 /* Write to TIMx CCMR2 and CCER registers */
7449 TIMx->CCMR2 = tmpccmr2;
7450 TIMx->CCER = tmpccer;
7451 }
7452
7453 /**
7454 * @brief Configure the TI4 as Input.
7455 * @param TIMx to select the TIM peripheral
7456 * @param TIM_ICPolarity The Input Polarity.
7457 * This parameter can be one of the following values:
7458 * @arg TIM_ICPOLARITY_RISING
7459 * @arg TIM_ICPOLARITY_FALLING
7460 * @param TIM_ICSelection specifies the input to be used.
7461 * This parameter can be one of the following values:
7462 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
7463 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
7464 * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
7465 * @param TIM_ICFilter Specifies the Input Capture Filter.
7466 * This parameter must be a value between 0x00 and 0x0F.
7467 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
7468 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7469 * protected against un-initialized filter and polarity values.
7470 * @retval None
7471 */
TIM_TI4_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7472 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7473 uint32_t TIM_ICFilter)
7474 {
7475 uint32_t tmpccmr2;
7476 uint32_t tmpccer;
7477
7478 /* Disable the Channel 4: Reset the CC4E Bit */
7479 tmpccer = TIMx->CCER;
7480 TIMx->CCER &= ~TIM_CCER_CC4E;
7481 tmpccmr2 = TIMx->CCMR2;
7482
7483 /* Select the Input */
7484 tmpccmr2 &= ~TIM_CCMR2_CC4S;
7485 tmpccmr2 |= (TIM_ICSelection << 8U);
7486
7487 /* Set the filter */
7488 tmpccmr2 &= ~TIM_CCMR2_IC4F;
7489 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
7490
7491 /* Select the Polarity and set the CC4E Bit */
7492 tmpccer &= ~(TIM_CCER_CC4P);
7493 tmpccer |= ((TIM_ICPolarity << 12U) & TIM_CCER_CC4P);
7494
7495 /* Write to TIMx CCMR2 and CCER registers */
7496 TIMx->CCMR2 = tmpccmr2;
7497 TIMx->CCER = tmpccer ;
7498 }
7499
7500 /**
7501 * @brief Selects the Input Trigger source
7502 * @param TIMx to select the TIM peripheral
7503 * @param InputTriggerSource The Input Trigger source.
7504 * This parameter can be one of the following values:
7505 * @arg TIM_TS_ITR0: Internal Trigger 0
7506 * @arg TIM_TS_ITR1: Internal Trigger 1
7507 * @arg TIM_TS_ITR2: Internal Trigger 2
7508 * @arg TIM_TS_ITR3: Internal Trigger 3
7509 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
7510 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
7511 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
7512 * @arg TIM_TS_ETRF: External Trigger input
7513 * @retval None
7514 */
TIM_ITRx_SetConfig(TIM_TypeDef * TIMx,uint32_t InputTriggerSource)7515 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
7516 {
7517 uint32_t tmpsmcr;
7518
7519 /* Get the TIMx SMCR register value */
7520 tmpsmcr = TIMx->SMCR;
7521 /* Reset the TS Bits */
7522 tmpsmcr &= ~TIM_SMCR_TS;
7523 /* Set the Input Trigger source and the slave mode*/
7524 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
7525 /* Write to TIMx SMCR */
7526 TIMx->SMCR = tmpsmcr;
7527 }
7528 /**
7529 * @brief Configures the TIMx External Trigger (ETR).
7530 * @param TIMx to select the TIM peripheral
7531 * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
7532 * This parameter can be one of the following values:
7533 * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
7534 * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
7535 * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
7536 * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
7537 * @param TIM_ExtTRGPolarity The external Trigger Polarity.
7538 * This parameter can be one of the following values:
7539 * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
7540 * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
7541 * @param ExtTRGFilter External Trigger Filter.
7542 * This parameter must be a value between 0x00 and 0x0F
7543 * @retval None
7544 */
TIM_ETR_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ExtTRGPrescaler,uint32_t TIM_ExtTRGPolarity,uint32_t ExtTRGFilter)7545 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
7546 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
7547 {
7548 uint32_t tmpsmcr;
7549
7550 tmpsmcr = TIMx->SMCR;
7551
7552 /* Reset the ETR Bits */
7553 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
7554
7555 /* Set the Prescaler, the Filter value and the Polarity */
7556 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
7557
7558 /* Write to TIMx SMCR */
7559 TIMx->SMCR = tmpsmcr;
7560 }
7561
7562 /**
7563 * @brief Enables or disables the TIM Capture Compare Channel x.
7564 * @param TIMx to select the TIM peripheral
7565 * @param Channel specifies the TIM Channel
7566 * This parameter can be one of the following values:
7567 * @arg TIM_CHANNEL_1: TIM Channel 1
7568 * @arg TIM_CHANNEL_2: TIM Channel 2
7569 * @arg TIM_CHANNEL_3: TIM Channel 3
7570 * @arg TIM_CHANNEL_4: TIM Channel 4
7571 * @param ChannelState specifies the TIM Channel CCxE bit new state.
7572 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
7573 * @retval None
7574 */
TIM_CCxChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelState)7575 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
7576 {
7577 uint32_t tmp;
7578
7579 /* Check the parameters */
7580 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
7581 assert_param(IS_TIM_CHANNELS(Channel));
7582
7583 tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
7584
7585 /* Reset the CCxE Bit */
7586 TIMx->CCER &= ~tmp;
7587
7588 /* Set or reset the CCxE Bit */
7589 TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
7590 }
7591
7592 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7593 /**
7594 * @brief Reset interrupt callbacks to the legacy weak callbacks.
7595 * @param htim pointer to a TIM_HandleTypeDef structure that contains
7596 * the configuration information for TIM module.
7597 * @retval None
7598 */
TIM_ResetCallback(TIM_HandleTypeDef * htim)7599 void TIM_ResetCallback(TIM_HandleTypeDef *htim)
7600 {
7601 /* Reset the TIM callback to the legacy weak callbacks */
7602 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
7603 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
7604 htim->TriggerCallback = HAL_TIM_TriggerCallback;
7605 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
7606 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
7607 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
7608 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
7609 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
7610 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
7611 htim->ErrorCallback = HAL_TIM_ErrorCallback;
7612 htim->CommutationCallback = HAL_TIMEx_CommutCallback;
7613 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
7614 htim->BreakCallback = HAL_TIMEx_BreakCallback;
7615 }
7616 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7617
7618 /**
7619 * @}
7620 */
7621
7622 #endif /* HAL_TIM_MODULE_ENABLED */
7623 /**
7624 * @}
7625 */
7626
7627 /**
7628 * @}
7629 */
7630
