1 /**
2 ******************************************************************************
3 * @file stm32f1xx_hal_rcc.c
4 * @author MCD Application Team
5 * @brief RCC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Reset and Clock Control (RCC) peripheral:
8 * + Initialization and de-initialization functions
9 * + Peripheral Control functions
10 *
11 @verbatim
12 ==============================================================================
13 ##### RCC specific features #####
14 ==============================================================================
15 [..]
16 After reset the device is running from Internal High Speed oscillator
17 (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
18 and all peripherals are off except internal SRAM, Flash and JTAG.
19 (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
20 all peripherals mapped on these buses are running at HSI speed.
21 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
22 (+) All GPIOs are in input floating state, except the JTAG pins which
23 are assigned to be used for debug purpose.
24 [..] Once the device started from reset, the user application has to:
25 (+) Configure the clock source to be used to drive the System clock
26 (if the application needs higher frequency/performance)
27 (+) Configure the System clock frequency and Flash settings
28 (+) Configure the AHB and APB buses prescalers
29 (+) Enable the clock for the peripheral(s) to be used
30 (+) Configure the clock source(s) for peripherals whose clocks are not
31 derived from the System clock (I2S, RTC, ADC, USB OTG FS)
32
33 ##### RCC Limitations #####
34 ==============================================================================
35 [..]
36 A delay between an RCC peripheral clock enable and the effective peripheral
37 enabling should be taken into account in order to manage the peripheral read/write
38 from/to registers.
39 (+) This delay depends on the peripheral mapping.
40 (++) AHB & APB peripherals, 1 dummy read is necessary
41
42 [..]
43 Workarounds:
44 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
45 inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
46
47 @endverbatim
48 ******************************************************************************
49 * @attention
50 *
51 * Copyright (c) 2016 STMicroelectronics.
52 * All rights reserved.
53 *
54 * This software is licensed under terms that can be found in the LICENSE file in
55 * the root directory of this software component.
56 * If no LICENSE file comes with this software, it is provided AS-IS.
57 ******************************************************************************
58 */
59
60 /* Includes ------------------------------------------------------------------*/
61 #include "stm32f1xx_hal.h"
62
63 /** @addtogroup STM32F1xx_HAL_Driver
64 * @{
65 */
66
67 /** @defgroup RCC RCC
68 * @brief RCC HAL module driver
69 * @{
70 */
71
72 #ifdef HAL_RCC_MODULE_ENABLED
73
74 /* Private typedef -----------------------------------------------------------*/
75 /* Private define ------------------------------------------------------------*/
76 /** @defgroup RCC_Private_Constants RCC Private Constants
77 * @{
78 */
79 /**
80 * @}
81 */
82 /* Private macro -------------------------------------------------------------*/
83 /** @defgroup RCC_Private_Macros RCC Private Macros
84 * @{
85 */
86
87 #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
88 #define MCO1_GPIO_PORT GPIOA
89 #define MCO1_PIN GPIO_PIN_8
90
91 /**
92 * @}
93 */
94
95 /* Private variables ---------------------------------------------------------*/
96 /** @defgroup RCC_Private_Variables RCC Private Variables
97 * @{
98 */
99 /**
100 * @}
101 */
102
103 /* Private function prototypes -----------------------------------------------*/
104 static void RCC_Delay(uint32_t mdelay);
105
106 /* Exported functions --------------------------------------------------------*/
107
108 /** @defgroup RCC_Exported_Functions RCC Exported Functions
109 * @{
110 */
111
112 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
113 * @brief Initialization and Configuration functions
114 *
115 @verbatim
116 ===============================================================================
117 ##### Initialization and de-initialization functions #####
118 ===============================================================================
119 [..]
120 This section provides functions allowing to configure the internal/external oscillators
121 (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
122 and APB2).
123
124 [..] Internal/external clock and PLL configuration
125 (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
126 the PLL as System clock source.
127 (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC
128 clock source.
129
130 (#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x) crystal oscillator used directly or
131 through the PLL as System clock source. Can be used also as RTC clock source.
132
133 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
134
135 (#) PLL (clocked by HSI or HSE), featuring different output clocks:
136 (++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx)
137 (++) The second output is used to generate the clock for the USB OTG FS (48 MHz)
138
139 (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
140 and if a HSE clock failure occurs(HSE used directly or through PLL as System
141 clock source), the System clocks automatically switched to HSI and an interrupt
142 is generated if enabled. The interrupt is linked to the Cortex-M3 NMI
143 (Non-Maskable Interrupt) exception vector.
144
145 (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI,
146 HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x
147
148 [..] System, AHB and APB buses clocks configuration
149 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
150 HSE and PLL.
151 The AHB clock (HCLK) is derived from System clock through configurable
152 prescaler and used to clock the CPU, memory and peripherals mapped
153 on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
154 from AHB clock through configurable prescalers and used to clock
155 the peripherals mapped on these buses. You can use
156 "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
157
158 -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
159 (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock
160 divided by 128.
161 (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz
162 to work correctly. This clock is derived of the main PLL through PLL Multiplier.
163 (+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK
164 (+@) IWDG clock which is always the LSI clock.
165
166 (#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz.
167 For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz.
168 Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.
169 @endverbatim
170 * @{
171 */
172
173 /*
174 Additional consideration on the SYSCLK based on Latency settings:
175 +-----------------------------------------------+
176 | Latency | SYSCLK clock frequency (MHz) |
177 |---------------|-------------------------------|
178 |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
179 |---------------|-------------------------------|
180 |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
181 |---------------|-------------------------------|
182 |2WS(3CPU cycle)| 48 < SYSCLK <= 72 |
183 +-----------------------------------------------+
184 */
185
186 /**
187 * @brief Resets the RCC clock configuration to the default reset state.
188 * @note The default reset state of the clock configuration is given below:
189 * - HSI ON and used as system clock source
190 * - HSE, PLL, PLL2 and PLL3 are OFF
191 * - AHB, APB1 and APB2 prescaler set to 1.
192 * - CSS and MCO1 OFF
193 * - All interrupts disabled
194 * - All flags are cleared
195 * @note This function does not modify the configuration of the
196 * - Peripheral clocks
197 * - LSI, LSE and RTC clocks
198 * @retval HAL_StatusTypeDef
199 */
HAL_RCC_DeInit(void)200 HAL_StatusTypeDef HAL_RCC_DeInit(void)
201 {
202 uint32_t tickstart;
203
204 /* Get Start Tick */
205 tickstart = HAL_GetTick();
206
207 /* Set HSION bit */
208 SET_BIT(RCC->CR, RCC_CR_HSION);
209
210 /* Wait till HSI is ready */
211 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
212 {
213 if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
214 {
215 return HAL_TIMEOUT;
216 }
217 }
218
219 /* Set HSITRIM bits to the reset value */
220 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos));
221
222 /* Get Start Tick */
223 tickstart = HAL_GetTick();
224
225 /* Reset CFGR register */
226 CLEAR_REG(RCC->CFGR);
227
228 /* Wait till clock switch is ready */
229 while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET)
230 {
231 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
232 {
233 return HAL_TIMEOUT;
234 }
235 }
236
237 /* Update the SystemCoreClock global variable */
238 SystemCoreClock = HSI_VALUE;
239
240 /* Adapt Systick interrupt period */
241 if (HAL_InitTick(uwTickPrio) != HAL_OK)
242 {
243 return HAL_ERROR;
244 }
245
246 /* Get Start Tick */
247 tickstart = HAL_GetTick();
248
249 /* Second step is to clear PLLON bit */
250 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
251
252 /* Wait till PLL is disabled */
253 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)
254 {
255 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
256 {
257 return HAL_TIMEOUT;
258 }
259 }
260
261 /* Ensure to reset PLLSRC and PLLMUL bits */
262 CLEAR_REG(RCC->CFGR);
263
264 /* Get Start Tick */
265 tickstart = HAL_GetTick();
266
267 /* Reset HSEON & CSSON bits */
268 CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON);
269
270 /* Wait till HSE is disabled */
271 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET)
272 {
273 if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
274 {
275 return HAL_TIMEOUT;
276 }
277 }
278
279 /* Reset HSEBYP bit */
280 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
281
282 #if defined(RCC_PLL2_SUPPORT)
283 /* Get Start Tick */
284 tickstart = HAL_GetTick();
285
286 /* Clear PLL2ON bit */
287 CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
288
289 /* Wait till PLL2 is disabled */
290 while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET)
291 {
292 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
293 {
294 return HAL_TIMEOUT;
295 }
296 }
297 #endif /* RCC_PLL2_SUPPORT */
298
299 #if defined(RCC_PLLI2S_SUPPORT)
300 /* Get Start Tick */
301 tickstart = HAL_GetTick();
302
303 /* Clear PLL3ON bit */
304 CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
305
306 /* Wait till PLL3 is disabled */
307 while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET)
308 {
309 if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
310 {
311 return HAL_TIMEOUT;
312 }
313 }
314 #endif /* RCC_PLLI2S_SUPPORT */
315
316 #if defined(RCC_CFGR2_PREDIV1)
317 /* Reset CFGR2 register */
318 CLEAR_REG(RCC->CFGR2);
319 #endif /* RCC_CFGR2_PREDIV1 */
320
321 /* Reset all CSR flags */
322 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
323
324 /* Disable all interrupts */
325 CLEAR_REG(RCC->CIR);
326
327 return HAL_OK;
328 }
329
330 /**
331 * @brief Initializes the RCC Oscillators according to the specified parameters in the
332 * RCC_OscInitTypeDef.
333 * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
334 * contains the configuration information for the RCC Oscillators.
335 * @note The PLL is not disabled when used as system clock.
336 * @note The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS)
337 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
338 * supported by this macro. User should request a transition to LSE Off
339 * first and then LSE On or LSE Bypass.
340 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
341 * supported by this macro. User should request a transition to HSE Off
342 * first and then HSE On or HSE Bypass.
343 * @retval HAL status
344 */
HAL_RCC_OscConfig(RCC_OscInitTypeDef * RCC_OscInitStruct)345 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
346 {
347 uint32_t tickstart;
348 uint32_t pll_config;
349
350 /* Check Null pointer */
351 if (RCC_OscInitStruct == NULL)
352 {
353 return HAL_ERROR;
354 }
355
356 /* Check the parameters */
357 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
358
359 /*------------------------------- HSE Configuration ------------------------*/
360 if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
361 {
362 /* Check the parameters */
363 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
364
365 /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
366 if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
367 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
368 {
369 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
370 {
371 return HAL_ERROR;
372 }
373 }
374 else
375 {
376 /* Set the new HSE configuration ---------------------------------------*/
377 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
378
379
380 /* Check the HSE State */
381 if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
382 {
383 /* Get Start Tick */
384 tickstart = HAL_GetTick();
385
386 /* Wait till HSE is ready */
387 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
388 {
389 if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
390 {
391 return HAL_TIMEOUT;
392 }
393 }
394 }
395 else
396 {
397 /* Get Start Tick */
398 tickstart = HAL_GetTick();
399
400 /* Wait till HSE is disabled */
401 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
402 {
403 if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
404 {
405 return HAL_TIMEOUT;
406 }
407 }
408 }
409 }
410 }
411 /*----------------------------- HSI Configuration --------------------------*/
412 if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
413 {
414 /* Check the parameters */
415 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
416 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
417
418 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
419 if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
420 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
421 {
422 /* When HSI is used as system clock it will not disabled */
423 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
424 {
425 return HAL_ERROR;
426 }
427 /* Otherwise, just the calibration is allowed */
428 else
429 {
430 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
431 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
432 }
433 }
434 else
435 {
436 /* Check the HSI State */
437 if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
438 {
439 /* Enable the Internal High Speed oscillator (HSI). */
440 __HAL_RCC_HSI_ENABLE();
441
442 /* Get Start Tick */
443 tickstart = HAL_GetTick();
444
445 /* Wait till HSI is ready */
446 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
447 {
448 if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
449 {
450 return HAL_TIMEOUT;
451 }
452 }
453
454 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
455 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
456 }
457 else
458 {
459 /* Disable the Internal High Speed oscillator (HSI). */
460 __HAL_RCC_HSI_DISABLE();
461
462 /* Get Start Tick */
463 tickstart = HAL_GetTick();
464
465 /* Wait till HSI is disabled */
466 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
467 {
468 if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
469 {
470 return HAL_TIMEOUT;
471 }
472 }
473 }
474 }
475 }
476 /*------------------------------ LSI Configuration -------------------------*/
477 if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
478 {
479 /* Check the parameters */
480 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
481
482 /* Check the LSI State */
483 if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
484 {
485 /* Enable the Internal Low Speed oscillator (LSI). */
486 __HAL_RCC_LSI_ENABLE();
487
488 /* Get Start Tick */
489 tickstart = HAL_GetTick();
490
491 /* Wait till LSI is ready */
492 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
493 {
494 if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
495 {
496 return HAL_TIMEOUT;
497 }
498 }
499 /* To have a fully stabilized clock in the specified range, a software delay of 1ms
500 should be added.*/
501 RCC_Delay(1);
502 }
503 else
504 {
505 /* Disable the Internal Low Speed oscillator (LSI). */
506 __HAL_RCC_LSI_DISABLE();
507
508 /* Get Start Tick */
509 tickstart = HAL_GetTick();
510
511 /* Wait till LSI is disabled */
512 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
513 {
514 if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
515 {
516 return HAL_TIMEOUT;
517 }
518 }
519 }
520 }
521 /*------------------------------ LSE Configuration -------------------------*/
522 if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
523 {
524 FlagStatus pwrclkchanged = RESET;
525
526 /* Check the parameters */
527 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
528
529 /* Update LSE configuration in Backup Domain control register */
530 /* Requires to enable write access to Backup Domain of necessary */
531 if (__HAL_RCC_PWR_IS_CLK_DISABLED())
532 {
533 __HAL_RCC_PWR_CLK_ENABLE();
534 pwrclkchanged = SET;
535 }
536
537 if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
538 {
539 /* Enable write access to Backup domain */
540 SET_BIT(PWR->CR, PWR_CR_DBP);
541
542 /* Wait for Backup domain Write protection disable */
543 tickstart = HAL_GetTick();
544
545 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
546 {
547 if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
548 {
549 return HAL_TIMEOUT;
550 }
551 }
552 }
553
554 /* Set the new LSE configuration -----------------------------------------*/
555 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
556 /* Check the LSE State */
557 if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
558 {
559 /* Get Start Tick */
560 tickstart = HAL_GetTick();
561
562 /* Wait till LSE is ready */
563 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
564 {
565 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
566 {
567 return HAL_TIMEOUT;
568 }
569 }
570 }
571 else
572 {
573 /* Get Start Tick */
574 tickstart = HAL_GetTick();
575
576 /* Wait till LSE is disabled */
577 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
578 {
579 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
580 {
581 return HAL_TIMEOUT;
582 }
583 }
584 }
585
586 /* Require to disable power clock if necessary */
587 if (pwrclkchanged == SET)
588 {
589 __HAL_RCC_PWR_CLK_DISABLE();
590 }
591 }
592
593 #if defined(RCC_CR_PLL2ON)
594 /*-------------------------------- PLL2 Configuration -----------------------*/
595 /* Check the parameters */
596 assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State));
597 if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE)
598 {
599 /* This bit can not be cleared if the PLL2 clock is used indirectly as system
600 clock (i.e. it is used as PLL clock entry that is used as system clock). */
601 if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
602 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
603 ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
604 {
605 return HAL_ERROR;
606 }
607 else
608 {
609 if ((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON)
610 {
611 /* Check the parameters */
612 assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL));
613 assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value));
614
615 /* Prediv2 can be written only when the PLLI2S is disabled. */
616 /* Return an error only if new value is different from the programmed value */
617 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \
618 (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value))
619 {
620 return HAL_ERROR;
621 }
622
623 /* Disable the main PLL2. */
624 __HAL_RCC_PLL2_DISABLE();
625
626 /* Get Start Tick */
627 tickstart = HAL_GetTick();
628
629 /* Wait till PLL2 is disabled */
630 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
631 {
632 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
633 {
634 return HAL_TIMEOUT;
635 }
636 }
637
638 /* Configure the HSE prediv2 factor --------------------------------*/
639 __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value);
640
641 /* Configure the main PLL2 multiplication factors. */
642 __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL);
643
644 /* Enable the main PLL2. */
645 __HAL_RCC_PLL2_ENABLE();
646
647 /* Get Start Tick */
648 tickstart = HAL_GetTick();
649
650 /* Wait till PLL2 is ready */
651 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
652 {
653 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
654 {
655 return HAL_TIMEOUT;
656 }
657 }
658 }
659 else
660 {
661 /* Set PREDIV1 source to HSE */
662 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);
663
664 /* Disable the main PLL2. */
665 __HAL_RCC_PLL2_DISABLE();
666
667 /* Get Start Tick */
668 tickstart = HAL_GetTick();
669
670 /* Wait till PLL2 is disabled */
671 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
672 {
673 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
674 {
675 return HAL_TIMEOUT;
676 }
677 }
678 }
679 }
680 }
681
682 #endif /* RCC_CR_PLL2ON */
683 /*-------------------------------- PLL Configuration -----------------------*/
684 /* Check the parameters */
685 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
686 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
687 {
688 /* Check if the PLL is used as system clock or not */
689 if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
690 {
691 if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
692 {
693 /* Check the parameters */
694 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
695 assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
696
697 /* Disable the main PLL. */
698 __HAL_RCC_PLL_DISABLE();
699
700 /* Get Start Tick */
701 tickstart = HAL_GetTick();
702
703 /* Wait till PLL is disabled */
704 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
705 {
706 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
707 {
708 return HAL_TIMEOUT;
709 }
710 }
711
712 /* Configure the HSE prediv factor --------------------------------*/
713 /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
714 if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
715 {
716 /* Check the parameter */
717 assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue));
718 #if defined(RCC_CFGR2_PREDIV1SRC)
719 assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source));
720
721 /* Set PREDIV1 source */
722 SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
723 #endif /* RCC_CFGR2_PREDIV1SRC */
724
725 /* Set PREDIV1 Value */
726 __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
727 }
728
729 /* Configure the main PLL clock source and multiplication factors. */
730 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
731 RCC_OscInitStruct->PLL.PLLMUL);
732 /* Enable the main PLL. */
733 __HAL_RCC_PLL_ENABLE();
734
735 /* Get Start Tick */
736 tickstart = HAL_GetTick();
737
738 /* Wait till PLL is ready */
739 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
740 {
741 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
742 {
743 return HAL_TIMEOUT;
744 }
745 }
746 }
747 else
748 {
749 /* Disable the main PLL. */
750 __HAL_RCC_PLL_DISABLE();
751
752 /* Get Start Tick */
753 tickstart = HAL_GetTick();
754
755 /* Wait till PLL is disabled */
756 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
757 {
758 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
759 {
760 return HAL_TIMEOUT;
761 }
762 }
763 }
764 }
765 else
766 {
767 /* Check if there is a request to disable the PLL used as System clock source */
768 if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
769 {
770 return HAL_ERROR;
771 }
772 else
773 {
774 /* Do not return HAL_ERROR if request repeats the current configuration */
775 pll_config = RCC->CFGR;
776 if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
777 (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
778 {
779 return HAL_ERROR;
780 }
781 }
782 }
783 }
784
785 return HAL_OK;
786 }
787
788 /**
789 * @brief Initializes the CPU, AHB and APB buses clocks according to the specified
790 * parameters in the RCC_ClkInitStruct.
791 * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
792 * contains the configuration information for the RCC peripheral.
793 * @param FLatency FLASH Latency
794 * The value of this parameter depend on device used within the same series
795 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
796 * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
797 *
798 * @note The HSI is used (enabled by hardware) as system clock source after
799 * start-up from Reset, wake-up from STOP and STANDBY mode, or in case
800 * of failure of the HSE used directly or indirectly as system clock
801 * (if the Clock Security System CSS is enabled).
802 *
803 * @note A switch from one clock source to another occurs only if the target
804 * clock source is ready (clock stable after start-up delay or PLL locked).
805 * If a clock source which is not yet ready is selected, the switch will
806 * occur when the clock source will be ready.
807 * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
808 * currently used as system clock source.
809 * @retval HAL status
810 */
HAL_RCC_ClockConfig(RCC_ClkInitTypeDef * RCC_ClkInitStruct,uint32_t FLatency)811 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
812 {
813 uint32_t tickstart;
814
815 /* Check Null pointer */
816 if (RCC_ClkInitStruct == NULL)
817 {
818 return HAL_ERROR;
819 }
820
821 /* Check the parameters */
822 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
823 assert_param(IS_FLASH_LATENCY(FLatency));
824
825 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
826 must be correctly programmed according to the frequency of the CPU clock
827 (HCLK) of the device. */
828
829 #if defined(FLASH_ACR_LATENCY)
830 /* Increasing the number of wait states because of higher CPU frequency */
831 if (FLatency > __HAL_FLASH_GET_LATENCY())
832 {
833 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
834 __HAL_FLASH_SET_LATENCY(FLatency);
835
836 /* Check that the new number of wait states is taken into account to access the Flash
837 memory by reading the FLASH_ACR register */
838 if (__HAL_FLASH_GET_LATENCY() != FLatency)
839 {
840 return HAL_ERROR;
841 }
842 }
843
844 #endif /* FLASH_ACR_LATENCY */
845 /*-------------------------- HCLK Configuration --------------------------*/
846 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
847 {
848 /* Set the highest APBx dividers in order to ensure that we do not go through
849 a non-spec phase whatever we decrease or increase HCLK. */
850 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
851 {
852 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
853 }
854
855 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
856 {
857 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
858 }
859
860 /* Set the new HCLK clock divider */
861 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
862 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
863 }
864
865 /*------------------------- SYSCLK Configuration ---------------------------*/
866 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
867 {
868 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
869
870 /* HSE is selected as System Clock Source */
871 if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
872 {
873 /* Check the HSE ready flag */
874 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
875 {
876 return HAL_ERROR;
877 }
878 }
879 /* PLL is selected as System Clock Source */
880 else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
881 {
882 /* Check the PLL ready flag */
883 if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
884 {
885 return HAL_ERROR;
886 }
887 }
888 /* HSI is selected as System Clock Source */
889 else
890 {
891 /* Check the HSI ready flag */
892 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
893 {
894 return HAL_ERROR;
895 }
896 }
897 __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
898
899 /* Get Start Tick */
900 tickstart = HAL_GetTick();
901
902 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
903 {
904 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
905 {
906 return HAL_TIMEOUT;
907 }
908 }
909 }
910
911 #if defined(FLASH_ACR_LATENCY)
912 /* Decreasing the number of wait states because of lower CPU frequency */
913 if (FLatency < __HAL_FLASH_GET_LATENCY())
914 {
915 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
916 __HAL_FLASH_SET_LATENCY(FLatency);
917
918 /* Check that the new number of wait states is taken into account to access the Flash
919 memory by reading the FLASH_ACR register */
920 if (__HAL_FLASH_GET_LATENCY() != FLatency)
921 {
922 return HAL_ERROR;
923 }
924 }
925 #endif /* FLASH_ACR_LATENCY */
926
927 /*-------------------------- PCLK1 Configuration ---------------------------*/
928 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
929 {
930 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
931 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
932 }
933
934 /*-------------------------- PCLK2 Configuration ---------------------------*/
935 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
936 {
937 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
938 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
939 }
940
941 /* Update the SystemCoreClock global variable */
942 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
943
944 /* Configure the source of time base considering new system clocks settings*/
945 HAL_InitTick(uwTickPrio);
946
947 return HAL_OK;
948 }
949
950 /**
951 * @}
952 */
953
954 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
955 * @brief RCC clocks control functions
956 *
957 @verbatim
958 ===============================================================================
959 ##### Peripheral Control functions #####
960 ===============================================================================
961 [..]
962 This subsection provides a set of functions allowing to control the RCC Clocks
963 frequencies.
964
965 @endverbatim
966 * @{
967 */
968
969 /**
970 * @brief Selects the clock source to output on MCO pin.
971 * @note MCO pin should be configured in alternate function mode.
972 * @param RCC_MCOx specifies the output direction for the clock source.
973 * This parameter can be one of the following values:
974 * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
975 * @param RCC_MCOSource specifies the clock source to output.
976 * This parameter can be one of the following values:
977 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
978 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock
979 * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
980 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
981 @if STM32F105xC
982 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source
983 * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source
984 * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
985 * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source
986 * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source
987 @endif
988 @if STM32F107xC
989 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source
990 * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source
991 * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
992 * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source
993 * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source
994 @endif
995 * @param RCC_MCODiv specifies the MCO DIV.
996 * This parameter can be one of the following values:
997 * @arg @ref RCC_MCODIV_1 no division applied to MCO clock
998 * @retval None
999 */
HAL_RCC_MCOConfig(uint32_t RCC_MCOx,uint32_t RCC_MCOSource,uint32_t RCC_MCODiv)1000 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
1001 {
1002 GPIO_InitTypeDef gpio = {0U};
1003
1004 /* Check the parameters */
1005 assert_param(IS_RCC_MCO(RCC_MCOx));
1006 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
1007 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
1008
1009 /* Prevent unused argument(s) compilation warning */
1010 UNUSED(RCC_MCOx);
1011 UNUSED(RCC_MCODiv);
1012
1013 /* Configure the MCO1 pin in alternate function mode */
1014 gpio.Mode = GPIO_MODE_AF_PP;
1015 gpio.Speed = GPIO_SPEED_FREQ_HIGH;
1016 gpio.Pull = GPIO_NOPULL;
1017 gpio.Pin = MCO1_PIN;
1018
1019 /* MCO1 Clock Enable */
1020 MCO1_CLK_ENABLE();
1021
1022 HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
1023
1024 /* Configure the MCO clock source */
1025 __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);
1026 }
1027
1028 /**
1029 * @brief Enables the Clock Security System.
1030 * @note If a failure is detected on the HSE oscillator clock, this oscillator
1031 * is automatically disabled and an interrupt is generated to inform the
1032 * software about the failure (Clock Security System Interrupt, CSSI),
1033 * allowing the MCU to perform rescue operations. The CSSI is linked to
1034 * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
1035 * @retval None
1036 */
HAL_RCC_EnableCSS(void)1037 void HAL_RCC_EnableCSS(void)
1038 {
1039 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
1040 }
1041
1042 /**
1043 * @brief Disables the Clock Security System.
1044 * @retval None
1045 */
HAL_RCC_DisableCSS(void)1046 void HAL_RCC_DisableCSS(void)
1047 {
1048 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
1049 }
1050
1051 /**
1052 * @brief Returns the SYSCLK frequency
1053 * @note The system frequency computed by this function is not the real
1054 * frequency in the chip. It is calculated based on the predefined
1055 * constant and the selected clock source:
1056 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
1057 * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE
1058 * divided by PREDIV factor(**)
1059 * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE
1060 * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
1061 * @note (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
1062 * 8 MHz) but the real value may vary depending on the variations
1063 * in voltage and temperature.
1064 * @note (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
1065 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
1066 * frequency of the crystal used. Otherwise, this function may
1067 * have wrong result.
1068 *
1069 * @note The result of this function could be not correct when using fractional
1070 * value for HSE crystal.
1071 *
1072 * @note This function can be used by the user application to compute the
1073 * baud-rate for the communication peripherals or configure other parameters.
1074 *
1075 * @note Each time SYSCLK changes, this function must be called to update the
1076 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
1077 *
1078 * @retval SYSCLK frequency
1079 */
HAL_RCC_GetSysClockFreq(void)1080 uint32_t HAL_RCC_GetSysClockFreq(void)
1081 {
1082 #if defined(RCC_CFGR2_PREDIV1SRC)
1083 static const uint8_t aPLLMULFactorTable[14U] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
1084 static const uint8_t aPredivFactorTable[16U] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
1085 #else
1086 static const uint8_t aPLLMULFactorTable[16U] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
1087 #if defined(RCC_CFGR2_PREDIV1)
1088 static const uint8_t aPredivFactorTable[16U] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
1089 #else
1090 static const uint8_t aPredivFactorTable[2U] = {1, 2};
1091 #endif /*RCC_CFGR2_PREDIV1*/
1092
1093 #endif
1094 uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
1095 uint32_t sysclockfreq = 0U;
1096 #if defined(RCC_CFGR2_PREDIV1SRC)
1097 uint32_t prediv2 = 0U, pll2mul = 0U;
1098 #endif /*RCC_CFGR2_PREDIV1SRC*/
1099
1100 tmpreg = RCC->CFGR;
1101
1102 /* Get SYSCLK source -------------------------------------------------------*/
1103 switch (tmpreg & RCC_CFGR_SWS)
1104 {
1105 case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
1106 {
1107 sysclockfreq = HSE_VALUE;
1108 break;
1109 }
1110 case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
1111 {
1112 pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
1113 if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
1114 {
1115 #if defined(RCC_CFGR2_PREDIV1)
1116 prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
1117 #else
1118 prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
1119 #endif /*RCC_CFGR2_PREDIV1*/
1120 #if defined(RCC_CFGR2_PREDIV1SRC)
1121
1122 if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
1123 {
1124 /* PLL2 selected as Prediv1 source */
1125 /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
1126 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
1127 pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2;
1128 pllclk = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv));
1129 }
1130 else
1131 {
1132 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
1133 pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
1134 }
1135
1136 /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
1137 /* In this case need to divide pllclk by 2 */
1138 if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos])
1139 {
1140 pllclk = pllclk / 2;
1141 }
1142 #else
1143 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
1144 pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
1145 #endif /*RCC_CFGR2_PREDIV1SRC*/
1146 }
1147 else
1148 {
1149 /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
1150 pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
1151 }
1152 sysclockfreq = pllclk;
1153 break;
1154 }
1155 case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
1156 default: /* HSI used as system clock */
1157 {
1158 sysclockfreq = HSI_VALUE;
1159 break;
1160 }
1161 }
1162 return sysclockfreq;
1163 }
1164
1165 /**
1166 * @brief Returns the HCLK frequency
1167 * @note Each time HCLK changes, this function must be called to update the
1168 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
1169 *
1170 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
1171 * and updated within this function
1172 * @retval HCLK frequency
1173 */
HAL_RCC_GetHCLKFreq(void)1174 uint32_t HAL_RCC_GetHCLKFreq(void)
1175 {
1176 return SystemCoreClock;
1177 }
1178
1179 /**
1180 * @brief Returns the PCLK1 frequency
1181 * @note Each time PCLK1 changes, this function must be called to update the
1182 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
1183 * @retval PCLK1 frequency
1184 */
HAL_RCC_GetPCLK1Freq(void)1185 uint32_t HAL_RCC_GetPCLK1Freq(void)
1186 {
1187 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
1188 return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
1189 }
1190
1191 /**
1192 * @brief Returns the PCLK2 frequency
1193 * @note Each time PCLK2 changes, this function must be called to update the
1194 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
1195 * @retval PCLK2 frequency
1196 */
HAL_RCC_GetPCLK2Freq(void)1197 uint32_t HAL_RCC_GetPCLK2Freq(void)
1198 {
1199 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
1200 return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
1201 }
1202
1203 /**
1204 * @brief Configures the RCC_OscInitStruct according to the internal
1205 * RCC configuration registers.
1206 * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
1207 * will be configured.
1208 * @retval None
1209 */
HAL_RCC_GetOscConfig(RCC_OscInitTypeDef * RCC_OscInitStruct)1210 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
1211 {
1212 /* Check the parameters */
1213 assert_param(RCC_OscInitStruct != NULL);
1214
1215 /* Set all possible values for the Oscillator type parameter ---------------*/
1216 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \
1217 | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
1218
1219 #if defined(RCC_CFGR2_PREDIV1SRC)
1220 /* Get the Prediv1 source --------------------------------------------------*/
1221 RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);
1222 #endif /* RCC_CFGR2_PREDIV1SRC */
1223
1224 /* Get the HSE configuration -----------------------------------------------*/
1225 if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
1226 {
1227 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
1228 }
1229 else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
1230 {
1231 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
1232 }
1233 else
1234 {
1235 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
1236 }
1237 RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();
1238
1239 /* Get the HSI configuration -----------------------------------------------*/
1240 if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
1241 {
1242 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
1243 }
1244 else
1245 {
1246 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
1247 }
1248
1249 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
1250
1251 /* Get the LSE configuration -----------------------------------------------*/
1252 if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
1253 {
1254 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
1255 }
1256 else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
1257 {
1258 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
1259 }
1260 else
1261 {
1262 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
1263 }
1264
1265 /* Get the LSI configuration -----------------------------------------------*/
1266 if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION)
1267 {
1268 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
1269 }
1270 else
1271 {
1272 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
1273 }
1274
1275
1276 /* Get the PLL configuration -----------------------------------------------*/
1277 if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
1278 {
1279 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
1280 }
1281 else
1282 {
1283 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
1284 }
1285 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
1286 RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL);
1287 #if defined(RCC_CR_PLL2ON)
1288 /* Get the PLL2 configuration -----------------------------------------------*/
1289 if ((RCC->CR & RCC_CR_PLL2ON) == RCC_CR_PLL2ON)
1290 {
1291 RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON;
1292 }
1293 else
1294 {
1295 RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_OFF;
1296 }
1297 RCC_OscInitStruct->PLL2.HSEPrediv2Value = __HAL_RCC_HSE_GET_PREDIV2();
1298 RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL);
1299 #endif /* RCC_CR_PLL2ON */
1300 }
1301
1302 /**
1303 * @brief Get the RCC_ClkInitStruct according to the internal
1304 * RCC configuration registers.
1305 * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
1306 * contains the current clock configuration.
1307 * @param pFLatency Pointer on the Flash Latency.
1308 * @retval None
1309 */
HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef * RCC_ClkInitStruct,uint32_t * pFLatency)1310 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
1311 {
1312 /* Check the parameters */
1313 assert_param(RCC_ClkInitStruct != NULL);
1314 assert_param(pFLatency != NULL);
1315
1316 /* Set all possible values for the Clock type parameter --------------------*/
1317 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
1318
1319 /* Get the SYSCLK configuration --------------------------------------------*/
1320 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
1321
1322 /* Get the HCLK configuration ----------------------------------------------*/
1323 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
1324
1325 /* Get the APB1 configuration ----------------------------------------------*/
1326 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
1327
1328 /* Get the APB2 configuration ----------------------------------------------*/
1329 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
1330
1331 #if defined(FLASH_ACR_LATENCY)
1332 /* Get the Flash Wait State (Latency) configuration ------------------------*/
1333 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
1334 #else
1335 /* For VALUE lines devices, only LATENCY_0 can be set*/
1336 *pFLatency = (uint32_t)FLASH_LATENCY_0;
1337 #endif
1338 }
1339
1340 /**
1341 * @brief This function handles the RCC CSS interrupt request.
1342 * @note This API should be called under the NMI_Handler().
1343 * @retval None
1344 */
HAL_RCC_NMI_IRQHandler(void)1345 void HAL_RCC_NMI_IRQHandler(void)
1346 {
1347 /* Check RCC CSSF flag */
1348 if (__HAL_RCC_GET_IT(RCC_IT_CSS))
1349 {
1350 /* RCC Clock Security System interrupt user callback */
1351 HAL_RCC_CSSCallback();
1352
1353 /* Clear RCC CSS pending bit */
1354 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
1355 }
1356 }
1357
1358 /**
1359 * @brief This function provides delay (in milliseconds) based on CPU cycles method.
1360 * @param mdelay: specifies the delay time length, in milliseconds.
1361 * @retval None
1362 */
RCC_Delay(uint32_t mdelay)1363 static void RCC_Delay(uint32_t mdelay)
1364 {
1365 __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
1366 do
1367 {
1368 __NOP();
1369 }
1370 while (Delay --);
1371 }
1372
1373 /**
1374 * @brief RCC Clock Security System interrupt callback
1375 * @retval none
1376 */
HAL_RCC_CSSCallback(void)1377 __weak void HAL_RCC_CSSCallback(void)
1378 {
1379 /* NOTE : This function Should not be modified, when the callback is needed,
1380 the HAL_RCC_CSSCallback could be implemented in the user file
1381 */
1382 }
1383
1384 /**
1385 * @}
1386 */
1387
1388 /**
1389 * @}
1390 */
1391
1392 #endif /* HAL_RCC_MODULE_ENABLED */
1393 /**
1394 * @}
1395 */
1396
1397 /**
1398 * @}
1399 */
1400
1401
