1 /**
2 ******************************************************************************
3 * @file stm32f0xx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32f0xx_ll_tim.h"
22 #include "stm32f0xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32F0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7)
35
36 /** @addtogroup TIM_LL
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /** @addtogroup TIM_LL_Private_Macros
45 * @{
46 */
47 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
48 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
49 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
50 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
51 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
52
53 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
54 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
55 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
56
57 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
58 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
59 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
60 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
61 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
62 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
63 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
64 || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
65
66 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
67 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
68
69 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
70 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
71
72 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
73 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
74
75 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
76 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
77 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
78
79 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
80 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
81 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
82 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
83
84 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
85 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
86 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
87 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
88 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
89 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
90 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
91 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
92 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
93 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
94 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
95 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
96 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
97 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
98 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
99 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
100
101 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
102 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
103 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
104
105 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
106 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
107 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
108
109 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
110 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
111
112 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
113 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
114
115 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
116 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
117
118 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
119 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
120 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
121 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
122
123 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
124 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
125
126 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
127 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
128
129 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
130 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
131 /**
132 * @}
133 */
134
135
136 /* Private function prototypes -----------------------------------------------*/
137 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
138 * @{
139 */
140 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
141 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
142 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
143 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
144 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
145 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
146 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
147 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
148 /**
149 * @}
150 */
151
152 /* Exported functions --------------------------------------------------------*/
153 /** @addtogroup TIM_LL_Exported_Functions
154 * @{
155 */
156
157 /** @addtogroup TIM_LL_EF_Init
158 * @{
159 */
160
161 /**
162 * @brief Set TIMx registers to their reset values.
163 * @param TIMx Timer instance
164 * @retval An ErrorStatus enumeration value:
165 * - SUCCESS: TIMx registers are de-initialized
166 * - ERROR: invalid TIMx instance
167 */
LL_TIM_DeInit(const TIM_TypeDef * TIMx)168 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)
169 {
170 ErrorStatus result = SUCCESS;
171
172 /* Check the parameters */
173 assert_param(IS_TIM_INSTANCE(TIMx));
174
175 if (TIMx == TIM1)
176 {
177 LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM1);
178 LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM1);
179 }
180 #if defined (TIM2)
181 else if (TIMx == TIM2)
182 {
183 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
184 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
185 }
186 #endif /* TIM2 */
187 #if defined(TIM3)
188 else if (TIMx == TIM3)
189 {
190 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
191 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
192 }
193 #endif /* TIM3 */
194 #if defined(TIM5)
195 else if (TIMx == TIM5)
196 {
197 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
198 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
199 }
200 #endif /* TIM5 */
201 #if defined (TIM6)
202 else if (TIMx == TIM6)
203 {
204 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
205 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
206 }
207 #endif /* TIM6 */
208 #if defined (TIM7)
209 else if (TIMx == TIM7)
210 {
211 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
212 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
213 }
214 #endif /* TIM7 */
215 #if defined(TIM8)
216 else if (TIMx == TIM8)
217 {
218 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
219 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
220 }
221 #endif /* TIM8 */
222 #if defined (TIM14)
223 else if (TIMx == TIM14)
224 {
225 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
226 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
227 }
228 #endif /* TIM14 */
229 #if defined (TIM15)
230 else if (TIMx == TIM15)
231 {
232 LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM15);
233 LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM15);
234 }
235 #endif /* TIM15 */
236 #if defined (TIM16)
237 else if (TIMx == TIM16)
238 {
239 LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM16);
240 LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM16);
241 }
242 #endif /* TIM16 */
243 #if defined(TIM17)
244 else if (TIMx == TIM17)
245 {
246 LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM17);
247 LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM17);
248 }
249 #endif /* TIM17 */
250 else
251 {
252 result = ERROR;
253 }
254
255 return result;
256 }
257
258 /**
259 * @brief Set the fields of the time base unit configuration data structure
260 * to their default values.
261 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
262 * @retval None
263 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)264 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
265 {
266 /* Set the default configuration */
267 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
268 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
269 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
270 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
271 TIM_InitStruct->RepetitionCounter = 0x00000000U;
272 }
273
274 /**
275 * @brief Configure the TIMx time base unit.
276 * @param TIMx Timer Instance
277 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
278 * (TIMx time base unit configuration data structure)
279 * @retval An ErrorStatus enumeration value:
280 * - SUCCESS: TIMx registers are de-initialized
281 * - ERROR: not applicable
282 */
LL_TIM_Init(TIM_TypeDef * TIMx,const LL_TIM_InitTypeDef * TIM_InitStruct)283 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
284 {
285 uint32_t tmpcr1;
286
287 /* Check the parameters */
288 assert_param(IS_TIM_INSTANCE(TIMx));
289 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
290 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
291
292 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
293
294 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
295 {
296 /* Select the Counter Mode */
297 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
298 }
299
300 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
301 {
302 /* Set the clock division */
303 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
304 }
305
306 /* Write to TIMx CR1 */
307 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
308
309 /* Set the Autoreload value */
310 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
311
312 /* Set the Prescaler value */
313 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
314
315 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
316 {
317 /* Set the Repetition Counter value */
318 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
319 }
320
321 /* Generate an update event to reload the Prescaler
322 and the repetition counter value (if applicable) immediately */
323 LL_TIM_GenerateEvent_UPDATE(TIMx);
324
325 return SUCCESS;
326 }
327
328 /**
329 * @brief Set the fields of the TIMx output channel configuration data
330 * structure to their default values.
331 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
332 * (the output channel configuration data structure)
333 * @retval None
334 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)335 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
336 {
337 /* Set the default configuration */
338 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
339 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
340 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
341 TIM_OC_InitStruct->CompareValue = 0x00000000U;
342 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
343 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
344 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
345 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
346 }
347
348 /**
349 * @brief Configure the TIMx output channel.
350 * @param TIMx Timer Instance
351 * @param Channel This parameter can be one of the following values:
352 * @arg @ref LL_TIM_CHANNEL_CH1
353 * @arg @ref LL_TIM_CHANNEL_CH2
354 * @arg @ref LL_TIM_CHANNEL_CH3
355 * @arg @ref LL_TIM_CHANNEL_CH4
356 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
357 * data structure)
358 * @retval An ErrorStatus enumeration value:
359 * - SUCCESS: TIMx output channel is initialized
360 * - ERROR: TIMx output channel is not initialized
361 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)362 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
363 {
364 ErrorStatus result = ERROR;
365
366 switch (Channel)
367 {
368 case LL_TIM_CHANNEL_CH1:
369 result = OC1Config(TIMx, TIM_OC_InitStruct);
370 break;
371 case LL_TIM_CHANNEL_CH2:
372 result = OC2Config(TIMx, TIM_OC_InitStruct);
373 break;
374 case LL_TIM_CHANNEL_CH3:
375 result = OC3Config(TIMx, TIM_OC_InitStruct);
376 break;
377 case LL_TIM_CHANNEL_CH4:
378 result = OC4Config(TIMx, TIM_OC_InitStruct);
379 break;
380 default:
381 break;
382 }
383
384 return result;
385 }
386
387 /**
388 * @brief Set the fields of the TIMx input channel configuration data
389 * structure to their default values.
390 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
391 * data structure)
392 * @retval None
393 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)394 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
395 {
396 /* Set the default configuration */
397 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
398 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
399 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
400 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
401 }
402
403 /**
404 * @brief Configure the TIMx input channel.
405 * @param TIMx Timer Instance
406 * @param Channel This parameter can be one of the following values:
407 * @arg @ref LL_TIM_CHANNEL_CH1
408 * @arg @ref LL_TIM_CHANNEL_CH2
409 * @arg @ref LL_TIM_CHANNEL_CH3
410 * @arg @ref LL_TIM_CHANNEL_CH4
411 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
412 * structure)
413 * @retval An ErrorStatus enumeration value:
414 * - SUCCESS: TIMx output channel is initialized
415 * - ERROR: TIMx output channel is not initialized
416 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)417 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
418 {
419 ErrorStatus result = ERROR;
420
421 switch (Channel)
422 {
423 case LL_TIM_CHANNEL_CH1:
424 result = IC1Config(TIMx, TIM_IC_InitStruct);
425 break;
426 case LL_TIM_CHANNEL_CH2:
427 result = IC2Config(TIMx, TIM_IC_InitStruct);
428 break;
429 case LL_TIM_CHANNEL_CH3:
430 result = IC3Config(TIMx, TIM_IC_InitStruct);
431 break;
432 case LL_TIM_CHANNEL_CH4:
433 result = IC4Config(TIMx, TIM_IC_InitStruct);
434 break;
435 default:
436 break;
437 }
438
439 return result;
440 }
441
442 /**
443 * @brief Fills each TIM_EncoderInitStruct field with its default value
444 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
445 * configuration data structure)
446 * @retval None
447 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)448 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
449 {
450 /* Set the default configuration */
451 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
452 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
453 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
454 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
455 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
456 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
457 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
458 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
459 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
460 }
461
462 /**
463 * @brief Configure the encoder interface of the timer instance.
464 * @param TIMx Timer Instance
465 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
466 * configuration data structure)
467 * @retval An ErrorStatus enumeration value:
468 * - SUCCESS: TIMx registers are de-initialized
469 * - ERROR: not applicable
470 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,const LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)471 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
472 {
473 uint32_t tmpccmr1;
474 uint32_t tmpccer;
475
476 /* Check the parameters */
477 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
478 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
479 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
480 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
481 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
482 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
483 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
484 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
485 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
486 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
487
488 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
489 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
490
491 /* Get the TIMx CCMR1 register value */
492 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
493
494 /* Get the TIMx CCER register value */
495 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
496
497 /* Configure TI1 */
498 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
499 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
500 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
501 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
502
503 /* Configure TI2 */
504 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
505 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
506 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
507 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
508
509 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
510 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
511 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
512 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
513 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
514
515 /* Set encoder mode */
516 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
517
518 /* Write to TIMx CCMR1 */
519 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
520
521 /* Write to TIMx CCER */
522 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
523
524 return SUCCESS;
525 }
526
527 /**
528 * @brief Set the fields of the TIMx Hall sensor interface configuration data
529 * structure to their default values.
530 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
531 * configuration data structure)
532 * @retval None
533 */
LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)534 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
535 {
536 /* Set the default configuration */
537 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
538 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
539 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
540 TIM_HallSensorInitStruct->CommutationDelay = 0U;
541 }
542
543 /**
544 * @brief Configure the Hall sensor interface of the timer instance.
545 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
546 * to the TI1 input channel
547 * @note TIMx slave mode controller is configured in reset mode.
548 Selected internal trigger is TI1F_ED.
549 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
550 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
551 * between 2 changes on the inputs. It gives information about motor speed.
552 * @note Channel 2 is configured in output PWM 2 mode.
553 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
554 * @note OC2REF is selected as trigger output on TRGO.
555 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
556 * when TIMx operates in Hall sensor interface mode.
557 * @param TIMx Timer Instance
558 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
559 * interface configuration data structure)
560 * @retval An ErrorStatus enumeration value:
561 * - SUCCESS: TIMx registers are de-initialized
562 * - ERROR: not applicable
563 */
LL_TIM_HALLSENSOR_Init(TIM_TypeDef * TIMx,const LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)564 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
565 {
566 uint32_t tmpcr2;
567 uint32_t tmpccmr1;
568 uint32_t tmpccer;
569 uint32_t tmpsmcr;
570
571 /* Check the parameters */
572 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
573 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
574 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
575 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
576
577 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
578 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
579
580 /* Get the TIMx CR2 register value */
581 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
582
583 /* Get the TIMx CCMR1 register value */
584 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
585
586 /* Get the TIMx CCER register value */
587 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
588
589 /* Get the TIMx SMCR register value */
590 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
591
592 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
593 tmpcr2 |= TIM_CR2_TI1S;
594
595 /* OC2REF signal is used as trigger output (TRGO) */
596 tmpcr2 |= LL_TIM_TRGO_OC2REF;
597
598 /* Configure the slave mode controller */
599 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
600 tmpsmcr |= LL_TIM_TS_TI1F_ED;
601 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
602
603 /* Configure input channel 1 */
604 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
605 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
606 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
607 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
608
609 /* Configure input channel 2 */
610 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
611 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
612
613 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
614 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
615 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
616 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
617
618 /* Write to TIMx CR2 */
619 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
620
621 /* Write to TIMx SMCR */
622 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
623
624 /* Write to TIMx CCMR1 */
625 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
626
627 /* Write to TIMx CCER */
628 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
629
630 /* Write to TIMx CCR2 */
631 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
632
633 return SUCCESS;
634 }
635
636 /**
637 * @brief Set the fields of the Break and Dead Time configuration data structure
638 * to their default values.
639 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
640 * data structure)
641 * @retval None
642 */
LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)643 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
644 {
645 /* Set the default configuration */
646 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
647 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
648 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
649 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
650 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
651 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
652 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
653 }
654
655 /**
656 * @brief Configure the Break and Dead Time feature of the timer instance.
657 * @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked
658 * depending on the LOCK configuration, it can be necessary to configure all of
659 * them during the first write access to the TIMx_BDTR register.
660 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
661 * a timer instance provides a break input.
662 * @param TIMx Timer Instance
663 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
664 * data structure)
665 * @retval An ErrorStatus enumeration value:
666 * - SUCCESS: Break and Dead Time is initialized
667 * - ERROR: not applicable
668 */
LL_TIM_BDTR_Init(TIM_TypeDef * TIMx,const LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)669 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
670 {
671 uint32_t tmpbdtr = 0;
672
673 /* Check the parameters */
674 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
675 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
676 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
677 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
678 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
679 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
680 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
681
682 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
683 the OSSI State, the dead time value and the Automatic Output Enable Bit */
684
685 /* Set the BDTR bits */
686 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
687 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
688 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
689 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
690 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
691 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
692 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
693
694 /* Set TIMx_BDTR */
695 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
696
697 return SUCCESS;
698 }
699 /**
700 * @}
701 */
702
703 /**
704 * @}
705 */
706
707 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
708 * @brief Private functions
709 * @{
710 */
711 /**
712 * @brief Configure the TIMx output channel 1.
713 * @param TIMx Timer Instance
714 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
715 * @retval An ErrorStatus enumeration value:
716 * - SUCCESS: TIMx registers are de-initialized
717 * - ERROR: not applicable
718 */
OC1Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)719 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
720 {
721 uint32_t tmpccmr1;
722 uint32_t tmpccer;
723 uint32_t tmpcr2;
724
725 /* Check the parameters */
726 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
727 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
728 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
729 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
730
731 /* Disable the Channel 1: Reset the CC1E Bit */
732 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
733
734 /* Get the TIMx CCER register value */
735 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
736
737 /* Get the TIMx CR2 register value */
738 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
739
740 /* Get the TIMx CCMR1 register value */
741 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
742
743 /* Reset Capture/Compare selection Bits */
744 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
745
746 /* Set the Output Compare Mode */
747 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
748
749 /* Set the Output Compare Polarity */
750 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
751
752 /* Set the Output State */
753 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
754
755 if (IS_TIM_BREAK_INSTANCE(TIMx))
756 {
757 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
758 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
759 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
760 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
761
762 /* Set the complementary output Polarity */
763 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
764
765 /* Set the complementary output State */
766 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
767
768 /* Set the Output Idle state */
769 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
770
771 /* Set the complementary output Idle state */
772 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
773 }
774
775 /* Write to TIMx CR2 */
776 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
777
778 /* Write to TIMx CCMR1 */
779 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
780
781 /* Set the Capture Compare Register value */
782 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
783
784 /* Write to TIMx CCER */
785 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
786
787 return SUCCESS;
788 }
789
790 /**
791 * @brief Configure the TIMx output channel 2.
792 * @param TIMx Timer Instance
793 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
794 * @retval An ErrorStatus enumeration value:
795 * - SUCCESS: TIMx registers are de-initialized
796 * - ERROR: not applicable
797 */
OC2Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)798 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
799 {
800 uint32_t tmpccmr1;
801 uint32_t tmpccer;
802 uint32_t tmpcr2;
803
804 /* Check the parameters */
805 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
806 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
807 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
808 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
809
810 /* Disable the Channel 2: Reset the CC2E Bit */
811 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
812
813 /* Get the TIMx CCER register value */
814 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
815
816 /* Get the TIMx CR2 register value */
817 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
818
819 /* Get the TIMx CCMR1 register value */
820 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
821
822 /* Reset Capture/Compare selection Bits */
823 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
824
825 /* Select the Output Compare Mode */
826 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
827
828 /* Set the Output Compare Polarity */
829 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
830
831 /* Set the Output State */
832 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
833
834 if (IS_TIM_BREAK_INSTANCE(TIMx))
835 {
836 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
837 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
838 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
839 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
840
841 /* Set the complementary output Polarity */
842 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
843
844 /* Set the complementary output State */
845 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
846
847 /* Set the Output Idle state */
848 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
849
850 /* Set the complementary output Idle state */
851 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
852 }
853
854 /* Write to TIMx CR2 */
855 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
856
857 /* Write to TIMx CCMR1 */
858 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
859
860 /* Set the Capture Compare Register value */
861 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
862
863 /* Write to TIMx CCER */
864 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
865
866 return SUCCESS;
867 }
868
869 /**
870 * @brief Configure the TIMx output channel 3.
871 * @param TIMx Timer Instance
872 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
873 * @retval An ErrorStatus enumeration value:
874 * - SUCCESS: TIMx registers are de-initialized
875 * - ERROR: not applicable
876 */
OC3Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)877 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
878 {
879 uint32_t tmpccmr2;
880 uint32_t tmpccer;
881 uint32_t tmpcr2;
882
883 /* Check the parameters */
884 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
885 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
886 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
887 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
888
889 /* Disable the Channel 3: Reset the CC3E Bit */
890 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
891
892 /* Get the TIMx CCER register value */
893 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
894
895 /* Get the TIMx CR2 register value */
896 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
897
898 /* Get the TIMx CCMR2 register value */
899 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
900
901 /* Reset Capture/Compare selection Bits */
902 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
903
904 /* Select the Output Compare Mode */
905 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
906
907 /* Set the Output Compare Polarity */
908 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
909
910 /* Set the Output State */
911 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
912
913 if (IS_TIM_BREAK_INSTANCE(TIMx))
914 {
915 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
916 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
917 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
918 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
919
920 /* Set the complementary output Polarity */
921 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
922
923 /* Set the complementary output State */
924 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
925
926 /* Set the Output Idle state */
927 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
928
929 /* Set the complementary output Idle state */
930 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
931 }
932
933 /* Write to TIMx CR2 */
934 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
935
936 /* Write to TIMx CCMR2 */
937 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
938
939 /* Set the Capture Compare Register value */
940 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
941
942 /* Write to TIMx CCER */
943 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
944
945 return SUCCESS;
946 }
947
948 /**
949 * @brief Configure the TIMx output channel 4.
950 * @param TIMx Timer Instance
951 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
952 * @retval An ErrorStatus enumeration value:
953 * - SUCCESS: TIMx registers are de-initialized
954 * - ERROR: not applicable
955 */
OC4Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)956 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
957 {
958 uint32_t tmpccmr2;
959 uint32_t tmpccer;
960 uint32_t tmpcr2;
961
962 /* Check the parameters */
963 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
964 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
965 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
966 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
967
968 /* Disable the Channel 4: Reset the CC4E Bit */
969 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
970
971 /* Get the TIMx CCER register value */
972 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
973
974 /* Get the TIMx CR2 register value */
975 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
976
977 /* Get the TIMx CCMR2 register value */
978 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
979
980 /* Reset Capture/Compare selection Bits */
981 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
982
983 /* Select the Output Compare Mode */
984 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
985
986 /* Set the Output Compare Polarity */
987 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
988
989 /* Set the Output State */
990 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
991
992 if (IS_TIM_BREAK_INSTANCE(TIMx))
993 {
994 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
995
996 /* Set the Output Idle state */
997 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
998 }
999
1000 /* Write to TIMx CR2 */
1001 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1002
1003 /* Write to TIMx CCMR2 */
1004 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1005
1006 /* Set the Capture Compare Register value */
1007 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1008
1009 /* Write to TIMx CCER */
1010 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1011
1012 return SUCCESS;
1013 }
1014
1015 /**
1016 * @brief Configure the TIMx input channel 1.
1017 * @param TIMx Timer Instance
1018 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1019 * @retval An ErrorStatus enumeration value:
1020 * - SUCCESS: TIMx registers are de-initialized
1021 * - ERROR: not applicable
1022 */
IC1Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1023 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1024 {
1025 /* Check the parameters */
1026 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1027 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1028 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1029 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1030 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1031
1032 /* Disable the Channel 1: Reset the CC1E Bit */
1033 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1034
1035 /* Select the Input and set the filter and the prescaler value */
1036 MODIFY_REG(TIMx->CCMR1,
1037 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1038 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1039
1040 /* Select the Polarity and set the CC1E Bit */
1041 MODIFY_REG(TIMx->CCER,
1042 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1043 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1044
1045 return SUCCESS;
1046 }
1047
1048 /**
1049 * @brief Configure the TIMx input channel 2.
1050 * @param TIMx Timer Instance
1051 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1052 * @retval An ErrorStatus enumeration value:
1053 * - SUCCESS: TIMx registers are de-initialized
1054 * - ERROR: not applicable
1055 */
IC2Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1056 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1057 {
1058 /* Check the parameters */
1059 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1060 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1061 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1062 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1063 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1064
1065 /* Disable the Channel 2: Reset the CC2E Bit */
1066 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1067
1068 /* Select the Input and set the filter and the prescaler value */
1069 MODIFY_REG(TIMx->CCMR1,
1070 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1071 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1072
1073 /* Select the Polarity and set the CC2E Bit */
1074 MODIFY_REG(TIMx->CCER,
1075 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1076 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1077
1078 return SUCCESS;
1079 }
1080
1081 /**
1082 * @brief Configure the TIMx input channel 3.
1083 * @param TIMx Timer Instance
1084 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1085 * @retval An ErrorStatus enumeration value:
1086 * - SUCCESS: TIMx registers are de-initialized
1087 * - ERROR: not applicable
1088 */
IC3Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1089 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1090 {
1091 /* Check the parameters */
1092 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1093 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1094 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1095 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1096 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1097
1098 /* Disable the Channel 3: Reset the CC3E Bit */
1099 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1100
1101 /* Select the Input and set the filter and the prescaler value */
1102 MODIFY_REG(TIMx->CCMR2,
1103 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1104 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1105
1106 /* Select the Polarity and set the CC3E Bit */
1107 MODIFY_REG(TIMx->CCER,
1108 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1109 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1110
1111 return SUCCESS;
1112 }
1113
1114 /**
1115 * @brief Configure the TIMx input channel 4.
1116 * @param TIMx Timer Instance
1117 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1118 * @retval An ErrorStatus enumeration value:
1119 * - SUCCESS: TIMx registers are de-initialized
1120 * - ERROR: not applicable
1121 */
IC4Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1122 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1123 {
1124 /* Check the parameters */
1125 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1126 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1127 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1128 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1129 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1130
1131 /* Disable the Channel 4: Reset the CC4E Bit */
1132 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1133
1134 /* Select the Input and set the filter and the prescaler value */
1135 MODIFY_REG(TIMx->CCMR2,
1136 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1137 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1138
1139 /* Select the Polarity and set the CC4E Bit */
1140 MODIFY_REG(TIMx->CCER,
1141 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1142 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1143
1144 return SUCCESS;
1145 }
1146
1147
1148 /**
1149 * @}
1150 */
1151
1152 /**
1153 * @}
1154 */
1155
1156 #endif /* TIM1 || TIM2 || TIM3 || TIM14 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */
1157
1158 /**
1159 * @}
1160 */
1161
1162 #endif /* USE_FULL_LL_DRIVER */
1163
1164
