1 /**
2 ******************************************************************************
3 * @file stm32f0xx_hal_spi.c
4 * @author MCD Application Team
5 * @brief SPI HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2016 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 ==============================================================================
25 ##### How to use this driver #####
26 ==============================================================================
27 [..]
28 The SPI HAL driver can be used as follows:
29
30 (#) Declare a SPI_HandleTypeDef handle structure, for example:
31 SPI_HandleTypeDef hspi;
32
33 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
34 (##) Enable the SPIx interface clock
35 (##) SPI pins configuration
36 (+++) Enable the clock for the SPI GPIOs
37 (+++) Configure these SPI pins as alternate function push-pull
38 (##) NVIC configuration if you need to use interrupt process
39 (+++) Configure the SPIx interrupt priority
40 (+++) Enable the NVIC SPI IRQ handle
41 (##) DMA Configuration if you need to use DMA process
42 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
43 (+++) Enable the DMAx clock
44 (+++) Configure the DMA handle parameters
45 (+++) Configure the DMA Tx or Rx Stream/Channel
46 (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle
47 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
48
49 (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
50 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
51
52 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
53 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
54 by calling the customized HAL_SPI_MspInit() API.
55 [..]
56 Circular mode restriction:
57 (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
58 (##) Master 2Lines RxOnly
59 (##) Master 1Line Rx
60 (#) The CRC feature is not managed when the DMA circular mode is enabled
61 (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
62 the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
63 [..]
64 Master Receive mode restriction:
65 (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
66 bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
67 does not initiate a new transfer the following procedure has to be respected:
68 (##) HAL_SPI_DeInit()
69 (##) HAL_SPI_Init()
70 [..]
71 Callback registration:
72
73 (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
74 allows the user to configure dynamically the driver callbacks.
75 Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
76
77 Function HAL_SPI_RegisterCallback() allows to register following callbacks:
78 (++) TxCpltCallback : SPI Tx Completed callback
79 (++) RxCpltCallback : SPI Rx Completed callback
80 (++) TxRxCpltCallback : SPI TxRx Completed callback
81 (++) TxHalfCpltCallback : SPI Tx Half Completed callback
82 (++) RxHalfCpltCallback : SPI Rx Half Completed callback
83 (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
84 (++) ErrorCallback : SPI Error callback
85 (++) AbortCpltCallback : SPI Abort callback
86 (++) MspInitCallback : SPI Msp Init callback
87 (++) MspDeInitCallback : SPI Msp DeInit callback
88 This function takes as parameters the HAL peripheral handle, the Callback ID
89 and a pointer to the user callback function.
90
91
92 (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
93 weak function.
94 HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
95 and the Callback ID.
96 This function allows to reset following callbacks:
97 (++) TxCpltCallback : SPI Tx Completed callback
98 (++) RxCpltCallback : SPI Rx Completed callback
99 (++) TxRxCpltCallback : SPI TxRx Completed callback
100 (++) TxHalfCpltCallback : SPI Tx Half Completed callback
101 (++) RxHalfCpltCallback : SPI Rx Half Completed callback
102 (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
103 (++) ErrorCallback : SPI Error callback
104 (++) AbortCpltCallback : SPI Abort callback
105 (++) MspInitCallback : SPI Msp Init callback
106 (++) MspDeInitCallback : SPI Msp DeInit callback
107
108 [..]
109 By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
110 all callbacks are set to the corresponding weak functions:
111 examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
112 Exception done for MspInit and MspDeInit functions that are
113 reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
114 these callbacks are null (not registered beforehand).
115 If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
116 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
117
118 [..]
119 Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
120 Exception done MspInit/MspDeInit functions that can be registered/unregistered
121 in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
122 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
123 Then, the user first registers the MspInit/MspDeInit user callbacks
124 using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
125 or HAL_SPI_Init() function.
126
127 [..]
128 When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
129 not defined, the callback registering feature is not available
130 and weak (surcharged) callbacks are used.
131
132 [..]
133 Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
134 the following table resume the max SPI frequency reached with data size 8bits/16bits,
135 according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
136
137 @endverbatim
138
139 Additional table :
140
141 DataSize = SPI_DATASIZE_8BIT:
142 +----------------------------------------------------------------------------------------------+
143 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
144 | Process | Transfer mode |---------------------|----------------------|----------------------|
145 | | | Master | Slave | Master | Slave | Master | Slave |
146 |==============================================================================================|
147 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
148 | X |----------------|----------|----------|-----------|----------|-----------|----------|
149 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
150 | R |----------------|----------|----------|-----------|----------|-----------|----------|
151 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
152 |=========|================|==========|==========|===========|==========|===========|==========|
153 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
154 | |----------------|----------|----------|-----------|----------|-----------|----------|
155 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
156 | X |----------------|----------|----------|-----------|----------|-----------|----------|
157 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
158 |=========|================|==========|==========|===========|==========|===========|==========|
159 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
160 | |----------------|----------|----------|-----------|----------|-----------|----------|
161 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
162 | X |----------------|----------|----------|-----------|----------|-----------|----------|
163 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
164 +----------------------------------------------------------------------------------------------+
165
166 DataSize = SPI_DATASIZE_16BIT:
167 +----------------------------------------------------------------------------------------------+
168 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
169 | Process | Transfer mode |---------------------|----------------------|----------------------|
170 | | | Master | Slave | Master | Slave | Master | Slave |
171 |==============================================================================================|
172 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
173 | X |----------------|----------|----------|-----------|----------|-----------|----------|
174 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
175 | R |----------------|----------|----------|-----------|----------|-----------|----------|
176 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
177 |=========|================|==========|==========|===========|==========|===========|==========|
178 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
179 | |----------------|----------|----------|-----------|----------|-----------|----------|
180 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
181 | X |----------------|----------|----------|-----------|----------|-----------|----------|
182 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
183 |=========|================|==========|==========|===========|==========|===========|==========|
184 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
185 | |----------------|----------|----------|-----------|----------|-----------|----------|
186 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
187 | X |----------------|----------|----------|-----------|----------|-----------|----------|
188 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
189 +----------------------------------------------------------------------------------------------+
190 @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
191 SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
192 @note
193 (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
194 (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
195 (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
196
197 */
198
199 /* Includes ------------------------------------------------------------------*/
200 #include "stm32f0xx_hal.h"
201
202 /** @addtogroup STM32F0xx_HAL_Driver
203 * @{
204 */
205
206 /** @defgroup SPI SPI
207 * @brief SPI HAL module driver
208 * @{
209 */
210 #ifdef HAL_SPI_MODULE_ENABLED
211
212 /* Private typedef -----------------------------------------------------------*/
213 /* Private defines -----------------------------------------------------------*/
214 /** @defgroup SPI_Private_Constants SPI Private Constants
215 * @{
216 */
217 #define SPI_DEFAULT_TIMEOUT 100U
218 /**
219 * @}
220 */
221
222 /* Private macros ------------------------------------------------------------*/
223 /* Private variables ---------------------------------------------------------*/
224 /* Private function prototypes -----------------------------------------------*/
225 /** @defgroup SPI_Private_Functions SPI Private Functions
226 * @{
227 */
228 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
229 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
230 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
231 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
232 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
233 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
234 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
235 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
236 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
237 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
238 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
239 uint32_t Timeout, uint32_t Tickstart);
240 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
241 uint32_t Timeout, uint32_t Tickstart);
242 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
243 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
244 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
245 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
246 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
247 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
248 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
249 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
250 #if (USE_SPI_CRC != 0U)
251 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
252 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
253 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
254 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
255 #endif /* USE_SPI_CRC */
256 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
257 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
258 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
259 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
260 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
261 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
262 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
263 /**
264 * @}
265 */
266
267 /* Exported functions --------------------------------------------------------*/
268 /** @defgroup SPI_Exported_Functions SPI Exported Functions
269 * @{
270 */
271
272 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
273 * @brief Initialization and Configuration functions
274 *
275 @verbatim
276 ===============================================================================
277 ##### Initialization and de-initialization functions #####
278 ===============================================================================
279 [..] This subsection provides a set of functions allowing to initialize and
280 de-initialize the SPIx peripheral:
281
282 (+) User must implement HAL_SPI_MspInit() function in which he configures
283 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
284
285 (+) Call the function HAL_SPI_Init() to configure the selected device with
286 the selected configuration:
287 (++) Mode
288 (++) Direction
289 (++) Data Size
290 (++) Clock Polarity and Phase
291 (++) NSS Management
292 (++) BaudRate Prescaler
293 (++) FirstBit
294 (++) TIMode
295 (++) CRC Calculation
296 (++) CRC Polynomial if CRC enabled
297 (++) CRC Length, used only with Data8 and Data16
298 (++) FIFO reception threshold
299
300 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
301 of the selected SPIx peripheral.
302
303 @endverbatim
304 * @{
305 */
306
307 /**
308 * @brief Initialize the SPI according to the specified parameters
309 * in the SPI_InitTypeDef and initialize the associated handle.
310 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
311 * the configuration information for SPI module.
312 * @retval HAL status
313 */
HAL_SPI_Init(SPI_HandleTypeDef * hspi)314 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
315 {
316 uint32_t frxth;
317
318 /* Check the SPI handle allocation */
319 if (hspi == NULL)
320 {
321 return HAL_ERROR;
322 }
323
324 /* Check the parameters */
325 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
326 assert_param(IS_SPI_MODE(hspi->Init.Mode));
327 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
328 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
329 assert_param(IS_SPI_NSS(hspi->Init.NSS));
330 assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
331 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
332 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
333 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
334 if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
335 {
336 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
337 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
338
339 if (hspi->Init.Mode == SPI_MODE_MASTER)
340 {
341 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
342 }
343 else
344 {
345 /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
346 hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
347 }
348 }
349 else
350 {
351 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
352
353 /* Force polarity and phase to TI protocaol requirements */
354 hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
355 hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
356 }
357 #if (USE_SPI_CRC != 0U)
358 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
359 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
360 {
361 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
362 assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
363 }
364 #else
365 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
366 #endif /* USE_SPI_CRC */
367
368 if (hspi->State == HAL_SPI_STATE_RESET)
369 {
370 /* Allocate lock resource and initialize it */
371 hspi->Lock = HAL_UNLOCKED;
372
373 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
374 /* Init the SPI Callback settings */
375 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
376 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
377 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
378 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
379 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
380 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
381 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
382 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
383
384 if (hspi->MspInitCallback == NULL)
385 {
386 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
387 }
388
389 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
390 hspi->MspInitCallback(hspi);
391 #else
392 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
393 HAL_SPI_MspInit(hspi);
394 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
395 }
396
397 hspi->State = HAL_SPI_STATE_BUSY;
398
399 /* Disable the selected SPI peripheral */
400 __HAL_SPI_DISABLE(hspi);
401
402 /* Align by default the rs fifo threshold on the data size */
403 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
404 {
405 frxth = SPI_RXFIFO_THRESHOLD_HF;
406 }
407 else
408 {
409 frxth = SPI_RXFIFO_THRESHOLD_QF;
410 }
411
412 /* CRC calculation is valid only for 16Bit and 8 Bit */
413 if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
414 {
415 /* CRC must be disabled */
416 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
417 }
418
419 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
420 /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
421 Communication speed, First bit and CRC calculation state */
422 WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
423 (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) |
424 (hspi->Init.CLKPolarity & SPI_CR1_CPOL) |
425 (hspi->Init.CLKPhase & SPI_CR1_CPHA) |
426 (hspi->Init.NSS & SPI_CR1_SSM) |
427 (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
428 (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
429 (hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
430 #if (USE_SPI_CRC != 0U)
431 /*---------------------------- SPIx CRCL Configuration -------------------*/
432 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
433 {
434 /* Align the CRC Length on the data size */
435 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
436 {
437 /* CRC Length aligned on the data size : value set by default */
438 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
439 {
440 hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
441 }
442 else
443 {
444 hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
445 }
446 }
447
448 /* Configure : CRC Length */
449 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
450 {
451 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCL);
452 }
453 }
454 #endif /* USE_SPI_CRC */
455
456 /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
457 WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
458 (hspi->Init.TIMode & SPI_CR2_FRF) |
459 (hspi->Init.NSSPMode & SPI_CR2_NSSP) |
460 (hspi->Init.DataSize & SPI_CR2_DS_Msk) |
461 (frxth & SPI_CR2_FRXTH)));
462
463 #if (USE_SPI_CRC != 0U)
464 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
465 /* Configure : CRC Polynomial */
466 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
467 {
468 WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk));
469 }
470 #endif /* USE_SPI_CRC */
471
472 #if defined(SPI_I2SCFGR_I2SMOD)
473 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
474 CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
475 #endif /* SPI_I2SCFGR_I2SMOD */
476
477 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
478 hspi->State = HAL_SPI_STATE_READY;
479
480 return HAL_OK;
481 }
482
483 /**
484 * @brief De-Initialize the SPI peripheral.
485 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
486 * the configuration information for SPI module.
487 * @retval HAL status
488 */
HAL_SPI_DeInit(SPI_HandleTypeDef * hspi)489 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
490 {
491 /* Check the SPI handle allocation */
492 if (hspi == NULL)
493 {
494 return HAL_ERROR;
495 }
496
497 /* Check SPI Instance parameter */
498 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
499
500 hspi->State = HAL_SPI_STATE_BUSY;
501
502 /* Disable the SPI Peripheral Clock */
503 __HAL_SPI_DISABLE(hspi);
504
505 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
506 if (hspi->MspDeInitCallback == NULL)
507 {
508 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
509 }
510
511 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
512 hspi->MspDeInitCallback(hspi);
513 #else
514 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
515 HAL_SPI_MspDeInit(hspi);
516 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
517
518 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
519 hspi->State = HAL_SPI_STATE_RESET;
520
521 /* Release Lock */
522 __HAL_UNLOCK(hspi);
523
524 return HAL_OK;
525 }
526
527 /**
528 * @brief Initialize the SPI MSP.
529 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
530 * the configuration information for SPI module.
531 * @retval None
532 */
HAL_SPI_MspInit(SPI_HandleTypeDef * hspi)533 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
534 {
535 /* Prevent unused argument(s) compilation warning */
536 UNUSED(hspi);
537
538 /* NOTE : This function should not be modified, when the callback is needed,
539 the HAL_SPI_MspInit should be implemented in the user file
540 */
541 }
542
543 /**
544 * @brief De-Initialize the SPI MSP.
545 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
546 * the configuration information for SPI module.
547 * @retval None
548 */
HAL_SPI_MspDeInit(SPI_HandleTypeDef * hspi)549 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
550 {
551 /* Prevent unused argument(s) compilation warning */
552 UNUSED(hspi);
553
554 /* NOTE : This function should not be modified, when the callback is needed,
555 the HAL_SPI_MspDeInit should be implemented in the user file
556 */
557 }
558
559 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
560 /**
561 * @brief Register a User SPI Callback
562 * To be used instead of the weak predefined callback
563 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
564 * the configuration information for the specified SPI.
565 * @param CallbackID ID of the callback to be registered
566 * @param pCallback pointer to the Callback function
567 * @retval HAL status
568 */
HAL_SPI_RegisterCallback(SPI_HandleTypeDef * hspi,HAL_SPI_CallbackIDTypeDef CallbackID,pSPI_CallbackTypeDef pCallback)569 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
570 pSPI_CallbackTypeDef pCallback)
571 {
572 HAL_StatusTypeDef status = HAL_OK;
573
574 if (pCallback == NULL)
575 {
576 /* Update the error code */
577 hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
578
579 return HAL_ERROR;
580 }
581 /* Process locked */
582 __HAL_LOCK(hspi);
583
584 if (HAL_SPI_STATE_READY == hspi->State)
585 {
586 switch (CallbackID)
587 {
588 case HAL_SPI_TX_COMPLETE_CB_ID :
589 hspi->TxCpltCallback = pCallback;
590 break;
591
592 case HAL_SPI_RX_COMPLETE_CB_ID :
593 hspi->RxCpltCallback = pCallback;
594 break;
595
596 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
597 hspi->TxRxCpltCallback = pCallback;
598 break;
599
600 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
601 hspi->TxHalfCpltCallback = pCallback;
602 break;
603
604 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
605 hspi->RxHalfCpltCallback = pCallback;
606 break;
607
608 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
609 hspi->TxRxHalfCpltCallback = pCallback;
610 break;
611
612 case HAL_SPI_ERROR_CB_ID :
613 hspi->ErrorCallback = pCallback;
614 break;
615
616 case HAL_SPI_ABORT_CB_ID :
617 hspi->AbortCpltCallback = pCallback;
618 break;
619
620 case HAL_SPI_MSPINIT_CB_ID :
621 hspi->MspInitCallback = pCallback;
622 break;
623
624 case HAL_SPI_MSPDEINIT_CB_ID :
625 hspi->MspDeInitCallback = pCallback;
626 break;
627
628 default :
629 /* Update the error code */
630 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
631
632 /* Return error status */
633 status = HAL_ERROR;
634 break;
635 }
636 }
637 else if (HAL_SPI_STATE_RESET == hspi->State)
638 {
639 switch (CallbackID)
640 {
641 case HAL_SPI_MSPINIT_CB_ID :
642 hspi->MspInitCallback = pCallback;
643 break;
644
645 case HAL_SPI_MSPDEINIT_CB_ID :
646 hspi->MspDeInitCallback = pCallback;
647 break;
648
649 default :
650 /* Update the error code */
651 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
652
653 /* Return error status */
654 status = HAL_ERROR;
655 break;
656 }
657 }
658 else
659 {
660 /* Update the error code */
661 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
662
663 /* Return error status */
664 status = HAL_ERROR;
665 }
666
667 /* Release Lock */
668 __HAL_UNLOCK(hspi);
669 return status;
670 }
671
672 /**
673 * @brief Unregister an SPI Callback
674 * SPI callback is redirected to the weak predefined callback
675 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
676 * the configuration information for the specified SPI.
677 * @param CallbackID ID of the callback to be unregistered
678 * @retval HAL status
679 */
HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef * hspi,HAL_SPI_CallbackIDTypeDef CallbackID)680 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
681 {
682 HAL_StatusTypeDef status = HAL_OK;
683
684 /* Process locked */
685 __HAL_LOCK(hspi);
686
687 if (HAL_SPI_STATE_READY == hspi->State)
688 {
689 switch (CallbackID)
690 {
691 case HAL_SPI_TX_COMPLETE_CB_ID :
692 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
693 break;
694
695 case HAL_SPI_RX_COMPLETE_CB_ID :
696 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
697 break;
698
699 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
700 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
701 break;
702
703 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
704 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
705 break;
706
707 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
708 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
709 break;
710
711 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
712 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
713 break;
714
715 case HAL_SPI_ERROR_CB_ID :
716 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
717 break;
718
719 case HAL_SPI_ABORT_CB_ID :
720 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
721 break;
722
723 case HAL_SPI_MSPINIT_CB_ID :
724 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
725 break;
726
727 case HAL_SPI_MSPDEINIT_CB_ID :
728 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
729 break;
730
731 default :
732 /* Update the error code */
733 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
734
735 /* Return error status */
736 status = HAL_ERROR;
737 break;
738 }
739 }
740 else if (HAL_SPI_STATE_RESET == hspi->State)
741 {
742 switch (CallbackID)
743 {
744 case HAL_SPI_MSPINIT_CB_ID :
745 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
746 break;
747
748 case HAL_SPI_MSPDEINIT_CB_ID :
749 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
750 break;
751
752 default :
753 /* Update the error code */
754 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
755
756 /* Return error status */
757 status = HAL_ERROR;
758 break;
759 }
760 }
761 else
762 {
763 /* Update the error code */
764 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
765
766 /* Return error status */
767 status = HAL_ERROR;
768 }
769
770 /* Release Lock */
771 __HAL_UNLOCK(hspi);
772 return status;
773 }
774 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
775 /**
776 * @}
777 */
778
779 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
780 * @brief Data transfers functions
781 *
782 @verbatim
783 ==============================================================================
784 ##### IO operation functions #####
785 ===============================================================================
786 [..]
787 This subsection provides a set of functions allowing to manage the SPI
788 data transfers.
789
790 [..] The SPI supports master and slave mode :
791
792 (#) There are two modes of transfer:
793 (++) Blocking mode: The communication is performed in polling mode.
794 The HAL status of all data processing is returned by the same function
795 after finishing transfer.
796 (++) No-Blocking mode: The communication is performed using Interrupts
797 or DMA, These APIs return the HAL status.
798 The end of the data processing will be indicated through the
799 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
800 using DMA mode.
801 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
802 will be executed respectively at the end of the transmit or Receive process
803 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
804
805 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
806 exist for 1Line (simplex) and 2Lines (full duplex) modes.
807
808 @endverbatim
809 * @{
810 */
811
812 /**
813 * @brief Transmit an amount of data in blocking mode.
814 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
815 * the configuration information for SPI module.
816 * @param pData pointer to data buffer
817 * @param Size amount of data to be sent
818 * @param Timeout Timeout duration
819 * @retval HAL status
820 */
HAL_SPI_Transmit(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size,uint32_t Timeout)821 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
822 {
823 uint32_t tickstart;
824 HAL_StatusTypeDef errorcode = HAL_OK;
825 uint16_t initial_TxXferCount;
826
827 /* Check Direction parameter */
828 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
829
830 /* Process Locked */
831 __HAL_LOCK(hspi);
832
833 /* Init tickstart for timeout management*/
834 tickstart = HAL_GetTick();
835 initial_TxXferCount = Size;
836
837 if (hspi->State != HAL_SPI_STATE_READY)
838 {
839 errorcode = HAL_BUSY;
840 goto error;
841 }
842
843 if ((pData == NULL) || (Size == 0U))
844 {
845 errorcode = HAL_ERROR;
846 goto error;
847 }
848
849 /* Set the transaction information */
850 hspi->State = HAL_SPI_STATE_BUSY_TX;
851 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
852 hspi->pTxBuffPtr = (uint8_t *)pData;
853 hspi->TxXferSize = Size;
854 hspi->TxXferCount = Size;
855
856 /*Init field not used in handle to zero */
857 hspi->pRxBuffPtr = (uint8_t *)NULL;
858 hspi->RxXferSize = 0U;
859 hspi->RxXferCount = 0U;
860 hspi->TxISR = NULL;
861 hspi->RxISR = NULL;
862
863 /* Configure communication direction : 1Line */
864 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
865 {
866 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
867 __HAL_SPI_DISABLE(hspi);
868 SPI_1LINE_TX(hspi);
869 }
870
871 #if (USE_SPI_CRC != 0U)
872 /* Reset CRC Calculation */
873 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
874 {
875 SPI_RESET_CRC(hspi);
876 }
877 #endif /* USE_SPI_CRC */
878
879 /* Check if the SPI is already enabled */
880 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
881 {
882 /* Enable SPI peripheral */
883 __HAL_SPI_ENABLE(hspi);
884 }
885
886 /* Transmit data in 16 Bit mode */
887 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
888 {
889 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
890 {
891 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
892 hspi->pTxBuffPtr += sizeof(uint16_t);
893 hspi->TxXferCount--;
894 }
895 /* Transmit data in 16 Bit mode */
896 while (hspi->TxXferCount > 0U)
897 {
898 /* Wait until TXE flag is set to send data */
899 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
900 {
901 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
902 hspi->pTxBuffPtr += sizeof(uint16_t);
903 hspi->TxXferCount--;
904 }
905 else
906 {
907 /* Timeout management */
908 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
909 {
910 errorcode = HAL_TIMEOUT;
911 hspi->State = HAL_SPI_STATE_READY;
912 goto error;
913 }
914 }
915 }
916 }
917 /* Transmit data in 8 Bit mode */
918 else
919 {
920 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
921 {
922 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
923 hspi->pTxBuffPtr += sizeof(uint8_t);
924 hspi->TxXferCount--;
925 }
926 while (hspi->TxXferCount > 0U)
927 {
928 /* Wait until TXE flag is set to send data */
929 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
930 {
931 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
932 hspi->pTxBuffPtr += sizeof(uint8_t);
933 hspi->TxXferCount--;
934 }
935 else
936 {
937 /* Timeout management */
938 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
939 {
940 errorcode = HAL_TIMEOUT;
941 hspi->State = HAL_SPI_STATE_READY;
942 goto error;
943 }
944 }
945 }
946 }
947 #if (USE_SPI_CRC != 0U)
948 /* Enable CRC Transmission */
949 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
950 {
951 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
952 }
953 #endif /* USE_SPI_CRC */
954
955 /* Check the end of the transaction */
956 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
957 {
958 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
959 }
960
961 /* Clear overrun flag in 2 Lines communication mode because received is not read */
962 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
963 {
964 __HAL_SPI_CLEAR_OVRFLAG(hspi);
965 }
966
967 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
968 {
969 errorcode = HAL_ERROR;
970 }
971 else
972 {
973 hspi->State = HAL_SPI_STATE_READY;
974 }
975
976 error:
977 /* Process Unlocked */
978 __HAL_UNLOCK(hspi);
979 return errorcode;
980 }
981
982 /**
983 * @brief Receive an amount of data in blocking mode.
984 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
985 * the configuration information for SPI module.
986 * @param pData pointer to data buffer
987 * @param Size amount of data to be received
988 * @param Timeout Timeout duration
989 * @retval HAL status
990 */
HAL_SPI_Receive(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size,uint32_t Timeout)991 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
992 {
993 #if (USE_SPI_CRC != 0U)
994 __IO uint32_t tmpreg = 0U;
995 __IO uint8_t *ptmpreg8;
996 __IO uint8_t tmpreg8 = 0;
997 #endif /* USE_SPI_CRC */
998 uint32_t tickstart;
999 HAL_StatusTypeDef errorcode = HAL_OK;
1000
1001 if (hspi->State != HAL_SPI_STATE_READY)
1002 {
1003 errorcode = HAL_BUSY;
1004 goto error;
1005 }
1006
1007 if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
1008 {
1009 hspi->State = HAL_SPI_STATE_BUSY_RX;
1010 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1011 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
1012 }
1013
1014 /* Process Locked */
1015 __HAL_LOCK(hspi);
1016
1017 /* Init tickstart for timeout management*/
1018 tickstart = HAL_GetTick();
1019
1020 if ((pData == NULL) || (Size == 0U))
1021 {
1022 errorcode = HAL_ERROR;
1023 goto error;
1024 }
1025
1026 /* Set the transaction information */
1027 hspi->State = HAL_SPI_STATE_BUSY_RX;
1028 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1029 hspi->pRxBuffPtr = (uint8_t *)pData;
1030 hspi->RxXferSize = Size;
1031 hspi->RxXferCount = Size;
1032
1033 /*Init field not used in handle to zero */
1034 hspi->pTxBuffPtr = (uint8_t *)NULL;
1035 hspi->TxXferSize = 0U;
1036 hspi->TxXferCount = 0U;
1037 hspi->RxISR = NULL;
1038 hspi->TxISR = NULL;
1039
1040 #if (USE_SPI_CRC != 0U)
1041 /* Reset CRC Calculation */
1042 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1043 {
1044 SPI_RESET_CRC(hspi);
1045 /* this is done to handle the CRCNEXT before the latest data */
1046 hspi->RxXferCount--;
1047 }
1048 #endif /* USE_SPI_CRC */
1049
1050 /* Set the Rx Fifo threshold */
1051 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1052 {
1053 /* Set RX Fifo threshold according the reception data length: 16bit */
1054 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1055 }
1056 else
1057 {
1058 /* Set RX Fifo threshold according the reception data length: 8bit */
1059 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1060 }
1061
1062 /* Configure communication direction: 1Line */
1063 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1064 {
1065 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1066 __HAL_SPI_DISABLE(hspi);
1067 SPI_1LINE_RX(hspi);
1068 }
1069
1070 /* Check if the SPI is already enabled */
1071 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1072 {
1073 /* Enable SPI peripheral */
1074 __HAL_SPI_ENABLE(hspi);
1075 }
1076
1077 /* Receive data in 8 Bit mode */
1078 if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
1079 {
1080 /* Transfer loop */
1081 while (hspi->RxXferCount > 0U)
1082 {
1083 /* Check the RXNE flag */
1084 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1085 {
1086 /* read the received data */
1087 (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1088 hspi->pRxBuffPtr += sizeof(uint8_t);
1089 hspi->RxXferCount--;
1090 }
1091 else
1092 {
1093 /* Timeout management */
1094 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1095 {
1096 errorcode = HAL_TIMEOUT;
1097 hspi->State = HAL_SPI_STATE_READY;
1098 goto error;
1099 }
1100 }
1101 }
1102 }
1103 else
1104 {
1105 /* Transfer loop */
1106 while (hspi->RxXferCount > 0U)
1107 {
1108 /* Check the RXNE flag */
1109 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1110 {
1111 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1112 hspi->pRxBuffPtr += sizeof(uint16_t);
1113 hspi->RxXferCount--;
1114 }
1115 else
1116 {
1117 /* Timeout management */
1118 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1119 {
1120 errorcode = HAL_TIMEOUT;
1121 hspi->State = HAL_SPI_STATE_READY;
1122 goto error;
1123 }
1124 }
1125 }
1126 }
1127
1128 #if (USE_SPI_CRC != 0U)
1129 /* Handle the CRC Transmission */
1130 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1131 {
1132 /* freeze the CRC before the latest data */
1133 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1134
1135 /* Read the latest data */
1136 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1137 {
1138 /* the latest data has not been received */
1139 errorcode = HAL_TIMEOUT;
1140 goto error;
1141 }
1142
1143 /* Receive last data in 16 Bit mode */
1144 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1145 {
1146 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1147 }
1148 /* Receive last data in 8 Bit mode */
1149 else
1150 {
1151 (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1152 }
1153
1154 /* Wait the CRC data */
1155 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1156 {
1157 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1158 errorcode = HAL_TIMEOUT;
1159 goto error;
1160 }
1161
1162 /* Read CRC to Flush DR and RXNE flag */
1163 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1164 {
1165 /* Read 16bit CRC */
1166 tmpreg = READ_REG(hspi->Instance->DR);
1167 /* To avoid GCC warning */
1168 UNUSED(tmpreg);
1169 }
1170 else
1171 {
1172 /* Initialize the 8bit temporary pointer */
1173 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
1174 /* Read 8bit CRC */
1175 tmpreg8 = *ptmpreg8;
1176 /* To avoid GCC warning */
1177 UNUSED(tmpreg8);
1178
1179 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1180 {
1181 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1182 {
1183 /* Error on the CRC reception */
1184 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1185 errorcode = HAL_TIMEOUT;
1186 goto error;
1187 }
1188 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
1189 tmpreg8 = *ptmpreg8;
1190 /* To avoid GCC warning */
1191 UNUSED(tmpreg8);
1192 }
1193 }
1194 }
1195 #endif /* USE_SPI_CRC */
1196
1197 /* Check the end of the transaction */
1198 if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1199 {
1200 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1201 }
1202
1203 #if (USE_SPI_CRC != 0U)
1204 /* Check if CRC error occurred */
1205 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1206 {
1207 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1208 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1209 }
1210 #endif /* USE_SPI_CRC */
1211
1212 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1213 {
1214 errorcode = HAL_ERROR;
1215 }
1216 else
1217 {
1218 hspi->State = HAL_SPI_STATE_READY;
1219 }
1220
1221 error :
1222 __HAL_UNLOCK(hspi);
1223 return errorcode;
1224 }
1225
1226 /**
1227 * @brief Transmit and Receive an amount of data in blocking mode.
1228 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1229 * the configuration information for SPI module.
1230 * @param pTxData pointer to transmission data buffer
1231 * @param pRxData pointer to reception data buffer
1232 * @param Size amount of data to be sent and received
1233 * @param Timeout Timeout duration
1234 * @retval HAL status
1235 */
HAL_SPI_TransmitReceive(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size,uint32_t Timeout)1236 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
1237 uint32_t Timeout)
1238 {
1239 uint16_t initial_TxXferCount;
1240 uint32_t tmp_mode;
1241 HAL_SPI_StateTypeDef tmp_state;
1242 uint32_t tickstart;
1243 #if (USE_SPI_CRC != 0U)
1244 __IO uint32_t tmpreg = 0U;
1245 uint32_t spi_cr1;
1246 uint32_t spi_cr2;
1247 __IO uint8_t *ptmpreg8;
1248 __IO uint8_t tmpreg8 = 0;
1249 #endif /* USE_SPI_CRC */
1250
1251 /* Variable used to alternate Rx and Tx during transfer */
1252 uint32_t txallowed = 1U;
1253 HAL_StatusTypeDef errorcode = HAL_OK;
1254
1255 /* Check Direction parameter */
1256 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1257
1258 /* Process Locked */
1259 __HAL_LOCK(hspi);
1260
1261 /* Init tickstart for timeout management*/
1262 tickstart = HAL_GetTick();
1263
1264 /* Init temporary variables */
1265 tmp_state = hspi->State;
1266 tmp_mode = hspi->Init.Mode;
1267 initial_TxXferCount = Size;
1268 #if (USE_SPI_CRC != 0U)
1269 spi_cr1 = READ_REG(hspi->Instance->CR1);
1270 spi_cr2 = READ_REG(hspi->Instance->CR2);
1271 #endif /* USE_SPI_CRC */
1272
1273 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1274 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1275 {
1276 errorcode = HAL_BUSY;
1277 goto error;
1278 }
1279
1280 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1281 {
1282 errorcode = HAL_ERROR;
1283 goto error;
1284 }
1285
1286 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1287 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1288 {
1289 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1290 }
1291
1292 /* Set the transaction information */
1293 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1294 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1295 hspi->RxXferCount = Size;
1296 hspi->RxXferSize = Size;
1297 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1298 hspi->TxXferCount = Size;
1299 hspi->TxXferSize = Size;
1300
1301 /*Init field not used in handle to zero */
1302 hspi->RxISR = NULL;
1303 hspi->TxISR = NULL;
1304
1305 #if (USE_SPI_CRC != 0U)
1306 /* Reset CRC Calculation */
1307 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1308 {
1309 SPI_RESET_CRC(hspi);
1310 }
1311 #endif /* USE_SPI_CRC */
1312
1313 /* Set the Rx Fifo threshold */
1314 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1315 {
1316 /* Set fiforxthreshold according the reception data length: 16bit */
1317 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1318 }
1319 else
1320 {
1321 /* Set fiforxthreshold according the reception data length: 8bit */
1322 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1323 }
1324
1325 /* Check if the SPI is already enabled */
1326 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1327 {
1328 /* Enable SPI peripheral */
1329 __HAL_SPI_ENABLE(hspi);
1330 }
1331
1332 /* Transmit and Receive data in 16 Bit mode */
1333 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1334 {
1335 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1336 {
1337 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1338 hspi->pTxBuffPtr += sizeof(uint16_t);
1339 hspi->TxXferCount--;
1340
1341 #if (USE_SPI_CRC != 0U)
1342 /* Enable CRC Transmission */
1343 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1344 {
1345 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
1346 if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
1347 {
1348 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
1349 }
1350 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1351 }
1352 #endif /* USE_SPI_CRC */
1353
1354 }
1355 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1356 {
1357 /* Check TXE flag */
1358 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1359 {
1360 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1361 hspi->pTxBuffPtr += sizeof(uint16_t);
1362 hspi->TxXferCount--;
1363 /* Next Data is a reception (Rx). Tx not allowed */
1364 txallowed = 0U;
1365
1366 #if (USE_SPI_CRC != 0U)
1367 /* Enable CRC Transmission */
1368 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1369 {
1370 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
1371 if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
1372 {
1373 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
1374 }
1375 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1376 }
1377 #endif /* USE_SPI_CRC */
1378 }
1379
1380 /* Check RXNE flag */
1381 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1382 {
1383 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1384 hspi->pRxBuffPtr += sizeof(uint16_t);
1385 hspi->RxXferCount--;
1386 /* Next Data is a Transmission (Tx). Tx is allowed */
1387 txallowed = 1U;
1388 }
1389 if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
1390 {
1391 errorcode = HAL_TIMEOUT;
1392 hspi->State = HAL_SPI_STATE_READY;
1393 goto error;
1394 }
1395 }
1396 }
1397 /* Transmit and Receive data in 8 Bit mode */
1398 else
1399 {
1400 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1401 {
1402 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
1403 hspi->pTxBuffPtr += sizeof(uint8_t);
1404 hspi->TxXferCount--;
1405
1406 #if (USE_SPI_CRC != 0U)
1407 /* Enable CRC Transmission */
1408 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1409 {
1410 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
1411 if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
1412 {
1413 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
1414 }
1415 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1416 }
1417 #endif /* USE_SPI_CRC */
1418 }
1419 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1420 {
1421 /* Check TXE flag */
1422 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1423 {
1424 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
1425 hspi->pTxBuffPtr++;
1426 hspi->TxXferCount--;
1427 /* Next Data is a reception (Rx). Tx not allowed */
1428 txallowed = 0U;
1429
1430 #if (USE_SPI_CRC != 0U)
1431 /* Enable CRC Transmission */
1432 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1433 {
1434 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
1435 if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
1436 {
1437 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
1438 }
1439 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1440 }
1441 #endif /* USE_SPI_CRC */
1442 }
1443
1444 /* Wait until RXNE flag is reset */
1445 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1446 {
1447 (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1448 hspi->pRxBuffPtr++;
1449 hspi->RxXferCount--;
1450 /* Next Data is a Transmission (Tx). Tx is allowed */
1451 txallowed = 1U;
1452 }
1453 if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
1454 {
1455 errorcode = HAL_TIMEOUT;
1456 hspi->State = HAL_SPI_STATE_READY;
1457 goto error;
1458 }
1459 }
1460 }
1461
1462 #if (USE_SPI_CRC != 0U)
1463 /* Read CRC from DR to close CRC calculation process */
1464 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1465 {
1466 /* Wait until TXE flag */
1467 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1468 {
1469 /* Error on the CRC reception */
1470 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1471 errorcode = HAL_TIMEOUT;
1472 goto error;
1473 }
1474 /* Read CRC */
1475 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1476 {
1477 /* Read 16bit CRC */
1478 tmpreg = READ_REG(hspi->Instance->DR);
1479 /* To avoid GCC warning */
1480 UNUSED(tmpreg);
1481 }
1482 else
1483 {
1484 /* Initialize the 8bit temporary pointer */
1485 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
1486 /* Read 8bit CRC */
1487 tmpreg8 = *ptmpreg8;
1488 /* To avoid GCC warning */
1489 UNUSED(tmpreg8);
1490
1491 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
1492 {
1493 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1494 {
1495 /* Error on the CRC reception */
1496 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1497 errorcode = HAL_TIMEOUT;
1498 goto error;
1499 }
1500 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
1501 tmpreg8 = *ptmpreg8;
1502 /* To avoid GCC warning */
1503 UNUSED(tmpreg8);
1504 }
1505 }
1506 }
1507
1508 /* Check if CRC error occurred */
1509 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1510 {
1511 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1512 /* Clear CRC Flag */
1513 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1514
1515 errorcode = HAL_ERROR;
1516 }
1517 #endif /* USE_SPI_CRC */
1518
1519 /* Check the end of the transaction */
1520 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1521 {
1522 errorcode = HAL_ERROR;
1523 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1524 }
1525
1526 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1527 {
1528 errorcode = HAL_ERROR;
1529 }
1530 else
1531 {
1532 hspi->State = HAL_SPI_STATE_READY;
1533 }
1534
1535 error :
1536 __HAL_UNLOCK(hspi);
1537 return errorcode;
1538 }
1539
1540 /**
1541 * @brief Transmit an amount of data in non-blocking mode with Interrupt.
1542 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1543 * the configuration information for SPI module.
1544 * @param pData pointer to data buffer
1545 * @param Size amount of data to be sent
1546 * @retval HAL status
1547 */
HAL_SPI_Transmit_IT(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1548 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1549 {
1550 HAL_StatusTypeDef errorcode = HAL_OK;
1551
1552 /* Check Direction parameter */
1553 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1554
1555
1556 if ((pData == NULL) || (Size == 0U))
1557 {
1558 errorcode = HAL_ERROR;
1559 goto error;
1560 }
1561
1562 if (hspi->State != HAL_SPI_STATE_READY)
1563 {
1564 errorcode = HAL_BUSY;
1565 goto error;
1566 }
1567
1568 /* Process Locked */
1569 __HAL_LOCK(hspi);
1570
1571 /* Set the transaction information */
1572 hspi->State = HAL_SPI_STATE_BUSY_TX;
1573 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1574 hspi->pTxBuffPtr = (uint8_t *)pData;
1575 hspi->TxXferSize = Size;
1576 hspi->TxXferCount = Size;
1577
1578 /* Init field not used in handle to zero */
1579 hspi->pRxBuffPtr = (uint8_t *)NULL;
1580 hspi->RxXferSize = 0U;
1581 hspi->RxXferCount = 0U;
1582 hspi->RxISR = NULL;
1583
1584 /* Set the function for IT treatment */
1585 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1586 {
1587 hspi->TxISR = SPI_TxISR_16BIT;
1588 }
1589 else
1590 {
1591 hspi->TxISR = SPI_TxISR_8BIT;
1592 }
1593
1594 /* Configure communication direction : 1Line */
1595 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1596 {
1597 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1598 __HAL_SPI_DISABLE(hspi);
1599 SPI_1LINE_TX(hspi);
1600 }
1601
1602 #if (USE_SPI_CRC != 0U)
1603 /* Reset CRC Calculation */
1604 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1605 {
1606 SPI_RESET_CRC(hspi);
1607 }
1608 #endif /* USE_SPI_CRC */
1609
1610 /* Check if the SPI is already enabled */
1611 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1612 {
1613 /* Enable SPI peripheral */
1614 __HAL_SPI_ENABLE(hspi);
1615 }
1616
1617 /* Process Unlocked */
1618 __HAL_UNLOCK(hspi);
1619 /* Enable TXE and ERR interrupt */
1620 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
1621
1622 error :
1623 return errorcode;
1624 }
1625
1626 /**
1627 * @brief Receive an amount of data in non-blocking mode with Interrupt.
1628 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1629 * the configuration information for SPI module.
1630 * @param pData pointer to data buffer
1631 * @param Size amount of data to be sent
1632 * @retval HAL status
1633 */
HAL_SPI_Receive_IT(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1634 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1635 {
1636 HAL_StatusTypeDef errorcode = HAL_OK;
1637
1638
1639 if (hspi->State != HAL_SPI_STATE_READY)
1640 {
1641 errorcode = HAL_BUSY;
1642 goto error;
1643 }
1644
1645 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1646 {
1647 hspi->State = HAL_SPI_STATE_BUSY_RX;
1648 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1649 return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
1650 }
1651
1652
1653 if ((pData == NULL) || (Size == 0U))
1654 {
1655 errorcode = HAL_ERROR;
1656 goto error;
1657 }
1658
1659 /* Process Locked */
1660 __HAL_LOCK(hspi);
1661
1662 /* Set the transaction information */
1663 hspi->State = HAL_SPI_STATE_BUSY_RX;
1664 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1665 hspi->pRxBuffPtr = (uint8_t *)pData;
1666 hspi->RxXferSize = Size;
1667 hspi->RxXferCount = Size;
1668
1669 /* Init field not used in handle to zero */
1670 hspi->pTxBuffPtr = (uint8_t *)NULL;
1671 hspi->TxXferSize = 0U;
1672 hspi->TxXferCount = 0U;
1673 hspi->TxISR = NULL;
1674
1675 /* Check the data size to adapt Rx threshold and the set the function for IT treatment */
1676 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1677 {
1678 /* Set RX Fifo threshold according the reception data length: 16 bit */
1679 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1680 hspi->RxISR = SPI_RxISR_16BIT;
1681 }
1682 else
1683 {
1684 /* Set RX Fifo threshold according the reception data length: 8 bit */
1685 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1686 hspi->RxISR = SPI_RxISR_8BIT;
1687 }
1688
1689 /* Configure communication direction : 1Line */
1690 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1691 {
1692 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1693 __HAL_SPI_DISABLE(hspi);
1694 SPI_1LINE_RX(hspi);
1695 }
1696
1697 #if (USE_SPI_CRC != 0U)
1698 /* Reset CRC Calculation */
1699 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1700 {
1701 hspi->CRCSize = 1U;
1702 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1703 {
1704 hspi->CRCSize = 2U;
1705 }
1706 SPI_RESET_CRC(hspi);
1707 }
1708 else
1709 {
1710 hspi->CRCSize = 0U;
1711 }
1712 #endif /* USE_SPI_CRC */
1713
1714 /* Note : The SPI must be enabled after unlocking current process
1715 to avoid the risk of SPI interrupt handle execution before current
1716 process unlock */
1717
1718 /* Check if the SPI is already enabled */
1719 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1720 {
1721 /* Enable SPI peripheral */
1722 __HAL_SPI_ENABLE(hspi);
1723 }
1724
1725 /* Process Unlocked */
1726 __HAL_UNLOCK(hspi);
1727 /* Enable RXNE and ERR interrupt */
1728 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
1729
1730 error :
1731 return errorcode;
1732 }
1733
1734 /**
1735 * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
1736 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1737 * the configuration information for SPI module.
1738 * @param pTxData pointer to transmission data buffer
1739 * @param pRxData pointer to reception data buffer
1740 * @param Size amount of data to be sent and received
1741 * @retval HAL status
1742 */
HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size)1743 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
1744 {
1745 uint32_t tmp_mode;
1746 HAL_SPI_StateTypeDef tmp_state;
1747 HAL_StatusTypeDef errorcode = HAL_OK;
1748
1749 /* Check Direction parameter */
1750 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1751
1752 /* Init temporary variables */
1753 tmp_state = hspi->State;
1754 tmp_mode = hspi->Init.Mode;
1755
1756 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1757 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1758 {
1759 errorcode = HAL_BUSY;
1760 goto error;
1761 }
1762
1763 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1764 {
1765 errorcode = HAL_ERROR;
1766 goto error;
1767 }
1768
1769 /* Process locked */
1770 __HAL_LOCK(hspi);
1771
1772 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1773 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1774 {
1775 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1776 }
1777
1778 /* Set the transaction information */
1779 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1780 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1781 hspi->TxXferSize = Size;
1782 hspi->TxXferCount = Size;
1783 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1784 hspi->RxXferSize = Size;
1785 hspi->RxXferCount = Size;
1786
1787 /* Set the function for IT treatment */
1788 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1789 {
1790 hspi->RxISR = SPI_2linesRxISR_16BIT;
1791 hspi->TxISR = SPI_2linesTxISR_16BIT;
1792 }
1793 else
1794 {
1795 hspi->RxISR = SPI_2linesRxISR_8BIT;
1796 hspi->TxISR = SPI_2linesTxISR_8BIT;
1797 }
1798
1799 #if (USE_SPI_CRC != 0U)
1800 /* Reset CRC Calculation */
1801 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1802 {
1803 hspi->CRCSize = 1U;
1804 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1805 {
1806 hspi->CRCSize = 2U;
1807 }
1808 SPI_RESET_CRC(hspi);
1809 }
1810 else
1811 {
1812 hspi->CRCSize = 0U;
1813 }
1814 #endif /* USE_SPI_CRC */
1815
1816 /* Check if packing mode is enabled and if there is more than 2 data to receive */
1817 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U))
1818 {
1819 /* Set RX Fifo threshold according the reception data length: 16 bit */
1820 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1821 }
1822 else
1823 {
1824 /* Set RX Fifo threshold according the reception data length: 8 bit */
1825 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1826 }
1827
1828
1829 /* Check if the SPI is already enabled */
1830 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1831 {
1832 /* Enable SPI peripheral */
1833 __HAL_SPI_ENABLE(hspi);
1834 }
1835
1836 /* Process Unlocked */
1837 __HAL_UNLOCK(hspi);
1838 /* Enable TXE, RXNE and ERR interrupt */
1839 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
1840
1841 error :
1842 return errorcode;
1843 }
1844
1845 /**
1846 * @brief Transmit an amount of data in non-blocking mode with DMA.
1847 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1848 * the configuration information for SPI module.
1849 * @param pData pointer to data buffer
1850 * @param Size amount of data to be sent
1851 * @retval HAL status
1852 */
HAL_SPI_Transmit_DMA(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1853 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1854 {
1855 HAL_StatusTypeDef errorcode = HAL_OK;
1856
1857 /* Check tx dma handle */
1858 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1859
1860 /* Check Direction parameter */
1861 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1862
1863 /* Process Locked */
1864 __HAL_LOCK(hspi);
1865
1866 if (hspi->State != HAL_SPI_STATE_READY)
1867 {
1868 errorcode = HAL_BUSY;
1869 goto error;
1870 }
1871
1872 if ((pData == NULL) || (Size == 0U))
1873 {
1874 errorcode = HAL_ERROR;
1875 goto error;
1876 }
1877
1878 /* Set the transaction information */
1879 hspi->State = HAL_SPI_STATE_BUSY_TX;
1880 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1881 hspi->pTxBuffPtr = (uint8_t *)pData;
1882 hspi->TxXferSize = Size;
1883 hspi->TxXferCount = Size;
1884
1885 /* Init field not used in handle to zero */
1886 hspi->pRxBuffPtr = (uint8_t *)NULL;
1887 hspi->TxISR = NULL;
1888 hspi->RxISR = NULL;
1889 hspi->RxXferSize = 0U;
1890 hspi->RxXferCount = 0U;
1891
1892 /* Configure communication direction : 1Line */
1893 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1894 {
1895 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1896 __HAL_SPI_DISABLE(hspi);
1897 SPI_1LINE_TX(hspi);
1898 }
1899
1900 #if (USE_SPI_CRC != 0U)
1901 /* Reset CRC Calculation */
1902 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1903 {
1904 SPI_RESET_CRC(hspi);
1905 }
1906 #endif /* USE_SPI_CRC */
1907
1908 /* Set the SPI TxDMA Half transfer complete callback */
1909 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
1910
1911 /* Set the SPI TxDMA transfer complete callback */
1912 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
1913
1914 /* Set the DMA error callback */
1915 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
1916
1917 /* Set the DMA AbortCpltCallback */
1918 hspi->hdmatx->XferAbortCallback = NULL;
1919
1920 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1921 /* Packing mode is enabled only if the DMA setting is HALWORD */
1922 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
1923 {
1924 /* Check the even/odd of the data size + crc if enabled */
1925 if ((hspi->TxXferCount & 0x1U) == 0U)
1926 {
1927 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1928 hspi->TxXferCount = (hspi->TxXferCount >> 1U);
1929 }
1930 else
1931 {
1932 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1933 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
1934 }
1935 }
1936
1937 /* Enable the Tx DMA Stream/Channel */
1938 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
1939 hspi->TxXferCount))
1940 {
1941 /* Update SPI error code */
1942 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
1943 errorcode = HAL_ERROR;
1944
1945 goto error;
1946 }
1947
1948 /* Check if the SPI is already enabled */
1949 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1950 {
1951 /* Enable SPI peripheral */
1952 __HAL_SPI_ENABLE(hspi);
1953 }
1954
1955 /* Enable the SPI Error Interrupt Bit */
1956 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
1957
1958 /* Enable Tx DMA Request */
1959 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1960
1961 error :
1962 /* Process Unlocked */
1963 __HAL_UNLOCK(hspi);
1964 return errorcode;
1965 }
1966
1967 /**
1968 * @brief Receive an amount of data in non-blocking mode with DMA.
1969 * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
1970 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1971 * the configuration information for SPI module.
1972 * @param pData pointer to data buffer
1973 * @note When the CRC feature is enabled the pData Length must be Size + 1.
1974 * @param Size amount of data to be sent
1975 * @retval HAL status
1976 */
HAL_SPI_Receive_DMA(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1977 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1978 {
1979 HAL_StatusTypeDef errorcode = HAL_OK;
1980
1981 /* Check rx dma handle */
1982 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
1983
1984 if (hspi->State != HAL_SPI_STATE_READY)
1985 {
1986 errorcode = HAL_BUSY;
1987 goto error;
1988 }
1989
1990 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1991 {
1992 hspi->State = HAL_SPI_STATE_BUSY_RX;
1993
1994 /* Check tx dma handle */
1995 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1996
1997 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1998 return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
1999 }
2000
2001 /* Process Locked */
2002 __HAL_LOCK(hspi);
2003
2004 if ((pData == NULL) || (Size == 0U))
2005 {
2006 errorcode = HAL_ERROR;
2007 goto error;
2008 }
2009
2010 /* Set the transaction information */
2011 hspi->State = HAL_SPI_STATE_BUSY_RX;
2012 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2013 hspi->pRxBuffPtr = (uint8_t *)pData;
2014 hspi->RxXferSize = Size;
2015 hspi->RxXferCount = Size;
2016
2017 /*Init field not used in handle to zero */
2018 hspi->RxISR = NULL;
2019 hspi->TxISR = NULL;
2020 hspi->TxXferSize = 0U;
2021 hspi->TxXferCount = 0U;
2022
2023 /* Configure communication direction : 1Line */
2024 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
2025 {
2026 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
2027 __HAL_SPI_DISABLE(hspi);
2028 SPI_1LINE_RX(hspi);
2029 }
2030
2031 #if (USE_SPI_CRC != 0U)
2032 /* Reset CRC Calculation */
2033 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2034 {
2035 SPI_RESET_CRC(hspi);
2036 }
2037 #endif /* USE_SPI_CRC */
2038
2039 #if defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6)|| defined (STM32F038xx) || defined (STM32F051x8) || defined (STM32F058xx)
2040 /* Packing mode management is enabled by the DMA settings */
2041 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
2042 {
2043 /* Restriction the DMA data received is not allowed in this mode */
2044 errorcode = HAL_ERROR;
2045 goto error;
2046 }
2047 #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F058xx */
2048
2049 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2050 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
2051 {
2052 /* Set RX Fifo threshold according the reception data length: 16bit */
2053 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2054 }
2055 else
2056 {
2057 /* Set RX Fifo threshold according the reception data length: 8bit */
2058 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2059
2060 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2061 {
2062 /* Set RX Fifo threshold according the reception data length: 16bit */
2063 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2064
2065 if ((hspi->RxXferCount & 0x1U) == 0x0U)
2066 {
2067 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2068 hspi->RxXferCount = hspi->RxXferCount >> 1U;
2069 }
2070 else
2071 {
2072 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2073 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
2074 }
2075 }
2076 }
2077
2078 /* Set the SPI RxDMA Half transfer complete callback */
2079 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
2080
2081 /* Set the SPI Rx DMA transfer complete callback */
2082 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
2083
2084 /* Set the DMA error callback */
2085 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
2086
2087 /* Set the DMA AbortCpltCallback */
2088 hspi->hdmarx->XferAbortCallback = NULL;
2089
2090 /* Enable the Rx DMA Stream/Channel */
2091 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
2092 hspi->RxXferCount))
2093 {
2094 /* Update SPI error code */
2095 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2096 errorcode = HAL_ERROR;
2097
2098 goto error;
2099 }
2100
2101 /* Check if the SPI is already enabled */
2102 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
2103 {
2104 /* Enable SPI peripheral */
2105 __HAL_SPI_ENABLE(hspi);
2106 }
2107
2108 /* Enable the SPI Error Interrupt Bit */
2109 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
2110
2111 /* Enable Rx DMA Request */
2112 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2113
2114 error:
2115 /* Process Unlocked */
2116 __HAL_UNLOCK(hspi);
2117 return errorcode;
2118 }
2119
2120 /**
2121 * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
2122 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2123 * the configuration information for SPI module.
2124 * @param pTxData pointer to transmission data buffer
2125 * @param pRxData pointer to reception data buffer
2126 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
2127 * @param Size amount of data to be sent
2128 * @retval HAL status
2129 */
HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size)2130 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
2131 uint16_t Size)
2132 {
2133 uint32_t tmp_mode;
2134 HAL_SPI_StateTypeDef tmp_state;
2135 HAL_StatusTypeDef errorcode = HAL_OK;
2136
2137 /* Check rx & tx dma handles */
2138 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
2139 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
2140
2141 /* Check Direction parameter */
2142 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
2143
2144 /* Process locked */
2145 __HAL_LOCK(hspi);
2146
2147 /* Init temporary variables */
2148 tmp_state = hspi->State;
2149 tmp_mode = hspi->Init.Mode;
2150
2151 if (!((tmp_state == HAL_SPI_STATE_READY) ||
2152 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
2153 {
2154 errorcode = HAL_BUSY;
2155 goto error;
2156 }
2157
2158 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
2159 {
2160 errorcode = HAL_ERROR;
2161 goto error;
2162 }
2163
2164 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
2165 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
2166 {
2167 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
2168 }
2169
2170 /* Set the transaction information */
2171 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2172 hspi->pTxBuffPtr = (uint8_t *)pTxData;
2173 hspi->TxXferSize = Size;
2174 hspi->TxXferCount = Size;
2175 hspi->pRxBuffPtr = (uint8_t *)pRxData;
2176 hspi->RxXferSize = Size;
2177 hspi->RxXferCount = Size;
2178
2179 /* Init field not used in handle to zero */
2180 hspi->RxISR = NULL;
2181 hspi->TxISR = NULL;
2182
2183 #if (USE_SPI_CRC != 0U)
2184 /* Reset CRC Calculation */
2185 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2186 {
2187 SPI_RESET_CRC(hspi);
2188 }
2189 #endif /* USE_SPI_CRC */
2190
2191 #if defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F051x8) || defined (STM32F058xx)
2192 /* Packing mode management is enabled by the DMA settings */
2193 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
2194 {
2195 /* Restriction the DMA data received is not allowed in this mode */
2196 errorcode = HAL_ERROR;
2197 goto error;
2198 }
2199 #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F058xx */
2200
2201 /* Reset the threshold bit */
2202 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
2203
2204 /* The packing mode management is enabled by the DMA settings according the spi data size */
2205 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
2206 {
2207 /* Set fiforxthreshold according the reception data length: 16bit */
2208 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2209 }
2210 else
2211 {
2212 /* Set RX Fifo threshold according the reception data length: 8bit */
2213 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2214
2215 if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2216 {
2217 if ((hspi->TxXferSize & 0x1U) == 0x0U)
2218 {
2219 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
2220 hspi->TxXferCount = hspi->TxXferCount >> 1U;
2221 }
2222 else
2223 {
2224 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
2225 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
2226 }
2227 }
2228
2229 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2230 {
2231 /* Set RX Fifo threshold according the reception data length: 16bit */
2232 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2233
2234 if ((hspi->RxXferCount & 0x1U) == 0x0U)
2235 {
2236 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2237 hspi->RxXferCount = hspi->RxXferCount >> 1U;
2238 }
2239 else
2240 {
2241 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2242 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
2243 }
2244 }
2245 }
2246
2247 /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
2248 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
2249 {
2250 /* Set the SPI Rx DMA Half transfer complete callback */
2251 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
2252 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
2253 }
2254 else
2255 {
2256 /* Set the SPI Tx/Rx DMA Half transfer complete callback */
2257 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
2258 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
2259 }
2260
2261 /* Set the DMA error callback */
2262 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
2263
2264 /* Set the DMA AbortCpltCallback */
2265 hspi->hdmarx->XferAbortCallback = NULL;
2266
2267 /* Enable the Rx DMA Stream/Channel */
2268 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
2269 hspi->RxXferCount))
2270 {
2271 /* Update SPI error code */
2272 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2273 errorcode = HAL_ERROR;
2274
2275 goto error;
2276 }
2277
2278 /* Enable Rx DMA Request */
2279 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2280
2281 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
2282 is performed in DMA reception complete callback */
2283 hspi->hdmatx->XferHalfCpltCallback = NULL;
2284 hspi->hdmatx->XferCpltCallback = NULL;
2285 hspi->hdmatx->XferErrorCallback = NULL;
2286 hspi->hdmatx->XferAbortCallback = NULL;
2287
2288 /* Enable the Tx DMA Stream/Channel */
2289 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
2290 hspi->TxXferCount))
2291 {
2292 /* Update SPI error code */
2293 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2294 errorcode = HAL_ERROR;
2295
2296 goto error;
2297 }
2298
2299 /* Check if the SPI is already enabled */
2300 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
2301 {
2302 /* Enable SPI peripheral */
2303 __HAL_SPI_ENABLE(hspi);
2304 }
2305 /* Enable the SPI Error Interrupt Bit */
2306 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
2307
2308 /* Enable Tx DMA Request */
2309 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2310
2311 error :
2312 /* Process Unlocked */
2313 __HAL_UNLOCK(hspi);
2314 return errorcode;
2315 }
2316
2317 /**
2318 * @brief Abort ongoing transfer (blocking mode).
2319 * @param hspi SPI handle.
2320 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2321 * started in Interrupt or DMA mode.
2322 * This procedure performs following operations :
2323 * - Disable SPI Interrupts (depending of transfer direction)
2324 * - Disable the DMA transfer in the peripheral register (if enabled)
2325 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
2326 * - Set handle State to READY
2327 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
2328 * @retval HAL status
2329 */
HAL_SPI_Abort(SPI_HandleTypeDef * hspi)2330 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
2331 {
2332 HAL_StatusTypeDef errorcode;
2333 __IO uint32_t count;
2334 __IO uint32_t resetcount;
2335
2336 /* Initialized local variable */
2337 errorcode = HAL_OK;
2338 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2339 count = resetcount;
2340
2341 /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
2342 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2343
2344 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
2345 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2346 {
2347 hspi->TxISR = SPI_AbortTx_ISR;
2348 /* Wait HAL_SPI_STATE_ABORT state */
2349 do
2350 {
2351 if (count == 0U)
2352 {
2353 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2354 break;
2355 }
2356 count--;
2357 } while (hspi->State != HAL_SPI_STATE_ABORT);
2358 /* Reset Timeout Counter */
2359 count = resetcount;
2360 }
2361
2362 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2363 {
2364 hspi->RxISR = SPI_AbortRx_ISR;
2365 /* Wait HAL_SPI_STATE_ABORT state */
2366 do
2367 {
2368 if (count == 0U)
2369 {
2370 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2371 break;
2372 }
2373 count--;
2374 } while (hspi->State != HAL_SPI_STATE_ABORT);
2375 /* Reset Timeout Counter */
2376 count = resetcount;
2377 }
2378
2379 /* Disable the SPI DMA Tx request if enabled */
2380 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2381 {
2382 /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
2383 if (hspi->hdmatx != NULL)
2384 {
2385 /* Set the SPI DMA Abort callback :
2386 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2387 hspi->hdmatx->XferAbortCallback = NULL;
2388
2389 /* Abort DMA Tx Handle linked to SPI Peripheral */
2390 if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
2391 {
2392 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2393 }
2394
2395 /* Disable Tx DMA Request */
2396 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
2397
2398 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2399 {
2400 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2401 }
2402
2403 /* Disable SPI Peripheral */
2404 __HAL_SPI_DISABLE(hspi);
2405
2406 /* Empty the FRLVL fifo */
2407 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2408 {
2409 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2410 }
2411 }
2412 }
2413
2414 /* Disable the SPI DMA Rx request if enabled */
2415 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2416 {
2417 /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
2418 if (hspi->hdmarx != NULL)
2419 {
2420 /* Set the SPI DMA Abort callback :
2421 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2422 hspi->hdmarx->XferAbortCallback = NULL;
2423
2424 /* Abort DMA Rx Handle linked to SPI Peripheral */
2425 if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
2426 {
2427 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2428 }
2429
2430 /* Disable peripheral */
2431 __HAL_SPI_DISABLE(hspi);
2432
2433 /* Control the BSY flag */
2434 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2435 {
2436 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2437 }
2438
2439 /* Empty the FRLVL fifo */
2440 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2441 {
2442 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2443 }
2444
2445 /* Disable Rx DMA Request */
2446 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
2447 }
2448 }
2449 /* Reset Tx and Rx transfer counters */
2450 hspi->RxXferCount = 0U;
2451 hspi->TxXferCount = 0U;
2452
2453 /* Check error during Abort procedure */
2454 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2455 {
2456 /* return HAL_Error in case of error during Abort procedure */
2457 errorcode = HAL_ERROR;
2458 }
2459 else
2460 {
2461 /* Reset errorCode */
2462 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2463 }
2464
2465 /* Clear the Error flags in the SR register */
2466 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2467 __HAL_SPI_CLEAR_FREFLAG(hspi);
2468
2469 /* Restore hspi->state to ready */
2470 hspi->State = HAL_SPI_STATE_READY;
2471
2472 return errorcode;
2473 }
2474
2475 /**
2476 * @brief Abort ongoing transfer (Interrupt mode).
2477 * @param hspi SPI handle.
2478 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2479 * started in Interrupt or DMA mode.
2480 * This procedure performs following operations :
2481 * - Disable SPI Interrupts (depending of transfer direction)
2482 * - Disable the DMA transfer in the peripheral register (if enabled)
2483 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
2484 * - Set handle State to READY
2485 * - At abort completion, call user abort complete callback
2486 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
2487 * considered as completed only when user abort complete callback is executed (not when exiting function).
2488 * @retval HAL status
2489 */
HAL_SPI_Abort_IT(SPI_HandleTypeDef * hspi)2490 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
2491 {
2492 HAL_StatusTypeDef errorcode;
2493 uint32_t abortcplt ;
2494 __IO uint32_t count;
2495 __IO uint32_t resetcount;
2496
2497 /* Initialized local variable */
2498 errorcode = HAL_OK;
2499 abortcplt = 1U;
2500 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2501 count = resetcount;
2502
2503 /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
2504 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2505
2506 /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
2507 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2508 {
2509 hspi->TxISR = SPI_AbortTx_ISR;
2510 /* Wait HAL_SPI_STATE_ABORT state */
2511 do
2512 {
2513 if (count == 0U)
2514 {
2515 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2516 break;
2517 }
2518 count--;
2519 } while (hspi->State != HAL_SPI_STATE_ABORT);
2520 /* Reset Timeout Counter */
2521 count = resetcount;
2522 }
2523
2524 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2525 {
2526 hspi->RxISR = SPI_AbortRx_ISR;
2527 /* Wait HAL_SPI_STATE_ABORT state */
2528 do
2529 {
2530 if (count == 0U)
2531 {
2532 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2533 break;
2534 }
2535 count--;
2536 } while (hspi->State != HAL_SPI_STATE_ABORT);
2537 /* Reset Timeout Counter */
2538 count = resetcount;
2539 }
2540
2541 /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
2542 before any call to DMA Abort functions */
2543 /* DMA Tx Handle is valid */
2544 if (hspi->hdmatx != NULL)
2545 {
2546 /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
2547 Otherwise, set it to NULL */
2548 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2549 {
2550 hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
2551 }
2552 else
2553 {
2554 hspi->hdmatx->XferAbortCallback = NULL;
2555 }
2556 }
2557 /* DMA Rx Handle is valid */
2558 if (hspi->hdmarx != NULL)
2559 {
2560 /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
2561 Otherwise, set it to NULL */
2562 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2563 {
2564 hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
2565 }
2566 else
2567 {
2568 hspi->hdmarx->XferAbortCallback = NULL;
2569 }
2570 }
2571
2572 /* Disable the SPI DMA Tx request if enabled */
2573 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2574 {
2575 /* Abort the SPI DMA Tx Stream/Channel */
2576 if (hspi->hdmatx != NULL)
2577 {
2578 /* Abort DMA Tx Handle linked to SPI Peripheral */
2579 if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
2580 {
2581 hspi->hdmatx->XferAbortCallback = NULL;
2582 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2583 }
2584 else
2585 {
2586 abortcplt = 0U;
2587 }
2588 }
2589 }
2590 /* Disable the SPI DMA Rx request if enabled */
2591 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2592 {
2593 /* Abort the SPI DMA Rx Stream/Channel */
2594 if (hspi->hdmarx != NULL)
2595 {
2596 /* Abort DMA Rx Handle linked to SPI Peripheral */
2597 if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
2598 {
2599 hspi->hdmarx->XferAbortCallback = NULL;
2600 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2601 }
2602 else
2603 {
2604 abortcplt = 0U;
2605 }
2606 }
2607 }
2608
2609 if (abortcplt == 1U)
2610 {
2611 /* Reset Tx and Rx transfer counters */
2612 hspi->RxXferCount = 0U;
2613 hspi->TxXferCount = 0U;
2614
2615 /* Check error during Abort procedure */
2616 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2617 {
2618 /* return HAL_Error in case of error during Abort procedure */
2619 errorcode = HAL_ERROR;
2620 }
2621 else
2622 {
2623 /* Reset errorCode */
2624 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2625 }
2626
2627 /* Clear the Error flags in the SR register */
2628 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2629 __HAL_SPI_CLEAR_FREFLAG(hspi);
2630
2631 /* Restore hspi->State to Ready */
2632 hspi->State = HAL_SPI_STATE_READY;
2633
2634 /* As no DMA to be aborted, call directly user Abort complete callback */
2635 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2636 hspi->AbortCpltCallback(hspi);
2637 #else
2638 HAL_SPI_AbortCpltCallback(hspi);
2639 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2640 }
2641
2642 return errorcode;
2643 }
2644
2645 /**
2646 * @brief Pause the DMA Transfer.
2647 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2648 * the configuration information for the specified SPI module.
2649 * @retval HAL status
2650 */
HAL_SPI_DMAPause(SPI_HandleTypeDef * hspi)2651 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
2652 {
2653 /* Process Locked */
2654 __HAL_LOCK(hspi);
2655
2656 /* Disable the SPI DMA Tx & Rx requests */
2657 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2658
2659 /* Process Unlocked */
2660 __HAL_UNLOCK(hspi);
2661
2662 return HAL_OK;
2663 }
2664
2665 /**
2666 * @brief Resume the DMA Transfer.
2667 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2668 * the configuration information for the specified SPI module.
2669 * @retval HAL status
2670 */
HAL_SPI_DMAResume(SPI_HandleTypeDef * hspi)2671 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
2672 {
2673 /* Process Locked */
2674 __HAL_LOCK(hspi);
2675
2676 /* Enable the SPI DMA Tx & Rx requests */
2677 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2678
2679 /* Process Unlocked */
2680 __HAL_UNLOCK(hspi);
2681
2682 return HAL_OK;
2683 }
2684
2685 /**
2686 * @brief Stop the DMA Transfer.
2687 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2688 * the configuration information for the specified SPI module.
2689 * @retval HAL status
2690 */
HAL_SPI_DMAStop(SPI_HandleTypeDef * hspi)2691 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
2692 {
2693 HAL_StatusTypeDef errorcode = HAL_OK;
2694 /* The Lock is not implemented on this API to allow the user application
2695 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
2696 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
2697 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
2698 */
2699
2700 /* Abort the SPI DMA tx Stream/Channel */
2701 if (hspi->hdmatx != NULL)
2702 {
2703 if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
2704 {
2705 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2706 errorcode = HAL_ERROR;
2707 }
2708 }
2709 /* Abort the SPI DMA rx Stream/Channel */
2710 if (hspi->hdmarx != NULL)
2711 {
2712 if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
2713 {
2714 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2715 errorcode = HAL_ERROR;
2716 }
2717 }
2718
2719 /* Disable the SPI DMA Tx & Rx requests */
2720 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2721 hspi->State = HAL_SPI_STATE_READY;
2722 return errorcode;
2723 }
2724
2725 /**
2726 * @brief Handle SPI interrupt request.
2727 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2728 * the configuration information for the specified SPI module.
2729 * @retval None
2730 */
HAL_SPI_IRQHandler(SPI_HandleTypeDef * hspi)2731 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
2732 {
2733 uint32_t itsource = hspi->Instance->CR2;
2734 uint32_t itflag = hspi->Instance->SR;
2735
2736 /* SPI in mode Receiver ----------------------------------------------------*/
2737 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
2738 (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
2739 {
2740 hspi->RxISR(hspi);
2741 return;
2742 }
2743
2744 /* SPI in mode Transmitter -------------------------------------------------*/
2745 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
2746 {
2747 hspi->TxISR(hspi);
2748 return;
2749 }
2750
2751 /* SPI in Error Treatment --------------------------------------------------*/
2752 if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
2753 || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
2754 {
2755 /* SPI Overrun error interrupt occurred ----------------------------------*/
2756 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
2757 {
2758 if (hspi->State != HAL_SPI_STATE_BUSY_TX)
2759 {
2760 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
2761 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2762 }
2763 else
2764 {
2765 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2766 return;
2767 }
2768 }
2769
2770 /* SPI Mode Fault error interrupt occurred -------------------------------*/
2771 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
2772 {
2773 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
2774 __HAL_SPI_CLEAR_MODFFLAG(hspi);
2775 }
2776
2777 /* SPI Frame error interrupt occurred ------------------------------------*/
2778 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
2779 {
2780 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
2781 __HAL_SPI_CLEAR_FREFLAG(hspi);
2782 }
2783
2784 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2785 {
2786 /* Disable all interrupts */
2787 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
2788
2789 hspi->State = HAL_SPI_STATE_READY;
2790 /* Disable the SPI DMA requests if enabled */
2791 if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
2792 {
2793 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
2794
2795 /* Abort the SPI DMA Rx channel */
2796 if (hspi->hdmarx != NULL)
2797 {
2798 /* Set the SPI DMA Abort callback :
2799 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2800 hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
2801 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
2802 {
2803 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2804 }
2805 }
2806 /* Abort the SPI DMA Tx channel */
2807 if (hspi->hdmatx != NULL)
2808 {
2809 /* Set the SPI DMA Abort callback :
2810 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2811 hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
2812 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
2813 {
2814 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2815 }
2816 }
2817 }
2818 else
2819 {
2820 /* Call user error callback */
2821 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2822 hspi->ErrorCallback(hspi);
2823 #else
2824 HAL_SPI_ErrorCallback(hspi);
2825 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2826 }
2827 }
2828 return;
2829 }
2830 }
2831
2832 /**
2833 * @brief Tx Transfer completed callback.
2834 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2835 * the configuration information for SPI module.
2836 * @retval None
2837 */
HAL_SPI_TxCpltCallback(SPI_HandleTypeDef * hspi)2838 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
2839 {
2840 /* Prevent unused argument(s) compilation warning */
2841 UNUSED(hspi);
2842
2843 /* NOTE : This function should not be modified, when the callback is needed,
2844 the HAL_SPI_TxCpltCallback should be implemented in the user file
2845 */
2846 }
2847
2848 /**
2849 * @brief Rx Transfer completed callback.
2850 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2851 * the configuration information for SPI module.
2852 * @retval None
2853 */
HAL_SPI_RxCpltCallback(SPI_HandleTypeDef * hspi)2854 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
2855 {
2856 /* Prevent unused argument(s) compilation warning */
2857 UNUSED(hspi);
2858
2859 /* NOTE : This function should not be modified, when the callback is needed,
2860 the HAL_SPI_RxCpltCallback should be implemented in the user file
2861 */
2862 }
2863
2864 /**
2865 * @brief Tx and Rx Transfer completed callback.
2866 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2867 * the configuration information for SPI module.
2868 * @retval None
2869 */
HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef * hspi)2870 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
2871 {
2872 /* Prevent unused argument(s) compilation warning */
2873 UNUSED(hspi);
2874
2875 /* NOTE : This function should not be modified, when the callback is needed,
2876 the HAL_SPI_TxRxCpltCallback should be implemented in the user file
2877 */
2878 }
2879
2880 /**
2881 * @brief Tx Half Transfer completed callback.
2882 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2883 * the configuration information for SPI module.
2884 * @retval None
2885 */
HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef * hspi)2886 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2887 {
2888 /* Prevent unused argument(s) compilation warning */
2889 UNUSED(hspi);
2890
2891 /* NOTE : This function should not be modified, when the callback is needed,
2892 the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
2893 */
2894 }
2895
2896 /**
2897 * @brief Rx Half Transfer completed callback.
2898 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2899 * the configuration information for SPI module.
2900 * @retval None
2901 */
HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef * hspi)2902 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2903 {
2904 /* Prevent unused argument(s) compilation warning */
2905 UNUSED(hspi);
2906
2907 /* NOTE : This function should not be modified, when the callback is needed,
2908 the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
2909 */
2910 }
2911
2912 /**
2913 * @brief Tx and Rx Half Transfer callback.
2914 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2915 * the configuration information for SPI module.
2916 * @retval None
2917 */
HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef * hspi)2918 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2919 {
2920 /* Prevent unused argument(s) compilation warning */
2921 UNUSED(hspi);
2922
2923 /* NOTE : This function should not be modified, when the callback is needed,
2924 the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
2925 */
2926 }
2927
2928 /**
2929 * @brief SPI error callback.
2930 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2931 * the configuration information for SPI module.
2932 * @retval None
2933 */
HAL_SPI_ErrorCallback(SPI_HandleTypeDef * hspi)2934 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
2935 {
2936 /* Prevent unused argument(s) compilation warning */
2937 UNUSED(hspi);
2938
2939 /* NOTE : This function should not be modified, when the callback is needed,
2940 the HAL_SPI_ErrorCallback should be implemented in the user file
2941 */
2942 /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
2943 and user can use HAL_SPI_GetError() API to check the latest error occurred
2944 */
2945 }
2946
2947 /**
2948 * @brief SPI Abort Complete callback.
2949 * @param hspi SPI handle.
2950 * @retval None
2951 */
HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef * hspi)2952 __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
2953 {
2954 /* Prevent unused argument(s) compilation warning */
2955 UNUSED(hspi);
2956
2957 /* NOTE : This function should not be modified, when the callback is needed,
2958 the HAL_SPI_AbortCpltCallback can be implemented in the user file.
2959 */
2960 }
2961
2962 /**
2963 * @}
2964 */
2965
2966 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
2967 * @brief SPI control functions
2968 *
2969 @verbatim
2970 ===============================================================================
2971 ##### Peripheral State and Errors functions #####
2972 ===============================================================================
2973 [..]
2974 This subsection provides a set of functions allowing to control the SPI.
2975 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
2976 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
2977 @endverbatim
2978 * @{
2979 */
2980
2981 /**
2982 * @brief Return the SPI handle state.
2983 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2984 * the configuration information for SPI module.
2985 * @retval SPI state
2986 */
HAL_SPI_GetState(SPI_HandleTypeDef * hspi)2987 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
2988 {
2989 /* Return SPI handle state */
2990 return hspi->State;
2991 }
2992
2993 /**
2994 * @brief Return the SPI error code.
2995 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2996 * the configuration information for SPI module.
2997 * @retval SPI error code in bitmap format
2998 */
HAL_SPI_GetError(SPI_HandleTypeDef * hspi)2999 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
3000 {
3001 /* Return SPI ErrorCode */
3002 return hspi->ErrorCode;
3003 }
3004
3005 /**
3006 * @}
3007 */
3008
3009 /**
3010 * @}
3011 */
3012
3013 /** @addtogroup SPI_Private_Functions
3014 * @brief Private functions
3015 * @{
3016 */
3017
3018 /**
3019 * @brief DMA SPI transmit process complete callback.
3020 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3021 * the configuration information for the specified DMA module.
3022 * @retval None
3023 */
SPI_DMATransmitCplt(DMA_HandleTypeDef * hdma)3024 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
3025 {
3026 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3027 uint32_t tickstart;
3028
3029 /* Init tickstart for timeout management*/
3030 tickstart = HAL_GetTick();
3031
3032 /* DMA Normal Mode */
3033 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
3034 {
3035 /* Disable ERR interrupt */
3036 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3037
3038 /* Disable Tx DMA Request */
3039 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
3040
3041 /* Check the end of the transaction */
3042 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3043 {
3044 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3045 }
3046
3047 /* Clear overrun flag in 2 Lines communication mode because received data is not read */
3048 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
3049 {
3050 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3051 }
3052
3053 hspi->TxXferCount = 0U;
3054 hspi->State = HAL_SPI_STATE_READY;
3055
3056 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3057 {
3058 /* Call user error callback */
3059 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3060 hspi->ErrorCallback(hspi);
3061 #else
3062 HAL_SPI_ErrorCallback(hspi);
3063 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3064 return;
3065 }
3066 }
3067 /* Call user Tx complete callback */
3068 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3069 hspi->TxCpltCallback(hspi);
3070 #else
3071 HAL_SPI_TxCpltCallback(hspi);
3072 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3073 }
3074
3075 /**
3076 * @brief DMA SPI receive process complete callback.
3077 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3078 * the configuration information for the specified DMA module.
3079 * @retval None
3080 */
SPI_DMAReceiveCplt(DMA_HandleTypeDef * hdma)3081 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
3082 {
3083 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3084 uint32_t tickstart;
3085 #if (USE_SPI_CRC != 0U)
3086 __IO uint32_t tmpreg = 0U;
3087 __IO uint8_t *ptmpreg8;
3088 __IO uint8_t tmpreg8 = 0;
3089 #endif /* USE_SPI_CRC */
3090
3091 /* Init tickstart for timeout management*/
3092 tickstart = HAL_GetTick();
3093
3094 /* DMA Normal Mode */
3095 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
3096 {
3097 /* Disable ERR interrupt */
3098 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3099
3100 #if (USE_SPI_CRC != 0U)
3101 /* CRC handling */
3102 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3103 {
3104 /* Wait until RXNE flag */
3105 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3106 {
3107 /* Error on the CRC reception */
3108 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3109 }
3110 /* Read CRC */
3111 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
3112 {
3113 /* Read 16bit CRC */
3114 tmpreg = READ_REG(hspi->Instance->DR);
3115 /* To avoid GCC warning */
3116 UNUSED(tmpreg);
3117 }
3118 else
3119 {
3120 /* Initialize the 8bit temporary pointer */
3121 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3122 /* Read 8bit CRC */
3123 tmpreg8 = *ptmpreg8;
3124 /* To avoid GCC warning */
3125 UNUSED(tmpreg8);
3126
3127 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
3128 {
3129 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3130 {
3131 /* Error on the CRC reception */
3132 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3133 }
3134 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
3135 tmpreg8 = *ptmpreg8;
3136 /* To avoid GCC warning */
3137 UNUSED(tmpreg8);
3138 }
3139 }
3140 }
3141 #endif /* USE_SPI_CRC */
3142
3143 /* Check if we are in Master RX 2 line mode */
3144 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
3145 {
3146 /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
3147 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3148 }
3149 else
3150 {
3151 /* Normal case */
3152 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
3153 }
3154
3155 /* Check the end of the transaction */
3156 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3157 {
3158 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
3159 }
3160
3161 hspi->RxXferCount = 0U;
3162 hspi->State = HAL_SPI_STATE_READY;
3163
3164 #if (USE_SPI_CRC != 0U)
3165 /* Check if CRC error occurred */
3166 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
3167 {
3168 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3169 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3170 }
3171 #endif /* USE_SPI_CRC */
3172
3173 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3174 {
3175 /* Call user error callback */
3176 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3177 hspi->ErrorCallback(hspi);
3178 #else
3179 HAL_SPI_ErrorCallback(hspi);
3180 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3181 return;
3182 }
3183 }
3184 /* Call user Rx complete callback */
3185 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3186 hspi->RxCpltCallback(hspi);
3187 #else
3188 HAL_SPI_RxCpltCallback(hspi);
3189 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3190 }
3191
3192 /**
3193 * @brief DMA SPI transmit receive process complete callback.
3194 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3195 * the configuration information for the specified DMA module.
3196 * @retval None
3197 */
SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef * hdma)3198 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
3199 {
3200 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3201 uint32_t tickstart;
3202 #if (USE_SPI_CRC != 0U)
3203 __IO uint32_t tmpreg = 0U;
3204 __IO uint8_t *ptmpreg8;
3205 __IO uint8_t tmpreg8 = 0;
3206 #endif /* USE_SPI_CRC */
3207
3208 /* Init tickstart for timeout management*/
3209 tickstart = HAL_GetTick();
3210
3211 /* DMA Normal Mode */
3212 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
3213 {
3214 /* Disable ERR interrupt */
3215 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3216
3217 #if (USE_SPI_CRC != 0U)
3218 /* CRC handling */
3219 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3220 {
3221 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
3222 {
3223 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
3224 tickstart) != HAL_OK)
3225 {
3226 /* Error on the CRC reception */
3227 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3228 }
3229 /* Initialize the 8bit temporary pointer */
3230 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3231 /* Read 8bit CRC */
3232 tmpreg8 = *ptmpreg8;
3233 /* To avoid GCC warning */
3234 UNUSED(tmpreg8);
3235 }
3236 else
3237 {
3238 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3239 {
3240 /* Error on the CRC reception */
3241 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3242 }
3243 /* Read CRC to Flush DR and RXNE flag */
3244 tmpreg = READ_REG(hspi->Instance->DR);
3245 /* To avoid GCC warning */
3246 UNUSED(tmpreg);
3247 }
3248 }
3249 #endif /* USE_SPI_CRC */
3250
3251 /* Check the end of the transaction */
3252 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3253 {
3254 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3255 }
3256
3257 /* Disable Rx/Tx DMA Request */
3258 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3259
3260 hspi->TxXferCount = 0U;
3261 hspi->RxXferCount = 0U;
3262 hspi->State = HAL_SPI_STATE_READY;
3263
3264 #if (USE_SPI_CRC != 0U)
3265 /* Check if CRC error occurred */
3266 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
3267 {
3268 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3269 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3270 }
3271 #endif /* USE_SPI_CRC */
3272
3273 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3274 {
3275 /* Call user error callback */
3276 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3277 hspi->ErrorCallback(hspi);
3278 #else
3279 HAL_SPI_ErrorCallback(hspi);
3280 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3281 return;
3282 }
3283 }
3284 /* Call user TxRx complete callback */
3285 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3286 hspi->TxRxCpltCallback(hspi);
3287 #else
3288 HAL_SPI_TxRxCpltCallback(hspi);
3289 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3290 }
3291
3292 /**
3293 * @brief DMA SPI half transmit process complete callback.
3294 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3295 * the configuration information for the specified DMA module.
3296 * @retval None
3297 */
SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef * hdma)3298 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
3299 {
3300 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3301
3302 /* Call user Tx half complete callback */
3303 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3304 hspi->TxHalfCpltCallback(hspi);
3305 #else
3306 HAL_SPI_TxHalfCpltCallback(hspi);
3307 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3308 }
3309
3310 /**
3311 * @brief DMA SPI half receive process complete callback
3312 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3313 * the configuration information for the specified DMA module.
3314 * @retval None
3315 */
SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef * hdma)3316 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
3317 {
3318 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3319
3320 /* Call user Rx half complete callback */
3321 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3322 hspi->RxHalfCpltCallback(hspi);
3323 #else
3324 HAL_SPI_RxHalfCpltCallback(hspi);
3325 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3326 }
3327
3328 /**
3329 * @brief DMA SPI half transmit receive process complete callback.
3330 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3331 * the configuration information for the specified DMA module.
3332 * @retval None
3333 */
SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef * hdma)3334 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
3335 {
3336 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3337
3338 /* Call user TxRx half complete callback */
3339 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3340 hspi->TxRxHalfCpltCallback(hspi);
3341 #else
3342 HAL_SPI_TxRxHalfCpltCallback(hspi);
3343 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3344 }
3345
3346 /**
3347 * @brief DMA SPI communication error callback.
3348 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3349 * the configuration information for the specified DMA module.
3350 * @retval None
3351 */
SPI_DMAError(DMA_HandleTypeDef * hdma)3352 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
3353 {
3354 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3355
3356 /* Stop the disable DMA transfer on SPI side */
3357 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3358
3359 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
3360 hspi->State = HAL_SPI_STATE_READY;
3361 /* Call user error callback */
3362 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3363 hspi->ErrorCallback(hspi);
3364 #else
3365 HAL_SPI_ErrorCallback(hspi);
3366 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3367 }
3368
3369 /**
3370 * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
3371 * (To be called at end of DMA Abort procedure following error occurrence).
3372 * @param hdma DMA handle.
3373 * @retval None
3374 */
SPI_DMAAbortOnError(DMA_HandleTypeDef * hdma)3375 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
3376 {
3377 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3378 hspi->RxXferCount = 0U;
3379 hspi->TxXferCount = 0U;
3380
3381 /* Call user error callback */
3382 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3383 hspi->ErrorCallback(hspi);
3384 #else
3385 HAL_SPI_ErrorCallback(hspi);
3386 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3387 }
3388
3389 /**
3390 * @brief DMA SPI Tx communication abort callback, when initiated by user
3391 * (To be called at end of DMA Tx Abort procedure following user abort request).
3392 * @note When this callback is executed, User Abort complete call back is called only if no
3393 * Abort still ongoing for Rx DMA Handle.
3394 * @param hdma DMA handle.
3395 * @retval None
3396 */
SPI_DMATxAbortCallback(DMA_HandleTypeDef * hdma)3397 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
3398 {
3399 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3400
3401 hspi->hdmatx->XferAbortCallback = NULL;
3402
3403 /* Disable Tx DMA Request */
3404 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
3405
3406 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3407 {
3408 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3409 }
3410
3411 /* Disable SPI Peripheral */
3412 __HAL_SPI_DISABLE(hspi);
3413
3414 /* Empty the FRLVL fifo */
3415 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3416 {
3417 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3418 }
3419
3420 /* Check if an Abort process is still ongoing */
3421 if (hspi->hdmarx != NULL)
3422 {
3423 if (hspi->hdmarx->XferAbortCallback != NULL)
3424 {
3425 return;
3426 }
3427 }
3428
3429 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3430 hspi->RxXferCount = 0U;
3431 hspi->TxXferCount = 0U;
3432
3433 /* Check no error during Abort procedure */
3434 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3435 {
3436 /* Reset errorCode */
3437 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3438 }
3439
3440 /* Clear the Error flags in the SR register */
3441 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3442 __HAL_SPI_CLEAR_FREFLAG(hspi);
3443
3444 /* Restore hspi->State to Ready */
3445 hspi->State = HAL_SPI_STATE_READY;
3446
3447 /* Call user Abort complete callback */
3448 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3449 hspi->AbortCpltCallback(hspi);
3450 #else
3451 HAL_SPI_AbortCpltCallback(hspi);
3452 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3453 }
3454
3455 /**
3456 * @brief DMA SPI Rx communication abort callback, when initiated by user
3457 * (To be called at end of DMA Rx Abort procedure following user abort request).
3458 * @note When this callback is executed, User Abort complete call back is called only if no
3459 * Abort still ongoing for Tx DMA Handle.
3460 * @param hdma DMA handle.
3461 * @retval None
3462 */
SPI_DMARxAbortCallback(DMA_HandleTypeDef * hdma)3463 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
3464 {
3465 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3466
3467 /* Disable SPI Peripheral */
3468 __HAL_SPI_DISABLE(hspi);
3469
3470 hspi->hdmarx->XferAbortCallback = NULL;
3471
3472 /* Disable Rx DMA Request */
3473 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
3474
3475 /* Control the BSY flag */
3476 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3477 {
3478 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3479 }
3480
3481 /* Empty the FRLVL fifo */
3482 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3483 {
3484 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3485 }
3486
3487 /* Check if an Abort process is still ongoing */
3488 if (hspi->hdmatx != NULL)
3489 {
3490 if (hspi->hdmatx->XferAbortCallback != NULL)
3491 {
3492 return;
3493 }
3494 }
3495
3496 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3497 hspi->RxXferCount = 0U;
3498 hspi->TxXferCount = 0U;
3499
3500 /* Check no error during Abort procedure */
3501 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3502 {
3503 /* Reset errorCode */
3504 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3505 }
3506
3507 /* Clear the Error flags in the SR register */
3508 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3509 __HAL_SPI_CLEAR_FREFLAG(hspi);
3510
3511 /* Restore hspi->State to Ready */
3512 hspi->State = HAL_SPI_STATE_READY;
3513
3514 /* Call user Abort complete callback */
3515 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3516 hspi->AbortCpltCallback(hspi);
3517 #else
3518 HAL_SPI_AbortCpltCallback(hspi);
3519 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3520 }
3521
3522 /**
3523 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3524 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3525 * the configuration information for SPI module.
3526 * @retval None
3527 */
SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3528 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3529 {
3530 /* Receive data in packing mode */
3531 if (hspi->RxXferCount > 1U)
3532 {
3533 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3534 hspi->pRxBuffPtr += sizeof(uint16_t);
3535 hspi->RxXferCount -= 2U;
3536 if (hspi->RxXferCount == 1U)
3537 {
3538 /* Set RX Fifo threshold according the reception data length: 8bit */
3539 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
3540 }
3541 }
3542 /* Receive data in 8 Bit mode */
3543 else
3544 {
3545 *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
3546 hspi->pRxBuffPtr++;
3547 hspi->RxXferCount--;
3548 }
3549
3550 /* Check end of the reception */
3551 if (hspi->RxXferCount == 0U)
3552 {
3553 #if (USE_SPI_CRC != 0U)
3554 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3555 {
3556 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
3557 hspi->RxISR = SPI_2linesRxISR_8BITCRC;
3558 return;
3559 }
3560 #endif /* USE_SPI_CRC */
3561
3562 /* Disable RXNE and ERR interrupt */
3563 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3564
3565 if (hspi->TxXferCount == 0U)
3566 {
3567 SPI_CloseRxTx_ISR(hspi);
3568 }
3569 }
3570 }
3571
3572 #if (USE_SPI_CRC != 0U)
3573 /**
3574 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3575 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3576 * the configuration information for SPI module.
3577 * @retval None
3578 */
SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef * hspi)3579 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3580 {
3581 __IO uint8_t *ptmpreg8;
3582 __IO uint8_t tmpreg8 = 0;
3583
3584 /* Initialize the 8bit temporary pointer */
3585 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3586 /* Read 8bit CRC to flush Data Register */
3587 tmpreg8 = *ptmpreg8;
3588 /* To avoid GCC warning */
3589 UNUSED(tmpreg8);
3590
3591 hspi->CRCSize--;
3592
3593 /* Check end of the reception */
3594 if (hspi->CRCSize == 0U)
3595 {
3596 /* Disable RXNE and ERR interrupt */
3597 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3598
3599 if (hspi->TxXferCount == 0U)
3600 {
3601 SPI_CloseRxTx_ISR(hspi);
3602 }
3603 }
3604 }
3605 #endif /* USE_SPI_CRC */
3606
3607 /**
3608 * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
3609 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3610 * the configuration information for SPI module.
3611 * @retval None
3612 */
SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3613 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3614 {
3615 /* Transmit data in packing Bit mode */
3616 if (hspi->TxXferCount >= 2U)
3617 {
3618 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3619 hspi->pTxBuffPtr += sizeof(uint16_t);
3620 hspi->TxXferCount -= 2U;
3621 }
3622 /* Transmit data in 8 Bit mode */
3623 else
3624 {
3625 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3626 hspi->pTxBuffPtr++;
3627 hspi->TxXferCount--;
3628 }
3629
3630 /* Check the end of the transmission */
3631 if (hspi->TxXferCount == 0U)
3632 {
3633 #if (USE_SPI_CRC != 0U)
3634 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3635 {
3636 /* Set CRC Next Bit to send CRC */
3637 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3638 /* Disable TXE interrupt */
3639 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3640 return;
3641 }
3642 #endif /* USE_SPI_CRC */
3643
3644 /* Disable TXE interrupt */
3645 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3646
3647 if (hspi->RxXferCount == 0U)
3648 {
3649 SPI_CloseRxTx_ISR(hspi);
3650 }
3651 }
3652 }
3653
3654 /**
3655 * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
3656 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3657 * the configuration information for SPI module.
3658 * @retval None
3659 */
SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3660 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3661 {
3662 /* Receive data in 16 Bit mode */
3663 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3664 hspi->pRxBuffPtr += sizeof(uint16_t);
3665 hspi->RxXferCount--;
3666
3667 if (hspi->RxXferCount == 0U)
3668 {
3669 #if (USE_SPI_CRC != 0U)
3670 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3671 {
3672 hspi->RxISR = SPI_2linesRxISR_16BITCRC;
3673 return;
3674 }
3675 #endif /* USE_SPI_CRC */
3676
3677 /* Disable RXNE interrupt */
3678 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3679
3680 if (hspi->TxXferCount == 0U)
3681 {
3682 SPI_CloseRxTx_ISR(hspi);
3683 }
3684 }
3685 }
3686
3687 #if (USE_SPI_CRC != 0U)
3688 /**
3689 * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
3690 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3691 * the configuration information for SPI module.
3692 * @retval None
3693 */
SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef * hspi)3694 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3695 {
3696 __IO uint32_t tmpreg = 0U;
3697
3698 /* Read 16bit CRC to flush Data Register */
3699 tmpreg = READ_REG(hspi->Instance->DR);
3700 /* To avoid GCC warning */
3701 UNUSED(tmpreg);
3702
3703 /* Disable RXNE interrupt */
3704 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3705
3706 SPI_CloseRxTx_ISR(hspi);
3707 }
3708 #endif /* USE_SPI_CRC */
3709
3710 /**
3711 * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
3712 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3713 * the configuration information for SPI module.
3714 * @retval None
3715 */
SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3716 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3717 {
3718 /* Transmit data in 16 Bit mode */
3719 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3720 hspi->pTxBuffPtr += sizeof(uint16_t);
3721 hspi->TxXferCount--;
3722
3723 /* Enable CRC Transmission */
3724 if (hspi->TxXferCount == 0U)
3725 {
3726 #if (USE_SPI_CRC != 0U)
3727 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3728 {
3729 /* Set CRC Next Bit to send CRC */
3730 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3731 /* Disable TXE interrupt */
3732 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3733 return;
3734 }
3735 #endif /* USE_SPI_CRC */
3736
3737 /* Disable TXE interrupt */
3738 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3739
3740 if (hspi->RxXferCount == 0U)
3741 {
3742 SPI_CloseRxTx_ISR(hspi);
3743 }
3744 }
3745 }
3746
3747 #if (USE_SPI_CRC != 0U)
3748 /**
3749 * @brief Manage the CRC 8-bit receive in Interrupt context.
3750 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3751 * the configuration information for SPI module.
3752 * @retval None
3753 */
SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef * hspi)3754 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3755 {
3756 __IO uint8_t *ptmpreg8;
3757 __IO uint8_t tmpreg8 = 0;
3758
3759 /* Initialize the 8bit temporary pointer */
3760 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3761 /* Read 8bit CRC to flush Data Register */
3762 tmpreg8 = *ptmpreg8;
3763 /* To avoid GCC warning */
3764 UNUSED(tmpreg8);
3765
3766 hspi->CRCSize--;
3767
3768 if (hspi->CRCSize == 0U)
3769 {
3770 SPI_CloseRx_ISR(hspi);
3771 }
3772 }
3773 #endif /* USE_SPI_CRC */
3774
3775 /**
3776 * @brief Manage the receive 8-bit in Interrupt context.
3777 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3778 * the configuration information for SPI module.
3779 * @retval None
3780 */
SPI_RxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3781 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3782 {
3783 *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
3784 hspi->pRxBuffPtr++;
3785 hspi->RxXferCount--;
3786
3787 #if (USE_SPI_CRC != 0U)
3788 /* Enable CRC Transmission */
3789 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3790 {
3791 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3792 }
3793 #endif /* USE_SPI_CRC */
3794
3795 if (hspi->RxXferCount == 0U)
3796 {
3797 #if (USE_SPI_CRC != 0U)
3798 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3799 {
3800 hspi->RxISR = SPI_RxISR_8BITCRC;
3801 return;
3802 }
3803 #endif /* USE_SPI_CRC */
3804 SPI_CloseRx_ISR(hspi);
3805 }
3806 }
3807
3808 #if (USE_SPI_CRC != 0U)
3809 /**
3810 * @brief Manage the CRC 16-bit receive in Interrupt context.
3811 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3812 * the configuration information for SPI module.
3813 * @retval None
3814 */
SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef * hspi)3815 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3816 {
3817 __IO uint32_t tmpreg = 0U;
3818
3819 /* Read 16bit CRC to flush Data Register */
3820 tmpreg = READ_REG(hspi->Instance->DR);
3821 /* To avoid GCC warning */
3822 UNUSED(tmpreg);
3823
3824 /* Disable RXNE and ERR interrupt */
3825 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3826
3827 SPI_CloseRx_ISR(hspi);
3828 }
3829 #endif /* USE_SPI_CRC */
3830
3831 /**
3832 * @brief Manage the 16-bit receive in Interrupt context.
3833 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3834 * the configuration information for SPI module.
3835 * @retval None
3836 */
SPI_RxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3837 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3838 {
3839 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3840 hspi->pRxBuffPtr += sizeof(uint16_t);
3841 hspi->RxXferCount--;
3842
3843 #if (USE_SPI_CRC != 0U)
3844 /* Enable CRC Transmission */
3845 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3846 {
3847 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3848 }
3849 #endif /* USE_SPI_CRC */
3850
3851 if (hspi->RxXferCount == 0U)
3852 {
3853 #if (USE_SPI_CRC != 0U)
3854 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3855 {
3856 hspi->RxISR = SPI_RxISR_16BITCRC;
3857 return;
3858 }
3859 #endif /* USE_SPI_CRC */
3860 SPI_CloseRx_ISR(hspi);
3861 }
3862 }
3863
3864 /**
3865 * @brief Handle the data 8-bit transmit in Interrupt mode.
3866 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3867 * the configuration information for SPI module.
3868 * @retval None
3869 */
SPI_TxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3870 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3871 {
3872 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3873 hspi->pTxBuffPtr++;
3874 hspi->TxXferCount--;
3875
3876 if (hspi->TxXferCount == 0U)
3877 {
3878 #if (USE_SPI_CRC != 0U)
3879 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3880 {
3881 /* Enable CRC Transmission */
3882 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3883 }
3884 #endif /* USE_SPI_CRC */
3885 SPI_CloseTx_ISR(hspi);
3886 }
3887 }
3888
3889 /**
3890 * @brief Handle the data 16-bit transmit in Interrupt mode.
3891 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3892 * the configuration information for SPI module.
3893 * @retval None
3894 */
SPI_TxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3895 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3896 {
3897 /* Transmit data in 16 Bit mode */
3898 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3899 hspi->pTxBuffPtr += sizeof(uint16_t);
3900 hspi->TxXferCount--;
3901
3902 if (hspi->TxXferCount == 0U)
3903 {
3904 #if (USE_SPI_CRC != 0U)
3905 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3906 {
3907 /* Enable CRC Transmission */
3908 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3909 }
3910 #endif /* USE_SPI_CRC */
3911 SPI_CloseTx_ISR(hspi);
3912 }
3913 }
3914
3915 /**
3916 * @brief Handle SPI Communication Timeout.
3917 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3918 * the configuration information for SPI module.
3919 * @param Flag SPI flag to check
3920 * @param State flag state to check
3921 * @param Timeout Timeout duration
3922 * @param Tickstart tick start value
3923 * @retval HAL status
3924 */
SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef * hspi,uint32_t Flag,FlagStatus State,uint32_t Timeout,uint32_t Tickstart)3925 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
3926 uint32_t Timeout, uint32_t Tickstart)
3927 {
3928 __IO uint32_t count;
3929 uint32_t tmp_timeout;
3930 uint32_t tmp_tickstart;
3931
3932 /* Adjust Timeout value in case of end of transfer */
3933 tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
3934 tmp_tickstart = HAL_GetTick();
3935
3936 /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
3937 count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
3938
3939 while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
3940 {
3941 if (Timeout != HAL_MAX_DELAY)
3942 {
3943 if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
3944 {
3945 /* Disable the SPI and reset the CRC: the CRC value should be cleared
3946 on both master and slave sides in order to resynchronize the master
3947 and slave for their respective CRC calculation */
3948
3949 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
3950 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
3951
3952 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3953 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3954 {
3955 /* Disable SPI peripheral */
3956 __HAL_SPI_DISABLE(hspi);
3957 }
3958
3959 /* Reset CRC Calculation */
3960 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3961 {
3962 SPI_RESET_CRC(hspi);
3963 }
3964
3965 hspi->State = HAL_SPI_STATE_READY;
3966
3967 /* Process Unlocked */
3968 __HAL_UNLOCK(hspi);
3969
3970 return HAL_TIMEOUT;
3971 }
3972 /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
3973 if (count == 0U)
3974 {
3975 tmp_timeout = 0U;
3976 }
3977 count--;
3978 }
3979 }
3980
3981 return HAL_OK;
3982 }
3983
3984 /**
3985 * @brief Handle SPI FIFO Communication Timeout.
3986 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3987 * the configuration information for SPI module.
3988 * @param Fifo Fifo to check
3989 * @param State Fifo state to check
3990 * @param Timeout Timeout duration
3991 * @param Tickstart tick start value
3992 * @retval HAL status
3993 */
SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef * hspi,uint32_t Fifo,uint32_t State,uint32_t Timeout,uint32_t Tickstart)3994 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
3995 uint32_t Timeout, uint32_t Tickstart)
3996 {
3997 __IO uint32_t count;
3998 uint32_t tmp_timeout;
3999 uint32_t tmp_tickstart;
4000 __IO uint8_t *ptmpreg8;
4001 __IO uint8_t tmpreg8 = 0;
4002
4003 /* Adjust Timeout value in case of end of transfer */
4004 tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
4005 tmp_tickstart = HAL_GetTick();
4006
4007 /* Initialize the 8bit temporary pointer */
4008 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
4009
4010 /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
4011 count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U);
4012
4013 while ((hspi->Instance->SR & Fifo) != State)
4014 {
4015 if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
4016 {
4017 /* Flush Data Register by a blank read */
4018 tmpreg8 = *ptmpreg8;
4019 /* To avoid GCC warning */
4020 UNUSED(tmpreg8);
4021 }
4022
4023 if (Timeout != HAL_MAX_DELAY)
4024 {
4025 if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
4026 {
4027 /* Disable the SPI and reset the CRC: the CRC value should be cleared
4028 on both master and slave sides in order to resynchronize the master
4029 and slave for their respective CRC calculation */
4030
4031 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
4032 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
4033
4034 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
4035 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
4036 {
4037 /* Disable SPI peripheral */
4038 __HAL_SPI_DISABLE(hspi);
4039 }
4040
4041 /* Reset CRC Calculation */
4042 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
4043 {
4044 SPI_RESET_CRC(hspi);
4045 }
4046
4047 hspi->State = HAL_SPI_STATE_READY;
4048
4049 /* Process Unlocked */
4050 __HAL_UNLOCK(hspi);
4051
4052 return HAL_TIMEOUT;
4053 }
4054 /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
4055 if (count == 0U)
4056 {
4057 tmp_timeout = 0U;
4058 }
4059 count--;
4060 }
4061 }
4062
4063 return HAL_OK;
4064 }
4065
4066 /**
4067 * @brief Handle the check of the RX transaction complete.
4068 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4069 * the configuration information for SPI module.
4070 * @param Timeout Timeout duration
4071 * @param Tickstart tick start value
4072 * @retval HAL status
4073 */
SPI_EndRxTransaction(SPI_HandleTypeDef * hspi,uint32_t Timeout,uint32_t Tickstart)4074 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
4075 {
4076 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
4077 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
4078 {
4079 /* Disable SPI peripheral */
4080 __HAL_SPI_DISABLE(hspi);
4081 }
4082
4083 /* Control the BSY flag */
4084 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
4085 {
4086 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4087 return HAL_TIMEOUT;
4088 }
4089
4090 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
4091 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
4092 {
4093 /* Empty the FRLVL fifo */
4094 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
4095 {
4096 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4097 return HAL_TIMEOUT;
4098 }
4099 }
4100 return HAL_OK;
4101 }
4102
4103 /**
4104 * @brief Handle the check of the RXTX or TX transaction complete.
4105 * @param hspi SPI handle
4106 * @param Timeout Timeout duration
4107 * @param Tickstart tick start value
4108 * @retval HAL status
4109 */
SPI_EndRxTxTransaction(SPI_HandleTypeDef * hspi,uint32_t Timeout,uint32_t Tickstart)4110 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
4111 {
4112 /* Control if the TX fifo is empty */
4113 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
4114 {
4115 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4116 return HAL_TIMEOUT;
4117 }
4118
4119 /* Control the BSY flag */
4120 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
4121 {
4122 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4123 return HAL_TIMEOUT;
4124 }
4125
4126 /* Control if the RX fifo is empty */
4127 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
4128 {
4129 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4130 return HAL_TIMEOUT;
4131 }
4132
4133 return HAL_OK;
4134 }
4135
4136 /**
4137 * @brief Handle the end of the RXTX transaction.
4138 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4139 * the configuration information for SPI module.
4140 * @retval None
4141 */
SPI_CloseRxTx_ISR(SPI_HandleTypeDef * hspi)4142 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
4143 {
4144 uint32_t tickstart;
4145
4146 /* Init tickstart for timeout management */
4147 tickstart = HAL_GetTick();
4148
4149 /* Disable ERR interrupt */
4150 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
4151
4152 /* Check the end of the transaction */
4153 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
4154 {
4155 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4156 }
4157
4158 #if (USE_SPI_CRC != 0U)
4159 /* Check if CRC error occurred */
4160 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
4161 {
4162 hspi->State = HAL_SPI_STATE_READY;
4163 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
4164 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
4165 /* Call user error callback */
4166 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4167 hspi->ErrorCallback(hspi);
4168 #else
4169 HAL_SPI_ErrorCallback(hspi);
4170 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4171 }
4172 else
4173 {
4174 #endif /* USE_SPI_CRC */
4175 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
4176 {
4177 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
4178 {
4179 hspi->State = HAL_SPI_STATE_READY;
4180 /* Call user Rx complete callback */
4181 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4182 hspi->RxCpltCallback(hspi);
4183 #else
4184 HAL_SPI_RxCpltCallback(hspi);
4185 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4186 }
4187 else
4188 {
4189 hspi->State = HAL_SPI_STATE_READY;
4190 /* Call user TxRx complete callback */
4191 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4192 hspi->TxRxCpltCallback(hspi);
4193 #else
4194 HAL_SPI_TxRxCpltCallback(hspi);
4195 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4196 }
4197 }
4198 else
4199 {
4200 hspi->State = HAL_SPI_STATE_READY;
4201 /* Call user error callback */
4202 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4203 hspi->ErrorCallback(hspi);
4204 #else
4205 HAL_SPI_ErrorCallback(hspi);
4206 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4207 }
4208 #if (USE_SPI_CRC != 0U)
4209 }
4210 #endif /* USE_SPI_CRC */
4211 }
4212
4213 /**
4214 * @brief Handle the end of the RX transaction.
4215 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4216 * the configuration information for SPI module.
4217 * @retval None
4218 */
SPI_CloseRx_ISR(SPI_HandleTypeDef * hspi)4219 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
4220 {
4221 /* Disable RXNE and ERR interrupt */
4222 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
4223
4224 /* Check the end of the transaction */
4225 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4226 {
4227 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4228 }
4229 hspi->State = HAL_SPI_STATE_READY;
4230
4231 #if (USE_SPI_CRC != 0U)
4232 /* Check if CRC error occurred */
4233 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
4234 {
4235 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
4236 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
4237 /* Call user error callback */
4238 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4239 hspi->ErrorCallback(hspi);
4240 #else
4241 HAL_SPI_ErrorCallback(hspi);
4242 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4243 }
4244 else
4245 {
4246 #endif /* USE_SPI_CRC */
4247 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
4248 {
4249 /* Call user Rx complete callback */
4250 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4251 hspi->RxCpltCallback(hspi);
4252 #else
4253 HAL_SPI_RxCpltCallback(hspi);
4254 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4255 }
4256 else
4257 {
4258 /* Call user error callback */
4259 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4260 hspi->ErrorCallback(hspi);
4261 #else
4262 HAL_SPI_ErrorCallback(hspi);
4263 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4264 }
4265 #if (USE_SPI_CRC != 0U)
4266 }
4267 #endif /* USE_SPI_CRC */
4268 }
4269
4270 /**
4271 * @brief Handle the end of the TX transaction.
4272 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4273 * the configuration information for SPI module.
4274 * @retval None
4275 */
SPI_CloseTx_ISR(SPI_HandleTypeDef * hspi)4276 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
4277 {
4278 uint32_t tickstart;
4279
4280 /* Init tickstart for timeout management*/
4281 tickstart = HAL_GetTick();
4282
4283 /* Disable TXE and ERR interrupt */
4284 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
4285
4286 /* Check the end of the transaction */
4287 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
4288 {
4289 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4290 }
4291
4292 /* Clear overrun flag in 2 Lines communication mode because received is not read */
4293 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
4294 {
4295 __HAL_SPI_CLEAR_OVRFLAG(hspi);
4296 }
4297
4298 hspi->State = HAL_SPI_STATE_READY;
4299 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
4300 {
4301 /* Call user error callback */
4302 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4303 hspi->ErrorCallback(hspi);
4304 #else
4305 HAL_SPI_ErrorCallback(hspi);
4306 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4307 }
4308 else
4309 {
4310 /* Call user Rx complete callback */
4311 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4312 hspi->TxCpltCallback(hspi);
4313 #else
4314 HAL_SPI_TxCpltCallback(hspi);
4315 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4316 }
4317 }
4318
4319 /**
4320 * @brief Handle abort a Rx transaction.
4321 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4322 * the configuration information for SPI module.
4323 * @retval None
4324 */
SPI_AbortRx_ISR(SPI_HandleTypeDef * hspi)4325 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
4326 {
4327 __IO uint32_t count;
4328
4329 /* Disable SPI Peripheral */
4330 __HAL_SPI_DISABLE(hspi);
4331
4332 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
4333
4334 /* Disable RXNEIE interrupt */
4335 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
4336
4337 /* Check RXNEIE is disabled */
4338 do
4339 {
4340 if (count == 0U)
4341 {
4342 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4343 break;
4344 }
4345 count--;
4346 } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
4347
4348 /* Control the BSY flag */
4349 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4350 {
4351 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4352 }
4353
4354 /* Empty the FRLVL fifo */
4355 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4356 {
4357 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4358 }
4359
4360 hspi->State = HAL_SPI_STATE_ABORT;
4361 }
4362
4363 /**
4364 * @brief Handle abort a Tx or Rx/Tx transaction.
4365 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4366 * the configuration information for SPI module.
4367 * @retval None
4368 */
SPI_AbortTx_ISR(SPI_HandleTypeDef * hspi)4369 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
4370 {
4371 __IO uint32_t count;
4372
4373 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
4374
4375 /* Disable TXEIE interrupt */
4376 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
4377
4378 /* Check TXEIE is disabled */
4379 do
4380 {
4381 if (count == 0U)
4382 {
4383 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4384 break;
4385 }
4386 count--;
4387 } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
4388
4389 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4390 {
4391 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4392 }
4393
4394 /* Disable SPI Peripheral */
4395 __HAL_SPI_DISABLE(hspi);
4396
4397 /* Empty the FRLVL fifo */
4398 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4399 {
4400 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4401 }
4402
4403 /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */
4404 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
4405 {
4406 /* Disable RXNEIE interrupt */
4407 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
4408
4409 /* Check RXNEIE is disabled */
4410 do
4411 {
4412 if (count == 0U)
4413 {
4414 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4415 break;
4416 }
4417 count--;
4418 } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
4419
4420 /* Control the BSY flag */
4421 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4422 {
4423 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4424 }
4425
4426 /* Empty the FRLVL fifo */
4427 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4428 {
4429 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4430 }
4431 }
4432 hspi->State = HAL_SPI_STATE_ABORT;
4433 }
4434
4435 /**
4436 * @}
4437 */
4438
4439 #endif /* HAL_SPI_MODULE_ENABLED */
4440
4441 /**
4442 * @}
4443 */
4444
4445 /**
4446 * @}
4447 */
4448
4449
