1 /**
2 ******************************************************************************
3 * @file stm32c0xx_ll_adc.c
4 * @author MCD Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32c0xx_ll_adc.h"
22 #include "stm32c0xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32C0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1)
35
36 /** @addtogroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @addtogroup ADC_LL_Private_Constants
44 * @{
45 */
46
47 /* Definitions of ADC hardware constraints delays */
48 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
49 /* not timeout values: */
50 /* Timeout values for ADC operations are dependent to device clock */
51 /* configuration (system clock versus ADC clock), */
52 /* and therefore must be defined in user application. */
53 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
54 /* values definition. */
55 /* Note: ADC timeout values are defined here in CPU cycles to be independent */
56 /* of device clock setting. */
57 /* In user application, ADC timeout values should be defined with */
58 /* temporal values, in function of device clock settings. */
59 /* Highest ratio CPU clock frequency vs ADC clock frequency: */
60 /* - ADC clock from synchronous clock with AHB prescaler 512, */
61 /* APB prescaler 16, ADC prescaler 4. */
62 /* - ADC clock from asynchronous clock (HSI) with prescaler 1, */
63 /* with highest ratio CPU clock frequency vs HSI clock frequency: */
64 /* CPU clock frequency max 48MHz, HSI frequency 16MHz: ratio 4. */
65 /* Unit: CPU cycles. */
66 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
67 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
68 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
69 /* Note: CCRDY handshake requires 1APB + 2 ADC + 3 APB cycles */
70 /* after the channel configuration has been changed. */
71 /* Driver timeout is approximated to 6 CPU cycles. */
72 #define ADC_TIMEOUT_CCRDY_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 6UL)
73
74 /**
75 * @}
76 */
77
78 /* Private macros ------------------------------------------------------------*/
79
80 /** @addtogroup ADC_LL_Private_Macros
81 * @{
82 */
83
84 /* Check of parameters for configuration of ADC hierarchical scope: */
85 /* common to several ADC instances. */
86 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
87 (((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
88 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
89 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
90 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
91 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
92 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
93 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
94 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
95 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
96 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
97 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
98 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
99 )
100
101 #define IS_LL_ADC_CLOCK_FREQ_MODE(__CLOCK_FREQ_MODE__) \
102 (((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_HIGH) \
103 || ((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_LOW) \
104 )
105
106 /* Check of parameters for configuration of ADC hierarchical scope: */
107 /* ADC instance. */
108 #define IS_LL_ADC_CLOCK(__CLOCK__) \
109 (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
110 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
111 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
112 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC) \
113 )
114
115 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
116 (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
117 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
118 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
119 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
120 )
121
122 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
123 (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
124 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
125 )
126
127 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
128 (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
129 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
130 || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF) \
131 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF) \
132 )
133
134 /* Check of parameters for configuration of ADC hierarchical scope: */
135 /* ADC group regular */
136 #if defined(TIM2)
137 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
138 (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
139 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
140 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 ) \
141 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
142 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
143 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
144 )
145 #else
146 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
147 (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
148 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
149 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 ) \
150 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
151 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
152 )
153 #endif /* TIM1 */
154
155 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
156 (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
157 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
158 )
159
160 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
161 (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
162 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
163 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
164 )
165
166 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
167 (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
168 || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
169 )
170
171 #define IS_LL_ADC_REG_SEQ_MODE(__REG_SEQ_MODE__) \
172 (((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_FIXED) \
173 || ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_CONFIGURABLE) \
174 )
175
176 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
177 (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
178 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
179 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
180 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
181 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
182 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
183 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
184 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
185 )
186
187 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
188 (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
189 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
190 )
191
192 /**
193 * @}
194 */
195
196
197 /* Private function prototypes -----------------------------------------------*/
198
199 /* Exported functions --------------------------------------------------------*/
200 /** @addtogroup ADC_LL_Exported_Functions
201 * @{
202 */
203
204 /** @addtogroup ADC_LL_EF_Init
205 * @{
206 */
207
208 /**
209 * @brief De-initialize registers of all ADC instances belonging to
210 * the same ADC common instance to their default reset values.
211 * @note This function is performing a hard reset, using high level
212 * clock source RCC ADC reset.
213 * @param ADCxy_COMMON ADC common instance
214 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
215 * @retval An ErrorStatus enumeration value:
216 * - SUCCESS: ADC common registers are de-initialized
217 * - ERROR: not applicable
218 */
LL_ADC_CommonDeInit(const ADC_Common_TypeDef * ADCxy_COMMON)219 ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON)
220 {
221 /* Check the parameters */
222 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
223
224 /* Prevent unused argument(s) compilation warning if no assert_param check */
225 (void)(ADCxy_COMMON);
226
227 /* Force reset of ADC clock (core clock) */
228 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC);
229
230 /* Release reset of ADC clock (core clock) */
231 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC);
232
233 return SUCCESS;
234 }
235
236 /**
237 * @brief Initialize some features of ADC common parameters
238 * (all ADC instances belonging to the same ADC common instance)
239 * and multimode (for devices with several ADC instances available).
240 * @note The setting of ADC common parameters is conditioned to
241 * ADC instances state:
242 * All ADC instances belonging to the same ADC common instance
243 * must be disabled.
244 * @param ADCxy_COMMON ADC common instance
245 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
246 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
247 * @retval An ErrorStatus enumeration value:
248 * - SUCCESS: ADC common registers are initialized
249 * - ERROR: ADC common registers are not initialized
250 */
LL_ADC_CommonInit(ADC_Common_TypeDef * ADCxy_COMMON,LL_ADC_CommonInitTypeDef * ADC_CommonInitStruct)251 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
252 {
253 ErrorStatus status = SUCCESS;
254
255 /* Check the parameters */
256 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
257 assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
258
259 /* Note: Hardware constraint (refer to description of functions */
260 /* "LL_ADC_SetCommonXXX()": */
261 /* On this STM32 series, setting of these features is conditioned to */
262 /* ADC state: */
263 /* All ADC instances of the ADC common group must be disabled. */
264 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
265 {
266 /* Configuration of ADC hierarchical scope: */
267 /* - common to several ADC */
268 /* (all ADC instances belonging to the same ADC common instance) */
269 /* - Set ADC clock (conversion clock) */
270 LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
271 }
272 else
273 {
274 /* Initialization error: One or several ADC instances belonging to */
275 /* the same ADC common instance are not disabled. */
276 status = ERROR;
277 }
278
279 return status;
280 }
281
282 /**
283 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
284 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
285 * whose fields will be set to default values.
286 * @retval None
287 */
LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef * ADC_CommonInitStruct)288 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
289 {
290 /* Set ADC_CommonInitStruct fields to default values */
291 /* Set fields of ADC common */
292 /* (all ADC instances belonging to the same ADC common instance) */
293 ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2;
294
295 }
296
297 /**
298 * @brief De-initialize registers of the selected ADC instance
299 * to their default reset values.
300 * @note To reset all ADC instances quickly (perform a hard reset),
301 * use function @ref LL_ADC_CommonDeInit().
302 * @note If this functions returns error status, it means that ADC instance
303 * is in an unknown state.
304 * In this case, perform a hard reset using high level
305 * clock source RCC ADC reset.
306 * Refer to function @ref LL_ADC_CommonDeInit().
307 * @param ADCx ADC instance
308 * @retval An ErrorStatus enumeration value:
309 * - SUCCESS: ADC registers are de-initialized
310 * - ERROR: ADC registers are not de-initialized
311 */
LL_ADC_DeInit(ADC_TypeDef * ADCx)312 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
313 {
314 ErrorStatus status = SUCCESS;
315
316 __IO uint32_t timeout_cpu_cycles = 0UL;
317
318 /* Check the parameters */
319 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
320
321 /* Disable ADC instance if not already disabled. */
322 if (LL_ADC_IsEnabled(ADCx) == 1UL)
323 {
324 /* Set ADC group regular trigger source to SW start to ensure to not */
325 /* have an external trigger event occurring during the conversion stop */
326 /* ADC disable process. */
327 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
328
329 /* Stop potential ADC conversion on going on ADC group regular. */
330 if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
331 {
332 if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL)
333 {
334 LL_ADC_REG_StopConversion(ADCx);
335 }
336 }
337
338 /* Wait for ADC conversions are effectively stopped */
339 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
340 while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1UL)
341 {
342 timeout_cpu_cycles--;
343 if (timeout_cpu_cycles == 0UL)
344 {
345 /* Time-out error */
346 status = ERROR;
347 break;
348 }
349 }
350
351 /* Disable the ADC instance */
352 LL_ADC_Disable(ADCx);
353
354 /* Wait for ADC instance is effectively disabled */
355 timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
356 while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
357 {
358 timeout_cpu_cycles--;
359 if (timeout_cpu_cycles == 0UL)
360 {
361 /* Time-out error */
362 status = ERROR;
363 break;
364 }
365 }
366 }
367
368 /* Check whether ADC state is compliant with expected state */
369 if (READ_BIT(ADCx->CR,
370 (ADC_CR_ADSTP | ADC_CR_ADSTART
371 | ADC_CR_ADDIS | ADC_CR_ADEN)
372 )
373 == 0UL)
374 {
375 /* ========== Reset ADC registers ========== */
376 /* Reset register IER */
377 CLEAR_BIT(ADCx->IER,
378 (LL_ADC_IT_ADRDY
379 | LL_ADC_IT_EOC
380 | LL_ADC_IT_EOS
381 | LL_ADC_IT_OVR
382 | LL_ADC_IT_EOSMP
383 | LL_ADC_IT_AWD1
384 | LL_ADC_IT_AWD2
385 | LL_ADC_IT_AWD3
386 | LL_ADC_IT_EOCAL
387 | LL_ADC_IT_CCRDY
388 )
389 );
390
391 /* Reset register ISR */
392 SET_BIT(ADCx->ISR,
393 (LL_ADC_FLAG_ADRDY
394 | LL_ADC_FLAG_EOC
395 | LL_ADC_FLAG_EOS
396 | LL_ADC_FLAG_OVR
397 | LL_ADC_FLAG_EOSMP
398 | LL_ADC_FLAG_AWD1
399 | LL_ADC_FLAG_AWD2
400 | LL_ADC_FLAG_AWD3
401 | LL_ADC_FLAG_EOCAL
402 | LL_ADC_FLAG_CCRDY
403 )
404 );
405
406 /* Reset register CR */
407 /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
408 /* "read-set": no direct reset applicable. */
409 CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN);
410
411 /* Reset register CFGR1 */
412 CLEAR_BIT(ADCx->CFGR1,
413 (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN
414 | ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD
415 | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES
416 | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN)
417 );
418
419 /* Reset register CFGR2 */
420 /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
421 /* already done above. */
422 CLEAR_BIT(ADCx->CFGR2,
423 (ADC_CFGR2_CKMODE
424 | ADC_CFGR2_TOVS | ADC_CFGR2_OVSS | ADC_CFGR2_OVSR
425 | ADC_CFGR2_OVSE)
426 );
427
428 /* Reset register SMPR */
429 CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP1 | ADC_SMPR_SMP2 | ADC_SMPR_SMPSEL);
430
431 /* Reset register AWD1TR */
432 MODIFY_REG(ADCx->AWD1TR, ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1, ADC_AWD1TR_HT1);
433
434 /* Reset register AWD2TR */
435 MODIFY_REG(ADCx->AWD2TR, ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2, ADC_AWD2TR_HT2);
436
437 /* Reset register AWD3TR */
438 MODIFY_REG(ADCx->AWD3TR, ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3, ADC_AWD3TR_HT3);
439
440 /* Reset register CHSELR */
441 CLEAR_BIT(ADCx->CHSELR,
442 (ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
443 | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
444 | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8
445 | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4
446 | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0)
447 );
448
449 /* Wait for ADC channel configuration ready */
450 timeout_cpu_cycles = ADC_TIMEOUT_CCRDY_CPU_CYCLES;
451 while (LL_ADC_IsActiveFlag_CCRDY(ADCx) == 0UL)
452 {
453 timeout_cpu_cycles--;
454 if (timeout_cpu_cycles == 0UL)
455 {
456 /* Time-out error */
457 status = ERROR;
458 break;
459 }
460 }
461
462 /* Clear flag ADC channel configuration ready */
463 LL_ADC_ClearFlag_CCRDY(ADCx);
464
465 /* Reset register DR */
466 /* bits in access mode read only, no direct reset applicable */
467
468 /* Reset register CALFACT */
469 CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT);
470
471 }
472 else
473 {
474 /* ADC instance is in an unknown state */
475 /* Need to performing a hard reset of ADC instance, using high level */
476 /* clock source RCC ADC reset. */
477 /* Caution: On this STM32 series, if several ADC instances are available */
478 /* on the selected device, RCC ADC reset will reset */
479 /* all ADC instances belonging to the common ADC instance. */
480 status = ERROR;
481 }
482
483 return status;
484 }
485
486 /**
487 * @brief Initialize some features of ADC instance.
488 * @note These parameters have an impact on ADC scope: ADC instance.
489 * Refer to corresponding unitary functions into
490 * @ref ADC_LL_EF_Configuration_ADC_Instance .
491 * @note The setting of these parameters by function @ref LL_ADC_Init()
492 * is conditioned to ADC state:
493 * ADC instance must be disabled.
494 * This condition is applied to all ADC features, for efficiency
495 * and compatibility over all STM32 families. However, the different
496 * features can be set under different ADC state conditions
497 * (setting possible with ADC enabled without conversion on going,
498 * ADC enabled with conversion on going, ...)
499 * Each feature can be updated afterwards with a unitary function
500 * and potentially with ADC in a different state than disabled,
501 * refer to description of each function for setting
502 * conditioned to ADC state.
503 * @note After using this function, some other features must be configured
504 * using LL unitary functions.
505 * The minimum configuration remaining to be done is:
506 * - Set ADC group regular sequencer:
507 * Depending on the sequencer mode (refer to
508 * function @ref LL_ADC_REG_SetSequencerConfigurable() ):
509 * - map channel on the selected sequencer rank.
510 * Refer to function @ref LL_ADC_REG_SetSequencerRanks();
511 * - map channel on rank corresponding to channel number.
512 * Refer to function @ref LL_ADC_REG_SetSequencerChannels();
513 * - Set ADC channel sampling time
514 * Refer to function LL_ADC_SetSamplingTimeCommonChannels();
515 * Refer to function LL_ADC_SetChannelSamplingTime();
516 * @param ADCx ADC instance
517 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
518 * @retval An ErrorStatus enumeration value:
519 * - SUCCESS: ADC registers are initialized
520 * - ERROR: ADC registers are not initialized
521 */
LL_ADC_Init(ADC_TypeDef * ADCx,LL_ADC_InitTypeDef * ADC_InitStruct)522 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
523 {
524 ErrorStatus status = SUCCESS;
525
526 /* Check the parameters */
527 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
528
529 assert_param(IS_LL_ADC_CLOCK(ADC_InitStruct->Clock));
530 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
531 assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
532 assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
533
534 /* Note: Hardware constraint (refer to description of this function): */
535 /* ADC instance must be disabled. */
536 if (LL_ADC_IsEnabled(ADCx) == 0UL)
537 {
538 /* Configuration of ADC hierarchical scope: */
539 /* - ADC instance */
540 /* - Set ADC data resolution */
541 /* - Set ADC conversion data alignment */
542 /* - Set ADC low power mode */
543 MODIFY_REG(ADCx->CFGR1,
544 ADC_CFGR1_RES
545 | ADC_CFGR1_ALIGN
546 | ADC_CFGR1_WAIT
547 | ADC_CFGR1_AUTOFF
548 ,
549 ADC_InitStruct->Resolution
550 | ADC_InitStruct->DataAlignment
551 | ADC_InitStruct->LowPowerMode
552 );
553
554 MODIFY_REG(ADCx->CFGR2,
555 ADC_CFGR2_CKMODE
556 ,
557 ADC_InitStruct->Clock
558 );
559 }
560 else
561 {
562 /* Initialization error: ADC instance is not disabled. */
563 status = ERROR;
564 }
565
566 return status;
567 }
568
569 /**
570 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
571 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
572 * whose fields will be set to default values.
573 * @retval None
574 */
LL_ADC_StructInit(LL_ADC_InitTypeDef * ADC_InitStruct)575 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
576 {
577 /* Set ADC_InitStruct fields to default values */
578 /* Set fields of ADC instance */
579 ADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
580 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
581 ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
582 ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
583
584 }
585
586 /**
587 * @brief Initialize some features of ADC group regular.
588 * @note These parameters have an impact on ADC scope: ADC group regular.
589 * Refer to corresponding unitary functions into
590 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
591 * (functions with prefix "REG").
592 * @note The setting of these parameters by function @ref LL_ADC_Init()
593 * is conditioned to ADC state:
594 * ADC instance must be disabled.
595 * This condition is applied to all ADC features, for efficiency
596 * and compatibility over all STM32 families. However, the different
597 * features can be set under different ADC state conditions
598 * (setting possible with ADC enabled without conversion on going,
599 * ADC enabled with conversion on going, ...)
600 * Each feature can be updated afterwards with a unitary function
601 * and potentially with ADC in a different state than disabled,
602 * refer to description of each function for setting
603 * conditioned to ADC state.
604 * @note Before using this function, ADC group regular sequencer
605 * must be configured: refer to function
606 * @ref LL_ADC_REG_SetSequencerConfigurable().
607 * @note After using this function, other features must be configured
608 * using LL unitary functions.
609 * The minimum configuration remaining to be done is:
610 * - Set ADC group regular sequencer:
611 * Depending on the sequencer mode (refer to
612 * function @ref LL_ADC_REG_SetSequencerConfigurable() ):
613 * - map channel on the selected sequencer rank.
614 * Refer to function @ref LL_ADC_REG_SetSequencerRanks();
615 * - map channel on rank corresponding to channel number.
616 * Refer to function @ref LL_ADC_REG_SetSequencerChannels();
617 * - Set ADC channel sampling time
618 * Refer to function LL_ADC_SetSamplingTimeCommonChannels();
619 * Refer to function LL_ADC_SetChannelSamplingTime();
620 * @param ADCx ADC instance
621 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
622 * @retval An ErrorStatus enumeration value:
623 * - SUCCESS: ADC registers are initialized
624 * - ERROR: ADC registers are not initialized
625 */
LL_ADC_REG_Init(ADC_TypeDef * ADCx,LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct)626 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
627 {
628 ErrorStatus status = SUCCESS;
629
630 /* Check the parameters */
631 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
632 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
633 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
634 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
635 assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
636
637 if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
638 {
639 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
640 }
641
642 if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
643 || (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
644 )
645 {
646 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
647
648 /* ADC group regular continuous mode and discontinuous mode */
649 /* can not be enabled simultenaeously */
650 assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
651 || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
652 }
653
654 /* Note: Hardware constraint (refer to description of this function): */
655 /* ADC instance must be disabled. */
656 if (LL_ADC_IsEnabled(ADCx) == 0UL)
657 {
658 /* Configuration of ADC hierarchical scope: */
659 /* - ADC group regular */
660 /* - Set ADC group regular trigger source */
661 /* - Set ADC group regular sequencer length */
662 /* - Set ADC group regular sequencer discontinuous mode */
663 /* - Set ADC group regular continuous mode */
664 /* - Set ADC group regular conversion data transfer: no transfer or */
665 /* transfer by DMA, and DMA requests mode */
666 /* - Set ADC group regular overrun behavior */
667 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
668 /* setting of trigger source to SW start. */
669 if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
670 || (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
671 )
672 {
673 /* Case of sequencer mode fixed
674 or sequencer length >= 2 ranks with sequencer mode fully configurable:
675 discontinuous mode configured */
676 MODIFY_REG(ADCx->CFGR1,
677 ADC_CFGR1_EXTSEL
678 | ADC_CFGR1_EXTEN
679 | ADC_CFGR1_DISCEN
680 | ADC_CFGR1_CONT
681 | ADC_CFGR1_DMAEN
682 | ADC_CFGR1_DMACFG
683 | ADC_CFGR1_OVRMOD
684 ,
685 ADC_REG_InitStruct->TriggerSource
686 | ADC_REG_InitStruct->SequencerDiscont
687 | ADC_REG_InitStruct->ContinuousMode
688 | ADC_REG_InitStruct->DMATransfer
689 | ADC_REG_InitStruct->Overrun
690 );
691 }
692 else
693 {
694 /* Case of sequencer mode fully configurable
695 and sequencer length 1 rank (sequencer disabled):
696 discontinuous mode discarded (fixed to disable) */
697 MODIFY_REG(ADCx->CFGR1,
698 ADC_CFGR1_EXTSEL
699 | ADC_CFGR1_EXTEN
700 | ADC_CFGR1_DISCEN
701 | ADC_CFGR1_CONT
702 | ADC_CFGR1_DMAEN
703 | ADC_CFGR1_DMACFG
704 | ADC_CFGR1_OVRMOD
705 ,
706 ADC_REG_InitStruct->TriggerSource
707 | LL_ADC_REG_SEQ_DISCONT_DISABLE
708 | ADC_REG_InitStruct->ContinuousMode
709 | ADC_REG_InitStruct->DMATransfer
710 | ADC_REG_InitStruct->Overrun
711 );
712 }
713
714 /* Set ADC group regular sequencer length */
715 if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
716 {
717 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
718 }
719 }
720 else
721 {
722 /* Initialization error: ADC instance is not disabled. */
723 status = ERROR;
724 }
725 return status;
726 }
727
728 /**
729 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
730 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
731 * whose fields will be set to default values.
732 * @retval None
733 */
LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct)734 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
735 {
736 /* Set ADC_REG_InitStruct fields to default values */
737 /* Set fields of ADC group regular */
738 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
739 /* setting of trigger source to SW start. */
740 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
741 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
742 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
743 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
744 ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
745 ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
746 }
747
748 /**
749 * @}
750 */
751
752 /**
753 * @}
754 */
755
756 /**
757 * @}
758 */
759
760 #endif /* ADC1 */
761
762 /**
763 * @}
764 */
765
766 #endif /* USE_FULL_LL_DRIVER */
767
