1 /**
2 ******************************************************************************
3 * @file stm32c0xx_hal_tim_ex.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer Extended peripheral:
8 * + Time Hall Sensor Interface Initialization
9 * + Time Hall Sensor Interface Start
10 * + Time Complementary signal break and dead time configuration
11 * + Time Master and Slave synchronization configuration
12 * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
13 * + Time OCRef clear configuration
14 * + Timer remapping capabilities configuration
15 ******************************************************************************
16 * @attention
17 *
18 * Copyright (c) 2022 STMicroelectronics.
19 * All rights reserved.
20 *
21 * This software is licensed under terms that can be found in the LICENSE file
22 * in the root directory of this software component.
23 * If no LICENSE file comes with this software, it is provided AS-IS.
24 *
25 ******************************************************************************
26 @verbatim
27 ==============================================================================
28 ##### TIMER Extended features #####
29 ==============================================================================
30 [..]
31 The Timer Extended features include:
32 (#) Complementary outputs with programmable dead-time for :
33 (++) Output Compare
34 (++) PWM generation (Edge and Center-aligned Mode)
35 (++) One-pulse mode output
36 (#) Synchronization circuit to control the timer with external signals and to
37 interconnect several timers together.
38 (#) Break input to put the timer output signals in reset state or in a known state.
39 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
40 positioning purposes
41
42 ##### How to use this driver #####
43 ==============================================================================
44 [..]
45 (#) Initialize the TIM low level resources by implementing the following functions
46 depending on the selected feature:
47 (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
48
49 (#) Initialize the TIM low level resources :
50 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
51 (##) TIM pins configuration
52 (+++) Enable the clock for the TIM GPIOs using the following function:
53 __HAL_RCC_GPIOx_CLK_ENABLE();
54 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
55
56 (#) The external Clock can be configured, if needed (the default clock is the
57 internal clock from the APBx), using the following function:
58 HAL_TIM_ConfigClockSource, the clock configuration should be done before
59 any start function.
60
61 (#) Configure the TIM in the desired functioning mode using one of the
62 initialization function of this driver:
63 (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
64 Timer Hall Sensor Interface and the commutation event with the corresponding
65 Interrupt and DMA request if needed (Note that One Timer is used to interface
66 with the Hall sensor Interface and another Timer should be used to use
67 the commutation event).
68
69 (#) Activate the TIM peripheral using one of the start functions:
70 (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
71 HAL_TIMEx_OCN_Start_IT()
72 (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
73 HAL_TIMEx_PWMN_Start_IT()
74 (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
75 (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(),
76 HAL_TIMEx_HallSensor_Start_IT().
77
78 @endverbatim
79 ******************************************************************************
80 */
81
82 /* Includes ------------------------------------------------------------------*/
83 #include "stm32c0xx_hal.h"
84
85 /** @addtogroup STM32C0xx_HAL_Driver
86 * @{
87 */
88
89 /** @defgroup TIMEx TIMEx
90 * @brief TIM Extended HAL module driver
91 * @{
92 */
93
94 #ifdef HAL_TIM_MODULE_ENABLED
95
96 /* Private typedef -----------------------------------------------------------*/
97 /* Private define ------------------------------------------------------------*/
98 /* Private constants ---------------------------------------------------------*/
99 /** @defgroup TIMEx_Private_Constants TIM Extended Private Constants
100 * @{
101 */
102 /* Timeout for break input rearm */
103 #define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */
104 /**
105 * @}
106 */
107 /* End of private constants --------------------------------------------------*/
108
109 /* Private macros ------------------------------------------------------------*/
110 /* Private variables ---------------------------------------------------------*/
111 /* Private function prototypes -----------------------------------------------*/
112 static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
113 static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
114 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
115
116 /* Exported functions --------------------------------------------------------*/
117 /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
118 * @{
119 */
120
121 /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
122 * @brief Timer Hall Sensor functions
123 *
124 @verbatim
125 ==============================================================================
126 ##### Timer Hall Sensor functions #####
127 ==============================================================================
128 [..]
129 This section provides functions allowing to:
130 (+) Initialize and configure TIM HAL Sensor.
131 (+) De-initialize TIM HAL Sensor.
132 (+) Start the Hall Sensor Interface.
133 (+) Stop the Hall Sensor Interface.
134 (+) Start the Hall Sensor Interface and enable interrupts.
135 (+) Stop the Hall Sensor Interface and disable interrupts.
136 (+) Start the Hall Sensor Interface and enable DMA transfers.
137 (+) Stop the Hall Sensor Interface and disable DMA transfers.
138
139 @endverbatim
140 * @{
141 */
142 /**
143 * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
144 * @note When the timer instance is initialized in Hall Sensor Interface mode,
145 * timer channels 1 and channel 2 are reserved and cannot be used for
146 * other purpose.
147 * @param htim TIM Hall Sensor Interface handle
148 * @param sConfig TIM Hall Sensor configuration structure
149 * @retval HAL status
150 */
HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef * htim,const TIM_HallSensor_InitTypeDef * sConfig)151 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig)
152 {
153 TIM_OC_InitTypeDef OC_Config;
154
155 /* Check the TIM handle allocation */
156 if (htim == NULL)
157 {
158 return HAL_ERROR;
159 }
160
161 /* Check the parameters */
162 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
163 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
164 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
165 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
166 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
167 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
168 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
169 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
170
171 if (htim->State == HAL_TIM_STATE_RESET)
172 {
173 /* Allocate lock resource and initialize it */
174 htim->Lock = HAL_UNLOCKED;
175
176 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
177 /* Reset interrupt callbacks to legacy week callbacks */
178 TIM_ResetCallback(htim);
179
180 if (htim->HallSensor_MspInitCallback == NULL)
181 {
182 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
183 }
184 /* Init the low level hardware : GPIO, CLOCK, NVIC */
185 htim->HallSensor_MspInitCallback(htim);
186 #else
187 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
188 HAL_TIMEx_HallSensor_MspInit(htim);
189 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
190 }
191
192 /* Set the TIM state */
193 htim->State = HAL_TIM_STATE_BUSY;
194
195 /* Configure the Time base in the Encoder Mode */
196 TIM_Base_SetConfig(htim->Instance, &htim->Init);
197
198 /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
199 TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
200
201 /* Reset the IC1PSC Bits */
202 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
203 /* Set the IC1PSC value */
204 htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
205
206 /* Enable the Hall sensor interface (XOR function of the three inputs) */
207 htim->Instance->CR2 |= TIM_CR2_TI1S;
208
209 /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
210 htim->Instance->SMCR &= ~TIM_SMCR_TS;
211 htim->Instance->SMCR |= TIM_TS_TI1F_ED;
212
213 /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
214 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
215 htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
216
217 /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
218 OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
219 OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
220 OC_Config.OCMode = TIM_OCMODE_PWM2;
221 OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
222 OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
223 OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
224 OC_Config.Pulse = sConfig->Commutation_Delay;
225
226 TIM_OC2_SetConfig(htim->Instance, &OC_Config);
227
228 /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
229 register to 101 */
230 htim->Instance->CR2 &= ~TIM_CR2_MMS;
231 htim->Instance->CR2 |= TIM_TRGO_OC2REF;
232
233 /* Initialize the DMA burst operation state */
234 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
235
236 /* Initialize the TIM channels state */
237 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
238 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
239 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
240 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
241
242 /* Initialize the TIM state*/
243 htim->State = HAL_TIM_STATE_READY;
244
245 return HAL_OK;
246 }
247
248 /**
249 * @brief DeInitializes the TIM Hall Sensor interface
250 * @param htim TIM Hall Sensor Interface handle
251 * @retval HAL status
252 */
HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef * htim)253 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
254 {
255 /* Check the parameters */
256 assert_param(IS_TIM_INSTANCE(htim->Instance));
257
258 htim->State = HAL_TIM_STATE_BUSY;
259
260 /* Disable the TIM Peripheral Clock */
261 __HAL_TIM_DISABLE(htim);
262
263 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
264 if (htim->HallSensor_MspDeInitCallback == NULL)
265 {
266 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
267 }
268 /* DeInit the low level hardware */
269 htim->HallSensor_MspDeInitCallback(htim);
270 #else
271 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
272 HAL_TIMEx_HallSensor_MspDeInit(htim);
273 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
274
275 /* Change the DMA burst operation state */
276 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
277
278 /* Change the TIM channels state */
279 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
280 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
281 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
282 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
283
284 /* Change TIM state */
285 htim->State = HAL_TIM_STATE_RESET;
286
287 /* Release Lock */
288 __HAL_UNLOCK(htim);
289
290 return HAL_OK;
291 }
292
293 /**
294 * @brief Initializes the TIM Hall Sensor MSP.
295 * @param htim TIM Hall Sensor Interface handle
296 * @retval None
297 */
HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef * htim)298 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
299 {
300 /* Prevent unused argument(s) compilation warning */
301 UNUSED(htim);
302
303 /* NOTE : This function should not be modified, when the callback is needed,
304 the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
305 */
306 }
307
308 /**
309 * @brief DeInitializes TIM Hall Sensor MSP.
310 * @param htim TIM Hall Sensor Interface handle
311 * @retval None
312 */
HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef * htim)313 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
314 {
315 /* Prevent unused argument(s) compilation warning */
316 UNUSED(htim);
317
318 /* NOTE : This function should not be modified, when the callback is needed,
319 the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
320 */
321 }
322
323 /**
324 * @brief Starts the TIM Hall Sensor Interface.
325 * @param htim TIM Hall Sensor Interface handle
326 * @retval HAL status
327 */
HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef * htim)328 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
329 {
330 uint32_t tmpsmcr;
331 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
332 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
333 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
334 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
335
336 /* Check the parameters */
337 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
338
339 /* Check the TIM channels state */
340 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
341 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
342 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
343 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
344 {
345 return HAL_ERROR;
346 }
347
348 /* Set the TIM channels state */
349 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
350 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
351 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
352 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
353
354 /* Enable the Input Capture channel 1
355 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
356 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
357 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
358
359 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
360 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
361 {
362 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
363 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
364 {
365 __HAL_TIM_ENABLE(htim);
366 }
367 }
368 else
369 {
370 __HAL_TIM_ENABLE(htim);
371 }
372
373 /* Return function status */
374 return HAL_OK;
375 }
376
377 /**
378 * @brief Stops the TIM Hall sensor Interface.
379 * @param htim TIM Hall Sensor Interface handle
380 * @retval HAL status
381 */
HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef * htim)382 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
383 {
384 /* Check the parameters */
385 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
386
387 /* Disable the Input Capture channels 1, 2 and 3
388 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
389 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
390 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
391
392 /* Disable the Peripheral */
393 __HAL_TIM_DISABLE(htim);
394
395 /* Set the TIM channels state */
396 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
397 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
398 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
399 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
400
401 /* Return function status */
402 return HAL_OK;
403 }
404
405 /**
406 * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
407 * @param htim TIM Hall Sensor Interface handle
408 * @retval HAL status
409 */
HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef * htim)410 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
411 {
412 uint32_t tmpsmcr;
413 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
414 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
415 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
416 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
417
418 /* Check the parameters */
419 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
420
421 /* Check the TIM channels state */
422 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
423 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
424 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
425 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
426 {
427 return HAL_ERROR;
428 }
429
430 /* Set the TIM channels state */
431 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
432 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
433 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
434 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
435
436 /* Enable the capture compare Interrupts 1 event */
437 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
438
439 /* Enable the Input Capture channel 1
440 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
441 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
442 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
443
444 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
445 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
446 {
447 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
448 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
449 {
450 __HAL_TIM_ENABLE(htim);
451 }
452 }
453 else
454 {
455 __HAL_TIM_ENABLE(htim);
456 }
457
458 /* Return function status */
459 return HAL_OK;
460 }
461
462 /**
463 * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
464 * @param htim TIM Hall Sensor Interface handle
465 * @retval HAL status
466 */
HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef * htim)467 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
468 {
469 /* Check the parameters */
470 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
471
472 /* Disable the Input Capture channel 1
473 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
474 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
475 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
476
477 /* Disable the capture compare Interrupts event */
478 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
479
480 /* Disable the Peripheral */
481 __HAL_TIM_DISABLE(htim);
482
483 /* Set the TIM channels state */
484 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
485 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
486 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
487 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
488
489 /* Return function status */
490 return HAL_OK;
491 }
492
493 /**
494 * @brief Starts the TIM Hall Sensor Interface in DMA mode.
495 * @param htim TIM Hall Sensor Interface handle
496 * @param pData The destination Buffer address.
497 * @param Length The length of data to be transferred from TIM peripheral to memory.
498 * @retval HAL status
499 */
HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef * htim,uint32_t * pData,uint16_t Length)500 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
501 {
502 uint32_t tmpsmcr;
503 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
504 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
505
506 /* Check the parameters */
507 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
508
509 /* Set the TIM channel state */
510 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
511 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
512 {
513 return HAL_BUSY;
514 }
515 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
516 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
517 {
518 if ((pData == NULL) || (Length == 0U))
519 {
520 return HAL_ERROR;
521 }
522 else
523 {
524 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
525 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
526 }
527 }
528 else
529 {
530 return HAL_ERROR;
531 }
532
533 /* Enable the Input Capture channel 1
534 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
535 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
536 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
537
538 /* Set the DMA Input Capture 1 Callbacks */
539 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
540 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
541 /* Set the DMA error callback */
542 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
543
544 /* Enable the DMA channel for Capture 1*/
545 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
546 {
547 /* Return error status */
548 return HAL_ERROR;
549 }
550 /* Enable the capture compare 1 Interrupt */
551 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
552
553 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
554 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
555 {
556 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
557 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
558 {
559 __HAL_TIM_ENABLE(htim);
560 }
561 }
562 else
563 {
564 __HAL_TIM_ENABLE(htim);
565 }
566
567 /* Return function status */
568 return HAL_OK;
569 }
570
571 /**
572 * @brief Stops the TIM Hall Sensor Interface in DMA mode.
573 * @param htim TIM Hall Sensor Interface handle
574 * @retval HAL status
575 */
HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef * htim)576 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
577 {
578 /* Check the parameters */
579 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
580
581 /* Disable the Input Capture channel 1
582 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
583 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
584 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
585
586
587 /* Disable the capture compare Interrupts 1 event */
588 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
589
590 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
591
592 /* Disable the Peripheral */
593 __HAL_TIM_DISABLE(htim);
594
595 /* Set the TIM channel state */
596 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
597 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
598
599 /* Return function status */
600 return HAL_OK;
601 }
602
603 /**
604 * @}
605 */
606
607 /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
608 * @brief Timer Complementary Output Compare functions
609 *
610 @verbatim
611 ==============================================================================
612 ##### Timer Complementary Output Compare functions #####
613 ==============================================================================
614 [..]
615 This section provides functions allowing to:
616 (+) Start the Complementary Output Compare/PWM.
617 (+) Stop the Complementary Output Compare/PWM.
618 (+) Start the Complementary Output Compare/PWM and enable interrupts.
619 (+) Stop the Complementary Output Compare/PWM and disable interrupts.
620 (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
621 (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
622
623 @endverbatim
624 * @{
625 */
626
627 /**
628 * @brief Starts the TIM Output Compare signal generation on the complementary
629 * output.
630 * @param htim TIM Output Compare handle
631 * @param Channel TIM Channel to be enabled
632 * This parameter can be one of the following values:
633 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
634 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
635 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
636 * @retval HAL status
637 */
HAL_TIMEx_OCN_Start(TIM_HandleTypeDef * htim,uint32_t Channel)638 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
639 {
640 uint32_t tmpsmcr;
641
642 /* Check the parameters */
643 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
644
645 /* Check the TIM complementary channel state */
646 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
647 {
648 return HAL_ERROR;
649 }
650
651 /* Set the TIM complementary channel state */
652 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
653
654 /* Enable the Capture compare channel N */
655 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
656
657 /* Enable the Main Output */
658 __HAL_TIM_MOE_ENABLE(htim);
659
660 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
661 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
662 {
663 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
664 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
665 {
666 __HAL_TIM_ENABLE(htim);
667 }
668 }
669 else
670 {
671 __HAL_TIM_ENABLE(htim);
672 }
673
674 /* Return function status */
675 return HAL_OK;
676 }
677
678 /**
679 * @brief Stops the TIM Output Compare signal generation on the complementary
680 * output.
681 * @param htim TIM handle
682 * @param Channel TIM Channel to be disabled
683 * This parameter can be one of the following values:
684 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
685 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
686 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
687 * @retval HAL status
688 */
HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)689 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
690 {
691 /* Check the parameters */
692 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
693
694 /* Disable the Capture compare channel N */
695 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
696
697 /* Disable the Main Output */
698 __HAL_TIM_MOE_DISABLE(htim);
699
700 /* Disable the Peripheral */
701 __HAL_TIM_DISABLE(htim);
702
703 /* Set the TIM complementary channel state */
704 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
705
706 /* Return function status */
707 return HAL_OK;
708 }
709
710 /**
711 * @brief Starts the TIM Output Compare signal generation in interrupt mode
712 * on the complementary output.
713 * @param htim TIM OC handle
714 * @param Channel TIM Channel to be enabled
715 * This parameter can be one of the following values:
716 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
717 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
718 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
719 * @retval HAL status
720 */
HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)721 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
722 {
723 HAL_StatusTypeDef status = HAL_OK;
724 uint32_t tmpsmcr;
725
726 /* Check the parameters */
727 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
728
729 /* Check the TIM complementary channel state */
730 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
731 {
732 return HAL_ERROR;
733 }
734
735 /* Set the TIM complementary channel state */
736 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
737
738 switch (Channel)
739 {
740 case TIM_CHANNEL_1:
741 {
742 /* Enable the TIM Output Compare interrupt */
743 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
744 break;
745 }
746
747 case TIM_CHANNEL_2:
748 {
749 /* Enable the TIM Output Compare interrupt */
750 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
751 break;
752 }
753
754 case TIM_CHANNEL_3:
755 {
756 /* Enable the TIM Output Compare interrupt */
757 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
758 break;
759 }
760
761
762 default:
763 status = HAL_ERROR;
764 break;
765 }
766
767 if (status == HAL_OK)
768 {
769 /* Enable the TIM Break interrupt */
770 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
771
772 /* Enable the Capture compare channel N */
773 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
774
775 /* Enable the Main Output */
776 __HAL_TIM_MOE_ENABLE(htim);
777
778 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
779 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
780 {
781 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
782 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
783 {
784 __HAL_TIM_ENABLE(htim);
785 }
786 }
787 else
788 {
789 __HAL_TIM_ENABLE(htim);
790 }
791 }
792
793 /* Return function status */
794 return status;
795 }
796
797 /**
798 * @brief Stops the TIM Output Compare signal generation in interrupt mode
799 * on the complementary output.
800 * @param htim TIM Output Compare handle
801 * @param Channel TIM Channel to be disabled
802 * This parameter can be one of the following values:
803 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
804 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
805 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
806 * @retval HAL status
807 */
HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)808 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
809 {
810 HAL_StatusTypeDef status = HAL_OK;
811 uint32_t tmpccer;
812
813 /* Check the parameters */
814 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
815
816 switch (Channel)
817 {
818 case TIM_CHANNEL_1:
819 {
820 /* Disable the TIM Output Compare interrupt */
821 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
822 break;
823 }
824
825 case TIM_CHANNEL_2:
826 {
827 /* Disable the TIM Output Compare interrupt */
828 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
829 break;
830 }
831
832 case TIM_CHANNEL_3:
833 {
834 /* Disable the TIM Output Compare interrupt */
835 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
836 break;
837 }
838
839 default:
840 status = HAL_ERROR;
841 break;
842 }
843
844 if (status == HAL_OK)
845 {
846 /* Disable the Capture compare channel N */
847 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
848
849 /* Disable the TIM Break interrupt (only if no more channel is active) */
850 tmpccer = htim->Instance->CCER;
851 if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
852 {
853 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
854 }
855
856 /* Disable the Main Output */
857 __HAL_TIM_MOE_DISABLE(htim);
858
859 /* Disable the Peripheral */
860 __HAL_TIM_DISABLE(htim);
861
862 /* Set the TIM complementary channel state */
863 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
864 }
865
866 /* Return function status */
867 return status;
868 }
869
870 /**
871 * @brief Starts the TIM Output Compare signal generation in DMA mode
872 * on the complementary output.
873 * @param htim TIM Output Compare handle
874 * @param Channel TIM Channel to be enabled
875 * This parameter can be one of the following values:
876 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
877 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
878 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
879 * @param pData The source Buffer address.
880 * @param Length The length of data to be transferred from memory to TIM peripheral
881 * @retval HAL status
882 */
HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)883 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
884 uint16_t Length)
885 {
886 HAL_StatusTypeDef status = HAL_OK;
887 uint32_t tmpsmcr;
888
889 /* Check the parameters */
890 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
891
892 /* Set the TIM complementary channel state */
893 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
894 {
895 return HAL_BUSY;
896 }
897 else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
898 {
899 if ((pData == NULL) || (Length == 0U))
900 {
901 return HAL_ERROR;
902 }
903 else
904 {
905 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
906 }
907 }
908 else
909 {
910 return HAL_ERROR;
911 }
912
913 switch (Channel)
914 {
915 case TIM_CHANNEL_1:
916 {
917 /* Set the DMA compare callbacks */
918 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
919 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
920
921 /* Set the DMA error callback */
922 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
923
924 /* Enable the DMA channel */
925 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
926 Length) != HAL_OK)
927 {
928 /* Return error status */
929 return HAL_ERROR;
930 }
931 /* Enable the TIM Output Compare DMA request */
932 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
933 break;
934 }
935
936 case TIM_CHANNEL_2:
937 {
938 /* Set the DMA compare callbacks */
939 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
940 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
941
942 /* Set the DMA error callback */
943 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
944
945 /* Enable the DMA channel */
946 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
947 Length) != HAL_OK)
948 {
949 /* Return error status */
950 return HAL_ERROR;
951 }
952 /* Enable the TIM Output Compare DMA request */
953 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
954 break;
955 }
956
957 case TIM_CHANNEL_3:
958 {
959 /* Set the DMA compare callbacks */
960 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
961 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
962
963 /* Set the DMA error callback */
964 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
965
966 /* Enable the DMA channel */
967 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
968 Length) != HAL_OK)
969 {
970 /* Return error status */
971 return HAL_ERROR;
972 }
973 /* Enable the TIM Output Compare DMA request */
974 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
975 break;
976 }
977
978 default:
979 status = HAL_ERROR;
980 break;
981 }
982
983 if (status == HAL_OK)
984 {
985 /* Enable the Capture compare channel N */
986 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
987
988 /* Enable the Main Output */
989 __HAL_TIM_MOE_ENABLE(htim);
990
991 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
992 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
993 {
994 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
995 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
996 {
997 __HAL_TIM_ENABLE(htim);
998 }
999 }
1000 else
1001 {
1002 __HAL_TIM_ENABLE(htim);
1003 }
1004 }
1005
1006 /* Return function status */
1007 return status;
1008 }
1009
1010 /**
1011 * @brief Stops the TIM Output Compare signal generation in DMA mode
1012 * on the complementary output.
1013 * @param htim TIM Output Compare handle
1014 * @param Channel TIM Channel to be disabled
1015 * This parameter can be one of the following values:
1016 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1017 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1018 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1019 * @retval HAL status
1020 */
HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1021 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1022 {
1023 HAL_StatusTypeDef status = HAL_OK;
1024
1025 /* Check the parameters */
1026 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1027
1028 switch (Channel)
1029 {
1030 case TIM_CHANNEL_1:
1031 {
1032 /* Disable the TIM Output Compare DMA request */
1033 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1034 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1035 break;
1036 }
1037
1038 case TIM_CHANNEL_2:
1039 {
1040 /* Disable the TIM Output Compare DMA request */
1041 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1042 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1043 break;
1044 }
1045
1046 case TIM_CHANNEL_3:
1047 {
1048 /* Disable the TIM Output Compare DMA request */
1049 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1050 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1051 break;
1052 }
1053
1054 default:
1055 status = HAL_ERROR;
1056 break;
1057 }
1058
1059 if (status == HAL_OK)
1060 {
1061 /* Disable the Capture compare channel N */
1062 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1063
1064 /* Disable the Main Output */
1065 __HAL_TIM_MOE_DISABLE(htim);
1066
1067 /* Disable the Peripheral */
1068 __HAL_TIM_DISABLE(htim);
1069
1070 /* Set the TIM complementary channel state */
1071 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1072 }
1073
1074 /* Return function status */
1075 return status;
1076 }
1077
1078 /**
1079 * @}
1080 */
1081
1082 /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
1083 * @brief Timer Complementary PWM functions
1084 *
1085 @verbatim
1086 ==============================================================================
1087 ##### Timer Complementary PWM functions #####
1088 ==============================================================================
1089 [..]
1090 This section provides functions allowing to:
1091 (+) Start the Complementary PWM.
1092 (+) Stop the Complementary PWM.
1093 (+) Start the Complementary PWM and enable interrupts.
1094 (+) Stop the Complementary PWM and disable interrupts.
1095 (+) Start the Complementary PWM and enable DMA transfers.
1096 (+) Stop the Complementary PWM and disable DMA transfers.
1097 @endverbatim
1098 * @{
1099 */
1100
1101 /**
1102 * @brief Starts the PWM signal generation on the complementary output.
1103 * @param htim TIM handle
1104 * @param Channel TIM Channel to be enabled
1105 * This parameter can be one of the following values:
1106 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1107 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1108 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1109 * @retval HAL status
1110 */
HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1111 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1112 {
1113 uint32_t tmpsmcr;
1114
1115 /* Check the parameters */
1116 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1117
1118 /* Check the TIM complementary channel state */
1119 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1120 {
1121 return HAL_ERROR;
1122 }
1123
1124 /* Set the TIM complementary channel state */
1125 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1126
1127 /* Enable the complementary PWM output */
1128 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1129
1130 /* Enable the Main Output */
1131 __HAL_TIM_MOE_ENABLE(htim);
1132
1133 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1134 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1135 {
1136 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1137 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1138 {
1139 __HAL_TIM_ENABLE(htim);
1140 }
1141 }
1142 else
1143 {
1144 __HAL_TIM_ENABLE(htim);
1145 }
1146
1147 /* Return function status */
1148 return HAL_OK;
1149 }
1150
1151 /**
1152 * @brief Stops the PWM signal generation on the complementary output.
1153 * @param htim TIM handle
1154 * @param Channel TIM Channel to be disabled
1155 * This parameter can be one of the following values:
1156 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1157 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1158 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1159 * @retval HAL status
1160 */
HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1161 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1162 {
1163 /* Check the parameters */
1164 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1165
1166 /* Disable the complementary PWM output */
1167 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1168
1169 /* Disable the Main Output */
1170 __HAL_TIM_MOE_DISABLE(htim);
1171
1172 /* Disable the Peripheral */
1173 __HAL_TIM_DISABLE(htim);
1174
1175 /* Set the TIM complementary channel state */
1176 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1177
1178 /* Return function status */
1179 return HAL_OK;
1180 }
1181
1182 /**
1183 * @brief Starts the PWM signal generation in interrupt mode on the
1184 * complementary output.
1185 * @param htim TIM handle
1186 * @param Channel TIM Channel to be disabled
1187 * This parameter can be one of the following values:
1188 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1189 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1190 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1191 * @retval HAL status
1192 */
HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1193 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1194 {
1195 HAL_StatusTypeDef status = HAL_OK;
1196 uint32_t tmpsmcr;
1197
1198 /* Check the parameters */
1199 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1200
1201 /* Check the TIM complementary channel state */
1202 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1203 {
1204 return HAL_ERROR;
1205 }
1206
1207 /* Set the TIM complementary channel state */
1208 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1209
1210 switch (Channel)
1211 {
1212 case TIM_CHANNEL_1:
1213 {
1214 /* Enable the TIM Capture/Compare 1 interrupt */
1215 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1216 break;
1217 }
1218
1219 case TIM_CHANNEL_2:
1220 {
1221 /* Enable the TIM Capture/Compare 2 interrupt */
1222 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1223 break;
1224 }
1225
1226 case TIM_CHANNEL_3:
1227 {
1228 /* Enable the TIM Capture/Compare 3 interrupt */
1229 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1230 break;
1231 }
1232
1233 default:
1234 status = HAL_ERROR;
1235 break;
1236 }
1237
1238 if (status == HAL_OK)
1239 {
1240 /* Enable the TIM Break interrupt */
1241 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
1242
1243 /* Enable the complementary PWM output */
1244 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1245
1246 /* Enable the Main Output */
1247 __HAL_TIM_MOE_ENABLE(htim);
1248
1249 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1250 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1251 {
1252 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1253 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1254 {
1255 __HAL_TIM_ENABLE(htim);
1256 }
1257 }
1258 else
1259 {
1260 __HAL_TIM_ENABLE(htim);
1261 }
1262 }
1263
1264 /* Return function status */
1265 return status;
1266 }
1267
1268 /**
1269 * @brief Stops the PWM signal generation in interrupt mode on the
1270 * complementary output.
1271 * @param htim TIM handle
1272 * @param Channel TIM Channel to be disabled
1273 * This parameter can be one of the following values:
1274 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1275 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1276 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1277 * @retval HAL status
1278 */
HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1279 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1280 {
1281 HAL_StatusTypeDef status = HAL_OK;
1282 uint32_t tmpccer;
1283
1284 /* Check the parameters */
1285 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1286
1287 switch (Channel)
1288 {
1289 case TIM_CHANNEL_1:
1290 {
1291 /* Disable the TIM Capture/Compare 1 interrupt */
1292 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1293 break;
1294 }
1295
1296 case TIM_CHANNEL_2:
1297 {
1298 /* Disable the TIM Capture/Compare 2 interrupt */
1299 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1300 break;
1301 }
1302
1303 case TIM_CHANNEL_3:
1304 {
1305 /* Disable the TIM Capture/Compare 3 interrupt */
1306 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1307 break;
1308 }
1309
1310 default:
1311 status = HAL_ERROR;
1312 break;
1313 }
1314
1315 if (status == HAL_OK)
1316 {
1317 /* Disable the complementary PWM output */
1318 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1319
1320 /* Disable the TIM Break interrupt (only if no more channel is active) */
1321 tmpccer = htim->Instance->CCER;
1322 if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
1323 {
1324 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
1325 }
1326
1327 /* Disable the Main Output */
1328 __HAL_TIM_MOE_DISABLE(htim);
1329
1330 /* Disable the Peripheral */
1331 __HAL_TIM_DISABLE(htim);
1332
1333 /* Set the TIM complementary channel state */
1334 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1335 }
1336
1337 /* Return function status */
1338 return status;
1339 }
1340
1341 /**
1342 * @brief Starts the TIM PWM signal generation in DMA mode on the
1343 * complementary output
1344 * @param htim TIM handle
1345 * @param Channel TIM Channel to be enabled
1346 * This parameter can be one of the following values:
1347 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1348 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1349 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1350 * @param pData The source Buffer address.
1351 * @param Length The length of data to be transferred from memory to TIM peripheral
1352 * @retval HAL status
1353 */
HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1354 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1355 uint16_t Length)
1356 {
1357 HAL_StatusTypeDef status = HAL_OK;
1358 uint32_t tmpsmcr;
1359
1360 /* Check the parameters */
1361 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1362
1363 /* Set the TIM complementary channel state */
1364 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1365 {
1366 return HAL_BUSY;
1367 }
1368 else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1369 {
1370 if ((pData == NULL) || (Length == 0U))
1371 {
1372 return HAL_ERROR;
1373 }
1374 else
1375 {
1376 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1377 }
1378 }
1379 else
1380 {
1381 return HAL_ERROR;
1382 }
1383
1384 switch (Channel)
1385 {
1386 case TIM_CHANNEL_1:
1387 {
1388 /* Set the DMA compare callbacks */
1389 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1390 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1391
1392 /* Set the DMA error callback */
1393 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
1394
1395 /* Enable the DMA channel */
1396 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1397 Length) != HAL_OK)
1398 {
1399 /* Return error status */
1400 return HAL_ERROR;
1401 }
1402 /* Enable the TIM Capture/Compare 1 DMA request */
1403 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1404 break;
1405 }
1406
1407 case TIM_CHANNEL_2:
1408 {
1409 /* Set the DMA compare callbacks */
1410 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1411 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1412
1413 /* Set the DMA error callback */
1414 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
1415
1416 /* Enable the DMA channel */
1417 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1418 Length) != HAL_OK)
1419 {
1420 /* Return error status */
1421 return HAL_ERROR;
1422 }
1423 /* Enable the TIM Capture/Compare 2 DMA request */
1424 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1425 break;
1426 }
1427
1428 case TIM_CHANNEL_3:
1429 {
1430 /* Set the DMA compare callbacks */
1431 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1432 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1433
1434 /* Set the DMA error callback */
1435 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
1436
1437 /* Enable the DMA channel */
1438 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1439 Length) != HAL_OK)
1440 {
1441 /* Return error status */
1442 return HAL_ERROR;
1443 }
1444 /* Enable the TIM Capture/Compare 3 DMA request */
1445 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1446 break;
1447 }
1448
1449 default:
1450 status = HAL_ERROR;
1451 break;
1452 }
1453
1454 if (status == HAL_OK)
1455 {
1456 /* Enable the complementary PWM output */
1457 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1458
1459 /* Enable the Main Output */
1460 __HAL_TIM_MOE_ENABLE(htim);
1461
1462 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1463 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1464 {
1465 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1466 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1467 {
1468 __HAL_TIM_ENABLE(htim);
1469 }
1470 }
1471 else
1472 {
1473 __HAL_TIM_ENABLE(htim);
1474 }
1475 }
1476
1477 /* Return function status */
1478 return status;
1479 }
1480
1481 /**
1482 * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
1483 * output
1484 * @param htim TIM handle
1485 * @param Channel TIM Channel to be disabled
1486 * This parameter can be one of the following values:
1487 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1488 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1489 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1490 * @retval HAL status
1491 */
HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1492 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1493 {
1494 HAL_StatusTypeDef status = HAL_OK;
1495
1496 /* Check the parameters */
1497 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1498
1499 switch (Channel)
1500 {
1501 case TIM_CHANNEL_1:
1502 {
1503 /* Disable the TIM Capture/Compare 1 DMA request */
1504 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1505 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1506 break;
1507 }
1508
1509 case TIM_CHANNEL_2:
1510 {
1511 /* Disable the TIM Capture/Compare 2 DMA request */
1512 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1513 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1514 break;
1515 }
1516
1517 case TIM_CHANNEL_3:
1518 {
1519 /* Disable the TIM Capture/Compare 3 DMA request */
1520 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1521 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1522 break;
1523 }
1524
1525 default:
1526 status = HAL_ERROR;
1527 break;
1528 }
1529
1530 if (status == HAL_OK)
1531 {
1532 /* Disable the complementary PWM output */
1533 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1534
1535 /* Disable the Main Output */
1536 __HAL_TIM_MOE_DISABLE(htim);
1537
1538 /* Disable the Peripheral */
1539 __HAL_TIM_DISABLE(htim);
1540
1541 /* Set the TIM complementary channel state */
1542 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1543 }
1544
1545 /* Return function status */
1546 return status;
1547 }
1548
1549 /**
1550 * @}
1551 */
1552
1553 /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
1554 * @brief Timer Complementary One Pulse functions
1555 *
1556 @verbatim
1557 ==============================================================================
1558 ##### Timer Complementary One Pulse functions #####
1559 ==============================================================================
1560 [..]
1561 This section provides functions allowing to:
1562 (+) Start the Complementary One Pulse generation.
1563 (+) Stop the Complementary One Pulse.
1564 (+) Start the Complementary One Pulse and enable interrupts.
1565 (+) Stop the Complementary One Pulse and disable interrupts.
1566
1567 @endverbatim
1568 * @{
1569 */
1570
1571 /**
1572 * @brief Starts the TIM One Pulse signal generation on the complementary
1573 * output.
1574 * @note OutputChannel must match the pulse output channel chosen when calling
1575 * @ref HAL_TIM_OnePulse_ConfigChannel().
1576 * @param htim TIM One Pulse handle
1577 * @param OutputChannel pulse output channel to enable
1578 * This parameter can be one of the following values:
1579 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1580 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1581 * @retval HAL status
1582 */
HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1583 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1584 {
1585 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1586 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
1587 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
1588 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
1589 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
1590
1591 /* Check the parameters */
1592 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1593
1594 /* Check the TIM channels state */
1595 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1596 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
1597 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1598 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
1599 {
1600 return HAL_ERROR;
1601 }
1602
1603 /* Set the TIM channels state */
1604 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1605 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1606 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1607 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1608
1609 /* Enable the complementary One Pulse output channel and the Input Capture channel */
1610 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
1611 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
1612
1613 /* Enable the Main Output */
1614 __HAL_TIM_MOE_ENABLE(htim);
1615
1616 /* Return function status */
1617 return HAL_OK;
1618 }
1619
1620 /**
1621 * @brief Stops the TIM One Pulse signal generation on the complementary
1622 * output.
1623 * @note OutputChannel must match the pulse output channel chosen when calling
1624 * @ref HAL_TIM_OnePulse_ConfigChannel().
1625 * @param htim TIM One Pulse handle
1626 * @param OutputChannel pulse output channel to disable
1627 * This parameter can be one of the following values:
1628 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1629 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1630 * @retval HAL status
1631 */
HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1632 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1633 {
1634 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1635
1636 /* Check the parameters */
1637 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1638
1639 /* Disable the complementary One Pulse output channel and the Input Capture channel */
1640 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
1641 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
1642
1643 /* Disable the Main Output */
1644 __HAL_TIM_MOE_DISABLE(htim);
1645
1646 /* Disable the Peripheral */
1647 __HAL_TIM_DISABLE(htim);
1648
1649 /* Set the TIM channels state */
1650 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1651 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1652 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1653 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1654
1655 /* Return function status */
1656 return HAL_OK;
1657 }
1658
1659 /**
1660 * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
1661 * complementary channel.
1662 * @note OutputChannel must match the pulse output channel chosen when calling
1663 * @ref HAL_TIM_OnePulse_ConfigChannel().
1664 * @param htim TIM One Pulse handle
1665 * @param OutputChannel pulse output channel to enable
1666 * This parameter can be one of the following values:
1667 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1668 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1669 * @retval HAL status
1670 */
HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1671 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1672 {
1673 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1674 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
1675 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
1676 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
1677 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
1678
1679 /* Check the parameters */
1680 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1681
1682 /* Check the TIM channels state */
1683 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1684 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
1685 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1686 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
1687 {
1688 return HAL_ERROR;
1689 }
1690
1691 /* Set the TIM channels state */
1692 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1693 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1694 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1695 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1696
1697 /* Enable the TIM Capture/Compare 1 interrupt */
1698 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1699
1700 /* Enable the TIM Capture/Compare 2 interrupt */
1701 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1702
1703 /* Enable the complementary One Pulse output channel and the Input Capture channel */
1704 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
1705 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
1706
1707 /* Enable the Main Output */
1708 __HAL_TIM_MOE_ENABLE(htim);
1709
1710 /* Return function status */
1711 return HAL_OK;
1712 }
1713
1714 /**
1715 * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
1716 * complementary channel.
1717 * @note OutputChannel must match the pulse output channel chosen when calling
1718 * @ref HAL_TIM_OnePulse_ConfigChannel().
1719 * @param htim TIM One Pulse handle
1720 * @param OutputChannel pulse output channel to disable
1721 * This parameter can be one of the following values:
1722 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1723 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1724 * @retval HAL status
1725 */
HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1726 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1727 {
1728 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1729
1730 /* Check the parameters */
1731 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1732
1733 /* Disable the TIM Capture/Compare 1 interrupt */
1734 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1735
1736 /* Disable the TIM Capture/Compare 2 interrupt */
1737 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1738
1739 /* Disable the complementary One Pulse output channel and the Input Capture channel */
1740 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
1741 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
1742
1743 /* Disable the Main Output */
1744 __HAL_TIM_MOE_DISABLE(htim);
1745
1746 /* Disable the Peripheral */
1747 __HAL_TIM_DISABLE(htim);
1748
1749 /* Set the TIM channels state */
1750 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1751 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1752 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1753 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1754
1755 /* Return function status */
1756 return HAL_OK;
1757 }
1758
1759 /**
1760 * @}
1761 */
1762
1763 /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
1764 * @brief Peripheral Control functions
1765 *
1766 @verbatim
1767 ==============================================================================
1768 ##### Peripheral Control functions #####
1769 ==============================================================================
1770 [..]
1771 This section provides functions allowing to:
1772 (+) Configure the commutation event in case of use of the Hall sensor interface.
1773 (+) Configure Output channels for OC and PWM mode.
1774
1775 (+) Configure Complementary channels, break features and dead time.
1776 (+) Configure Master synchronization.
1777 (+) Configure timer remapping capabilities.
1778 (+) Select timer input source.
1779 (+) Enable or disable channel grouping.
1780
1781 @endverbatim
1782 * @{
1783 */
1784
1785 /**
1786 * @brief Configure the TIM commutation event sequence.
1787 * @note This function is mandatory to use the commutation event in order to
1788 * update the configuration at each commutation detection on the TRGI input of the Timer,
1789 * the typical use of this feature is with the use of another Timer(interface Timer)
1790 * configured in Hall sensor interface, this interface Timer will generate the
1791 * commutation at its TRGO output (connected to Timer used in this function) each time
1792 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1793 * @param htim TIM handle
1794 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
1795 * This parameter can be one of the following values:
1796 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1797 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1798 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1799 * @arg TIM_TS_ITR3: Internal trigger 3 selected
1800 * @arg TIM_TS_ITR7: Internal trigger 7 selected (*)
1801 * @arg TIM_TS_NONE: No trigger is needed
1802 *
1803 * (*) Value not defined in all devices.
1804 *
1805 * @param CommutationSource the Commutation Event source
1806 * This parameter can be one of the following values:
1807 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1808 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1809 * @retval HAL status
1810 */
HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)1811 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
1812 uint32_t CommutationSource)
1813 {
1814 /* Check the parameters */
1815 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
1816 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
1817
1818 __HAL_LOCK(htim);
1819
1820 #if defined(USB_BASE)
1821 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1822 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
1823 (InputTrigger == TIM_TS_ITR7))
1824 #else
1825 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1826 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
1827 #endif /* USB_BASE */
1828 {
1829 /* Select the Input trigger */
1830 htim->Instance->SMCR &= ~TIM_SMCR_TS;
1831 htim->Instance->SMCR |= InputTrigger;
1832 }
1833
1834 /* Select the Capture Compare preload feature */
1835 htim->Instance->CR2 |= TIM_CR2_CCPC;
1836 /* Select the Commutation event source */
1837 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
1838 htim->Instance->CR2 |= CommutationSource;
1839
1840 /* Disable Commutation Interrupt */
1841 __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
1842
1843 /* Disable Commutation DMA request */
1844 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
1845
1846 __HAL_UNLOCK(htim);
1847
1848 return HAL_OK;
1849 }
1850
1851 /**
1852 * @brief Configure the TIM commutation event sequence with interrupt.
1853 * @note This function is mandatory to use the commutation event in order to
1854 * update the configuration at each commutation detection on the TRGI input of the Timer,
1855 * the typical use of this feature is with the use of another Timer(interface Timer)
1856 * configured in Hall sensor interface, this interface Timer will generate the
1857 * commutation at its TRGO output (connected to Timer used in this function) each time
1858 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1859 * @param htim TIM handle
1860 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
1861 * This parameter can be one of the following values:
1862 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1863 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1864 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1865 * @arg TIM_TS_ITR3: Internal trigger 3 selected
1866 * @arg TIM_TS_ITR7: Internal trigger 7 selected (*)
1867 * @arg TIM_TS_NONE: No trigger is needed
1868 *
1869 * (*) Value not defined in all devices.
1870 *
1871 * @param CommutationSource the Commutation Event source
1872 * This parameter can be one of the following values:
1873 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1874 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1875 * @retval HAL status
1876 */
HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)1877 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
1878 uint32_t CommutationSource)
1879 {
1880 /* Check the parameters */
1881 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
1882 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
1883
1884 __HAL_LOCK(htim);
1885
1886 #if defined(USB_BASE)
1887 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1888 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
1889 (InputTrigger == TIM_TS_ITR7))
1890 #else
1891 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1892 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
1893 #endif /* USB_BASE */
1894 {
1895 /* Select the Input trigger */
1896 htim->Instance->SMCR &= ~TIM_SMCR_TS;
1897 htim->Instance->SMCR |= InputTrigger;
1898 }
1899
1900 /* Select the Capture Compare preload feature */
1901 htim->Instance->CR2 |= TIM_CR2_CCPC;
1902 /* Select the Commutation event source */
1903 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
1904 htim->Instance->CR2 |= CommutationSource;
1905
1906 /* Disable Commutation DMA request */
1907 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
1908
1909 /* Enable the Commutation Interrupt */
1910 __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
1911
1912 __HAL_UNLOCK(htim);
1913
1914 return HAL_OK;
1915 }
1916
1917 /**
1918 * @brief Configure the TIM commutation event sequence with DMA.
1919 * @note This function is mandatory to use the commutation event in order to
1920 * update the configuration at each commutation detection on the TRGI input of the Timer,
1921 * the typical use of this feature is with the use of another Timer(interface Timer)
1922 * configured in Hall sensor interface, this interface Timer will generate the
1923 * commutation at its TRGO output (connected to Timer used in this function) each time
1924 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1925 * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set
1926 * @param htim TIM handle
1927 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
1928 * This parameter can be one of the following values:
1929 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1930 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1931 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1932 * @arg TIM_TS_ITR3: Internal trigger 3 selected
1933 * @arg TIM_TS_ITR7: Internal trigger 7 selected (*)
1934 * @arg TIM_TS_NONE: No trigger is needed
1935 *
1936 * (*) Value not defined in all devices.
1937 *
1938 * @param CommutationSource the Commutation Event source
1939 * This parameter can be one of the following values:
1940 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1941 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1942 * @retval HAL status
1943 */
HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)1944 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
1945 uint32_t CommutationSource)
1946 {
1947 /* Check the parameters */
1948 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
1949 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
1950
1951 __HAL_LOCK(htim);
1952
1953 #if defined(USB_BASE)
1954 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1955 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) ||
1956 (InputTrigger == TIM_TS_ITR7))
1957 #else
1958 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1959 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
1960 #endif /* USB_BASE */
1961 {
1962 /* Select the Input trigger */
1963 htim->Instance->SMCR &= ~TIM_SMCR_TS;
1964 htim->Instance->SMCR |= InputTrigger;
1965 }
1966
1967 /* Select the Capture Compare preload feature */
1968 htim->Instance->CR2 |= TIM_CR2_CCPC;
1969 /* Select the Commutation event source */
1970 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
1971 htim->Instance->CR2 |= CommutationSource;
1972
1973 /* Enable the Commutation DMA Request */
1974 /* Set the DMA Commutation Callback */
1975 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
1976 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
1977 /* Set the DMA error callback */
1978 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
1979
1980 /* Disable Commutation Interrupt */
1981 __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
1982
1983 /* Enable the Commutation DMA Request */
1984 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
1985
1986 __HAL_UNLOCK(htim);
1987
1988 return HAL_OK;
1989 }
1990
1991 /**
1992 * @brief Configures the TIM in master mode.
1993 * @param htim TIM handle.
1994 * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
1995 * contains the selected trigger output (TRGO) and the Master/Slave
1996 * mode.
1997 * @retval HAL status
1998 */
HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef * htim,const TIM_MasterConfigTypeDef * sMasterConfig)1999 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
2000 const TIM_MasterConfigTypeDef *sMasterConfig)
2001 {
2002 uint32_t tmpcr2;
2003 uint32_t tmpsmcr;
2004
2005 /* Check the parameters */
2006 assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
2007 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
2008 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
2009
2010 /* Check input state */
2011 __HAL_LOCK(htim);
2012
2013 /* Change the handler state */
2014 htim->State = HAL_TIM_STATE_BUSY;
2015
2016 /* Get the TIMx CR2 register value */
2017 tmpcr2 = htim->Instance->CR2;
2018
2019 /* Get the TIMx SMCR register value */
2020 tmpsmcr = htim->Instance->SMCR;
2021
2022 /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
2023 if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
2024 {
2025 /* Check the parameters */
2026 assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
2027
2028 /* Clear the MMS2 bits */
2029 tmpcr2 &= ~TIM_CR2_MMS2;
2030 /* Select the TRGO2 source*/
2031 tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
2032 }
2033
2034 /* Reset the MMS Bits */
2035 tmpcr2 &= ~TIM_CR2_MMS;
2036 /* Select the TRGO source */
2037 tmpcr2 |= sMasterConfig->MasterOutputTrigger;
2038
2039 /* Update TIMx CR2 */
2040 htim->Instance->CR2 = tmpcr2;
2041
2042 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2043 {
2044 /* Reset the MSM Bit */
2045 tmpsmcr &= ~TIM_SMCR_MSM;
2046 /* Set master mode */
2047 tmpsmcr |= sMasterConfig->MasterSlaveMode;
2048
2049 /* Update TIMx SMCR */
2050 htim->Instance->SMCR = tmpsmcr;
2051 }
2052
2053 /* Change the htim state */
2054 htim->State = HAL_TIM_STATE_READY;
2055
2056 __HAL_UNLOCK(htim);
2057
2058 return HAL_OK;
2059 }
2060
2061 /**
2062 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
2063 * and the AOE(automatic output enable).
2064 * @param htim TIM handle
2065 * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
2066 * contains the BDTR Register configuration information for the TIM peripheral.
2067 * @note Interrupts can be generated when an active level is detected on the
2068 * break input, the break 2 input or the system break input. Break
2069 * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
2070 * @retval HAL status
2071 */
HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef * htim,const TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)2072 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
2073 const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
2074 {
2075 /* Keep this variable initialized to 0 as it is used to configure BDTR register */
2076 uint32_t tmpbdtr = 0U;
2077
2078 /* Check the parameters */
2079 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2080 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
2081 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
2082 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
2083 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
2084 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
2085 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
2086 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
2087 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
2088 assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
2089
2090 /* Check input state */
2091 __HAL_LOCK(htim);
2092
2093 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
2094 the OSSI State, the dead time value and the Automatic Output Enable Bit */
2095
2096 /* Set the BDTR bits */
2097 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
2098 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
2099 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
2100 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
2101 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
2102 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
2103 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
2104 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
2105 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
2106
2107 if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
2108 {
2109 /* Check the parameters */
2110 assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
2111 assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
2112 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
2113 assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
2114
2115 /* Set the BREAK2 input related BDTR bits */
2116 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
2117 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
2118 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
2119 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
2120 }
2121
2122 /* Set TIMx_BDTR */
2123 htim->Instance->BDTR = tmpbdtr;
2124
2125 __HAL_UNLOCK(htim);
2126
2127 return HAL_OK;
2128 }
2129
2130 /**
2131 * @brief Configures the break input source.
2132 * @param htim TIM handle.
2133 * @param BreakInput Break input to configure
2134 * This parameter can be one of the following values:
2135 * @arg TIM_BREAKINPUT_BRK: Timer break input
2136 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
2137 * @param sBreakInputConfig Break input source configuration
2138 * @retval HAL status
2139 */
HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef * htim,uint32_t BreakInput,const TIMEx_BreakInputConfigTypeDef * sBreakInputConfig)2140 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
2141 uint32_t BreakInput,
2142 const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
2143 {
2144 HAL_StatusTypeDef status = HAL_OK;
2145 uint32_t tmporx;
2146 uint32_t bkin_enable_mask;
2147 uint32_t bkin_polarity_mask;
2148 uint32_t bkin_enable_bitpos;
2149 uint32_t bkin_polarity_bitpos;
2150
2151 /* Check the parameters */
2152 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2153 assert_param(IS_TIM_BREAKINPUT(BreakInput));
2154 assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
2155 assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
2156 assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
2157
2158 /* Check input state */
2159 __HAL_LOCK(htim);
2160
2161 switch (sBreakInputConfig->Source)
2162 {
2163 case TIM_BREAKINPUTSOURCE_BKIN:
2164 {
2165 bkin_enable_mask = TIM_AF1_BKINE;
2166 bkin_enable_bitpos = TIM_AF1_BKINE_Pos;
2167 bkin_polarity_mask = TIM_AF1_BKINP;
2168 bkin_polarity_bitpos = TIM_AF1_BKINP_Pos;
2169 break;
2170 }
2171
2172 default:
2173 {
2174 bkin_enable_mask = 0U;
2175 bkin_polarity_mask = 0U;
2176 bkin_enable_bitpos = 0U;
2177 bkin_polarity_bitpos = 0U;
2178 break;
2179 }
2180 }
2181
2182 switch (BreakInput)
2183 {
2184 case TIM_BREAKINPUT_BRK:
2185 {
2186 /* Get the TIMx_AF1 register value */
2187 tmporx = htim->Instance->AF1;
2188
2189 /* Enable the break input */
2190 tmporx &= ~bkin_enable_mask;
2191 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
2192
2193 /* Set the break input polarity */
2194 tmporx &= ~bkin_polarity_mask;
2195 tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
2196
2197 /* Set TIMx_AF1 */
2198 htim->Instance->AF1 = tmporx;
2199 break;
2200 }
2201 case TIM_BREAKINPUT_BRK2:
2202 {
2203 /* Get the TIMx_AF2 register value */
2204 tmporx = htim->Instance->AF2;
2205
2206 /* Enable the break input */
2207 tmporx &= ~bkin_enable_mask;
2208 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
2209
2210 /* Set the break input polarity */
2211 tmporx &= ~bkin_polarity_mask;
2212 tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
2213
2214 /* Set TIMx_AF2 */
2215 htim->Instance->AF2 = tmporx;
2216 break;
2217 }
2218 default:
2219 status = HAL_ERROR;
2220 break;
2221 }
2222
2223 __HAL_UNLOCK(htim);
2224
2225 return status;
2226 }
2227
2228 /**
2229 * @brief Configures the TIMx Remapping input capabilities.
2230 * @param htim TIM handle.
2231 * @param Remap specifies the TIM remapping source.
2232 * For TIM1, the parameter can take one of the following values:
2233 * @arg TIM_TIM1_ETR_GPIO: TIM1 ETR is is connected to GPIO
2234 * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1 ETR is connected to ADC1 AWD1
2235 * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1 ETR is connected to ADC1 AWD2
2236 * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1 ETR is connected to ADC1 AWD3
2237 *
2238 * For TIM2, the parameter can take one of the following values: (*)
2239 * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO
2240 * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE
2241 * @arg TIM_TIM2_ETR_MCO: TIM2_ETR is connected to MCO
2242 * @arg TIM_TIM2_ETR_MCO2: TIM2_ETR is connected to MCO2
2243 *
2244 * For TIM3, the parameter can take one of the following values:
2245 * @arg TIM_TIM3_ETR_GPIO TIM3_ETR is connected to GPIO
2246 *
2247 * (*) Timer instance not available on all devices \n
2248 *
2249 * @retval HAL status
2250 */
HAL_TIMEx_RemapConfig(TIM_HandleTypeDef * htim,uint32_t Remap)2251 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
2252 {
2253 /* Check parameters */
2254 assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
2255 assert_param(IS_TIM_REMAP(Remap));
2256
2257 __HAL_LOCK(htim);
2258
2259 MODIFY_REG(htim->Instance->AF1, TIM_AF1_ETRSEL_Msk, Remap);
2260
2261 __HAL_UNLOCK(htim);
2262
2263 return HAL_OK;
2264 }
2265
2266 /**
2267 * @brief Select the timer input source
2268 * @param htim TIM handle.
2269 * @param Channel specifies the TIM Channel
2270 * This parameter can be one of the following values:
2271 * @arg TIM_CHANNEL_1: TI1 input channel
2272 * @arg TIM_CHANNEL_2: TI2 input channel
2273 * @param TISelection specifies the timer input source
2274 *
2275 * For TIM14, the parameter is one of the following values:
2276 * @arg TIM_TIM14_TI1_GPIO: TIM14 TI1 is connected to GPIO
2277 * @arg TIM_TIM14_TI1_RTC: TIM14 TI1 is connected to RTC clock
2278 * @arg TIM_TIM14_TI1_HSE_32: TIM14 TI1 is connected to HSE div 32
2279 * @arg TIM_TIM14_TI1_MCO: TIM14 TI1 is connected to MCO
2280 * @arg TIM_TIM14_TI1_MCO2: TIM14 TI1 is connected to MCO2
2281 *
2282 * For TIM16, the parameter can have the following values:
2283 * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
2284 * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI
2285 * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE
2286 * @arg TIM_TIM16_TI1_MCO2: TIM16 TI1 is connected to MCO2
2287 *
2288 * For TIM17, the parameter can have the following values:
2289 * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO
2290 * @arg TIM_TIM17_TI1_HSE_32: TIM17 TI1 is connected to HSE div 32
2291 * @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO
2292 * @arg TIM_TIM17_TI1_MCO2: TIM17 TI1 is connected to MCO2
2293 * @retval HAL status
2294 */
HAL_TIMEx_TISelection(TIM_HandleTypeDef * htim,uint32_t TISelection,uint32_t Channel)2295 HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
2296 {
2297 HAL_StatusTypeDef status = HAL_OK;
2298
2299 /* Check parameters */
2300 assert_param(IS_TIM_TISEL_INSTANCE(htim->Instance));
2301 assert_param(IS_TIM_TISEL(TISelection));
2302
2303 __HAL_LOCK(htim);
2304
2305 switch (Channel)
2306 {
2307 case TIM_CHANNEL_1:
2308 MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection);
2309 break;
2310 case TIM_CHANNEL_2:
2311 MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection);
2312 break;
2313 case TIM_CHANNEL_3:
2314 MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI3SEL, TISelection);
2315 break;
2316 default:
2317 status = HAL_ERROR;
2318 break;
2319 }
2320
2321 __HAL_UNLOCK(htim);
2322
2323 return status;
2324 }
2325
2326 /**
2327 * @brief Group channel 5 and channel 1, 2 or 3
2328 * @param htim TIM handle.
2329 * @param Channels specifies the reference signal(s) the OC5REF is combined with.
2330 * This parameter can be any combination of the following values:
2331 * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
2332 * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
2333 * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
2334 * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
2335 * @retval HAL status
2336 */
HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef * htim,uint32_t Channels)2337 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
2338 {
2339 /* Check parameters */
2340 assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
2341 assert_param(IS_TIM_GROUPCH5(Channels));
2342
2343 /* Process Locked */
2344 __HAL_LOCK(htim);
2345
2346 htim->State = HAL_TIM_STATE_BUSY;
2347
2348 /* Clear GC5Cx bit fields */
2349 htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
2350
2351 /* Set GC5Cx bit fields */
2352 htim->Instance->CCR5 |= Channels;
2353
2354 /* Change the htim state */
2355 htim->State = HAL_TIM_STATE_READY;
2356
2357 __HAL_UNLOCK(htim);
2358
2359 return HAL_OK;
2360 }
2361
2362 /**
2363 * @brief Disarm the designated break input (when it operates in bidirectional mode).
2364 * @param htim TIM handle.
2365 * @param BreakInput Break input to disarm
2366 * This parameter can be one of the following values:
2367 * @arg TIM_BREAKINPUT_BRK: Timer break input
2368 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
2369 * @note The break input can be disarmed only when it is configured in
2370 * bidirectional mode and when when MOE is reset.
2371 * @note Purpose is to be able to have the input voltage back to high-state,
2372 * whatever the time constant on the output .
2373 * @retval HAL status
2374 */
HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef * htim,uint32_t BreakInput)2375 HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput)
2376 {
2377 HAL_StatusTypeDef status = HAL_OK;
2378 uint32_t tmpbdtr;
2379
2380 /* Check the parameters */
2381 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2382 assert_param(IS_TIM_BREAKINPUT(BreakInput));
2383
2384 switch (BreakInput)
2385 {
2386 case TIM_BREAKINPUT_BRK:
2387 {
2388 /* Check initial conditions */
2389 tmpbdtr = READ_REG(htim->Instance->BDTR);
2390 if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) &&
2391 (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
2392 {
2393 /* Break input BRK is disarmed */
2394 SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM);
2395 }
2396 break;
2397 }
2398 case TIM_BREAKINPUT_BRK2:
2399 {
2400 /* Check initial conditions */
2401 tmpbdtr = READ_REG(htim->Instance->BDTR);
2402 if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) &&
2403 (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
2404 {
2405 /* Break input BRK is disarmed */
2406 SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM);
2407 }
2408 break;
2409 }
2410 default:
2411 status = HAL_ERROR;
2412 break;
2413 }
2414
2415 return status;
2416 }
2417
2418 /**
2419 * @brief Arm the designated break input (when it operates in bidirectional mode).
2420 * @param htim TIM handle.
2421 * @param BreakInput Break input to arm
2422 * This parameter can be one of the following values:
2423 * @arg TIM_BREAKINPUT_BRK: Timer break input
2424 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
2425 * @note Arming is possible at anytime, even if fault is present.
2426 * @note Break input is automatically armed as soon as MOE bit is set.
2427 * @retval HAL status
2428 */
HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef * htim,uint32_t BreakInput)2429 HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput)
2430 {
2431 HAL_StatusTypeDef status = HAL_OK;
2432 uint32_t tickstart;
2433
2434 /* Check the parameters */
2435 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2436 assert_param(IS_TIM_BREAKINPUT(BreakInput));
2437
2438 switch (BreakInput)
2439 {
2440 case TIM_BREAKINPUT_BRK:
2441 {
2442 /* Check initial conditions */
2443 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID)
2444 {
2445 /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
2446 /* Init tickstart for timeout management */
2447 tickstart = HAL_GetTick();
2448 while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
2449 {
2450 if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
2451 {
2452 /* New check to avoid false timeout detection in case of preemption */
2453 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
2454 {
2455 return HAL_TIMEOUT;
2456 }
2457 }
2458 }
2459 }
2460 break;
2461 }
2462
2463 case TIM_BREAKINPUT_BRK2:
2464 {
2465 /* Check initial conditions */
2466 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID)
2467 {
2468 /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
2469 /* Init tickstart for timeout management */
2470 tickstart = HAL_GetTick();
2471 while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
2472 {
2473 if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
2474 {
2475 /* New check to avoid false timeout detection in case of preemption */
2476 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
2477 {
2478 return HAL_TIMEOUT;
2479 }
2480 }
2481 }
2482 }
2483 break;
2484 }
2485 default:
2486 status = HAL_ERROR;
2487 break;
2488 }
2489
2490 return status;
2491 }
2492
2493 /**
2494 * @}
2495 */
2496
2497 /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
2498 * @brief Extended Callbacks functions
2499 *
2500 @verbatim
2501 ==============================================================================
2502 ##### Extended Callbacks functions #####
2503 ==============================================================================
2504 [..]
2505 This section provides Extended TIM callback functions:
2506 (+) Timer Commutation callback
2507 (+) Timer Break callback
2508
2509 @endverbatim
2510 * @{
2511 */
2512
2513 /**
2514 * @brief Commutation callback in non-blocking mode
2515 * @param htim TIM handle
2516 * @retval None
2517 */
HAL_TIMEx_CommutCallback(TIM_HandleTypeDef * htim)2518 __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
2519 {
2520 /* Prevent unused argument(s) compilation warning */
2521 UNUSED(htim);
2522
2523 /* NOTE : This function should not be modified, when the callback is needed,
2524 the HAL_TIMEx_CommutCallback could be implemented in the user file
2525 */
2526 }
2527 /**
2528 * @brief Commutation half complete callback in non-blocking mode
2529 * @param htim TIM handle
2530 * @retval None
2531 */
HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef * htim)2532 __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
2533 {
2534 /* Prevent unused argument(s) compilation warning */
2535 UNUSED(htim);
2536
2537 /* NOTE : This function should not be modified, when the callback is needed,
2538 the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
2539 */
2540 }
2541
2542 /**
2543 * @brief Break detection callback in non-blocking mode
2544 * @param htim TIM handle
2545 * @retval None
2546 */
HAL_TIMEx_BreakCallback(TIM_HandleTypeDef * htim)2547 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
2548 {
2549 /* Prevent unused argument(s) compilation warning */
2550 UNUSED(htim);
2551
2552 /* NOTE : This function should not be modified, when the callback is needed,
2553 the HAL_TIMEx_BreakCallback could be implemented in the user file
2554 */
2555 }
2556
2557 /**
2558 * @brief Break2 detection callback in non blocking mode
2559 * @param htim: TIM handle
2560 * @retval None
2561 */
HAL_TIMEx_Break2Callback(TIM_HandleTypeDef * htim)2562 __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
2563 {
2564 /* Prevent unused argument(s) compilation warning */
2565 UNUSED(htim);
2566
2567 /* NOTE : This function Should not be modified, when the callback is needed,
2568 the HAL_TIMEx_Break2Callback could be implemented in the user file
2569 */
2570 }
2571 /**
2572 * @}
2573 */
2574
2575 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
2576 * @brief Extended Peripheral State functions
2577 *
2578 @verbatim
2579 ==============================================================================
2580 ##### Extended Peripheral State functions #####
2581 ==============================================================================
2582 [..]
2583 This subsection permits to get in run-time the status of the peripheral
2584 and the data flow.
2585
2586 @endverbatim
2587 * @{
2588 */
2589
2590 /**
2591 * @brief Return the TIM Hall Sensor interface handle state.
2592 * @param htim TIM Hall Sensor handle
2593 * @retval HAL state
2594 */
HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef * htim)2595 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim)
2596 {
2597 return htim->State;
2598 }
2599
2600 /**
2601 * @brief Return actual state of the TIM complementary channel.
2602 * @param htim TIM handle
2603 * @param ChannelN TIM Complementary channel
2604 * This parameter can be one of the following values:
2605 * @arg TIM_CHANNEL_1: TIM Channel 1
2606 * @arg TIM_CHANNEL_2: TIM Channel 2
2607 * @arg TIM_CHANNEL_3: TIM Channel 3
2608 * @retval TIM Complementary channel state
2609 */
HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef * htim,uint32_t ChannelN)2610 HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN)
2611 {
2612 HAL_TIM_ChannelStateTypeDef channel_state;
2613
2614 /* Check the parameters */
2615 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
2616
2617 channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
2618
2619 return channel_state;
2620 }
2621 /**
2622 * @}
2623 */
2624
2625 /**
2626 * @}
2627 */
2628
2629 /* Private functions ---------------------------------------------------------*/
2630 /** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
2631 * @{
2632 */
2633
2634 /**
2635 * @brief TIM DMA Commutation callback.
2636 * @param hdma pointer to DMA handle.
2637 * @retval None
2638 */
TIMEx_DMACommutationCplt(DMA_HandleTypeDef * hdma)2639 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
2640 {
2641 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2642
2643 /* Change the htim state */
2644 htim->State = HAL_TIM_STATE_READY;
2645
2646 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2647 htim->CommutationCallback(htim);
2648 #else
2649 HAL_TIMEx_CommutCallback(htim);
2650 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2651 }
2652
2653 /**
2654 * @brief TIM DMA Commutation half complete callback.
2655 * @param hdma pointer to DMA handle.
2656 * @retval None
2657 */
TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef * hdma)2658 void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
2659 {
2660 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2661
2662 /* Change the htim state */
2663 htim->State = HAL_TIM_STATE_READY;
2664
2665 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2666 htim->CommutationHalfCpltCallback(htim);
2667 #else
2668 HAL_TIMEx_CommutHalfCpltCallback(htim);
2669 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2670 }
2671
2672
2673 /**
2674 * @brief TIM DMA Delay Pulse complete callback (complementary channel).
2675 * @param hdma pointer to DMA handle.
2676 * @retval None
2677 */
TIM_DMADelayPulseNCplt(DMA_HandleTypeDef * hdma)2678 static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
2679 {
2680 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2681
2682 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
2683 {
2684 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
2685
2686 if (hdma->Init.Mode == DMA_NORMAL)
2687 {
2688 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2689 }
2690 }
2691 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
2692 {
2693 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
2694
2695 if (hdma->Init.Mode == DMA_NORMAL)
2696 {
2697 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2698 }
2699 }
2700 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
2701 {
2702 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
2703
2704 if (hdma->Init.Mode == DMA_NORMAL)
2705 {
2706 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
2707 }
2708 }
2709 else
2710 {
2711 /* nothing to do */
2712 }
2713
2714 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2715 htim->PWM_PulseFinishedCallback(htim);
2716 #else
2717 HAL_TIM_PWM_PulseFinishedCallback(htim);
2718 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2719
2720 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2721 }
2722
2723 /**
2724 * @brief TIM DMA error callback (complementary channel)
2725 * @param hdma pointer to DMA handle.
2726 * @retval None
2727 */
TIM_DMAErrorCCxN(DMA_HandleTypeDef * hdma)2728 static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
2729 {
2730 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2731
2732 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
2733 {
2734 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
2735 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2736 }
2737 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
2738 {
2739 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
2740 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2741 }
2742 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
2743 {
2744 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
2745 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
2746 }
2747 else
2748 {
2749 /* nothing to do */
2750 }
2751
2752 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2753 htim->ErrorCallback(htim);
2754 #else
2755 HAL_TIM_ErrorCallback(htim);
2756 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2757
2758 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2759 }
2760
2761 /**
2762 * @brief Enables or disables the TIM Capture Compare Channel xN.
2763 * @param TIMx to select the TIM peripheral
2764 * @param Channel specifies the TIM Channel
2765 * This parameter can be one of the following values:
2766 * @arg TIM_CHANNEL_1: TIM Channel 1
2767 * @arg TIM_CHANNEL_2: TIM Channel 2
2768 * @arg TIM_CHANNEL_3: TIM Channel 3
2769 * @param ChannelNState specifies the TIM Channel CCxNE bit new state.
2770 * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
2771 * @retval None
2772 */
TIM_CCxNChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelNState)2773 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
2774 {
2775 uint32_t tmp;
2776
2777 tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */
2778
2779 /* Reset the CCxNE Bit */
2780 TIMx->CCER &= ~tmp;
2781
2782 /* Set or reset the CCxNE Bit */
2783 TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */
2784 }
2785 /**
2786 * @}
2787 */
2788
2789 #endif /* HAL_TIM_MODULE_ENABLED */
2790 /**
2791 * @}
2792 */
2793
2794 /**
2795 * @}
2796 */
2797
