1# ARM Generic Interrupt Controller (GIC) configuration
2
3# Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
4# SPDX-License-Identifier: Apache-2.0
5
6if CPU_CORTEX
7
8config GIC
9	bool
10
11config GIC_V1
12	bool
13	select GIC
14	help
15	  The ARM Generic Interrupt Controller v1 (e.g. PL390) works with the
16	  ARM Cortex-family processors.
17
18config GIC_V2
19	bool
20	select GIC
21	help
22	  The ARM Generic Interrupt Controller v2 (e.g. GIC-400) works with the
23	  ARM Cortex-family processors.
24
25config GIC_V3
26	bool
27	select GIC
28	help
29	  The ARM Generic Interrupt Controller v3 (e.g. GIC-500 and GIC-600)
30	  works with the ARM Cortex-family processors.
31
32config GIC_VER
33	int
34	depends on GIC
35	default 1 if GIC_V1
36	default 2 if GIC_V2
37	default 3 if GIC_V3
38
39config GIC_SINGLE_SECURITY_STATE
40	bool
41	depends on GIC_V3
42	help
43	  Some ARM Cortex-family processors only supports single security
44	  state.
45
46config GIC_V3_RDIST_MATCHING_AFF0_ONLY
47	bool
48	depends on GIC_V3
49	default y if CPU_CORTEX_R52
50	help
51	  Some platforms only use aff0 to match mpdir and GICR.aff. With this
52	  enabled, we find the target redistributor by comparing the aff0 only.
53
54config GIC_V3_ITS
55	bool "GIC v3 Interrupt Translation Service"
56	depends on GIC_V3
57	# ITS generates Non-secure Group 1 LPI interrupts, requiring EL1NS
58	select ARMV8_A_NS
59	select DYNAMIC_INTERRUPTS
60	help
61	  Support for the optional Interrupt Translation Service used to translate
62	  hardware interrupt from PCIe MSI messages for example. Please note
63	  that ITS uses dynamic memory, so HEAP_MEM_POOL_SIZE should be
64	  enough to allocate ITS tables (size is probed at runtime).
65
66endif # CPU_CORTEX
67