1# STM32 entropy generator driver configuration
2
3# Copyright (c) 2017 Erwin Rol <erwin@erwinrol.com>
4# SPDX-License-Identifier: Apache-2.0
5
6menuconfig ENTROPY_STM32_RNG
7	bool "STM32 RNG driver"
8	default y
9	depends on DT_HAS_ST_STM32_RNG_ENABLED
10	select ENTROPY_HAS_DRIVER
11	select USE_STM32_LL_RNG
12	help
13	  This option enables the RNG processor, which is a entropy number
14	  generator, based on a continuous analog noise, that provides
15	  a entropy 32-bit value to the host when read. It is available for
16	  F4 (except STM32F401 & STM32F411), L4, F7, H7 and G4 series.
17
18if ENTROPY_STM32_RNG
19
20config ENTROPY_STM32_THR_POOL_SIZE
21	int "Thread-mode random number pool size"
22	range ENTROPY_STM32_THR_THRESHOLD 256
23	default 8
24	help
25	  Buffer length in bytes used to store entropy bytes generated by the
26	  hardware to make them ready for thread mode consumers.
27	  Please note, that size of the pool must be a power of 2.
28
29config ENTROPY_STM32_THR_THRESHOLD
30	int "Thread-mode random number pool low-water threshold"
31	range 4 255
32	help
33	  Low water-mark threshold in bytes to trigger entropy generation for
34	  thread mode consumers. As soon as the number of available bytes in the
35	  buffer goes below this number hardware entropy generation will be
36	  started.
37
38config ENTROPY_STM32_ISR_POOL_SIZE
39	int "ISR-mode random number pool size"
40	range ENTROPY_STM32_ISR_THRESHOLD 256
41	default 16
42	help
43	  Buffer length in bytes used to store entropy bytes generated by the
44	  hardware to make them ready for ISR consumers.
45	  Please note, that size of the pool must be a power of 2.
46
47config ENTROPY_STM32_ISR_THRESHOLD
48	int "ISR-mode random number pool low-water threshold"
49	range 12 255
50	help
51	  Low water-mark threshold in bytes to trigger entropy generation for
52	  ISR consumers. As soon as the number of available bytes in the
53	  buffer goes below this number hardware entropy generation will be
54	  started.
55
56config ENTROPY_STM32_CLK_CHECK
57	bool "Runtime clock configuration check"
58	default y
59	help
60	  Enables a check on RNG clock configuration. Correct clock
61	  configuration depends on STM32 series. Check reference manual if an
62	  error is reported.
63	  This check assumes CED (Clock Error Detected) bit is enabled (when
64	  available, CED is enabeld by default). Disable this check if CED is
65	  disabled.
66
67endif # ENTROPY_STM32_RNG
68