1 /*
2 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
3 * Copyright (c) 2023, NVIDIA Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <assert.h>
9
10 #include <arch.h>
11 #include <arch_helpers.h>
12 #include <common/debug.h>
13 #include <common/interrupt_props.h>
14 #include <drivers/arm/gic600_multichip.h>
15 #include <drivers/arm/gic_common.h>
16
17 #include <platform_def.h>
18
19 #include "../common/gic_common_private.h"
20 #include "gicv3_private.h"
21
gicv3_get_multichip_base(uint32_t spi_id,uintptr_t gicd_base)22 uintptr_t gicv3_get_multichip_base(uint32_t spi_id, uintptr_t gicd_base)
23 {
24 #if GICV3_IMPL_GIC600_MULTICHIP
25 if (gic600_multichip_is_initialized()) {
26 return gic600_multichip_gicd_base_for_spi(spi_id);
27 }
28 #endif
29 return gicd_base;
30 }
31
32 /******************************************************************************
33 * This function marks the core as awake in the re-distributor and
34 * ensures that the interface is active.
35 *****************************************************************************/
gicv3_rdistif_mark_core_awake(uintptr_t gicr_base)36 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base)
37 {
38 /*
39 * The WAKER_PS_BIT should be changed to 0
40 * only when WAKER_CA_BIT is 1.
41 */
42 assert((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U);
43
44 /* Mark the connected core as awake */
45 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_PS_BIT);
46
47 /* Wait till the WAKER_CA_BIT changes to 0 */
48 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U) {
49 }
50 }
51
52 /******************************************************************************
53 * This function marks the core as asleep in the re-distributor and ensures
54 * that the interface is quiescent.
55 *****************************************************************************/
gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base)56 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base)
57 {
58 /* Mark the connected core as asleep */
59 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_PS_BIT);
60
61 /* Wait till the WAKER_CA_BIT changes to 1 */
62 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) == 0U) {
63 }
64 }
65
66 /*******************************************************************************
67 * This function probes the Redistributor frames when the driver is initialised
68 * and saves their base addresses. These base addresses are used later to
69 * initialise each Redistributor interface.
70 ******************************************************************************/
gicv3_rdistif_base_addrs_probe(uintptr_t * rdistif_base_addrs,unsigned int rdistif_num,uintptr_t gicr_base,mpidr_hash_fn mpidr_to_core_pos)71 void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs,
72 unsigned int rdistif_num,
73 uintptr_t gicr_base,
74 mpidr_hash_fn mpidr_to_core_pos)
75 {
76 u_register_t mpidr;
77 unsigned int proc_num;
78 uint64_t typer_val;
79 uintptr_t rdistif_base = gicr_base;
80
81 assert(rdistif_base_addrs != NULL);
82
83 /*
84 * Iterate over the Redistributor frames. Store the base address of each
85 * frame in the platform provided array. Use the "Processor Number"
86 * field to index into the array if the platform has not provided a hash
87 * function to convert an MPIDR (obtained from the "Affinity Value"
88 * field into a linear index.
89 */
90 do {
91 typer_val = gicr_read_typer(rdistif_base);
92 if (mpidr_to_core_pos != NULL) {
93 mpidr = mpidr_from_gicr_typer(typer_val);
94 proc_num = mpidr_to_core_pos(mpidr);
95 } else {
96 proc_num = (typer_val >> TYPER_PROC_NUM_SHIFT) &
97 TYPER_PROC_NUM_MASK;
98 }
99
100 if (proc_num < rdistif_num) {
101 rdistif_base_addrs[proc_num] = rdistif_base;
102 }
103 rdistif_base += gicv3_redist_size(typer_val);
104 } while ((typer_val & TYPER_LAST_BIT) == 0U);
105 }
106
107 /*******************************************************************************
108 * Helper function to get the maximum SPI INTID + 1.
109 ******************************************************************************/
gicv3_get_spi_limit(uintptr_t gicd_base)110 unsigned int gicv3_get_spi_limit(uintptr_t gicd_base)
111 {
112 unsigned int spi_limit;
113 unsigned int typer_reg = gicd_read_typer(gicd_base);
114
115 /* (maximum SPI INTID + 1) is equal to 32 * (GICD_TYPER.ITLinesNumber+1) */
116 spi_limit = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5;
117
118 /* Filter out special INTIDs 1020-1023 */
119 if (spi_limit > (MAX_SPI_ID + 1U)) {
120 return MAX_SPI_ID + 1U;
121 }
122
123 return spi_limit;
124 }
125
126 #if GIC_EXT_INTID
127 /*******************************************************************************
128 * Helper function to get the maximum ESPI INTID + 1.
129 ******************************************************************************/
gicv3_get_espi_limit(uintptr_t gicd_base)130 unsigned int gicv3_get_espi_limit(uintptr_t gicd_base)
131 {
132 unsigned int typer_reg = gicd_read_typer(gicd_base);
133
134 /* Check if extended SPI range is implemented */
135 if ((typer_reg & TYPER_ESPI) != 0U) {
136 /*
137 * (maximum ESPI INTID + 1) is equal to
138 * 32 * (GICD_TYPER.ESPI_range + 1) + 4096
139 */
140 return ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) &
141 TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID;
142 }
143
144 return 0U;
145 }
146 #endif /* GIC_EXT_INTID */
147
148 /*******************************************************************************
149 * Helper function to configure the default attributes of (E)SPIs.
150 ******************************************************************************/
gicv3_spis_config_defaults(uintptr_t gicd_base)151 void gicv3_spis_config_defaults(uintptr_t gicd_base)
152 {
153 unsigned int i, num_ints;
154 #if GIC_EXT_INTID
155 unsigned int num_eints;
156 #endif
157
158 num_ints = gicv3_get_spi_limit(gicd_base);
159 INFO("Maximum SPI INTID supported: %u\n", num_ints - 1);
160
161 /* Treat all (E)SPIs as G1NS by default. We do 32 at a time. */
162 for (i = MIN_SPI_ID; i < num_ints; i += (1U << IGROUPR_SHIFT)) {
163 gicd_write_igroupr(gicv3_get_multichip_base(i, gicd_base), i, ~0U);
164 }
165
166 #if GIC_EXT_INTID
167 num_eints = gicv3_get_espi_limit(gicd_base);
168 if (num_eints != 0U) {
169 INFO("Maximum ESPI INTID supported: %u\n", num_eints - 1);
170
171 for (i = MIN_ESPI_ID; i < num_eints;
172 i += (1U << IGROUPR_SHIFT)) {
173 gicd_write_igroupr(gicv3_get_multichip_base(i, gicd_base), i, ~0U);
174 }
175 } else {
176 INFO("ESPI range is not implemented.\n");
177 }
178 #endif
179
180 /* Setup the default (E)SPI priorities doing four at a time */
181 for (i = MIN_SPI_ID; i < num_ints; i += (1U << IPRIORITYR_SHIFT)) {
182 gicd_write_ipriorityr(gicv3_get_multichip_base(i, gicd_base), i, GICD_IPRIORITYR_DEF_VAL);
183 }
184
185 #if GIC_EXT_INTID
186 for (i = MIN_ESPI_ID; i < num_eints;
187 i += (1U << IPRIORITYR_SHIFT)) {
188 gicd_write_ipriorityr(gicv3_get_multichip_base(i, gicd_base), i, GICD_IPRIORITYR_DEF_VAL);
189 }
190 #endif
191 /*
192 * Treat all (E)SPIs as level triggered by default, write 16 at a time
193 */
194 for (i = MIN_SPI_ID; i < num_ints; i += (1U << ICFGR_SHIFT)) {
195 gicd_write_icfgr(gicv3_get_multichip_base(i, gicd_base), i, 0U);
196 }
197
198 #if GIC_EXT_INTID
199 for (i = MIN_ESPI_ID; i < num_eints; i += (1U << ICFGR_SHIFT)) {
200 gicd_write_icfgr(gicv3_get_multichip_base(i, gicd_base), i, 0U);
201 }
202 #endif
203 }
204
205 /*******************************************************************************
206 * Helper function to configure properties of secure (E)SPIs
207 ******************************************************************************/
gicv3_secure_spis_config_props(uintptr_t gicd_base,const interrupt_prop_t * interrupt_props,unsigned int interrupt_props_num)208 unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base,
209 const interrupt_prop_t *interrupt_props,
210 unsigned int interrupt_props_num)
211 {
212 unsigned int i;
213 const interrupt_prop_t *current_prop;
214 unsigned long long gic_affinity_val;
215 unsigned int ctlr_enable = 0U;
216
217 /* Make sure there's a valid property array */
218 if (interrupt_props_num > 0U) {
219 assert(interrupt_props != NULL);
220 }
221
222 for (i = 0U; i < interrupt_props_num; i++) {
223 current_prop = &interrupt_props[i];
224
225 unsigned int intr_num = current_prop->intr_num;
226 uintptr_t multichip_gicd_base;
227
228 /* Skip SGI, (E)PPI and LPI interrupts */
229 if (!IS_SPI(intr_num)) {
230 continue;
231 }
232
233 multichip_gicd_base =
234 gicv3_get_multichip_base(intr_num, gicd_base);
235
236 /* Configure this interrupt as a secure interrupt */
237 gicd_clr_igroupr(multichip_gicd_base, intr_num);
238
239 /* Configure this interrupt as G0 or a G1S interrupt */
240 assert((current_prop->intr_grp == INTR_GROUP0) ||
241 (current_prop->intr_grp == INTR_GROUP1S));
242
243 if (current_prop->intr_grp == INTR_GROUP1S) {
244 gicd_set_igrpmodr(multichip_gicd_base, intr_num);
245 ctlr_enable |= CTLR_ENABLE_G1S_BIT;
246 } else {
247 gicd_clr_igrpmodr(multichip_gicd_base, intr_num);
248 ctlr_enable |= CTLR_ENABLE_G0_BIT;
249 }
250
251 /* Set interrupt configuration */
252 gicd_set_icfgr(multichip_gicd_base, intr_num,
253 current_prop->intr_cfg);
254
255 /* Set the priority of this interrupt */
256 gicd_set_ipriorityr(multichip_gicd_base, intr_num,
257 current_prop->intr_pri);
258
259 /* Target (E)SPIs to the primary CPU */
260 gic_affinity_val =
261 gicd_irouter_val_from_mpidr(read_mpidr(), 0U);
262 gicd_write_irouter(multichip_gicd_base, intr_num,
263 gic_affinity_val);
264
265 /* Enable this interrupt */
266 gicd_set_isenabler(multichip_gicd_base, intr_num);
267 }
268
269 return ctlr_enable;
270 }
271
272 /*******************************************************************************
273 * Helper function to configure the default attributes of (E)PPIs/SGIs
274 ******************************************************************************/
gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base)275 void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base)
276 {
277 unsigned int i, ppi_regs_num, regs_num;
278
279 #if GIC_EXT_INTID
280 /* Calculate number of PPI registers */
281 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >>
282 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1;
283 /* All other values except PPInum [0-2] are reserved */
284 if (ppi_regs_num > 3U) {
285 ppi_regs_num = 1U;
286 }
287 #else
288 ppi_regs_num = 1U;
289 #endif
290 /*
291 * Disable all SGIs (imp. def.)/(E)PPIs before configuring them.
292 * This is a more scalable approach as it avoids clearing
293 * the enable bits in the GICD_CTLR.
294 */
295 for (i = 0U; i < ppi_regs_num; ++i) {
296 gicr_write_icenabler(gicr_base, i, ~0U);
297 }
298
299 /* Wait for pending writes to GICR_ICENABLER */
300 gicr_wait_for_pending_write(gicr_base);
301
302 /* 32 interrupt IDs per GICR_IGROUPR register */
303 for (i = 0U; i < ppi_regs_num; ++i) {
304 /* Treat all SGIs/(E)PPIs as G1NS by default */
305 gicr_write_igroupr(gicr_base, i, ~0U);
306 }
307
308 /* 4 interrupt IDs per GICR_IPRIORITYR register */
309 regs_num = ppi_regs_num << 3;
310 for (i = 0U; i < regs_num; ++i) {
311 /* Setup the default (E)PPI/SGI priorities doing 4 at a time */
312 gicr_write_ipriorityr(gicr_base, i << 2, GICD_IPRIORITYR_DEF_VAL);
313 }
314
315 /* 16 interrupt IDs per GICR_ICFGR register */
316 regs_num = ppi_regs_num << 1;
317 for (i = (MIN_PPI_ID >> ICFGR_SHIFT); i < regs_num; ++i) {
318 /* Configure all (E)PPIs as level triggered by default */
319 gicr_write_icfgr(gicr_base, i, 0U);
320 }
321 }
322
323 /*******************************************************************************
324 * Helper function to configure properties of secure G0 and G1S (E)PPIs and SGIs
325 ******************************************************************************/
gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base,const interrupt_prop_t * interrupt_props,unsigned int interrupt_props_num)326 unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base,
327 const interrupt_prop_t *interrupt_props,
328 unsigned int interrupt_props_num)
329 {
330 unsigned int i;
331 const interrupt_prop_t *current_prop;
332 unsigned int ctlr_enable = 0U;
333
334 /* Make sure there's a valid property array */
335 if (interrupt_props_num > 0U) {
336 assert(interrupt_props != NULL);
337 }
338
339 for (i = 0U; i < interrupt_props_num; i++) {
340 current_prop = &interrupt_props[i];
341
342 unsigned int intr_num = current_prop->intr_num;
343
344 /* Skip (E)SPI interrupt */
345 if (!IS_SGI_PPI(intr_num)) {
346 continue;
347 }
348
349 /* Configure this interrupt as a secure interrupt */
350 gicr_clr_igroupr(gicr_base, intr_num);
351
352 /* Configure this interrupt as G0 or a G1S interrupt */
353 assert((current_prop->intr_grp == INTR_GROUP0) ||
354 (current_prop->intr_grp == INTR_GROUP1S));
355
356 if (current_prop->intr_grp == INTR_GROUP1S) {
357 gicr_set_igrpmodr(gicr_base, intr_num);
358 ctlr_enable |= CTLR_ENABLE_G1S_BIT;
359 } else {
360 gicr_clr_igrpmodr(gicr_base, intr_num);
361 ctlr_enable |= CTLR_ENABLE_G0_BIT;
362 }
363
364 /* Set the priority of this interrupt */
365 gicr_set_ipriorityr(gicr_base, intr_num,
366 current_prop->intr_pri);
367
368 /*
369 * Set interrupt configuration for (E)PPIs.
370 * Configurations for SGIs 0-15 are ignored.
371 */
372 if (intr_num >= MIN_PPI_ID) {
373 gicr_set_icfgr(gicr_base, intr_num,
374 current_prop->intr_cfg);
375 }
376
377 /* Enable this interrupt */
378 gicr_set_isenabler(gicr_base, intr_num);
379 }
380
381 return ctlr_enable;
382 }
383
384 /**
385 * gicv3_rdistif_get_number_frames() - determine size of GICv3 GICR region
386 * @gicr_frame: base address of the GICR region to check
387 *
388 * This iterates over the GICR_TYPER registers of multiple GICR frames in
389 * a GICR region, to find the instance which has the LAST bit set. For most
390 * systems this corresponds to the number of cores handled by a redistributor,
391 * but there could be disabled cores among them.
392 * It assumes that each GICR region is fully accessible (till the LAST bit
393 * marks the end of the region).
394 * If a platform has multiple GICR regions, this function would need to be
395 * called multiple times, providing the respective GICR base address each time.
396 *
397 * Return: number of valid GICR frames (at least 1, up to PLATFORM_CORE_COUNT)
398 ******************************************************************************/
gicv3_rdistif_get_number_frames(const uintptr_t gicr_frame)399 unsigned int gicv3_rdistif_get_number_frames(const uintptr_t gicr_frame)
400 {
401 uintptr_t rdistif_base = gicr_frame;
402 unsigned int count;
403
404 for (count = 1U; count < PLATFORM_CORE_COUNT; count++) {
405 uint64_t typer_val = gicr_read_typer(rdistif_base);
406
407 if ((typer_val & TYPER_LAST_BIT) != 0U) {
408 break;
409 }
410 rdistif_base += gicv3_redist_size(typer_val);
411 }
412
413 return count;
414 }
415
gicv3_get_component_partnum(const uintptr_t gic_frame)416 unsigned int gicv3_get_component_partnum(const uintptr_t gic_frame)
417 {
418 unsigned int part_id;
419
420 /*
421 * The lower 8 bits of PIDR0, complemented by the lower 4 bits of
422 * PIDR1 contain a part number identifying the GIC component at a
423 * particular base address.
424 */
425 part_id = mmio_read_32(gic_frame + GICD_PIDR0_GICV3) & 0xff;
426 part_id |= (mmio_read_32(gic_frame + GICD_PIDR1_GICV3) << 8) & 0xf00;
427
428 return part_id;
429 }
430
431 /*******************************************************************************
432 * Helper function to return product ID and revision of GIC
433 * @gicd_base: base address of the GIC distributor
434 * @gic_prod_id: retrieved product id of GIC
435 * @gic_rev: retrieved revision of GIC
436 ******************************************************************************/
gicv3_get_component_prodid_rev(const uintptr_t gicd_base,unsigned int * gic_prod_id,uint8_t * gic_rev)437 void gicv3_get_component_prodid_rev(const uintptr_t gicd_base,
438 unsigned int *gic_prod_id,
439 uint8_t *gic_rev)
440 {
441 unsigned int gicd_iidr;
442 uint8_t gic_variant;
443
444 gicd_iidr = gicd_read_iidr(gicd_base);
445 *gic_prod_id = gicd_iidr >> IIDR_PRODUCT_ID_SHIFT;
446 *gic_prod_id &= IIDR_PRODUCT_ID_MASK;
447
448 gic_variant = gicd_iidr >> IIDR_VARIANT_SHIFT;
449 gic_variant &= IIDR_VARIANT_MASK;
450
451 *gic_rev = gicd_iidr >> IIDR_REV_SHIFT;
452 *gic_rev &= IIDR_REV_MASK;
453
454 /*
455 * pack gic variant and gic_rev in 1 byte
456 * gic_rev = gic_variant[7:4] and gic_rev[0:3]
457 */
458 *gic_rev = *gic_rev | gic_variant << 0x4;
459
460 }
461
