1 /*
2 * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
3 * Copyright (c) 2021, Arm Limited. All rights reserved.
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 */
17
18 #include "tfm_spm_log.h"
19 #include "driver_ppu.h"
20 #include "pc_config.h"
21 #include "ppu_config.h"
22 #include "RTE_Device.h"
23
24 #include "cy_device_headers.h"
25 #include "cy_prot.h"
26
27 struct ms_ppu_config {
28 uint16_t pcMask;
29 cy_en_prot_perm_t user;
30 cy_en_prot_perm_t priv;
31 bool secure;
32 };
33
34 struct ppu_resources {
35 enum ppu_type ppu_type;
36 union ppu {
37 PERI_MS_PPU_PR_Type *ms_ppu_pr;
38 PERI_MS_PPU_FX_Type *ms_ppu_fx;
39 PERI_PPU_PR_Type *ppu_pr;
40 PERI_PPU_GR_Type *ppu_gr;
41 PERI_GR_PPU_SL_Type *gr_ppu_sl;
42 PERI_GR_PPU_RG_Type *gr_ppu_rg;
43 } ppu;
44 union master_config {
45 struct ms_ppu_config ms_ppu;
46 cy_stc_ppu_prog_cfg_t ppu_pr;
47 cy_stc_ppu_gr_cfg_t ppu_gr;
48 cy_stc_ppu_sl_cfg_t gr_ppu_sl;
49 cy_stc_ppu_rg_cfg_t gr_ppu_rg;
50 } master_cfg;
51 union slave_config {
52 struct ms_ppu_config ms_ppu;
53 cy_stc_ppu_prog_cfg_t ppu_pr;
54 cy_stc_ppu_gr_cfg_t ppu_gr;
55 cy_stc_ppu_sl_cfg_t gr_ppu_sl;
56 cy_stc_ppu_rg_cfg_t gr_ppu_rg;
57 } slave_cfg;
58 /* These are only applicable when ppu_type is MS_PPU_PR */
59 uint32_t slave_address;
60 cy_en_prot_size_t slave_region_size;
61 };
62
63 /* Affect all 8 subregions */
64 #define ALL_ENABLED 0
65
66 /* The PDL doesn't work if we pass in pcMask values that are not supported by the hardware */
67 /* Note that this macro depends on the values of CY_PROT_PCMASKx macros */
68 #define FILTER_PCS(x) ((x) & ((1<<(PERI_PC_NR-1))-1))
69
70 /* Shared Driver wrapper functions */
PPU_Configure(const PPU_Resources * ppu_dev)71 cy_en_prot_status_t PPU_Configure(const PPU_Resources *ppu_dev)
72 {
73 cy_en_prot_status_t ret;
74
75 switch(ppu_dev->ppu_type) {
76 /* This block is only needed if there are MS_PPU_PR PPUs on the board */
77 #if defined(PERI_MS_PPU_PR0)
78 case MS_PPU_PR:
79 ret = Cy_Prot_ConfigPpuProgSlaveAddr(ppu_dev->ppu.ms_ppu_pr,
80 ppu_dev->slave_address,
81 ppu_dev->slave_region_size);
82 if (ret != CY_PROT_SUCCESS)
83 return ret;
84 /* Disable access from any other Protection Contexts */
85 ret = Cy_Prot_ConfigPpuProgSlaveAtt(ppu_dev->ppu.ms_ppu_pr,
86 FILTER_PCS(~ppu_dev->slave_cfg.ms_ppu.pcMask),
87 CY_PROT_PERM_DISABLED,
88 CY_PROT_PERM_DISABLED,
89 true);
90 if (ret != CY_PROT_SUCCESS)
91 return ret;
92 ret = Cy_Prot_ConfigPpuProgSlaveAtt(ppu_dev->ppu.ms_ppu_pr,
93 FILTER_PCS(ppu_dev->slave_cfg.ms_ppu.pcMask),
94 ppu_dev->slave_cfg.ms_ppu.user,
95 ppu_dev->slave_cfg.ms_ppu.priv,
96 ppu_dev->slave_cfg.ms_ppu.secure);
97 if (ret != CY_PROT_SUCCESS)
98 return ret;
99 ret = Cy_Prot_EnablePpuProgSlaveRegion(ppu_dev->ppu.ms_ppu_pr);
100 if (ret != CY_PROT_SUCCESS)
101 return ret;
102 /* Read-only access from any other Protection Contexts */
103 ret = Cy_Prot_ConfigPpuProgMasterAtt(ppu_dev->ppu.ms_ppu_pr,
104 FILTER_PCS(~ppu_dev->master_cfg.ms_ppu.pcMask),
105 CY_PROT_PERM_R,
106 CY_PROT_PERM_R,
107 true);
108 if (ret != CY_PROT_SUCCESS)
109 return ret;
110 ret = Cy_Prot_ConfigPpuProgMasterAtt(ppu_dev->ppu.ms_ppu_pr,
111 FILTER_PCS(ppu_dev->master_cfg.ms_ppu.pcMask),
112 ppu_dev->master_cfg.ms_ppu.user,
113 ppu_dev->master_cfg.ms_ppu.priv,
114 ppu_dev->master_cfg.ms_ppu.secure);
115 break;
116 #endif
117
118 /* This block is only needed if there are MS_PPU_FX PPUs on the board */
119 #if defined(PERI_MS_PPU_FX_PERI_MAIN)
120 case MS_PPU_FX:
121 /* Disable access from any other Protection Contexts */
122 ret = Cy_Prot_ConfigPpuFixedSlaveAtt(ppu_dev->ppu.ms_ppu_fx,
123 FILTER_PCS(~ppu_dev->slave_cfg.ms_ppu.pcMask),
124 CY_PROT_PERM_DISABLED,
125 CY_PROT_PERM_DISABLED,
126 true);
127 if (ret != CY_PROT_SUCCESS)
128 return ret;
129 ret = Cy_Prot_ConfigPpuFixedSlaveAtt(ppu_dev->ppu.ms_ppu_fx,
130 FILTER_PCS(ppu_dev->slave_cfg.ms_ppu.pcMask),
131 ppu_dev->slave_cfg.ms_ppu.user,
132 ppu_dev->slave_cfg.ms_ppu.priv,
133 ppu_dev->slave_cfg.ms_ppu.secure);
134 if (ret != CY_PROT_SUCCESS)
135 return ret;
136 /* Read-only access from any other Protection Contexts */
137 ret = Cy_Prot_ConfigPpuFixedMasterAtt(ppu_dev->ppu.ms_ppu_fx,
138 FILTER_PCS(~ppu_dev->master_cfg.ms_ppu.pcMask),
139 CY_PROT_PERM_R,
140 CY_PROT_PERM_R,
141 true);
142 if (ret != CY_PROT_SUCCESS)
143 return ret;
144 ret = Cy_Prot_ConfigPpuFixedMasterAtt(ppu_dev->ppu.ms_ppu_fx,
145 FILTER_PCS(ppu_dev->master_cfg.ms_ppu.pcMask),
146 ppu_dev->master_cfg.ms_ppu.user,
147 ppu_dev->master_cfg.ms_ppu.priv,
148 ppu_dev->master_cfg.ms_ppu.secure);
149 break;
150 #endif
151
152 /* This block is only needed if there are PPU_PR PPUs on the board */
153 #if defined(PERI_PPU_PR0)
154 case PPU_PR:
155 ret = Cy_Prot_ConfigPpuProgSlaveStruct(ppu_dev->ppu.ppu_pr,
156 &ppu_dev->slave_cfg.ppu_pr);
157 if (ret != CY_PROT_SUCCESS)
158 return ret;
159 ret = Cy_Prot_EnablePpuProgSlaveStruct(ppu_dev->ppu.ppu_pr);
160 if (ret != CY_PROT_SUCCESS)
161 return ret;
162 ret = Cy_Prot_ConfigPpuProgMasterStruct(ppu_dev->ppu.ppu_pr,
163 &ppu_dev->master_cfg.ppu_pr);
164 if (ret != CY_PROT_SUCCESS)
165 return ret;
166 ret = Cy_Prot_EnablePpuProgMasterStruct(ppu_dev->ppu.ppu_pr);
167 break;
168 #endif
169
170 /* This block is only needed if there are PPU_GR PPUs on the board */
171 #if defined(PERI_PPU_GR0)
172 case PPU_GR:
173 ret = Cy_Prot_ConfigPpuFixedGrSlaveStruct(ppu_dev->ppu.ppu_gr,
174 &ppu_dev->slave_cfg.ppu_gr);
175 if (ret != CY_PROT_SUCCESS)
176 return ret;
177 ret = Cy_Prot_EnablePpuFixedGrSlaveStruct(ppu_dev->ppu.ppu_gr);
178 if (ret != CY_PROT_SUCCESS)
179 return ret;
180 ret = Cy_Prot_ConfigPpuFixedGrMasterStruct(ppu_dev->ppu.ppu_gr,
181 &ppu_dev->master_cfg.ppu_gr);
182 if (ret != CY_PROT_SUCCESS)
183 return ret;
184 ret = Cy_Prot_EnablePpuFixedGrMasterStruct(ppu_dev->ppu.ppu_gr);
185 break;
186 #endif
187
188 /* This block is only needed if there are GR_PPU_SL PPUs on the board */
189 #if defined(PERI_GR_PPU_SL_CRYPTO)
190 case GR_PPU_SL:
191 ret = Cy_Prot_ConfigPpuFixedSlSlaveStruct(ppu_dev->ppu.gr_ppu_sl,
192 &ppu_dev->slave_cfg.gr_ppu_sl);
193 if (ret != CY_PROT_SUCCESS)
194 return ret;
195 ret = Cy_Prot_EnablePpuFixedSlSlaveStruct(ppu_dev->ppu.gr_ppu_sl);
196 if (ret != CY_PROT_SUCCESS)
197 return ret;
198 ret = Cy_Prot_ConfigPpuFixedSlMasterStruct(ppu_dev->ppu.gr_ppu_sl,
199 &ppu_dev->master_cfg.gr_ppu_sl);
200 if (ret != CY_PROT_SUCCESS)
201 return ret;
202 ret = Cy_Prot_EnablePpuFixedSlMasterStruct(ppu_dev->ppu.gr_ppu_sl);
203 break;
204 #endif
205
206 /* This block is only needed if there are GR_PPU_RG PPUs on the board */
207 #if defined(PERI_GR_PPU_RG_IPC_STRUCT0)
208 case GR_PPU_RG:
209 ret = Cy_Prot_ConfigPpuFixedRgSlaveStruct(ppu_dev->ppu.gr_ppu_rg,
210 &ppu_dev->slave_cfg.gr_ppu_rg);
211 if (ret != CY_PROT_SUCCESS)
212 return ret;
213 ret = Cy_Prot_EnablePpuFixedRgSlaveStruct(ppu_dev->ppu.gr_ppu_rg);
214 if (ret != CY_PROT_SUCCESS)
215 return ret;
216 ret = Cy_Prot_ConfigPpuFixedRgMasterStruct(ppu_dev->ppu.gr_ppu_rg,
217 &ppu_dev->master_cfg.gr_ppu_rg);
218 if (ret != CY_PROT_SUCCESS)
219 return ret;
220 ret = Cy_Prot_EnablePpuFixedRgMasterStruct(ppu_dev->ppu.gr_ppu_rg);
221 break;
222 #endif
223
224 default:
225 SPMLOG_ERRMSGVAL("Unexpected peripheral type ", ppu_dev->ppu_type);
226 return CY_PROT_BAD_PARAM;
227 }
228
229 return ret;
230 }
231
232 #define DEFINE_MS_PPU_PR(N) const PPU_Resources N##_PPU_Resources = { \
233 .ppu_type = MS_PPU_PR, \
234 .ppu = {.ms_ppu_pr = PERI_MS_PPU_##N}, \
235 .master_cfg.ms_ppu = PPU_##N##_MASTER_CONFIG, \
236 .slave_cfg.ms_ppu = PPU_##N##_SLAVE_CONFIG, \
237 .slave_address = PPU_##N##_SLAVE_ADDRESS, \
238 .slave_region_size = PPU_##N##_SLAVE_REGION_SIZE, \
239 };
240
241 #define DEFINE_MS_PPU_FX(N) const PPU_Resources N##_PPU_Resources = { \
242 .ppu_type = MS_PPU_FX, \
243 .ppu = {.ms_ppu_fx = PERI_MS_PPU_FX_##N}, \
244 .master_cfg.ms_ppu = PPU_##N##_MASTER_CONFIG, \
245 .slave_cfg.ms_ppu = PPU_##N##_SLAVE_CONFIG, \
246 };
247
248 #define DEFINE_PPU_PR(N) const PPU_Resources N##_PPU_Resources = { \
249 .ppu_type = PPU_PR, \
250 .ppu = {.ppu_pr = PERI_PPU_##N}, \
251 .master_cfg.ppu_pr = PPU_##N##_MASTER_CONFIG, \
252 .slave_cfg.ppu_pr = PPU_##N##_SLAVE_CONFIG, \
253 };
254
255 #define DEFINE_PPU_GR(N) const PPU_Resources N##_PPU_Resources = { \
256 .ppu_type = PPU_GR, \
257 .ppu = {.ppu_gr = PERI_PPU_##N}, \
258 .master_cfg.ppu_gr = PPU_##N##_MASTER_CONFIG, \
259 .slave_cfg.ppu_gr = PPU_##N##_SLAVE_CONFIG, \
260 };
261
262 #define DEFINE_GR_PPU_SL(N) const PPU_Resources N##_PPU_Resources = { \
263 .ppu_type = GR_PPU_SL, \
264 .ppu = {.gr_ppu_sl = PERI_GR_PPU_##N}, \
265 .master_cfg.gr_ppu_sl = PPU_##N##_MASTER_CONFIG, \
266 .slave_cfg.gr_ppu_sl = PPU_##N##_SLAVE_CONFIG, \
267 };
268
269 #define DEFINE_GR_PPU_RG(N) const PPU_Resources N##_PPU_Resources = { \
270 .ppu_type = GR_PPU_RG, \
271 .ppu = {.gr_ppu_rg = PERI_GR_PPU_##N}, \
272 .master_cfg.gr_ppu_rg = PPU_##N##_MASTER_CONFIG, \
273 .slave_cfg.gr_ppu_rg = PPU_##N##_SLAVE_CONFIG, \
274 };
275
276 #if (RTE_MS_PPU_PR7)
277 DEFINE_MS_PPU_PR(PR7)
278 #endif
279
280 #if (RTE_MS_PPU_PERI_MAIN)
281 DEFINE_MS_PPU_FX(PERI_MAIN)
282 #endif
283
284 #if (RTE_MS_PPU_PERI_GR0_GROUP)
285 DEFINE_MS_PPU_FX(PERI_GR0_GROUP)
286 #endif
287
288 #if (RTE_MS_PPU_PERI_GR1_GROUP)
289 DEFINE_MS_PPU_FX(PERI_GR1_GROUP)
290 #endif
291
292 #if (RTE_MS_PPU_PERI_GR2_GROUP)
293 DEFINE_MS_PPU_FX(PERI_GR2_GROUP)
294 #endif
295
296 #if (RTE_MS_PPU_PERI_GR3_GROUP)
297 DEFINE_MS_PPU_FX(PERI_GR3_GROUP)
298 #endif
299
300 #if (RTE_MS_PPU_PERI_GR4_GROUP)
301 DEFINE_MS_PPU_FX(PERI_GR4_GROUP)
302 #endif
303
304 #if (RTE_MS_PPU_PERI_GR6_GROUP)
305 DEFINE_MS_PPU_FX(PERI_GR6_GROUP)
306 #endif
307
308 #if (RTE_MS_PPU_PERI_GR9_GROUP)
309 DEFINE_MS_PPU_FX(PERI_GR9_GROUP)
310 #endif
311
312 #if (RTE_MS_PPU_PERI_GR10_GROUP)
313 DEFINE_MS_PPU_FX(PERI_GR10_GROUP)
314 #endif
315
316 #if (RTE_MS_PPU_PERI_TR)
317 DEFINE_MS_PPU_FX(PERI_TR)
318 #endif
319
320 #if (RTE_MS_PPU_CRYPTO_MAIN)
321 DEFINE_MS_PPU_FX(CRYPTO_MAIN)
322 #endif
323
324 #if (RTE_MS_PPU_CRYPTO_CRYPTO)
325 DEFINE_MS_PPU_FX(CRYPTO_CRYPTO)
326 #endif
327
328 #if (RTE_MS_PPU_CRYPTO_BOOT)
329 DEFINE_MS_PPU_FX(CRYPTO_BOOT)
330 #endif
331
332 #if (RTE_MS_PPU_CRYPTO_KEY0)
333 DEFINE_MS_PPU_FX(CRYPTO_KEY0)
334 #endif
335
336 #if (RTE_MS_PPU_CRYPTO_KEY1)
337 DEFINE_MS_PPU_FX(CRYPTO_KEY1)
338 #endif
339
340 #if (RTE_MS_PPU_CRYPTO_BUF)
341 DEFINE_MS_PPU_FX(CRYPTO_BUF)
342 #endif
343
344 #if (RTE_MS_PPU_CPUSS_CM4)
345 DEFINE_MS_PPU_FX(CPUSS_CM4)
346 #endif
347
348 #if (RTE_MS_PPU_CPUSS_CM0)
349 DEFINE_MS_PPU_FX(CPUSS_CM0)
350 #endif
351
352 #if (RTE_MS_PPU_CPUSS_CM0_INT)
353 DEFINE_MS_PPU_FX(CPUSS_CM0_INT)
354 #endif
355
356 #if (RTE_MS_PPU_CPUSS_CM4_INT)
357 DEFINE_MS_PPU_FX(CPUSS_CM4_INT)
358 #endif
359
360 #if (RTE_MS_PPU_FAULT_STRUCT0_MAIN)
361 DEFINE_MS_PPU_FX(FAULT_STRUCT0_MAIN)
362 #endif
363
364 #if (RTE_MS_PPU_FAULT_STRUCT1_MAIN)
365 DEFINE_MS_PPU_FX(FAULT_STRUCT1_MAIN)
366 #endif
367
368 #if (RTE_MS_PPU_IPC_STRUCT0_IPC)
369 DEFINE_MS_PPU_FX(IPC_STRUCT0_IPC)
370 #endif
371
372 #if (RTE_MS_PPU_IPC_STRUCT1_IPC)
373 DEFINE_MS_PPU_FX(IPC_STRUCT1_IPC)
374 #endif
375
376 #if (RTE_MS_PPU_IPC_STRUCT2_IPC)
377 DEFINE_MS_PPU_FX(IPC_STRUCT2_IPC)
378 #endif
379
380 #if (RTE_MS_PPU_IPC_STRUCT3_IPC)
381 DEFINE_MS_PPU_FX(IPC_STRUCT3_IPC)
382 #endif
383
384 #if (RTE_MS_PPU_IPC_STRUCT4_IPC)
385 DEFINE_MS_PPU_FX(IPC_STRUCT4_IPC)
386 #endif
387
388 #if (RTE_MS_PPU_IPC_STRUCT5_IPC)
389 DEFINE_MS_PPU_FX(IPC_STRUCT5_IPC)
390 #endif
391
392 #if (RTE_MS_PPU_IPC_STRUCT6_IPC)
393 DEFINE_MS_PPU_FX(IPC_STRUCT6_IPC)
394 #endif
395
396 #if (RTE_MS_PPU_IPC_STRUCT7_IPC)
397 DEFINE_MS_PPU_FX(IPC_STRUCT7_IPC)
398 #endif
399
400 #if (RTE_MS_PPU_IPC_STRUCT8_IPC)
401 DEFINE_MS_PPU_FX(IPC_STRUCT8_IPC)
402 #endif
403
404 #if (RTE_MS_PPU_IPC_STRUCT9_IPC)
405 DEFINE_MS_PPU_FX(IPC_STRUCT9_IPC)
406 #endif
407
408 #if (RTE_MS_PPU_IPC_STRUCT10_IPC)
409 DEFINE_MS_PPU_FX(IPC_STRUCT10_IPC)
410 #endif
411
412 #if (RTE_MS_PPU_IPC_STRUCT11_IPC)
413 DEFINE_MS_PPU_FX(IPC_STRUCT11_IPC)
414 #endif
415
416 #if (RTE_MS_PPU_IPC_STRUCT12_IPC)
417 DEFINE_MS_PPU_FX(IPC_STRUCT12_IPC)
418 #endif
419
420 #if (RTE_MS_PPU_IPC_STRUCT13_IPC)
421 DEFINE_MS_PPU_FX(IPC_STRUCT13_IPC)
422 #endif
423
424 #if (RTE_MS_PPU_IPC_STRUCT14_IPC)
425 DEFINE_MS_PPU_FX(IPC_STRUCT14_IPC)
426 #endif
427
428 #if (RTE_MS_PPU_IPC_STRUCT15_IPC)
429 DEFINE_MS_PPU_FX(IPC_STRUCT15_IPC)
430 #endif
431
432 #if (RTE_MS_PPU_IPC_INTR_STRUCT1_INTR)
433 DEFINE_MS_PPU_FX(IPC_INTR_STRUCT1_INTR)
434 #endif
435
436 #if (RTE_MS_PPU_IPC_INTR_STRUCT2_INTR)
437 DEFINE_MS_PPU_FX(IPC_INTR_STRUCT2_INTR)
438 #endif
439
440 #if (RTE_MS_PPU_IPC_INTR_STRUCT3_INTR)
441 DEFINE_MS_PPU_FX(IPC_INTR_STRUCT3_INTR)
442 #endif
443
444 #if (RTE_MS_PPU_IPC_INTR_STRUCT4_INTR)
445 DEFINE_MS_PPU_FX(IPC_INTR_STRUCT4_INTR)
446 #endif
447
448 #if (RTE_MS_PPU_IPC_INTR_STRUCT5_INTR)
449 DEFINE_MS_PPU_FX(IPC_INTR_STRUCT5_INTR)
450 #endif
451
452 #if (RTE_MS_PPU_IPC_INTR_STRUCT6_INTR)
453 DEFINE_MS_PPU_FX(IPC_INTR_STRUCT6_INTR)
454 #endif
455
456 #if (RTE_MS_PPU_IPC_INTR_STRUCT7_INTR)
457 DEFINE_MS_PPU_FX(IPC_INTR_STRUCT7_INTR)
458 #endif
459
460 #if (RTE_MS_PPU_IPC_INTR_STRUCT8_INTR)
461 DEFINE_MS_PPU_FX(IPC_INTR_STRUCT8_INTR)
462 #endif
463
464 #if (RTE_MS_PPU_IPC_INTR_STRUCT9_INTR)
465 DEFINE_MS_PPU_FX(IPC_INTR_STRUCT9_INTR)
466 #endif
467
468 #if (RTE_MS_PPU_IPC_INTR_STRUCT10_INTR)
469 DEFINE_MS_PPU_FX(IPC_INTR_STRUCT10_INTR)
470 #endif
471
472 #if (RTE_MS_PPU_IPC_INTR_STRUCT11_INTR)
473 DEFINE_MS_PPU_FX(IPC_INTR_STRUCT11_INTR)
474 #endif
475
476 #if (RTE_MS_PPU_IPC_INTR_STRUCT12_INTR)
477 DEFINE_MS_PPU_FX(IPC_INTR_STRUCT12_INTR)
478 #endif
479
480 #if (RTE_MS_PPU_IPC_INTR_STRUCT13_INTR)
481 DEFINE_MS_PPU_FX(IPC_INTR_STRUCT13_INTR)
482 #endif
483
484 #if (RTE_MS_PPU_IPC_INTR_STRUCT14_INTR)
485 DEFINE_MS_PPU_FX(IPC_INTR_STRUCT14_INTR)
486 #endif
487
488 #if (RTE_MS_PPU_IPC_INTR_STRUCT15_INTR)
489 DEFINE_MS_PPU_FX(IPC_INTR_STRUCT15_INTR)
490 #endif
491
492 #if (RTE_MS_PPU_PROT_SMPU_MAIN)
493 DEFINE_MS_PPU_FX(PROT_SMPU_MAIN)
494 #endif
495
496 #if (RTE_MS_PPU_PROT_MPU0_MAIN)
497 DEFINE_MS_PPU_FX(PROT_MPU0_MAIN)
498 #endif
499
500 #if (RTE_MS_PPU_PROT_MPU5_MAIN)
501 DEFINE_MS_PPU_FX(PROT_MPU5_MAIN)
502 #endif
503
504 #if (RTE_MS_PPU_PROT_MPU6_MAIN)
505 DEFINE_MS_PPU_FX(PROT_MPU6_MAIN)
506 #endif
507
508 #if (RTE_MS_PPU_PROT_MPU14_MAIN)
509 DEFINE_MS_PPU_FX(PROT_MPU14_MAIN)
510 #endif
511
512 #if (RTE_MS_PPU_FLASHC_MAIN)
513 DEFINE_MS_PPU_FX(FLASHC_MAIN)
514 #endif
515
516 #if (RTE_MS_PPU_FLASHC_CMD)
517 DEFINE_MS_PPU_FX(FLASHC_CMD)
518 #endif
519
520 #if (RTE_MS_PPU_SRSS_MAIN1)
521 DEFINE_MS_PPU_FX(SRSS_MAIN1)
522 #endif
523
524 #if (RTE_MS_PPU_SRSS_MAIN2)
525 DEFINE_MS_PPU_FX(SRSS_MAIN2)
526 #endif
527
528 #if (RTE_MS_PPU_WDT)
529 DEFINE_MS_PPU_FX(WDT)
530 #endif
531
532 #if (RTE_MS_PPU_MAIN)
533 DEFINE_MS_PPU_FX(MAIN)
534 #endif
535
536 #if (RTE_MS_PPU_SRSS_MAIN3)
537 DEFINE_MS_PPU_FX(SRSS_MAIN3)
538 #endif
539
540 #if (RTE_MS_PPU_SRSS_MAIN4)
541 DEFINE_MS_PPU_FX(SRSS_MAIN4)
542 #endif
543
544 #if (RTE_MS_PPU_SRSS_MAIN5)
545 DEFINE_MS_PPU_FX(SRSS_MAIN5)
546 #endif
547
548 #if (RTE_MS_PPU_SRSS_MAIN6)
549 DEFINE_MS_PPU_FX(SRSS_MAIN6)
550 #endif
551
552 #if (RTE_MS_PPU_SRSS_MAIN7)
553 DEFINE_MS_PPU_FX(SRSS_MAIN7)
554 #endif
555
556 #if (RTE_MS_PPU_BACKUP_BACKUP)
557 DEFINE_MS_PPU_FX(BACKUP_BACKUP)
558 #endif
559
560 #if (RTE_MS_PPU_DW0_DW)
561 DEFINE_MS_PPU_FX(DW0_DW)
562 #endif
563
564 #if (RTE_MS_PPU_DW1_DW)
565 DEFINE_MS_PPU_FX(DW1_DW)
566 #endif
567
568 #if (RTE_MS_PPU_DW0_DW_CRC)
569 DEFINE_MS_PPU_FX(DW0_DW_CRC)
570 #endif
571
572 #if (RTE_MS_PPU_DW1_DW_CRC)
573 DEFINE_MS_PPU_FX(DW1_DW_CRC)
574 #endif
575
576 #if (RTE_MS_PPU_DW0_CH_STRUCT0_CH)
577 DEFINE_MS_PPU_FX(DW0_CH_STRUCT0_CH)
578 #endif
579
580 #if (RTE_MS_PPU_DW0_CH_STRUCT1_CH)
581 DEFINE_MS_PPU_FX(DW0_CH_STRUCT1_CH)
582 #endif
583
584 #if (RTE_MS_PPU_DW0_CH_STRUCT2_CH)
585 DEFINE_MS_PPU_FX(DW0_CH_STRUCT2_CH)
586 #endif
587
588 #if (RTE_MS_PPU_DW0_CH_STRUCT3_CH)
589 DEFINE_MS_PPU_FX(DW0_CH_STRUCT3_CH)
590 #endif
591
592 #if (RTE_MS_PPU_DW0_CH_STRUCT4_CH)
593 DEFINE_MS_PPU_FX(DW0_CH_STRUCT4_CH)
594 #endif
595
596 #if (RTE_MS_PPU_DW0_CH_STRUCT5_CH)
597 DEFINE_MS_PPU_FX(DW0_CH_STRUCT5_CH)
598 #endif
599
600 #if (RTE_MS_PPU_DW0_CH_STRUCT6_CH)
601 DEFINE_MS_PPU_FX(DW0_CH_STRUCT6_CH)
602 #endif
603
604 #if (RTE_MS_PPU_DW0_CH_STRUCT7_CH)
605 DEFINE_MS_PPU_FX(DW0_CH_STRUCT7_CH)
606 #endif
607
608 #if (RTE_MS_PPU_DW0_CH_STRUCT8_CH)
609 DEFINE_MS_PPU_FX(DW0_CH_STRUCT8_CH)
610 #endif
611
612 #if (RTE_MS_PPU_DW0_CH_STRUCT9_CH)
613 DEFINE_MS_PPU_FX(DW0_CH_STRUCT9_CH)
614 #endif
615
616 #if (RTE_MS_PPU_DW0_CH_STRUCT10_CH)
617 DEFINE_MS_PPU_FX(DW0_CH_STRUCT10_CH)
618 #endif
619
620 #if (RTE_MS_PPU_DW0_CH_STRUCT11_CH)
621 DEFINE_MS_PPU_FX(DW0_CH_STRUCT11_CH)
622 #endif
623
624 #if (RTE_MS_PPU_DW0_CH_STRUCT12_CH)
625 DEFINE_MS_PPU_FX(DW0_CH_STRUCT12_CH)
626 #endif
627
628 #if (RTE_MS_PPU_DW0_CH_STRUCT13_CH)
629 DEFINE_MS_PPU_FX(DW0_CH_STRUCT13_CH)
630 #endif
631
632 #if (RTE_MS_PPU_DW0_CH_STRUCT14_CH)
633 DEFINE_MS_PPU_FX(DW0_CH_STRUCT14_CH)
634 #endif
635
636 #if (RTE_MS_PPU_DW0_CH_STRUCT15_CH)
637 DEFINE_MS_PPU_FX(DW0_CH_STRUCT15_CH)
638 #endif
639
640 #if (RTE_MS_PPU_DW0_CH_STRUCT16_CH)
641 DEFINE_MS_PPU_FX(DW0_CH_STRUCT16_CH)
642 #endif
643
644 #if (RTE_MS_PPU_DW0_CH_STRUCT17_CH)
645 DEFINE_MS_PPU_FX(DW0_CH_STRUCT17_CH)
646 #endif
647
648 #if (RTE_MS_PPU_DW0_CH_STRUCT18_CH)
649 DEFINE_MS_PPU_FX(DW0_CH_STRUCT18_CH)
650 #endif
651
652 #if (RTE_MS_PPU_DW0_CH_STRUCT19_CH)
653 DEFINE_MS_PPU_FX(DW0_CH_STRUCT19_CH)
654 #endif
655
656 #if (RTE_MS_PPU_DW0_CH_STRUCT20_CH)
657 DEFINE_MS_PPU_FX(DW0_CH_STRUCT20_CH)
658 #endif
659
660 #if (RTE_MS_PPU_DW0_CH_STRUCT21_CH)
661 DEFINE_MS_PPU_FX(DW0_CH_STRUCT21_CH)
662 #endif
663
664 #if (RTE_MS_PPU_DW0_CH_STRUCT22_CH)
665 DEFINE_MS_PPU_FX(DW0_CH_STRUCT22_CH)
666 #endif
667
668 #if (RTE_MS_PPU_DW0_CH_STRUCT23_CH)
669 DEFINE_MS_PPU_FX(DW0_CH_STRUCT23_CH)
670 #endif
671
672 #if (RTE_MS_PPU_DW0_CH_STRUCT24_CH)
673 DEFINE_MS_PPU_FX(DW0_CH_STRUCT24_CH)
674 #endif
675
676 #if (RTE_MS_PPU_DW0_CH_STRUCT25_CH)
677 DEFINE_MS_PPU_FX(DW0_CH_STRUCT25_CH)
678 #endif
679
680 #if (RTE_MS_PPU_DW0_CH_STRUCT26_CH)
681 DEFINE_MS_PPU_FX(DW0_CH_STRUCT26_CH)
682 #endif
683
684 #if (RTE_MS_PPU_DW0_CH_STRUCT27_CH)
685 DEFINE_MS_PPU_FX(DW0_CH_STRUCT27_CH)
686 #endif
687
688 #if (RTE_MS_PPU_DW0_CH_STRUCT28_CH)
689 DEFINE_MS_PPU_FX(DW0_CH_STRUCT28_CH)
690 #endif
691
692 #if (RTE_MS_PPU_DW1_CH_STRUCT0_CH)
693 DEFINE_MS_PPU_FX(DW1_CH_STRUCT0_CH)
694 #endif
695
696 #if (RTE_MS_PPU_DW1_CH_STRUCT1_CH)
697 DEFINE_MS_PPU_FX(DW1_CH_STRUCT1_CH)
698 #endif
699
700 #if (RTE_MS_PPU_DW1_CH_STRUCT2_CH)
701 DEFINE_MS_PPU_FX(DW1_CH_STRUCT2_CH)
702 #endif
703
704 #if (RTE_MS_PPU_DW1_CH_STRUCT3_CH)
705 DEFINE_MS_PPU_FX(DW1_CH_STRUCT3_CH)
706 #endif
707
708 #if (RTE_MS_PPU_DW1_CH_STRUCT4_CH)
709 DEFINE_MS_PPU_FX(DW1_CH_STRUCT4_CH)
710 #endif
711
712 #if (RTE_MS_PPU_DW1_CH_STRUCT5_CH)
713 DEFINE_MS_PPU_FX(DW1_CH_STRUCT5_CH)
714 #endif
715
716 #if (RTE_MS_PPU_DW1_CH_STRUCT6_CH)
717 DEFINE_MS_PPU_FX(DW1_CH_STRUCT6_CH)
718 #endif
719
720 #if (RTE_MS_PPU_DW1_CH_STRUCT7_CH)
721 DEFINE_MS_PPU_FX(DW1_CH_STRUCT7_CH)
722 #endif
723
724 #if (RTE_MS_PPU_DW1_CH_STRUCT8_CH)
725 DEFINE_MS_PPU_FX(DW1_CH_STRUCT8_CH)
726 #endif
727
728 #if (RTE_MS_PPU_DW1_CH_STRUCT9_CH)
729 DEFINE_MS_PPU_FX(DW1_CH_STRUCT9_CH)
730 #endif
731
732 #if (RTE_MS_PPU_DW1_CH_STRUCT10_CH)
733 DEFINE_MS_PPU_FX(DW1_CH_STRUCT10_CH)
734 #endif
735
736 #if (RTE_MS_PPU_DW1_CH_STRUCT11_CH)
737 DEFINE_MS_PPU_FX(DW1_CH_STRUCT11_CH)
738 #endif
739
740 #if (RTE_MS_PPU_DW1_CH_STRUCT12_CH)
741 DEFINE_MS_PPU_FX(DW1_CH_STRUCT12_CH)
742 #endif
743
744 #if (RTE_MS_PPU_DW1_CH_STRUCT13_CH)
745 DEFINE_MS_PPU_FX(DW1_CH_STRUCT13_CH)
746 #endif
747
748 #if (RTE_MS_PPU_DW1_CH_STRUCT14_CH)
749 DEFINE_MS_PPU_FX(DW1_CH_STRUCT14_CH)
750 #endif
751
752 #if (RTE_MS_PPU_DW1_CH_STRUCT15_CH)
753 DEFINE_MS_PPU_FX(DW1_CH_STRUCT15_CH)
754 #endif
755
756 #if (RTE_MS_PPU_DW1_CH_STRUCT16_CH)
757 DEFINE_MS_PPU_FX(DW1_CH_STRUCT16_CH)
758 #endif
759
760 #if (RTE_MS_PPU_DW1_CH_STRUCT17_CH)
761 DEFINE_MS_PPU_FX(DW1_CH_STRUCT17_CH)
762 #endif
763
764 #if (RTE_MS_PPU_DW1_CH_STRUCT18_CH)
765 DEFINE_MS_PPU_FX(DW1_CH_STRUCT18_CH)
766 #endif
767
768 #if (RTE_MS_PPU_DW1_CH_STRUCT19_CH)
769 DEFINE_MS_PPU_FX(DW1_CH_STRUCT19_CH)
770 #endif
771
772 #if (RTE_MS_PPU_DW1_CH_STRUCT20_CH)
773 DEFINE_MS_PPU_FX(DW1_CH_STRUCT20_CH)
774 #endif
775
776 #if (RTE_MS_PPU_DW1_CH_STRUCT21_CH)
777 DEFINE_MS_PPU_FX(DW1_CH_STRUCT21_CH)
778 #endif
779
780 #if (RTE_MS_PPU_DW1_CH_STRUCT22_CH)
781 DEFINE_MS_PPU_FX(DW1_CH_STRUCT22_CH)
782 #endif
783
784 #if (RTE_MS_PPU_DW1_CH_STRUCT23_CH)
785 DEFINE_MS_PPU_FX(DW1_CH_STRUCT23_CH)
786 #endif
787
788 #if (RTE_MS_PPU_DW1_CH_STRUCT24_CH)
789 DEFINE_MS_PPU_FX(DW1_CH_STRUCT24_CH)
790 #endif
791
792 #if (RTE_MS_PPU_DW1_CH_STRUCT25_CH)
793 DEFINE_MS_PPU_FX(DW1_CH_STRUCT25_CH)
794 #endif
795
796 #if (RTE_MS_PPU_DW1_CH_STRUCT26_CH)
797 DEFINE_MS_PPU_FX(DW1_CH_STRUCT26_CH)
798 #endif
799
800 #if (RTE_MS_PPU_DW1_CH_STRUCT27_CH)
801 DEFINE_MS_PPU_FX(DW1_CH_STRUCT27_CH)
802 #endif
803
804 #if (RTE_MS_PPU_DW1_CH_STRUCT28_CH)
805 DEFINE_MS_PPU_FX(DW1_CH_STRUCT28_CH)
806 #endif
807
808 #if (RTE_MS_PPU_DMAC_TOP)
809 DEFINE_MS_PPU_FX(DMAC_TOP)
810 #endif
811
812 #if (RTE_MS_PPU_DMAC_CH0_CH)
813 DEFINE_MS_PPU_FX(DMAC_CH0_CH)
814 #endif
815
816 #if (RTE_MS_PPU_DMAC_CH1_CH)
817 DEFINE_MS_PPU_FX(DMAC_CH1_CH)
818 #endif
819
820 #if (RTE_MS_PPU_DMAC_CH2_CH)
821 DEFINE_MS_PPU_FX(DMAC_CH2_CH)
822 #endif
823
824 #if (RTE_MS_PPU_DMAC_CH3_CH)
825 DEFINE_MS_PPU_FX(DMAC_CH3_CH)
826 #endif
827
828 #if (RTE_MS_PPU_EFUSE_DATA)
829 DEFINE_MS_PPU_FX(EFUSE_DATA)
830 #endif
831
832 #if (RTE_MS_PPU_PROFILE)
833 DEFINE_MS_PPU_FX(PROFILE)
834 #endif
835
836 #if (RTE_MS_PPU_HSIOM_PRT0_PRT)
837 DEFINE_MS_PPU_FX(HSIOM_PRT0_PRT)
838 #endif
839
840 #if (RTE_MS_PPU_HSIOM_PRT1_PRT)
841 DEFINE_MS_PPU_FX(HSIOM_PRT1_PRT)
842 #endif
843
844 #if (RTE_MS_PPU_HSIOM_PRT2_PRT)
845 DEFINE_MS_PPU_FX(HSIOM_PRT2_PRT)
846 #endif
847
848 #if (RTE_MS_PPU_HSIOM_PRT3_PRT)
849 DEFINE_MS_PPU_FX(HSIOM_PRT3_PRT)
850 #endif
851
852 #if (RTE_MS_PPU_HSIOM_PRT4_PRT)
853 DEFINE_MS_PPU_FX(HSIOM_PRT4_PRT)
854 #endif
855
856 #if (RTE_MS_PPU_HSIOM_PRT5_PRT)
857 DEFINE_MS_PPU_FX(HSIOM_PRT5_PRT)
858 #endif
859
860 #if (RTE_MS_PPU_HSIOM_PRT6_PRT)
861 DEFINE_MS_PPU_FX(HSIOM_PRT6_PRT)
862 #endif
863
864 #if (RTE_MS_PPU_HSIOM_PRT7_PRT)
865 DEFINE_MS_PPU_FX(HSIOM_PRT7_PRT)
866 #endif
867
868 #if (RTE_MS_PPU_HSIOM_PRT8_PRT)
869 DEFINE_MS_PPU_FX(HSIOM_PRT8_PRT)
870 #endif
871
872 #if (RTE_MS_PPU_HSIOM_PRT9_PRT)
873 DEFINE_MS_PPU_FX(HSIOM_PRT9_PRT)
874 #endif
875
876 #if (RTE_MS_PPU_HSIOM_PRT10_PRT)
877 DEFINE_MS_PPU_FX(HSIOM_PRT10_PRT)
878 #endif
879
880 #if (RTE_MS_PPU_HSIOM_PRT11_PRT)
881 DEFINE_MS_PPU_FX(HSIOM_PRT11_PRT)
882 #endif
883
884 #if (RTE_MS_PPU_HSIOM_PRT12_PRT)
885 DEFINE_MS_PPU_FX(HSIOM_PRT12_PRT)
886 #endif
887
888 #if (RTE_MS_PPU_HSIOM_PRT13_PRT)
889 DEFINE_MS_PPU_FX(HSIOM_PRT13_PRT)
890 #endif
891
892 #if (RTE_MS_PPU_HSIOM_PRT14_PRT)
893 DEFINE_MS_PPU_FX(HSIOM_PRT14_PRT)
894 #endif
895
896 #if (RTE_MS_PPU_HSIOM_AMUX)
897 DEFINE_MS_PPU_FX(HSIOM_AMUX)
898 #endif
899
900 #if (RTE_MS_PPU_HSIOM_MON)
901 DEFINE_MS_PPU_FX(HSIOM_MON)
902 #endif
903
904 #if (RTE_MS_PPU_GPIO_PRT0_PRT)
905 DEFINE_MS_PPU_FX(GPIO_PRT0_PRT)
906 #endif
907
908 #if (RTE_MS_PPU_GPIO_PRT1_PRT)
909 DEFINE_MS_PPU_FX(GPIO_PRT1_PRT)
910 #endif
911
912 #if (RTE_MS_PPU_GPIO_PRT2_PRT)
913 DEFINE_MS_PPU_FX(GPIO_PRT2_PRT)
914 #endif
915
916 #if (RTE_MS_PPU_GPIO_PRT3_PRT)
917 DEFINE_MS_PPU_FX(GPIO_PRT3_PRT)
918 #endif
919
920 #if (RTE_MS_PPU_GPIO_PRT4_PRT)
921 DEFINE_MS_PPU_FX(GPIO_PRT4_PRT)
922 #endif
923
924 #if (RTE_MS_PPU_GPIO_PRT5_PRT)
925 DEFINE_MS_PPU_FX(GPIO_PRT5_PRT)
926 #endif
927
928 #if (RTE_MS_PPU_GPIO_PRT6_PRT)
929 DEFINE_MS_PPU_FX(GPIO_PRT6_PRT)
930 #endif
931
932 #if (RTE_MS_PPU_GPIO_PRT7_PRT)
933 DEFINE_MS_PPU_FX(GPIO_PRT7_PRT)
934 #endif
935
936 #if (RTE_MS_PPU_GPIO_PRT8_PRT)
937 DEFINE_MS_PPU_FX(GPIO_PRT8_PRT)
938 #endif
939
940 #if (RTE_MS_PPU_GPIO_PRT9_PRT)
941 DEFINE_MS_PPU_FX(GPIO_PRT9_PRT)
942 #endif
943
944 #if (RTE_MS_PPU_GPIO_PRT10_PRT)
945 DEFINE_MS_PPU_FX(GPIO_PRT10_PRT)
946 #endif
947
948 #if (RTE_MS_PPU_GPIO_PRT11_PRT)
949 DEFINE_MS_PPU_FX(GPIO_PRT11_PRT)
950 #endif
951
952 #if (RTE_MS_PPU_GPIO_PRT12_PRT)
953 DEFINE_MS_PPU_FX(GPIO_PRT12_PRT)
954 #endif
955
956 #if (RTE_MS_PPU_GPIO_PRT13_PRT)
957 DEFINE_MS_PPU_FX(GPIO_PRT13_PRT)
958 #endif
959
960 #if (RTE_MS_PPU_GPIO_PRT14_PRT)
961 DEFINE_MS_PPU_FX(GPIO_PRT14_PRT)
962 #endif
963
964 #if (RTE_MS_PPU_GPIO_PRT0_CFG)
965 DEFINE_MS_PPU_FX(GPIO_PRT0_CFG)
966 #endif
967
968 #if (RTE_MS_PPU_GPIO_PRT1_CFG)
969 DEFINE_MS_PPU_FX(GPIO_PRT1_CFG)
970 #endif
971
972 #if (RTE_MS_PPU_GPIO_PRT2_CFG)
973 DEFINE_MS_PPU_FX(GPIO_PRT2_CFG)
974 #endif
975
976 #if (RTE_MS_PPU_GPIO_PRT3_CFG)
977 DEFINE_MS_PPU_FX(GPIO_PRT3_CFG)
978 #endif
979
980 #if (RTE_MS_PPU_GPIO_PRT4_CFG)
981 DEFINE_MS_PPU_FX(GPIO_PRT4_CFG)
982 #endif
983
984 #if (RTE_MS_PPU_GPIO_PRT5_CFG)
985 DEFINE_MS_PPU_FX(GPIO_PRT5_CFG)
986 #endif
987
988 #if (RTE_MS_PPU_GPIO_PRT6_CFG)
989 DEFINE_MS_PPU_FX(GPIO_PRT6_CFG)
990 #endif
991
992 #if (RTE_MS_PPU_GPIO_PRT7_CFG)
993 DEFINE_MS_PPU_FX(GPIO_PRT7_CFG)
994 #endif
995
996 #if (RTE_MS_PPU_GPIO_PRT8_CFG)
997 DEFINE_MS_PPU_FX(GPIO_PRT8_CFG)
998 #endif
999
1000 #if (RTE_MS_PPU_GPIO_PRT9_CFG)
1001 DEFINE_MS_PPU_FX(GPIO_PRT9_CFG)
1002 #endif
1003
1004 #if (RTE_MS_PPU_GPIO_PRT10_CFG)
1005 DEFINE_MS_PPU_FX(GPIO_PRT10_CFG)
1006 #endif
1007
1008 #if (RTE_MS_PPU_GPIO_PRT11_CFG)
1009 DEFINE_MS_PPU_FX(GPIO_PRT11_CFG)
1010 #endif
1011
1012 #if (RTE_MS_PPU_GPIO_PRT12_CFG)
1013 DEFINE_MS_PPU_FX(GPIO_PRT12_CFG)
1014 #endif
1015
1016 #if (RTE_MS_PPU_GPIO_PRT13_CFG)
1017 DEFINE_MS_PPU_FX(GPIO_PRT13_CFG)
1018 #endif
1019
1020 #if (RTE_MS_PPU_GPIO_PRT14_CFG)
1021 DEFINE_MS_PPU_FX(GPIO_PRT14_CFG)
1022 #endif
1023
1024 #if (RTE_MS_PPU_GPIO_GPIO)
1025 DEFINE_MS_PPU_FX(GPIO_GPIO)
1026 #endif
1027
1028 #if (RTE_MS_PPU_SMARTIO_PRT8_PRT)
1029 DEFINE_MS_PPU_FX(SMARTIO_PRT8_PRT)
1030 #endif
1031
1032 #if (RTE_MS_PPU_SMARTIO_PRT9_PRT)
1033 DEFINE_MS_PPU_FX(SMARTIO_PRT9_PRT)
1034 #endif
1035
1036 #if (RTE_MS_PPU_LPCOMP)
1037 DEFINE_MS_PPU_FX(LPCOMP)
1038 #endif
1039
1040 #if (RTE_MS_PPU_CSD0)
1041 DEFINE_MS_PPU_FX(CSD0)
1042 #endif
1043
1044 #if (RTE_MS_PPU_TCPWM0)
1045 DEFINE_MS_PPU_FX(TCPWM0)
1046 #endif
1047
1048 #if (RTE_MS_PPU_TCPWM1)
1049 DEFINE_MS_PPU_FX(TCPWM1)
1050 #endif
1051
1052 #if (RTE_MS_PPU_LCD0)
1053 DEFINE_MS_PPU_FX(LCD0)
1054 #endif
1055
1056 #if (RTE_MS_PPU_USBFS0)
1057 DEFINE_MS_PPU_FX(USBFS0)
1058 #endif
1059
1060 #if (RTE_MS_PPU_SMIF0)
1061 DEFINE_MS_PPU_FX(SMIF0)
1062 #endif
1063
1064 #if (RTE_MS_PPU_SDHC0)
1065 DEFINE_MS_PPU_FX(SDHC0)
1066 #endif
1067
1068 #if (RTE_MS_PPU_SDHC1)
1069 DEFINE_MS_PPU_FX(SDHC1)
1070 #endif
1071
1072 #if (RTE_MS_PPU_SCB0)
1073 DEFINE_MS_PPU_FX(SCB0)
1074 #endif
1075
1076 #if (RTE_MS_PPU_SCB1)
1077 DEFINE_MS_PPU_FX(SCB1)
1078 #endif
1079
1080 #if (RTE_MS_PPU_SCB2)
1081 DEFINE_MS_PPU_FX(SCB2)
1082 #endif
1083
1084 #if (RTE_MS_PPU_SCB3)
1085 DEFINE_MS_PPU_FX(SCB3)
1086 #endif
1087
1088 #if (RTE_MS_PPU_SCB4)
1089 DEFINE_MS_PPU_FX(SCB4)
1090 #endif
1091
1092 #if (RTE_MS_PPU_SCB5)
1093 DEFINE_MS_PPU_FX(SCB5)
1094 #endif
1095
1096 #if (RTE_MS_PPU_SCB6)
1097 DEFINE_MS_PPU_FX(SCB6)
1098 #endif
1099
1100 #if (RTE_MS_PPU_SCB7)
1101 DEFINE_MS_PPU_FX(SCB7)
1102 #endif
1103
1104 #if (RTE_MS_PPU_SCB8)
1105 DEFINE_MS_PPU_FX(SCB8)
1106 #endif
1107
1108 #if (RTE_MS_PPU_SCB9)
1109 DEFINE_MS_PPU_FX(SCB9)
1110 #endif
1111
1112 #if (RTE_MS_PPU_SCB10)
1113 DEFINE_MS_PPU_FX(SCB10)
1114 #endif
1115
1116 #if (RTE_MS_PPU_SCB11)
1117 DEFINE_MS_PPU_FX(SCB11)
1118 #endif
1119
1120 #if (RTE_MS_PPU_SCB12)
1121 DEFINE_MS_PPU_FX(SCB12)
1122 #endif
1123
1124 #if (RTE_MS_PPU_PDM0)
1125 DEFINE_MS_PPU_FX(PDM0)
1126 #endif
1127
1128 #if (RTE_MS_PPU_I2S0)
1129 DEFINE_MS_PPU_FX(I2S0)
1130 #endif
1131
1132 #if (RTE_MS_PPU_I2S1)
1133 DEFINE_MS_PPU_FX(I2S1)
1134 #endif
1135
