1 /* 2 * Copyright (c) 2020 Linaro Limited 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 #ifndef DMA_ATMEL_SAMV71_H_ 7 #define DMA_ATMEL_SAMV71_H_ 8 9 /** Peripheral Hardware Request Line Identifier */ 10 #define DMA_PERID_HSMCI_TX_RX 0 11 #define DMA_PERID_SPI0_TX 1 12 #define DMA_PERID_SPI0_RX 2 13 #define DMA_PERID_SPI1_TX 3 14 #define DMA_PERID_SPI1_RX 4 15 #define DMA_PERID_QSPI_TX 5 16 #define DMA_PERID_QSPI_RX 6 17 #define DMA_PERID_USART0_TX 7 18 #define DMA_PERID_USART0_RX 8 19 #define DMA_PERID_USART1_TX 9 20 #define DMA_PERID_USART1_RX 10 21 #define DMA_PERID_USART2_TX 11 22 #define DMA_PERID_USART2_RX 12 23 #define DMA_PERID_PWM0_TX 13 24 #define DMA_PERID_TWIHS0_TX 14 25 #define DMA_PERID_TWIHS0_RX 15 26 #define DMA_PERID_TWIHS1_TX 16 27 #define DMA_PERID_TWIHS1_RX 17 28 #define DMA_PERID_TWIHS2_TX 18 29 #define DMA_PERID_TWIHS2_RX 19 30 #define DMA_PERID_UART0_TX 20 31 #define DMA_PERID_UART0_RX 21 32 #define DMA_PERID_UART1_TX 22 33 #define DMA_PERID_UART1_RX 23 34 #define DMA_PERID_UART2_TX 24 35 #define DMA_PERID_UART2_RX 25 36 #define DMA_PERID_UART3_TX 26 37 #define DMA_PERID_UART3_RX 27 38 #define DMA_PERID_UART4_TX 28 39 #define DMA_PERID_UART4_RX 29 40 #define DMA_PERID_DACC0_TX 30 41 #define DMA_PERID_DACC1_TX 31 42 #define DMA_PERID_SSC_TX 32 43 #define DMA_PERID_SSC_RX 33 44 #define DMA_PERID_PIOA_RX 34 45 #define DMA_PERID_AFEC0_RX 35 46 #define DMA_PERID_AFEC1_RX 36 47 #define DMA_PERID_AES_TX 37 48 #define DMA_PERID_AES_RX 38 49 #define DMA_PERID_PWM1_TX 39 50 #define DMA_PERID_TC0_RX 40 51 #define DMA_PERID_TC3_RX 41 52 #define DMA_PERID_TC6_RX 42 53 #define DMA_PERID_TC9_RX 43 54 #define DMA_PERID_I2SC0_TX_L 44 55 #define DMA_PERID_I2SC0_RX_L 45 56 #define DMA_PERID_I2SC1_TX_L 46 57 #define DMA_PERID_I2SC1_RX_L 47 58 #define DMA_PERID_I2SC0_TX_R 48 59 #define DMA_PERID_I2SC0_RX_R 49 60 #define DMA_PERID_I2SC1_TX_R 50 61 #define DMA_PERID_I2SC1_RX_R 51 62 63 #endif /* DMA_ATMEL_SAMV71_H_ */ 64
