1 /*
2 * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include "freertos/FreeRTOS.h"
8 #include "soc/periph_defs.h"
9 #include "soc/soc_memory_layout.h"
10 #include "hal/cp_dma_hal.h"
11 #include "hal/cp_dma_ll.h"
12 #include "esp_log.h"
13 #include "esp_attr.h"
14 #include "esp_err.h"
15 #include "esp_etm.h"
16 #include "esp_async_memcpy_impl.h"
17
async_memcpy_impl_default_isr_handler(void * args)18 IRAM_ATTR static void async_memcpy_impl_default_isr_handler(void *args)
19 {
20 async_memcpy_impl_t *mcp_impl = (async_memcpy_impl_t *)args;
21
22 portENTER_CRITICAL_ISR(&mcp_impl->hal_lock);
23 uint32_t status = cp_dma_hal_get_intr_status(&mcp_impl->hal);
24 cp_dma_hal_clear_intr_status(&mcp_impl->hal, status);
25 portEXIT_CRITICAL_ISR(&mcp_impl->hal_lock);
26
27 // End-Of-Frame on RX side
28 if (status & CP_DMA_LL_EVENT_RX_EOF) {
29 mcp_impl->rx_eof_addr = cp_dma_ll_get_rx_eof_descriptor_address(mcp_impl->hal.dev);
30 async_memcpy_isr_on_rx_done_event(mcp_impl);
31 }
32
33 if (mcp_impl->isr_need_yield) {
34 mcp_impl->isr_need_yield = false;
35 portYIELD_FROM_ISR();
36 }
37 }
38
async_memcpy_impl_init(async_memcpy_impl_t * impl)39 esp_err_t async_memcpy_impl_init(async_memcpy_impl_t *impl)
40 {
41 esp_err_t ret = ESP_OK;
42
43 impl->hal_lock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
44 cp_dma_hal_config_t config = {};
45 cp_dma_hal_init(&impl->hal, &config);
46
47 ret = esp_intr_alloc(ETS_DMA_COPY_INTR_SOURCE, ESP_INTR_FLAG_IRAM, async_memcpy_impl_default_isr_handler, impl, &impl->intr);
48 return ret;
49 }
50
async_memcpy_impl_deinit(async_memcpy_impl_t * impl)51 esp_err_t async_memcpy_impl_deinit(async_memcpy_impl_t *impl)
52 {
53 esp_err_t ret = ESP_OK;
54
55 cp_dma_hal_deinit(&impl->hal);
56 ret = esp_intr_free(impl->intr);
57 return ret;
58 }
59
async_memcpy_impl_start(async_memcpy_impl_t * impl,intptr_t outlink_base,intptr_t inlink_base)60 esp_err_t async_memcpy_impl_start(async_memcpy_impl_t *impl, intptr_t outlink_base, intptr_t inlink_base)
61 {
62 cp_dma_hal_set_desc_base_addr(&impl->hal, outlink_base, inlink_base);
63 cp_dma_hal_start(&impl->hal); // enable DMA and interrupt
64 return ESP_OK;
65 }
66
async_memcpy_impl_stop(async_memcpy_impl_t * impl)67 esp_err_t async_memcpy_impl_stop(async_memcpy_impl_t *impl)
68 {
69 cp_dma_hal_stop(&impl->hal); // disable DMA and interrupt
70 return ESP_OK;
71 }
72
async_memcpy_impl_restart(async_memcpy_impl_t * impl)73 esp_err_t async_memcpy_impl_restart(async_memcpy_impl_t *impl)
74 {
75 cp_dma_hal_restart_rx(&impl->hal);
76 cp_dma_hal_restart_tx(&impl->hal);
77 return ESP_OK;
78 }
79
async_memcpy_impl_new_etm_event(async_memcpy_impl_t * impl,async_memcpy_etm_event_t event_type,esp_etm_event_handle_t * out_event)80 esp_err_t async_memcpy_impl_new_etm_event(async_memcpy_impl_t *impl, async_memcpy_etm_event_t event_type, esp_etm_event_handle_t *out_event)
81 {
82 (void)impl;
83 (void)event_type;
84 (void)out_event;
85 return ESP_ERR_NOT_SUPPORTED;
86 }
87
async_memcpy_impl_is_buffer_address_valid(async_memcpy_impl_t * impl,void * src,void * dst)88 bool async_memcpy_impl_is_buffer_address_valid(async_memcpy_impl_t *impl, void *src, void *dst)
89 {
90 // CP_DMA can only access SRAM
91 return esp_ptr_internal(src) && esp_ptr_internal(dst);
92 }
93
