1 /****************************************************************************** 2 * Filename: ccfg.c 3 * Revised: $Date: 2017-11-02 11:36:28 +0100 (Thu, 02 Nov 2017) $ 4 * Revision: $Revision: 18030 $ 5 * 6 * Description: Customer Configuration for: 7 * CC13x2, CC13x4, CC26x2, CC26x4 device family (HW rev 2). 8 * 9 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ 10 * 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 16 * Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 19 * Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * Neither the name of Texas Instruments Incorporated nor the names of 24 * its contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 * 39 ******************************************************************************/ 40 41 #ifndef __CCFC_C__ 42 #define __CCFC_C__ 43 44 #include <stdint.h> 45 #include "../inc/hw_types.h" 46 #include "../inc/hw_ccfg.h" 47 #include "../inc/hw_ccfg_simple_struct.h" 48 49 /* Required for Zephyr __ti_ccfg_section macro */ 50 #include <linker/sections.h> 51 52 //***************************************************************************** 53 // 54 // Introduction 55 // 56 // This file contains fields used by Boot ROM, startup code, and SW radio 57 // stacks to configure chip behavior. 58 // 59 // Fields are documented in more details in hw_ccfg.h and CCFG.html in 60 // DriverLib documentation (doc_overview.html -> CPU Domain Memory Map -> CCFG). 61 // 62 // PLEASE NOTE: 63 // It is not recommended to do modifications inside the ccfg.c file. 64 // This file is part of the CoreSDK release and future releases may have 65 // important modifications and new fields added without notice. 66 // The recommended method to modify the CCFG settings is to have a separate 67 // <customer_ccfg>.c file that defines the specific CCFG values to be 68 // overridden and then include the TI provided ccfg.c at the very end, 69 // giving default values for non-overriden settings. 70 // 71 // Example: 72 // #define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0xC5 // Enable ROM boot loader 73 // #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x3 // LF RCOSC 74 // //---- Use default values for all others ---- 75 // #include "<project-path>/source/ti/devices/<device>/startup_files/ccfg.c" 76 // 77 //***************************************************************************** 78 79 //***************************************************************************** 80 // 81 // Internal settings, forcing several bit-fields to be set to a specific value. 82 // 83 //***************************************************************************** 84 85 //##################################### 86 // Force VDDR high setting (Higher output power but also higher power consumption) 87 // This is also called "boost mode" 88 //##################################### 89 90 #ifndef CCFG_FORCE_VDDR_HH 91 #define CCFG_FORCE_VDDR_HH 0x0 // Use default VDDR trim 92 // #define CCFG_FORCE_VDDR_HH 0x1 // Force VDDR voltage to the factory HH setting (FCFG1..VDDR_TRIM_HH) 93 #endif 94 95 //***************************************************************************** 96 // 97 // Set the values of the individual bit fields. 98 // 99 //***************************************************************************** 100 101 //##################################### 102 // Alternative DC/DC settings 103 //##################################### 104 105 #ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 106 #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x0 // Alternative DC/DC setting enabled 107 // #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x1 // Alternative DC/DC setting disabled 108 #endif 109 110 #if ( CCFG_FORCE_VDDR_HH ) 111 #define SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN 0xC // Special VMIN level (2.5V) when forced VDDR HH voltage 112 #else 113 #ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN 114 #define SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN 0x8 // 2.25V 115 #endif 116 #endif 117 118 #ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 119 #define SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x0 // Dithering disabled 120 // #define SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x1 // Dithering enabled 121 #endif 122 123 #ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK 124 #define SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK 0x0 // Peak current 125 #endif 126 127 //##################################### 128 // XOSC override settings 129 //##################################### 130 131 #ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 132 // #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x0 // Enable override 133 #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x1 // Disable override 134 #endif 135 136 #ifndef SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT 137 #define SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT 0x0 // Delta = 0 138 #endif 139 140 #ifndef SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET 141 #define SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET 0x0 // Delta = 0 142 #endif 143 144 #ifndef SET_CCFG_MODE_CONF_1_XOSC_MAX_START 145 #define SET_CCFG_MODE_CONF_1_XOSC_MAX_START 0x10 // 1600us 146 #endif 147 148 //##################################### 149 // Power settings 150 //##################################### 151 152 #ifndef SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA 153 #define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA 0xF // Signed delta value +1 to apply to the VDDR_TRIM_SLEEP target (0xF=-1=default=no compensation) 154 #endif 155 156 #ifndef SET_CCFG_MODE_CONF_DCDC_RECHARGE 157 #define SET_CCFG_MODE_CONF_DCDC_RECHARGE 0x0 // Use the DC/DC during recharge in powerdown 158 // #define SET_CCFG_MODE_CONF_DCDC_RECHARGE 0x1 // Do not use the DC/DC during recharge in powerdown 159 #endif 160 161 #ifndef SET_CCFG_MODE_CONF_DCDC_ACTIVE 162 #define SET_CCFG_MODE_CONF_DCDC_ACTIVE 0x0 // Use the DC/DC during active mode 163 // #define SET_CCFG_MODE_CONF_DCDC_ACTIVE 0x1 // Do not use the DC/DC during active mode 164 #endif 165 166 #if ( CCFG_FORCE_VDDR_HH ) 167 #define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x1 // Special setting to enable forced VDDR HH voltage 168 #else 169 #ifndef SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 170 // #define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x0 // VDDS BOD level is 2.0V 171 #define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x1 // VDDS BOD level is 1.8V (or 1.65V for external regulator mode) 172 #endif 173 #endif 174 175 #ifndef SET_CCFG_MODE_CONF_VDDR_CAP 176 #define SET_CCFG_MODE_CONF_VDDR_CAP 0x3A // Unsigned 8-bit integer representing the min. decoupling capacitance on VDDR in units of 100nF 177 #endif 178 179 #ifndef SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 180 #define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x1 // Temperature compensation on VDDR sleep trim disabled (default) 181 // #define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x0 // Temperature compensation on VDDR sleep trim enabled 182 #endif 183 184 //##################################### 185 // Clock settings 186 //##################################### 187 188 #ifndef SET_CCFG_MODE_CONF_SCLK_LF_OPTION 189 // #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x0 // LF clock derived from HF clock. Note: using this configuration will block the device from entering Standby mode. 190 // #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x1 // External LF clock 191 #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x2 // LF XOSC 192 // #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x3 // LF RCOSC 193 #endif 194 195 #ifndef SET_CCFG_MODE_CONF_XOSC_CAP_MOD 196 // #define SET_CCFG_MODE_CONF_XOSC_CAP_MOD 0x0 // Apply cap-array delta 197 #define SET_CCFG_MODE_CONF_XOSC_CAP_MOD 0x1 // Don't apply cap-array delta 198 #endif 199 200 #ifndef SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA 201 #define SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA 0xFF // Signed 8-bit value, directly modifying trimmed XOSC cap-array value 202 #endif 203 204 #ifndef SET_CCFG_EXT_LF_CLK_DIO 205 #define SET_CCFG_EXT_LF_CLK_DIO 0x01 // DIO number if using external LF clock 206 #endif 207 208 #ifndef SET_CCFG_EXT_LF_CLK_RTC_INCREMENT 209 #define SET_CCFG_EXT_LF_CLK_RTC_INCREMENT 0x800000 // RTC increment representing the external LF clock frequency 210 #endif 211 212 //##################################### 213 // Special HF clock source setting 214 //##################################### 215 #ifndef SET_CCFG_MODE_CONF_XOSC_FREQ 216 // #define SET_CCFG_MODE_CONF_XOSC_FREQ 0x0 // HF source is 48 MHz TCXO 217 // #define SET_CCFG_MODE_CONF_XOSC_FREQ 0x1 // HF source is HPOSC (BAW) (only valid for CC2652RB) 218 #define SET_CCFG_MODE_CONF_XOSC_FREQ 0x2 // HF source is a 48 MHz xtal 219 // #define SET_CCFG_MODE_CONF_XOSC_FREQ 0x3 // HF source is a 24 MHz xtal (not supported) 220 #endif 221 222 //##################################### 223 // Bootloader settings 224 //##################################### 225 226 #ifndef SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 227 #define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0x00 // Disable ROM boot loader 228 // #define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0xC5 // Enable ROM boot loader 229 #endif 230 231 #ifndef SET_CCFG_BL_CONFIG_BL_LEVEL 232 // #define SET_CCFG_BL_CONFIG_BL_LEVEL 0x0 // Active low to open boot loader backdoor 233 #define SET_CCFG_BL_CONFIG_BL_LEVEL 0x1 // Active high to open boot loader backdoor 234 #endif 235 236 #ifndef SET_CCFG_BL_CONFIG_BL_PIN_NUMBER 237 #define SET_CCFG_BL_CONFIG_BL_PIN_NUMBER 0xFF // DIO number for boot loader backdoor 238 #endif 239 240 #ifndef SET_CCFG_BL_CONFIG_BL_ENABLE 241 // #define SET_CCFG_BL_CONFIG_BL_ENABLE 0xC5 // Enabled boot loader backdoor 242 #define SET_CCFG_BL_CONFIG_BL_ENABLE 0xFF // Disabled boot loader backdoor 243 #endif 244 245 //##################################### 246 // Debug access settings 247 //##################################### 248 249 #ifndef SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE 250 #define SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE 0x00 // Disable unlocking of TI FA option. 251 // #define SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE 0xC5 // Enable unlocking of TI FA option with the unlock code 252 #endif 253 254 #ifndef SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 255 // #define SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0x00 // Access disabled 256 #define SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG 257 #endif 258 259 #ifndef SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE 260 //#define SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE 0x00 // Access disabled 261 #define SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG 262 #endif 263 264 #ifndef SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 265 #define SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0x00 // Access disabled 266 //#define SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG 267 #endif 268 269 #ifndef SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE 270 #define SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE 0x00 // Access disabled 271 // #define SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG 272 #endif 273 274 #ifndef SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE 275 #define SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE 0x00 // Access disabled 276 // #define SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG 277 #endif 278 279 #ifndef SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE 280 #define SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE 0x00 // Access disabled 281 // #define SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG 282 #endif 283 284 //##################################### 285 // Alternative IEEE 802.15.4 MAC address 286 //##################################### 287 #ifndef SET_CCFG_IEEE_MAC_0 288 #define SET_CCFG_IEEE_MAC_0 0xFFFFFFFF // Bits [31:0] 289 #endif 290 291 #ifndef SET_CCFG_IEEE_MAC_1 292 #define SET_CCFG_IEEE_MAC_1 0xFFFFFFFF // Bits [63:32] 293 #endif 294 295 //##################################### 296 // Alternative BLE address 297 //##################################### 298 #ifndef SET_CCFG_IEEE_BLE_0 299 #define SET_CCFG_IEEE_BLE_0 0xFFFFFFFF // Bits [31:0] 300 #endif 301 302 #ifndef SET_CCFG_IEEE_BLE_1 303 #define SET_CCFG_IEEE_BLE_1 0xFFFFFFFF // Bits [63:32] 304 #endif 305 306 //##################################### 307 // Flash erase settings 308 //##################################### 309 310 #ifndef SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 311 // #define SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x0 // Any chip erase request detected during boot will be ignored 312 #define SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x1 // Any chip erase request detected during boot will be performed by the boot FW 313 #endif 314 315 #ifndef SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N 316 // #define SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x0 // Disable the boot loader bank erase function 317 #define SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x1 // Enable the boot loader bank erase function 318 #endif 319 320 //##################################### 321 // Flash image valid 322 //##################################### 323 #ifndef SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID 324 #define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID 0x00000000 // Flash image vector table is at address 0x00000000 (default) 325 // #define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID <valid_vector_table_addr> // Flash image vector table is at address <valid_vector_table_addr> 326 // #define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID <invalid_vector_table_addr> // Flash image vector table address is invalid. ROM boot loader is called. 327 #endif 328 329 //##################################### 330 // Flash sector write protection 331 //##################################### 332 #ifndef SET_CCFG_CCFG_PROT_31_0 333 #define SET_CCFG_CCFG_PROT_31_0 0xFFFFFFFF 334 #endif 335 336 #ifndef SET_CCFG_CCFG_PROT_63_32 337 #define SET_CCFG_CCFG_PROT_63_32 0xFFFFFFFF 338 #endif 339 340 #ifndef SET_CCFG_CCFG_PROT_95_64 341 #define SET_CCFG_CCFG_PROT_95_64 0xFFFFFFFF 342 #endif 343 344 #ifndef SET_CCFG_CCFG_PROT_127_96 345 #define SET_CCFG_CCFG_PROT_127_96 0xFFFFFFFF 346 #endif 347 348 //##################################### 349 // Select between cache or GPRAM 350 //##################################### 351 #ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 352 // #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x0 // Cache is disabled and GPRAM is available at 0x11000000-0x11001FFF 353 #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x1 // Cache is enabled and GPRAM is disabled (unavailable) 354 #endif 355 356 //##################################### 357 // TCXO settings 358 //##################################### 359 #ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 360 #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x1 // Deprecated. Must be set to 0x1. 361 #endif 362 363 #ifndef SET_CCFG_MODE_CONF_1_TCXO_TYPE 364 #define SET_CCFG_MODE_CONF_1_TCXO_TYPE 0x1 // 1 = Clipped-sine type. 365 //#define SET_CCFG_MODE_CONF_1_TCXO_TYPE 0x0 // 0 = CMOS type. 366 #endif 367 368 #ifndef SET_CCFG_MODE_CONF_1_TCXO_MAX_START 369 #define SET_CCFG_MODE_CONF_1_TCXO_MAX_START 0x7F // Maximum TCXO startup time in units of 100us. 370 #endif 371 372 //***************************************************************************** 373 // 374 // CCFG values that should not be modified. 375 // 376 //***************************************************************************** 377 #define SET_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG 0x0058 378 #define SET_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS (CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M >> CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S) 379 380 #if ( CCFG_FORCE_VDDR_HH ) 381 #define SET_CCFG_MODE_CONF_VDDR_EXT_LOAD 0x0 // Special setting to enable forced VDDR HH voltage 382 #else 383 #define SET_CCFG_MODE_CONF_VDDR_EXT_LOAD 0x1 384 #endif 385 386 #define SET_CCFG_MODE_CONF_RTC_COMP 0x1 387 #define SET_CCFG_MODE_CONF_HF_COMP 0x1 388 389 #define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45 0xFF 390 #define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25 0xFF 391 #define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5 0xFF 392 #define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15 0xFF 393 394 #define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125 0xFF 395 #define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105 0xFF 396 #define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85 0xFF 397 #define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65 0xFF 398 399 #define SET_CCFG_RTC_OFFSET_RTC_COMP_P0 0xFFFF 400 #define SET_CCFG_RTC_OFFSET_RTC_COMP_P1 0xFF 401 #define SET_CCFG_RTC_OFFSET_RTC_COMP_P2 0xFF 402 403 #define SET_CCFG_FREQ_OFFSET_HF_COMP_P0 0xFFFF 404 #define SET_CCFG_FREQ_OFFSET_HF_COMP_P1 0xFF 405 #define SET_CCFG_FREQ_OFFSET_HF_COMP_P2 0xFF 406 407 //***************************************************************************** 408 // 409 // Concatenate bit fields to words. 410 // DO NOT EDIT! 411 // 412 //***************************************************************************** 413 #define DEFAULT_CCFG_EXT_LF_CLK ( \ 414 ((((uint32_t)( SET_CCFG_EXT_LF_CLK_DIO )) << CCFG_EXT_LF_CLK_DIO_S ) | ~CCFG_EXT_LF_CLK_DIO_M ) & \ 415 ((((uint32_t)( SET_CCFG_EXT_LF_CLK_RTC_INCREMENT )) << CCFG_EXT_LF_CLK_RTC_INCREMENT_S ) | ~CCFG_EXT_LF_CLK_RTC_INCREMENT_M ) ) 416 417 #define DEFAULT_CCFG_MODE_CONF_1 ( \ 418 ((((uint32_t)( SET_CCFG_MODE_CONF_1_TCXO_TYPE )) << CCFG_MODE_CONF_1_TCXO_TYPE_S ) | ~CCFG_MODE_CONF_1_TCXO_TYPE_M ) & \ 419 ((((uint32_t)( SET_CCFG_MODE_CONF_1_TCXO_MAX_START )) << CCFG_MODE_CONF_1_TCXO_MAX_START_S ) | ~CCFG_MODE_CONF_1_TCXO_MAX_START_M ) & \ 420 ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN )) << CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M ) & \ 421 ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN )) << CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_M ) & \ 422 ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK )) << CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_M ) & \ 423 ((((uint32_t)( SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT )) << CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S ) | ~CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_M ) & \ 424 ((((uint32_t)( SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET )) << CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S ) | ~CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_M ) & \ 425 ((((uint32_t)( SET_CCFG_MODE_CONF_1_XOSC_MAX_START )) << CCFG_MODE_CONF_1_XOSC_MAX_START_S ) | ~CCFG_MODE_CONF_1_XOSC_MAX_START_M ) ) 426 427 #define DEFAULT_CCFG_SIZE_AND_DIS_FLAGS ( \ 428 ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG )) << CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_M ) & \ 429 ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS )) << CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M ) & \ 430 ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_M ) & \ 431 ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M ) & \ 432 ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_M ) & \ 433 ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) ) 434 435 #define DEFAULT_CCFG_MODE_CONF ( \ 436 ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA )) << CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S ) | ~CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_M ) & \ 437 ((((uint32_t)( SET_CCFG_MODE_CONF_DCDC_RECHARGE )) << CCFG_MODE_CONF_DCDC_RECHARGE_S ) | ~CCFG_MODE_CONF_DCDC_RECHARGE_M ) & \ 438 ((((uint32_t)( SET_CCFG_MODE_CONF_DCDC_ACTIVE )) << CCFG_MODE_CONF_DCDC_ACTIVE_S ) | ~CCFG_MODE_CONF_DCDC_ACTIVE_M ) & \ 439 ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_EXT_LOAD )) << CCFG_MODE_CONF_VDDR_EXT_LOAD_S ) | ~CCFG_MODE_CONF_VDDR_EXT_LOAD_M ) & \ 440 ((((uint32_t)( SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL )) << CCFG_MODE_CONF_VDDS_BOD_LEVEL_S ) | ~CCFG_MODE_CONF_VDDS_BOD_LEVEL_M ) & \ 441 ((((uint32_t)( SET_CCFG_MODE_CONF_SCLK_LF_OPTION )) << CCFG_MODE_CONF_SCLK_LF_OPTION_S ) | ~CCFG_MODE_CONF_SCLK_LF_OPTION_M ) & \ 442 ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC )) << CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_S ) | ~CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_M ) & \ 443 ((((uint32_t)( SET_CCFG_MODE_CONF_RTC_COMP )) << CCFG_MODE_CONF_RTC_COMP_S ) | ~CCFG_MODE_CONF_RTC_COMP_M ) & \ 444 ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_FREQ )) << CCFG_MODE_CONF_XOSC_FREQ_S ) | ~CCFG_MODE_CONF_XOSC_FREQ_M ) & \ 445 ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_CAP_MOD )) << CCFG_MODE_CONF_XOSC_CAP_MOD_S ) | ~CCFG_MODE_CONF_XOSC_CAP_MOD_M ) & \ 446 ((((uint32_t)( SET_CCFG_MODE_CONF_HF_COMP )) << CCFG_MODE_CONF_HF_COMP_S ) | ~CCFG_MODE_CONF_HF_COMP_M ) & \ 447 ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA )) << CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S ) | ~CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M ) & \ 448 ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_CAP )) << CCFG_MODE_CONF_VDDR_CAP_S ) | ~CCFG_MODE_CONF_VDDR_CAP_M ) ) 449 450 #define DEFAULT_CCFG_VOLT_LOAD_0 ( \ 451 ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_M ) & \ 452 ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_M ) & \ 453 ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_M ) & \ 454 ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_M ) ) 455 456 #define DEFAULT_CCFG_VOLT_LOAD_1 ( \ 457 ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_M ) & \ 458 ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_M ) & \ 459 ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_M ) & \ 460 ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_M ) ) 461 462 #define DEFAULT_CCFG_RTC_OFFSET ( \ 463 ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P0 )) << CCFG_RTC_OFFSET_RTC_COMP_P0_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P0_M ) & \ 464 ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P1 )) << CCFG_RTC_OFFSET_RTC_COMP_P1_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P1_M ) & \ 465 ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P2 )) << CCFG_RTC_OFFSET_RTC_COMP_P2_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P2_M ) ) 466 467 #define DEFAULT_CCFG_FREQ_OFFSET ( \ 468 ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P0 )) << CCFG_FREQ_OFFSET_HF_COMP_P0_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P0_M ) & \ 469 ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P1 )) << CCFG_FREQ_OFFSET_HF_COMP_P1_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P1_M ) & \ 470 ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P2 )) << CCFG_FREQ_OFFSET_HF_COMP_P2_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P2_M ) ) 471 472 #define DEFAULT_CCFG_IEEE_MAC_0 SET_CCFG_IEEE_MAC_0 473 #define DEFAULT_CCFG_IEEE_MAC_1 SET_CCFG_IEEE_MAC_1 474 #define DEFAULT_CCFG_IEEE_BLE_0 SET_CCFG_IEEE_BLE_0 475 #define DEFAULT_CCFG_IEEE_BLE_1 SET_CCFG_IEEE_BLE_1 476 477 #define DEFAULT_CCFG_BL_CONFIG ( \ 478 ((((uint32_t)( SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE )) << CCFG_BL_CONFIG_BOOTLOADER_ENABLE_S ) | ~CCFG_BL_CONFIG_BOOTLOADER_ENABLE_M ) & \ 479 ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_LEVEL )) << CCFG_BL_CONFIG_BL_LEVEL_S ) | ~CCFG_BL_CONFIG_BL_LEVEL_M ) & \ 480 ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_PIN_NUMBER )) << CCFG_BL_CONFIG_BL_PIN_NUMBER_S ) | ~CCFG_BL_CONFIG_BL_PIN_NUMBER_M ) & \ 481 ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_ENABLE )) << CCFG_BL_CONFIG_BL_ENABLE_S ) | ~CCFG_BL_CONFIG_BL_ENABLE_M ) ) 482 483 #define DEFAULT_CCFG_ERASE_CONF ( \ 484 ((((uint32_t)( SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N )) << CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_S ) | ~CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_M ) & \ 485 ((((uint32_t)( SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N )) << CCFG_ERASE_CONF_BANK_ERASE_DIS_N_S ) | ~CCFG_ERASE_CONF_BANK_ERASE_DIS_N_M ) ) 486 487 #define DEFAULT_CCFG_CCFG_TI_OPTIONS ( \ 488 ((((uint32_t)( SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE )) << CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_S ) | ~CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_M ) ) 489 490 #define DEFAULT_CCFG_CCFG_TAP_DAP_0 ( \ 491 ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_M ) & \ 492 ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_M ) & \ 493 ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_M ) ) 494 495 #define DEFAULT_CCFG_CCFG_TAP_DAP_1 ( \ 496 ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_M ) & \ 497 ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_M ) & \ 498 ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_M ) ) 499 500 #define DEFAULT_CCFG_IMAGE_VALID_CONF SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID 501 502 #define DEFAULT_CCFG_CCFG_PROT_31_0 SET_CCFG_CCFG_PROT_31_0 503 #define DEFAULT_CCFG_CCFG_PROT_63_32 SET_CCFG_CCFG_PROT_63_32 504 #define DEFAULT_CCFG_CCFG_PROT_95_64 SET_CCFG_CCFG_PROT_95_64 505 #define DEFAULT_CCFG_CCFG_PROT_127_96 SET_CCFG_CCFG_PROT_127_96 506 507 //***************************************************************************** 508 // 509 // Customer Configuration Area in Lock Page 510 // 511 //***************************************************************************** 512 #if defined(__IAR_SYSTEMS_ICC__) 513 __root const ccfg_t __ccfg @ ".ccfg" = 514 #elif defined(__TI_COMPILER_VERSION__) 515 #pragma DATA_SECTION(__ccfg, ".ccfg") 516 #pragma RETAIN(__ccfg) 517 const ccfg_t __ccfg = 518 #else 519 /* Modified for Zephyr to use __ti_ccfg_section */ 520 const ccfg_t __ti_ccfg_section __ccfg = 521 #endif 522 { // Mapped to address 523 DEFAULT_CCFG_EXT_LF_CLK , // 0x50003FA8 (0x50003xxx maps to last 524 DEFAULT_CCFG_MODE_CONF_1 , // 0x50003FAC sector in FLASH. 525 DEFAULT_CCFG_SIZE_AND_DIS_FLAGS , // 0x50003FB0 Independent of FLASH size) 526 DEFAULT_CCFG_MODE_CONF , // 0x50003FB4 527 DEFAULT_CCFG_VOLT_LOAD_0 , // 0x50003FB8 528 DEFAULT_CCFG_VOLT_LOAD_1 , // 0x50003FBC 529 DEFAULT_CCFG_RTC_OFFSET , // 0x50003FC0 530 DEFAULT_CCFG_FREQ_OFFSET , // 0x50003FC4 531 DEFAULT_CCFG_IEEE_MAC_0 , // 0x50003FC8 532 DEFAULT_CCFG_IEEE_MAC_1 , // 0x50003FCC 533 DEFAULT_CCFG_IEEE_BLE_0 , // 0x50003FD0 534 DEFAULT_CCFG_IEEE_BLE_1 , // 0x50003FD4 535 DEFAULT_CCFG_BL_CONFIG , // 0x50003FD8 536 DEFAULT_CCFG_ERASE_CONF , // 0x50003FDC 537 DEFAULT_CCFG_CCFG_TI_OPTIONS , // 0x50003FE0 538 DEFAULT_CCFG_CCFG_TAP_DAP_0 , // 0x50003FE4 539 DEFAULT_CCFG_CCFG_TAP_DAP_1 , // 0x50003FE8 540 DEFAULT_CCFG_IMAGE_VALID_CONF , // 0x50003FEC 541 DEFAULT_CCFG_CCFG_PROT_31_0 , // 0x50003FF0 542 DEFAULT_CCFG_CCFG_PROT_63_32 , // 0x50003FF4 543 DEFAULT_CCFG_CCFG_PROT_95_64 , // 0x50003FF8 544 DEFAULT_CCFG_CCFG_PROT_127_96 , // 0x50003FFC 545 }; 546 547 #endif // __CCFC_C__ 548
