1 /****************************************************************************** 2 * Filename: ccfg.c 3 * Revised: $Date: 2017-11-02 11:36:28 +0100 (Thu, 02 Nov 2017) $ 4 * Revision: $Revision: 18030 $ 5 * 6 * Description: Customer Configuration for: 7 * CC13x2, CC13x4, CC26x2, CC26x4 device family (HW rev 2). 8 * 9 * Copyright (C) 2018 - 2020, Texas Instruments Incorporated - http://www.ti.com/ 10 * 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 16 * Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 19 * Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * Neither the name of Texas Instruments Incorporated nor the names of 24 * its contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 * 39 ******************************************************************************/ 40 41 #ifndef __CCFC_C__ 42 #define __CCFC_C__ 43 44 #include <stdint.h> 45 #include "../inc/hw_types.h" 46 #include "../inc/hw_ccfg.h" 47 #include "../inc/hw_ccfg_simple_struct.h" 48 49 /* Required for Zephyr __ti_ccfg_section macro */ 50 #include <zephyr/linker/sections.h> 51 52 //***************************************************************************** 53 // 54 // Introduction 55 // 56 // This file contains fields used by Boot ROM, startup code, and SW radio 57 // stacks to configure chip behavior. 58 // 59 // Fields are documented in more details in hw_ccfg.h and CCFG.html in 60 // DriverLib documentation (doc_overview.html -> CPU Domain Memory Map -> CCFG). 61 // 62 // PLEASE NOTE: 63 // It is not recommended to do modifications inside the ccfg.c file. 64 // This file is part of the CoreSDK release and future releases may have 65 // important modifications and new fields added without notice. 66 // The recommended method to modify the CCFG settings is to have a separate 67 // <customer_ccfg>.c file that defines the specific CCFG values to be 68 // overridden and then include the TI provided ccfg.c at the very end, 69 // giving default values for non-overriden settings. 70 // 71 // Example: 72 // #define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0xC5 // Enable ROM boot loader 73 // #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x3 // LF RCOSC 74 // //---- Use default values for all others ---- 75 // #include "<project-path>/source/ti/devices/<device>/startup_files/ccfg.c" 76 // 77 //***************************************************************************** 78 79 //***************************************************************************** 80 // 81 // Internal settings, forcing several bit-fields to be set to a specific value. 82 // 83 //***************************************************************************** 84 85 //##################################### 86 // Force VDDR high setting (Higher output power but also higher power consumption) 87 // This is also called "boost mode" 88 // WARNING: CCFG_FORCE_VDDR_HH must not be set to 1 if running in external regulator mode. 89 //##################################### 90 91 #ifndef CCFG_FORCE_VDDR_HH 92 #define CCFG_FORCE_VDDR_HH 0x0 // Use default VDDR trim 93 // #define CCFG_FORCE_VDDR_HH 0x1 // Force VDDR voltage to the factory HH setting (FCFG1..VDDR_TRIM_HH) 94 #endif 95 96 //***************************************************************************** 97 // 98 // Set the values of the individual bit fields. 99 // 100 //***************************************************************************** 101 102 //##################################### 103 // Alternative DC/DC settings 104 //##################################### 105 106 #ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 107 #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x0 // Alternative DC/DC setting enabled 108 // #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x1 // Alternative DC/DC setting disabled 109 #endif 110 111 #if ( CCFG_FORCE_VDDR_HH ) 112 #define SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN 0xC // Special VMIN level (2.5V) when forced VDDR HH voltage 113 #else 114 #ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN 115 #define SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN 0x8 // 2.25V 116 #endif 117 #endif 118 119 #ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 120 #define SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x0 // Dithering disabled 121 // #define SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x1 // Dithering enabled 122 #endif 123 124 #ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK 125 #define SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK 0x0 // Peak current 126 #endif 127 128 //##################################### 129 // XOSC override settings 130 //##################################### 131 132 #ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 133 // #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x0 // Enable override 134 #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x1 // Disable override 135 #endif 136 137 #ifndef SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT 138 #define SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT 0x0 // Delta = 0 139 #endif 140 141 #ifndef SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET 142 #define SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET 0x0 // Delta = 0 143 #endif 144 145 #ifndef SET_CCFG_MODE_CONF_1_XOSC_MAX_START 146 #define SET_CCFG_MODE_CONF_1_XOSC_MAX_START 0x10 // 1600us 147 #endif 148 149 //##################################### 150 // Power settings 151 //##################################### 152 153 #ifndef SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA 154 #define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA 0xF // Signed delta value +1 to apply to the VDDR_TRIM_SLEEP target (0xF=-1=default=no compensation) 155 #endif 156 157 #ifndef SET_CCFG_MODE_CONF_DCDC_RECHARGE 158 #define SET_CCFG_MODE_CONF_DCDC_RECHARGE 0x0 // Use the DC/DC during recharge in powerdown 159 // #define SET_CCFG_MODE_CONF_DCDC_RECHARGE 0x1 // Do not use the DC/DC during recharge in powerdown 160 #endif 161 162 #ifndef SET_CCFG_MODE_CONF_DCDC_ACTIVE 163 #define SET_CCFG_MODE_CONF_DCDC_ACTIVE 0x0 // Use the DC/DC during active mode 164 // #define SET_CCFG_MODE_CONF_DCDC_ACTIVE 0x1 // Do not use the DC/DC during active mode 165 #endif 166 167 #if ( CCFG_FORCE_VDDR_HH ) 168 #define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x1 // Special setting to enable forced VDDR HH voltage 169 #else 170 #ifndef SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 171 // #define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x0 // VDDS BOD level is 2.0V 172 #define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x1 // VDDS BOD level is 1.8V (or 1.65V for external regulator mode) 173 #endif 174 #endif 175 176 #ifndef SET_CCFG_MODE_CONF_VDDR_CAP 177 #define SET_CCFG_MODE_CONF_VDDR_CAP 0x3A // Unsigned 8-bit integer representing the min. decoupling capacitance on VDDR in units of 100nF 178 #endif 179 180 #ifndef SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 181 #define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x1 // Temperature compensation on VDDR sleep trim disabled (default) 182 // #define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x0 // Temperature compensation on VDDR sleep trim enabled 183 #endif 184 185 //##################################### 186 // Clock settings 187 //##################################### 188 189 #ifndef SET_CCFG_MODE_CONF_SCLK_LF_OPTION 190 // #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x0 // LF clock derived from HF clock. Note: using this configuration will block the device from entering Standby mode. 191 // #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x1 // External LF clock 192 #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x2 // LF XOSC 193 // #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x3 // LF RCOSC 194 #endif 195 196 #ifndef SET_CCFG_MODE_CONF_XOSC_CAP_MOD 197 // #define SET_CCFG_MODE_CONF_XOSC_CAP_MOD 0x0 // Apply cap-array delta 198 #define SET_CCFG_MODE_CONF_XOSC_CAP_MOD 0x1 // Don't apply cap-array delta 199 #endif 200 201 #ifndef SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA 202 #define SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA 0xFF // Signed 8-bit value, directly modifying trimmed XOSC cap-array value 203 #endif 204 205 #ifndef SET_CCFG_EXT_LF_CLK_DIO 206 #define SET_CCFG_EXT_LF_CLK_DIO 0x01 // DIO number if using external LF clock 207 #endif 208 209 #ifndef SET_CCFG_EXT_LF_CLK_RTC_INCREMENT 210 #define SET_CCFG_EXT_LF_CLK_RTC_INCREMENT 0x800000 // RTC increment representing the external LF clock frequency 211 #endif 212 213 //##################################### 214 // Special HF clock source setting 215 //##################################### 216 #ifndef SET_CCFG_MODE_CONF_XOSC_FREQ 217 // #define SET_CCFG_MODE_CONF_XOSC_FREQ 0x0 // HF source is 48 MHz TCXO 218 // #define SET_CCFG_MODE_CONF_XOSC_FREQ 0x1 // HF source is HPOSC (BAW) (only valid for CC2652RB) 219 #define SET_CCFG_MODE_CONF_XOSC_FREQ 0x2 // HF source is a 48 MHz xtal 220 // #define SET_CCFG_MODE_CONF_XOSC_FREQ 0x3 // HF source is a 24 MHz xtal (not supported) 221 #endif 222 223 //##################################### 224 // Bootloader settings 225 //##################################### 226 227 #ifndef SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 228 #define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0x00 // Disable ROM boot loader 229 // #define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0xC5 // Enable ROM boot loader 230 #endif 231 232 #ifndef SET_CCFG_BL_CONFIG_BL_LEVEL 233 // #define SET_CCFG_BL_CONFIG_BL_LEVEL 0x0 // Active low to open boot loader backdoor 234 #define SET_CCFG_BL_CONFIG_BL_LEVEL 0x1 // Active high to open boot loader backdoor 235 #endif 236 237 #ifndef SET_CCFG_BL_CONFIG_BL_PIN_NUMBER 238 #define SET_CCFG_BL_CONFIG_BL_PIN_NUMBER 0xFF // DIO number for boot loader backdoor 239 #endif 240 241 #ifndef SET_CCFG_BL_CONFIG_BL_ENABLE 242 // #define SET_CCFG_BL_CONFIG_BL_ENABLE 0xC5 // Enabled boot loader backdoor 243 #define SET_CCFG_BL_CONFIG_BL_ENABLE 0xFF // Disabled boot loader backdoor 244 #endif 245 246 //##################################### 247 // Debug access settings 248 //##################################### 249 250 #ifndef SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE 251 #define SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE 0x00 // Disable unlocking of TI FA option. 252 // #define SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE 0xC5 // Enable unlocking of TI FA option with the unlock code 253 #endif 254 255 #ifndef SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 256 // #define SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0x00 // Access disabled 257 #define SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG 258 #endif 259 260 #ifndef SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE 261 //#define SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE 0x00 // Access disabled 262 #define SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG 263 #endif 264 265 #ifndef SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 266 #define SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0x00 // Access disabled 267 //#define SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG 268 #endif 269 270 #ifndef SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE 271 #define SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE 0x00 // Access disabled 272 // #define SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG 273 #endif 274 275 #ifndef SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE 276 #define SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE 0x00 // Access disabled 277 // #define SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG 278 #endif 279 280 #ifndef SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE 281 #define SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE 0x00 // Access disabled 282 // #define SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG 283 #endif 284 285 //##################################### 286 // Alternative IEEE 802.15.4 MAC address 287 //##################################### 288 #ifndef SET_CCFG_IEEE_MAC_0 289 #define SET_CCFG_IEEE_MAC_0 0xFFFFFFFF // Bits [31:0] 290 #endif 291 292 #ifndef SET_CCFG_IEEE_MAC_1 293 #define SET_CCFG_IEEE_MAC_1 0xFFFFFFFF // Bits [63:32] 294 #endif 295 296 //##################################### 297 // Alternative BLE address 298 //##################################### 299 #ifndef SET_CCFG_IEEE_BLE_0 300 #define SET_CCFG_IEEE_BLE_0 0xFFFFFFFF // Bits [31:0] 301 #endif 302 303 #ifndef SET_CCFG_IEEE_BLE_1 304 #define SET_CCFG_IEEE_BLE_1 0xFFFFFFFF // Bits [63:32] 305 #endif 306 307 //##################################### 308 // Flash erase settings 309 //##################################### 310 311 #ifndef SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 312 // #define SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x0 // Any chip erase request detected during boot will be ignored 313 #define SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x1 // Any chip erase request detected during boot will be performed by the boot FW 314 #endif 315 316 #ifndef SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N 317 // #define SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x0 // Disable the boot loader bank erase function 318 #define SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x1 // Enable the boot loader bank erase function 319 #endif 320 321 //##################################### 322 // Flash image valid 323 //##################################### 324 #ifndef SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID 325 #define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID 0x00000000 // Flash image vector table is at address 0x00000000 (default) 326 // #define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID <valid_vector_table_addr> // Flash image vector table is at address <valid_vector_table_addr> 327 // #define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID <invalid_vector_table_addr> // Flash image vector table address is invalid. ROM boot loader is called. 328 #endif 329 330 //##################################### 331 // Flash sector write protection 332 //##################################### 333 #ifndef SET_CCFG_CCFG_PROT_31_0 334 #define SET_CCFG_CCFG_PROT_31_0 0xFFFFFFFF 335 #endif 336 337 #ifndef SET_CCFG_CCFG_PROT_63_32 338 #define SET_CCFG_CCFG_PROT_63_32 0xFFFFFFFF 339 #endif 340 341 #ifndef SET_CCFG_CCFG_PROT_95_64 342 #define SET_CCFG_CCFG_PROT_95_64 0xFFFFFFFF 343 #endif 344 345 #ifndef SET_CCFG_CCFG_PROT_127_96 346 #define SET_CCFG_CCFG_PROT_127_96 0xFFFFFFFF 347 #endif 348 349 //##################################### 350 // Select between cache or GPRAM 351 //##################################### 352 #ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 353 // #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x0 // Cache is disabled and GPRAM is available at 0x11000000-0x11001FFF 354 #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x1 // Cache is enabled and GPRAM is disabled (unavailable) 355 #endif 356 357 //##################################### 358 // TCXO settings 359 //##################################### 360 #ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 361 #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x1 // Deprecated. Must be set to 0x1. 362 #endif 363 364 #ifndef SET_CCFG_MODE_CONF_1_TCXO_TYPE 365 #define SET_CCFG_MODE_CONF_1_TCXO_TYPE 0x1 // 1 = Clipped-sine type. 366 //#define SET_CCFG_MODE_CONF_1_TCXO_TYPE 0x0 // 0 = CMOS type. 367 #endif 368 369 #ifndef SET_CCFG_MODE_CONF_1_TCXO_MAX_START 370 #define SET_CCFG_MODE_CONF_1_TCXO_MAX_START 0x7F // Maximum TCXO startup time in units of 100us. 371 #endif 372 373 //***************************************************************************** 374 // 375 // CCFG values that should not be modified. 376 // 377 //***************************************************************************** 378 #define SET_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG 0x0058 379 #define SET_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS (CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M >> CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S) 380 381 #if ( CCFG_FORCE_VDDR_HH ) 382 #define SET_CCFG_MODE_CONF_VDDR_EXT_LOAD 0x0 // Special setting to enable forced VDDR HH voltage 383 #else 384 #define SET_CCFG_MODE_CONF_VDDR_EXT_LOAD 0x1 385 #endif 386 387 #define SET_CCFG_MODE_CONF_RTC_COMP 0x1 388 #define SET_CCFG_MODE_CONF_HF_COMP 0x1 389 390 #define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45 0xFF 391 #define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25 0xFF 392 #define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5 0xFF 393 #define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15 0xFF 394 395 #define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125 0xFF 396 #define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105 0xFF 397 #define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85 0xFF 398 #define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65 0xFF 399 400 #define SET_CCFG_RTC_OFFSET_RTC_COMP_P0 0xFFFF 401 #define SET_CCFG_RTC_OFFSET_RTC_COMP_P1 0xFF 402 #define SET_CCFG_RTC_OFFSET_RTC_COMP_P2 0xFF 403 404 #define SET_CCFG_FREQ_OFFSET_HF_COMP_P0 0xFFFF 405 #define SET_CCFG_FREQ_OFFSET_HF_COMP_P1 0xFF 406 #define SET_CCFG_FREQ_OFFSET_HF_COMP_P2 0xFF 407 408 //***************************************************************************** 409 // 410 // Concatenate bit fields to words. 411 // DO NOT EDIT! 412 // 413 //***************************************************************************** 414 #define DEFAULT_CCFG_EXT_LF_CLK ( \ 415 ((((uint32_t)( SET_CCFG_EXT_LF_CLK_DIO )) << CCFG_EXT_LF_CLK_DIO_S ) | ~CCFG_EXT_LF_CLK_DIO_M ) & \ 416 ((((uint32_t)( SET_CCFG_EXT_LF_CLK_RTC_INCREMENT )) << CCFG_EXT_LF_CLK_RTC_INCREMENT_S ) | ~CCFG_EXT_LF_CLK_RTC_INCREMENT_M ) ) 417 418 #define DEFAULT_CCFG_MODE_CONF_1 ( \ 419 ((((uint32_t)( SET_CCFG_MODE_CONF_1_TCXO_TYPE )) << CCFG_MODE_CONF_1_TCXO_TYPE_S ) | ~CCFG_MODE_CONF_1_TCXO_TYPE_M ) & \ 420 ((((uint32_t)( SET_CCFG_MODE_CONF_1_TCXO_MAX_START )) << CCFG_MODE_CONF_1_TCXO_MAX_START_S ) | ~CCFG_MODE_CONF_1_TCXO_MAX_START_M ) & \ 421 ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN )) << CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M ) & \ 422 ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN )) << CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_M ) & \ 423 ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK )) << CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_M ) & \ 424 ((((uint32_t)( SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT )) << CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S ) | ~CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_M ) & \ 425 ((((uint32_t)( SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET )) << CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S ) | ~CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_M ) & \ 426 ((((uint32_t)( SET_CCFG_MODE_CONF_1_XOSC_MAX_START )) << CCFG_MODE_CONF_1_XOSC_MAX_START_S ) | ~CCFG_MODE_CONF_1_XOSC_MAX_START_M ) ) 427 428 #define DEFAULT_CCFG_SIZE_AND_DIS_FLAGS ( \ 429 ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG )) << CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_M ) & \ 430 ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS )) << CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M ) & \ 431 ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_M ) & \ 432 ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M ) & \ 433 ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_M ) & \ 434 ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) ) 435 436 #define DEFAULT_CCFG_MODE_CONF ( \ 437 ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA )) << CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S ) | ~CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_M ) & \ 438 ((((uint32_t)( SET_CCFG_MODE_CONF_DCDC_RECHARGE )) << CCFG_MODE_CONF_DCDC_RECHARGE_S ) | ~CCFG_MODE_CONF_DCDC_RECHARGE_M ) & \ 439 ((((uint32_t)( SET_CCFG_MODE_CONF_DCDC_ACTIVE )) << CCFG_MODE_CONF_DCDC_ACTIVE_S ) | ~CCFG_MODE_CONF_DCDC_ACTIVE_M ) & \ 440 ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_EXT_LOAD )) << CCFG_MODE_CONF_VDDR_EXT_LOAD_S ) | ~CCFG_MODE_CONF_VDDR_EXT_LOAD_M ) & \ 441 ((((uint32_t)( SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL )) << CCFG_MODE_CONF_VDDS_BOD_LEVEL_S ) | ~CCFG_MODE_CONF_VDDS_BOD_LEVEL_M ) & \ 442 ((((uint32_t)( SET_CCFG_MODE_CONF_SCLK_LF_OPTION )) << CCFG_MODE_CONF_SCLK_LF_OPTION_S ) | ~CCFG_MODE_CONF_SCLK_LF_OPTION_M ) & \ 443 ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC )) << CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_S ) | ~CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_M ) & \ 444 ((((uint32_t)( SET_CCFG_MODE_CONF_RTC_COMP )) << CCFG_MODE_CONF_RTC_COMP_S ) | ~CCFG_MODE_CONF_RTC_COMP_M ) & \ 445 ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_FREQ )) << CCFG_MODE_CONF_XOSC_FREQ_S ) | ~CCFG_MODE_CONF_XOSC_FREQ_M ) & \ 446 ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_CAP_MOD )) << CCFG_MODE_CONF_XOSC_CAP_MOD_S ) | ~CCFG_MODE_CONF_XOSC_CAP_MOD_M ) & \ 447 ((((uint32_t)( SET_CCFG_MODE_CONF_HF_COMP )) << CCFG_MODE_CONF_HF_COMP_S ) | ~CCFG_MODE_CONF_HF_COMP_M ) & \ 448 ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA )) << CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S ) | ~CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M ) & \ 449 ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_CAP )) << CCFG_MODE_CONF_VDDR_CAP_S ) | ~CCFG_MODE_CONF_VDDR_CAP_M ) ) 450 451 #define DEFAULT_CCFG_VOLT_LOAD_0 ( \ 452 ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_M ) & \ 453 ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_M ) & \ 454 ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_M ) & \ 455 ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_M ) ) 456 457 #define DEFAULT_CCFG_VOLT_LOAD_1 ( \ 458 ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_M ) & \ 459 ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_M ) & \ 460 ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_M ) & \ 461 ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_M ) ) 462 463 #define DEFAULT_CCFG_RTC_OFFSET ( \ 464 ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P0 )) << CCFG_RTC_OFFSET_RTC_COMP_P0_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P0_M ) & \ 465 ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P1 )) << CCFG_RTC_OFFSET_RTC_COMP_P1_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P1_M ) & \ 466 ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P2 )) << CCFG_RTC_OFFSET_RTC_COMP_P2_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P2_M ) ) 467 468 #define DEFAULT_CCFG_FREQ_OFFSET ( \ 469 ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P0 )) << CCFG_FREQ_OFFSET_HF_COMP_P0_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P0_M ) & \ 470 ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P1 )) << CCFG_FREQ_OFFSET_HF_COMP_P1_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P1_M ) & \ 471 ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P2 )) << CCFG_FREQ_OFFSET_HF_COMP_P2_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P2_M ) ) 472 473 #define DEFAULT_CCFG_IEEE_MAC_0 SET_CCFG_IEEE_MAC_0 474 #define DEFAULT_CCFG_IEEE_MAC_1 SET_CCFG_IEEE_MAC_1 475 #define DEFAULT_CCFG_IEEE_BLE_0 SET_CCFG_IEEE_BLE_0 476 #define DEFAULT_CCFG_IEEE_BLE_1 SET_CCFG_IEEE_BLE_1 477 478 #define DEFAULT_CCFG_BL_CONFIG ( \ 479 ((((uint32_t)( SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE )) << CCFG_BL_CONFIG_BOOTLOADER_ENABLE_S ) | ~CCFG_BL_CONFIG_BOOTLOADER_ENABLE_M ) & \ 480 ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_LEVEL )) << CCFG_BL_CONFIG_BL_LEVEL_S ) | ~CCFG_BL_CONFIG_BL_LEVEL_M ) & \ 481 ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_PIN_NUMBER )) << CCFG_BL_CONFIG_BL_PIN_NUMBER_S ) | ~CCFG_BL_CONFIG_BL_PIN_NUMBER_M ) & \ 482 ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_ENABLE )) << CCFG_BL_CONFIG_BL_ENABLE_S ) | ~CCFG_BL_CONFIG_BL_ENABLE_M ) ) 483 484 #define DEFAULT_CCFG_ERASE_CONF ( \ 485 ((((uint32_t)( SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N )) << CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_S ) | ~CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_M ) & \ 486 ((((uint32_t)( SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N )) << CCFG_ERASE_CONF_BANK_ERASE_DIS_N_S ) | ~CCFG_ERASE_CONF_BANK_ERASE_DIS_N_M ) ) 487 488 #define DEFAULT_CCFG_CCFG_TI_OPTIONS ( \ 489 ((((uint32_t)( SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE )) << CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_S ) | ~CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_M ) ) 490 491 #define DEFAULT_CCFG_CCFG_TAP_DAP_0 ( \ 492 ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_M ) & \ 493 ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_M ) & \ 494 ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_M ) ) 495 496 #define DEFAULT_CCFG_CCFG_TAP_DAP_1 ( \ 497 ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_M ) & \ 498 ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_M ) & \ 499 ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_M ) ) 500 501 #define DEFAULT_CCFG_IMAGE_VALID_CONF SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID 502 503 #define DEFAULT_CCFG_CCFG_PROT_31_0 SET_CCFG_CCFG_PROT_31_0 504 #define DEFAULT_CCFG_CCFG_PROT_63_32 SET_CCFG_CCFG_PROT_63_32 505 #define DEFAULT_CCFG_CCFG_PROT_95_64 SET_CCFG_CCFG_PROT_95_64 506 #define DEFAULT_CCFG_CCFG_PROT_127_96 SET_CCFG_CCFG_PROT_127_96 507 508 //***************************************************************************** 509 // 510 // Customer Configuration Area in Lock Page 511 // 512 //***************************************************************************** 513 #if defined(__IAR_SYSTEMS_ICC__) 514 __root const ccfg_t __ccfg @ ".ccfg" = 515 #elif defined(__TI_COMPILER_VERSION__) 516 #pragma DATA_SECTION(__ccfg, ".ccfg") 517 #pragma RETAIN(__ccfg) 518 const ccfg_t __ccfg = 519 #else 520 /* Modified for Zephyr to use __ti_ccfg_section */ 521 const ccfg_t __ti_ccfg_section __ccfg = 522 #endif 523 { // Mapped to address 524 DEFAULT_CCFG_EXT_LF_CLK , // 0x50003FA8 (0x50003xxx maps to last 525 DEFAULT_CCFG_MODE_CONF_1 , // 0x50003FAC sector in FLASH. 526 DEFAULT_CCFG_SIZE_AND_DIS_FLAGS , // 0x50003FB0 Independent of FLASH size) 527 DEFAULT_CCFG_MODE_CONF , // 0x50003FB4 528 DEFAULT_CCFG_VOLT_LOAD_0 , // 0x50003FB8 529 DEFAULT_CCFG_VOLT_LOAD_1 , // 0x50003FBC 530 DEFAULT_CCFG_RTC_OFFSET , // 0x50003FC0 531 DEFAULT_CCFG_FREQ_OFFSET , // 0x50003FC4 532 DEFAULT_CCFG_IEEE_MAC_0 , // 0x50003FC8 533 DEFAULT_CCFG_IEEE_MAC_1 , // 0x50003FCC 534 DEFAULT_CCFG_IEEE_BLE_0 , // 0x50003FD0 535 DEFAULT_CCFG_IEEE_BLE_1 , // 0x50003FD4 536 DEFAULT_CCFG_BL_CONFIG , // 0x50003FD8 537 DEFAULT_CCFG_ERASE_CONF , // 0x50003FDC 538 DEFAULT_CCFG_CCFG_TI_OPTIONS , // 0x50003FE0 539 DEFAULT_CCFG_CCFG_TAP_DAP_0 , // 0x50003FE4 540 DEFAULT_CCFG_CCFG_TAP_DAP_1 , // 0x50003FE8 541 DEFAULT_CCFG_IMAGE_VALID_CONF , // 0x50003FEC 542 DEFAULT_CCFG_CCFG_PROT_31_0 , // 0x50003FF0 543 DEFAULT_CCFG_CCFG_PROT_63_32 , // 0x50003FF4 544 DEFAULT_CCFG_CCFG_PROT_95_64 , // 0x50003FF8 545 DEFAULT_CCFG_CCFG_PROT_127_96 , // 0x50003FFC 546 }; 547 548 #endif // __CCFC_C__ 549
