1<?xml version="1.0" encoding="utf-8"?>
2<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
3  <vendor>Cypress Semiconductor</vendor>
4  <vendorID>Cypress</vendorID>
5  <name>cyw20829</name>
6  <series>CYW20829</series>
7  <version>1.0</version>
8  <description>CYW20829</description>
9  <licenseText>(c) (2016-2021), Cypress Semiconductor Corporation (an Infineon company)\n
10    or an affiliate of Cypress Semiconductor Corporation.\n
11\n
12    SPDX-License-Identifier: Apache-2.0\n
13\n
14    Licensed under the Apache License, Version 2.0 (the "License");\n
15    you may not use this file except in compliance with the License.\n
16    You may obtain a copy of the License at\n
17\n
18      http://www.apache.org/licenses/LICENSE-2.0\n
19\n
20    Unless required by applicable law or agreed to in writing, software\n
21    distributed under the License is distributed on an "AS IS" BASIS,\n
22    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n
23    See the License for the specific language governing permissions and\n
24    limitations under the License.</licenseText>
25  <cpu>
26    <name>CM33</name>
27    <revision>r0p1</revision>
28    <endian>little</endian>
29    <mpuPresent>true</mpuPresent>
30    <fpuPresent>true</fpuPresent>
31    <vtorPresent>1</vtorPresent>
32    <nvicPrioBits>3</nvicPrioBits>
33    <vendorSystickConfig>0</vendorSystickConfig>
34  </cpu>
35  <addressUnitBits>8</addressUnitBits>
36  <width>32</width>
37  <resetValue>0x00000000</resetValue>
38  <resetMask>0xFFFFFFFF</resetMask>
39  <peripherals>
40    <peripheral>
41      <name>PERI</name>
42      <description>Peripheral interconnect</description>
43      <baseAddress>0x40000000</baseAddress>
44      <addressBlock>
45        <offset>0</offset>
46        <size>65536</size>
47        <usage>registers</usage>
48      </addressBlock>
49      <registers>
50        <register>
51          <name>TIMEOUT_CTL</name>
52          <description>Timeout control</description>
53          <addressOffset>0x200</addressOffset>
54          <size>32</size>
55          <access>read-write</access>
56          <resetValue>0xFFFF</resetValue>
57          <resetMask>0x8000FFFF</resetMask>
58          <fields>
59            <field>
60              <name>TIMEOUT</name>
61              <description>This field specifies a number of peripheral group root undivided (clk_group_root[i]) clock cycles. If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB5 bus error and a timeout status is set. '0x0000'-'0xfffe': Number of peripheral group clock cycles. '0xffff': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated, and a interrupt will never be generated.
62Note that TIMEOUT_CTL.TIMEOUT[15:0] in clk_pclk0_root (clk_hf0) is used directly in peripheral group clock domain clk_group_root[i], even if clk_group_root[i] is async to clk_pclk0_root. This is on the assumption that this register is programmed once by SW, remain constant. Following SW programming restrictions apply to TIMEOUT_CTL.TIMEOUT[15:0]. SW should make sure that no other AHB transactions are initiated through PERI before programming this register. SW should make sure that write to TIMEOUT_CTL.TIMEOUT[15:0] is completed by doing a readback.
63Note that peripheral group-0 slaves are excluded from timeout (Refer Timeout section in mxsperi.1 BROS for more details).</description>
64              <bitRange>[15:0]</bitRange>
65              <access>read-write</access>
66            </field>
67            <field>
68              <name>HWRST_DISABLE</name>
69              <description>This field provides control for HW to reset the slave that is causing the timeout to occur.
701 - no HW reset during timeout.
710 - HW resets the corresponding slave during timeout.
72This ensures the AHB bus not to be hung after a timeout has occurred. HW asserts the reset only when INTR_AHB_ERROR.TIMEOUT_VIO[i]=1. SW needs to clear the INTR_AHB_ERROR.TIMEOUT_VIO[i]=0 before re-initialize the corresponding slave. ('i' -represents the peripheral group number)
73Note, SW needs to take care of the implication when clearing this bit when a HW reset has occurred as clearing this bit will cause HW reset de-assert.
74Note that peripheral group-0 slaves are excluded from timeout (Refer Timeout section in mxsperi.1 BROS for more details).</description>
75              <bitRange>[31:31]</bitRange>
76              <access>read-write</access>
77            </field>
78          </fields>
79        </register>
80        <register>
81          <dim>16</dim>
82          <dimIncrement>4</dimIncrement>
83          <name>AHB_ERROR_STATUS1[%s]</name>
84          <description>AHB error status1</description>
85          <addressOffset>0x1000</addressOffset>
86          <size>32</size>
87          <access>read-only</access>
88          <resetValue>0x0</resetValue>
89          <resetMask>0x0</resetMask>
90          <fields>
91            <field>
92              <name>ADDR</name>
93              <description>This field indicates the AHB transaction address[31:0] that the AHB error response is detected. This field is valid when INTR_AHB_ERROR.AHB_ERROR_VIO[i] is set for respective peripheral group (i-represent group number). Note that quantity of this register is '16', each register is dedicated to peripheral group-i starting from group-0;</description>
94              <bitRange>[31:0]</bitRange>
95              <access>read-only</access>
96            </field>
97          </fields>
98        </register>
99        <register>
100          <dim>16</dim>
101          <dimIncrement>4</dimIncrement>
102          <name>AHB_ERROR_STATUS2[%s]</name>
103          <description>AHB error status2</description>
104          <addressOffset>0x1040</addressOffset>
105          <size>32</size>
106          <access>read-only</access>
107          <resetValue>0x0</resetValue>
108          <resetMask>0x0</resetMask>
109          <fields>
110            <field>
111              <name>P</name>
112              <description>N/A</description>
113              <bitRange>[0:0]</bitRange>
114              <access>read-only</access>
115            </field>
116            <field>
117              <name>NS</name>
118              <description>N/A</description>
119              <bitRange>[1:1]</bitRange>
120              <access>read-only</access>
121            </field>
122            <field>
123              <name>W</name>
124              <description>N/A</description>
125              <bitRange>[2:2]</bitRange>
126              <access>read-only</access>
127            </field>
128            <field>
129              <name>PC</name>
130              <description>N/A</description>
131              <bitRange>[7:4]</bitRange>
132              <access>read-only</access>
133            </field>
134            <field>
135              <name>MS</name>
136              <description>N/A</description>
137              <bitRange>[23:8]</bitRange>
138              <access>read-only</access>
139            </field>
140            <field>
141              <name>TYPE</name>
142              <description>N/A</description>
143              <bitRange>[31:30]</bitRange>
144              <access>read-only</access>
145            </field>
146          </fields>
147        </register>
148        <register>
149          <dim>16</dim>
150          <dimIncrement>4</dimIncrement>
151          <name>AHB_ERROR_STATUS3[%s]</name>
152          <description>AHB error status3</description>
153          <addressOffset>0x1080</addressOffset>
154          <size>32</size>
155          <access>read-only</access>
156          <resetValue>0x0</resetValue>
157          <resetMask>0x0</resetMask>
158          <fields>
159            <field>
160              <name>SLAVE_NO</name>
161              <description>Indicate slave number in respective peripheral group for which Timeout is detected.
162This field is valid when INTR_AHB_ERROR.TIMEOUT[i] is set for respective peripheral group (i-represents peripheral group).
163Note that quantity of this register is '16', each register is dedicated to peripheral group-i starting from group-1;</description>
164              <bitRange>[4:0]</bitRange>
165              <access>read-only</access>
166            </field>
167          </fields>
168        </register>
169        <register>
170          <name>INTR_AHB_ERROR</name>
171          <description>Interrupt AHB error</description>
172          <addressOffset>0x10C0</addressOffset>
173          <size>32</size>
174          <access>read-write</access>
175          <resetValue>0x0</resetValue>
176          <resetMask>0xFFFEFFFF</resetMask>
177          <fields>
178            <field>
179              <name>AHB_ERROR_VIO</name>
180              <description>HW sets respective bit in this field to '1', when AHB error is detected on respective peripheral group. This is 16-bit interrupt register field.
181Bit-0 indicates AHB error response is detected in peripheral group-0,
182Bit-1 indicates AHB error response is detected in peripheral group-1,
183             ..
184Bit-15 indicates AHB error response is detected in peripheral group-15.</description>
185              <bitRange>[15:0]</bitRange>
186              <access>read-write</access>
187            </field>
188            <field>
189              <name>TIMEOUT_VIO</name>
190              <description>HW sets respective bit in this field to '1', when AHB timeout  is detected on respective peripheral group. This is 15-bit interrupt register field.
191Bit-17 indicates AHB timeout is detected in peripheral group-1,
192Bit-18 indicates AHB timeout is detected in peripheral group-2,
193             ..
194Bit-31 indicates AHB timeout is detected in peripheral group-15.</description>
195              <bitRange>[31:17]</bitRange>
196              <access>read-write</access>
197            </field>
198          </fields>
199        </register>
200        <register>
201          <name>INTR_AHB_ERROR_SET</name>
202          <description>Interrupt AHB error set</description>
203          <addressOffset>0x10C4</addressOffset>
204          <size>32</size>
205          <access>read-write</access>
206          <resetValue>0x0</resetValue>
207          <resetMask>0xFFFEFFFF</resetMask>
208          <fields>
209            <field>
210              <name>AHB_ERROR_VIO</name>
211              <description>Write this field with '1' to set corresponding INTR_AHB_ERROR field (a write of '0' has no effect).</description>
212              <bitRange>[15:0]</bitRange>
213              <access>read-write</access>
214            </field>
215            <field>
216              <name>TIMEOUT_VIO</name>
217              <description>Write this field with '1' to set corresponding INTR_AHB_ERROR field (a write of '0' has no effect).</description>
218              <bitRange>[31:17]</bitRange>
219              <access>read-write</access>
220            </field>
221          </fields>
222        </register>
223        <register>
224          <name>INTR_AHB_ERROR_MASK</name>
225          <description>Interrupt AHB error mask</description>
226          <addressOffset>0x10C8</addressOffset>
227          <size>32</size>
228          <access>read-write</access>
229          <resetValue>0x0</resetValue>
230          <resetMask>0xFFFEFFFF</resetMask>
231          <fields>
232            <field>
233              <name>AHB_ERROR_VIO</name>
234              <description>Mask for corresponding field in INTR_AHB_ERROR register.</description>
235              <bitRange>[15:0]</bitRange>
236              <access>read-write</access>
237            </field>
238            <field>
239              <name>TIMEOUT_VIO</name>
240              <description>Mask for corresponding field in INTR_AHB_ERROR register.</description>
241              <bitRange>[31:17]</bitRange>
242              <access>read-write</access>
243            </field>
244          </fields>
245        </register>
246        <register>
247          <name>INTR_AHB_ERROR_MASKED</name>
248          <description>Interrupt AHB error masked</description>
249          <addressOffset>0x10CC</addressOffset>
250          <size>32</size>
251          <access>read-only</access>
252          <resetValue>0x0</resetValue>
253          <resetMask>0xFFFEFFFF</resetMask>
254          <fields>
255            <field>
256              <name>AHB_ERROR_VIO</name>
257              <description>Logical AND of corresponding INTR_AHB_ERROR and INTR_AHB_ERROR_MASK fields.</description>
258              <bitRange>[15:0]</bitRange>
259              <access>read-only</access>
260            </field>
261            <field>
262              <name>TIMEOUT_VIO</name>
263              <description>Logical AND of corresponding INTR_AHB_ERROR and INTR_AHB_ERROR_MASK fields.</description>
264              <bitRange>[31:17]</bitRange>
265              <access>read-only</access>
266            </field>
267          </fields>
268        </register>
269        <register>
270          <name>TR_CMD</name>
271          <description>Trigger command</description>
272          <addressOffset>0x2000</addressOffset>
273          <size>32</size>
274          <access>read-write</access>
275          <resetValue>0x0</resetValue>
276          <resetMask>0xE0001FFF</resetMask>
277          <fields>
278            <field>
279              <name>TR_SEL</name>
280              <description>Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not present, the trigger activation has no effect.</description>
281              <bitRange>[7:0]</bitRange>
282              <access>read-write</access>
283            </field>
284            <field>
285              <name>GROUP_SEL</name>
286              <description>Specifies the trigger group:
287'0'-'15': trigger multiplexer groups.
288'16'-'31': trigger 1-to-1 groups.</description>
289              <bitRange>[12:8]</bitRange>
290              <access>read-write</access>
291            </field>
292            <field>
293              <name>TR_EDGE</name>
294              <description>Specifies if the activated  trigger is treated as a level sensitive or edge sensitive  trigger.
295'0': level sensitive. The trigger reflects TR_CMD.ACTIVATE.
296'1': edge sensitive trigger. The trigger is activated for two clk_peri cycles.</description>
297              <bitRange>[29:29]</bitRange>
298              <access>read-write</access>
299            </field>
300            <field>
301              <name>OUT_SEL</name>
302              <description>Specifies whether trigger activation is for a specific input or output trigger of the trigger multiplexer. Activation of a specific input trigger, will result in activation of all output triggers that have the specific input trigger selected through their TR_OUT_CTL.TR_SEL  field. Activation of a specific output trigger, will result in activation of the specified TR_SEL output trigger only.
303'0': TR_SEL selection and trigger activation is for an input trigger to the trigger multiplexer.
304'1': TR_SEL selection and trigger activation is for an output trigger from the trigger multiplexer.
305
306Note: this field is not used for trigger 1-to-1 groups.</description>
307              <bitRange>[30:30]</bitRange>
308              <access>read-write</access>
309            </field>
310            <field>
311              <name>ACTIVATE</name>
312              <description>SW sets this field to '1' to activate (set to '1') a trigger as identified by TR_SEL, TR_EDGE and OUT_SEL. HW sets this field to '0' for edge sensitive triggers AFTER the selected trigger is activated for two clk_peri cycles.
313
314Note: when ACTIVATE is '1', SW should not modify the other register fields.
315SW MUST NOT set ACTIVATE bit to '1' while updating the other register bits simultaneously. At first the SW MUST update the other register bits as needed, and then set ACTIVATE to '1' with a new register write.</description>
316              <bitRange>[31:31]</bitRange>
317              <access>read-write</access>
318            </field>
319          </fields>
320        </register>
321        <register>
322          <name>INFRA_CLK_FORCE</name>
323          <description>Infrastructure clock force enable</description>
324          <addressOffset>0x2004</addressOffset>
325          <size>32</size>
326          <access>read-write</access>
327          <resetValue>0x0</resetValue>
328          <resetMask>0x1</resetMask>
329          <fields>
330            <field>
331              <name>ENABLED</name>
332              <description>Infrastructure clock force enable.
3330: Disabled
3341: Enabled</description>
335              <bitRange>[0:0]</bitRange>
336              <access>read-write</access>
337            </field>
338          </fields>
339        </register>
340        <cluster>
341          <dim>4</dim>
342          <dimIncrement>64</dimIncrement>
343          <name>GR[%s]</name>
344          <description>Peripheral group structure</description>
345          <addressOffset>0x00004000</addressOffset>
346          <register>
347            <name>CLOCK_CTL</name>
348            <description>Clock control</description>
349            <addressOffset>0x0</addressOffset>
350            <size>32</size>
351            <access>read-write</access>
352            <resetValue>0x0</resetValue>
353            <resetMask>0xFF00</resetMask>
354            <fields>
355              <field>
356                <name>INT8_DIV</name>
357                <description>Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[1/2/3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256].
358
359Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
360                <bitRange>[15:8]</bitRange>
361                <access>read-write</access>
362              </field>
363            </fields>
364          </register>
365          <register>
366            <name>SL_CTL</name>
367            <description>Slave control</description>
368            <addressOffset>0x10</addressOffset>
369            <size>32</size>
370            <access>read-write</access>
371            <resetValue>0x0</resetValue>
372            <resetMask>0xFFFFFFFF</resetMask>
373            <fields>
374              <field>
375                <name>ENABLED</name>
376                <description>Slave Enable. Each bit indicates whether the respective slave is enabled. If the slave is disabled, its clock is gated off (constant '0').
377
378Note: For peripheral group 0 slave 0,1, and 2 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.
379The peripheral IP that drives the Q-Channel back to Clock Controllers need to ensure that it has clock (usually driven by Clk_hf1~N that is only available after CPU configures their roots in the SRSS) to provide back the Q-Channel handshake, if not the deadlock situation will procure. To avoid deadlock mentioned above, all IPs in all groups other than group-0 are disabled  (SL_CTL.ENABLED is set to '0') by default after POR (cold boot) (i.e. PERI HW hardcodes local parameter SL_CTL_DEFAULT to 32'hFFFFFFFF for group-0 and to 32'h00000000 for other groups (group-1 to group-15)).  Once CPU is up and running &amp; Clk_hf1~N configured, CPU can enable them.
380The SL_CTL.ENABLED are retained during DEEPSLEEP to avoid enabling configuration after wakeup.</description>
381                <bitRange>[31:0]</bitRange>
382                <access>read-write</access>
383              </field>
384            </fields>
385          </register>
386          <register>
387            <name>SL_CTL2</name>
388            <description>Slave control2</description>
389            <addressOffset>0x14</addressOffset>
390            <size>32</size>
391            <access>read-write</access>
392            <resetValue>0x0</resetValue>
393            <resetMask>0xFFFFFFFF</resetMask>
394            <fields>
395              <field>
396                <name>RST</name>
397                <description>Slave reset. Each bit indicates whether the respective slave is enabled. If the slave is under reset, its clock is gated off (constant '0') and its resets are activated.
398
399Note: For peripheral group 0 slave 0,1, and 2 (the peripheral interconnect MMIO registers), this field is a constant '0' (SW: R): the slave can NOT be in reset.</description>
400                <bitRange>[31:0]</bitRange>
401                <access>read-write</access>
402              </field>
403            </fields>
404          </register>
405          <register>
406            <name>SL_CTL3</name>
407            <description>Slave control3</description>
408            <addressOffset>0x18</addressOffset>
409            <size>32</size>
410            <access>read-only</access>
411            <resetValue>0x0</resetValue>
412            <resetMask>0xFFFFFFFF</resetMask>
413            <fields>
414              <field>
415                <name>SS_POWERSTATE</name>
416                <description>Slave status to represent subsystem (SS) IP current power status. Each bit represents the respective IP power state (Note that separate mxsperi peripheral group should be defined for type4 peripheral, should not be mixed with type1/2/3 and same peripheral group can have multiple type4 peripherals)
4170 - indiacates IP is in OFF state.
4181 - indicates IP is in ON state.
419This register exists only for peripheral group with type4 peripherals (has its own PPU, P/Q-Channel consolidation and clock gating).
420This is readonly register connecting to PERI input signal coming from the respective SS IP.
421Since this register is passthorugh of status signal from peripheral the default value defined is w.r.t. respective IP reset.</description>
422                <bitRange>[31:0]</bitRange>
423                <access>read-only</access>
424              </field>
425            </fields>
426          </register>
427        </cluster>
428        <cluster>
429          <dim>10</dim>
430          <dimIncrement>1024</dimIncrement>
431          <name>TR_GR[%s]</name>
432          <description>Trigger group</description>
433          <addressOffset>0x00008000</addressOffset>
434          <register>
435            <dim>256</dim>
436            <dimIncrement>4</dimIncrement>
437            <name>TR_CTL[%s]</name>
438            <description>Trigger control register</description>
439            <addressOffset>0x0</addressOffset>
440            <size>32</size>
441            <access>read-write</access>
442            <resetValue>0x0</resetValue>
443            <resetMask>0x13FF</resetMask>
444            <fields>
445              <field>
446                <name>TR_SEL</name>
447                <description>Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.</description>
448                <bitRange>[7:0]</bitRange>
449                <access>read-write</access>
450              </field>
451              <field>
452                <name>TR_INV</name>
453                <description>Specifies if the output trigger is inverted.</description>
454                <bitRange>[8:8]</bitRange>
455                <access>read-write</access>
456              </field>
457              <field>
458                <name>TR_EDGE</name>
459                <description>Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive  trigger.
460'0': level sensitive.
461'1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.</description>
462                <bitRange>[9:9]</bitRange>
463                <access>read-write</access>
464              </field>
465              <field>
466                <name>DBG_FREEZE_EN</name>
467                <description>Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation.</description>
468                <bitRange>[12:12]</bitRange>
469                <access>read-write</access>
470              </field>
471            </fields>
472          </register>
473        </cluster>
474        <cluster>
475          <dim>5</dim>
476          <dimIncrement>1024</dimIncrement>
477          <name>TR_1TO1_GR[%s]</name>
478          <description>Trigger 1-to-1 group</description>
479          <addressOffset>0x0000C000</addressOffset>
480          <register>
481            <dim>256</dim>
482            <dimIncrement>4</dimIncrement>
483            <name>TR_CTL[%s]</name>
484            <description>Trigger control register</description>
485            <addressOffset>0x0</addressOffset>
486            <size>32</size>
487            <access>read-write</access>
488            <resetValue>0x0</resetValue>
489            <resetMask>0x1301</resetMask>
490            <fields>
491              <field>
492                <name>TR_SEL</name>
493                <description>Specifies input trigger:
494'0'': constant signal level '0'.
495'1': input trigger.</description>
496                <bitRange>[0:0]</bitRange>
497                <access>read-write</access>
498              </field>
499              <field>
500                <name>TR_INV</name>
501                <description>Specifies if the output trigger is inverted.</description>
502                <bitRange>[8:8]</bitRange>
503                <access>read-write</access>
504              </field>
505              <field>
506                <name>TR_EDGE</name>
507                <description>Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive  trigger.
508'0': level sensitive.
509'1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.</description>
510                <bitRange>[9:9]</bitRange>
511                <access>read-write</access>
512              </field>
513              <field>
514                <name>DBG_FREEZE_EN</name>
515                <description>Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation.</description>
516                <bitRange>[12:12]</bitRange>
517                <access>read-write</access>
518              </field>
519            </fields>
520          </register>
521        </cluster>
522      </registers>
523    </peripheral>
524    <peripheral>
525      <name>PPC</name>
526      <description>Peripheral Protection Controller</description>
527      <baseAddress>0x40020000</baseAddress>
528      <addressBlock>
529        <offset>0</offset>
530        <size>65536</size>
531        <usage>registers</usage>
532      </addressBlock>
533      <registers>
534        <register>
535          <name>CTL</name>
536          <description>PPC Control Registers</description>
537          <addressOffset>0x0</addressOffset>
538          <size>32</size>
539          <access>read-write</access>
540          <resetValue>0x0</resetValue>
541          <resetMask>0x1</resetMask>
542          <fields>
543            <field>
544              <name>RESP_CFG</name>
545              <description>Response Configuration. This field configures the security violation response.
5460 - Read-Zero Write Ignore (RZWI)
5471 - Bus Error</description>
548              <bitRange>[0:0]</bitRange>
549              <access>read-write</access>
550            </field>
551          </fields>
552        </register>
553        <register>
554          <name>STATUS1</name>
555          <description>Status1 Register</description>
556          <addressOffset>0x4</addressOffset>
557          <size>32</size>
558          <access>read-only</access>
559          <resetValue>0x0</resetValue>
560          <resetMask>0xFF07F3FF</resetMask>
561          <fields>
562            <field>
563              <name>INDEX</name>
564              <description>Index to indicate which peripheral region has first violated security access when INTR_PPC.SECURE_VIO=1. This field is only valid when INTR_PPC.SECURE_VIO=1.
565Note that when STATUS1.TYPE=AHB_ERROR (3'd5), this field is not valid.</description>
566              <bitRange>[9:0]</bitRange>
567              <access>read-only</access>
568            </field>
569            <field>
570              <name>PC</name>
571              <description>Indicates the master interface transaction PC value when violation is detected.
572This field is only valid when INTR_PPC.SECURE_VIO=1.</description>
573              <bitRange>[15:12]</bitRange>
574              <access>read-only</access>
575            </field>
576            <field>
577              <name>TYPE</name>
578              <description>N/A</description>
579              <bitRange>[18:16]</bitRange>
580              <access>read-only</access>
581            </field>
582            <field>
583              <name>MS</name>
584              <description>Indicates the Master ID of violating transfer.</description>
585              <bitRange>[31:24]</bitRange>
586              <access>read-only</access>
587            </field>
588          </fields>
589        </register>
590        <register>
591          <name>STATUS2</name>
592          <description>Status2 Register</description>
593          <addressOffset>0x8</addressOffset>
594          <size>32</size>
595          <access>read-only</access>
596          <resetValue>0x0</resetValue>
597          <resetMask>0xFFFFFFFF</resetMask>
598          <fields>
599            <field>
600              <name>ADDR</name>
601              <description>Indicates the address of PPC violating transfer. STATUS2.ADDR status register is addition to PPC STATUS1 register. And all rules applicable for STATUS1 is applies to STATUS2 also.</description>
602              <bitRange>[31:0]</bitRange>
603              <access>read-only</access>
604            </field>
605          </fields>
606        </register>
607        <register>
608          <name>LOCK_MASK</name>
609          <description>Locked Mask</description>
610          <addressOffset>0xC</addressOffset>
611          <size>32</size>
612          <access>read-write</access>
613          <resetValue>0x0</resetValue>
614          <resetMask>0xFFFFFFFF</resetMask>
615          <fields>
616            <field>
617              <name>LOCK_MASK</name>
618              <description>A mask that indicates which protection contexts are 'locked'.  Once locked, a protection context cannot be unlocked until the next reset or power cycle. Bit i specifies the locked status for protection context i.
6190: The protection context is unlocked.
6201: The protection context is locked.
621
622When a PC is locked, the PPC_PC_MASK, PPC_NS_ATT and PPC_S_P_ATT register bits for peripheral regions to which this PC has access can no longer be modified (PPC_NS_P_ATT is not subject to these restrictions).  The one exception to this is that PPC_PC_MASK bits associated with other protection contexts that are not themselves locked can still be cleared (but not set).</description>
623              <bitRange>[31:0]</bitRange>
624              <access>read-write</access>
625            </field>
626          </fields>
627        </register>
628        <register>
629          <name>INTR_PPC</name>
630          <description>Interrupt</description>
631          <addressOffset>0x20</addressOffset>
632          <size>32</size>
633          <access>read-write</access>
634          <resetValue>0x0</resetValue>
635          <resetMask>0x1</resetMask>
636          <fields>
637            <field>
638              <name>SECURE_VIO</name>
639              <description>HW sets this field to '1', when a security violation is detected.</description>
640              <bitRange>[0:0]</bitRange>
641              <access>read-write</access>
642            </field>
643          </fields>
644        </register>
645        <register>
646          <name>INTR_PPC_SET</name>
647          <description>Interrupt set</description>
648          <addressOffset>0x24</addressOffset>
649          <size>32</size>
650          <access>read-write</access>
651          <resetValue>0x0</resetValue>
652          <resetMask>0x1</resetMask>
653          <fields>
654            <field>
655              <name>SECURE_VIO</name>
656              <description>Write this field with '1' to set corresponding INTR_PPC field (a write of '0' has no effect).</description>
657              <bitRange>[0:0]</bitRange>
658              <access>read-write</access>
659            </field>
660          </fields>
661        </register>
662        <register>
663          <name>INTR_PPC_MASK</name>
664          <description>Interrupt mask</description>
665          <addressOffset>0x28</addressOffset>
666          <size>32</size>
667          <access>read-write</access>
668          <resetValue>0x0</resetValue>
669          <resetMask>0x1</resetMask>
670          <fields>
671            <field>
672              <name>SECURE_VIO</name>
673              <description>Mask for corresponding field in INTR_PPC register.</description>
674              <bitRange>[0:0]</bitRange>
675              <access>read-write</access>
676            </field>
677          </fields>
678        </register>
679        <register>
680          <name>INTR_PPC_MASKED</name>
681          <description>Interrupt masked</description>
682          <addressOffset>0x2C</addressOffset>
683          <size>32</size>
684          <access>read-only</access>
685          <resetValue>0x0</resetValue>
686          <resetMask>0x1</resetMask>
687          <fields>
688            <field>
689              <name>SECURE_VIO</name>
690              <description>Logical AND of corresponding INTR_PPC and INTR_PPC_MASK fields.</description>
691              <bitRange>[0:0]</bitRange>
692              <access>read-only</access>
693            </field>
694          </fields>
695        </register>
696        <register>
697          <dim>1024</dim>
698          <dimIncrement>4</dimIncrement>
699          <name>PC_MASK[%s]</name>
700          <description>Protection Context Mask</description>
701          <addressOffset>0x1000</addressOffset>
702          <size>32</size>
703          <access>read-write</access>
704          <resetValue>0xFFFFFFFF</resetValue>
705          <resetMask>0xFFFFFFFF</resetMask>
706          <fields>
707            <field>
708              <name>PC_MASK</name>
709              <description>A mask that indicates which protection contexts have access to a peripheral region.  Bit i specifies the access for protection context i.
7100: The protection context has no access to this region.
7111: The protection context has access to this region, subject to secure and privilege attribute constraints setup in PPC_NS_ATT, PPC_S_P_ATT, PPC_NS_P_ATT registers)</description>
712              <bitRange>[31:0]</bitRange>
713              <access>read-write</access>
714            </field>
715          </fields>
716        </register>
717        <register>
718          <dim>32</dim>
719          <dimIncrement>4</dimIncrement>
720          <name>NS_ATT[%s]</name>
721          <description>Non-secure attribute</description>
722          <addressOffset>0x2000</addressOffset>
723          <size>32</size>
724          <access>read-write</access>
725          <resetValue>0x0</resetValue>
726          <resetMask>0xFFFFFFFF</resetMask>
727          <fields>
728            <field>
729              <name>NS</name>
730              <description>Non-Secure. Each bit indicates whether access to a peripheral region must be secure or non-secure:
731IF SECURITY_AWARE=0
7320 - allow only secure access to respective peripheral region.
7331 - allow only non-secure access to respective peripheral region.
734IF SECURITY_AWARE=1
7350 - allow only secure access to respective peripheral region.
7361 - allows both secure and non-secure access to respective peripheral region.
737(Note that, depending on this setting the privilege access requirement for this region is specified in the corresponding PPC_S_P_ATT or PPC_NS_P_ATT register)</description>
738              <bitRange>[31:0]</bitRange>
739              <access>read-write</access>
740            </field>
741          </fields>
742        </register>
743        <register>
744          <dim>32</dim>
745          <dimIncrement>4</dimIncrement>
746          <name>S_P_ATT[%s]</name>
747          <description>Secure Privilege Attribute</description>
748          <addressOffset>0x2400</addressOffset>
749          <size>32</size>
750          <access>read-write</access>
751          <resetValue>0x0</resetValue>
752          <resetMask>0xFFFFFFFF</resetMask>
753          <fields>
754            <field>
755              <name>S_P</name>
756              <description>Secure Privilege. Each bit indicates whether access to a secure peripheral region requires privilege:
7570 - allow only secure privileged access to respective peripheral region.
7581 - allow only secure unprivileged or privileged access to respective peripheral region.</description>
759              <bitRange>[31:0]</bitRange>
760              <access>read-write</access>
761            </field>
762          </fields>
763        </register>
764        <register>
765          <dim>32</dim>
766          <dimIncrement>4</dimIncrement>
767          <name>NS_P_ATT[%s]</name>
768          <description>Non-secure Privilege Attribute</description>
769          <addressOffset>0x4000</addressOffset>
770          <size>32</size>
771          <access>read-write</access>
772          <resetValue>0x0</resetValue>
773          <resetMask>0xFFFFFFFF</resetMask>
774          <fields>
775            <field>
776              <name>NS_P</name>
777              <description>Non-Secure Privilege. Each bit indicates whether access to a non-secure peripheral region requires privilege:
7780 - allow only non-secure privileged access to respective peripheral region.
7791 - allow only non-secure unprivileged or privileged access to respective peripheral region.</description>
780              <bitRange>[31:0]</bitRange>
781              <access>read-write</access>
782            </field>
783          </fields>
784        </register>
785        <cluster>
786          <dim>157</dim>
787          <dimIncrement>4</dimIncrement>
788          <name>R_ADDR[%s]</name>
789          <description>Region Address</description>
790          <addressOffset>0x00005000</addressOffset>
791          <register>
792            <name>R_ADDR</name>
793            <description>Region Address</description>
794            <addressOffset>0x0</addressOffset>
795            <size>32</size>
796            <access>read-only</access>
797            <resetValue>0x0</resetValue>
798            <resetMask>0xFFFFFFFC</resetMask>
799            <fields>
800              <field>
801                <name>R_ADDR</name>
802                <description>This field specifies the base address of the peripheral region. The region size is defined by R_ATTR.R_SIZE. A region of n Bytes mus be n Byte aligned. Therefore, some of the lesser significant address bits of ADDR must be '0's. E.g., a 64KB address region (R_SIZE is '15') must be 64 KByte aligned, and R_ADDR[13:0] must be '0's.</description>
803                <bitRange>[31:2]</bitRange>
804                <access>read-only</access>
805              </field>
806            </fields>
807          </register>
808        </cluster>
809        <cluster>
810          <dim>157</dim>
811          <dimIncrement>4</dimIncrement>
812          <name>R_ATT[%s]</name>
813          <description>Region Attribute</description>
814          <addressOffset>0x00006000</addressOffset>
815          <register>
816            <name>R_ATT</name>
817            <description>Region Attribute</description>
818            <addressOffset>0x0</addressOffset>
819            <size>32</size>
820            <access>read-only</access>
821            <resetValue>0x0</resetValue>
822            <resetMask>0x1F000000</resetMask>
823            <fields>
824              <field>
825                <name>R_SIZE</name>
826                <description>This field specifies the size of the peripheral region:
827'0': Undefined.
828'1': 4 B region (this is the smallest region size).
829'2': 8 B region
830'3': 16 B region
831'4': 32 B region
832'5': 64 B region
833'6': 128 B region
834'7': 256 B region
835'8': 512 B region
836'9': 1 KB region
837'10': 2 KB region
838'11': 4 KB region
839'12': 8 KB region
840'13': 16 KB region
841'14': 32 KB region
842'15': 64 KB region
843'16': 128 KB region
844'17': 256 KB region
845'18': 512 KB region
846'19': 1 MB region
847'20': 2 MB region
848'21': 4 MB region
849'22': 8 MB region
850'23': 16 MB region
851'24': 32 MB region
852'25': 64 MB region
853'26': 128 MB region
854'27': 256 MB region
855'28': 512 MB region
856'29': 1 GB region
857'30': 2 GB region
858'31': 4 GB region</description>
859                <bitRange>[28:24]</bitRange>
860                <access>read-only</access>
861              </field>
862            </fields>
863          </register>
864        </cluster>
865      </registers>
866    </peripheral>
867    <peripheral>
868      <name>PERI_PCLK</name>
869      <description>Peripheral PCLK groups</description>
870      <baseAddress>0x40040000</baseAddress>
871      <addressBlock>
872        <offset>0</offset>
873        <size>131072</size>
874        <usage>registers</usage>
875      </addressBlock>
876      <registers>
877        <cluster>
878          <dim>7</dim>
879          <dimIncrement>8192</dimIncrement>
880          <name>GR[%s]</name>
881          <description>PERI clock domains</description>
882          <addressOffset>0x00000000</addressOffset>
883          <register>
884            <name>DIV_CMD</name>
885            <description>Divider command</description>
886            <addressOffset>0x0</addressOffset>
887            <size>32</size>
888            <access>read-write</access>
889            <resetValue>0x3FF03FF</resetValue>
890            <resetMask>0xC3FF03FF</resetMask>
891            <fields>
892              <field>
893                <name>DIV_SEL</name>
894                <description>(TYPE_SEL, DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed.
895
896If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock signal(s) are generated.</description>
897                <bitRange>[7:0]</bitRange>
898                <access>read-write</access>
899              </field>
900              <field>
901                <name>TYPE_SEL</name>
902                <description>Specifies the divider type of the divider on which the command is performed:
9030: 8.0 (integer) clock dividers.
9041: 16.0 (integer) clock dividers.
9052: 16.5 (fractional) clock dividers.
9063: 24.5 (fractional) clock dividers.</description>
907                <bitRange>[9:8]</bitRange>
908                <access>read-write</access>
909              </field>
910              <field>
911                <name>PA_DIV_SEL</name>
912                <description>(PA_TYPE_SEL, PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other, even when they are enabled at different times.
913
914If PA_DIV_SEL is '255' and PA_TYPE_SEL is '3', 'clk_pclk_root[i]' is used as reference.</description>
915                <bitRange>[23:16]</bitRange>
916                <access>read-write</access>
917              </field>
918              <field>
919                <name>PA_TYPE_SEL</name>
920                <description>Specifies the divider type of the divider to which phase alignment is performed for the clock enable command:
9210: 8.0 (integer) clock dividers.
9221: 16.0 (integer) clock dividers.
9232: 16.5 (fractional) clock dividers.
9243: 24.5 (fractional) clock dividers.</description>
925                <bitRange>[25:24]</bitRange>
926                <access>read-write</access>
927              </field>
928              <field>
929                <name>DISABLE</name>
930                <description>Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'.
931
932The DIV_SEL and TYPE_SEL fields specify which divider is to be disabled.
933
934The HW sets the DISABLE field to '0' immediately and the HW sets the DIV_XXX_CTL.EN field of the divider to '0' immediately.</description>
935                <bitRange>[30:30]</bitRange>
936                <access>read-write</access>
937              </field>
938              <field>
939                <name>ENABLE</name>
940                <description>Clock divider enable command (mutually exclusive with DISABLE). Typically, SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled, its integer and fractional (if present) counters are initialized to '0'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps:
9410: Disable the divider using the DIV_CMD.DISABLE field.
9421: Configure the divider's DIV_XXX_CTL register.
9432: Enable the divider using the DIV_CMD_ENABLE field.
944
945The DIV_SEL and TYPE_SEL fields specify which divider is to be enabled. The enabled divider may be phase aligned to either 'clk_pclk_root[i]' (typical usage) or to ANY enabled divider.
946
947The PA_DIV_SEL and PA_TYPE_SEL fields specify the reference divider.
948
949The HW sets the ENABLE field to '0' when the enabling is performed and the HW set the DIV_XXX_CTL.EN field of the divider to '1' when the enabling is performed. Note that enabling with phase alignment to a low frequency divider takes time. E.g. To align to a divider that generates a clock of 'clk_pclk_root[i]'/n (with n being the integer divider value INT_DIV+1), up to n cycles may be required to perform alignment. Phase alignment to 'clk_pclk_root[i]' takes affect immediately. SW can set this field to '0' during phase alignment to abort the enabling process.</description>
950                <bitRange>[31:31]</bitRange>
951                <access>read-write</access>
952              </field>
953            </fields>
954          </register>
955          <register>
956            <dim>256</dim>
957            <dimIncrement>4</dimIncrement>
958            <name>CLOCK_CTL[%s]</name>
959            <description>Clock control</description>
960            <addressOffset>0xC00</addressOffset>
961            <size>32</size>
962            <access>read-write</access>
963            <resetValue>0x3FF</resetValue>
964            <resetMask>0x3FF</resetMask>
965            <fields>
966              <field>
967                <name>DIV_SEL</name>
968                <description>Specifies one of the dividers of the divider type specified by TYPE_SEL.
969
970If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated.
971
972When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_pclk_root[i]' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.</description>
973                <bitRange>[7:0]</bitRange>
974                <access>read-write</access>
975              </field>
976              <field>
977                <name>TYPE_SEL</name>
978                <description>Specifies divider type:
9790: 8.0 (integer) clock dividers.
9801: 16.0 (integer) clock dividers.
9812: 16.5 (fractional) clock dividers.
9823: 24.5 (fractional) clock dividers.</description>
983                <bitRange>[9:8]</bitRange>
984                <access>read-write</access>
985              </field>
986            </fields>
987          </register>
988          <register>
989            <dim>256</dim>
990            <dimIncrement>4</dimIncrement>
991            <name>DIV_8_CTL[%s]</name>
992            <description>Divider control (for 8.0 divider)</description>
993            <addressOffset>0x1000</addressOffset>
994            <size>32</size>
995            <access>read-write</access>
996            <resetValue>0x0</resetValue>
997            <resetMask>0xFF01</resetMask>
998            <fields>
999              <field>
1000                <name>EN</name>
1001                <description>Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command.
1002
1003Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.</description>
1004                <bitRange>[0:0]</bitRange>
1005                <access>read-only</access>
1006              </field>
1007              <field>
1008                <name>INT8_DIV</name>
1009                <description>Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division.
1010
1011For the generation of a divided clock, the integer division range is restricted to [2, 256].
1012
1013For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50  percent duty cycle analog divided clock has no restrictions.
1014
1015Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
1016                <bitRange>[15:8]</bitRange>
1017                <access>read-write</access>
1018              </field>
1019            </fields>
1020          </register>
1021          <register>
1022            <dim>256</dim>
1023            <dimIncrement>4</dimIncrement>
1024            <name>DIV_16_CTL[%s]</name>
1025            <description>Divider control (for 16.0 divider)</description>
1026            <addressOffset>0x1400</addressOffset>
1027            <size>32</size>
1028            <access>read-write</access>
1029            <resetValue>0x0</resetValue>
1030            <resetMask>0xFFFF01</resetMask>
1031            <fields>
1032              <field>
1033                <name>EN</name>
1034                <description>Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command.
1035
1036Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.</description>
1037                <bitRange>[0:0]</bitRange>
1038                <access>read-only</access>
1039              </field>
1040              <field>
1041                <name>INT16_DIV</name>
1042                <description>Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division.
1043
1044For the generation of a divided clock, the integer division range is restricted to [2, 65,536].
1045
1046For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50  percent duty cycle analog divided clock has no restrictions.
1047
1048Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
1049                <bitRange>[23:8]</bitRange>
1050                <access>read-write</access>
1051              </field>
1052            </fields>
1053          </register>
1054          <register>
1055            <dim>256</dim>
1056            <dimIncrement>4</dimIncrement>
1057            <name>DIV_16_5_CTL[%s]</name>
1058            <description>Divider control (for 16.5 divider)</description>
1059            <addressOffset>0x1800</addressOffset>
1060            <size>32</size>
1061            <access>read-write</access>
1062            <resetValue>0x0</resetValue>
1063            <resetMask>0xFFFFF9</resetMask>
1064            <fields>
1065              <field>
1066                <name>EN</name>
1067                <description>Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command.
1068
1069Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.</description>
1070                <bitRange>[0:0]</bitRange>
1071                <access>read-only</access>
1072              </field>
1073              <field>
1074                <name>FRAC5_DIV</name>
1075                <description>Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_pclk_root[i]' cycle longer than other clock periods.
1076
1077Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
1078                <bitRange>[7:3]</bitRange>
1079                <access>read-write</access>
1080              </field>
1081              <field>
1082                <name>INT16_DIV</name>
1083                <description>Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments.
1084
1085For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32].
1086
1087For the generation of a 50/50 percent duty cycle divided clock, the  division range is restricted to [2, 65,536].
1088
1089Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
1090                <bitRange>[23:8]</bitRange>
1091                <access>read-write</access>
1092              </field>
1093            </fields>
1094          </register>
1095          <register>
1096            <dim>255</dim>
1097            <dimIncrement>4</dimIncrement>
1098            <name>DIV_24_5_CTL[%s]</name>
1099            <description>Divider control (for 24.5 divider)</description>
1100            <addressOffset>0x1C00</addressOffset>
1101            <size>32</size>
1102            <access>read-write</access>
1103            <resetValue>0x0</resetValue>
1104            <resetMask>0xFFFFFFF9</resetMask>
1105            <fields>
1106              <field>
1107                <name>EN</name>
1108                <description>Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command.
1109
1110Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.</description>
1111                <bitRange>[0:0]</bitRange>
1112                <access>read-only</access>
1113              </field>
1114              <field>
1115                <name>FRAC5_DIV</name>
1116                <description>Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_pclk_root[i]' cycle longer than other clock periods.
1117
1118Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
1119                <bitRange>[7:3]</bitRange>
1120                <access>read-write</access>
1121              </field>
1122              <field>
1123                <name>INT24_DIV</name>
1124                <description>Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments.
1125
1126For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32].
1127
1128For the generation of a 50/50 percent duty cycle divided clock, the  division range is restricted to [2, 16,777,216].
1129
1130Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
1131                <bitRange>[31:8]</bitRange>
1132                <access>read-write</access>
1133              </field>
1134            </fields>
1135          </register>
1136        </cluster>
1137      </registers>
1138    </peripheral>
1139    <peripheral>
1140      <name>RAMC_PPU0</name>
1141      <description>Power Policy Unit Registers for System RAM</description>
1142      <headerStructName>RAMC_PPU</headerStructName>
1143      <baseAddress>0x40100000</baseAddress>
1144      <addressBlock>
1145        <offset>0</offset>
1146        <size>4096</size>
1147        <usage>registers</usage>
1148      </addressBlock>
1149      <registers>
1150        <register>
1151          <name>PWPR</name>
1152          <description>Power Policy Register</description>
1153          <addressOffset>0x0</addressOffset>
1154          <size>32</size>
1155          <access>read-write</access>
1156          <resetValue>0x108</resetValue>
1157          <resetMask>0x10F110F</resetMask>
1158          <fields>
1159            <field>
1160              <name>PWR_POLICY</name>
1161              <description>Power mode policy.  When static power mode transitions are enabled, PWR_DYN_EN is set to 0, this is the target power mode for the PPU.  When dynamic power mode transitions are enabled, PWR_DYN_EN is set to 1, this is the minimum power mode for the PPU.
1162
1163This PPU supports the following modes: OFF(0), MEM_RET(2), ON(8).  Do not use WARM_RST(9) or other unsupported modes.</description>
1164              <bitRange>[3:0]</bitRange>
1165              <access>read-write</access>
1166            </field>
1167            <field>
1168              <name>PWR_DYN_EN</name>
1169              <description>Power mode dynamic transition enable.  When this bit is set to 1 dynamic transitions are enabled for power modes, allowing transitions to be initiated by changes on power mode DEVACTIVE inputs.</description>
1170              <bitRange>[8:8]</bitRange>
1171              <access>read-write</access>
1172            </field>
1173            <field>
1174              <name>LOCK_EN</name>
1175              <description>N/A</description>
1176              <bitRange>[12:12]</bitRange>
1177              <access>read-write</access>
1178            </field>
1179            <field>
1180              <name>OP_POLICY</name>
1181              <description>N/A</description>
1182              <bitRange>[19:16]</bitRange>
1183              <access>read-write</access>
1184            </field>
1185            <field>
1186              <name>OP_DYN_EN</name>
1187              <description>N/A</description>
1188              <bitRange>[24:24]</bitRange>
1189              <access>read-write</access>
1190            </field>
1191          </fields>
1192        </register>
1193        <register>
1194          <name>PMER</name>
1195          <description>Power Mode Emulation Register</description>
1196          <addressOffset>0x4</addressOffset>
1197          <size>32</size>
1198          <access>read-write</access>
1199          <resetValue>0x0</resetValue>
1200          <resetMask>0x1</resetMask>
1201          <fields>
1202            <field>
1203              <name>EMU_EN</name>
1204              <description>N/A</description>
1205              <bitRange>[0:0]</bitRange>
1206              <access>read-write</access>
1207            </field>
1208          </fields>
1209        </register>
1210        <register>
1211          <name>PWSR</name>
1212          <description>Power Status Register</description>
1213          <addressOffset>0x8</addressOffset>
1214          <size>32</size>
1215          <access>read-only</access>
1216          <resetValue>0x0</resetValue>
1217          <resetMask>0x10F110F</resetMask>
1218          <fields>
1219            <field>
1220              <name>PWR_STATUS</name>
1221              <description>Power mode status.  These bits reflect the current power mode of the PPU.  See PPU_PWPR.PWR_POLICY for power mode enumeration.</description>
1222              <bitRange>[3:0]</bitRange>
1223              <access>read-only</access>
1224            </field>
1225            <field>
1226              <name>PWR_DYN_STATUS</name>
1227              <description>Power mode dynamic transition status.  When set to 1 power mode dynamic transitions are enabled.  There might be a delay in dynamic transitions becoming active or inactive if the PPU is transitioning when PWR_DYN_EN is programmed.</description>
1228              <bitRange>[8:8]</bitRange>
1229              <access>read-only</access>
1230            </field>
1231            <field>
1232              <name>LOCK_STATUS</name>
1233              <description>N/A</description>
1234              <bitRange>[12:12]</bitRange>
1235              <access>read-only</access>
1236            </field>
1237            <field>
1238              <name>OP_STATUS</name>
1239              <description>N/A</description>
1240              <bitRange>[19:16]</bitRange>
1241              <access>read-only</access>
1242            </field>
1243            <field>
1244              <name>OP_DYN_STATUS</name>
1245              <description>N/A</description>
1246              <bitRange>[24:24]</bitRange>
1247              <access>read-only</access>
1248            </field>
1249          </fields>
1250        </register>
1251        <register>
1252          <name>DISR</name>
1253          <description>Device Interface Input Current Status Register</description>
1254          <addressOffset>0x10</addressOffset>
1255          <size>32</size>
1256          <access>read-only</access>
1257          <resetValue>0x0</resetValue>
1258          <resetMask>0xFF0007FF</resetMask>
1259          <fields>
1260            <field>
1261              <name>PWR_DEVACTIVE_STATUS</name>
1262              <description>Status of the power mode DEVACTIVE inputs.
1263
1264There is one bit for each device interface Q-Channel DEVQACTIVE.  For example, bit 0 is for Q-channel device 0 DEVQACTIVE.  Refer to PPU_IDR0.DEVCHAN for device channel enumeration.</description>
1265              <bitRange>[10:0]</bitRange>
1266              <access>read-only</access>
1267            </field>
1268            <field>
1269              <name>OP_DEVACTIVE_STATUS</name>
1270              <description>N/A</description>
1271              <bitRange>[31:24]</bitRange>
1272              <access>read-only</access>
1273            </field>
1274          </fields>
1275        </register>
1276        <register>
1277          <name>MISR</name>
1278          <description>Miscellaneous Input Current Status Register</description>
1279          <addressOffset>0x14</addressOffset>
1280          <size>32</size>
1281          <access>read-only</access>
1282          <resetValue>0x0</resetValue>
1283          <resetMask>0xFFFF01</resetMask>
1284          <fields>
1285            <field>
1286              <name>PCSMPACCEPT_STATUS</name>
1287              <description>The status of the PCSMPACCEPT input.</description>
1288              <bitRange>[0:0]</bitRange>
1289              <access>read-only</access>
1290            </field>
1291            <field>
1292              <name>DEVACCEPT_STATUS</name>
1293              <description>Status of the device interface DEVACCEPT inputs.
1294
1295There is one bit for each device interface DEVQACCEPTn.  For example, bit 8 is for Q-Channel 0 DEVQACCEPTn and bit 9 for Q-Channel 1 DEVQACCEPTn.   Refer to PPU_IDR0.DEVCHAN for device channel enumeration.</description>
1296              <bitRange>[15:8]</bitRange>
1297              <access>read-only</access>
1298            </field>
1299            <field>
1300              <name>DEVDENY_STATUS</name>
1301              <description>Status of the device interface DEVDENY inputs.
1302
1303There is one bit for each device interface DEVQDENY.  For example, bit 16 is for Q-Channel 0 DEVQDENY, and bit 17 for Q-Channel 1 DEVQDENY.  Refer to PPU_IDR0.DEVCHAN for device channel enumeration.</description>
1304              <bitRange>[23:16]</bitRange>
1305              <access>read-only</access>
1306            </field>
1307          </fields>
1308        </register>
1309        <register>
1310          <name>STSR</name>
1311          <description>Stored Status Register</description>
1312          <addressOffset>0x18</addressOffset>
1313          <size>32</size>
1314          <access>read-only</access>
1315          <resetValue>0x0</resetValue>
1316          <resetMask>0xFF</resetMask>
1317          <fields>
1318            <field>
1319              <name>STORED_DEVDENY</name>
1320              <description>N/A</description>
1321              <bitRange>[7:0]</bitRange>
1322              <access>read-only</access>
1323            </field>
1324          </fields>
1325        </register>
1326        <register>
1327          <name>UNLK</name>
1328          <description>Unlock register</description>
1329          <addressOffset>0x1C</addressOffset>
1330          <size>32</size>
1331          <access>read-write</access>
1332          <resetValue>0x0</resetValue>
1333          <resetMask>0x1</resetMask>
1334          <fields>
1335            <field>
1336              <name>UNLOCK</name>
1337              <description>N/A</description>
1338              <bitRange>[0:0]</bitRange>
1339              <access>read-write</access>
1340            </field>
1341          </fields>
1342        </register>
1343        <register>
1344          <name>PWCR</name>
1345          <description>Power Configuration Register</description>
1346          <addressOffset>0x20</addressOffset>
1347          <size>32</size>
1348          <access>read-write</access>
1349          <resetValue>0x101</resetValue>
1350          <resetMask>0xFF07FFFF</resetMask>
1351          <fields>
1352            <field>
1353              <name>DEVREQEN</name>
1354              <description>When set to 1 enables the device interface handshake for transitions.  All available bits are reset to 1.
1355
1356There is one bit for each device interface channel.  For example, bit 0 is for Q-Channel 0, and bit 1 is for Q-Channel 1.  Refer to PPU_IDR0.DEVCHAN for device channel enumeration.</description>
1357              <bitRange>[7:0]</bitRange>
1358              <access>read-write</access>
1359            </field>
1360            <field>
1361              <name>PWR_DEVACTIVEEN</name>
1362              <description>These bits enable the power mode DEVACTIVE inputs.  When a bit is to 1 the related DEVACTIVE input is enabled, when set to 0 it is disabled.  All available bits are reset to 1.
1363
1364There is one bit for each device interface Q-Channel DEVQACTIVE.  For example, bit 8 is for the Q-Channel 0 DEVQACTIVE, and bit 9 for the Q-Channel 1 DEVQACTIVE.  Refer to PPU_IDR0.DEVCHAN for device channel enumeration.</description>
1365              <bitRange>[18:8]</bitRange>
1366              <access>read-write</access>
1367            </field>
1368            <field>
1369              <name>OP_DEVACTIVEEN</name>
1370              <description>N/A</description>
1371              <bitRange>[31:24]</bitRange>
1372              <access>read-write</access>
1373            </field>
1374          </fields>
1375        </register>
1376        <register>
1377          <name>PTCR</name>
1378          <description>Power Mode Transition Configuration Register</description>
1379          <addressOffset>0x24</addressOffset>
1380          <size>32</size>
1381          <access>read-write</access>
1382          <resetValue>0x0</resetValue>
1383          <resetMask>0x3</resetMask>
1384          <fields>
1385            <field>
1386              <name>WARM_RST_DEVREQEN</name>
1387              <description>Transition behavior between ON and WARM_RST.  This bit should not be modified when the PPU is in WARM_RST, or if the PPU is performing a transition, otherwise PPU behavior is UNPREDICTABLE.
13880:  The PPU does not perform a device interface handshake when transitioning between ON and WARM_RST.
13891:  The PPU performs a device interface handshake when transitioning between ON and WARM_RST.  This disables all Q-Channels for this transition.</description>
1390              <bitRange>[0:0]</bitRange>
1391              <access>read-write</access>
1392            </field>
1393            <field>
1394              <name>DBG_RECOV_PORST_EN</name>
1395              <description>N/A</description>
1396              <bitRange>[1:1]</bitRange>
1397              <access>read-write</access>
1398            </field>
1399          </fields>
1400        </register>
1401        <register>
1402          <name>IMR</name>
1403          <description>Interrupt Mask Register</description>
1404          <addressOffset>0x30</addressOffset>
1405          <size>32</size>
1406          <access>read-write</access>
1407          <resetValue>0x3A</resetValue>
1408          <resetMask>0x3F</resetMask>
1409          <fields>
1410            <field>
1411              <name>STA_POLICY_TRN_IRQ_MASK</name>
1412              <description>Static full policy transition completion event mask.</description>
1413              <bitRange>[0:0]</bitRange>
1414              <access>read-write</access>
1415            </field>
1416            <field>
1417              <name>STA_ACCEPT_IRQ_MASK</name>
1418              <description>Static transition acceptance event mask.</description>
1419              <bitRange>[1:1]</bitRange>
1420              <access>read-write</access>
1421            </field>
1422            <field>
1423              <name>STA_DENY_IRQ_MASK</name>
1424              <description>Static transition denial event mask.</description>
1425              <bitRange>[2:2]</bitRange>
1426              <access>read-write</access>
1427            </field>
1428            <field>
1429              <name>EMU_ACCEPT_IRQ_MASK</name>
1430              <description>N/A</description>
1431              <bitRange>[3:3]</bitRange>
1432              <access>read-write</access>
1433            </field>
1434            <field>
1435              <name>EMU_DENY_IRQ_MASK</name>
1436              <description>N/A</description>
1437              <bitRange>[4:4]</bitRange>
1438              <access>read-write</access>
1439            </field>
1440            <field>
1441              <name>LOCKED_IRQ_MASK</name>
1442              <description>N/A</description>
1443              <bitRange>[5:5]</bitRange>
1444              <access>read-write</access>
1445            </field>
1446          </fields>
1447        </register>
1448        <register>
1449          <name>AIMR</name>
1450          <description>Additional Interrupt Mask Register</description>
1451          <addressOffset>0x34</addressOffset>
1452          <size>32</size>
1453          <access>read-write</access>
1454          <resetValue>0x1E</resetValue>
1455          <resetMask>0x1F</resetMask>
1456          <fields>
1457            <field>
1458              <name>UNSPT_POLICY_IRQ_MASK</name>
1459              <description>Unsupported Policy event mask.</description>
1460              <bitRange>[0:0]</bitRange>
1461              <access>read-write</access>
1462            </field>
1463            <field>
1464              <name>DYN_ACCEPT_IRQ_MASK</name>
1465              <description>Dynamic transition acceptance event mask.</description>
1466              <bitRange>[1:1]</bitRange>
1467              <access>read-write</access>
1468            </field>
1469            <field>
1470              <name>DYN_DENY_IRQ_MASK</name>
1471              <description>Dynamic transition denial event mask.</description>
1472              <bitRange>[2:2]</bitRange>
1473              <access>read-write</access>
1474            </field>
1475            <field>
1476              <name>STA_POLICY_PWR_IRQ_MASK</name>
1477              <description>N/A</description>
1478              <bitRange>[3:3]</bitRange>
1479              <access>read-write</access>
1480            </field>
1481            <field>
1482              <name>STA_POLICY_OP_IRQ_MASK</name>
1483              <description>N/A</description>
1484              <bitRange>[4:4]</bitRange>
1485              <access>read-write</access>
1486            </field>
1487          </fields>
1488        </register>
1489        <register>
1490          <name>ISR</name>
1491          <description>Interrupt Status Register</description>
1492          <addressOffset>0x38</addressOffset>
1493          <size>32</size>
1494          <access>read-write</access>
1495          <resetValue>0x0</resetValue>
1496          <resetMask>0xFF07FFBF</resetMask>
1497          <fields>
1498            <field>
1499              <name>STA_POLICY_TRN_IRQ</name>
1500              <description>Static full policy transition completion event status.</description>
1501              <bitRange>[0:0]</bitRange>
1502              <access>read-write</access>
1503            </field>
1504            <field>
1505              <name>STA_ACCEPT_IRQ</name>
1506              <description>Static transition acceptance event status.</description>
1507              <bitRange>[1:1]</bitRange>
1508              <access>read-write</access>
1509            </field>
1510            <field>
1511              <name>STA_DENY_IRQ</name>
1512              <description>Static transition denial event status.</description>
1513              <bitRange>[2:2]</bitRange>
1514              <access>read-write</access>
1515            </field>
1516            <field>
1517              <name>EMU_ACCEPT_IRQ</name>
1518              <description>N/A</description>
1519              <bitRange>[3:3]</bitRange>
1520              <access>read-write</access>
1521            </field>
1522            <field>
1523              <name>EMU_DENY_IRQ</name>
1524              <description>N/A</description>
1525              <bitRange>[4:4]</bitRange>
1526              <access>read-write</access>
1527            </field>
1528            <field>
1529              <name>LOCKED_IRQ</name>
1530              <description>N/A</description>
1531              <bitRange>[5:5]</bitRange>
1532              <access>read-write</access>
1533            </field>
1534            <field>
1535              <name>OTHER_IRQ</name>
1536              <description>Indicates there is an interrupt event pending in the Additional Interrupt Status Register (PPU_AISR).</description>
1537              <bitRange>[7:7]</bitRange>
1538              <access>read-only</access>
1539            </field>
1540            <field>
1541              <name>PWR_ACTIVE_EDGE_IRQ</name>
1542              <description>N/A</description>
1543              <bitRange>[18:8]</bitRange>
1544              <access>read-write</access>
1545            </field>
1546            <field>
1547              <name>OP_ACTIVE_EDGE_IRQ</name>
1548              <description>N/A</description>
1549              <bitRange>[31:24]</bitRange>
1550              <access>read-write</access>
1551            </field>
1552          </fields>
1553        </register>
1554        <register>
1555          <name>AISR</name>
1556          <description>Additional Interrupt Status Register</description>
1557          <addressOffset>0x3C</addressOffset>
1558          <size>32</size>
1559          <access>read-write</access>
1560          <resetValue>0x0</resetValue>
1561          <resetMask>0x1F</resetMask>
1562          <fields>
1563            <field>
1564              <name>UNSPT_POLICY_IRQ</name>
1565              <description>Unsupported Policy event status.</description>
1566              <bitRange>[0:0]</bitRange>
1567              <access>read-write</access>
1568            </field>
1569            <field>
1570              <name>DYN_ACCEPT_IRQ</name>
1571              <description>Dynamic transition acceptance event status.</description>
1572              <bitRange>[1:1]</bitRange>
1573              <access>read-write</access>
1574            </field>
1575            <field>
1576              <name>DYN_DENY_IRQ</name>
1577              <description>Dynamic transition denial event status.</description>
1578              <bitRange>[2:2]</bitRange>
1579              <access>read-write</access>
1580            </field>
1581            <field>
1582              <name>STA_POLICY_PWR_IRQ</name>
1583              <description>N/A</description>
1584              <bitRange>[3:3]</bitRange>
1585              <access>read-write</access>
1586            </field>
1587            <field>
1588              <name>STA_POLICY_OP_IRQ</name>
1589              <description>N/A</description>
1590              <bitRange>[4:4]</bitRange>
1591              <access>read-write</access>
1592            </field>
1593          </fields>
1594        </register>
1595        <register>
1596          <name>IESR</name>
1597          <description>Input Edge Sensitivity Register</description>
1598          <addressOffset>0x40</addressOffset>
1599          <size>32</size>
1600          <access>read-write</access>
1601          <resetValue>0x0</resetValue>
1602          <resetMask>0x3FFFFF</resetMask>
1603          <fields>
1604            <field>
1605              <name>DEVACTIVE00_EDGE</name>
1606              <description>DEVACTIVE 0 edge sensitivity.</description>
1607              <bitRange>[1:0]</bitRange>
1608              <access>read-write</access>
1609            </field>
1610            <field>
1611              <name>DEVACTIVE01_EDGE</name>
1612              <description>N/A</description>
1613              <bitRange>[3:2]</bitRange>
1614              <access>read-write</access>
1615            </field>
1616            <field>
1617              <name>DEVACTIVE02_EDGE</name>
1618              <description>N/A</description>
1619              <bitRange>[5:4]</bitRange>
1620              <access>read-write</access>
1621            </field>
1622            <field>
1623              <name>DEVACTIVE03_EDGE</name>
1624              <description>N/A</description>
1625              <bitRange>[7:6]</bitRange>
1626              <access>read-write</access>
1627            </field>
1628            <field>
1629              <name>DEVACTIVE04_EDGE</name>
1630              <description>N/A</description>
1631              <bitRange>[9:8]</bitRange>
1632              <access>read-write</access>
1633            </field>
1634            <field>
1635              <name>DEVACTIVE05_EDGE</name>
1636              <description>N/A</description>
1637              <bitRange>[11:10]</bitRange>
1638              <access>read-write</access>
1639            </field>
1640            <field>
1641              <name>DEVACTIVE06_EDGE</name>
1642              <description>N/A</description>
1643              <bitRange>[13:12]</bitRange>
1644              <access>read-write</access>
1645            </field>
1646            <field>
1647              <name>DEVACTIVE07_EDGE</name>
1648              <description>N/A</description>
1649              <bitRange>[15:14]</bitRange>
1650              <access>read-write</access>
1651            </field>
1652            <field>
1653              <name>DEVACTIVE08_EDGE</name>
1654              <description>N/A</description>
1655              <bitRange>[17:16]</bitRange>
1656              <access>read-write</access>
1657            </field>
1658            <field>
1659              <name>DEVACTIVE09_EDGE</name>
1660              <description>N/A</description>
1661              <bitRange>[19:18]</bitRange>
1662              <access>read-write</access>
1663            </field>
1664            <field>
1665              <name>DEVACTIVE10_EDGE</name>
1666              <description>N/A</description>
1667              <bitRange>[21:20]</bitRange>
1668              <access>read-write</access>
1669            </field>
1670          </fields>
1671        </register>
1672        <register>
1673          <name>OPSR</name>
1674          <description>Operating Mode Active Edge Sensitivity Register</description>
1675          <addressOffset>0x44</addressOffset>
1676          <size>32</size>
1677          <access>read-write</access>
1678          <resetValue>0x0</resetValue>
1679          <resetMask>0xFFFF</resetMask>
1680          <fields>
1681            <field>
1682              <name>DEVACTIVE16_EDGE</name>
1683              <description>N/A</description>
1684              <bitRange>[1:0]</bitRange>
1685              <access>read-write</access>
1686            </field>
1687            <field>
1688              <name>DEVACTIVE17_EDGE</name>
1689              <description>N/A</description>
1690              <bitRange>[3:2]</bitRange>
1691              <access>read-write</access>
1692            </field>
1693            <field>
1694              <name>DEVACTIVE18_EDGE</name>
1695              <description>N/A</description>
1696              <bitRange>[5:4]</bitRange>
1697              <access>read-write</access>
1698            </field>
1699            <field>
1700              <name>DEVACTIVE19_EDGE</name>
1701              <description>N/A</description>
1702              <bitRange>[7:6]</bitRange>
1703              <access>read-write</access>
1704            </field>
1705            <field>
1706              <name>DEVACTIVE20_EDGE</name>
1707              <description>N/A</description>
1708              <bitRange>[9:8]</bitRange>
1709              <access>read-write</access>
1710            </field>
1711            <field>
1712              <name>DEVACTIVE21_EDGE</name>
1713              <description>N/A</description>
1714              <bitRange>[11:10]</bitRange>
1715              <access>read-write</access>
1716            </field>
1717            <field>
1718              <name>DEVACTIVE22_EDGE</name>
1719              <description>N/A</description>
1720              <bitRange>[13:12]</bitRange>
1721              <access>read-write</access>
1722            </field>
1723            <field>
1724              <name>DEVACTIVE23_EDGE</name>
1725              <description>N/A</description>
1726              <bitRange>[15:14]</bitRange>
1727              <access>read-write</access>
1728            </field>
1729          </fields>
1730        </register>
1731        <register>
1732          <name>FUNRR</name>
1733          <description>Functional Retention RAM Configuration Register</description>
1734          <addressOffset>0x50</addressOffset>
1735          <size>32</size>
1736          <access>read-write</access>
1737          <resetValue>0x0</resetValue>
1738          <resetMask>0xFF</resetMask>
1739          <fields>
1740            <field>
1741              <name>FUNC_RET_RAM_CFG</name>
1742              <description>N/A</description>
1743              <bitRange>[7:0]</bitRange>
1744              <access>read-write</access>
1745            </field>
1746          </fields>
1747        </register>
1748        <register>
1749          <name>FULRR</name>
1750          <description>Full Retention RAM Configuration Register</description>
1751          <addressOffset>0x54</addressOffset>
1752          <size>32</size>
1753          <access>read-write</access>
1754          <resetValue>0x0</resetValue>
1755          <resetMask>0xFF</resetMask>
1756          <fields>
1757            <field>
1758              <name>FULL_RET_RAM_CFG</name>
1759              <description>N/A</description>
1760              <bitRange>[7:0]</bitRange>
1761              <access>read-write</access>
1762            </field>
1763          </fields>
1764        </register>
1765        <register>
1766          <name>MEMRR</name>
1767          <description>Memory Retention RAM Configuration Register</description>
1768          <addressOffset>0x58</addressOffset>
1769          <size>32</size>
1770          <access>read-write</access>
1771          <resetValue>0x0</resetValue>
1772          <resetMask>0xFF</resetMask>
1773          <fields>
1774            <field>
1775              <name>MEM_RET_RAM_CFG</name>
1776              <description>N/A</description>
1777              <bitRange>[7:0]</bitRange>
1778              <access>read-write</access>
1779            </field>
1780          </fields>
1781        </register>
1782        <register>
1783          <name>EDTR0</name>
1784          <description>Power Mode Entry Delay Register 0</description>
1785          <addressOffset>0x160</addressOffset>
1786          <size>32</size>
1787          <access>read-write</access>
1788          <resetValue>0x0</resetValue>
1789          <resetMask>0xFFFFFFFF</resetMask>
1790          <fields>
1791            <field>
1792              <name>OFF_DEL</name>
1793              <description>N/A</description>
1794              <bitRange>[7:0]</bitRange>
1795              <access>read-write</access>
1796            </field>
1797            <field>
1798              <name>MEM_RET_DEL</name>
1799              <description>N/A</description>
1800              <bitRange>[15:8]</bitRange>
1801              <access>read-write</access>
1802            </field>
1803            <field>
1804              <name>LOGIC_RET_DEL</name>
1805              <description>N/A</description>
1806              <bitRange>[23:16]</bitRange>
1807              <access>read-write</access>
1808            </field>
1809            <field>
1810              <name>FULL_RET_DEL</name>
1811              <description>N/A</description>
1812              <bitRange>[31:24]</bitRange>
1813              <access>read-write</access>
1814            </field>
1815          </fields>
1816        </register>
1817        <register>
1818          <name>EDTR1</name>
1819          <description>Power Mode Entry Delay Register 1</description>
1820          <addressOffset>0x164</addressOffset>
1821          <size>32</size>
1822          <access>read-write</access>
1823          <resetValue>0x0</resetValue>
1824          <resetMask>0xFFFF</resetMask>
1825          <fields>
1826            <field>
1827              <name>MEM_OFF_DEL</name>
1828              <description>N/A</description>
1829              <bitRange>[7:0]</bitRange>
1830              <access>read-write</access>
1831            </field>
1832            <field>
1833              <name>FUNC_RET_DEL</name>
1834              <description>N/A</description>
1835              <bitRange>[15:8]</bitRange>
1836              <access>read-write</access>
1837            </field>
1838          </fields>
1839        </register>
1840        <register>
1841          <name>DCDR0</name>
1842          <description>Device Control Delay Configuration Register 0</description>
1843          <addressOffset>0x170</addressOffset>
1844          <size>32</size>
1845          <access>read-only</access>
1846          <resetValue>0x0</resetValue>
1847          <resetMask>0xFFFFFF</resetMask>
1848          <fields>
1849            <field>
1850              <name>CLKEN_RST_DLY</name>
1851              <description>N/A</description>
1852              <bitRange>[7:0]</bitRange>
1853              <access>read-only</access>
1854            </field>
1855            <field>
1856              <name>ISO_CLKEN_DLY</name>
1857              <description>N/A</description>
1858              <bitRange>[15:8]</bitRange>
1859              <access>read-only</access>
1860            </field>
1861            <field>
1862              <name>RST_HWSTAT_DLY</name>
1863              <description>N/A</description>
1864              <bitRange>[23:16]</bitRange>
1865              <access>read-only</access>
1866            </field>
1867          </fields>
1868        </register>
1869        <register>
1870          <name>DCDR1</name>
1871          <description>Device Control Delay Configuration Register 1</description>
1872          <addressOffset>0x174</addressOffset>
1873          <size>32</size>
1874          <access>read-only</access>
1875          <resetValue>0x0</resetValue>
1876          <resetMask>0xFFFF</resetMask>
1877          <fields>
1878            <field>
1879              <name>ISO_RST_DLY</name>
1880              <description>N/A</description>
1881              <bitRange>[7:0]</bitRange>
1882              <access>read-only</access>
1883            </field>
1884            <field>
1885              <name>CLKEN_ISO_DLY</name>
1886              <description>N/A</description>
1887              <bitRange>[15:8]</bitRange>
1888              <access>read-only</access>
1889            </field>
1890          </fields>
1891        </register>
1892        <register>
1893          <name>IDR0</name>
1894          <description>PPU Identification Register 0</description>
1895          <addressOffset>0xFB0</addressOffset>
1896          <size>32</size>
1897          <access>read-only</access>
1898          <resetValue>0x10530501</resetValue>
1899          <resetMask>0x3FF7FFFF</resetMask>
1900          <fields>
1901            <field>
1902              <name>DEVCHAN</name>
1903              <description>No. of Device Interface Channels.  The device enumeration is:
1904Device 0: PDCM</description>
1905              <bitRange>[3:0]</bitRange>
1906              <access>read-only</access>
1907            </field>
1908            <field>
1909              <name>NUM_OPMODE</name>
1910              <description>No. of operating modes supported is NUM_OPMODE + 1.</description>
1911              <bitRange>[7:4]</bitRange>
1912              <access>read-only</access>
1913            </field>
1914            <field>
1915              <name>STA_OFF_SPT</name>
1916              <description>OFF support.</description>
1917              <bitRange>[8:8]</bitRange>
1918              <access>read-only</access>
1919            </field>
1920            <field>
1921              <name>STA_OFF_EMU_SPT</name>
1922              <description>OFF_EMU support.</description>
1923              <bitRange>[9:9]</bitRange>
1924              <access>read-only</access>
1925            </field>
1926            <field>
1927              <name>STA_MEM_RET_SPT</name>
1928              <description>MEM_RET support.</description>
1929              <bitRange>[10:10]</bitRange>
1930              <access>read-only</access>
1931            </field>
1932            <field>
1933              <name>STA_MEM_RET_EMU_SPT</name>
1934              <description>MEM_RET_EMU support.</description>
1935              <bitRange>[11:11]</bitRange>
1936              <access>read-only</access>
1937            </field>
1938            <field>
1939              <name>STA_LGC_RET_SPT</name>
1940              <description>LOGIC_RET support.</description>
1941              <bitRange>[12:12]</bitRange>
1942              <access>read-only</access>
1943            </field>
1944            <field>
1945              <name>STA_MEM_OFF_SPT</name>
1946              <description>MEM_OFF support.</description>
1947              <bitRange>[13:13]</bitRange>
1948              <access>read-only</access>
1949            </field>
1950            <field>
1951              <name>STA_FULL_RET_SPT</name>
1952              <description>FULL_RET support.</description>
1953              <bitRange>[14:14]</bitRange>
1954              <access>read-only</access>
1955            </field>
1956            <field>
1957              <name>STA_FUNC_RET_SPT</name>
1958              <description>FUNC_RET support.</description>
1959              <bitRange>[15:15]</bitRange>
1960              <access>read-only</access>
1961            </field>
1962            <field>
1963              <name>STA_ON_SPT</name>
1964              <description>ON support.</description>
1965              <bitRange>[16:16]</bitRange>
1966              <access>read-only</access>
1967            </field>
1968            <field>
1969              <name>STA_WRM_RST_SPT</name>
1970              <description>WARM_RST support.  Ignore this bit.  Do not use WARM_RST.</description>
1971              <bitRange>[17:17]</bitRange>
1972              <access>read-only</access>
1973            </field>
1974            <field>
1975              <name>STA_DBG_RECOV_SPT</name>
1976              <description>DBG_RECOV support.</description>
1977              <bitRange>[18:18]</bitRange>
1978              <access>read-only</access>
1979            </field>
1980            <field>
1981              <name>DYN_OFF_SPT</name>
1982              <description>Dynamic OFF support.</description>
1983              <bitRange>[20:20]</bitRange>
1984              <access>read-only</access>
1985            </field>
1986            <field>
1987              <name>DYN_OFF_EMU_SPT</name>
1988              <description>Dynamic OFF_EMU support.</description>
1989              <bitRange>[21:21]</bitRange>
1990              <access>read-only</access>
1991            </field>
1992            <field>
1993              <name>DYN_MEM_RET_SPT</name>
1994              <description>Dynamic MEM_RET support.</description>
1995              <bitRange>[22:22]</bitRange>
1996              <access>read-only</access>
1997            </field>
1998            <field>
1999              <name>DYN_MEM_RET_EMU_SPT</name>
2000              <description>Dynamic MEM_RET_EMU support</description>
2001              <bitRange>[23:23]</bitRange>
2002              <access>read-only</access>
2003            </field>
2004            <field>
2005              <name>DYN_LGC_RET_SPT</name>
2006              <description>Dynamic LOGIC_RET support.</description>
2007              <bitRange>[24:24]</bitRange>
2008              <access>read-only</access>
2009            </field>
2010            <field>
2011              <name>DYN_MEM_OFF_SPT</name>
2012              <description>Dynamic MEM_OFF support.</description>
2013              <bitRange>[25:25]</bitRange>
2014              <access>read-only</access>
2015            </field>
2016            <field>
2017              <name>DYN_FULL_RET_SPT</name>
2018              <description>Dynamic FULL_RET support.</description>
2019              <bitRange>[26:26]</bitRange>
2020              <access>read-only</access>
2021            </field>
2022            <field>
2023              <name>DYN_FUNC_RET_SPT</name>
2024              <description>Dynamic FUNC_RET support.</description>
2025              <bitRange>[27:27]</bitRange>
2026              <access>read-only</access>
2027            </field>
2028            <field>
2029              <name>DYN_ON_SPT</name>
2030              <description>Dynamic ON support.</description>
2031              <bitRange>[28:28]</bitRange>
2032              <access>read-only</access>
2033            </field>
2034            <field>
2035              <name>DYN_WRM_RST_SPT</name>
2036              <description>Dynamic WARM_RST support.</description>
2037              <bitRange>[29:29]</bitRange>
2038              <access>read-only</access>
2039            </field>
2040          </fields>
2041        </register>
2042        <register>
2043          <name>IDR1</name>
2044          <description>PPU Identification Register 1</description>
2045          <addressOffset>0xFB4</addressOffset>
2046          <size>32</size>
2047          <access>read-only</access>
2048          <resetValue>0x0</resetValue>
2049          <resetMask>0x1777</resetMask>
2050          <fields>
2051            <field>
2052              <name>PWR_MODE_ENTRY_DEL_SPT</name>
2053              <description>Power mode entry delay support.</description>
2054              <bitRange>[0:0]</bitRange>
2055              <access>read-only</access>
2056            </field>
2057            <field>
2058              <name>SW_DEV_DEL_SPT</name>
2059              <description>Software device delay control configuration support.</description>
2060              <bitRange>[1:1]</bitRange>
2061              <access>read-only</access>
2062            </field>
2063            <field>
2064              <name>LOCK_SPT</name>
2065              <description>Lock and the lock interrupt event are supported.</description>
2066              <bitRange>[2:2]</bitRange>
2067              <access>read-only</access>
2068            </field>
2069            <field>
2070              <name>MEM_RET_RAM_REG</name>
2071              <description>N/A</description>
2072              <bitRange>[4:4]</bitRange>
2073              <access>read-only</access>
2074            </field>
2075            <field>
2076              <name>FULL_RET_RAM_REG</name>
2077              <description>N/A</description>
2078              <bitRange>[5:5]</bitRange>
2079              <access>read-only</access>
2080            </field>
2081            <field>
2082              <name>FUNC_RET_RAM_REG</name>
2083              <description>N/A</description>
2084              <bitRange>[6:6]</bitRange>
2085              <access>read-only</access>
2086            </field>
2087            <field>
2088              <name>STA_POLICY_PWR_IRQ_SPT</name>
2089              <description>Power policy transition completion event status.</description>
2090              <bitRange>[8:8]</bitRange>
2091              <access>read-only</access>
2092            </field>
2093            <field>
2094              <name>STA_POLICY_OP_IRQ_SPT</name>
2095              <description>Operating policy transition completion event status.</description>
2096              <bitRange>[9:9]</bitRange>
2097              <access>read-only</access>
2098            </field>
2099            <field>
2100              <name>OP_ACTIVE</name>
2101              <description>N/A</description>
2102              <bitRange>[10:10]</bitRange>
2103              <access>read-only</access>
2104            </field>
2105            <field>
2106              <name>OFF_MEM_RET_TRANS</name>
2107              <description>OFF to MEM_RET direct transition.  Indicates if direct transitions from OFF to MEM_RET and from OFF_EMU to MEM_RET_EMU are supported.</description>
2108              <bitRange>[12:12]</bitRange>
2109              <access>read-only</access>
2110            </field>
2111          </fields>
2112        </register>
2113        <register>
2114          <name>IIDR</name>
2115          <description>Implementation Identification Register</description>
2116          <addressOffset>0xFC8</addressOffset>
2117          <size>32</size>
2118          <access>read-only</access>
2119          <resetValue>0xB50043B</resetValue>
2120          <resetMask>0xFFFFFFFF</resetMask>
2121          <fields>
2122            <field>
2123              <name>IMPLEMENTER</name>
2124              <description>Implementer identification.  [11:8] The JEP106 continuation code of the implementer.  [7] Always 0.  [6:0] The JEP106 identity code of the implementer.  For an Arm implementation, bits [11:0] are 0x43B.</description>
2125              <bitRange>[11:0]</bitRange>
2126              <access>read-only</access>
2127            </field>
2128            <field>
2129              <name>REVISION</name>
2130              <description>Minor revision of the product.</description>
2131              <bitRange>[15:12]</bitRange>
2132              <access>read-only</access>
2133            </field>
2134            <field>
2135              <name>VARIANT</name>
2136              <description>Major revision of the product.</description>
2137              <bitRange>[19:16]</bitRange>
2138              <access>read-only</access>
2139            </field>
2140            <field>
2141              <name>PRODUCT_ID</name>
2142              <description>PPU part identification.</description>
2143              <bitRange>[31:20]</bitRange>
2144              <access>read-only</access>
2145            </field>
2146          </fields>
2147        </register>
2148        <register>
2149          <name>AIDR</name>
2150          <description>Architecture Identification Register</description>
2151          <addressOffset>0xFCC</addressOffset>
2152          <size>32</size>
2153          <access>read-only</access>
2154          <resetValue>0x11</resetValue>
2155          <resetMask>0xFF</resetMask>
2156          <fields>
2157            <field>
2158              <name>ARCH_REV_MINOR</name>
2159              <description>N/A</description>
2160              <bitRange>[3:0]</bitRange>
2161              <access>read-only</access>
2162            </field>
2163            <field>
2164              <name>ARCH_REV_MAJOR</name>
2165              <description>N/A</description>
2166              <bitRange>[7:4]</bitRange>
2167              <access>read-only</access>
2168            </field>
2169          </fields>
2170        </register>
2171        <register>
2172          <name>PID4</name>
2173          <description>Implementation Defined Identification Register (PID4)</description>
2174          <addressOffset>0xFD0</addressOffset>
2175          <size>32</size>
2176          <access>read-only</access>
2177          <resetValue>0x4</resetValue>
2178          <resetMask>0xF</resetMask>
2179          <fields>
2180            <field>
2181              <name>IMPLEMENTER_11_8</name>
2182              <description>The JEP106 continuation code of the implementer, which is 0x4 hardcoded value.</description>
2183              <bitRange>[3:0]</bitRange>
2184              <access>read-only</access>
2185            </field>
2186          </fields>
2187        </register>
2188        <register>
2189          <name>PID0</name>
2190          <description>Implementation Defined Identification Register (PID0)</description>
2191          <addressOffset>0xFE0</addressOffset>
2192          <size>32</size>
2193          <access>read-only</access>
2194          <resetValue>0xB5</resetValue>
2195          <resetMask>0xFF</resetMask>
2196          <fields>
2197            <field>
2198              <name>PRODUCT_ID_7_0</name>
2199              <description>PPU part identification bits [7:0].</description>
2200              <bitRange>[7:0]</bitRange>
2201              <access>read-only</access>
2202            </field>
2203          </fields>
2204        </register>
2205        <register>
2206          <name>PID1</name>
2207          <description>Implementation Defined Identification Register (PID1)</description>
2208          <addressOffset>0xFE4</addressOffset>
2209          <size>32</size>
2210          <access>read-only</access>
2211          <resetValue>0xB0</resetValue>
2212          <resetMask>0xFF</resetMask>
2213          <fields>
2214            <field>
2215              <name>PRODUCT_ID_11_8</name>
2216              <description>PPU part identification bits [11:8]</description>
2217              <bitRange>[3:0]</bitRange>
2218              <access>read-only</access>
2219            </field>
2220            <field>
2221              <name>IMPLEMENTER_3_0</name>
2222              <description>JEP106_ID bits [3:0]</description>
2223              <bitRange>[7:4]</bitRange>
2224              <access>read-only</access>
2225            </field>
2226          </fields>
2227        </register>
2228        <register>
2229          <name>PID2</name>
2230          <description>Implementation Defined Identification Register (PID2)</description>
2231          <addressOffset>0xFE8</addressOffset>
2232          <size>32</size>
2233          <access>read-only</access>
2234          <resetValue>0xB</resetValue>
2235          <resetMask>0xFF</resetMask>
2236          <fields>
2237            <field>
2238              <name>IMPLEMENTER_6_4</name>
2239              <description>JEP106_ID bits [6:4]</description>
2240              <bitRange>[2:0]</bitRange>
2241              <access>read-only</access>
2242            </field>
2243            <field>
2244              <name>CONST_HIGH</name>
2245              <description>Constant HIGH</description>
2246              <bitRange>[3:3]</bitRange>
2247              <access>read-only</access>
2248            </field>
2249            <field>
2250              <name>REV_CONST</name>
2251              <description>Constant LOW  Revision (4 bits)</description>
2252              <bitRange>[7:4]</bitRange>
2253              <access>read-only</access>
2254            </field>
2255          </fields>
2256        </register>
2257        <register>
2258          <name>PID3</name>
2259          <description>Implementation Defined Identification Register (PID3)</description>
2260          <addressOffset>0xFEC</addressOffset>
2261          <size>32</size>
2262          <access>read-only</access>
2263          <resetValue>0x0</resetValue>
2264          <resetMask>0xFF</resetMask>
2265          <fields>
2266            <field>
2267              <name>PID3_REV_CONST</name>
2268              <description>Constant LOW (4 bits)</description>
2269              <bitRange>[3:0]</bitRange>
2270              <access>read-only</access>
2271            </field>
2272            <field>
2273              <name>PID3_REVISION</name>
2274              <description>Minor revision of the product.</description>
2275              <bitRange>[7:4]</bitRange>
2276              <access>read-only</access>
2277            </field>
2278          </fields>
2279        </register>
2280        <register>
2281          <name>ID0</name>
2282          <description>Implementation Defined Identification Register (ID0)</description>
2283          <addressOffset>0xFF0</addressOffset>
2284          <size>32</size>
2285          <access>read-only</access>
2286          <resetValue>0xD</resetValue>
2287          <resetMask>0xFF</resetMask>
2288          <fields>
2289            <field>
2290              <name>ID0</name>
2291              <description>ID0 hard coded value</description>
2292              <bitRange>[7:0]</bitRange>
2293              <access>read-only</access>
2294            </field>
2295          </fields>
2296        </register>
2297        <register>
2298          <name>ID1</name>
2299          <description>Implementation Defined Identification Register (ID1)</description>
2300          <addressOffset>0xFF4</addressOffset>
2301          <size>32</size>
2302          <access>read-only</access>
2303          <resetValue>0xF0</resetValue>
2304          <resetMask>0xFF</resetMask>
2305          <fields>
2306            <field>
2307              <name>ID1</name>
2308              <description>ID1 hardcoded value</description>
2309              <bitRange>[7:0]</bitRange>
2310              <access>read-only</access>
2311            </field>
2312          </fields>
2313        </register>
2314        <register>
2315          <name>ID2</name>
2316          <description>Implementation Defined Identification Register (ID2)</description>
2317          <addressOffset>0xFF8</addressOffset>
2318          <size>32</size>
2319          <access>read-only</access>
2320          <resetValue>0x5</resetValue>
2321          <resetMask>0xFF</resetMask>
2322          <fields>
2323            <field>
2324              <name>ID2</name>
2325              <description>ID2 hardcoded value</description>
2326              <bitRange>[7:0]</bitRange>
2327              <access>read-only</access>
2328            </field>
2329          </fields>
2330        </register>
2331        <register>
2332          <name>ID3</name>
2333          <description>Implementation Defined Identification Register (ID3)</description>
2334          <addressOffset>0xFFC</addressOffset>
2335          <size>32</size>
2336          <access>read-only</access>
2337          <resetValue>0xB1</resetValue>
2338          <resetMask>0xFF</resetMask>
2339          <fields>
2340            <field>
2341              <name>ID3</name>
2342              <description>ID3 hardcoded value</description>
2343              <bitRange>[7:0]</bitRange>
2344              <access>read-only</access>
2345            </field>
2346          </fields>
2347        </register>
2348      </registers>
2349    </peripheral>
2350    <peripheral derivedFrom="RAMC_PPU0">
2351      <name>RAMC_PPU1</name>
2352      <baseAddress>0x40101000</baseAddress>
2353    </peripheral>
2354    <peripheral derivedFrom="RAMC_PPU0">
2355      <name>RAMC_PPU2</name>
2356      <baseAddress>0x40102000</baseAddress>
2357    </peripheral>
2358    <peripheral>
2359      <name>ICACHE0</name>
2360      <description>CM33_0/1 CA APB interface</description>
2361      <headerStructName>ICACHE</headerStructName>
2362      <baseAddress>0x40103000</baseAddress>
2363      <addressBlock>
2364        <offset>0</offset>
2365        <size>4096</size>
2366        <usage>registers</usage>
2367      </addressBlock>
2368      <registers>
2369        <register>
2370          <name>CTL</name>
2371          <description>Cache control</description>
2372          <addressOffset>0x0</addressOffset>
2373          <size>32</size>
2374          <access>read-write</access>
2375          <resetValue>0xC0000001</resetValue>
2376          <resetMask>0xDF030003</resetMask>
2377          <fields>
2378            <field>
2379              <name>ECC_EN</name>
2380              <description>Enable ECC checking for cache accesses:
23810: Disabled.
23821: Enabled.</description>
2383              <bitRange>[0:0]</bitRange>
2384              <access>read-write</access>
2385            </field>
2386            <field>
2387              <name>ECC_INJ_EN</name>
2388              <description>Enable error injection for cache.
2389When '1', the parity (ECC_CTL.PARITY[6:0]) is used when a cache refill is done to the ECC_CTL.WORD_ADDR[23:0] word address.</description>
2390              <bitRange>[1:1]</bitRange>
2391              <access>read-write</access>
2392            </field>
2393            <field>
2394              <name>WAY</name>
2395              <description>Specifies the cache way for which cache information is provided in STATUS0/1/2.</description>
2396              <bitRange>[17:16]</bitRange>
2397              <access>read-write</access>
2398            </field>
2399            <field>
2400              <name>SET_ADDR</name>
2401              <description>Specifies the cache set for which cache information is provided in STATUS0/1/2.</description>
2402              <bitRange>[28:24]</bitRange>
2403              <access>read-write</access>
2404            </field>
2405            <field>
2406              <name>PREF_EN</name>
2407              <description>Prefetch enable:
24080: Disabled.
24091: Enabled.
2410
2411Prefetching requires the cache to be enabled; i.e. ENABLED is '1'.</description>
2412              <bitRange>[30:30]</bitRange>
2413              <access>read-write</access>
2414            </field>
2415            <field>
2416              <name>CA_EN</name>
2417              <description>Cache enable:
24180: Disabled. The cache tag valid bits are reset to '0's and the cache LRU information is set to '1's (making way 0 the LRU way and way 3 the MRU way).
24191: Enabled.</description>
2420              <bitRange>[31:31]</bitRange>
2421              <access>read-write</access>
2422            </field>
2423          </fields>
2424        </register>
2425        <register>
2426          <name>CMD</name>
2427          <description>Cache command</description>
2428          <addressOffset>0x8</addressOffset>
2429          <size>32</size>
2430          <access>read-write</access>
2431          <resetValue>0x0</resetValue>
2432          <resetMask>0x3</resetMask>
2433          <fields>
2434            <field>
2435              <name>INV</name>
2436              <description>Invalidation of cahce and buffer. SW writes a '1' to clear the caches. HW sets this field to '0' when the operation is completed. The caches' LRU structures are also reset to their default state.</description>
2437              <bitRange>[0:0]</bitRange>
2438              <access>read-write</access>
2439            </field>
2440            <field>
2441              <name>BUFF_INV</name>
2442              <description>Invalidation of  buffers (does not invalidate the caches). SW writes a '1' to clear the buffers. HW sets this field to '0' when the operation is completed.</description>
2443              <bitRange>[1:1]</bitRange>
2444              <access>read-write</access>
2445            </field>
2446          </fields>
2447        </register>
2448        <register>
2449          <name>STATUS0</name>
2450          <description>Cache status 0</description>
2451          <addressOffset>0x80</addressOffset>
2452          <size>32</size>
2453          <access>read-only</access>
2454          <resetValue>0x0</resetValue>
2455          <resetMask>0xFFFFFFFF</resetMask>
2456          <fields>
2457            <field>
2458              <name>VALID32</name>
2459              <description>Sixteen valid bits of the cache line specified by CTL.WAY and CTL.SET_ADDR.</description>
2460              <bitRange>[31:0]</bitRange>
2461              <access>read-only</access>
2462            </field>
2463          </fields>
2464        </register>
2465        <register>
2466          <name>STATUS1</name>
2467          <description>Cache status 1</description>
2468          <addressOffset>0x84</addressOffset>
2469          <size>32</size>
2470          <access>read-only</access>
2471          <resetValue>0x0</resetValue>
2472          <resetMask>0x0</resetMask>
2473          <fields>
2474            <field>
2475              <name>TAG</name>
2476              <description>Cache line address of the cache line specified by CTL.WAY and CTL.SET_ADDR.</description>
2477              <bitRange>[31:0]</bitRange>
2478              <access>read-only</access>
2479            </field>
2480          </fields>
2481        </register>
2482        <register>
2483          <name>STATUS2</name>
2484          <description>Cache status 2</description>
2485          <addressOffset>0x88</addressOffset>
2486          <size>32</size>
2487          <access>read-only</access>
2488          <resetValue>0x0</resetValue>
2489          <resetMask>0x0</resetMask>
2490          <fields>
2491            <field>
2492              <name>LRU</name>
2493              <description>Six bit LRU representation of the cache set specified by CTL.SET_ADDR. The encoding of the field is as follows ('X_LRU_Y' indicates that way X is Less Recently Used than way Y):
2494Bit 5: 0_LRU_1: way 0 less recently used than way 1.
2495Bit 4: 0_LRU_2.
2496Bit 3: 0_LRU_3.
2497Bit 2: 1_LRU_2.
2498Bit 1: 1_LRU_3.
2499Bit 0: 2_LRU_3.</description>
2500              <bitRange>[5:0]</bitRange>
2501              <access>read-only</access>
2502            </field>
2503          </fields>
2504        </register>
2505        <register>
2506          <name>ECC_CTL</name>
2507          <description>ECC control</description>
2508          <addressOffset>0x100</addressOffset>
2509          <size>32</size>
2510          <access>read-write</access>
2511          <resetValue>0x0</resetValue>
2512          <resetMask>0x7FFFFFFF</resetMask>
2513          <fields>
2514            <field>
2515              <name>WORD_ADDR</name>
2516              <description>Specifies the word address where an error will be injected.
2517- On a write transfer to this SRAM address and when the CTL.ECC_INJ_EN bit is '1', the parity (PARITY) is injected.</description>
2518              <bitRange>[23:0]</bitRange>
2519              <access>read-write</access>
2520            </field>
2521            <field>
2522              <name>PARITY</name>
2523              <description>ECC parity to use for ECC error injection at address WORD_ADDR.
2524- For cache SRAM ECC, the 7-bit parity PARITY[6:0] is for a 32-bit word.</description>
2525              <bitRange>[30:24]</bitRange>
2526              <access>read-write</access>
2527            </field>
2528          </fields>
2529        </register>
2530      </registers>
2531    </peripheral>
2532    <peripheral derivedFrom="ICACHE0">
2533      <name>ICACHE1</name>
2534      <baseAddress>0x40104000</baseAddress>
2535    </peripheral>
2536    <peripheral>
2537      <name>CPUSS_PPU</name>
2538      <description>Power Policy Unit Registers for CPUSS</description>
2539      <baseAddress>0x40105000</baseAddress>
2540      <addressBlock>
2541        <offset>0</offset>
2542        <size>4096</size>
2543        <usage>registers</usage>
2544      </addressBlock>
2545      <registers>
2546        <register>
2547          <name>PWPR</name>
2548          <description>Power Policy Register</description>
2549          <addressOffset>0x0</addressOffset>
2550          <size>32</size>
2551          <access>read-write</access>
2552          <resetValue>0x108</resetValue>
2553          <resetMask>0x10F110F</resetMask>
2554          <fields>
2555            <field>
2556              <name>PWR_POLICY</name>
2557              <description>Power mode policy.  When static power mode transitions are enabled, PWR_DYN_EN is set to 0, this is the target power mode for the PPU.  When dynamic power mode transitions are enabled, PWR_DYN_EN is set to 1, this is the minimum power mode for the PPU.
2558
2559This PPU supports the following modes: OFF(0), FULL_RET(5), ON(8).  Do not use WARM_RST(9) or other unsupported modes.</description>
2560              <bitRange>[3:0]</bitRange>
2561              <access>read-write</access>
2562            </field>
2563            <field>
2564              <name>PWR_DYN_EN</name>
2565              <description>Power mode dynamic transition enable.  When this bit is set to 1 dynamic transitions are enabled for power modes, allowing transitions to be initiated by changes on power mode DEVACTIVE inputs.</description>
2566              <bitRange>[8:8]</bitRange>
2567              <access>read-write</access>
2568            </field>
2569            <field>
2570              <name>LOCK_EN</name>
2571              <description>N/A</description>
2572              <bitRange>[12:12]</bitRange>
2573              <access>read-write</access>
2574            </field>
2575            <field>
2576              <name>OP_POLICY</name>
2577              <description>N/A</description>
2578              <bitRange>[19:16]</bitRange>
2579              <access>read-write</access>
2580            </field>
2581            <field>
2582              <name>OP_DYN_EN</name>
2583              <description>N/A</description>
2584              <bitRange>[24:24]</bitRange>
2585              <access>read-write</access>
2586            </field>
2587          </fields>
2588        </register>
2589        <register>
2590          <name>PMER</name>
2591          <description>Power Mode Emulation Register</description>
2592          <addressOffset>0x4</addressOffset>
2593          <size>32</size>
2594          <access>read-write</access>
2595          <resetValue>0x0</resetValue>
2596          <resetMask>0x1</resetMask>
2597          <fields>
2598            <field>
2599              <name>EMU_EN</name>
2600              <description>N/A</description>
2601              <bitRange>[0:0]</bitRange>
2602              <access>read-write</access>
2603            </field>
2604          </fields>
2605        </register>
2606        <register>
2607          <name>PWSR</name>
2608          <description>Power Status Register</description>
2609          <addressOffset>0x8</addressOffset>
2610          <size>32</size>
2611          <access>read-only</access>
2612          <resetValue>0x0</resetValue>
2613          <resetMask>0x10F110F</resetMask>
2614          <fields>
2615            <field>
2616              <name>PWR_STATUS</name>
2617              <description>Power mode status.  These bits reflect the current power mode of the PPU.  See PPU_PWPR.PWR_POLICY for power mode enumeration.</description>
2618              <bitRange>[3:0]</bitRange>
2619              <access>read-only</access>
2620            </field>
2621            <field>
2622              <name>PWR_DYN_STATUS</name>
2623              <description>Power mode dynamic transition status.  When set to 1 power mode dynamic transitions are enabled.  There might be a delay in dynamic transitions becoming active or inactive if the PPU is transitioning when PWR_DYN_EN is programmed.</description>
2624              <bitRange>[8:8]</bitRange>
2625              <access>read-only</access>
2626            </field>
2627            <field>
2628              <name>LOCK_STATUS</name>
2629              <description>N/A</description>
2630              <bitRange>[12:12]</bitRange>
2631              <access>read-only</access>
2632            </field>
2633            <field>
2634              <name>OP_STATUS</name>
2635              <description>N/A</description>
2636              <bitRange>[19:16]</bitRange>
2637              <access>read-only</access>
2638            </field>
2639            <field>
2640              <name>OP_DYN_STATUS</name>
2641              <description>N/A</description>
2642              <bitRange>[24:24]</bitRange>
2643              <access>read-only</access>
2644            </field>
2645          </fields>
2646        </register>
2647        <register>
2648          <name>DISR</name>
2649          <description>Device Interface Input Current Status Register</description>
2650          <addressOffset>0x10</addressOffset>
2651          <size>32</size>
2652          <access>read-only</access>
2653          <resetValue>0x0</resetValue>
2654          <resetMask>0xFF0007FF</resetMask>
2655          <fields>
2656            <field>
2657              <name>PWR_DEVACTIVE_STATUS</name>
2658              <description>Status of the power mode DEVACTIVE inputs.
2659
2660There is one bit for each device interface Q-Channel DEVQACTIVE.  For example, bit 0 is for Q-channel device 0 DEVQACTIVE.  Refer to PPU_IDR0.DEVCHAN for device channel enumeration.</description>
2661              <bitRange>[10:0]</bitRange>
2662              <access>read-only</access>
2663            </field>
2664            <field>
2665              <name>OP_DEVACTIVE_STATUS</name>
2666              <description>N/A</description>
2667              <bitRange>[31:24]</bitRange>
2668              <access>read-only</access>
2669            </field>
2670          </fields>
2671        </register>
2672        <register>
2673          <name>MISR</name>
2674          <description>Miscellaneous Input Current Status Register</description>
2675          <addressOffset>0x14</addressOffset>
2676          <size>32</size>
2677          <access>read-only</access>
2678          <resetValue>0x0</resetValue>
2679          <resetMask>0xFFFF01</resetMask>
2680          <fields>
2681            <field>
2682              <name>PCSMPACCEPT_STATUS</name>
2683              <description>The status of the PCSMPACCEPT input.</description>
2684              <bitRange>[0:0]</bitRange>
2685              <access>read-only</access>
2686            </field>
2687            <field>
2688              <name>DEVACCEPT_STATUS</name>
2689              <description>Status of the device interface DEVACCEPT inputs.
2690
2691There is one bit for each device interface DEVQACCEPTn.  For example, bit 8 is for Q-Channel 0 DEVQACCEPTn and bit 9 for Q-Channel 1 DEVQACCEPTn.   Refer to PPU_IDR0.DEVCHAN for device channel enumeration.</description>
2692              <bitRange>[15:8]</bitRange>
2693              <access>read-only</access>
2694            </field>
2695            <field>
2696              <name>DEVDENY_STATUS</name>
2697              <description>Status of the device interface DEVDENY inputs.
2698
2699There is one bit for each device interface DEVQDENY.  For example, bit 16 is for Q-Channel 0 DEVQDENY, and bit 17 for Q-Channel 1 DEVQDENY.  Refer to PPU_IDR0.DEVCHAN for device channel enumeration.</description>
2700              <bitRange>[23:16]</bitRange>
2701              <access>read-only</access>
2702            </field>
2703          </fields>
2704        </register>
2705        <register>
2706          <name>STSR</name>
2707          <description>Stored Status Register</description>
2708          <addressOffset>0x18</addressOffset>
2709          <size>32</size>
2710          <access>read-only</access>
2711          <resetValue>0x0</resetValue>
2712          <resetMask>0xFF</resetMask>
2713          <fields>
2714            <field>
2715              <name>STORED_DEVDENY</name>
2716              <description>Status of the DEVDENY signals from the last device interface Q-Channel transition.  For Q-Channel:  There is one bit for each device interface DEVQDENY.  For example, bit 0 is for Q-Channel 0 DEVQDENY, and bit 1 for Q-Channel 1 DEVQDENY.  Refer to PPU_DISR.PWR_DEVACTIVE_STATUS for device enumeration.</description>
2717              <bitRange>[7:0]</bitRange>
2718              <access>read-only</access>
2719            </field>
2720          </fields>
2721        </register>
2722        <register>
2723          <name>UNLK</name>
2724          <description>Unlock register</description>
2725          <addressOffset>0x1C</addressOffset>
2726          <size>32</size>
2727          <access>read-write</access>
2728          <resetValue>0x0</resetValue>
2729          <resetMask>0x1</resetMask>
2730          <fields>
2731            <field>
2732              <name>UNLOCK</name>
2733              <description>N/A</description>
2734              <bitRange>[0:0]</bitRange>
2735              <access>read-write</access>
2736            </field>
2737          </fields>
2738        </register>
2739        <register>
2740          <name>PWCR</name>
2741          <description>Power Configuration Register</description>
2742          <addressOffset>0x20</addressOffset>
2743          <size>32</size>
2744          <access>read-write</access>
2745          <resetValue>0x303</resetValue>
2746          <resetMask>0xFF07FFFF</resetMask>
2747          <fields>
2748            <field>
2749              <name>DEVREQEN</name>
2750              <description>When set to 1 enables the device interface handshake for transitions.  All available bits are reset to 1.
2751
2752There is one bit for each device interface channel.  For example, bit 0 is for Q-Channel 0, and bit 1 is for Q-Channel 1.  Refer to PPU_IDR0.DEVCHAN for device channel enumeration.</description>
2753              <bitRange>[7:0]</bitRange>
2754              <access>read-write</access>
2755            </field>
2756            <field>
2757              <name>PWR_DEVACTIVEEN</name>
2758              <description>These bits enable the power mode DEVACTIVE inputs.  When a bit is to 1 the related DEVACTIVE input is enabled, when set to 0 it is disabled.  All available bits are reset to 1.
2759
2760There is one bit for each device interface Q-Channel DEVQACTIVE.  For example, bit 8 is for the Q-Channel 0 DEVQACTIVE, and bit 9 for the Q-Channel 1 DEVQACTIVE.  Refer to PPU_IDR0.DEVCHAN for device channel enumeration.</description>
2761              <bitRange>[18:8]</bitRange>
2762              <access>read-write</access>
2763            </field>
2764            <field>
2765              <name>OP_DEVACTIVEEN</name>
2766              <description>N/A</description>
2767              <bitRange>[31:24]</bitRange>
2768              <access>read-write</access>
2769            </field>
2770          </fields>
2771        </register>
2772        <register>
2773          <name>PTCR</name>
2774          <description>Power Mode Transition Configuration Register</description>
2775          <addressOffset>0x24</addressOffset>
2776          <size>32</size>
2777          <access>read-write</access>
2778          <resetValue>0x0</resetValue>
2779          <resetMask>0x3</resetMask>
2780          <fields>
2781            <field>
2782              <name>WARM_RST_DEVREQEN</name>
2783              <description>Transition behavior between ON and WARM_RST.  This bit should not be modified when the PPU is in WARM_RST, or if the PPU is performing a transition, otherwise PPU behavior is UNPREDICTABLE.
27840:  The PPU does not perform a device interface handshake when transitioning between ON and WARM_RST.
27851:  The PPU performs a device interface handshake when transitioning between ON and WARM_RST.  This disables all Q-Channels for this transition.</description>
2786              <bitRange>[0:0]</bitRange>
2787              <access>read-write</access>
2788            </field>
2789            <field>
2790              <name>DBG_RECOV_PORST_EN</name>
2791              <description>N/A</description>
2792              <bitRange>[1:1]</bitRange>
2793              <access>read-write</access>
2794            </field>
2795          </fields>
2796        </register>
2797        <register>
2798          <name>IMR</name>
2799          <description>Interrupt Mask Register</description>
2800          <addressOffset>0x30</addressOffset>
2801          <size>32</size>
2802          <access>read-write</access>
2803          <resetValue>0x2</resetValue>
2804          <resetMask>0x3F</resetMask>
2805          <fields>
2806            <field>
2807              <name>STA_POLICY_TRN_IRQ_MASK</name>
2808              <description>Static full policy transition completion event mask.</description>
2809              <bitRange>[0:0]</bitRange>
2810              <access>read-write</access>
2811            </field>
2812            <field>
2813              <name>STA_ACCEPT_IRQ_MASK</name>
2814              <description>Static transition acceptance event mask.</description>
2815              <bitRange>[1:1]</bitRange>
2816              <access>read-write</access>
2817            </field>
2818            <field>
2819              <name>STA_DENY_IRQ_MASK</name>
2820              <description>Static transition denial event mask.</description>
2821              <bitRange>[2:2]</bitRange>
2822              <access>read-write</access>
2823            </field>
2824            <field>
2825              <name>EMU_ACCEPT_IRQ_MASK</name>
2826              <description>N/A</description>
2827              <bitRange>[3:3]</bitRange>
2828              <access>read-write</access>
2829            </field>
2830            <field>
2831              <name>EMU_DENY_IRQ_MASK</name>
2832              <description>N/A</description>
2833              <bitRange>[4:4]</bitRange>
2834              <access>read-write</access>
2835            </field>
2836            <field>
2837              <name>LOCKED_IRQ_MASK</name>
2838              <description>N/A</description>
2839              <bitRange>[5:5]</bitRange>
2840              <access>read-write</access>
2841            </field>
2842          </fields>
2843        </register>
2844        <register>
2845          <name>AIMR</name>
2846          <description>Additional Interrupt Mask Register</description>
2847          <addressOffset>0x34</addressOffset>
2848          <size>32</size>
2849          <access>read-write</access>
2850          <resetValue>0x6</resetValue>
2851          <resetMask>0x1F</resetMask>
2852          <fields>
2853            <field>
2854              <name>UNSPT_POLICY_IRQ_MASK</name>
2855              <description>Unsupported Policy event mask.</description>
2856              <bitRange>[0:0]</bitRange>
2857              <access>read-write</access>
2858            </field>
2859            <field>
2860              <name>DYN_ACCEPT_IRQ_MASK</name>
2861              <description>Dynamic transition acceptance event mask.</description>
2862              <bitRange>[1:1]</bitRange>
2863              <access>read-write</access>
2864            </field>
2865            <field>
2866              <name>DYN_DENY_IRQ_MASK</name>
2867              <description>Dynamic transition denial event mask.</description>
2868              <bitRange>[2:2]</bitRange>
2869              <access>read-write</access>
2870            </field>
2871            <field>
2872              <name>STA_POLICY_PWR_IRQ_MASK</name>
2873              <description>N/A</description>
2874              <bitRange>[3:3]</bitRange>
2875              <access>read-write</access>
2876            </field>
2877            <field>
2878              <name>STA_POLICY_OP_IRQ_MASK</name>
2879              <description>N/A</description>
2880              <bitRange>[4:4]</bitRange>
2881              <access>read-write</access>
2882            </field>
2883          </fields>
2884        </register>
2885        <register>
2886          <name>ISR</name>
2887          <description>Interrupt Status Register</description>
2888          <addressOffset>0x38</addressOffset>
2889          <size>32</size>
2890          <access>read-write</access>
2891          <resetValue>0x0</resetValue>
2892          <resetMask>0xFF07FFBF</resetMask>
2893          <fields>
2894            <field>
2895              <name>STA_POLICY_TRN_IRQ</name>
2896              <description>Static full policy transition completion event status.</description>
2897              <bitRange>[0:0]</bitRange>
2898              <access>read-write</access>
2899            </field>
2900            <field>
2901              <name>STA_ACCEPT_IRQ</name>
2902              <description>Static transition acceptance event status.</description>
2903              <bitRange>[1:1]</bitRange>
2904              <access>read-write</access>
2905            </field>
2906            <field>
2907              <name>STA_DENY_IRQ</name>
2908              <description>Static transition denial event status.</description>
2909              <bitRange>[2:2]</bitRange>
2910              <access>read-write</access>
2911            </field>
2912            <field>
2913              <name>EMU_ACCEPT_IRQ</name>
2914              <description>N/A</description>
2915              <bitRange>[3:3]</bitRange>
2916              <access>read-write</access>
2917            </field>
2918            <field>
2919              <name>EMU_DENY_IRQ</name>
2920              <description>N/A</description>
2921              <bitRange>[4:4]</bitRange>
2922              <access>read-write</access>
2923            </field>
2924            <field>
2925              <name>LOCKED_IRQ</name>
2926              <description>N/A</description>
2927              <bitRange>[5:5]</bitRange>
2928              <access>read-write</access>
2929            </field>
2930            <field>
2931              <name>OTHER_IRQ</name>
2932              <description>Indicates there is an interrupt event pending in the Additional Interrupt Status Register (PPU_AISR).</description>
2933              <bitRange>[7:7]</bitRange>
2934              <access>read-only</access>
2935            </field>
2936            <field>
2937              <name>PWR_ACTIVE_EDGE_IRQ</name>
2938              <description>N/A</description>
2939              <bitRange>[18:8]</bitRange>
2940              <access>read-write</access>
2941            </field>
2942            <field>
2943              <name>OP_ACTIVE_EDGE_IRQ</name>
2944              <description>N/A</description>
2945              <bitRange>[31:24]</bitRange>
2946              <access>read-write</access>
2947            </field>
2948          </fields>
2949        </register>
2950        <register>
2951          <name>AISR</name>
2952          <description>Additional Interrupt Status Register</description>
2953          <addressOffset>0x3C</addressOffset>
2954          <size>32</size>
2955          <access>read-write</access>
2956          <resetValue>0x0</resetValue>
2957          <resetMask>0x1F</resetMask>
2958          <fields>
2959            <field>
2960              <name>UNSPT_POLICY_IRQ</name>
2961              <description>Unsupported Policy event status.</description>
2962              <bitRange>[0:0]</bitRange>
2963              <access>read-write</access>
2964            </field>
2965            <field>
2966              <name>DYN_ACCEPT_IRQ</name>
2967              <description>Dynamic transition acceptance event status.</description>
2968              <bitRange>[1:1]</bitRange>
2969              <access>read-write</access>
2970            </field>
2971            <field>
2972              <name>DYN_DENY_IRQ</name>
2973              <description>Dynamic transition denial event status.</description>
2974              <bitRange>[2:2]</bitRange>
2975              <access>read-write</access>
2976            </field>
2977            <field>
2978              <name>STA_POLICY_PWR_IRQ</name>
2979              <description>N/A</description>
2980              <bitRange>[3:3]</bitRange>
2981              <access>read-write</access>
2982            </field>
2983            <field>
2984              <name>STA_POLICY_OP_IRQ</name>
2985              <description>N/A</description>
2986              <bitRange>[4:4]</bitRange>
2987              <access>read-write</access>
2988            </field>
2989          </fields>
2990        </register>
2991        <register>
2992          <name>IESR</name>
2993          <description>Input Edge Sensitivity Register</description>
2994          <addressOffset>0x40</addressOffset>
2995          <size>32</size>
2996          <access>read-write</access>
2997          <resetValue>0x0</resetValue>
2998          <resetMask>0x3FFFFF</resetMask>
2999          <fields>
3000            <field>
3001              <name>DEVACTIVE00_EDGE</name>
3002              <description>DEVACTIVE 0 edge sensitivity.</description>
3003              <bitRange>[1:0]</bitRange>
3004              <access>read-write</access>
3005            </field>
3006            <field>
3007              <name>DEVACTIVE01_EDGE</name>
3008              <description>DEVACTIVE 1 edge sensitivity.</description>
3009              <bitRange>[3:2]</bitRange>
3010              <access>read-write</access>
3011            </field>
3012            <field>
3013              <name>DEVACTIVE02_EDGE</name>
3014              <description>DEVACTIVE 2 edge sensitivity.</description>
3015              <bitRange>[5:4]</bitRange>
3016              <access>read-write</access>
3017            </field>
3018            <field>
3019              <name>DEVACTIVE03_EDGE</name>
3020              <description>N/A</description>
3021              <bitRange>[7:6]</bitRange>
3022              <access>read-write</access>
3023            </field>
3024            <field>
3025              <name>DEVACTIVE04_EDGE</name>
3026              <description>N/A</description>
3027              <bitRange>[9:8]</bitRange>
3028              <access>read-write</access>
3029            </field>
3030            <field>
3031              <name>DEVACTIVE05_EDGE</name>
3032              <description>N/A</description>
3033              <bitRange>[11:10]</bitRange>
3034              <access>read-write</access>
3035            </field>
3036            <field>
3037              <name>DEVACTIVE06_EDGE</name>
3038              <description>N/A</description>
3039              <bitRange>[13:12]</bitRange>
3040              <access>read-write</access>
3041            </field>
3042            <field>
3043              <name>DEVACTIVE07_EDGE</name>
3044              <description>N/A</description>
3045              <bitRange>[15:14]</bitRange>
3046              <access>read-write</access>
3047            </field>
3048            <field>
3049              <name>DEVACTIVE08_EDGE</name>
3050              <description>N/A</description>
3051              <bitRange>[17:16]</bitRange>
3052              <access>read-write</access>
3053            </field>
3054            <field>
3055              <name>DEVACTIVE09_EDGE</name>
3056              <description>N/A</description>
3057              <bitRange>[19:18]</bitRange>
3058              <access>read-write</access>
3059            </field>
3060            <field>
3061              <name>DEVACTIVE10_EDGE</name>
3062              <description>N/A</description>
3063              <bitRange>[21:20]</bitRange>
3064              <access>read-write</access>
3065            </field>
3066          </fields>
3067        </register>
3068        <register>
3069          <name>OPSR</name>
3070          <description>Operating Mode Active Edge Sensitivity Register</description>
3071          <addressOffset>0x44</addressOffset>
3072          <size>32</size>
3073          <access>read-write</access>
3074          <resetValue>0x0</resetValue>
3075          <resetMask>0xFFFF</resetMask>
3076          <fields>
3077            <field>
3078              <name>DEVACTIVE16_EDGE</name>
3079              <description>N/A</description>
3080              <bitRange>[1:0]</bitRange>
3081              <access>read-write</access>
3082            </field>
3083            <field>
3084              <name>DEVACTIVE17_EDGE</name>
3085              <description>N/A</description>
3086              <bitRange>[3:2]</bitRange>
3087              <access>read-write</access>
3088            </field>
3089            <field>
3090              <name>DEVACTIVE18_EDGE</name>
3091              <description>N/A</description>
3092              <bitRange>[5:4]</bitRange>
3093              <access>read-write</access>
3094            </field>
3095            <field>
3096              <name>DEVACTIVE19_EDGE</name>
3097              <description>N/A</description>
3098              <bitRange>[7:6]</bitRange>
3099              <access>read-write</access>
3100            </field>
3101            <field>
3102              <name>DEVACTIVE20_EDGE</name>
3103              <description>N/A</description>
3104              <bitRange>[9:8]</bitRange>
3105              <access>read-write</access>
3106            </field>
3107            <field>
3108              <name>DEVACTIVE21_EDGE</name>
3109              <description>N/A</description>
3110              <bitRange>[11:10]</bitRange>
3111              <access>read-write</access>
3112            </field>
3113            <field>
3114              <name>DEVACTIVE22_EDGE</name>
3115              <description>N/A</description>
3116              <bitRange>[13:12]</bitRange>
3117              <access>read-write</access>
3118            </field>
3119            <field>
3120              <name>DEVACTIVE23_EDGE</name>
3121              <description>N/A</description>
3122              <bitRange>[15:14]</bitRange>
3123              <access>read-write</access>
3124            </field>
3125          </fields>
3126        </register>
3127        <register>
3128          <name>FUNRR</name>
3129          <description>Functional Retention RAM Configuration Register</description>
3130          <addressOffset>0x50</addressOffset>
3131          <size>32</size>
3132          <access>read-write</access>
3133          <resetValue>0x0</resetValue>
3134          <resetMask>0xFF</resetMask>
3135          <fields>
3136            <field>
3137              <name>FUNC_RET_RAM_CFG</name>
3138              <description>N/A</description>
3139              <bitRange>[7:0]</bitRange>
3140              <access>read-write</access>
3141            </field>
3142          </fields>
3143        </register>
3144        <register>
3145          <name>FULRR</name>
3146          <description>Full Retention RAM Configuration Register</description>
3147          <addressOffset>0x54</addressOffset>
3148          <size>32</size>
3149          <access>read-write</access>
3150          <resetValue>0x0</resetValue>
3151          <resetMask>0xFF</resetMask>
3152          <fields>
3153            <field>
3154              <name>FULL_RET_RAM_CFG</name>
3155              <description>N/A</description>
3156              <bitRange>[7:0]</bitRange>
3157              <access>read-write</access>
3158            </field>
3159          </fields>
3160        </register>
3161        <register>
3162          <name>MEMRR</name>
3163          <description>Memory Retention RAM Configuration Register</description>
3164          <addressOffset>0x58</addressOffset>
3165          <size>32</size>
3166          <access>read-write</access>
3167          <resetValue>0x0</resetValue>
3168          <resetMask>0xFF</resetMask>
3169          <fields>
3170            <field>
3171              <name>MEM_RET_RAM_CFG</name>
3172              <description>N/A</description>
3173              <bitRange>[7:0]</bitRange>
3174              <access>read-write</access>
3175            </field>
3176          </fields>
3177        </register>
3178        <register>
3179          <name>EDTR0</name>
3180          <description>Power Mode Entry Delay Register 0</description>
3181          <addressOffset>0x160</addressOffset>
3182          <size>32</size>
3183          <access>read-write</access>
3184          <resetValue>0x0</resetValue>
3185          <resetMask>0xFFFFFFFF</resetMask>
3186          <fields>
3187            <field>
3188              <name>OFF_DEL</name>
3189              <description>N/A</description>
3190              <bitRange>[7:0]</bitRange>
3191              <access>read-write</access>
3192            </field>
3193            <field>
3194              <name>MEM_RET_DEL</name>
3195              <description>N/A</description>
3196              <bitRange>[15:8]</bitRange>
3197              <access>read-write</access>
3198            </field>
3199            <field>
3200              <name>LOGIC_RET_DEL</name>
3201              <description>N/A</description>
3202              <bitRange>[23:16]</bitRange>
3203              <access>read-write</access>
3204            </field>
3205            <field>
3206              <name>FULL_RET_DEL</name>
3207              <description>N/A</description>
3208              <bitRange>[31:24]</bitRange>
3209              <access>read-write</access>
3210            </field>
3211          </fields>
3212        </register>
3213        <register>
3214          <name>EDTR1</name>
3215          <description>Power Mode Entry Delay Register 1</description>
3216          <addressOffset>0x164</addressOffset>
3217          <size>32</size>
3218          <access>read-write</access>
3219          <resetValue>0x0</resetValue>
3220          <resetMask>0xFFFF</resetMask>
3221          <fields>
3222            <field>
3223              <name>MEM_OFF_DEL</name>
3224              <description>N/A</description>
3225              <bitRange>[7:0]</bitRange>
3226              <access>read-write</access>
3227            </field>
3228            <field>
3229              <name>FUNC_RET_DEL</name>
3230              <description>N/A</description>
3231              <bitRange>[15:8]</bitRange>
3232              <access>read-write</access>
3233            </field>
3234          </fields>
3235        </register>
3236        <register>
3237          <name>DCDR0</name>
3238          <description>Device Control Delay Configuration Register 0</description>
3239          <addressOffset>0x170</addressOffset>
3240          <size>32</size>
3241          <access>read-only</access>
3242          <resetValue>0x0</resetValue>
3243          <resetMask>0xFFFFFF</resetMask>
3244          <fields>
3245            <field>
3246              <name>CLKEN_RST_DLY</name>
3247              <description>N/A</description>
3248              <bitRange>[7:0]</bitRange>
3249              <access>read-only</access>
3250            </field>
3251            <field>
3252              <name>ISO_CLKEN_DLY</name>
3253              <description>N/A</description>
3254              <bitRange>[15:8]</bitRange>
3255              <access>read-only</access>
3256            </field>
3257            <field>
3258              <name>RST_HWSTAT_DLY</name>
3259              <description>N/A</description>
3260              <bitRange>[23:16]</bitRange>
3261              <access>read-only</access>
3262            </field>
3263          </fields>
3264        </register>
3265        <register>
3266          <name>DCDR1</name>
3267          <description>Device Control Delay Configuration Register 1</description>
3268          <addressOffset>0x174</addressOffset>
3269          <size>32</size>
3270          <access>read-only</access>
3271          <resetValue>0x0</resetValue>
3272          <resetMask>0xFFFF</resetMask>
3273          <fields>
3274            <field>
3275              <name>ISO_RST_DLY</name>
3276              <description>N/A</description>
3277              <bitRange>[7:0]</bitRange>
3278              <access>read-only</access>
3279            </field>
3280            <field>
3281              <name>CLKEN_ISO_DLY</name>
3282              <description>N/A</description>
3283              <bitRange>[15:8]</bitRange>
3284              <access>read-only</access>
3285            </field>
3286          </fields>
3287        </register>
3288        <register>
3289          <name>IDR0</name>
3290          <description>PPU Identification Register 0</description>
3291          <addressOffset>0xFB0</addressOffset>
3292          <size>32</size>
3293          <access>read-only</access>
3294          <resetValue>0x14134102</resetValue>
3295          <resetMask>0x3FF7FFFF</resetMask>
3296          <fields>
3297            <field>
3298              <name>DEVCHAN</name>
3299              <description>No. of Device Interface Channels.
33000: This is a P-Channel PPU.  Refer to PPU_IDR1.OP_ACTIVE for the number of DEVPACTIVE inputs and their meaning.
3301non-zero: The value is the number of Q-Channels.
3302
3303The device enumeration is:
3304Device 0: SRSS PDCM,
3305Device 1: CPUSS SEQ between SS level LPD500 EXP &amp; PERI Q-Channel</description>
3306              <bitRange>[3:0]</bitRange>
3307              <access>read-only</access>
3308            </field>
3309            <field>
3310              <name>NUM_OPMODE</name>
3311              <description>No. of operating modes supported is NUM_OPMODE + 1.</description>
3312              <bitRange>[7:4]</bitRange>
3313              <access>read-only</access>
3314            </field>
3315            <field>
3316              <name>STA_OFF_SPT</name>
3317              <description>OFF support.</description>
3318              <bitRange>[8:8]</bitRange>
3319              <access>read-only</access>
3320            </field>
3321            <field>
3322              <name>STA_OFF_EMU_SPT</name>
3323              <description>OFF_EMU support.</description>
3324              <bitRange>[9:9]</bitRange>
3325              <access>read-only</access>
3326            </field>
3327            <field>
3328              <name>STA_MEM_RET_SPT</name>
3329              <description>MEM_RET support.</description>
3330              <bitRange>[10:10]</bitRange>
3331              <access>read-only</access>
3332            </field>
3333            <field>
3334              <name>STA_MEM_RET_EMU_SPT</name>
3335              <description>MEM_RET_EMU support.</description>
3336              <bitRange>[11:11]</bitRange>
3337              <access>read-only</access>
3338            </field>
3339            <field>
3340              <name>STA_LGC_RET_SPT</name>
3341              <description>LOGIC_RET support.</description>
3342              <bitRange>[12:12]</bitRange>
3343              <access>read-only</access>
3344            </field>
3345            <field>
3346              <name>STA_MEM_OFF_SPT</name>
3347              <description>MEM_OFF support.</description>
3348              <bitRange>[13:13]</bitRange>
3349              <access>read-only</access>
3350            </field>
3351            <field>
3352              <name>STA_FULL_RET_SPT</name>
3353              <description>FULL_RET support.</description>
3354              <bitRange>[14:14]</bitRange>
3355              <access>read-only</access>
3356            </field>
3357            <field>
3358              <name>STA_FUNC_RET_SPT</name>
3359              <description>FUNC_RET support.</description>
3360              <bitRange>[15:15]</bitRange>
3361              <access>read-only</access>
3362            </field>
3363            <field>
3364              <name>STA_ON_SPT</name>
3365              <description>ON support.</description>
3366              <bitRange>[16:16]</bitRange>
3367              <access>read-only</access>
3368            </field>
3369            <field>
3370              <name>STA_WRM_RST_SPT</name>
3371              <description>WARM_RST support.  Ignore this bit.  Do not use WARM_RST.</description>
3372              <bitRange>[17:17]</bitRange>
3373              <access>read-only</access>
3374            </field>
3375            <field>
3376              <name>STA_DBG_RECOV_SPT</name>
3377              <description>DBG_RECOV support.</description>
3378              <bitRange>[18:18]</bitRange>
3379              <access>read-only</access>
3380            </field>
3381            <field>
3382              <name>DYN_OFF_SPT</name>
3383              <description>Dynamic OFF support.</description>
3384              <bitRange>[20:20]</bitRange>
3385              <access>read-only</access>
3386            </field>
3387            <field>
3388              <name>DYN_OFF_EMU_SPT</name>
3389              <description>Dynamic OFF_EMU support.</description>
3390              <bitRange>[21:21]</bitRange>
3391              <access>read-only</access>
3392            </field>
3393            <field>
3394              <name>DYN_MEM_RET_SPT</name>
3395              <description>Dynamic MEM_RET support.</description>
3396              <bitRange>[22:22]</bitRange>
3397              <access>read-only</access>
3398            </field>
3399            <field>
3400              <name>DYN_MEM_RET_EMU_SPT</name>
3401              <description>Dynamic MEM_RET_EMU support</description>
3402              <bitRange>[23:23]</bitRange>
3403              <access>read-only</access>
3404            </field>
3405            <field>
3406              <name>DYN_LGC_RET_SPT</name>
3407              <description>Dynamic LOGIC_RET support.</description>
3408              <bitRange>[24:24]</bitRange>
3409              <access>read-only</access>
3410            </field>
3411            <field>
3412              <name>DYN_MEM_OFF_SPT</name>
3413              <description>Dynamic MEM_OFF support.</description>
3414              <bitRange>[25:25]</bitRange>
3415              <access>read-only</access>
3416            </field>
3417            <field>
3418              <name>DYN_FULL_RET_SPT</name>
3419              <description>Dynamic FULL_RET support.</description>
3420              <bitRange>[26:26]</bitRange>
3421              <access>read-only</access>
3422            </field>
3423            <field>
3424              <name>DYN_FUNC_RET_SPT</name>
3425              <description>Dynamic FUNC_RET support.</description>
3426              <bitRange>[27:27]</bitRange>
3427              <access>read-only</access>
3428            </field>
3429            <field>
3430              <name>DYN_ON_SPT</name>
3431              <description>Dynamic ON support.</description>
3432              <bitRange>[28:28]</bitRange>
3433              <access>read-only</access>
3434            </field>
3435            <field>
3436              <name>DYN_WRM_RST_SPT</name>
3437              <description>Dynamic WARM_RST support.</description>
3438              <bitRange>[29:29]</bitRange>
3439              <access>read-only</access>
3440            </field>
3441          </fields>
3442        </register>
3443        <register>
3444          <name>IDR1</name>
3445          <description>PPU Identification Register 1</description>
3446          <addressOffset>0xFB4</addressOffset>
3447          <size>32</size>
3448          <access>read-only</access>
3449          <resetValue>0x0</resetValue>
3450          <resetMask>0x1777</resetMask>
3451          <fields>
3452            <field>
3453              <name>PWR_MODE_ENTRY_DEL_SPT</name>
3454              <description>Power mode entry delay support.</description>
3455              <bitRange>[0:0]</bitRange>
3456              <access>read-only</access>
3457            </field>
3458            <field>
3459              <name>SW_DEV_DEL_SPT</name>
3460              <description>Software device delay control configuration support.</description>
3461              <bitRange>[1:1]</bitRange>
3462              <access>read-only</access>
3463            </field>
3464            <field>
3465              <name>LOCK_SPT</name>
3466              <description>Lock and the lock interrupt event are supported.</description>
3467              <bitRange>[2:2]</bitRange>
3468              <access>read-only</access>
3469            </field>
3470            <field>
3471              <name>MEM_RET_RAM_REG</name>
3472              <description>N/A</description>
3473              <bitRange>[4:4]</bitRange>
3474              <access>read-only</access>
3475            </field>
3476            <field>
3477              <name>FULL_RET_RAM_REG</name>
3478              <description>N/A</description>
3479              <bitRange>[5:5]</bitRange>
3480              <access>read-only</access>
3481            </field>
3482            <field>
3483              <name>FUNC_RET_RAM_REG</name>
3484              <description>N/A</description>
3485              <bitRange>[6:6]</bitRange>
3486              <access>read-only</access>
3487            </field>
3488            <field>
3489              <name>STA_POLICY_PWR_IRQ_SPT</name>
3490              <description>Power policy transition completion event status.</description>
3491              <bitRange>[8:8]</bitRange>
3492              <access>read-only</access>
3493            </field>
3494            <field>
3495              <name>STA_POLICY_OP_IRQ_SPT</name>
3496              <description>Operating policy transition completion event status.</description>
3497              <bitRange>[9:9]</bitRange>
3498              <access>read-only</access>
3499            </field>
3500            <field>
3501              <name>OP_ACTIVE</name>
3502              <description>N/A</description>
3503              <bitRange>[10:10]</bitRange>
3504              <access>read-only</access>
3505            </field>
3506            <field>
3507              <name>OFF_MEM_RET_TRANS</name>
3508              <description>OFF to MEM_RET direct transition.  Indicates if direct transitions from OFF to MEM_RET and from OFF_EMU to MEM_RET_EMU are supported.</description>
3509              <bitRange>[12:12]</bitRange>
3510              <access>read-only</access>
3511            </field>
3512          </fields>
3513        </register>
3514        <register>
3515          <name>IIDR</name>
3516          <description>Implementation Identification Register</description>
3517          <addressOffset>0xFC8</addressOffset>
3518          <size>32</size>
3519          <access>read-only</access>
3520          <resetValue>0xB50043B</resetValue>
3521          <resetMask>0xFFFFFFFF</resetMask>
3522          <fields>
3523            <field>
3524              <name>IMPLEMENTER</name>
3525              <description>Implementer identification.  [11:8] The JEP106 continuation code of the implementer.  [7] Always 0.  [6:0] The JEP106 identity code of the implementer.  For an Arm implementation, bits [11:0] are 0x43B.</description>
3526              <bitRange>[11:0]</bitRange>
3527              <access>read-only</access>
3528            </field>
3529            <field>
3530              <name>REVISION</name>
3531              <description>Minor revision of the product.</description>
3532              <bitRange>[15:12]</bitRange>
3533              <access>read-only</access>
3534            </field>
3535            <field>
3536              <name>VARIANT</name>
3537              <description>Major revision of the product.</description>
3538              <bitRange>[19:16]</bitRange>
3539              <access>read-only</access>
3540            </field>
3541            <field>
3542              <name>PRODUCT_ID</name>
3543              <description>PPU part identification.</description>
3544              <bitRange>[31:20]</bitRange>
3545              <access>read-only</access>
3546            </field>
3547          </fields>
3548        </register>
3549        <register>
3550          <name>AIDR</name>
3551          <description>Architecture Identification Register</description>
3552          <addressOffset>0xFCC</addressOffset>
3553          <size>32</size>
3554          <access>read-only</access>
3555          <resetValue>0x11</resetValue>
3556          <resetMask>0xFF</resetMask>
3557          <fields>
3558            <field>
3559              <name>ARCH_REV_MINOR</name>
3560              <description>N/A</description>
3561              <bitRange>[3:0]</bitRange>
3562              <access>read-only</access>
3563            </field>
3564            <field>
3565              <name>ARCH_REV_MAJOR</name>
3566              <description>N/A</description>
3567              <bitRange>[7:4]</bitRange>
3568              <access>read-only</access>
3569            </field>
3570          </fields>
3571        </register>
3572        <register>
3573          <name>PID4</name>
3574          <description>Implementation Defined Identification Register (PID4)</description>
3575          <addressOffset>0xFD0</addressOffset>
3576          <size>32</size>
3577          <access>read-only</access>
3578          <resetValue>0x4</resetValue>
3579          <resetMask>0xF</resetMask>
3580          <fields>
3581            <field>
3582              <name>IMPLEMENTER_11_8</name>
3583              <description>The JEP106 continuation code of the implementer, which is 0x4 hardcoded value.</description>
3584              <bitRange>[3:0]</bitRange>
3585              <access>read-only</access>
3586            </field>
3587          </fields>
3588        </register>
3589        <register>
3590          <name>PID0</name>
3591          <description>Implementation Defined Identification Register (PID0)</description>
3592          <addressOffset>0xFE0</addressOffset>
3593          <size>32</size>
3594          <access>read-only</access>
3595          <resetValue>0xB5</resetValue>
3596          <resetMask>0xFF</resetMask>
3597          <fields>
3598            <field>
3599              <name>PRODUCT_ID_7_0</name>
3600              <description>PPU part identification bits [7:0].</description>
3601              <bitRange>[7:0]</bitRange>
3602              <access>read-only</access>
3603            </field>
3604          </fields>
3605        </register>
3606        <register>
3607          <name>PID1</name>
3608          <description>Implementation Defined Identification Register (PID1)</description>
3609          <addressOffset>0xFE4</addressOffset>
3610          <size>32</size>
3611          <access>read-only</access>
3612          <resetValue>0xB0</resetValue>
3613          <resetMask>0xFF</resetMask>
3614          <fields>
3615            <field>
3616              <name>PRODUCT_ID_11_8</name>
3617              <description>PPU part identification bits [11:8]</description>
3618              <bitRange>[3:0]</bitRange>
3619              <access>read-only</access>
3620            </field>
3621            <field>
3622              <name>IMPLEMENTER_3_0</name>
3623              <description>JEP106_ID bits [3:0]</description>
3624              <bitRange>[7:4]</bitRange>
3625              <access>read-only</access>
3626            </field>
3627          </fields>
3628        </register>
3629        <register>
3630          <name>PID2</name>
3631          <description>Implementation Defined Identification Register (PID2)</description>
3632          <addressOffset>0xFE8</addressOffset>
3633          <size>32</size>
3634          <access>read-only</access>
3635          <resetValue>0xB</resetValue>
3636          <resetMask>0xFF</resetMask>
3637          <fields>
3638            <field>
3639              <name>IMPLEMENTER_6_4</name>
3640              <description>JEP106_ID bits [6:4]</description>
3641              <bitRange>[2:0]</bitRange>
3642              <access>read-only</access>
3643            </field>
3644            <field>
3645              <name>CONST_HIGH</name>
3646              <description>Constant HIGH</description>
3647              <bitRange>[3:3]</bitRange>
3648              <access>read-only</access>
3649            </field>
3650            <field>
3651              <name>REV_CONST</name>
3652              <description>Constant LOW  Revision (4 bits)</description>
3653              <bitRange>[7:4]</bitRange>
3654              <access>read-only</access>
3655            </field>
3656          </fields>
3657        </register>
3658        <register>
3659          <name>PID3</name>
3660          <description>Implementation Defined Identification Register (PID3)</description>
3661          <addressOffset>0xFEC</addressOffset>
3662          <size>32</size>
3663          <access>read-only</access>
3664          <resetValue>0x0</resetValue>
3665          <resetMask>0xFF</resetMask>
3666          <fields>
3667            <field>
3668              <name>PID3_REV_CONST</name>
3669              <description>Constant LOW (4 bits)</description>
3670              <bitRange>[3:0]</bitRange>
3671              <access>read-only</access>
3672            </field>
3673            <field>
3674              <name>PID3_REVISION</name>
3675              <description>Minor revision of the product.</description>
3676              <bitRange>[7:4]</bitRange>
3677              <access>read-only</access>
3678            </field>
3679          </fields>
3680        </register>
3681        <register>
3682          <name>ID0</name>
3683          <description>Implementation Defined Identification Register (ID0)</description>
3684          <addressOffset>0xFF0</addressOffset>
3685          <size>32</size>
3686          <access>read-only</access>
3687          <resetValue>0xD</resetValue>
3688          <resetMask>0xFF</resetMask>
3689          <fields>
3690            <field>
3691              <name>ID0</name>
3692              <description>ID0 hard coded value</description>
3693              <bitRange>[7:0]</bitRange>
3694              <access>read-only</access>
3695            </field>
3696          </fields>
3697        </register>
3698        <register>
3699          <name>ID1</name>
3700          <description>Implementation Defined Identification Register (ID1)</description>
3701          <addressOffset>0xFF4</addressOffset>
3702          <size>32</size>
3703          <access>read-only</access>
3704          <resetValue>0xF0</resetValue>
3705          <resetMask>0xFF</resetMask>
3706          <fields>
3707            <field>
3708              <name>ID1</name>
3709              <description>ID1 hardcoded value</description>
3710              <bitRange>[7:0]</bitRange>
3711              <access>read-only</access>
3712            </field>
3713          </fields>
3714        </register>
3715        <register>
3716          <name>ID2</name>
3717          <description>Implementation Defined Identification Register (ID2)</description>
3718          <addressOffset>0xFF8</addressOffset>
3719          <size>32</size>
3720          <access>read-only</access>
3721          <resetValue>0x5</resetValue>
3722          <resetMask>0xFF</resetMask>
3723          <fields>
3724            <field>
3725              <name>ID2</name>
3726              <description>ID2 hardcoded value</description>
3727              <bitRange>[7:0]</bitRange>
3728              <access>read-only</access>
3729            </field>
3730          </fields>
3731        </register>
3732        <register>
3733          <name>ID3</name>
3734          <description>Implementation Defined Identification Register (ID3)</description>
3735          <addressOffset>0xFFC</addressOffset>
3736          <size>32</size>
3737          <access>read-only</access>
3738          <resetValue>0xB1</resetValue>
3739          <resetMask>0xFF</resetMask>
3740          <fields>
3741            <field>
3742              <name>ID3</name>
3743              <description>ID3 hardcoded value</description>
3744              <bitRange>[7:0]</bitRange>
3745              <access>read-only</access>
3746            </field>
3747          </fields>
3748        </register>
3749      </registers>
3750    </peripheral>
3751    <peripheral>
3752      <name>RAMC0</name>
3753      <description>RAMC0/1/2</description>
3754      <headerStructName>RAMC</headerStructName>
3755      <baseAddress>0x40110000</baseAddress>
3756      <addressBlock>
3757        <offset>0</offset>
3758        <size>65536</size>
3759        <usage>registers</usage>
3760      </addressBlock>
3761      <registers>
3762        <register>
3763          <name>CTL</name>
3764          <description>Control</description>
3765          <addressOffset>0x0</addressOffset>
3766          <size>32</size>
3767          <access>read-write</access>
3768          <resetValue>0x0</resetValue>
3769          <resetMask>0x10003</resetMask>
3770          <fields>
3771            <field>
3772              <name>SRAM_WS</name>
3773              <description>Wait states.</description>
3774              <bitRange>[1:0]</bitRange>
3775              <access>read-write</access>
3776              <enumeratedValues>
3777                <enumeratedValue>
3778                  <name>WS_0</name>
3779                  <description>N/A</description>
3780                  <value>0</value>
3781                </enumeratedValue>
3782                <enumeratedValue>
3783                  <name>WS_1</name>
3784                  <description>N/A</description>
3785                  <value>1</value>
3786                </enumeratedValue>
3787                <enumeratedValue>
3788                  <name>WS_2</name>
3789                  <description>N/A</description>
3790                  <value>2</value>
3791                </enumeratedValue>
3792                <enumeratedValue>
3793                  <name>WS_3</name>
3794                  <description>N/A</description>
3795                  <value>3</value>
3796                </enumeratedValue>
3797              </enumeratedValues>
3798            </field>
3799            <field>
3800              <name>CLOCK_FORCE</name>
3801              <description>Force EAM clock gating to be always ON.
38020: Disabled
38031: Enabled
3804
3805This bit provides fail safe mechanism for dynamic clock gating added on EAM block.</description>
3806              <bitRange>[16:16]</bitRange>
3807              <access>read-write</access>
3808            </field>
3809          </fields>
3810        </register>
3811        <register>
3812          <name>STATUS</name>
3813          <description>Status</description>
3814          <addressOffset>0x8</addressOffset>
3815          <size>32</size>
3816          <access>read-only</access>
3817          <resetValue>0x11</resetValue>
3818          <resetMask>0x11</resetMask>
3819          <fields>
3820            <field>
3821              <name>WB_EMPTY</name>
3822              <description>Write buffer empty. This information is used when entering DeepSleep power mode: WB_EMPTY must be '1' before a transition to system DeepSleep power mode.
3823'0': Write buffer NOT empty.
3824'1': Write buffer empty.
3825
3826Note: the SRAM controller write buffer is only used when ECC checking is enabled. (RAMi_CTL.ECC_EN is '1').</description>
3827              <bitRange>[0:0]</bitRange>
3828              <access>read-only</access>
3829            </field>
3830            <field>
3831              <name>PWR_DONE</name>
3832              <description>After a PWR_MACRO_CTL.OFF change this flag indicates if the new power mode has taken effect or not.
38331: Indicates change is effective;
38340: Indicates change is in progress;</description>
3835              <bitRange>[4:4]</bitRange>
3836              <access>read-only</access>
3837            </field>
3838          </fields>
3839        </register>
3840        <register>
3841          <name>PWR_MACRO_CTL</name>
3842          <description>SRAM power partition power control</description>
3843          <addressOffset>0x200</addressOffset>
3844          <size>32</size>
3845          <access>read-write</access>
3846          <resetValue>0x0</resetValue>
3847          <resetMask>0xFFFFFFFF</resetMask>
3848          <fields>
3849            <field>
3850              <name>OFF</name>
3851              <description>Each bit represent the individual RAM power partition power state.  One bit for each macro of RAM controller when all 32 bits are populated as 32 independent power partitions.
38520: Macros in power partion is to be powered-ON
38531: Macros in power partion is to be powered-OFF
3854
3855Note that it is not allowed to disable few macros while enable others in the same AHB write transaction.
3856
3857It is mandatory to check for STATUS.PWR_DONE to become 1 once this PWR_MACRO_DTL register contents are changed to ensure SRAM mode transition is completed successfully.</description>
3858              <bitRange>[31:0]</bitRange>
3859              <access>read-write</access>
3860            </field>
3861          </fields>
3862        </register>
3863        <register>
3864          <name>PWR_MACRO_CTL_LOCK</name>
3865          <description>SRAM power partition power control Lock</description>
3866          <addressOffset>0x240</addressOffset>
3867          <size>32</size>
3868          <access>read-write</access>
3869          <resetValue>0x3</resetValue>
3870          <resetMask>0x3</resetMask>
3871          <fields>
3872            <field>
3873              <name>PWR_MACRO_CTL_LOCK</name>
3874              <description>Prohibits Read/Write access to PWR_MACRO_CTL register when this field is not equal to 0.  Requires at least two different writes to unlock.
3875Note that this field is 2 bits to force multiple writes only.
3876By default AHB reads/writes to PWR_MACRO_CTL register are locked.</description>
3877              <bitRange>[1:0]</bitRange>
3878              <access>read-write</access>
3879              <enumeratedValues>
3880                <enumeratedValue>
3881                  <name>NO_CHG</name>
3882                  <description>No effect</description>
3883                  <value>0</value>
3884                </enumeratedValue>
3885                <enumeratedValue>
3886                  <name>CLR0</name>
3887                  <description>Clears bit 0</description>
3888                  <value>1</value>
3889                </enumeratedValue>
3890                <enumeratedValue>
3891                  <name>CLR1</name>
3892                  <description>Clears bit 1</description>
3893                  <value>2</value>
3894                </enumeratedValue>
3895                <enumeratedValue>
3896                  <name>SET01</name>
3897                  <description>Sets both bits 0 and 1</description>
3898                  <value>3</value>
3899                </enumeratedValue>
3900              </enumeratedValues>
3901            </field>
3902          </fields>
3903        </register>
3904        <register>
3905          <name>PWR_DELAY_CTL</name>
3906          <description>SRAM power switch power up &amp; sequence delay</description>
3907          <addressOffset>0x280</addressOffset>
3908          <size>32</size>
3909          <access>read-write</access>
3910          <resetValue>0x9020009</resetValue>
3911          <resetMask>0xFFFF03FF</resetMask>
3912          <fields>
3913            <field>
3914              <name>UP</name>
3915              <description>Number of IMO clock cycles delay needed after power domain power up</description>
3916              <bitRange>[9:0]</bitRange>
3917              <access>read-write</access>
3918            </field>
3919            <field>
3920              <name>SEQ0_DELAY</name>
3921              <description>Number of IMO clock cycles delay needed for sequence-0 of SRAM power transition</description>
3922              <bitRange>[23:16]</bitRange>
3923              <access>read-write</access>
3924            </field>
3925            <field>
3926              <name>SEQ1_DELAY</name>
3927              <description>Number of IMO clock cycles delay needed for sequence-1 of SRAM power transition</description>
3928              <bitRange>[31:24]</bitRange>
3929              <access>read-write</access>
3930            </field>
3931          </fields>
3932        </register>
3933        <cluster>
3934          <name>MPC</name>
3935          <description>MPC Memory Protection Controller registers</description>
3936          <addressOffset>0x00004000</addressOffset>
3937          <register>
3938            <name>CFG</name>
3939            <description>Config register with error response, RegionID PPC_MPC_MAIN is the security owner PC. The error response configuration is located in CFG.RESPONSE, only one such configuration exists applying to all protection contexts in the system.</description>
3940            <addressOffset>0x0</addressOffset>
3941            <size>32</size>
3942            <access>read-write</access>
3943            <resetValue>0x0</resetValue>
3944            <resetMask>0x10</resetMask>
3945            <fields>
3946              <field>
3947                <name>RESPONSE</name>
3948                <description>Response Configuration for Security and PC violations
39490: Read-Zero Write Ignore (RAZ/WI)
39501: Bus Error</description>
3951                <bitRange>[4:4]</bitRange>
3952                <access>read-write</access>
3953              </field>
3954            </fields>
3955          </register>
3956          <register>
3957            <name>INTR</name>
3958            <description>Interrupt</description>
3959            <addressOffset>0x10</addressOffset>
3960            <size>32</size>
3961            <access>read-write</access>
3962            <resetValue>0x0</resetValue>
3963            <resetMask>0x1</resetMask>
3964            <fields>
3965              <field>
3966                <name>VIOLATION</name>
3967                <description>HW sets this field to '1', when a security violation is detected.
3968SW writes '1' to this field to clear</description>
3969                <bitRange>[0:0]</bitRange>
3970                <access>read-write</access>
3971              </field>
3972            </fields>
3973          </register>
3974          <register>
3975            <name>INTR_SET</name>
3976            <description>Interrupt set</description>
3977            <addressOffset>0x14</addressOffset>
3978            <size>32</size>
3979            <access>read-write</access>
3980            <resetValue>0x0</resetValue>
3981            <resetMask>0x1</resetMask>
3982            <fields>
3983              <field>
3984                <name>VIOLATION</name>
3985                <description>SW write this field with '1' to set INTR register (a write of '0' has no effect).</description>
3986                <bitRange>[0:0]</bitRange>
3987                <access>read-write</access>
3988              </field>
3989            </fields>
3990          </register>
3991          <register>
3992            <name>INTR_MASK</name>
3993            <description>Interrupt mask</description>
3994            <addressOffset>0x18</addressOffset>
3995            <size>32</size>
3996            <access>read-write</access>
3997            <resetValue>0x0</resetValue>
3998            <resetMask>0x1</resetMask>
3999            <fields>
4000              <field>
4001                <name>VIOLATION</name>
4002                <description>Mask for corresponding field in INTR register.</description>
4003                <bitRange>[0:0]</bitRange>
4004                <access>read-write</access>
4005              </field>
4006            </fields>
4007          </register>
4008          <register>
4009            <name>INTR_MASKED</name>
4010            <description>Interrupt masked</description>
4011            <addressOffset>0x1C</addressOffset>
4012            <size>32</size>
4013            <access>read-only</access>
4014            <resetValue>0x0</resetValue>
4015            <resetMask>0x1</resetMask>
4016            <fields>
4017              <field>
4018                <name>VIOLATION</name>
4019                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
4020                <bitRange>[0:0]</bitRange>
4021                <access>read-only</access>
4022              </field>
4023            </fields>
4024          </register>
4025          <register>
4026            <name>INTR_INFO1</name>
4027            <description>Infor about violation</description>
4028            <addressOffset>0x20</addressOffset>
4029            <size>32</size>
4030            <access>read-only</access>
4031            <resetValue>0x0</resetValue>
4032            <resetMask>0xFFFFFFFF</resetMask>
4033            <fields>
4034              <field>
4035                <name>VALUE</name>
4036                <description>Full address of the access that caused violation</description>
4037                <bitRange>[31:0]</bitRange>
4038                <access>read-only</access>
4039              </field>
4040            </fields>
4041          </register>
4042          <register>
4043            <name>INTR_INFO2</name>
4044            <description>Infor about violation</description>
4045            <addressOffset>0x24</addressOffset>
4046            <size>32</size>
4047            <access>read-only</access>
4048            <resetValue>0x0</resetValue>
4049            <resetMask>0xCF07FFFF</resetMask>
4050            <fields>
4051              <field>
4052                <name>HMASTER</name>
4053                <description>The master ID of the master that made the access causing the violation (taken from the AHB HMASTER signal)</description>
4054                <bitRange>[15:0]</bitRange>
4055                <access>read-only</access>
4056              </field>
4057              <field>
4058                <name>HNONSEC</name>
4059                <description>The security status of the access address causing the violation (taken from the AHB5 HNONSEC signal).</description>
4060                <bitRange>[16:16]</bitRange>
4061                <access>read-only</access>
4062              </field>
4063              <field>
4064                <name>CFG_NS</name>
4065                <description>The secure/non-secure configuration of the block access attempt causing the violation.</description>
4066                <bitRange>[17:17]</bitRange>
4067                <access>read-only</access>
4068              </field>
4069              <field>
4070                <name>HWRITE</name>
4071                <description>The R/W status from which the violating access was made.</description>
4072                <bitRange>[18:18]</bitRange>
4073                <access>read-only</access>
4074              </field>
4075              <field>
4076                <name>HAUSER</name>
4077                <description>The protection context from which the violating access was made (taken from the AHB5 HAUSER signal).</description>
4078                <bitRange>[27:24]</bitRange>
4079                <access>read-only</access>
4080              </field>
4081              <field>
4082                <name>SECURITY_VIOLATION</name>
4083                <description>This bit is set when a secure access was done to a non-secure block of memory, or a non-secure access was done to a secure block of memory.</description>
4084                <bitRange>[30:30]</bitRange>
4085                <access>read-only</access>
4086              </field>
4087              <field>
4088                <name>ACCESS_VIOLATION</name>
4089                <description>This bit is set when a read or write transaction was done from a protection context that does not have access to this block of memory.</description>
4090                <bitRange>[31:31]</bitRange>
4091                <access>read-only</access>
4092              </field>
4093            </fields>
4094          </register>
4095          <register>
4096            <name>CTRL</name>
4097            <description>Control register with lock bit and auto-increment only (Separate CTRL for each PC depends on access_pc)</description>
4098            <addressOffset>0x100</addressOffset>
4099            <size>32</size>
4100            <access>read-write</access>
4101            <resetValue>0x100</resetValue>
4102            <resetMask>0x80000100</resetMask>
4103            <fields>
4104              <field>
4105                <name>AUTO_INC</name>
4106                <description>Auto-increment BLK_IDX by 1 for this protection context as a side effect of each read/write access to BLK_LUT</description>
4107                <bitRange>[8:8]</bitRange>
4108                <access>read-write</access>
4109              </field>
4110              <field>
4111                <name>LOCK</name>
4112                <description>Security lockdown for this protection context. Software can set this bit but not clear it once set.  When set, write operations to BLK_LUT are not possible  from this protection context. Setting LOCK also blocks writes to CTRL itself (for that PC copy). All writes are ignored.</description>
4113                <bitRange>[31:31]</bitRange>
4114                <access>read-write</access>
4115              </field>
4116            </fields>
4117          </register>
4118          <register>
4119            <name>BLK_MAX</name>
4120            <description>Max value of block-based index register</description>
4121            <addressOffset>0x104</addressOffset>
4122            <size>32</size>
4123            <access>read-only</access>
4124            <resetValue>0x0</resetValue>
4125            <resetMask>0xFFFFFFFF</resetMask>
4126            <fields>
4127              <field>
4128                <name>VALUE</name>
4129                <description>Maximum value of block-based index register.  The number and size blocks in an MPC is design time configurable and for embedded memories defaults to covering the entire memory using 4kB blocks; See product datasheet for details on protection of external memories.</description>
4130                <bitRange>[31:0]</bitRange>
4131                <access>read-only</access>
4132              </field>
4133            </fields>
4134          </register>
4135          <register>
4136            <name>BLK_CFG</name>
4137            <description>Block size &amp; initialization in progress</description>
4138            <addressOffset>0x108</addressOffset>
4139            <size>32</size>
4140            <access>read-only</access>
4141            <resetValue>0x80000000</resetValue>
4142            <resetMask>0x8000000F</resetMask>
4143            <fields>
4144              <field>
4145                <name>BLOCK_SIZE</name>
4146                <description>Block size of individually protected blocks (0: 32B, 1: 64B, ... up to 15: 1MB)
4147Block size= (1&lt;&lt;(BLOCK_SIZE+5))
4148The number and size blocks in an MPC is design time configurable and for embedded memories defaults to covering the entire memory using 4kB blocks; see product datasheet for details on protection of external memories.</description>
4149                <bitRange>[3:0]</bitRange>
4150                <access>read-only</access>
4151              </field>
4152              <field>
4153                <name>INIT_IN_PROGRESS</name>
4154                <description>During initialization INIT_IN_PROGRESS is '1' and MMIO register accesses to BLK_LUT is blocked (BLK_IDX increment is also ignored). The block attributes are retained in DeepSleep (and obviously Active) power mode. Initialization is only required from a power mode in which the block attributes are not retained. E.g., initialization is required for a cold boot (after a Power-on-Reset).
4155HW initializes the block attributes: the NS attributes are set to '0' (secure), the R attributes are set to '1' (read access allowed) and the W attributes are set to '1' (write access allowed). During initialization, the MPC supports memory accesses (memory accesses are NOT blocked) with the initialization block attribute values as mentioned above. This e.g. allows MPC initialization to proceed in parallel with boot program memory accesses (as opposed to serializing the two), improving device boot time.
4156HW initializes the block attributes NS to 1 in case SECEXT = 0.</description>
4157                <bitRange>[31:31]</bitRange>
4158                <access>read-only</access>
4159              </field>
4160            </fields>
4161          </register>
4162          <register>
4163            <name>BLK_IDX</name>
4164            <description>Index of 32-block group accessed through BLK_LUT (Separate IDX for each PC depending on access_pc)</description>
4165            <addressOffset>0x10C</addressOffset>
4166            <size>32</size>
4167            <access>read-write</access>
4168            <resetValue>0x0</resetValue>
4169            <resetMask>0xFFFFFFFF</resetMask>
4170            <fields>
4171              <field>
4172                <name>VALUE</name>
4173                <description>Index value for accessing block-based lookup table using BLK_LUT. Programming out of LUT range is an user error and it loops back to '0' once overflow occurs.</description>
4174                <bitRange>[31:0]</bitRange>
4175                <access>read-write</access>
4176              </field>
4177            </fields>
4178          </register>
4179          <register>
4180            <name>BLK_LUT</name>
4181            <description>NS status for 32 blocks at BLK_IDX with PC=&lt;access_pc&gt;</description>
4182            <addressOffset>0x110</addressOffset>
4183            <size>32</size>
4184            <access>read-write</access>
4185            <resetValue>0x0</resetValue>
4186            <resetMask>0xFFFFFFFF</resetMask>
4187            <fields>
4188              <field>
4189                <name>ATTR_NS0</name>
4190                <description>NS bit for block 0 based on BLK_IDX</description>
4191                <bitRange>[0:0]</bitRange>
4192                <access>read-write</access>
4193              </field>
4194              <field>
4195                <name>ATTR_NS1</name>
4196                <description>NS bit for block 1 based on BLK_IDX</description>
4197                <bitRange>[1:1]</bitRange>
4198                <access>read-write</access>
4199              </field>
4200              <field>
4201                <name>ATTR_NS2</name>
4202                <description>NS bit for block 2 based on BLK_IDX</description>
4203                <bitRange>[2:2]</bitRange>
4204                <access>read-write</access>
4205              </field>
4206              <field>
4207                <name>ATTR_NS3</name>
4208                <description>NS bit for block 3 based on BLK_IDX</description>
4209                <bitRange>[3:3]</bitRange>
4210                <access>read-write</access>
4211              </field>
4212              <field>
4213                <name>ATTR_NS4</name>
4214                <description>NS bit for block 4 based on BLK_IDX</description>
4215                <bitRange>[4:4]</bitRange>
4216                <access>read-write</access>
4217              </field>
4218              <field>
4219                <name>ATTR_NS5</name>
4220                <description>NS bit for block 5 based on BLK_IDX</description>
4221                <bitRange>[5:5]</bitRange>
4222                <access>read-write</access>
4223              </field>
4224              <field>
4225                <name>ATTR_NS6</name>
4226                <description>NS bit for block 6 based on BLK_IDX</description>
4227                <bitRange>[6:6]</bitRange>
4228                <access>read-write</access>
4229              </field>
4230              <field>
4231                <name>ATTR_NS7</name>
4232                <description>NS bit for block 7 based on BLK_IDX</description>
4233                <bitRange>[7:7]</bitRange>
4234                <access>read-write</access>
4235              </field>
4236              <field>
4237                <name>ATTR_NS8</name>
4238                <description>NS bit for block 8 based on BLK_IDX</description>
4239                <bitRange>[8:8]</bitRange>
4240                <access>read-write</access>
4241              </field>
4242              <field>
4243                <name>ATTR_NS9</name>
4244                <description>NS bit for block 9 based on BLK_IDX</description>
4245                <bitRange>[9:9]</bitRange>
4246                <access>read-write</access>
4247              </field>
4248              <field>
4249                <name>ATTR_NS10</name>
4250                <description>NS bit for block 10 based on BLK_IDX</description>
4251                <bitRange>[10:10]</bitRange>
4252                <access>read-write</access>
4253              </field>
4254              <field>
4255                <name>ATTR_NS11</name>
4256                <description>NS bit for block 11 based on BLK_IDX</description>
4257                <bitRange>[11:11]</bitRange>
4258                <access>read-write</access>
4259              </field>
4260              <field>
4261                <name>ATTR_NS12</name>
4262                <description>NS bit for block 12 based on BLK_IDX</description>
4263                <bitRange>[12:12]</bitRange>
4264                <access>read-write</access>
4265              </field>
4266              <field>
4267                <name>ATTR_NS13</name>
4268                <description>NS bit for block 13 based on BLK_IDX</description>
4269                <bitRange>[13:13]</bitRange>
4270                <access>read-write</access>
4271              </field>
4272              <field>
4273                <name>ATTR_NS14</name>
4274                <description>NS bit for block 14 based on BLK_IDX</description>
4275                <bitRange>[14:14]</bitRange>
4276                <access>read-write</access>
4277              </field>
4278              <field>
4279                <name>ATTR_NS15</name>
4280                <description>NS bit for block 15 based on BLK_IDX</description>
4281                <bitRange>[15:15]</bitRange>
4282                <access>read-write</access>
4283              </field>
4284              <field>
4285                <name>ATTR_NS16</name>
4286                <description>NS bit for block 16 based on BLK_IDX</description>
4287                <bitRange>[16:16]</bitRange>
4288                <access>read-write</access>
4289              </field>
4290              <field>
4291                <name>ATTR_NS17</name>
4292                <description>NS bit for block 17 based on BLK_IDX</description>
4293                <bitRange>[17:17]</bitRange>
4294                <access>read-write</access>
4295              </field>
4296              <field>
4297                <name>ATTR_NS18</name>
4298                <description>NS bit for block 18 based on BLK_IDX</description>
4299                <bitRange>[18:18]</bitRange>
4300                <access>read-write</access>
4301              </field>
4302              <field>
4303                <name>ATTR_NS19</name>
4304                <description>NS bit for block 19 based on BLK_IDX</description>
4305                <bitRange>[19:19]</bitRange>
4306                <access>read-write</access>
4307              </field>
4308              <field>
4309                <name>ATTR_NS20</name>
4310                <description>NS bit for block 20 based on BLK_IDX</description>
4311                <bitRange>[20:20]</bitRange>
4312                <access>read-write</access>
4313              </field>
4314              <field>
4315                <name>ATTR_NS21</name>
4316                <description>NS bit for block 21 based on BLK_IDX</description>
4317                <bitRange>[21:21]</bitRange>
4318                <access>read-write</access>
4319              </field>
4320              <field>
4321                <name>ATTR_NS22</name>
4322                <description>NS bit for block 22 based on BLK_IDX</description>
4323                <bitRange>[22:22]</bitRange>
4324                <access>read-write</access>
4325              </field>
4326              <field>
4327                <name>ATTR_NS23</name>
4328                <description>NS bit for block 23 based on BLK_IDX</description>
4329                <bitRange>[23:23]</bitRange>
4330                <access>read-write</access>
4331              </field>
4332              <field>
4333                <name>ATTR_NS24</name>
4334                <description>NS bit for block 24 based on BLK_IDX</description>
4335                <bitRange>[24:24]</bitRange>
4336                <access>read-write</access>
4337              </field>
4338              <field>
4339                <name>ATTR_NS25</name>
4340                <description>NS bit for block 25 based on BLK_IDX</description>
4341                <bitRange>[25:25]</bitRange>
4342                <access>read-write</access>
4343              </field>
4344              <field>
4345                <name>ATTR_NS26</name>
4346                <description>NS bit for block 26 based on BLK_IDX</description>
4347                <bitRange>[26:26]</bitRange>
4348                <access>read-write</access>
4349              </field>
4350              <field>
4351                <name>ATTR_NS27</name>
4352                <description>NS bit for block 27 based on BLK_IDX</description>
4353                <bitRange>[27:27]</bitRange>
4354                <access>read-write</access>
4355              </field>
4356              <field>
4357                <name>ATTR_NS28</name>
4358                <description>NS bit for block 28 based on BLK_IDX</description>
4359                <bitRange>[28:28]</bitRange>
4360                <access>read-write</access>
4361              </field>
4362              <field>
4363                <name>ATTR_NS29</name>
4364                <description>NS bit for block 29 based on BLK_IDX</description>
4365                <bitRange>[29:29]</bitRange>
4366                <access>read-write</access>
4367              </field>
4368              <field>
4369                <name>ATTR_NS30</name>
4370                <description>NS bit for block 30 based on BLK_IDX</description>
4371                <bitRange>[30:30]</bitRange>
4372                <access>read-write</access>
4373              </field>
4374              <field>
4375                <name>ATTR_NS31</name>
4376                <description>NS bit for block 31 based on BLK_IDX</description>
4377                <bitRange>[31:31]</bitRange>
4378                <access>read-write</access>
4379              </field>
4380            </fields>
4381          </register>
4382          <register>
4383            <name>ROT_CTRL</name>
4384            <description>Control register with lock bit and auto-increment only</description>
4385            <addressOffset>0x200</addressOffset>
4386            <size>32</size>
4387            <access>read-write</access>
4388            <resetValue>0x100</resetValue>
4389            <resetMask>0x80000100</resetMask>
4390            <fields>
4391              <field>
4392                <name>AUTO_INC</name>
4393                <description>Auto-increment BLK_IDX by 1 for each read/write of ROT_BLK_LUT</description>
4394                <bitRange>[8:8]</bitRange>
4395                <access>read-write</access>
4396              </field>
4397              <field>
4398                <name>LOCK</name>
4399                <description>Security lockdown for the root-of-trust configuration registers. Software can set this bit but not clear it once set.  When set, write operations to ROT_BLK_LUT are not possible. Write is ignored.</description>
4400                <bitRange>[31:31]</bitRange>
4401                <access>read-write</access>
4402              </field>
4403            </fields>
4404          </register>
4405          <register>
4406            <name>ROT_CFG</name>
4407            <description>Sets block-size to match memory size (external memory only)</description>
4408            <addressOffset>0x204</addressOffset>
4409            <size>32</size>
4410            <access>read-write</access>
4411            <resetValue>0x0</resetValue>
4412            <resetMask>0xF</resetMask>
4413            <fields>
4414              <field>
4415                <name>BLOCK_SIZE</name>
4416                <description>Block size of individually protected blocks (0: 32B, 1: 64B, ...up to 15:1 MB)
4417Block size= (1&lt;&lt;(BLOCK_SIZE+5))
4418The number and size blocks in an MPC is design time configurable and for external memories defaults to covering the entire memory using 4kB blocks; see product datasheet for details on protection of external memories.</description>
4419                <bitRange>[3:0]</bitRange>
4420                <access>read-write</access>
4421              </field>
4422            </fields>
4423          </register>
4424          <register>
4425            <name>ROT_BLK_MAX</name>
4426            <description>Max value of block-based index register for ROT</description>
4427            <addressOffset>0x208</addressOffset>
4428            <size>32</size>
4429            <access>read-only</access>
4430            <resetValue>0x0</resetValue>
4431            <resetMask>0xFFFFFFFF</resetMask>
4432            <fields>
4433              <field>
4434                <name>VALUE</name>
4435                <description>Maximum value of block-based index register.  The number and size blocks in an MPC is design time configurable and for embedded memories defaults to covering the entire memory using 4kB blocks; see product datasheet for details on protection of external memories.</description>
4436                <bitRange>[31:0]</bitRange>
4437                <access>read-only</access>
4438              </field>
4439            </fields>
4440          </register>
4441          <register>
4442            <name>ROT_BLK_CFG</name>
4443            <description>Same as BLK_CFG</description>
4444            <addressOffset>0x20C</addressOffset>
4445            <size>32</size>
4446            <access>read-only</access>
4447            <resetValue>0x80000000</resetValue>
4448            <resetMask>0x8000000F</resetMask>
4449            <fields>
4450              <field>
4451                <name>BLOCK_SIZE</name>
4452                <description>Block size of individually protected blocks (0: 32B, 1: 64B, ...up to 15:1MB)
4453Block size= (1&lt;&lt;(BLOCK_SIZE+5))
4454The number and size blocks in an MPC is design time configurable and for embedded memories defaults to covering the entire memory using 4kB blocks; see product datasheet for details on protection of external memories.</description>
4455                <bitRange>[3:0]</bitRange>
4456                <access>read-only</access>
4457              </field>
4458              <field>
4459                <name>INIT_IN_PROGRESS</name>
4460                <description>During initialization INIT_IN_PROGRESS is '1' and MMIO register accesses to ROT_BLK_LUT is RAZWI. The block attributes are retained in DeepSleep (and obviously Active) power mode. Initialization is only required from a power mode in which the block attributes are not retained. E.g., initialization is required for a cold boot (after a Power-on-Reset).
4461HW initializes the block attributes: the NS attributes are set to '0' (secure), the R attributes are set to '1' (read access allowed) and the W attributes are set to '1' (write access allowed). During initialization, the MPC supports memory accesses (memory accesses are NOT blocked) with the initialization block attribute values as mentioned above. This e.g. allows MPC initialization to proceed in parallel with boot program memory accesses (as opposed to serializing the two), improving device boot time.
4462HW initializes the block attributes NS to 1 in case SECEXT = 0.</description>
4463                <bitRange>[31:31]</bitRange>
4464                <access>read-only</access>
4465              </field>
4466            </fields>
4467          </register>
4468          <register>
4469            <name>ROT_BLK_IDX</name>
4470            <description>Index of 8-block group accessed through ROT_BLK_LUT_*</description>
4471            <addressOffset>0x210</addressOffset>
4472            <size>32</size>
4473            <access>read-write</access>
4474            <resetValue>0x0</resetValue>
4475            <resetMask>0xFFFFFFFF</resetMask>
4476            <fields>
4477              <field>
4478                <name>VALUE</name>
4479                <description>Index value for accessing block-based lookup table using ROT_BLK_LUT. Programming out of LUT range is an user error and it loops back to '0' once overflow occurs.</description>
4480                <bitRange>[31:0]</bitRange>
4481                <access>read-write</access>
4482              </field>
4483            </fields>
4484          </register>
4485          <register>
4486            <name>ROT_BLK_PC</name>
4487            <description>Protection context of 8-block group accesses through ROT_BLK_LUT</description>
4488            <addressOffset>0x214</addressOffset>
4489            <size>32</size>
4490            <access>read-write</access>
4491            <resetValue>0x0</resetValue>
4492            <resetMask>0xF</resetMask>
4493            <fields>
4494              <field>
4495                <name>PC</name>
4496                <description>Specify PC values for ROT_BLK_IDX and ROT_BLK_LUT</description>
4497                <bitRange>[3:0]</bitRange>
4498                <access>read-write</access>
4499              </field>
4500            </fields>
4501          </register>
4502          <register>
4503            <name>ROT_BLK_LUT</name>
4504            <description>(R,W,NS) bits for 8 blocks at ROT_BLK_IDX for PC=ROT_BKL_PC</description>
4505            <addressOffset>0x218</addressOffset>
4506            <size>32</size>
4507            <access>read-write</access>
4508            <resetValue>0x0</resetValue>
4509            <resetMask>0x77777777</resetMask>
4510            <fields>
4511              <field>
4512                <name>ATTR0</name>
4513                <description>W/R/NS bits for block 0 indicated by ROT_BLK_IDX for ROT_BLK_PC PC</description>
4514                <bitRange>[2:0]</bitRange>
4515                <access>read-write</access>
4516              </field>
4517              <field>
4518                <name>ATTR1</name>
4519                <description>W/R/NS bits for block 1 indicated by ROT_BLK_IDX for ROT_BLK_PC PC</description>
4520                <bitRange>[6:4]</bitRange>
4521                <access>read-write</access>
4522              </field>
4523              <field>
4524                <name>ATTR2</name>
4525                <description>W/R/NS bits for block 2 indicated by ROT_BLK_IDX for ROT_BLK_PC PC</description>
4526                <bitRange>[10:8]</bitRange>
4527                <access>read-write</access>
4528              </field>
4529              <field>
4530                <name>ATTR3</name>
4531                <description>W/R/NS bits for block 3 indicated by ROT_BLK_IDX for ROT_BLK_PC PC</description>
4532                <bitRange>[14:12]</bitRange>
4533                <access>read-write</access>
4534              </field>
4535              <field>
4536                <name>ATTR4</name>
4537                <description>W/R/NS bits for block 4 indicated by ROT_BLK_IDX for ROT_BLK_PC PC</description>
4538                <bitRange>[18:16]</bitRange>
4539                <access>read-write</access>
4540              </field>
4541              <field>
4542                <name>ATTR5</name>
4543                <description>W/R/NS bits for block 5 indicated by ROT_BLK_IDX for ROT_BLK_PC PC</description>
4544                <bitRange>[22:20]</bitRange>
4545                <access>read-write</access>
4546              </field>
4547              <field>
4548                <name>ATTR6</name>
4549                <description>W/R/NS bits for block 6 indicated by ROT_BLK_IDX for ROT_BLK_PC PC</description>
4550                <bitRange>[26:24]</bitRange>
4551                <access>read-write</access>
4552              </field>
4553              <field>
4554                <name>ATTR7</name>
4555                <description>W/R/NS bits for block 7 indicated by ROT_BLK_IDX for ROT_BLK_PC PC</description>
4556                <bitRange>[30:28]</bitRange>
4557                <access>read-write</access>
4558              </field>
4559            </fields>
4560          </register>
4561        </cluster>
4562      </registers>
4563    </peripheral>
4564    <peripheral>
4565      <name>PROMC</name>
4566      <description>Patchable ROM Controller</description>
4567      <baseAddress>0x40140000</baseAddress>
4568      <addressBlock>
4569        <offset>0</offset>
4570        <size>65536</size>
4571        <usage>registers</usage>
4572      </addressBlock>
4573      <registers>
4574        <register>
4575          <name>CTL</name>
4576          <description>Control</description>
4577          <addressOffset>0x0</addressOffset>
4578          <size>32</size>
4579          <access>read-write</access>
4580          <resetValue>0x0</resetValue>
4581          <resetMask>0x3</resetMask>
4582          <fields>
4583            <field>
4584              <name>ROM_WS</name>
4585              <description>Wait states.</description>
4586              <bitRange>[1:0]</bitRange>
4587              <access>read-write</access>
4588              <enumeratedValues>
4589                <enumeratedValue>
4590                  <name>WS_0</name>
4591                  <description>N/A</description>
4592                  <value>0</value>
4593                </enumeratedValue>
4594                <enumeratedValue>
4595                  <name>WS_1</name>
4596                  <description>N/A</description>
4597                  <value>1</value>
4598                </enumeratedValue>
4599                <enumeratedValue>
4600                  <name>WS_2</name>
4601                  <description>N/A</description>
4602                  <value>2</value>
4603                </enumeratedValue>
4604                <enumeratedValue>
4605                  <name>WS_3</name>
4606                  <description>N/A</description>
4607                  <value>3</value>
4608                </enumeratedValue>
4609              </enumeratedValues>
4610            </field>
4611          </fields>
4612        </register>
4613        <cluster>
4614          <name>MPC</name>
4615          <description>MPC Memory Protection Controller registers</description>
4616          <addressOffset>0x00001000</addressOffset>
4617          <register>
4618            <name>CFG</name>
4619            <description>Config register with error response, RegionID PPC_MPC_MAIN is the security owner PC. The error response configuration is located in CFG.RESPONSE, only one such configuration exists applying to all protection contexts in the system.</description>
4620            <addressOffset>0x0</addressOffset>
4621            <size>32</size>
4622            <access>read-write</access>
4623            <resetValue>0x0</resetValue>
4624            <resetMask>0x10</resetMask>
4625            <fields>
4626              <field>
4627                <name>RESPONSE</name>
4628                <description>Response Configuration for Security and PC violations
46290: Read-Zero Write Ignore (RAZ/WI)
46301: Bus Error</description>
4631                <bitRange>[4:4]</bitRange>
4632                <access>read-write</access>
4633              </field>
4634            </fields>
4635          </register>
4636          <register>
4637            <name>INTR</name>
4638            <description>Interrupt</description>
4639            <addressOffset>0x10</addressOffset>
4640            <size>32</size>
4641            <access>read-write</access>
4642            <resetValue>0x0</resetValue>
4643            <resetMask>0x1</resetMask>
4644            <fields>
4645              <field>
4646                <name>VIOLATION</name>
4647                <description>HW sets this field to '1', when a security violation is detected.
4648SW writes '1' to this field to clear</description>
4649                <bitRange>[0:0]</bitRange>
4650                <access>read-write</access>
4651              </field>
4652            </fields>
4653          </register>
4654          <register>
4655            <name>INTR_SET</name>
4656            <description>Interrupt set</description>
4657            <addressOffset>0x14</addressOffset>
4658            <size>32</size>
4659            <access>read-write</access>
4660            <resetValue>0x0</resetValue>
4661            <resetMask>0x1</resetMask>
4662            <fields>
4663              <field>
4664                <name>VIOLATION</name>
4665                <description>SW write this field with '1' to set INTR register (a write of '0' has no effect).</description>
4666                <bitRange>[0:0]</bitRange>
4667                <access>read-write</access>
4668              </field>
4669            </fields>
4670          </register>
4671          <register>
4672            <name>INTR_MASK</name>
4673            <description>Interrupt mask</description>
4674            <addressOffset>0x18</addressOffset>
4675            <size>32</size>
4676            <access>read-write</access>
4677            <resetValue>0x0</resetValue>
4678            <resetMask>0x1</resetMask>
4679            <fields>
4680              <field>
4681                <name>VIOLATION</name>
4682                <description>Mask for corresponding field in INTR register.</description>
4683                <bitRange>[0:0]</bitRange>
4684                <access>read-write</access>
4685              </field>
4686            </fields>
4687          </register>
4688          <register>
4689            <name>INTR_MASKED</name>
4690            <description>Interrupt masked</description>
4691            <addressOffset>0x1C</addressOffset>
4692            <size>32</size>
4693            <access>read-only</access>
4694            <resetValue>0x0</resetValue>
4695            <resetMask>0x1</resetMask>
4696            <fields>
4697              <field>
4698                <name>VIOLATION</name>
4699                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
4700                <bitRange>[0:0]</bitRange>
4701                <access>read-only</access>
4702              </field>
4703            </fields>
4704          </register>
4705          <register>
4706            <name>INTR_INFO1</name>
4707            <description>Infor about violation</description>
4708            <addressOffset>0x20</addressOffset>
4709            <size>32</size>
4710            <access>read-only</access>
4711            <resetValue>0x0</resetValue>
4712            <resetMask>0xFFFFFFFF</resetMask>
4713            <fields>
4714              <field>
4715                <name>VALUE</name>
4716                <description>Full address of the access that caused violation</description>
4717                <bitRange>[31:0]</bitRange>
4718                <access>read-only</access>
4719              </field>
4720            </fields>
4721          </register>
4722          <register>
4723            <name>INTR_INFO2</name>
4724            <description>Infor about violation</description>
4725            <addressOffset>0x24</addressOffset>
4726            <size>32</size>
4727            <access>read-only</access>
4728            <resetValue>0x0</resetValue>
4729            <resetMask>0xCF07FFFF</resetMask>
4730            <fields>
4731              <field>
4732                <name>HMASTER</name>
4733                <description>The master ID of the master that made the access causing the violation (taken from the AHB HMASTER signal)</description>
4734                <bitRange>[15:0]</bitRange>
4735                <access>read-only</access>
4736              </field>
4737              <field>
4738                <name>HNONSEC</name>
4739                <description>The security status of the access address causing the violation (taken from the AHB5 HNONSEC signal).</description>
4740                <bitRange>[16:16]</bitRange>
4741                <access>read-only</access>
4742              </field>
4743              <field>
4744                <name>CFG_NS</name>
4745                <description>The secure/non-secure configuration of the block access attempt causing the violation.</description>
4746                <bitRange>[17:17]</bitRange>
4747                <access>read-only</access>
4748              </field>
4749              <field>
4750                <name>HWRITE</name>
4751                <description>The R/W status from which the violating access was made.</description>
4752                <bitRange>[18:18]</bitRange>
4753                <access>read-only</access>
4754              </field>
4755              <field>
4756                <name>HAUSER</name>
4757                <description>The protection context from which the violating access was made (taken from the AHB5 HAUSER signal).</description>
4758                <bitRange>[27:24]</bitRange>
4759                <access>read-only</access>
4760              </field>
4761              <field>
4762                <name>SECURITY_VIOLATION</name>
4763                <description>This bit is set when a secure access was done to a non-secure block of memory, or a non-secure access was done to a secure block of memory.</description>
4764                <bitRange>[30:30]</bitRange>
4765                <access>read-only</access>
4766              </field>
4767              <field>
4768                <name>ACCESS_VIOLATION</name>
4769                <description>This bit is set when a read or write transaction was done from a protection context that does not have access to this block of memory.</description>
4770                <bitRange>[31:31]</bitRange>
4771                <access>read-only</access>
4772              </field>
4773            </fields>
4774          </register>
4775          <register>
4776            <name>CTRL</name>
4777            <description>Control register with lock bit and auto-increment only (Separate CTRL for each PC depends on access_pc)</description>
4778            <addressOffset>0x100</addressOffset>
4779            <size>32</size>
4780            <access>read-write</access>
4781            <resetValue>0x100</resetValue>
4782            <resetMask>0x80000100</resetMask>
4783            <fields>
4784              <field>
4785                <name>AUTO_INC</name>
4786                <description>Auto-increment BLK_IDX by 1 for this protection context as a side effect of each read/write access to BLK_LUT</description>
4787                <bitRange>[8:8]</bitRange>
4788                <access>read-write</access>
4789              </field>
4790              <field>
4791                <name>LOCK</name>
4792                <description>Security lockdown for this protection context. Software can set this bit but not clear it once set.  When set, write operations to BLK_LUT are not possible  from this protection context. Setting LOCK also blocks writes to CTRL itself (for that PC copy). All writes are ignored.</description>
4793                <bitRange>[31:31]</bitRange>
4794                <access>read-write</access>
4795              </field>
4796            </fields>
4797          </register>
4798          <register>
4799            <name>BLK_MAX</name>
4800            <description>Max value of block-based index register</description>
4801            <addressOffset>0x104</addressOffset>
4802            <size>32</size>
4803            <access>read-only</access>
4804            <resetValue>0x0</resetValue>
4805            <resetMask>0xFFFFFFFF</resetMask>
4806            <fields>
4807              <field>
4808                <name>VALUE</name>
4809                <description>Maximum value of block-based index register.  The number and size blocks in an MPC is design time configurable and for embedded memories defaults to covering the entire memory using 4kB blocks; See product datasheet for details on protection of external memories.</description>
4810                <bitRange>[31:0]</bitRange>
4811                <access>read-only</access>
4812              </field>
4813            </fields>
4814          </register>
4815          <register>
4816            <name>BLK_CFG</name>
4817            <description>Block size &amp; initialization in progress</description>
4818            <addressOffset>0x108</addressOffset>
4819            <size>32</size>
4820            <access>read-only</access>
4821            <resetValue>0x80000000</resetValue>
4822            <resetMask>0x8000000F</resetMask>
4823            <fields>
4824              <field>
4825                <name>BLOCK_SIZE</name>
4826                <description>Block size of individually protected blocks (0: 32B, 1: 64B, ... up to 15: 1MB)
4827Block size= (1&lt;&lt;(BLOCK_SIZE+5))
4828The number and size blocks in an MPC is design time configurable and for embedded memories defaults to covering the entire memory using 4kB blocks; see product datasheet for details on protection of external memories.</description>
4829                <bitRange>[3:0]</bitRange>
4830                <access>read-only</access>
4831              </field>
4832              <field>
4833                <name>INIT_IN_PROGRESS</name>
4834                <description>During initialization INIT_IN_PROGRESS is '1' and MMIO register accesses to BLK_LUT is blocked (BLK_IDX increment is also ignored). The block attributes are retained in DeepSleep (and obviously Active) power mode. Initialization is only required from a power mode in which the block attributes are not retained. E.g., initialization is required for a cold boot (after a Power-on-Reset).
4835HW initializes the block attributes: the NS attributes are set to '0' (secure), the R attributes are set to '1' (read access allowed) and the W attributes are set to '1' (write access allowed). During initialization, the MPC supports memory accesses (memory accesses are NOT blocked) with the initialization block attribute values as mentioned above. This e.g. allows MPC initialization to proceed in parallel with boot program memory accesses (as opposed to serializing the two), improving device boot time.
4836HW initializes the block attributes NS to 1 in case SECEXT = 0.</description>
4837                <bitRange>[31:31]</bitRange>
4838                <access>read-only</access>
4839              </field>
4840            </fields>
4841          </register>
4842          <register>
4843            <name>BLK_IDX</name>
4844            <description>Index of 32-block group accessed through BLK_LUT (Separate IDX for each PC depending on access_pc)</description>
4845            <addressOffset>0x10C</addressOffset>
4846            <size>32</size>
4847            <access>read-write</access>
4848            <resetValue>0x0</resetValue>
4849            <resetMask>0xFFFFFFFF</resetMask>
4850            <fields>
4851              <field>
4852                <name>VALUE</name>
4853                <description>Index value for accessing block-based lookup table using BLK_LUT. Programming out of LUT range is an user error and it loops back to '0' once overflow occurs.</description>
4854                <bitRange>[31:0]</bitRange>
4855                <access>read-write</access>
4856              </field>
4857            </fields>
4858          </register>
4859          <register>
4860            <name>BLK_LUT</name>
4861            <description>NS status for 32 blocks at BLK_IDX with PC=&lt;access_pc&gt;</description>
4862            <addressOffset>0x110</addressOffset>
4863            <size>32</size>
4864            <access>read-write</access>
4865            <resetValue>0x0</resetValue>
4866            <resetMask>0xFFFFFFFF</resetMask>
4867            <fields>
4868              <field>
4869                <name>ATTR_NS0</name>
4870                <description>NS bit for block 0 based on BLK_IDX</description>
4871                <bitRange>[0:0]</bitRange>
4872                <access>read-write</access>
4873              </field>
4874              <field>
4875                <name>ATTR_NS1</name>
4876                <description>NS bit for block 1 based on BLK_IDX</description>
4877                <bitRange>[1:1]</bitRange>
4878                <access>read-write</access>
4879              </field>
4880              <field>
4881                <name>ATTR_NS2</name>
4882                <description>NS bit for block 2 based on BLK_IDX</description>
4883                <bitRange>[2:2]</bitRange>
4884                <access>read-write</access>
4885              </field>
4886              <field>
4887                <name>ATTR_NS3</name>
4888                <description>NS bit for block 3 based on BLK_IDX</description>
4889                <bitRange>[3:3]</bitRange>
4890                <access>read-write</access>
4891              </field>
4892              <field>
4893                <name>ATTR_NS4</name>
4894                <description>NS bit for block 4 based on BLK_IDX</description>
4895                <bitRange>[4:4]</bitRange>
4896                <access>read-write</access>
4897              </field>
4898              <field>
4899                <name>ATTR_NS5</name>
4900                <description>NS bit for block 5 based on BLK_IDX</description>
4901                <bitRange>[5:5]</bitRange>
4902                <access>read-write</access>
4903              </field>
4904              <field>
4905                <name>ATTR_NS6</name>
4906                <description>NS bit for block 6 based on BLK_IDX</description>
4907                <bitRange>[6:6]</bitRange>
4908                <access>read-write</access>
4909              </field>
4910              <field>
4911                <name>ATTR_NS7</name>
4912                <description>NS bit for block 7 based on BLK_IDX</description>
4913                <bitRange>[7:7]</bitRange>
4914                <access>read-write</access>
4915              </field>
4916              <field>
4917                <name>ATTR_NS8</name>
4918                <description>NS bit for block 8 based on BLK_IDX</description>
4919                <bitRange>[8:8]</bitRange>
4920                <access>read-write</access>
4921              </field>
4922              <field>
4923                <name>ATTR_NS9</name>
4924                <description>NS bit for block 9 based on BLK_IDX</description>
4925                <bitRange>[9:9]</bitRange>
4926                <access>read-write</access>
4927              </field>
4928              <field>
4929                <name>ATTR_NS10</name>
4930                <description>NS bit for block 10 based on BLK_IDX</description>
4931                <bitRange>[10:10]</bitRange>
4932                <access>read-write</access>
4933              </field>
4934              <field>
4935                <name>ATTR_NS11</name>
4936                <description>NS bit for block 11 based on BLK_IDX</description>
4937                <bitRange>[11:11]</bitRange>
4938                <access>read-write</access>
4939              </field>
4940              <field>
4941                <name>ATTR_NS12</name>
4942                <description>NS bit for block 12 based on BLK_IDX</description>
4943                <bitRange>[12:12]</bitRange>
4944                <access>read-write</access>
4945              </field>
4946              <field>
4947                <name>ATTR_NS13</name>
4948                <description>NS bit for block 13 based on BLK_IDX</description>
4949                <bitRange>[13:13]</bitRange>
4950                <access>read-write</access>
4951              </field>
4952              <field>
4953                <name>ATTR_NS14</name>
4954                <description>NS bit for block 14 based on BLK_IDX</description>
4955                <bitRange>[14:14]</bitRange>
4956                <access>read-write</access>
4957              </field>
4958              <field>
4959                <name>ATTR_NS15</name>
4960                <description>NS bit for block 15 based on BLK_IDX</description>
4961                <bitRange>[15:15]</bitRange>
4962                <access>read-write</access>
4963              </field>
4964              <field>
4965                <name>ATTR_NS16</name>
4966                <description>NS bit for block 16 based on BLK_IDX</description>
4967                <bitRange>[16:16]</bitRange>
4968                <access>read-write</access>
4969              </field>
4970              <field>
4971                <name>ATTR_NS17</name>
4972                <description>NS bit for block 17 based on BLK_IDX</description>
4973                <bitRange>[17:17]</bitRange>
4974                <access>read-write</access>
4975              </field>
4976              <field>
4977                <name>ATTR_NS18</name>
4978                <description>NS bit for block 18 based on BLK_IDX</description>
4979                <bitRange>[18:18]</bitRange>
4980                <access>read-write</access>
4981              </field>
4982              <field>
4983                <name>ATTR_NS19</name>
4984                <description>NS bit for block 19 based on BLK_IDX</description>
4985                <bitRange>[19:19]</bitRange>
4986                <access>read-write</access>
4987              </field>
4988              <field>
4989                <name>ATTR_NS20</name>
4990                <description>NS bit for block 20 based on BLK_IDX</description>
4991                <bitRange>[20:20]</bitRange>
4992                <access>read-write</access>
4993              </field>
4994              <field>
4995                <name>ATTR_NS21</name>
4996                <description>NS bit for block 21 based on BLK_IDX</description>
4997                <bitRange>[21:21]</bitRange>
4998                <access>read-write</access>
4999              </field>
5000              <field>
5001                <name>ATTR_NS22</name>
5002                <description>NS bit for block 22 based on BLK_IDX</description>
5003                <bitRange>[22:22]</bitRange>
5004                <access>read-write</access>
5005              </field>
5006              <field>
5007                <name>ATTR_NS23</name>
5008                <description>NS bit for block 23 based on BLK_IDX</description>
5009                <bitRange>[23:23]</bitRange>
5010                <access>read-write</access>
5011              </field>
5012              <field>
5013                <name>ATTR_NS24</name>
5014                <description>NS bit for block 24 based on BLK_IDX</description>
5015                <bitRange>[24:24]</bitRange>
5016                <access>read-write</access>
5017              </field>
5018              <field>
5019                <name>ATTR_NS25</name>
5020                <description>NS bit for block 25 based on BLK_IDX</description>
5021                <bitRange>[25:25]</bitRange>
5022                <access>read-write</access>
5023              </field>
5024              <field>
5025                <name>ATTR_NS26</name>
5026                <description>NS bit for block 26 based on BLK_IDX</description>
5027                <bitRange>[26:26]</bitRange>
5028                <access>read-write</access>
5029              </field>
5030              <field>
5031                <name>ATTR_NS27</name>
5032                <description>NS bit for block 27 based on BLK_IDX</description>
5033                <bitRange>[27:27]</bitRange>
5034                <access>read-write</access>
5035              </field>
5036              <field>
5037                <name>ATTR_NS28</name>
5038                <description>NS bit for block 28 based on BLK_IDX</description>
5039                <bitRange>[28:28]</bitRange>
5040                <access>read-write</access>
5041              </field>
5042              <field>
5043                <name>ATTR_NS29</name>
5044                <description>NS bit for block 29 based on BLK_IDX</description>
5045                <bitRange>[29:29]</bitRange>
5046                <access>read-write</access>
5047              </field>
5048              <field>
5049                <name>ATTR_NS30</name>
5050                <description>NS bit for block 30 based on BLK_IDX</description>
5051                <bitRange>[30:30]</bitRange>
5052                <access>read-write</access>
5053              </field>
5054              <field>
5055                <name>ATTR_NS31</name>
5056                <description>NS bit for block 31 based on BLK_IDX</description>
5057                <bitRange>[31:31]</bitRange>
5058                <access>read-write</access>
5059              </field>
5060            </fields>
5061          </register>
5062          <register>
5063            <name>ROT_CTRL</name>
5064            <description>Control register with lock bit and auto-increment only</description>
5065            <addressOffset>0x200</addressOffset>
5066            <size>32</size>
5067            <access>read-write</access>
5068            <resetValue>0x100</resetValue>
5069            <resetMask>0x80000100</resetMask>
5070            <fields>
5071              <field>
5072                <name>AUTO_INC</name>
5073                <description>Auto-increment BLK_IDX by 1 for each read/write of ROT_BLK_LUT</description>
5074                <bitRange>[8:8]</bitRange>
5075                <access>read-write</access>
5076              </field>
5077              <field>
5078                <name>LOCK</name>
5079                <description>Security lockdown for the root-of-trust configuration registers. Software can set this bit but not clear it once set.  When set, write operations to ROT_BLK_LUT are not possible. Write is ignored.</description>
5080                <bitRange>[31:31]</bitRange>
5081                <access>read-write</access>
5082              </field>
5083            </fields>
5084          </register>
5085          <register>
5086            <name>ROT_CFG</name>
5087            <description>Sets block-size to match memory size (external memory only)</description>
5088            <addressOffset>0x204</addressOffset>
5089            <size>32</size>
5090            <access>read-write</access>
5091            <resetValue>0x0</resetValue>
5092            <resetMask>0xF</resetMask>
5093            <fields>
5094              <field>
5095                <name>BLOCK_SIZE</name>
5096                <description>Block size of individually protected blocks (0: 32B, 1: 64B, ...up to 15:1 MB)
5097Block size= (1&lt;&lt;(BLOCK_SIZE+5))
5098The number and size blocks in an MPC is design time configurable and for external memories defaults to covering the entire memory using 4kB blocks; see product datasheet for details on protection of external memories.</description>
5099                <bitRange>[3:0]</bitRange>
5100                <access>read-write</access>
5101              </field>
5102            </fields>
5103          </register>
5104          <register>
5105            <name>ROT_BLK_MAX</name>
5106            <description>Max value of block-based index register for ROT</description>
5107            <addressOffset>0x208</addressOffset>
5108            <size>32</size>
5109            <access>read-only</access>
5110            <resetValue>0x0</resetValue>
5111            <resetMask>0xFFFFFFFF</resetMask>
5112            <fields>
5113              <field>
5114                <name>VALUE</name>
5115                <description>Maximum value of block-based index register.  The number and size blocks in an MPC is design time configurable and for embedded memories defaults to covering the entire memory using 4kB blocks; see product datasheet for details on protection of external memories.</description>
5116                <bitRange>[31:0]</bitRange>
5117                <access>read-only</access>
5118              </field>
5119            </fields>
5120          </register>
5121          <register>
5122            <name>ROT_BLK_CFG</name>
5123            <description>Same as BLK_CFG</description>
5124            <addressOffset>0x20C</addressOffset>
5125            <size>32</size>
5126            <access>read-only</access>
5127            <resetValue>0x80000000</resetValue>
5128            <resetMask>0x8000000F</resetMask>
5129            <fields>
5130              <field>
5131                <name>BLOCK_SIZE</name>
5132                <description>Block size of individually protected blocks (0: 32B, 1: 64B, ...up to 15:1MB)
5133Block size= (1&lt;&lt;(BLOCK_SIZE+5))
5134The number and size blocks in an MPC is design time configurable and for embedded memories defaults to covering the entire memory using 4kB blocks; see product datasheet for details on protection of external memories.</description>
5135                <bitRange>[3:0]</bitRange>
5136                <access>read-only</access>
5137              </field>
5138              <field>
5139                <name>INIT_IN_PROGRESS</name>
5140                <description>During initialization INIT_IN_PROGRESS is '1' and MMIO register accesses to ROT_BLK_LUT is RAZWI. The block attributes are retained in DeepSleep (and obviously Active) power mode. Initialization is only required from a power mode in which the block attributes are not retained. E.g., initialization is required for a cold boot (after a Power-on-Reset).
5141HW initializes the block attributes: the NS attributes are set to '0' (secure), the R attributes are set to '1' (read access allowed) and the W attributes are set to '1' (write access allowed). During initialization, the MPC supports memory accesses (memory accesses are NOT blocked) with the initialization block attribute values as mentioned above. This e.g. allows MPC initialization to proceed in parallel with boot program memory accesses (as opposed to serializing the two), improving device boot time.
5142HW initializes the block attributes NS to 1 in case SECEXT = 0.</description>
5143                <bitRange>[31:31]</bitRange>
5144                <access>read-only</access>
5145              </field>
5146            </fields>
5147          </register>
5148          <register>
5149            <name>ROT_BLK_IDX</name>
5150            <description>Index of 8-block group accessed through ROT_BLK_LUT_*</description>
5151            <addressOffset>0x210</addressOffset>
5152            <size>32</size>
5153            <access>read-write</access>
5154            <resetValue>0x0</resetValue>
5155            <resetMask>0xFFFFFFFF</resetMask>
5156            <fields>
5157              <field>
5158                <name>VALUE</name>
5159                <description>Index value for accessing block-based lookup table using ROT_BLK_LUT. Programming out of LUT range is an user error and it loops back to '0' once overflow occurs.</description>
5160                <bitRange>[31:0]</bitRange>
5161                <access>read-write</access>
5162              </field>
5163            </fields>
5164          </register>
5165          <register>
5166            <name>ROT_BLK_PC</name>
5167            <description>Protection context of 8-block group accesses through ROT_BLK_LUT</description>
5168            <addressOffset>0x214</addressOffset>
5169            <size>32</size>
5170            <access>read-write</access>
5171            <resetValue>0x0</resetValue>
5172            <resetMask>0xF</resetMask>
5173            <fields>
5174              <field>
5175                <name>PC</name>
5176                <description>Specify PC values for ROT_BLK_IDX and ROT_BLK_LUT</description>
5177                <bitRange>[3:0]</bitRange>
5178                <access>read-write</access>
5179              </field>
5180            </fields>
5181          </register>
5182          <register>
5183            <name>ROT_BLK_LUT</name>
5184            <description>(R,W,NS) bits for 8 blocks at ROT_BLK_IDX for PC=ROT_BKL_PC</description>
5185            <addressOffset>0x218</addressOffset>
5186            <size>32</size>
5187            <access>read-write</access>
5188            <resetValue>0x0</resetValue>
5189            <resetMask>0x77777777</resetMask>
5190            <fields>
5191              <field>
5192                <name>ATTR0</name>
5193                <description>W/R/NS bits for block 0 indicated by ROT_BLK_IDX for ROT_BLK_PC PC</description>
5194                <bitRange>[2:0]</bitRange>
5195                <access>read-write</access>
5196              </field>
5197              <field>
5198                <name>ATTR1</name>
5199                <description>W/R/NS bits for block 1 indicated by ROT_BLK_IDX for ROT_BLK_PC PC</description>
5200                <bitRange>[6:4]</bitRange>
5201                <access>read-write</access>
5202              </field>
5203              <field>
5204                <name>ATTR2</name>
5205                <description>W/R/NS bits for block 2 indicated by ROT_BLK_IDX for ROT_BLK_PC PC</description>
5206                <bitRange>[10:8]</bitRange>
5207                <access>read-write</access>
5208              </field>
5209              <field>
5210                <name>ATTR3</name>
5211                <description>W/R/NS bits for block 3 indicated by ROT_BLK_IDX for ROT_BLK_PC PC</description>
5212                <bitRange>[14:12]</bitRange>
5213                <access>read-write</access>
5214              </field>
5215              <field>
5216                <name>ATTR4</name>
5217                <description>W/R/NS bits for block 4 indicated by ROT_BLK_IDX for ROT_BLK_PC PC</description>
5218                <bitRange>[18:16]</bitRange>
5219                <access>read-write</access>
5220              </field>
5221              <field>
5222                <name>ATTR5</name>
5223                <description>W/R/NS bits for block 5 indicated by ROT_BLK_IDX for ROT_BLK_PC PC</description>
5224                <bitRange>[22:20]</bitRange>
5225                <access>read-write</access>
5226              </field>
5227              <field>
5228                <name>ATTR6</name>
5229                <description>W/R/NS bits for block 6 indicated by ROT_BLK_IDX for ROT_BLK_PC PC</description>
5230                <bitRange>[26:24]</bitRange>
5231                <access>read-write</access>
5232              </field>
5233              <field>
5234                <name>ATTR7</name>
5235                <description>W/R/NS bits for block 7 indicated by ROT_BLK_IDX for ROT_BLK_PC PC</description>
5236                <bitRange>[30:28]</bitRange>
5237                <access>read-write</access>
5238              </field>
5239            </fields>
5240          </register>
5241        </cluster>
5242      </registers>
5243    </peripheral>
5244    <peripheral>
5245      <name>MXCM33</name>
5246      <description>MXCM33-0/1</description>
5247      <baseAddress>0x40160000</baseAddress>
5248      <addressBlock>
5249        <offset>0</offset>
5250        <size>65536</size>
5251        <usage>registers</usage>
5252      </addressBlock>
5253      <registers>
5254        <register>
5255          <name>CM33_CTL</name>
5256          <description>Control</description>
5257          <addressOffset>0x0</addressOffset>
5258          <size>32</size>
5259          <access>read-write</access>
5260          <resetValue>0x0</resetValue>
5261          <resetMask>0x9F001F10</resetMask>
5262          <fields>
5263            <field>
5264              <name>CPU_WAIT</name>
5265              <description>When this signal is '1' out of reset, it forces the CPU into a quiescent state that delays its boot-up sequence and instruction execution until this signal is driven '0'.</description>
5266              <bitRange>[4:4]</bitRange>
5267              <access>read-write</access>
5268            </field>
5269            <field>
5270              <name>LOCKNSVTOR</name>
5271              <description>Asserting this bit prevents changes to the Non-secure vector table base address.
5272'1': Disables writes to the VTOR_NS register.
5273'0': Unlocks this register.</description>
5274              <bitRange>[8:8]</bitRange>
5275              <access>read-write</access>
5276            </field>
5277            <field>
5278              <name>LOCKSVTAIRCR</name>
5279              <description>Asserting this bit prevents changes to:
5280- The Secure vector table base address.
5281- Handling of Secure interrupt priority.
5282- BusFault, HardFault, and NMI security target settings in the processor.
5283'1': Disables writes to the VTOR_S,AIRCR.PRIS, and AIRCR.BFHFNMINS registers.
5284'0': Unlocks these registers.</description>
5285              <bitRange>[9:9]</bitRange>
5286              <access>read-write</access>
5287            </field>
5288            <field>
5289              <name>LOCKSMPU</name>
5290              <description>Asserting this bit prevents changes to programmed Secure MPU memory regions and all writes to the registers are ignored.
5291'1': Disables writes to the MPU_CTRL, MPU_RNR, MPU_RBAR,
5292MPU_RLAR, MPU_RBAR_An and MPU_RLAR_An from software or
5293from a debug agent connected to the processor in Secure state.
5294'0': Unlocks these registers.
5295This bit has no affect if the Cortex-M33 processor has not been configured with support for the Armv8-M Security Extension, or if no Secure MPU regions have been configured.</description>
5296              <bitRange>[10:10]</bitRange>
5297              <access>read-write</access>
5298            </field>
5299            <field>
5300              <name>LOCKNSMPU</name>
5301              <description>Asserting this bit prevents changes to Nonsecure MPU memory regions already programmed. All writes to the registers are
5302ignored.
5303'1': Disables writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and
5304MPU_RLAR_A_NSn from software or from a debug agent connected to the processor.
5305'0': Unlocks these registers.
5306This signal has no affect if the Cortex-M33 processor has been configured without any Nonsecure MPU regions.</description>
5307              <bitRange>[11:11]</bitRange>
5308              <access>read-write</access>
5309            </field>
5310            <field>
5311              <name>LOCKSAU</name>
5312              <description>Asserting this bit prevents changes to Secure SAU memory regions already programmed. All writes to the registers are ignored.
5313'1': Disables writes to the SAU_CTRL, SAU_RNR, SAU_RBAR and
5314SAU_RLAR registers from software or from a debug agent connected to the processor.
5315'0': Unlocks these registers.
5316This signal has no affect if the Cortex-M33 processor has not been configured with support for the Armv8-M Security Extension, or if no SAU regions have been configured.</description>
5317              <bitRange>[12:12]</bitRange>
5318              <access>read-write</access>
5319            </field>
5320            <field>
5321              <name>IOC_MASK</name>
5322              <description>CPU floating point unit (FPU) exception mask for the CPU's FPCSR.IOC 'invalid operation' exception condition:
5323'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt.
5324'1': the CPU's exception condition activates the CPU's floating point interrupt.
5325
5326Note: the ARM architecture does NOT support FPU exceptions; i.e. there is no precise FPU exception handler. Instead, FPU conditions are captured in the CPU's FPCSR register and the conditions are provided as CPU interface signals. The interface signals are 'masked' with the fields a provide by this register (CM7_0_CTL). The 'masked' signals are reduced/OR-ed into a single CPU floating point interrupt signal. The associated CPU interrupt handler allows for imprecise handling of FPU exception conditions.
5327
5328Note: the CPU's FPCSR exception conditions are 'sticky'. Typically, the CPU FPU interrupt handler will clear the exception condition(s) to '0'.
5329
5330Note: by default, the FPU exception masks are '0'. Therefore, FPU exception conditions will NOT activate the CPU's floating point interrupt.</description>
5331              <bitRange>[24:24]</bitRange>
5332              <access>read-write</access>
5333            </field>
5334            <field>
5335              <name>DZC_MASK</name>
5336              <description>CPU FPU exception mask for the CPU's FPCSR.DZC 'divide by zero' exception condition:
5337'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt.
5338'1': the CPU's exception condition activates the CPU's floating point interrupt.</description>
5339              <bitRange>[25:25]</bitRange>
5340              <access>read-write</access>
5341            </field>
5342            <field>
5343              <name>OFC_MASK</name>
5344              <description>CPU FPU exception mask for the CPU's FPCSR.OFC 'overflow' exception condition:
5345'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt.
5346'1': the CPU's exception condition activates the CPU's floating point interrupt.</description>
5347              <bitRange>[26:26]</bitRange>
5348              <access>read-write</access>
5349            </field>
5350            <field>
5351              <name>UFC_MASK</name>
5352              <description>CPU FPU exception mask for the CPU's FPCSR.UFC 'underflow' exception condition:
5353'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt.
5354'1': the CPU's exception condition activates the CPU's floating point interrupt.</description>
5355              <bitRange>[27:27]</bitRange>
5356              <access>read-write</access>
5357            </field>
5358            <field>
5359              <name>IXC_MASK</name>
5360              <description>CPU FPU exception mask for the CPU's FPCSR.IXC 'inexact' exception condition:
5361'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt.
5362'1': the CPU's exception condition activates the CPU's floating point interrupt.
5363
5364Note: the 'inexact' condition is set as a result of rounding. Rounding may occur frequently and is typically not an error condition. To prevent frequent CPU FPU interrupts as a result of rounding, this field is typically set to '0'.</description>
5365              <bitRange>[28:28]</bitRange>
5366              <access>read-write</access>
5367            </field>
5368            <field>
5369              <name>IDC_MASK</name>
5370              <description>CPU FPU exception mask for the CPU's FPCSR.IDC 'input denormalized' exception condition:
5371'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt.
5372'1': the CPU's exception condition activates the CPU's floating point interrupt.
5373
5374Note: if the CPU FPCSR.FZ field is set to '1', denormalized inputs are 'flushed to zero'. Dependent on the FPU algorithm, this may or may not occur frequently. To prevent frequent CPU FPU interrupts as a result of denormalized inputs, this field may be set to '0'.</description>
5375              <bitRange>[31:31]</bitRange>
5376              <access>read-write</access>
5377            </field>
5378          </fields>
5379        </register>
5380        <register>
5381          <name>CM33_CMD</name>
5382          <description>Command</description>
5383          <addressOffset>0x4</addressOffset>
5384          <size>32</size>
5385          <access>read-write</access>
5386          <resetValue>0xFA050002</resetValue>
5387          <resetMask>0xFFFF0002</resetMask>
5388          <fields>
5389            <field>
5390              <name>ENABLED</name>
5391              <description>Processor enable:
5392'0': Disabled. Processor clock is turned off and reset is activated. After SW clears this field to '0', HW automatically sets this field to '1'. This effectively results in a CM33 reset, followed by a CM33 warm boot.
5393'1': Enabled.
5394Note: The intent is that this bit is modified only through an external probe or by the other CM33 while this CM33 is in Sleep or DeepSleep power mode. If this field is cleared to '0' by this CM33 itself, it should be done under controlled conditions (such that undesirable side effects can be prevented).
5395
5396Note: The CM33 CPU has a AIRCR.SYSRESETREQ register field that allows the CM33 to reset the complete device (ENABLED only disables/enables the CM33), resulting in a warm boot. This CPU register field has similar 'built-in protection' as this register to prevent accidental system writes (the upper 16-bits of the register need to be written with a 0x05fa key value; see CPU user manual for more details).</description>
5397              <bitRange>[1:1]</bitRange>
5398              <access>read-write</access>
5399            </field>
5400            <field>
5401              <name>VECTKEYSTAT</name>
5402              <description>Register key (to prevent accidental writes).
5403- Should be written with a 0x05fa key value for the write to take effect.
5404- Always reads as 0xfa05.</description>
5405              <bitRange>[31:16]</bitRange>
5406              <access>read-only</access>
5407            </field>
5408          </fields>
5409        </register>
5410        <register>
5411          <name>CM33_STATUS</name>
5412          <description>Status</description>
5413          <addressOffset>0x8</addressOffset>
5414          <size>32</size>
5415          <access>read-only</access>
5416          <resetValue>0x0</resetValue>
5417          <resetMask>0x3</resetMask>
5418          <fields>
5419            <field>
5420              <name>SLEEPING</name>
5421              <description>Specifies if the CPU is in Active, Sleep or DeepSleep power mode:
5422- Active power mode: SLEEPING is '0'.
5423- Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'.
5424- DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'.</description>
5425              <bitRange>[0:0]</bitRange>
5426              <access>read-only</access>
5427            </field>
5428            <field>
5429              <name>SLEEPDEEP</name>
5430              <description>Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field.</description>
5431              <bitRange>[1:1]</bitRange>
5432              <access>read-only</access>
5433            </field>
5434          </fields>
5435        </register>
5436        <register>
5437          <dim>16</dim>
5438          <dimIncrement>4</dimIncrement>
5439          <name>CM33_INT_STATUS[%s]</name>
5440          <description>CM33 interrupt status</description>
5441          <addressOffset>0x40</addressOffset>
5442          <size>32</size>
5443          <access>read-only</access>
5444          <resetValue>0x0</resetValue>
5445          <resetMask>0x80000000</resetMask>
5446          <fields>
5447            <field>
5448              <name>SYSTEM_INT_IDX</name>
5449              <description>Lowest CM33 activated system interrupt index for given CPU interrupt.
5450
5451Multiple system interrupts can be mapped on the same CPU interrupt. The selected system interrupt is the system interrupt with the lowest system interrupt index that has an activated interrupt request at the time of the fetch (system_interrupts[SYSTEM_INT_IDX] is '1').
5452
5453The CPU interrupt handler SW can read SYSTEM_INT_IDX to determine the system interrupt that activated the handler.</description>
5454              <bitRange>[9:0]</bitRange>
5455              <access>read-only</access>
5456            </field>
5457            <field>
5458              <name>SYSTEM_INT_VALID</name>
5459              <description>Valid indication for SYSTEM_INT_IDX. When '0', no system interrupt for CPU interrupt 0 is valid/activated.</description>
5460              <bitRange>[31:31]</bitRange>
5461              <access>read-only</access>
5462            </field>
5463          </fields>
5464        </register>
5465        <register>
5466          <dim>4</dim>
5467          <dimIncrement>4</dimIncrement>
5468          <name>CM33_NMI_CTL[%s]</name>
5469          <description>CM33 NMI control</description>
5470          <addressOffset>0x80</addressOffset>
5471          <size>32</size>
5472          <access>read-write</access>
5473          <resetValue>0x3FF</resetValue>
5474          <resetMask>0x3FF</resetMask>
5475          <fields>
5476            <field>
5477              <name>SYSTEM_INT_IDX</name>
5478              <description>System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset.</description>
5479              <bitRange>[9:0]</bitRange>
5480              <access>read-write</access>
5481            </field>
5482          </fields>
5483        </register>
5484        <register>
5485          <name>CM33_NS_VECTOR_TABLE_BASE</name>
5486          <description>CM33 non-secure vector table base</description>
5487          <addressOffset>0x1004</addressOffset>
5488          <size>32</size>
5489          <access>read-write</access>
5490          <resetValue>0x0</resetValue>
5491          <resetMask>0xFFFFFF80</resetMask>
5492          <fields>
5493            <field>
5494              <name>ADDR25</name>
5495              <description>Address of CM33 non-secure vector table to be used at reset.  The default value points to Non-secure ROM start address i.e. 0x0000_0000.</description>
5496              <bitRange>[31:7]</bitRange>
5497              <access>read-write</access>
5498            </field>
5499          </fields>
5500        </register>
5501        <register>
5502          <name>CM33_PC_CTL</name>
5503          <description>CM33 protection context control</description>
5504          <addressOffset>0x2000</addressOffset>
5505          <size>32</size>
5506          <access>read-write</access>
5507          <resetValue>0x0</resetValue>
5508          <resetMask>0xF</resetMask>
5509          <fields>
5510            <field>
5511              <name>VALID</name>
5512              <description>Valid fields for the protection context handler CM33_PCi_HANDLER registers:
5513Bit 0: Valid field for CM33_PC0_HANDLER.
5514Bit 1: Valid field for CM33_PC1_HANDLER.
5515Bit 2: Valid field for CM33_PC2_HANDLER.
5516Bit 3: Valid field for CM33_PC3_HANDLER.</description>
5517              <bitRange>[3:0]</bitRange>
5518              <access>read-write</access>
5519            </field>
5520          </fields>
5521        </register>
5522        <register>
5523          <name>CM33_PC0_HANDLER</name>
5524          <description>CM33 protection context 0 handler</description>
5525          <addressOffset>0x2040</addressOffset>
5526          <size>32</size>
5527          <access>read-write</access>
5528          <resetValue>0x0</resetValue>
5529          <resetMask>0xFFFFFFFF</resetMask>
5530          <fields>
5531            <field>
5532              <name>ADDR</name>
5533              <description>Address of the protection context 0 handler. This field is used to detect entry to Cypress 'trusted' code through an exception/interrupt.</description>
5534              <bitRange>[31:0]</bitRange>
5535              <access>read-write</access>
5536            </field>
5537          </fields>
5538        </register>
5539        <register>
5540          <name>CM33_PC1_HANDLER</name>
5541          <description>CM33 protection context 1 handler</description>
5542          <addressOffset>0x2044</addressOffset>
5543          <size>32</size>
5544          <access>read-write</access>
5545          <resetValue>0x0</resetValue>
5546          <resetMask>0xFFFFFFFF</resetMask>
5547          <fields>
5548            <field>
5549              <name>ADDR</name>
5550              <description>Address of the protection context 1 handler.</description>
5551              <bitRange>[31:0]</bitRange>
5552              <access>read-write</access>
5553            </field>
5554          </fields>
5555        </register>
5556        <register>
5557          <name>CM33_PC2_HANDLER</name>
5558          <description>CM33 protection context 2 handler</description>
5559          <addressOffset>0x2048</addressOffset>
5560          <size>32</size>
5561          <access>read-write</access>
5562          <resetValue>0x0</resetValue>
5563          <resetMask>0xFFFFFFFF</resetMask>
5564          <fields>
5565            <field>
5566              <name>ADDR</name>
5567              <description>Address of the protection context 2 handler.</description>
5568              <bitRange>[31:0]</bitRange>
5569              <access>read-write</access>
5570            </field>
5571          </fields>
5572        </register>
5573        <register>
5574          <name>CM33_PC3_HANDLER</name>
5575          <description>CM33 protection context 3 handler</description>
5576          <addressOffset>0x204C</addressOffset>
5577          <size>32</size>
5578          <access>read-write</access>
5579          <resetValue>0x0</resetValue>
5580          <resetMask>0xFFFFFFFF</resetMask>
5581          <fields>
5582            <field>
5583              <name>ADDR</name>
5584              <description>Address of the protection context 3 handler.</description>
5585              <bitRange>[31:0]</bitRange>
5586              <access>read-write</access>
5587            </field>
5588          </fields>
5589        </register>
5590        <register>
5591          <dim>1023</dim>
5592          <dimIncrement>4</dimIncrement>
5593          <name>CM33_SYSTEM_INT_CTL[%s]</name>
5594          <description>CM33 system interrupt control</description>
5595          <addressOffset>0x8000</addressOffset>
5596          <size>32</size>
5597          <access>read-write</access>
5598          <resetValue>0x0</resetValue>
5599          <resetMask>0x80000000</resetMask>
5600          <fields>
5601            <field>
5602              <name>CPU_INT_IDX</name>
5603              <description>CPU interrupt index (legal range [0, 15]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'.
5604
5605Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
5606
5607Note: CPU_INT_IDX register width is derived from mxcm33 parameter IRQ_IDX_WIDTH.
5608IRQ_IDX_WIDTH  = (CM33_INT_NR == 16) ? 4 : 3</description>
5609              <bitRange>[3:0]</bitRange>
5610              <access>read-write</access>
5611            </field>
5612            <field>
5613              <name>CPU_INT_VALID</name>
5614              <description>Interrupt enable:
5615'0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt.
5616'1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX.
5617
5618Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.</description>
5619              <bitRange>[31:31]</bitRange>
5620              <access>read-write</access>
5621            </field>
5622          </fields>
5623        </register>
5624      </registers>
5625    </peripheral>
5626    <peripheral>
5627      <name>DW0</name>
5628      <description>DW-0/1</description>
5629      <headerStructName>DW</headerStructName>
5630      <baseAddress>0x40180000</baseAddress>
5631      <addressBlock>
5632        <offset>0</offset>
5633        <size>65536</size>
5634        <usage>registers</usage>
5635      </addressBlock>
5636      <registers>
5637        <register>
5638          <name>CTL</name>
5639          <description>Control</description>
5640          <addressOffset>0x0</addressOffset>
5641          <size>32</size>
5642          <access>read-write</access>
5643          <resetValue>0x1</resetValue>
5644          <resetMask>0x80000003</resetMask>
5645          <fields>
5646            <field>
5647              <name>ECC_EN</name>
5648              <description>Enable ECC checking:
5649'0': Disabled.
5650'1': Enabled.</description>
5651              <bitRange>[0:0]</bitRange>
5652              <access>read-write</access>
5653            </field>
5654            <field>
5655              <name>ECC_INJ_EN</name>
5656              <description>Enable parity injection for SRAM.
5657When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of the SRAM.</description>
5658              <bitRange>[1:1]</bitRange>
5659              <access>read-write</access>
5660            </field>
5661            <field>
5662              <name>ENABLED</name>
5663              <description>IP enable:
5664'0': Disabled. Disabling the IP activates the IP's Active logic reset: Active logic and non-retention MMIO registers are reset (retention MMIO registers are not affected).
5665Note that DW SRAM writes/reads are possible when ENABLED=0 also.
5666'1': Enabled.</description>
5667              <bitRange>[31:31]</bitRange>
5668              <access>read-write</access>
5669            </field>
5670          </fields>
5671        </register>
5672        <register>
5673          <name>STATUS</name>
5674          <description>Status</description>
5675          <addressOffset>0x4</addressOffset>
5676          <size>32</size>
5677          <access>read-only</access>
5678          <resetValue>0x0</resetValue>
5679          <resetMask>0xF0000000</resetMask>
5680          <fields>
5681            <field>
5682              <name>P</name>
5683              <description>Active channel, user/privileged access control:
5684'0': user mode.
5685'1': privileged mode.</description>
5686              <bitRange>[0:0]</bitRange>
5687              <access>read-only</access>
5688            </field>
5689            <field>
5690              <name>NS</name>
5691              <description>Active channel, secure/non-secure access control:
5692'0': secure.
5693'1': non-secure.</description>
5694              <bitRange>[1:1]</bitRange>
5695              <access>read-only</access>
5696            </field>
5697            <field>
5698              <name>B</name>
5699              <description>Active channel, non-bufferable/bufferable access control:
5700'0': non-bufferable
5701'1': bufferable.</description>
5702              <bitRange>[2:2]</bitRange>
5703              <access>read-only</access>
5704            </field>
5705            <field>
5706              <name>PC</name>
5707              <description>Active channel protection context.</description>
5708              <bitRange>[7:4]</bitRange>
5709              <access>read-only</access>
5710            </field>
5711            <field>
5712              <name>PRIO</name>
5713              <description>Active channel priority.</description>
5714              <bitRange>[9:8]</bitRange>
5715              <access>read-only</access>
5716            </field>
5717            <field>
5718              <name>PREEMPTABLE</name>
5719              <description>Active channel preemptable.</description>
5720              <bitRange>[11:11]</bitRange>
5721              <access>read-only</access>
5722            </field>
5723            <field>
5724              <name>CH_IDX</name>
5725              <description>Active channel index.</description>
5726              <bitRange>[24:16]</bitRange>
5727              <access>read-only</access>
5728            </field>
5729            <field>
5730              <name>STATE</name>
5731              <description>State of the DW controller.
5732'0': Default/inactive state.
5733'1': Loading descriptor.
5734'2': Loading data element from source location.
5735'3': Storing data element to destination location.
5736'4': CRC functionality (only used for CRC transfer descriptor type).
5737'5': Update of active control information (e.g. source and destination addresses) and wait for trigger de-activation.
5738'6': Error.</description>
5739              <bitRange>[30:28]</bitRange>
5740              <access>read-only</access>
5741            </field>
5742            <field>
5743              <name>ACTIVE</name>
5744              <description>Active channel present:
5745'0': No.
5746'1': Yes.</description>
5747              <bitRange>[31:31]</bitRange>
5748              <access>read-only</access>
5749            </field>
5750          </fields>
5751        </register>
5752        <register>
5753          <name>ACT_DESCR_CTL</name>
5754          <description>Active descriptor control</description>
5755          <addressOffset>0x20</addressOffset>
5756          <size>32</size>
5757          <access>read-only</access>
5758          <resetValue>0x0</resetValue>
5759          <resetMask>0x0</resetMask>
5760          <fields>
5761            <field>
5762              <name>DATA</name>
5763              <description>N/A</description>
5764              <bitRange>[31:0]</bitRange>
5765              <access>read-only</access>
5766            </field>
5767          </fields>
5768        </register>
5769        <register>
5770          <name>ACT_DESCR_SRC</name>
5771          <description>Active descriptor source</description>
5772          <addressOffset>0x24</addressOffset>
5773          <size>32</size>
5774          <access>read-only</access>
5775          <resetValue>0x0</resetValue>
5776          <resetMask>0x0</resetMask>
5777          <fields>
5778            <field>
5779              <name>DATA</name>
5780              <description>Copy of DESCR_SRC of the currently active descriptor.
5781
5782Base address of source location.</description>
5783              <bitRange>[31:0]</bitRange>
5784              <access>read-only</access>
5785            </field>
5786          </fields>
5787        </register>
5788        <register>
5789          <name>ACT_DESCR_DST</name>
5790          <description>Active descriptor destination</description>
5791          <addressOffset>0x28</addressOffset>
5792          <size>32</size>
5793          <access>read-only</access>
5794          <resetValue>0x0</resetValue>
5795          <resetMask>0x0</resetMask>
5796          <fields>
5797            <field>
5798              <name>DATA</name>
5799              <description>Copy of DESCR_DST of the currently active descriptor.
5800
5801Base address of destination location.
5802
5803Note: For a CRC transfer descriptor, this field should be programmed with the address of the CRC_LFSR_CTL register. The calculated CRC LFSR state is written to this address (through the CRYPTO AHB-Lite master interface) when the input trigger is processed. The write transfer will be submitted to the CPUSS and PERI protection schemes.</description>
5804              <bitRange>[31:0]</bitRange>
5805              <access>read-only</access>
5806            </field>
5807          </fields>
5808        </register>
5809        <register>
5810          <name>ACT_DESCR_X_CTL</name>
5811          <description>Active descriptor X loop control</description>
5812          <addressOffset>0x30</addressOffset>
5813          <size>32</size>
5814          <access>read-only</access>
5815          <resetValue>0x0</resetValue>
5816          <resetMask>0x0</resetMask>
5817          <fields>
5818            <field>
5819              <name>DATA</name>
5820              <description>Copy of DESCR_X_CTL of the currently active descriptor.
5821
5822[11:0] SRC_X_INCR
5823Specifies increment of source address for each X loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. If this field is '0', the source address is not incremented. This is useful for reading from RX FIFO structures.
5824
5825[23:12] DST_X_INCR
5826Specifies increment of destination address for each X loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. If this field is '0', the destination address is not incremented. This is useful for writing to TX FIFO structures.
5827
5828Note: this field is not used for CRC transfer descriptors and must be set to '0'.
5829
5830[31:24] X_COUNT
5831Number of iterations (minus 1) of the 'X loop' (X_COUNT+1 is the number of single transfers in a 1D transfer). This field is an unsigned number in the range [0, 255], representing 1 through 256 iterations.
5832
5833For a single transfer descriptor type, descriptor will not have X_CTL.</description>
5834              <bitRange>[31:0]</bitRange>
5835              <access>read-only</access>
5836            </field>
5837          </fields>
5838        </register>
5839        <register>
5840          <name>ACT_DESCR_Y_CTL</name>
5841          <description>Active descriptor Y loop control</description>
5842          <addressOffset>0x34</addressOffset>
5843          <size>32</size>
5844          <access>read-only</access>
5845          <resetValue>0x0</resetValue>
5846          <resetMask>0x0</resetMask>
5847          <fields>
5848            <field>
5849              <name>DATA</name>
5850              <description>Copy of DESCR_Y_CTL of the currently active descriptor.
5851
5852[11:0] SRC_Y_INCR
5853Specifies increment of source address for each Y loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047].
5854
5855[23:12] DST_Y_INCR
5856Specifies increment of destination address for each Y loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047].
5857
5858[31:24] Y_COUNT
5859Number of iterations (minus 1) of the 'Y loop' (X_COUNT+1)*(Y_COUNT+1) is the number of single transfers in a 2D transfer). This field is an unsigned number in the range [0, 255], representing 1 through 256 iterations.
5860
5861For single, 1D and CRC transfer descriptor types, descriptor will not have Y_CTL.</description>
5862              <bitRange>[31:0]</bitRange>
5863              <access>read-only</access>
5864            </field>
5865          </fields>
5866        </register>
5867        <register>
5868          <name>ACT_DESCR_NEXT_PTR</name>
5869          <description>Active descriptor next pointer</description>
5870          <addressOffset>0x38</addressOffset>
5871          <size>32</size>
5872          <access>read-only</access>
5873          <resetValue>0x0</resetValue>
5874          <resetMask>0x0</resetMask>
5875          <fields>
5876            <field>
5877              <name>ADDR</name>
5878              <description>Copy of DESCR_NEXT_PTR of the currently active descriptor.
5879
5880[31:2] ADDR
5881Address of next descriptor in descriptor list. When this field is '0', this is the last descriptor in the descriptor list.</description>
5882              <bitRange>[31:2]</bitRange>
5883              <access>read-only</access>
5884            </field>
5885          </fields>
5886        </register>
5887        <register>
5888          <name>ACT_SRC</name>
5889          <description>Active source</description>
5890          <addressOffset>0x40</addressOffset>
5891          <size>32</size>
5892          <access>read-only</access>
5893          <resetValue>0x0</resetValue>
5894          <resetMask>0x0</resetMask>
5895          <fields>
5896            <field>
5897              <name>SRC_ADDR</name>
5898              <description>Current address of source location.</description>
5899              <bitRange>[31:0]</bitRange>
5900              <access>read-only</access>
5901            </field>
5902          </fields>
5903        </register>
5904        <register>
5905          <name>ACT_DST</name>
5906          <description>Active destination</description>
5907          <addressOffset>0x44</addressOffset>
5908          <size>32</size>
5909          <access>read-only</access>
5910          <resetValue>0x0</resetValue>
5911          <resetMask>0x0</resetMask>
5912          <fields>
5913            <field>
5914              <name>DST_ADDR</name>
5915              <description>Current address of destination location.</description>
5916              <bitRange>[31:0]</bitRange>
5917              <access>read-only</access>
5918            </field>
5919          </fields>
5920        </register>
5921        <register>
5922          <name>CRC_CTL</name>
5923          <description>CRC control</description>
5924          <addressOffset>0x100</addressOffset>
5925          <size>32</size>
5926          <access>read-write</access>
5927          <resetValue>0x0</resetValue>
5928          <resetMask>0x101</resetMask>
5929          <fields>
5930            <field>
5931              <name>DATA_REVERSE</name>
5932              <description>Specifies the bit order in which a data Byte is processed (reversal is performed after XORing):
5933'0': Most significant bit (bit 1) first.
5934'1': Least significant bit (bit 0) first.</description>
5935              <bitRange>[0:0]</bitRange>
5936              <access>read-write</access>
5937            </field>
5938            <field>
5939              <name>REM_REVERSE</name>
5940              <description>Specifies whether the remainder is bit reversed (reversal is performed after XORing):
5941'0': No.
5942'1': Yes.</description>
5943              <bitRange>[8:8]</bitRange>
5944              <access>read-write</access>
5945            </field>
5946          </fields>
5947        </register>
5948        <register>
5949          <name>CRC_DATA_CTL</name>
5950          <description>CRC data control</description>
5951          <addressOffset>0x110</addressOffset>
5952          <size>32</size>
5953          <access>read-write</access>
5954          <resetValue>0x0</resetValue>
5955          <resetMask>0xFF</resetMask>
5956          <fields>
5957            <field>
5958              <name>DATA_XOR</name>
5959              <description>Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal.</description>
5960              <bitRange>[7:0]</bitRange>
5961              <access>read-write</access>
5962            </field>
5963          </fields>
5964        </register>
5965        <register>
5966          <name>CRC_POL_CTL</name>
5967          <description>CRC polynomial control</description>
5968          <addressOffset>0x120</addressOffset>
5969          <size>32</size>
5970          <access>read-write</access>
5971          <resetValue>0x0</resetValue>
5972          <resetMask>0xFFFFFFFF</resetMask>
5973          <fields>
5974            <field>
5975              <name>POLYNOMIAL</name>
5976              <description>CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's. Some frequently used polynomials:
5977- CRC32: POLYNOMIAL is 0x04c11db7 (x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1).
5978- CRC16: POLYNOMIAL is 0x80050000 (x^16 + x^15 + x^2 + 1, shifted by 16 bit positions).
5979- CRC16 CCITT: POLYNOMIAL is 0x10210000 (x^16 + x^12 + x^5 + 1, shifted by 16 bit positions).</description>
5980              <bitRange>[31:0]</bitRange>
5981              <access>read-write</access>
5982            </field>
5983          </fields>
5984        </register>
5985        <register>
5986          <name>CRC_LFSR_CTL</name>
5987          <description>CRC LFSR control</description>
5988          <addressOffset>0x130</addressOffset>
5989          <size>32</size>
5990          <access>read-write</access>
5991          <resetValue>0x0</resetValue>
5992          <resetMask>0xFFFFFFFF</resetMask>
5993          <fields>
5994            <field>
5995              <name>LFSR32</name>
5996              <description>State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value.
5997
5998The seed value should be aligned such that the more significant bits (bit 31 and down) contain the seed value and the less significant bits (bit 0 and up) contain padding '0's.
5999
6000Note that SW can write this field. This functionality can be used prevent information leakage (through either CRC_LFSR_CTL or CRC_REM_RESULT).</description>
6001              <bitRange>[31:0]</bitRange>
6002              <access>read-write</access>
6003            </field>
6004          </fields>
6005        </register>
6006        <register>
6007          <name>CRC_REM_CTL</name>
6008          <description>CRC remainder control</description>
6009          <addressOffset>0x140</addressOffset>
6010          <size>32</size>
6011          <access>read-write</access>
6012          <resetValue>0x0</resetValue>
6013          <resetMask>0xFFFFFFFF</resetMask>
6014          <fields>
6015            <field>
6016              <name>REM_XOR</name>
6017              <description>Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal.</description>
6018              <bitRange>[31:0]</bitRange>
6019              <access>read-write</access>
6020            </field>
6021          </fields>
6022        </register>
6023        <register>
6024          <name>CRC_REM_RESULT</name>
6025          <description>CRC remainder result</description>
6026          <addressOffset>0x148</addressOffset>
6027          <size>32</size>
6028          <access>read-only</access>
6029          <resetValue>0x0</resetValue>
6030          <resetMask>0xFFFFFFFF</resetMask>
6031          <fields>
6032            <field>
6033              <name>REM</name>
6034              <description>Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE:
6035'0': the more significant bits (bit 31 and down) contain the remainder.
6036'1': the less significant bits (bit 0 and up) contain the remainder.
6037
6038Note: This field is combinatorially derived from CRC_LFSR_CTL.LFSR32, CRC_CTL.REM_REVERSE and CRC_REM_CTL.REM_XOR.</description>
6039              <bitRange>[31:0]</bitRange>
6040              <access>read-only</access>
6041            </field>
6042          </fields>
6043        </register>
6044        <cluster>
6045          <dim>16</dim>
6046          <dimIncrement>64</dimIncrement>
6047          <name>CH_STRUCT[%s]</name>
6048          <description>DW channel structure</description>
6049          <addressOffset>0x00008000</addressOffset>
6050          <register>
6051            <name>CH_CTL</name>
6052            <description>Channel control</description>
6053            <addressOffset>0x0</addressOffset>
6054            <size>32</size>
6055            <access>read-write</access>
6056            <resetValue>0x0</resetValue>
6057            <resetMask>0x80000300</resetMask>
6058            <fields>
6059              <field>
6060                <name>P</name>
6061                <description>User/privileged access control:
6062'0': user mode.
6063'1': privileged mode.
6064
6065This field is set with the user/privileged access control of the transaction that writes this register; i.e.  the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R).
6066
6067All transactions for this channel use the P field for the user/privileged access control ('hprot[1]').</description>
6068                <bitRange>[0:0]</bitRange>
6069                <access>read-write</access>
6070              </field>
6071              <field>
6072                <name>NS</name>
6073                <description>Secure/on-secure access control:
6074'0': secure.
6075'1': non-secure.
6076
6077This field is set with the secure/non-secure access control of the transaction that writes this register; i.e.  the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R).
6078
6079All transactions for this channel use the NS field for the secure/non-secure access control ('hnonsec').</description>
6080                <bitRange>[1:1]</bitRange>
6081                <access>read-write</access>
6082              </field>
6083              <field>
6084                <name>B</name>
6085                <description>Non-bufferable/bufferable access control:
6086'0': non-bufferable.
6087'1': bufferable.
6088
6089This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data.
6090
6091All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]').</description>
6092                <bitRange>[2:2]</bitRange>
6093                <access>read-write</access>
6094              </field>
6095              <field>
6096                <name>PC</name>
6097                <description>Protection context.
6098
6099This field is set with the protection context of the transaction that writes this register;  i.e.  the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R).
6100
6101All transactions for this channel uses the PC field for the protection context.
6102
6103Note: protection context (PC) is routed on 'hauser' bus of the AHB5 bus.</description>
6104                <bitRange>[7:4]</bitRange>
6105                <access>read-write</access>
6106              </field>
6107              <field>
6108                <name>PRIO</name>
6109                <description>Channel priority:
6110'0': highest priority.
6111'1'
6112'2'
6113'3': lowest priority.
6114
6115Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, round robin arbitration is applied. Round robin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group).</description>
6116                <bitRange>[9:8]</bitRange>
6117                <access>read-write</access>
6118              </field>
6119              <field>
6120                <name>PREEMPTABLE</name>
6121                <description>Specifies if the channel is preemptable.
6122'0': Not preemptable.
6123'1': Preemptable. This field allows higher priority pending channels (from a higher priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated.</description>
6124                <bitRange>[11:11]</bitRange>
6125                <access>read-write</access>
6126              </field>
6127              <field>
6128                <name>ENABLED</name>
6129                <description>Channel enable:
6130'0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pending channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed).
6131'1': Enabled.
6132
6133SW sets this field to '1' to enable a specific channel.
6134
6135HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE).</description>
6136                <bitRange>[31:31]</bitRange>
6137                <access>read-write</access>
6138              </field>
6139            </fields>
6140          </register>
6141          <register>
6142            <name>CH_STATUS</name>
6143            <description>Channel status</description>
6144            <addressOffset>0x4</addressOffset>
6145            <size>32</size>
6146            <access>read-only</access>
6147            <resetValue>0x0</resetValue>
6148            <resetMask>0x80000000</resetMask>
6149            <fields>
6150              <field>
6151                <name>INTR_CAUSE</name>
6152                <description>Specifies the source of the interrupt cause:
6153'0': NO_INTR
6154'1': COMPLETION
6155'2': SRC_BUS_ERROR
6156'3': DST_BUS_ERROR
6157'4': SRC_MISAL
6158'5': DST_MISAL
6159'6': CURR_PTR_NULL
6160'7': ACTIVE_CH_DISABLED
6161'8': DESCR_BUS_ERROR
6162'9'-'15': Not used.
6163
6164For error related interrupt causes (INTR_CAUSE is '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0').</description>
6165                <bitRange>[3:0]</bitRange>
6166                <access>read-only</access>
6167              </field>
6168              <field>
6169                <name>PENDING</name>
6170                <description>Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s)).</description>
6171                <bitRange>[31:31]</bitRange>
6172                <access>read-only</access>
6173              </field>
6174            </fields>
6175          </register>
6176          <register>
6177            <name>CH_IDX</name>
6178            <description>Channel current indices</description>
6179            <addressOffset>0x8</addressOffset>
6180            <size>32</size>
6181            <access>read-write</access>
6182            <resetValue>0x0</resetValue>
6183            <resetMask>0x0</resetMask>
6184            <fields>
6185              <field>
6186                <name>X_IDX</name>
6187                <description>Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor.
6188
6189Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor.
6190
6191Note: SW should set this field to '0' when it updates CH_CURR_PTR.</description>
6192                <bitRange>[7:0]</bitRange>
6193                <access>read-write</access>
6194              </field>
6195              <field>
6196                <name>Y_IDX</name>
6197                <description>Specifies the Y loop index, with X_COUNT taken from the current descriptor.
6198
6199Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor.
6200
6201Note: SW should set this field to '0' when it updates CH_CURR_PTR.</description>
6202                <bitRange>[15:8]</bitRange>
6203                <access>read-write</access>
6204              </field>
6205            </fields>
6206          </register>
6207          <register>
6208            <name>CH_CURR_PTR</name>
6209            <description>Channel current descriptor pointer</description>
6210            <addressOffset>0xC</addressOffset>
6211            <size>32</size>
6212            <access>read-write</access>
6213            <resetValue>0x0</resetValue>
6214            <resetMask>0x0</resetMask>
6215            <fields>
6216              <field>
6217                <name>ADDR</name>
6218                <description>Address of current descriptor. When this field is '0', there is no valid descriptor.
6219
6220Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor.
6221
6222Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'.</description>
6223                <bitRange>[31:2]</bitRange>
6224                <access>read-write</access>
6225              </field>
6226            </fields>
6227          </register>
6228          <register>
6229            <name>INTR</name>
6230            <description>Interrupt</description>
6231            <addressOffset>0x10</addressOffset>
6232            <size>32</size>
6233            <access>read-write</access>
6234            <resetValue>0x0</resetValue>
6235            <resetMask>0x1</resetMask>
6236            <fields>
6237              <field>
6238                <name>CH</name>
6239                <description>Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit.</description>
6240                <bitRange>[0:0]</bitRange>
6241                <access>read-write</access>
6242              </field>
6243            </fields>
6244          </register>
6245          <register>
6246            <name>INTR_SET</name>
6247            <description>Interrupt set</description>
6248            <addressOffset>0x14</addressOffset>
6249            <size>32</size>
6250            <access>read-write</access>
6251            <resetValue>0x0</resetValue>
6252            <resetMask>0x1</resetMask>
6253            <fields>
6254              <field>
6255                <name>CH</name>
6256                <description>Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect).</description>
6257                <bitRange>[0:0]</bitRange>
6258                <access>read-write</access>
6259              </field>
6260            </fields>
6261          </register>
6262          <register>
6263            <name>INTR_MASK</name>
6264            <description>Interrupt mask</description>
6265            <addressOffset>0x18</addressOffset>
6266            <size>32</size>
6267            <access>read-write</access>
6268            <resetValue>0x0</resetValue>
6269            <resetMask>0x1</resetMask>
6270            <fields>
6271              <field>
6272                <name>CH</name>
6273                <description>Mask for corresponding field in INTR register.</description>
6274                <bitRange>[0:0]</bitRange>
6275                <access>read-write</access>
6276              </field>
6277            </fields>
6278          </register>
6279          <register>
6280            <name>INTR_MASKED</name>
6281            <description>Interrupt masked</description>
6282            <addressOffset>0x1C</addressOffset>
6283            <size>32</size>
6284            <access>read-only</access>
6285            <resetValue>0x0</resetValue>
6286            <resetMask>0x1</resetMask>
6287            <fields>
6288              <field>
6289                <name>CH</name>
6290                <description>Logical and of corresponding INTR and INTR_MASK fields.</description>
6291                <bitRange>[0:0]</bitRange>
6292                <access>read-only</access>
6293              </field>
6294            </fields>
6295          </register>
6296          <register>
6297            <name>SRAM_DATA0</name>
6298            <description>SRAM data 0</description>
6299            <addressOffset>0x20</addressOffset>
6300            <size>32</size>
6301            <access>read-write</access>
6302            <resetValue>0x0</resetValue>
6303            <resetMask>0x0</resetMask>
6304            <fields>
6305              <field>
6306                <name>DATA</name>
6307                <description>N/A</description>
6308                <bitRange>[31:0]</bitRange>
6309                <access>read-write</access>
6310              </field>
6311            </fields>
6312          </register>
6313          <register>
6314            <name>SRAM_DATA1</name>
6315            <description>SRAM data 1</description>
6316            <addressOffset>0x24</addressOffset>
6317            <size>32</size>
6318            <access>read-write</access>
6319            <resetValue>0x0</resetValue>
6320            <resetMask>0x0</resetMask>
6321            <fields>
6322              <field>
6323                <name>DATA</name>
6324                <description>Refer SRAM_DATA0</description>
6325                <bitRange>[31:0]</bitRange>
6326                <access>read-write</access>
6327              </field>
6328            </fields>
6329          </register>
6330          <register>
6331            <name>TR_CMD</name>
6332            <description>Channel software trigger</description>
6333            <addressOffset>0x28</addressOffset>
6334            <size>32</size>
6335            <access>read-write</access>
6336            <resetValue>0x0</resetValue>
6337            <resetMask>0x1</resetMask>
6338            <fields>
6339              <field>
6340                <name>ACTIVATE</name>
6341                <description>Software trigger. When written with '1', a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0.</description>
6342                <bitRange>[0:0]</bitRange>
6343                <access>read-write</access>
6344              </field>
6345            </fields>
6346          </register>
6347        </cluster>
6348      </registers>
6349    </peripheral>
6350    <peripheral>
6351      <name>CPUSS</name>
6352      <description>SYSCPUSS registers</description>
6353      <baseAddress>0x401C0000</baseAddress>
6354      <addressBlock>
6355        <offset>0</offset>
6356        <size>16384</size>
6357        <usage>registers</usage>
6358      </addressBlock>
6359      <interrupt>
6360        <name>ioss_interrupts_gpio_0</name>
6361        <description>GPIO Port Interrupt #0</description>
6362        <value>0</value>
6363      </interrupt>
6364      <interrupt>
6365        <name>ioss_interrupts_gpio_1</name>
6366        <description>GPIO Port Interrupt #1</description>
6367        <value>1</value>
6368      </interrupt>
6369      <interrupt>
6370        <name>ioss_interrupts_gpio_2</name>
6371        <description>GPIO Port Interrupt #2</description>
6372        <value>2</value>
6373      </interrupt>
6374      <interrupt>
6375        <name>ioss_interrupts_gpio_3</name>
6376        <description>GPIO Port Interrupt #3</description>
6377        <value>3</value>
6378      </interrupt>
6379      <interrupt>
6380        <name>ioss_interrupts_gpio_4</name>
6381        <description>GPIO Port Interrupt #4</description>
6382        <value>4</value>
6383      </interrupt>
6384      <interrupt>
6385        <name>ioss_interrupts_gpio_5</name>
6386        <description>GPIO Port Interrupt #5</description>
6387        <value>5</value>
6388      </interrupt>
6389      <interrupt>
6390        <name>ioss_interrupt_vdd</name>
6391        <description>GPIO Supply Detect Interrupt</description>
6392        <value>6</value>
6393      </interrupt>
6394      <interrupt>
6395        <name>ioss_interrupt_gpio</name>
6396        <description>GPIO All Ports</description>
6397        <value>7</value>
6398      </interrupt>
6399      <interrupt>
6400        <name>scb_0_interrupt</name>
6401        <description>Serial Communication Block #0 (DeepSleep capable)</description>
6402        <value>8</value>
6403      </interrupt>
6404      <interrupt>
6405        <name>srss_interrupt_mcwdt_0</name>
6406        <description>Multi Counter Watchdog Timer interrupt</description>
6407        <value>9</value>
6408      </interrupt>
6409      <interrupt>
6410        <name>srss_interrupt_backup</name>
6411        <description>Backup domain interrupt</description>
6412        <value>10</value>
6413      </interrupt>
6414      <interrupt>
6415        <name>srss_interrupt</name>
6416        <description>Other combined Interrupts for srss (LVD and CLKCAL, CLKCAL only supported in Active mode)</description>
6417        <value>11</value>
6418      </interrupt>
6419      <interrupt>
6420        <name>cpuss_interrupts_ipc_dpslp_0</name>
6421        <description>cpuss Inter Process Communication Interrupt #0</description>
6422        <value>12</value>
6423      </interrupt>
6424      <interrupt>
6425        <name>cpuss_interrupts_ipc_dpslp_1</name>
6426        <description>cpuss Inter Process Communication Interrupt #1</description>
6427        <value>13</value>
6428      </interrupt>
6429      <interrupt>
6430        <name>keyscan_interrupt</name>
6431        <description>mxkeyscan interrupt for keyscan edge or fifo thresh to WIC in M33</description>
6432        <value>14</value>
6433      </interrupt>
6434      <interrupt>
6435        <name>srss_interrupt_wdt</name>
6436        <description>Interrupt from WDT</description>
6437        <value>15</value>
6438      </interrupt>
6439      <interrupt>
6440        <name>btss_interrupt_btss_ipc</name>
6441        <description>interrupt from BTSS IPC</description>
6442        <value>16</value>
6443      </interrupt>
6444      <interrupt>
6445        <name>scb_1_interrupt</name>
6446        <description>Serial Communication Block #1</description>
6447        <value>17</value>
6448      </interrupt>
6449      <interrupt>
6450        <name>scb_2_interrupt</name>
6451        <description>Serial Communication Block #2</description>
6452        <value>18</value>
6453      </interrupt>
6454      <interrupt>
6455        <name>cpuss_interrupts_dw0_0</name>
6456        <description>cpuss DataWire #0, Channel #0</description>
6457        <value>19</value>
6458      </interrupt>
6459      <interrupt>
6460        <name>cpuss_interrupts_dw0_1</name>
6461        <description>cpuss DataWire #0, Channel #1</description>
6462        <value>20</value>
6463      </interrupt>
6464      <interrupt>
6465        <name>cpuss_interrupts_dw0_2</name>
6466        <description>cpuss DataWire #0, Channel #2</description>
6467        <value>21</value>
6468      </interrupt>
6469      <interrupt>
6470        <name>cpuss_interrupts_dw0_3</name>
6471        <description>cpuss DataWire #0, Channel #3</description>
6472        <value>22</value>
6473      </interrupt>
6474      <interrupt>
6475        <name>cpuss_interrupts_dw0_4</name>
6476        <description>cpuss DataWire #0, Channel #4</description>
6477        <value>23</value>
6478      </interrupt>
6479      <interrupt>
6480        <name>cpuss_interrupts_dw0_5</name>
6481        <description>cpuss DataWire #0, Channel #5</description>
6482        <value>24</value>
6483      </interrupt>
6484      <interrupt>
6485        <name>cpuss_interrupts_dw0_6</name>
6486        <description>cpuss DataWire #0, Channel #6</description>
6487        <value>25</value>
6488      </interrupt>
6489      <interrupt>
6490        <name>cpuss_interrupts_dw0_7</name>
6491        <description>cpuss DataWire #0, Channel #7</description>
6492        <value>26</value>
6493      </interrupt>
6494      <interrupt>
6495        <name>cpuss_interrupts_dw0_8</name>
6496        <description>cpuss DataWire #0, Channel #8</description>
6497        <value>27</value>
6498      </interrupt>
6499      <interrupt>
6500        <name>cpuss_interrupts_dw0_9</name>
6501        <description>cpuss DataWire #0, Channel #9</description>
6502        <value>28</value>
6503      </interrupt>
6504      <interrupt>
6505        <name>cpuss_interrupts_dw0_10</name>
6506        <description>cpuss DataWire #0, Channel #10</description>
6507        <value>29</value>
6508      </interrupt>
6509      <interrupt>
6510        <name>cpuss_interrupts_dw0_11</name>
6511        <description>cpuss DataWire #0, Channel #11</description>
6512        <value>30</value>
6513      </interrupt>
6514      <interrupt>
6515        <name>cpuss_interrupts_dw0_12</name>
6516        <description>cpuss DataWire #0, Channel #12</description>
6517        <value>31</value>
6518      </interrupt>
6519      <interrupt>
6520        <name>cpuss_interrupts_dw0_13</name>
6521        <description>cpuss DataWire #0, Channel #13</description>
6522        <value>32</value>
6523      </interrupt>
6524      <interrupt>
6525        <name>cpuss_interrupts_dw0_14</name>
6526        <description>cpuss DataWire #0, Channel #14</description>
6527        <value>33</value>
6528      </interrupt>
6529      <interrupt>
6530        <name>cpuss_interrupts_dw0_15</name>
6531        <description>cpuss DataWire #0, Channel #15</description>
6532        <value>34</value>
6533      </interrupt>
6534      <interrupt>
6535        <name>cpuss_interrupt_mpc_promc</name>
6536        <description>PROMC Int</description>
6537        <value>35</value>
6538      </interrupt>
6539      <interrupt>
6540        <name>cpuss_interrupt_ppu_sramc0</name>
6541        <description>PPU SRAM0</description>
6542        <value>36</value>
6543      </interrupt>
6544      <interrupt>
6545        <name>cpuss_interrupt_mpc_sramc0</name>
6546        <description>MPC SRAM0</description>
6547        <value>37</value>
6548      </interrupt>
6549      <interrupt>
6550        <name>cpuss_interrupt_cm33_0_fp</name>
6551        <description>CM33 0 Floating Point Interrupt</description>
6552        <value>38</value>
6553      </interrupt>
6554      <interrupt>
6555        <name>cpuss_interrupts_cm33_0_cti_0</name>
6556        <description>CM33-0 CTI interrupt outputs</description>
6557        <value>39</value>
6558      </interrupt>
6559      <interrupt>
6560        <name>cpuss_interrupts_cm33_0_cti_1</name>
6561        <description>CM33-1 CTI interrupt outputs</description>
6562        <value>40</value>
6563      </interrupt>
6564      <interrupt>
6565        <name>cpuss_interrupt_exp_br_ahb_error</name>
6566        <description>EXPANSION BRIDGE AHB Error interrupt</description>
6567        <value>41</value>
6568      </interrupt>
6569      <interrupt>
6570        <name>tcpwm_0_interrupts_0</name>
6571        <description>TCPWM #0, Counter #0</description>
6572        <value>42</value>
6573      </interrupt>
6574      <interrupt>
6575        <name>tcpwm_0_interrupts_1</name>
6576        <description>TCPWM #0, Counter #1</description>
6577        <value>43</value>
6578      </interrupt>
6579      <interrupt>
6580        <name>tcpwm_0_interrupts_256</name>
6581        <description>TCPWM #0, Counter #256</description>
6582        <value>44</value>
6583      </interrupt>
6584      <interrupt>
6585        <name>tcpwm_0_interrupts_257</name>
6586        <description>TCPWM #0, Counter #257</description>
6587        <value>45</value>
6588      </interrupt>
6589      <interrupt>
6590        <name>tcpwm_0_interrupts_258</name>
6591        <description>TCPWM #0, Counter #258</description>
6592        <value>46</value>
6593      </interrupt>
6594      <interrupt>
6595        <name>tcpwm_0_interrupts_259</name>
6596        <description>TCPWM #0, Counter #259</description>
6597        <value>47</value>
6598      </interrupt>
6599      <interrupt>
6600        <name>tcpwm_0_interrupts_260</name>
6601        <description>TCPWM #0, Counter #260</description>
6602        <value>48</value>
6603      </interrupt>
6604      <interrupt>
6605        <name>tcpwm_0_interrupts_261</name>
6606        <description>TCPWM #0, Counter #261</description>
6607        <value>49</value>
6608      </interrupt>
6609      <interrupt>
6610        <name>tcpwm_0_interrupts_262</name>
6611        <description>TCPWM #0, Counter #262</description>
6612        <value>50</value>
6613      </interrupt>
6614      <interrupt>
6615        <name>smif_interrupt_normal</name>
6616        <description>Serial Memory Interface interrupt</description>
6617        <value>51</value>
6618      </interrupt>
6619      <interrupt>
6620        <name>smif_interrupt_mpc</name>
6621        <description>Serial Memory Interface interrupt</description>
6622        <value>52</value>
6623      </interrupt>
6624      <interrupt>
6625        <name>tdm_0_interrupts_rx_0</name>
6626        <description>TDM0 Audio interrupt RX</description>
6627        <value>53</value>
6628      </interrupt>
6629      <interrupt>
6630        <name>tdm_0_interrupts_tx_0</name>
6631        <description>TDM0 Audio interrupt TX</description>
6632        <value>54</value>
6633      </interrupt>
6634      <interrupt>
6635        <name>pdm_0_interrupts_0</name>
6636        <description>PDM0/PCM0 Audio interrupt</description>
6637        <value>55</value>
6638      </interrupt>
6639      <interrupt>
6640        <name>pdm_0_interrupts_1</name>
6641        <description>PDM0/PCM0 Audio interrupt</description>
6642        <value>56</value>
6643      </interrupt>
6644      <interrupt>
6645        <name>srss_interrupt_main_ppu</name>
6646        <description>SRSS Main PPU Interrupt</description>
6647        <value>57</value>
6648      </interrupt>
6649      <interrupt>
6650        <name>peri_interrupt_ppc</name>
6651        <description>PERI PPC Interrupt</description>
6652        <value>58</value>
6653      </interrupt>
6654      <interrupt>
6655        <name>peri_interrupt_ahb_error</name>
6656        <description>PERI AHB Interrupt</description>
6657        <value>59</value>
6658      </interrupt>
6659      <interrupt>
6660        <name>lin_0_interrupts_0</name>
6661        <description>LIN Interrupt, Channel #0</description>
6662        <value>60</value>
6663      </interrupt>
6664      <interrupt>
6665        <name>lin_0_interrupts_1</name>
6666        <description>LIN Interrupt, Channel #1</description>
6667        <value>61</value>
6668      </interrupt>
6669      <interrupt>
6670        <name>crypto_interrupt_error</name>
6671        <description>Crypto Interrupt</description>
6672        <value>62</value>
6673      </interrupt>
6674      <interrupt>
6675        <name>cpuss_interrupt_ppu_cpuss</name>
6676        <description>CPUSS PPU Interrupt</description>
6677        <value>63</value>
6678      </interrupt>
6679      <interrupt>
6680        <name>canfd_0_interrupts0_0</name>
6681        <description>CAN #0, Interrupt #0, Channel #0</description>
6682        <value>64</value>
6683      </interrupt>
6684      <interrupt>
6685        <name>canfd_0_interrupts1_0</name>
6686        <description>CAN #0, Interrupt #1, Channel #0</description>
6687        <value>65</value>
6688      </interrupt>
6689      <interrupt>
6690        <name>canfd_0_interrupt0</name>
6691        <description>Can #0, Consolidated interrupt #0</description>
6692        <value>66</value>
6693      </interrupt>
6694      <interrupt>
6695        <name>adcmic_interrupt_adcmic</name>
6696        <description>ADCMIC interrupt</description>
6697        <value>67</value>
6698      </interrupt>
6699      <interrupt>
6700        <name>btss_interrupt_btss_exception</name>
6701        <description>interrupt indicating BTSS has encountered exception</description>
6702        <value>68</value>
6703      </interrupt>
6704      <interrupt>
6705        <name>crypto_interrupt_trng</name>
6706        <description>Crypto TRNG Interrupt</description>
6707        <value>69</value>
6708      </interrupt>
6709      <registers>
6710        <register>
6711          <name>IDENTITY</name>
6712          <description>Identity</description>
6713          <addressOffset>0x0</addressOffset>
6714          <size>32</size>
6715          <access>read-only</access>
6716          <resetValue>0x0</resetValue>
6717          <resetMask>0x0</resetMask>
6718          <fields>
6719            <field>
6720              <name>P</name>
6721              <description>This field specifies the privileged setting ('0': user mode; '1': privileged mode) of the transfer that reads the register.</description>
6722              <bitRange>[0:0]</bitRange>
6723              <access>read-only</access>
6724            </field>
6725            <field>
6726              <name>NS</name>
6727              <description>This field specifies the security setting ('0': secure mode; '1': non-secure mode) of the transfer that reads the register.</description>
6728              <bitRange>[1:1]</bitRange>
6729              <access>read-only</access>
6730            </field>
6731            <field>
6732              <name>PC</name>
6733              <description>This field specifies the protection context of the transfer that reads the register.</description>
6734              <bitRange>[7:4]</bitRange>
6735              <access>read-only</access>
6736            </field>
6737            <field>
6738              <name>MS</name>
6739              <description>This field specifies the bus master identifier of the transfer that reads the register.</description>
6740              <bitRange>[15:8]</bitRange>
6741              <access>read-only</access>
6742            </field>
6743          </fields>
6744        </register>
6745        <register>
6746          <name>PRODUCT_ID</name>
6747          <description>Product identifier and version (same as CoreSight RomTables)</description>
6748          <addressOffset>0x10</addressOffset>
6749          <size>32</size>
6750          <access>read-only</access>
6751          <resetValue>0x0</resetValue>
6752          <resetMask>0xFFF</resetMask>
6753          <fields>
6754            <field>
6755              <name>FAMILY_ID</name>
6756              <description>Family ID. Common ID for a product family.</description>
6757              <bitRange>[11:0]</bitRange>
6758              <access>read-only</access>
6759            </field>
6760            <field>
6761              <name>MAJOR_REV</name>
6762              <description>Major Revision, starts with 1, increments with all layer tape-out (implemented with metal ECO-able  tie-off)</description>
6763              <bitRange>[19:16]</bitRange>
6764              <access>read-only</access>
6765            </field>
6766            <field>
6767              <name>MINOR_REV</name>
6768              <description>Minor Revision, starts with 1, increments with metal layer only tape-out (implemented with metal ECO-able  tie-off)</description>
6769              <bitRange>[23:20]</bitRange>
6770              <access>read-only</access>
6771            </field>
6772          </fields>
6773        </register>
6774        <register>
6775          <name>DP_STATUS</name>
6776          <description>Debug port status</description>
6777          <addressOffset>0x20</addressOffset>
6778          <size>32</size>
6779          <access>read-only</access>
6780          <resetValue>0x4</resetValue>
6781          <resetMask>0x7</resetMask>
6782          <fields>
6783            <field>
6784              <name>SWJ_CONNECTED</name>
6785              <description>Specifies if the SWJ debug port is connected; i.e. debug host interface is active:
6786'0': Not connected/not active.
6787'1': Connected/active.</description>
6788              <bitRange>[0:0]</bitRange>
6789              <access>read-only</access>
6790            </field>
6791            <field>
6792              <name>SWJ_DEBUG_EN</name>
6793              <description>Specifies if SWJ debug is enabled, i.e. CDBGPWRUPACK is '1' and thus debug clocks are on:
6794'0': Disabled.
6795'1': Enabled.</description>
6796              <bitRange>[1:1]</bitRange>
6797              <access>read-only</access>
6798            </field>
6799            <field>
6800              <name>SWJ_JTAG_SEL</name>
6801              <description>Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL is '0' (SWJ mode selected) and SWJ_CONNECTED is '1' (SWJ is connected).
6802'0': SWD selected.
6803'1': JTAG selected.</description>
6804              <bitRange>[2:2]</bitRange>
6805              <access>read-only</access>
6806            </field>
6807          </fields>
6808        </register>
6809        <register>
6810          <name>BUFF_CTL</name>
6811          <description>Buffer control</description>
6812          <addressOffset>0x30</addressOffset>
6813          <size>32</size>
6814          <access>read-write</access>
6815          <resetValue>0x1</resetValue>
6816          <resetMask>0x1</resetMask>
6817          <fields>
6818            <field>
6819              <name>WRITE_BUFF</name>
6820              <description>Specifies if write transfer can be buffered in the bus infrastructure bridges:
6821'0': Write transfers are not buffered, independent of the transfer's bufferable attribute.
6822'1': Write transfers can be buffered, if the transfer's bufferable attribute indicates that the transfer is a bufferable/posted write.
6823
6824This bit will control only the IPs which use mxambatk AHB2AHB bridge (mxambatk_ahb2ahb) and it will NOT control the buffering that may be happening in bus infrastructure components used from ARM SIE200.</description>
6825              <bitRange>[0:0]</bitRange>
6826              <access>read-write</access>
6827            </field>
6828          </fields>
6829        </register>
6830        <register>
6831          <name>CAL_SUP_SET</name>
6832          <description>Calibration support set and read</description>
6833          <addressOffset>0x40</addressOffset>
6834          <size>32</size>
6835          <access>read-write</access>
6836          <resetValue>0x0</resetValue>
6837          <resetMask>0xFFFFFFFF</resetMask>
6838          <fields>
6839            <field>
6840              <name>DATA</name>
6841              <description>Read without side effect, write 1 to set</description>
6842              <bitRange>[31:0]</bitRange>
6843              <access>read-write</access>
6844            </field>
6845          </fields>
6846        </register>
6847        <register>
6848          <name>CAL_SUP_CLR</name>
6849          <description>Calibration support clear and reset</description>
6850          <addressOffset>0x44</addressOffset>
6851          <size>32</size>
6852          <access>read-write</access>
6853          <resetValue>0x0</resetValue>
6854          <resetMask>0xFFFFFFFF</resetMask>
6855          <fields>
6856            <field>
6857              <name>DATA</name>
6858              <description>Read side effect: when read all bits are cleared, write 1 to clear a specific bit
6859Note: no exception for the debug host, it also causes the read side effect</description>
6860              <bitRange>[31:0]</bitRange>
6861              <access>read-write</access>
6862            </field>
6863          </fields>
6864        </register>
6865        <register>
6866          <name>INFRA_CTL</name>
6867          <description>Infrastructure Control</description>
6868          <addressOffset>0x50</addressOffset>
6869          <size>32</size>
6870          <access>read-write</access>
6871          <resetValue>0x0</resetValue>
6872          <resetMask>0x1</resetMask>
6873          <fields>
6874            <field>
6875              <name>CLOCK_FORCE</name>
6876              <description>Force Infrastructure clock gating to be always ON.
68770: Disabled
68781: Enabled</description>
6879              <bitRange>[0:0]</bitRange>
6880              <access>read-write</access>
6881            </field>
6882          </fields>
6883        </register>
6884        <register>
6885          <name>SYSTICK_NS_CTL</name>
6886          <description>Non Secure SysTick timer control</description>
6887          <addressOffset>0x120</addressOffset>
6888          <size>32</size>
6889          <access>read-write</access>
6890          <resetValue>0x40000147</resetValue>
6891          <resetMask>0xC3FFFFFF</resetMask>
6892          <fields>
6893            <field>
6894              <name>TENMS</name>
6895              <description>Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g., for a 32,768 Hz reference clock, TENMS is 328 - 1 = 327.</description>
6896              <bitRange>[23:0]</bitRange>
6897              <access>read-write</access>
6898            </field>
6899            <field>
6900              <name>CLOCK_SOURCE</name>
6901              <description>Specifies an external clock source:
6902'0': The low frequency clock 'clk_lf' is selected. The precision of this clock depends on whether the low frequency clock source is a SRSS internal RC oscillator (imprecise) or a device external crystal oscillator (precise).
6903'1': The internal main oscillator (IMO) clock 'clk_imo' is selected. The MXS40 platform uses a fixed frequency IMO clock.
6904o '2': The external crystal oscillator (ECO) clock 'clk_eco' is selected.
6905'3': The SRSS 'clk_timer' is selected ('clk_timer' is a divided/gated version of 'clk_hf' or 'clk_imo').
6906
6907Note: If NOREF is '1', the CLOCK_SOURCE value is NOT used.
6908Note: It is SW's responsibility to provide the correct NOREF, SKEW and TENMS field values for the selected clock source.</description>
6909              <bitRange>[25:24]</bitRange>
6910              <access>read-write</access>
6911            </field>
6912            <field>
6913              <name>SKEW</name>
6914              <description>Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock:
6915'0': Precise.
6916'1': Imprecise.</description>
6917              <bitRange>[30:30]</bitRange>
6918              <access>read-write</access>
6919            </field>
6920            <field>
6921              <name>NOREF</name>
6922              <description>Specifies if an external clock source is provided:
6923'0': An external clock source is provided.
6924'1': An external clock source is NOT provided and only the CPU internal clock can be used as SysTick timer clock source.</description>
6925              <bitRange>[31:31]</bitRange>
6926              <access>read-write</access>
6927            </field>
6928          </fields>
6929        </register>
6930        <register>
6931          <name>AHB_ERROR_STATUS1</name>
6932          <description>AHB Error status1</description>
6933          <addressOffset>0x210</addressOffset>
6934          <size>32</size>
6935          <access>read-only</access>
6936          <resetValue>0x0</resetValue>
6937          <resetMask>0xFFFFFFFF</resetMask>
6938          <fields>
6939            <field>
6940              <name>ADDR</name>
6941              <description>This field indicates the AHB transaction address[31:0] that the AHB ERROR detected. This field is valid when INTR_AHB_ERROR.AHB_ERROR is set.</description>
6942              <bitRange>[31:0]</bitRange>
6943              <access>read-only</access>
6944            </field>
6945          </fields>
6946        </register>
6947        <register>
6948          <name>AHB_ERROR_STATUS2</name>
6949          <description>AHB Error status2</description>
6950          <addressOffset>0x214</addressOffset>
6951          <size>32</size>
6952          <access>read-only</access>
6953          <resetValue>0x0</resetValue>
6954          <resetMask>0xFFF7</resetMask>
6955          <fields>
6956            <field>
6957              <name>P</name>
6958              <description>This field indicates the atributes of AHB transaction where AHB ERROR detected. This field is valid when INTR_AHB_ERROR.AHB_ERROR is set.
6959P - '1' inidcates priviliged mode; '0' indicates user mode</description>
6960              <bitRange>[0:0]</bitRange>
6961              <access>read-only</access>
6962            </field>
6963            <field>
6964              <name>NS</name>
6965              <description>NS - '1' indicates non secure transfer; '0' indicates secure transfer.</description>
6966              <bitRange>[1:1]</bitRange>
6967              <access>read-only</access>
6968            </field>
6969            <field>
6970              <name>W</name>
6971              <description>W - '1' inidicates write; '0' indicates read.</description>
6972              <bitRange>[2:2]</bitRange>
6973              <access>read-only</access>
6974            </field>
6975            <field>
6976              <name>PC</name>
6977              <description>PC - protection context</description>
6978              <bitRange>[7:4]</bitRange>
6979              <access>read-only</access>
6980            </field>
6981            <field>
6982              <name>MS</name>
6983              <description>MS - master ID of AHB master from which transfer is initiated.</description>
6984              <bitRange>[15:8]</bitRange>
6985              <access>read-only</access>
6986            </field>
6987          </fields>
6988        </register>
6989        <register>
6990          <name>INTR_AHB_ERROR</name>
6991          <description>Interrupt AHB ERROR</description>
6992          <addressOffset>0x220</addressOffset>
6993          <size>32</size>
6994          <access>read-write</access>
6995          <resetValue>0x0</resetValue>
6996          <resetMask>0x1</resetMask>
6997          <fields>
6998            <field>
6999              <name>AHB_ERROR</name>
7000              <description>This interrupt cause field is activated (HW sets the field to '1') when there is an AHB error response from slaves on EXPANSION bridge.
7001
7002SW writes a '1' to this field to clear the interrupt cause to '0'. The HW captures a new interrupt only after clearing the interrupt cause.</description>
7003              <bitRange>[0:0]</bitRange>
7004              <access>read-write</access>
7005            </field>
7006          </fields>
7007        </register>
7008        <register>
7009          <name>INTR_SET_AHB_ERROR</name>
7010          <description>Interrupt AHB ERROR set</description>
7011          <addressOffset>0x224</addressOffset>
7012          <size>32</size>
7013          <access>read-write</access>
7014          <resetValue>0x0</resetValue>
7015          <resetMask>0x1</resetMask>
7016          <fields>
7017            <field>
7018              <name>AHB_ERROR</name>
7019              <description>Write INTR_SET field with '1' to set corresponding INTR_AHB_ERROR.AHB_ERROR field (a write of '0' has no effect).
7020
7021Note that when this register is set by S/W, the AHB_ERROR_STATUS1 and AHB_ERROR_STATUS2 doesn't indicate actual cause data and these status indication needs to be ignored at that time.</description>
7022              <bitRange>[0:0]</bitRange>
7023              <access>read-write</access>
7024            </field>
7025          </fields>
7026        </register>
7027        <register>
7028          <name>INTR_MASK_AHB_ERROR</name>
7029          <description>Interrupt AHB ERROR mask</description>
7030          <addressOffset>0x228</addressOffset>
7031          <size>32</size>
7032          <access>read-write</access>
7033          <resetValue>0x0</resetValue>
7034          <resetMask>0x1</resetMask>
7035          <fields>
7036            <field>
7037              <name>AHB_ERROR</name>
7038              <description>Mask bit for corresponding field in the INTR register.</description>
7039              <bitRange>[0:0]</bitRange>
7040              <access>read-write</access>
7041            </field>
7042          </fields>
7043        </register>
7044        <register>
7045          <name>INTR_MASKED_AHB_ERROR</name>
7046          <description>Interrupt AHB ERROR masked</description>
7047          <addressOffset>0x22C</addressOffset>
7048          <size>32</size>
7049          <access>read-only</access>
7050          <resetValue>0x0</resetValue>
7051          <resetMask>0x1</resetMask>
7052          <fields>
7053            <field>
7054              <name>AHB_ERROR</name>
7055              <description>Logical and of corresponding INTR and INTR_MASK fields.</description>
7056              <bitRange>[0:0]</bitRange>
7057              <access>read-only</access>
7058            </field>
7059          </fields>
7060        </register>
7061        <register>
7062          <name>AP_CTL</name>
7063          <description>Access port control</description>
7064          <addressOffset>0x1000</addressOffset>
7065          <size>32</size>
7066          <access>read-write</access>
7067          <resetValue>0x0</resetValue>
7068          <resetMask>0xFF70FF7</resetMask>
7069          <fields>
7070            <field>
7071              <name>CM33_0_ENABLE</name>
7072              <description>Enables the CM33_0 AP interface:
7073'0': Disabled.
7074'1': Enabled.</description>
7075              <bitRange>[0:0]</bitRange>
7076              <access>read-write</access>
7077            </field>
7078            <field>
7079              <name>CM33_1_ENABLE</name>
7080              <description>Enables the CM33_1 AP interface:
7081'0': Disabled.
7082'1': Enabled.</description>
7083              <bitRange>[1:1]</bitRange>
7084              <access>read-write</access>
7085            </field>
7086            <field>
7087              <name>SYS_ENABLE</name>
7088              <description>Enables the system AP interface:
7089'0': Disabled.
7090'1': Enabled.</description>
7091              <bitRange>[2:2]</bitRange>
7092              <access>read-write</access>
7093            </field>
7094            <field>
7095              <name>CM33_0_DBG_ENABLE</name>
7096              <description>Invasive debug enable for CM33_0.
7097'0': Disables all halt-mode and invasive debug features.
7098'1': Enables invasive debug features.</description>
7099              <bitRange>[4:4]</bitRange>
7100              <access>read-write</access>
7101            </field>
7102            <field>
7103              <name>CM33_0_NID_ENABLE</name>
7104              <description>Non-invasive debug enable for CM33_0.
7105'0': Disables all trace and non-invasive debug features.
7106'1': Enables all trace and non-invasive debug features.</description>
7107              <bitRange>[5:5]</bitRange>
7108              <access>read-write</access>
7109            </field>
7110            <field>
7111              <name>CM33_0_SPID_ENABLE</name>
7112              <description>Secure invasive debug enable for CM33_0.
7113'0': disables all halt mode and invasive debug features when the processor is in Secure state.
7114'1': Enables all halt mode and invasive debug features when the processor is in Secure state.</description>
7115              <bitRange>[6:6]</bitRange>
7116              <access>read-write</access>
7117            </field>
7118            <field>
7119              <name>CM33_0_SPNID_ENABLE</name>
7120              <description>Secure non-invasive debug enable for CM33_0.
7121'0': Disables non-invasive debug features when the processor is in Secure state.
7122'1': Enables non-invasive debug features when the processor is in Secure state.</description>
7123              <bitRange>[7:7]</bitRange>
7124              <access>read-write</access>
7125            </field>
7126            <field>
7127              <name>CM33_1_DBG_ENABLE</name>
7128              <description>Refer CM33_0_DBG_ENABLE.</description>
7129              <bitRange>[8:8]</bitRange>
7130              <access>read-write</access>
7131            </field>
7132            <field>
7133              <name>CM33_1_NID_ENABLE</name>
7134              <description>Refer CM33_0_NID_ENABLE.</description>
7135              <bitRange>[9:9]</bitRange>
7136              <access>read-write</access>
7137            </field>
7138            <field>
7139              <name>CM33_1_SPID_ENABLE</name>
7140              <description>Refer CM33_0_SPID_ENABLE.</description>
7141              <bitRange>[10:10]</bitRange>
7142              <access>read-write</access>
7143            </field>
7144            <field>
7145              <name>CM33_1_SPNID_ENABLE</name>
7146              <description>Refer CM33_0_SPNID_ENABLE.</description>
7147              <bitRange>[11:11]</bitRange>
7148              <access>read-write</access>
7149            </field>
7150            <field>
7151              <name>CM33_0_DISABLE</name>
7152              <description>Disables the CM33_0 AP interface:
7153'0': Enabled.
7154'1': Disabled.
7155
7156Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM0_DISABLE is '0' and CM0_ENABLE is '1'.</description>
7157              <bitRange>[16:16]</bitRange>
7158              <access>read-write</access>
7159            </field>
7160            <field>
7161              <name>CM33_1_DISABLE</name>
7162              <description>Disables the CM33_1 AP interface:
7163'0': Enabled.
7164'1': Disabled.
7165
7166Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM33_DISABLE is '0' and CM33_ENABLE is '1'.</description>
7167              <bitRange>[17:17]</bitRange>
7168              <access>read-write</access>
7169            </field>
7170            <field>
7171              <name>SYS_DISABLE</name>
7172              <description>Disables the system AP interface:
7173'0': Enabled.
7174'1': Disabled.
7175
7176Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when SYS_DISABLE is '0' and SYS_ENABLE is '1'.</description>
7177              <bitRange>[18:18]</bitRange>
7178              <access>read-write</access>
7179            </field>
7180            <field>
7181              <name>CM33_0_DBG_DISABLE</name>
7182              <description>Disable Invasive debug for CM33_0.
7183'1': Disables all halt-mode and invasive debug features.
7184'0': Enables invasive debug features.
7185
7186Typically, this field is set by the Cypress boot code with information from eFUSE. The invasive debug is only enabled when CM33_0_DBG_DISABLE is '0' and CM33_0_DBG_ENABLE is '1'.</description>
7187              <bitRange>[20:20]</bitRange>
7188              <access>read-write</access>
7189            </field>
7190            <field>
7191              <name>CM33_0_NID_DISABLE</name>
7192              <description>Disable Non-invasive debug for CM33_0.
7193'1': Disables all trace and non-invasive debug features.
7194'0': Enables all trace and non-invasive debug features.
7195
7196Typically, this field is set by the Cypress boot code with information from eFUSE. The non-invasive debug is only enabled when CM33_0_NID_DISABLE is '0' and CM33_0_NID_ENABLE is '1'.</description>
7197              <bitRange>[21:21]</bitRange>
7198              <access>read-write</access>
7199            </field>
7200            <field>
7201              <name>CM33_0_SPID_DISABLE</name>
7202              <description>Secure invasive debug disable for CM33_0.
7203'1': disables all halt mode and invasive debug features when the processor is in Secure state.
7204'0': Enables all halt mode and invasive debug features when the processor is in Secure state.
7205
7206Typically, this field is set by the Cypress boot code with information from eFUSE. The invasive debug in secure state is only enabled when CM33_0_SPID_DISABLE is '0' and CM33_0_SPID_ENABLE is '1'.</description>
7207              <bitRange>[22:22]</bitRange>
7208              <access>read-write</access>
7209            </field>
7210            <field>
7211              <name>CM33_0_SPNID_DISABLE</name>
7212              <description>Secure non-invasive debug disable for CM33_0.
7213'1': Disables non-invasive debug features when the processor is in Secure state.
7214'0': Enables non-invasive debug features when the processor is in Secure state.
7215
7216Typically, this field is set by the Cypress boot code with information from eFUSE. The non-invasive debug in secure state is only enabled when CM33_0_SPNID_DISABLE is '0' and CM33_0_SPNID_ENABLE is '1'.</description>
7217              <bitRange>[23:23]</bitRange>
7218              <access>read-write</access>
7219            </field>
7220            <field>
7221              <name>CM33_1_DBG_DISABLE</name>
7222              <description>Refer CM33_0_DBG_DISABLE description.</description>
7223              <bitRange>[24:24]</bitRange>
7224              <access>read-write</access>
7225            </field>
7226            <field>
7227              <name>CM33_1_NID_DISABLE</name>
7228              <description>Refer CM33_0_NID_DISABLE description.</description>
7229              <bitRange>[25:25]</bitRange>
7230              <access>read-write</access>
7231            </field>
7232            <field>
7233              <name>CM33_1_SPID_DISABLE</name>
7234              <description>Refer CM33_0_SPID_DISABLE description.</description>
7235              <bitRange>[26:26]</bitRange>
7236              <access>read-write</access>
7237            </field>
7238            <field>
7239              <name>CM33_1_SPNID_DISABLE</name>
7240              <description>Refer CM33_0_SPNID_DISABLE description.</description>
7241              <bitRange>[27:27]</bitRange>
7242              <access>read-write</access>
7243            </field>
7244          </fields>
7245        </register>
7246        <register>
7247          <name>PROTECTION</name>
7248          <description>Protection status</description>
7249          <addressOffset>0x2004</addressOffset>
7250          <size>32</size>
7251          <access>read-write</access>
7252          <resetValue>0x5B719A4F</resetValue>
7253          <resetMask>0xFFFFFFFF</resetMask>
7254          <fields>
7255            <field>
7256              <name>STATE</name>
7257              <description>Protection state:
7258'0x5B719A4F': UNKNOWN.
7259'0x5D48F714': VIRGIN.
7260'0x652372F7': NORMAL.
7261'0x8DF117A1': SECURE.
7262'0x2E94B3DD': DEAD.
7263
7264The following state transitions are allowed (and enforced by HW):
7265- UNKNOWN =&gt; VIRGIN/NORMAL/SECURE/DEAD
7266- NORMAL =&gt; DEAD
7267- SECURE =&gt; DEAD
7268An attempt to make a NOT allowed state transition will NOT affect this register field.</description>
7269              <bitRange>[31:0]</bitRange>
7270              <access>read-write</access>
7271            </field>
7272          </fields>
7273        </register>
7274        <register>
7275          <name>TRIM_ROM_CTL</name>
7276          <description>ROM trim control</description>
7277          <addressOffset>0x2100</addressOffset>
7278          <size>32</size>
7279          <access>read-write</access>
7280          <resetValue>0x0</resetValue>
7281          <resetMask>0xFFFFFFFF</resetMask>
7282          <fields>
7283            <field>
7284              <name>TRIM</name>
7285              <description>N/A</description>
7286              <bitRange>[31:0]</bitRange>
7287              <access>read-write</access>
7288            </field>
7289          </fields>
7290        </register>
7291        <register>
7292          <name>TRIM_RAM_CTL</name>
7293          <description>RAM trim control</description>
7294          <addressOffset>0x2110</addressOffset>
7295          <size>32</size>
7296          <access>read-write</access>
7297          <resetValue>0x0</resetValue>
7298          <resetMask>0xFFFFFFFF</resetMask>
7299          <fields>
7300            <field>
7301              <name>TRIM</name>
7302              <description>N/A</description>
7303              <bitRange>[31:0]</bitRange>
7304              <access>read-write</access>
7305            </field>
7306          </fields>
7307        </register>
7308      </registers>
7309    </peripheral>
7310    <peripheral>
7311      <name>MS_CTL_1_2</name>
7312      <description>Master control registers</description>
7313      <baseAddress>0x401C4000</baseAddress>
7314      <addressBlock>
7315        <offset>0</offset>
7316        <size>16384</size>
7317        <usage>registers</usage>
7318      </addressBlock>
7319      <registers>
7320        <cluster>
7321          <dim>6</dim>
7322          <dimIncrement>16</dimIncrement>
7323          <name>MS[%s]</name>
7324          <description>Master protection context control</description>
7325          <headerStructName>MS</headerStructName>
7326          <addressOffset>0x00000000</addressOffset>
7327          <register>
7328            <name>CTL</name>
7329            <description>Master 'x' protection context control</description>
7330            <addressOffset>0x0</addressOffset>
7331            <size>32</size>
7332            <access>read-write</access>
7333            <resetValue>0x3</resetValue>
7334            <resetMask>0xFFFF0003</resetMask>
7335            <fields>
7336              <field>
7337                <name>P</name>
7338                <description>Privileged setting ('0': user mode; '1': privileged mode).
7339
7340Notes:
7341This field is ONLY used for masters that do NOT provide their own user/privileged access control attribute.
7342The default/reset field value provides privileged mode access capabilities.</description>
7343                <bitRange>[0:0]</bitRange>
7344                <access>read-write</access>
7345              </field>
7346              <field>
7347                <name>NS</name>
7348                <description>Master security controller configuration.
73490: Bus master is secure. Master can send both secure and non-secure transfers. Accesses to secure addresses are not blocked and the security flag, HNONSEC, is set accordingly.
73501: Bus master is non-secure. Master can send only non-secure
7351transfers. Access to secure addresses, that is, outside the
7352Uncheck regions, are blocked.</description>
7353                <bitRange>[1:1]</bitRange>
7354                <access>read-write</access>
7355              </field>
7356              <field>
7357                <name>PC_MASK</name>
7358                <description>Protection context mask for protection contexts '15' down to '0'. Bit PC_MASK[i] indicates if the MS_PC_STRUCT[x].PC[3:0] protection context field can be set to the value 'i':
7359- PC_MASK[i] is '0': MS_PC_STRUCT[x].PC[3:0] can NOT be set to 'i'; and PC[3:0] is not changed.
7360- PC_MASK[i] is '1': MS_PC_STRUCT[x].PC[3:0] can be set to 'i'.
7361
7362Note: When CM33_0 CM33_PC_CTL.VALID[i] is '1' (the associated protection context handler is valid), write transfers to PC_MASK[i] always write '0', regardless of data written. This ensures that when valid protection context handlers are used to enter protection contexts 0, 1, 2 or 3 through HW (HW modifies MS_PC_STRUCT[x].PC[3:0] on entry of the handler), it is NOT possible for SW to enter those protection contexts.</description>
7363                <bitRange>[31:16]</bitRange>
7364                <access>read-write</access>
7365              </field>
7366            </fields>
7367          </register>
7368        </cluster>
7369        <cluster>
7370          <dim>6</dim>
7371          <dimIncrement>16</dimIncrement>
7372          <name>MS_PC[%s]</name>
7373          <description>Master protection context value</description>
7374          <headerStructName>MS_PC</headerStructName>
7375          <addressOffset>0x00001000</addressOffset>
7376          <register>
7377            <name>PC</name>
7378            <description>Master 'x' protection context value</description>
7379            <addressOffset>0x0</addressOffset>
7380            <size>32</size>
7381            <access>read-write</access>
7382            <resetValue>0x0</resetValue>
7383            <resetMask>0xF000F</resetMask>
7384            <fields>
7385              <field>
7386                <name>PC</name>
7387                <description>Active protection context (PC). Modifications to this field are constrained by the associated  MS_CTL_STRUCT[x].CTL.PC_MASK value. PC[3:0] can be set to 'i' only if the corresponding mask bit (PC_MASK[i]) is '1'.
7388
7389The CM33_0 PC register is special: the PC field is modifiable by BOTH HW and SW (for all other masters, the PC field is modifiable by SW ONLY. For CM33_0 PC field HW modifications, the following holds:
7390* On entry of a CM33_PC0/1/2/3_HANDLER exception/interrupt handler:
7391   IF (the new PC is the same as MS_PC_STRUCT[0].PC)
7392       PC is not affected; PC_SAVED is not affected.
7393   ELSE IF (CM33_PC_CTL.VALID[MS_PC_STRUCT[0].PC])
7394       An AHB5 bus error is generated for the exception handler fetch;
7395       PC is not affected; PC_SAVED is not affected.
7396   ELSE
7397       PC = 'new PC'; PC_SAVED = PC (push operation).
7398* On entry of any other exception/interrupt handler:
7399   PC = PC_SAVED; PC_SAVED is not affected (pop operation).
7400
7401Note that the CM33_PC0/1/2/3_HANDLER and CM33_PC_CTL registers are part of mxcm33 MMIO registers.
7402
7403Note: this field is NOT used by the DW controllers, DMA controllers as they inherit the protection context from master that configures the corresponding channel.</description>
7404                <bitRange>[3:0]</bitRange>
7405                <access>read-write</access>
7406              </field>
7407              <field>
7408                <name>PC_SAVED</name>
7409                <description>Saved protection context. Modifications to this field are constrained by the associated MS_CTL_STRUCT[x].CTL.PC_MASK.
7410
7411Note: this field is ONLY used by the CM33_0.</description>
7412                <bitRange>[19:16]</bitRange>
7413                <access>read-write</access>
7414              </field>
7415            </fields>
7416          </register>
7417          <register>
7418            <name>PC_READ_MIR</name>
7419            <description>Master 'x' protection context value read mirror register</description>
7420            <addressOffset>0x4</addressOffset>
7421            <size>32</size>
7422            <access>read-only</access>
7423            <resetValue>0x0</resetValue>
7424            <resetMask>0xF000F</resetMask>
7425            <fields>
7426              <field>
7427                <name>PC</name>
7428                <description>Read-only mirror of PC.PC</description>
7429                <bitRange>[3:0]</bitRange>
7430                <access>read-only</access>
7431              </field>
7432              <field>
7433                <name>PC_SAVED</name>
7434                <description>Read-only mirror of PC.PC_SAVED</description>
7435                <bitRange>[19:16]</bitRange>
7436                <access>read-only</access>
7437              </field>
7438            </fields>
7439          </register>
7440        </cluster>
7441        <register>
7442          <name>CODE_MS0_MSC_ACG_CTL</name>
7443          <description>CODE_MS0 master security Controller &amp; ACG configuration</description>
7444          <addressOffset>0x2000</addressOffset>
7445          <size>32</size>
7446          <access>read-write</access>
7447          <resetValue>0x2</resetValue>
7448          <resetMask>0x3</resetMask>
7449          <fields>
7450            <field>
7451              <name>CFG_GATE_RESP</name>
7452              <description>Response type when the ACG is blocking the incoming transfers:
74530: Waited transfer
74541: Error response</description>
7455              <bitRange>[0:0]</bitRange>
7456              <access>read-write</access>
7457            </field>
7458            <field>
7459              <name>SEC_RESP</name>
7460              <description>Reseponse type when transfers are not allowed by MSC.
74610: Read as zero, write ignore.
74621: Error response.</description>
7463              <bitRange>[1:1]</bitRange>
7464              <access>read-write</access>
7465            </field>
7466          </fields>
7467        </register>
7468        <register>
7469          <name>SYS_MS0_MSC_ACG_CTL</name>
7470          <description>SYS_MS0  master security Controller &amp; ACG configuration</description>
7471          <addressOffset>0x2010</addressOffset>
7472          <size>32</size>
7473          <access>read-write</access>
7474          <resetValue>0x2</resetValue>
7475          <resetMask>0x3</resetMask>
7476          <fields>
7477            <field>
7478              <name>CFG_GATE_RESP</name>
7479              <description>Response type when the ACG is blocking the incoming transfers:
74800: Waited transfer
74811: Error response</description>
7482              <bitRange>[0:0]</bitRange>
7483              <access>read-write</access>
7484            </field>
7485            <field>
7486              <name>SEC_RESP</name>
7487              <description>Reseponse type when transfers are not allowed by MSC.
74880: Read as zero, write ignore.
74891: Error response.</description>
7490              <bitRange>[1:1]</bitRange>
7491              <access>read-write</access>
7492            </field>
7493          </fields>
7494        </register>
7495        <register>
7496          <name>SYS_MS1_MSC_ACG_CTL</name>
7497          <description>SYS_MS1  master security Controller &amp; ACG configuration</description>
7498          <addressOffset>0x2014</addressOffset>
7499          <size>32</size>
7500          <access>read-write</access>
7501          <resetValue>0x2</resetValue>
7502          <resetMask>0x3</resetMask>
7503          <fields>
7504            <field>
7505              <name>CFG_GATE_RESP</name>
7506              <description>Response type when the ACG is blocking the incoming transfers:
75070: Waited transfer
75081: Error response</description>
7509              <bitRange>[0:0]</bitRange>
7510              <access>read-write</access>
7511            </field>
7512            <field>
7513              <name>SEC_RESP</name>
7514              <description>Reseponse type when transfers are not allowed by MSC.
75150: Read as zero, write ignore.
75161: Error response.</description>
7517              <bitRange>[1:1]</bitRange>
7518              <access>read-write</access>
7519            </field>
7520          </fields>
7521        </register>
7522        <register>
7523          <name>EXP_MS_MSC_ACG_CTL</name>
7524          <description>EXP_MS  master security Controller &amp; ACG configuration</description>
7525          <addressOffset>0x2020</addressOffset>
7526          <size>32</size>
7527          <access>read-write</access>
7528          <resetValue>0x2</resetValue>
7529          <resetMask>0x3</resetMask>
7530          <fields>
7531            <field>
7532              <name>CFG_GATE_RESP</name>
7533              <description>Response type when the ACG is blocking the incoming transfers:
75340: Waited transfer
75351: Error response</description>
7536              <bitRange>[0:0]</bitRange>
7537              <access>read-write</access>
7538            </field>
7539            <field>
7540              <name>SEC_RESP</name>
7541              <description>Reseponse type when transfers are not allowed by MSC.
75420: Read as zero, write ignore.
75431: Error response.</description>
7544              <bitRange>[1:1]</bitRange>
7545              <access>read-write</access>
7546            </field>
7547          </fields>
7548        </register>
7549        <register>
7550          <name>DMAC0_MSC_ACG_CTL</name>
7551          <description>DMAC-0  master security Controller &amp; ACG configuration</description>
7552          <addressOffset>0x2030</addressOffset>
7553          <size>32</size>
7554          <access>read-write</access>
7555          <resetValue>0x2</resetValue>
7556          <resetMask>0x3</resetMask>
7557          <fields>
7558            <field>
7559              <name>CFG_GATE_RESP</name>
7560              <description>Response type when the ACG is blocking the incoming transfers:
75610: Waited transfer
75621: Error response</description>
7563              <bitRange>[0:0]</bitRange>
7564              <access>read-write</access>
7565            </field>
7566            <field>
7567              <name>SEC_RESP</name>
7568              <description>Reseponse type when transfers are not allowed by MSC.
75690: Read as zero, write ignore.
75701: Error response.</description>
7571              <bitRange>[1:1]</bitRange>
7572              <access>read-write</access>
7573            </field>
7574          </fields>
7575        </register>
7576        <register>
7577          <name>DMAC1_MSC_ACG_CTL</name>
7578          <description>DMAC-1  master security Controller &amp; ACG configuration</description>
7579          <addressOffset>0x2040</addressOffset>
7580          <size>32</size>
7581          <access>read-write</access>
7582          <resetValue>0x2</resetValue>
7583          <resetMask>0x3</resetMask>
7584          <fields>
7585            <field>
7586              <name>CFG_GATE_RESP</name>
7587              <description>Response type when the ACG is blocking the incoming transfers:
75880: Waited transfer
75891: Error response</description>
7590              <bitRange>[0:0]</bitRange>
7591              <access>read-write</access>
7592            </field>
7593            <field>
7594              <name>SEC_RESP</name>
7595              <description>Reseponse type when transfers are not allowed by MSC.
75960: Read as zero, write ignore.
75971: Error response.</description>
7598              <bitRange>[1:1]</bitRange>
7599              <access>read-write</access>
7600            </field>
7601          </fields>
7602        </register>
7603      </registers>
7604    </peripheral>
7605    <peripheral>
7606      <name>CPUSS_SL_CTL</name>
7607      <description>SYSCPUSS Internal slave control registers</description>
7608      <baseAddress>0x401C8000</baseAddress>
7609      <addressBlock>
7610        <offset>0</offset>
7611        <size>16</size>
7612        <usage>registers</usage>
7613      </addressBlock>
7614      <registers>
7615        <register>
7616          <name>SL_CTL</name>
7617          <description>Slave control (Clock enables)</description>
7618          <addressOffset>0x0</addressOffset>
7619          <size>32</size>
7620          <access>read-write</access>
7621          <resetValue>0x7FB</resetValue>
7622          <resetMask>0x7FB</resetMask>
7623          <fields>
7624            <field>
7625              <name>PROMC_ENABLED</name>
7626              <description>Slave enable controls. Each bit indicates whether the respective slave is enabled or not.
76270: Disabled
76281: Enabled
7629If the slave is disabled, its clock is gated off (constant '0').
7630Any access (MMIO AHB access or ROM/System SRAM memory access) to slave  when disabled result in AHB error response.</description>
7631              <bitRange>[0:0]</bitRange>
7632              <access>read-write</access>
7633            </field>
7634            <field>
7635              <name>FLASHC_ENABLED</name>
7636              <description>N/A</description>
7637              <bitRange>[1:1]</bitRange>
7638              <access>read-write</access>
7639            </field>
7640            <field>
7641              <name>RAMC0_ENABLED</name>
7642              <description>N/A</description>
7643              <bitRange>[3:3]</bitRange>
7644              <access>read-write</access>
7645            </field>
7646            <field>
7647              <name>RAMC1_ENABLED</name>
7648              <description>N/A</description>
7649              <bitRange>[4:4]</bitRange>
7650              <access>read-write</access>
7651            </field>
7652            <field>
7653              <name>RAMC2_ENABLED</name>
7654              <description>N/A</description>
7655              <bitRange>[5:5]</bitRange>
7656              <access>read-write</access>
7657            </field>
7658            <field>
7659              <name>DW0_ENABLED</name>
7660              <description>N/A</description>
7661              <bitRange>[6:6]</bitRange>
7662              <access>read-write</access>
7663            </field>
7664            <field>
7665              <name>DW1_ENABLED</name>
7666              <description>N/A</description>
7667              <bitRange>[7:7]</bitRange>
7668              <access>read-write</access>
7669            </field>
7670            <field>
7671              <name>DMAC0_ENABLED</name>
7672              <description>N/A</description>
7673              <bitRange>[8:8]</bitRange>
7674              <access>read-write</access>
7675            </field>
7676            <field>
7677              <name>DMAC1_ENABLED</name>
7678              <description>N/A</description>
7679              <bitRange>[9:9]</bitRange>
7680              <access>read-write</access>
7681            </field>
7682            <field>
7683              <name>IPC_ENABLED</name>
7684              <description>N/A</description>
7685              <bitRange>[10:10]</bitRange>
7686              <access>read-write</access>
7687            </field>
7688          </fields>
7689        </register>
7690        <register>
7691          <name>SL_CTL2</name>
7692          <description>Slave control2 (Reset enables)</description>
7693          <addressOffset>0x4</addressOffset>
7694          <size>32</size>
7695          <access>read-write</access>
7696          <resetValue>0x0</resetValue>
7697          <resetMask>0x7FB</resetMask>
7698          <fields>
7699            <field>
7700              <name>PROMC_RST</name>
7701              <description>Slave reset controls. Each bit indicates whether the respective slave reset is enabled or not.
77020: Disabled
77031: Enabled
7704If the slave is under reset enabled state, its clock is gated off (constant '0') and its resets are in activated state (rst_n = 0)
7705Any access (MMIO AHB access or ROM/System SRAM memory access) to slave  when disabled result in AHB error response.</description>
7706              <bitRange>[0:0]</bitRange>
7707              <access>read-write</access>
7708            </field>
7709            <field>
7710              <name>FLASHC_RST</name>
7711              <description>N/A</description>
7712              <bitRange>[1:1]</bitRange>
7713              <access>read-write</access>
7714            </field>
7715            <field>
7716              <name>RAMC0_RST</name>
7717              <description>N/A</description>
7718              <bitRange>[3:3]</bitRange>
7719              <access>read-write</access>
7720            </field>
7721            <field>
7722              <name>RAMC1_RST</name>
7723              <description>N/A</description>
7724              <bitRange>[4:4]</bitRange>
7725              <access>read-write</access>
7726            </field>
7727            <field>
7728              <name>RAMC2_RST</name>
7729              <description>N/A</description>
7730              <bitRange>[5:5]</bitRange>
7731              <access>read-write</access>
7732            </field>
7733            <field>
7734              <name>DW0_RST</name>
7735              <description>N/A</description>
7736              <bitRange>[6:6]</bitRange>
7737              <access>read-write</access>
7738            </field>
7739            <field>
7740              <name>DW1_RST</name>
7741              <description>N/A</description>
7742              <bitRange>[7:7]</bitRange>
7743              <access>read-write</access>
7744            </field>
7745            <field>
7746              <name>DMAC0_RST</name>
7747              <description>N/A</description>
7748              <bitRange>[8:8]</bitRange>
7749              <access>read-write</access>
7750            </field>
7751            <field>
7752              <name>DMAC1_RST</name>
7753              <description>N/A</description>
7754              <bitRange>[9:9]</bitRange>
7755              <access>read-write</access>
7756            </field>
7757            <field>
7758              <name>IPC_RST</name>
7759              <description>N/A</description>
7760              <bitRange>[10:10]</bitRange>
7761              <access>read-write</access>
7762            </field>
7763          </fields>
7764        </register>
7765      </registers>
7766    </peripheral>
7767    <peripheral>
7768      <name>IPC</name>
7769      <description>IPC</description>
7770      <baseAddress>0x401D0000</baseAddress>
7771      <addressBlock>
7772        <offset>0</offset>
7773        <size>65536</size>
7774        <usage>registers</usage>
7775      </addressBlock>
7776      <registers>
7777        <cluster>
7778          <dim>4</dim>
7779          <dimIncrement>32</dimIncrement>
7780          <name>STRUCT[%s]</name>
7781          <description>IPC structure</description>
7782          <addressOffset>0x00000000</addressOffset>
7783          <register>
7784            <name>ACQUIRE</name>
7785            <description>IPC acquire</description>
7786            <addressOffset>0x0</addressOffset>
7787            <size>32</size>
7788            <access>read-only</access>
7789            <resetValue>0x0</resetValue>
7790            <resetMask>0x80000000</resetMask>
7791            <fields>
7792              <field>
7793                <name>P</name>
7794                <description>User/privileged access control:
7795'0': user mode.
7796'1': privileged mode.
7797
7798This field is set with the user/privileged access control of the access that successfully acquired the lock.</description>
7799                <bitRange>[0:0]</bitRange>
7800                <access>read-only</access>
7801              </field>
7802              <field>
7803                <name>NS</name>
7804                <description>Secure/non-secure access control:
7805'0': secure.
7806'1': non-secure.
7807
7808This field is set with the secure/non-secure access control of the access that successfully acquired the lock.</description>
7809                <bitRange>[1:1]</bitRange>
7810                <access>read-only</access>
7811              </field>
7812              <field>
7813                <name>PC</name>
7814                <description>This field specifies the protection context that successfully acquired the lock.</description>
7815                <bitRange>[7:4]</bitRange>
7816                <access>read-only</access>
7817              </field>
7818              <field>
7819                <name>MS</name>
7820                <description>This field specifies the bus master identifier (HMASTER[MASTER_WIDTH-1:0]) that successfully acquired the lock.</description>
7821                <bitRange>[15:8]</bitRange>
7822                <access>read-only</access>
7823              </field>
7824              <field>
7825                <name>SUCCESS</name>
7826                <description>Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED):
7827'0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access.
7828'1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access.
7829
7830Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value).</description>
7831                <bitRange>[31:31]</bitRange>
7832                <access>read-only</access>
7833              </field>
7834            </fields>
7835          </register>
7836          <register>
7837            <name>RELEASE</name>
7838            <description>IPC release</description>
7839            <addressOffset>0x4</addressOffset>
7840            <size>32</size>
7841            <access>write-only</access>
7842            <resetValue>0x0</resetValue>
7843            <resetMask>0xFFFF</resetMask>
7844            <fields>
7845              <field>
7846                <name>INTR_RELEASE</name>
7847                <description>Writing this field releases a lock and allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'.
7848
7849SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field.</description>
7850                <bitRange>[15:0]</bitRange>
7851                <access>write-only</access>
7852              </field>
7853            </fields>
7854          </register>
7855          <register>
7856            <name>NOTIFY</name>
7857            <description>IPC notification</description>
7858            <addressOffset>0x8</addressOffset>
7859            <size>32</size>
7860            <access>write-only</access>
7861            <resetValue>0x0</resetValue>
7862            <resetMask>0xFFFF</resetMask>
7863            <fields>
7864              <field>
7865                <name>INTR_NOTIFY</name>
7866                <description>This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'.
7867
7868SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field.</description>
7869                <bitRange>[15:0]</bitRange>
7870                <access>write-only</access>
7871              </field>
7872            </fields>
7873          </register>
7874          <register>
7875            <name>DATA0</name>
7876            <description>IPC data 0</description>
7877            <addressOffset>0xC</addressOffset>
7878            <size>32</size>
7879            <access>read-write</access>
7880            <resetValue>0x0</resetValue>
7881            <resetMask>0x0</resetMask>
7882            <fields>
7883              <field>
7884                <name>DATA</name>
7885                <description>This field holds a 32-bit data element that is associated with the IPC structure.</description>
7886                <bitRange>[31:0]</bitRange>
7887                <access>read-write</access>
7888              </field>
7889            </fields>
7890          </register>
7891          <register>
7892            <name>DATA1</name>
7893            <description>IPC data 1</description>
7894            <addressOffset>0x10</addressOffset>
7895            <size>32</size>
7896            <access>read-write</access>
7897            <resetValue>0x0</resetValue>
7898            <resetMask>0x0</resetMask>
7899            <fields>
7900              <field>
7901                <name>DATA</name>
7902                <description>This field holds a 32-bit data element that is associated with the IPC structure.</description>
7903                <bitRange>[31:0]</bitRange>
7904                <access>read-write</access>
7905              </field>
7906            </fields>
7907          </register>
7908          <register>
7909            <name>LOCK_STATUS</name>
7910            <description>IPC lock status</description>
7911            <addressOffset>0x1C</addressOffset>
7912            <size>32</size>
7913            <access>read-only</access>
7914            <resetValue>0x0</resetValue>
7915            <resetMask>0x80000000</resetMask>
7916            <fields>
7917              <field>
7918                <name>P</name>
7919                <description>This field specifies the user/privileged access control:
7920'0': user mode.
7921'1': privileged mode.</description>
7922                <bitRange>[0:0]</bitRange>
7923                <access>read-only</access>
7924              </field>
7925              <field>
7926                <name>NS</name>
7927                <description>This field specifies the secure/non-secure access control:
7928'0': secure.
7929'1': non-secure.</description>
7930                <bitRange>[1:1]</bitRange>
7931                <access>read-only</access>
7932              </field>
7933              <field>
7934                <name>PC</name>
7935                <description>This field specifies the protection context that successfully acquired the lock.</description>
7936                <bitRange>[7:4]</bitRange>
7937                <access>read-only</access>
7938              </field>
7939              <field>
7940                <name>MS</name>
7941                <description>This field specifies the bus master identifier (HMASTER[MASTER_WIDTH-1:0]) that successfully acquired the lock.</description>
7942                <bitRange>[15:8]</bitRange>
7943                <access>read-only</access>
7944              </field>
7945              <field>
7946                <name>ACQUIRED</name>
7947                <description>Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1'). If zero, P, NS, PC, and MS are not valid.</description>
7948                <bitRange>[31:31]</bitRange>
7949                <access>read-only</access>
7950              </field>
7951            </fields>
7952          </register>
7953        </cluster>
7954        <cluster>
7955          <dim>2</dim>
7956          <dimIncrement>32</dimIncrement>
7957          <name>INTR_STRUCT[%s]</name>
7958          <description>IPC interrupt structure</description>
7959          <addressOffset>0x00001000</addressOffset>
7960          <register>
7961            <name>INTR</name>
7962            <description>Interrupt</description>
7963            <addressOffset>0x0</addressOffset>
7964            <size>32</size>
7965            <access>read-write</access>
7966            <resetValue>0x0</resetValue>
7967            <resetMask>0xFFFFFFFF</resetMask>
7968            <fields>
7969              <field>
7970                <name>RELEASE</name>
7971                <description>These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.</description>
7972                <bitRange>[15:0]</bitRange>
7973                <access>read-write</access>
7974              </field>
7975              <field>
7976                <name>NOTIFY</name>
7977                <description>These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.</description>
7978                <bitRange>[31:16]</bitRange>
7979                <access>read-write</access>
7980              </field>
7981            </fields>
7982          </register>
7983          <register>
7984            <name>INTR_SET</name>
7985            <description>Interrupt set</description>
7986            <addressOffset>0x4</addressOffset>
7987            <size>32</size>
7988            <access>read-write</access>
7989            <resetValue>0x0</resetValue>
7990            <resetMask>0xFFFFFFFF</resetMask>
7991            <fields>
7992              <field>
7993                <name>RELEASE</name>
7994                <description>SW writes a '1' to this field to set the corresponding field in the INTR register.</description>
7995                <bitRange>[15:0]</bitRange>
7996                <access>read-write</access>
7997              </field>
7998              <field>
7999                <name>NOTIFY</name>
8000                <description>SW writes a '1' to this field to set the corresponding field in the INTR register.</description>
8001                <bitRange>[31:16]</bitRange>
8002                <access>read-write</access>
8003              </field>
8004            </fields>
8005          </register>
8006          <register>
8007            <name>INTR_MASK</name>
8008            <description>Interrupt mask</description>
8009            <addressOffset>0x8</addressOffset>
8010            <size>32</size>
8011            <access>read-write</access>
8012            <resetValue>0x0</resetValue>
8013            <resetMask>0xFFFFFFFF</resetMask>
8014            <fields>
8015              <field>
8016                <name>RELEASE</name>
8017                <description>Mask bit for corresponding field in the INTR register.</description>
8018                <bitRange>[15:0]</bitRange>
8019                <access>read-write</access>
8020              </field>
8021              <field>
8022                <name>NOTIFY</name>
8023                <description>Mask bit for corresponding field in the INTR register.</description>
8024                <bitRange>[31:16]</bitRange>
8025                <access>read-write</access>
8026              </field>
8027            </fields>
8028          </register>
8029          <register>
8030            <name>INTR_MASKED</name>
8031            <description>Interrupt masked</description>
8032            <addressOffset>0xC</addressOffset>
8033            <size>32</size>
8034            <access>read-only</access>
8035            <resetValue>0x0</resetValue>
8036            <resetMask>0xFFFFFFFF</resetMask>
8037            <fields>
8038              <field>
8039                <name>RELEASE</name>
8040                <description>Logical and of corresponding request and mask bits.</description>
8041                <bitRange>[15:0]</bitRange>
8042                <access>read-only</access>
8043              </field>
8044              <field>
8045                <name>NOTIFY</name>
8046                <description>Logical and of corresponding INTR and INTR_MASK fields.</description>
8047                <bitRange>[31:16]</bitRange>
8048                <access>read-only</access>
8049              </field>
8050            </fields>
8051          </register>
8052        </cluster>
8053      </registers>
8054    </peripheral>
8055    <peripheral>
8056      <name>SRSS</name>
8057      <description>SRSS Core Registers</description>
8058      <baseAddress>0x40200000</baseAddress>
8059      <addressBlock>
8060        <offset>0</offset>
8061        <size>65536</size>
8062        <usage>registers</usage>
8063      </addressBlock>
8064      <registers>
8065        <register>
8066          <name>PWR_LVD_STATUS</name>
8067          <description>High Voltage / Low Voltage Detector (HVLVD) Status Register</description>
8068          <addressOffset>0x40</addressOffset>
8069          <size>32</size>
8070          <access>read-only</access>
8071          <resetValue>0x0</resetValue>
8072          <resetMask>0x1</resetMask>
8073          <fields>
8074            <field>
8075              <name>HVLVD1_OK</name>
8076              <description>HVLVD1 output.
80770: below voltage threshold
80781: above voltage threshold</description>
8079              <bitRange>[0:0]</bitRange>
8080              <access>read-only</access>
8081            </field>
8082          </fields>
8083        </register>
8084        <register>
8085          <name>PWR_LVD_STATUS2</name>
8086          <description>High Voltage / Low Voltage Detector (HVLVD) Status Register #2</description>
8087          <addressOffset>0x44</addressOffset>
8088          <size>32</size>
8089          <access>read-only</access>
8090          <resetValue>0x0</resetValue>
8091          <resetMask>0x1</resetMask>
8092          <fields>
8093            <field>
8094              <name>HVLVD2_OUT</name>
8095              <description>HVLVD2 output.
80960: below voltage threshold
80971: above voltage threshold</description>
8098              <bitRange>[0:0]</bitRange>
8099              <access>read-only</access>
8100            </field>
8101          </fields>
8102        </register>
8103        <register>
8104          <dim>16</dim>
8105          <dimIncrement>4</dimIncrement>
8106          <name>CLK_DSI_SELECT[%s]</name>
8107          <description>Clock DSI Select Register</description>
8108          <addressOffset>0x100</addressOffset>
8109          <size>32</size>
8110          <access>read-write</access>
8111          <resetValue>0x0</resetValue>
8112          <resetMask>0x1F</resetMask>
8113          <fields>
8114            <field>
8115              <name>DSI_MUX</name>
8116              <description>Selects a DSI source or low frequency clock for use in a clock path.  The output of this mux can be selected for clock PATH&lt;i&gt; using CLK_SELECT_PATH register.  Using the output of this mux as HFCLK source will result in undefined behavior.  It can be used to clocks to DSI or as reference inputs for the FLL/PLL, subject to the frequency limits of those circuits.  This mux is not glitch free, so do not change the selection while it is an actively selected clock.</description>
8117              <bitRange>[4:0]</bitRange>
8118              <access>read-write</access>
8119              <enumeratedValues>
8120                <enumeratedValue>
8121                  <name>DSI_OUT0</name>
8122                  <description>DSI0 - dsi_out[0]</description>
8123                  <value>0</value>
8124                </enumeratedValue>
8125                <enumeratedValue>
8126                  <name>DSI_OUT1</name>
8127                  <description>DSI1 - dsi_out[1]</description>
8128                  <value>1</value>
8129                </enumeratedValue>
8130                <enumeratedValue>
8131                  <name>DSI_OUT2</name>
8132                  <description>DSI2 - dsi_out[2]</description>
8133                  <value>2</value>
8134                </enumeratedValue>
8135                <enumeratedValue>
8136                  <name>DSI_OUT3</name>
8137                  <description>DSI3 - dsi_out[3]</description>
8138                  <value>3</value>
8139                </enumeratedValue>
8140                <enumeratedValue>
8141                  <name>DSI_OUT4</name>
8142                  <description>DSI4 - dsi_out[4]</description>
8143                  <value>4</value>
8144                </enumeratedValue>
8145                <enumeratedValue>
8146                  <name>DSI_OUT5</name>
8147                  <description>DSI5 - dsi_out[5]</description>
8148                  <value>5</value>
8149                </enumeratedValue>
8150                <enumeratedValue>
8151                  <name>DSI_OUT6</name>
8152                  <description>DSI6 - dsi_out[6]</description>
8153                  <value>6</value>
8154                </enumeratedValue>
8155                <enumeratedValue>
8156                  <name>DSI_OUT7</name>
8157                  <description>DSI7 - dsi_out[7]</description>
8158                  <value>7</value>
8159                </enumeratedValue>
8160                <enumeratedValue>
8161                  <name>DSI_OUT8</name>
8162                  <description>DSI8 - dsi_out[8]</description>
8163                  <value>8</value>
8164                </enumeratedValue>
8165                <enumeratedValue>
8166                  <name>DSI_OUT9</name>
8167                  <description>DSI9 - dsi_out[9]</description>
8168                  <value>9</value>
8169                </enumeratedValue>
8170                <enumeratedValue>
8171                  <name>DSI_OUT10</name>
8172                  <description>DSI10 - dsi_out[10]</description>
8173                  <value>10</value>
8174                </enumeratedValue>
8175                <enumeratedValue>
8176                  <name>DSI_OUT11</name>
8177                  <description>DSI11 - dsi_out[11]</description>
8178                  <value>11</value>
8179                </enumeratedValue>
8180                <enumeratedValue>
8181                  <name>DSI_OUT12</name>
8182                  <description>DSI12 - dsi_out[12]</description>
8183                  <value>12</value>
8184                </enumeratedValue>
8185                <enumeratedValue>
8186                  <name>DSI_OUT13</name>
8187                  <description>DSI13 - dsi_out[13]</description>
8188                  <value>13</value>
8189                </enumeratedValue>
8190                <enumeratedValue>
8191                  <name>DSI_OUT14</name>
8192                  <description>DSI14 - dsi_out[14]</description>
8193                  <value>14</value>
8194                </enumeratedValue>
8195                <enumeratedValue>
8196                  <name>DSI_OUT15</name>
8197                  <description>DSI15 - dsi_out[15]</description>
8198                  <value>15</value>
8199                </enumeratedValue>
8200                <enumeratedValue>
8201                  <name>ILO</name>
8202                  <description>ILO - Internal Low-speed Oscillator #0</description>
8203                  <value>16</value>
8204                </enumeratedValue>
8205                <enumeratedValue>
8206                  <name>WCO</name>
8207                  <description>WCO - Watch-Crystal Oscillator</description>
8208                  <value>17</value>
8209                </enumeratedValue>
8210                <enumeratedValue>
8211                  <name>ALTLF</name>
8212                  <description>ALTLF - Alternate Low-Frequency Clock</description>
8213                  <value>18</value>
8214                </enumeratedValue>
8215                <enumeratedValue>
8216                  <name>PILO</name>
8217                  <description>PILO - Precision Internal Low-speed Oscillator</description>
8218                  <value>19</value>
8219                </enumeratedValue>
8220                <enumeratedValue>
8221                  <name>ILO1</name>
8222                  <description>ILO1 - Internal Low-speed Oscillator #1, if present.</description>
8223                  <value>20</value>
8224                </enumeratedValue>
8225              </enumeratedValues>
8226            </field>
8227          </fields>
8228        </register>
8229        <register>
8230          <name>CLK_OUTPUT_FAST</name>
8231          <description>Fast Clock Output Select Register</description>
8232          <addressOffset>0x140</addressOffset>
8233          <size>32</size>
8234          <access>read-write</access>
8235          <resetValue>0x0</resetValue>
8236          <resetMask>0xFFF0FFF</resetMask>
8237          <fields>
8238            <field>
8239              <name>FAST_SEL0</name>
8240              <description>Select signal for fast clock output #0</description>
8241              <bitRange>[3:0]</bitRange>
8242              <access>read-write</access>
8243              <enumeratedValues>
8244                <enumeratedValue>
8245                  <name>NC</name>
8246                  <description>Disabled - output is 0.  For power savings, clocks are blocked before entering any muxes, including PATH_SEL0 and HFCLK_SEL0.</description>
8247                  <value>0</value>
8248                </enumeratedValue>
8249                <enumeratedValue>
8250                  <name>ECO</name>
8251                  <description>External Crystal Oscillator (ECO)</description>
8252                  <value>1</value>
8253                </enumeratedValue>
8254                <enumeratedValue>
8255                  <name>EXTCLK</name>
8256                  <description>External clock input (EXTCLK)</description>
8257                  <value>2</value>
8258                </enumeratedValue>
8259                <enumeratedValue>
8260                  <name>ALTHF</name>
8261                  <description>Alternate High-Frequency (ALTHF) clock input to SRSS</description>
8262                  <value>3</value>
8263                </enumeratedValue>
8264                <enumeratedValue>
8265                  <name>TIMERCLK</name>
8266                  <description>Timer clock.  It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse.</description>
8267                  <value>4</value>
8268                </enumeratedValue>
8269                <enumeratedValue>
8270                  <name>PATH_SEL0</name>
8271                  <description>Selects the clock path chosen by PATH_SEL0 field</description>
8272                  <value>5</value>
8273                </enumeratedValue>
8274                <enumeratedValue>
8275                  <name>HFCLK_SEL0</name>
8276                  <description>Selects the output of the HFCLK_SEL0 mux</description>
8277                  <value>6</value>
8278                </enumeratedValue>
8279                <enumeratedValue>
8280                  <name>SLOW_SEL0</name>
8281                  <description>Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL0</description>
8282                  <value>7</value>
8283                </enumeratedValue>
8284                <enumeratedValue>
8285                  <name>IHO</name>
8286                  <description>Internal High-speed Oscillator (IHO).</description>
8287                  <value>8</value>
8288                </enumeratedValue>
8289                <enumeratedValue>
8290                  <name>PWR</name>
8291                  <description>clk_pwr: used for PPU and related components</description>
8292                  <value>9</value>
8293                </enumeratedValue>
8294              </enumeratedValues>
8295            </field>
8296            <field>
8297              <name>PATH_SEL0</name>
8298              <description>Selects a clock path to use in fast clock output #0 logic.</description>
8299              <bitRange>[7:4]</bitRange>
8300              <access>read-write</access>
8301            </field>
8302            <field>
8303              <name>HFCLK_SEL0</name>
8304              <description>Selects a HFCLK tree for use in fast clock output #0</description>
8305              <bitRange>[11:8]</bitRange>
8306              <access>read-write</access>
8307            </field>
8308            <field>
8309              <name>FAST_SEL1</name>
8310              <description>Select signal for fast clock output #1</description>
8311              <bitRange>[19:16]</bitRange>
8312              <access>read-write</access>
8313              <enumeratedValues>
8314                <enumeratedValue>
8315                  <name>NC</name>
8316                  <description>Disabled - output is 0.  For power savings, clocks are blocked before entering any muxes, including PATH_SEL1 and HFCLK_SEL1.</description>
8317                  <value>0</value>
8318                </enumeratedValue>
8319                <enumeratedValue>
8320                  <name>ECO</name>
8321                  <description>External Crystal Oscillator (ECO)</description>
8322                  <value>1</value>
8323                </enumeratedValue>
8324                <enumeratedValue>
8325                  <name>EXTCLK</name>
8326                  <description>External clock input (EXTCLK)</description>
8327                  <value>2</value>
8328                </enumeratedValue>
8329                <enumeratedValue>
8330                  <name>ALTHF</name>
8331                  <description>Alternate High-Frequency (ALTHF) clock input to SRSS</description>
8332                  <value>3</value>
8333                </enumeratedValue>
8334                <enumeratedValue>
8335                  <name>TIMERCLK</name>
8336                  <description>Timer clock.  It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse.</description>
8337                  <value>4</value>
8338                </enumeratedValue>
8339                <enumeratedValue>
8340                  <name>PATH_SEL1</name>
8341                  <description>Selects the clock path chosen by PATH_SEL1 field</description>
8342                  <value>5</value>
8343                </enumeratedValue>
8344                <enumeratedValue>
8345                  <name>HFCLK_SEL1</name>
8346                  <description>Selects the output of the HFCLK_SEL1 mux</description>
8347                  <value>6</value>
8348                </enumeratedValue>
8349                <enumeratedValue>
8350                  <name>SLOW_SEL1</name>
8351                  <description>Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL1</description>
8352                  <value>7</value>
8353                </enumeratedValue>
8354                <enumeratedValue>
8355                  <name>IHO</name>
8356                  <description>Internal High-speed Oscillator (IHO).</description>
8357                  <value>8</value>
8358                </enumeratedValue>
8359                <enumeratedValue>
8360                  <name>PWR</name>
8361                  <description>clk_pwr: used for PPU and related components</description>
8362                  <value>9</value>
8363                </enumeratedValue>
8364              </enumeratedValues>
8365            </field>
8366            <field>
8367              <name>PATH_SEL1</name>
8368              <description>Selects a clock path to use in fast clock output #1 logic.</description>
8369              <bitRange>[23:20]</bitRange>
8370              <access>read-write</access>
8371            </field>
8372            <field>
8373              <name>HFCLK_SEL1</name>
8374              <description>Selects a HFCLK tree for use in fast clock output #1 logic</description>
8375              <bitRange>[27:24]</bitRange>
8376              <access>read-write</access>
8377            </field>
8378          </fields>
8379        </register>
8380        <register>
8381          <name>CLK_OUTPUT_SLOW</name>
8382          <description>Slow Clock Output Select Register</description>
8383          <addressOffset>0x144</addressOffset>
8384          <size>32</size>
8385          <access>read-write</access>
8386          <resetValue>0x0</resetValue>
8387          <resetMask>0xFF</resetMask>
8388          <fields>
8389            <field>
8390              <name>SLOW_SEL0</name>
8391              <description>Select signal for slow clock output #0</description>
8392              <bitRange>[3:0]</bitRange>
8393              <access>read-write</access>
8394              <enumeratedValues>
8395                <enumeratedValue>
8396                  <name>NC</name>
8397                  <description>Disabled - output is 0.  For power savings, clocks are blocked before entering any muxes.</description>
8398                  <value>0</value>
8399                </enumeratedValue>
8400                <enumeratedValue>
8401                  <name>ILO</name>
8402                  <description>Internal Low Speed Oscillator (ILO)</description>
8403                  <value>1</value>
8404                </enumeratedValue>
8405                <enumeratedValue>
8406                  <name>WCO</name>
8407                  <description>Watch-Crystal Oscillator (WCO)</description>
8408                  <value>2</value>
8409                </enumeratedValue>
8410                <enumeratedValue>
8411                  <name>BAK</name>
8412                  <description>Root of the Backup domain clock tree (BAK)</description>
8413                  <value>3</value>
8414                </enumeratedValue>
8415                <enumeratedValue>
8416                  <name>ALTLF</name>
8417                  <description>Alternate low-frequency clock input to SRSS (ALTLF)</description>
8418                  <value>4</value>
8419                </enumeratedValue>
8420                <enumeratedValue>
8421                  <name>LFCLK</name>
8422                  <description>Root of the low-speed clock tree (LFCLK)</description>
8423                  <value>5</value>
8424                </enumeratedValue>
8425                <enumeratedValue>
8426                  <name>IMO</name>
8427                  <description>Internal Main Oscillator (IMO).  This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.</description>
8428                  <value>6</value>
8429                </enumeratedValue>
8430                <enumeratedValue>
8431                  <name>SLPCTRL</name>
8432                  <description>Sleep Controller clock (SLPCTRL).  This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.</description>
8433                  <value>7</value>
8434                </enumeratedValue>
8435                <enumeratedValue>
8436                  <name>PILO</name>
8437                  <description>Precision Internal Low Speed Oscillator (PILO)</description>
8438                  <value>8</value>
8439                </enumeratedValue>
8440                <enumeratedValue>
8441                  <name>ILO1</name>
8442                  <description>Internal Low Speed Oscillator (ILO1), if present on the product.</description>
8443                  <value>9</value>
8444                </enumeratedValue>
8445                <enumeratedValue>
8446                  <name>ECO_PRESCALER</name>
8447                  <description>ECO Prescaler (ECO_PRESCALER)</description>
8448                  <value>10</value>
8449                </enumeratedValue>
8450                <enumeratedValue>
8451                  <name>LPECO</name>
8452                  <description>LPECO</description>
8453                  <value>11</value>
8454                </enumeratedValue>
8455                <enumeratedValue>
8456                  <name>LPECO_PRESCALER</name>
8457                  <description>LPECO Prescaler (LPECO_PRESCALER)</description>
8458                  <value>12</value>
8459                </enumeratedValue>
8460                <enumeratedValue>
8461                  <name>MFO</name>
8462                  <description>Medium Frequency Oscillator (MFO)</description>
8463                  <value>13</value>
8464                </enumeratedValue>
8465              </enumeratedValues>
8466            </field>
8467            <field>
8468              <name>SLOW_SEL1</name>
8469              <description>Select signal for slow clock output #1</description>
8470              <bitRange>[7:4]</bitRange>
8471              <access>read-write</access>
8472              <enumeratedValues>
8473                <enumeratedValue>
8474                  <name>NC</name>
8475                  <description>Disabled - output is 0.  For power savings, clocks are blocked before entering any muxes.</description>
8476                  <value>0</value>
8477                </enumeratedValue>
8478                <enumeratedValue>
8479                  <name>ILO</name>
8480                  <description>Internal Low Speed Oscillator (ILO)</description>
8481                  <value>1</value>
8482                </enumeratedValue>
8483                <enumeratedValue>
8484                  <name>WCO</name>
8485                  <description>Watch-Crystal Oscillator (WCO)</description>
8486                  <value>2</value>
8487                </enumeratedValue>
8488                <enumeratedValue>
8489                  <name>BAK</name>
8490                  <description>Root of the Backup domain clock tree (BAK)</description>
8491                  <value>3</value>
8492                </enumeratedValue>
8493                <enumeratedValue>
8494                  <name>ALTLF</name>
8495                  <description>Alternate low-frequency clock input to SRSS (ALTLF)</description>
8496                  <value>4</value>
8497                </enumeratedValue>
8498                <enumeratedValue>
8499                  <name>LFCLK</name>
8500                  <description>Root of the low-speed clock tree (LFCLK)</description>
8501                  <value>5</value>
8502                </enumeratedValue>
8503                <enumeratedValue>
8504                  <name>IMO</name>
8505                  <description>Internal Main Oscillator (IMO).  This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.</description>
8506                  <value>6</value>
8507                </enumeratedValue>
8508                <enumeratedValue>
8509                  <name>SLPCTRL</name>
8510                  <description>Sleep Controller clock (SLPCTRL).  This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.</description>
8511                  <value>7</value>
8512                </enumeratedValue>
8513                <enumeratedValue>
8514                  <name>PILO</name>
8515                  <description>Precision Internal Low Speed Oscillator (PILO)</description>
8516                  <value>8</value>
8517                </enumeratedValue>
8518                <enumeratedValue>
8519                  <name>ILO1</name>
8520                  <description>Internal Low Speed Oscillator (ILO1), if present on the product.</description>
8521                  <value>9</value>
8522                </enumeratedValue>
8523                <enumeratedValue>
8524                  <name>ECO_PRESCALER</name>
8525                  <description>ECO Prescaler (ECO_PRESCALER)</description>
8526                  <value>10</value>
8527                </enumeratedValue>
8528                <enumeratedValue>
8529                  <name>LPECO</name>
8530                  <description>LPECO</description>
8531                  <value>11</value>
8532                </enumeratedValue>
8533                <enumeratedValue>
8534                  <name>LPECO_PRESCALER</name>
8535                  <description>LPECO Prescaler (LPECO_PRESCALER)</description>
8536                  <value>12</value>
8537                </enumeratedValue>
8538                <enumeratedValue>
8539                  <name>MFO</name>
8540                  <description>Medium Frequency Oscillator (MFO)</description>
8541                  <value>13</value>
8542                </enumeratedValue>
8543              </enumeratedValues>
8544            </field>
8545          </fields>
8546        </register>
8547        <register>
8548          <name>CLK_CAL_CNT1</name>
8549          <description>Clock Calibration Counter 1</description>
8550          <addressOffset>0x148</addressOffset>
8551          <size>32</size>
8552          <access>read-write</access>
8553          <resetValue>0x80000000</resetValue>
8554          <resetMask>0xE0FFFFFF</resetMask>
8555          <fields>
8556            <field>
8557              <name>CAL_COUNTER1</name>
8558              <description>Down-counter clocked on fast clock output #0 (see CLK_OUTPUT_FAST). This register always reads as zero.  Counting starts internally when this register is written with a nonzero value.  CAL_COUNTER_DONE goes immediately low to indicate that the counter has started and will be asserted when the counters are done.  Do not write this field unless CAL_COUNTER_DONE==1.  Both clocks must be running or the measurement will not complete, and this case can be recovered using CAL_RESET.</description>
8559              <bitRange>[23:0]</bitRange>
8560              <access>read-write</access>
8561            </field>
8562            <field>
8563              <name>CAL_RESET</name>
8564              <description>Reset clock calibration logic for window mode.  This can be used to recover from unexpected conditions, such as no clock present on counter #1.
8565Set this bit only when CLK_CAL_TEST.CAL_WINDOW_SEL=1 (window mode).  It takes 3 clock cycles for reset to propagate.</description>
8566              <bitRange>[29:29]</bitRange>
8567              <access>read-write</access>
8568            </field>
8569            <field>
8570              <name>CAL_CLK1_PRESENT</name>
8571              <description>Status bit indicating that a posedge was detected by counter #1.  If this bit never asserts, there is no clock on counter #1 and CAL_COUNTER_DONE will stay low indefinitely.  This can be recovered with CAL_RESET.</description>
8572              <bitRange>[30:30]</bitRange>
8573              <access>read-only</access>
8574            </field>
8575            <field>
8576              <name>CAL_COUNTER_DONE</name>
8577              <description>Status bit indicating that the internal counter #1 is finished counting and CLK_CAL_CNT2.COUNTER stopped counting up</description>
8578              <bitRange>[31:31]</bitRange>
8579              <access>read-only</access>
8580            </field>
8581          </fields>
8582        </register>
8583        <register>
8584          <name>CLK_CAL_CNT2</name>
8585          <description>Clock Calibration Counter 2</description>
8586          <addressOffset>0x14C</addressOffset>
8587          <size>32</size>
8588          <access>read-only</access>
8589          <resetValue>0x0</resetValue>
8590          <resetMask>0xFFFFFF</resetMask>
8591          <fields>
8592            <field>
8593              <name>CAL_COUNTER2</name>
8594              <description>Up-counter clocked on fast clock output  #1 (see CLK_OUTPUT_FAST). When CLK_CAL_CNT1.CAL_COUNTER_DONE==1, the counter is stopped and can be read by SW.  Do not read this value unless CAL_COUNTER_DONE==1.  The expected final value is related to the ratio of clock frequencies used for the two counters and the value loaded into counter 1: CLK_CAL_CNT2.COUNTER=(F_cnt2/F_cnt1)*(CLK_CAL_CNT1.COUNTER)</description>
8595              <bitRange>[23:0]</bitRange>
8596              <access>read-only</access>
8597            </field>
8598          </fields>
8599        </register>
8600        <register>
8601          <name>SRSS_INTR</name>
8602          <description>SRSS Interrupt Register</description>
8603          <addressOffset>0x200</addressOffset>
8604          <size>32</size>
8605          <access>read-write</access>
8606          <resetValue>0x0</resetValue>
8607          <resetMask>0x80000021</resetMask>
8608          <fields>
8609            <field>
8610              <name>WDT_MATCH</name>
8611              <description>WDT Interrupt Request.  This bit is set each time WDT_COUNTR==WDT_MATCH.  W1C also feeds the watch dog.  Missing 2 interrupts in a row will generate a reset.  Due to internal synchronization, it takes 2 SYSCLK cycles to update after a W1C.</description>
8612              <bitRange>[0:0]</bitRange>
8613              <access>read-write</access>
8614            </field>
8615            <field>
8616              <name>CLK_CAL</name>
8617              <description>Clock calibration counter is done.  This field is reset during DEEPSLEEP mode.</description>
8618              <bitRange>[5:5]</bitRange>
8619              <access>read-write</access>
8620            </field>
8621            <field>
8622              <name>AINTR</name>
8623              <description>See additional interrupts in SRSS_AINTR.</description>
8624              <bitRange>[31:31]</bitRange>
8625              <access>read-only</access>
8626            </field>
8627          </fields>
8628        </register>
8629        <register>
8630          <name>SRSS_INTR_SET</name>
8631          <description>SRSS Interrupt Set Register</description>
8632          <addressOffset>0x204</addressOffset>
8633          <size>32</size>
8634          <access>read-write</access>
8635          <resetValue>0x0</resetValue>
8636          <resetMask>0x21</resetMask>
8637          <fields>
8638            <field>
8639              <name>WDT_MATCH</name>
8640              <description>Set interrupt for low voltage detector WDT_MATCH</description>
8641              <bitRange>[0:0]</bitRange>
8642              <access>read-write</access>
8643            </field>
8644            <field>
8645              <name>CLK_CAL</name>
8646              <description>Set interrupt for clock calibration counter done.  This field is reset during DEEPSLEEP mode.</description>
8647              <bitRange>[5:5]</bitRange>
8648              <access>read-write</access>
8649            </field>
8650          </fields>
8651        </register>
8652        <register>
8653          <name>SRSS_INTR_MASK</name>
8654          <description>SRSS Interrupt Mask Register</description>
8655          <addressOffset>0x208</addressOffset>
8656          <size>32</size>
8657          <access>read-write</access>
8658          <resetValue>0x0</resetValue>
8659          <resetMask>0x21</resetMask>
8660          <fields>
8661            <field>
8662              <name>WDT_MATCH</name>
8663              <description>Mask for watchdog timer.  Clearing this bit will not forward the interrupt to the CPU.  It will not, however, disable the WDT reset generation on 2 missed interrupts.  When WDT resets the chip, it also internally pends an interrupt that survives the reset.  To prevent unintended ISR execution, clear SRSS_INTR.WDT_MATCH before setting this bit.</description>
8664              <bitRange>[0:0]</bitRange>
8665              <access>read-write</access>
8666            </field>
8667            <field>
8668              <name>CLK_CAL</name>
8669              <description>Mask for clock calibration done</description>
8670              <bitRange>[5:5]</bitRange>
8671              <access>read-write</access>
8672            </field>
8673          </fields>
8674        </register>
8675        <register>
8676          <name>SRSS_INTR_MASKED</name>
8677          <description>SRSS Interrupt Masked Register</description>
8678          <addressOffset>0x20C</addressOffset>
8679          <size>32</size>
8680          <access>read-only</access>
8681          <resetValue>0x0</resetValue>
8682          <resetMask>0x80000021</resetMask>
8683          <fields>
8684            <field>
8685              <name>WDT_MATCH</name>
8686              <description>Logical and of corresponding request and mask bits.</description>
8687              <bitRange>[0:0]</bitRange>
8688              <access>read-only</access>
8689            </field>
8690            <field>
8691              <name>CLK_CAL</name>
8692              <description>Logical and of corresponding request and mask bits.</description>
8693              <bitRange>[5:5]</bitRange>
8694              <access>read-only</access>
8695            </field>
8696            <field>
8697              <name>AINTR</name>
8698              <description>See additional MASKED bits in SRSS_AINTR_MASKED.ADDITIONAL</description>
8699              <bitRange>[31:31]</bitRange>
8700              <access>read-only</access>
8701            </field>
8702          </fields>
8703        </register>
8704        <register>
8705          <name>SRSS_AINTR</name>
8706          <description>SRSS Additional Interrupt Register</description>
8707          <addressOffset>0x300</addressOffset>
8708          <size>32</size>
8709          <access>read-write</access>
8710          <resetValue>0x0</resetValue>
8711          <resetMask>0x6</resetMask>
8712          <fields>
8713            <field>
8714              <name>HVLVD1</name>
8715              <description>Interrupt for low voltage detector HVLVD1</description>
8716              <bitRange>[1:1]</bitRange>
8717              <access>read-write</access>
8718            </field>
8719            <field>
8720              <name>HVLVD2</name>
8721              <description>Interrupt for low voltage detector HVLVD2</description>
8722              <bitRange>[2:2]</bitRange>
8723              <access>read-write</access>
8724            </field>
8725          </fields>
8726        </register>
8727        <register>
8728          <name>SRSS_AINTR_SET</name>
8729          <description>SRSS Additional Interrupt Set Register</description>
8730          <addressOffset>0x304</addressOffset>
8731          <size>32</size>
8732          <access>read-write</access>
8733          <resetValue>0x0</resetValue>
8734          <resetMask>0x6</resetMask>
8735          <fields>
8736            <field>
8737              <name>HVLVD1</name>
8738              <description>Set interrupt for low voltage detector HVLVD1</description>
8739              <bitRange>[1:1]</bitRange>
8740              <access>read-write</access>
8741            </field>
8742            <field>
8743              <name>HVLVD2</name>
8744              <description>Set interrupt for low voltage detector HVLVD2</description>
8745              <bitRange>[2:2]</bitRange>
8746              <access>read-write</access>
8747            </field>
8748          </fields>
8749        </register>
8750        <register>
8751          <name>SRSS_AINTR_MASK</name>
8752          <description>SRSS Additional Interrupt Mask Register</description>
8753          <addressOffset>0x308</addressOffset>
8754          <size>32</size>
8755          <access>read-write</access>
8756          <resetValue>0x0</resetValue>
8757          <resetMask>0x6</resetMask>
8758          <fields>
8759            <field>
8760              <name>HVLVD1</name>
8761              <description>Mask for low voltage detector HVLVD1</description>
8762              <bitRange>[1:1]</bitRange>
8763              <access>read-write</access>
8764            </field>
8765            <field>
8766              <name>HVLVD2</name>
8767              <description>Mask for low voltage detector HVLVD2</description>
8768              <bitRange>[2:2]</bitRange>
8769              <access>read-write</access>
8770            </field>
8771          </fields>
8772        </register>
8773        <register>
8774          <name>SRSS_AINTR_MASKED</name>
8775          <description>SRSS Additional Interrupt Masked Register</description>
8776          <addressOffset>0x30C</addressOffset>
8777          <size>32</size>
8778          <access>read-only</access>
8779          <resetValue>0x0</resetValue>
8780          <resetMask>0x6</resetMask>
8781          <fields>
8782            <field>
8783              <name>HVLVD1</name>
8784              <description>Logical and of corresponding request and mask bits.</description>
8785              <bitRange>[1:1]</bitRange>
8786              <access>read-only</access>
8787            </field>
8788            <field>
8789              <name>HVLVD2</name>
8790              <description>Logical and of corresponding request and mask bits.</description>
8791              <bitRange>[2:2]</bitRange>
8792              <access>read-only</access>
8793            </field>
8794          </fields>
8795        </register>
8796        <register>
8797          <name>TST_DEBUG_CTL</name>
8798          <description>Debug Control Register</description>
8799          <addressOffset>0x404</addressOffset>
8800          <size>32</size>
8801          <access>read-write</access>
8802          <resetValue>0x0</resetValue>
8803          <resetMask>0x8000000F</resetMask>
8804          <fields>
8805            <field>
8806              <name>REQUEST</name>
8807              <description>N/A</description>
8808              <bitRange>[3:0]</bitRange>
8809              <access>read-write</access>
8810            </field>
8811            <field>
8812              <name>DEBUG_WFA</name>
8813              <description>Wait for Action.  Set by BootROM when it waits for application or debug certificate to be loaded into the RAM. The bit must be cleared to continue BootROM operation. It is used by the Sys-AP.</description>
8814              <bitRange>[31:31]</bitRange>
8815              <access>read-write</access>
8816            </field>
8817          </fields>
8818        </register>
8819        <register>
8820          <name>TST_DEBUG_STATUS</name>
8821          <description>Debug Status Register</description>
8822          <addressOffset>0x408</addressOffset>
8823          <size>32</size>
8824          <access>read-write</access>
8825          <resetValue>0x0</resetValue>
8826          <resetMask>0xFFFFFFFF</resetMask>
8827          <fields>
8828            <field>
8829              <name>DEBUG_STATUS</name>
8830              <description>RAM application execution status. This status can be read by the debugger using Sys-AP or user application when RAM application completes with system reset. This field survives some resets, including a system reset.</description>
8831              <bitRange>[31:0]</bitRange>
8832              <access>read-write</access>
8833            </field>
8834          </fields>
8835        </register>
8836        <register>
8837          <name>RES_SOFT_CTL</name>
8838          <description>Soft Reset Trigger Register</description>
8839          <addressOffset>0x410</addressOffset>
8840          <size>32</size>
8841          <access>read-write</access>
8842          <resetValue>0x0</resetValue>
8843          <resetMask>0x1</resetMask>
8844          <fields>
8845            <field>
8846              <name>TRIGGER_SOFT</name>
8847              <description>Triggers a soft reset.  The reset clears this bit.</description>
8848              <bitRange>[0:0]</bitRange>
8849              <access>read-write</access>
8850            </field>
8851          </fields>
8852        </register>
8853        <register>
8854          <dim>16</dim>
8855          <dimIncrement>4</dimIncrement>
8856          <name>PWR_HIB_DATA[%s]</name>
8857          <description>HIBERNATE Data Register</description>
8858          <addressOffset>0x800</addressOffset>
8859          <size>32</size>
8860          <access>read-write</access>
8861          <resetValue>0x0</resetValue>
8862          <resetMask>0xFFFFFFFF</resetMask>
8863          <fields>
8864            <field>
8865              <name>HIB_DATA</name>
8866              <description>Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose.  Note that waking up from HIBERNATE using XRES will reset this register.</description>
8867              <bitRange>[31:0]</bitRange>
8868              <access>read-write</access>
8869            </field>
8870          </fields>
8871        </register>
8872        <register>
8873          <name>PWR_HIB_WAKE_CTL</name>
8874          <description>Hibernate Wakeup Mask Register</description>
8875          <addressOffset>0x8A0</addressOffset>
8876          <size>32</size>
8877          <access>read-write</access>
8878          <resetValue>0x0</resetValue>
8879          <resetMask>0xE0FFFFFF</resetMask>
8880          <fields>
8881            <field>
8882              <name>HIB_WAKE_SRC</name>
8883              <description>When set, HIBERNATE will wakeup for the assigned source  The number and assignment of HIBERNATE wakeup sources are product-specific.</description>
8884              <bitRange>[23:0]</bitRange>
8885              <access>read-write</access>
8886            </field>
8887            <field>
8888              <name>HIB_WAKE_CSV_BAK</name>
8889              <description>When set, HIBERNATE will wakeup for CSV_BAK detection.</description>
8890              <bitRange>[29:29]</bitRange>
8891              <access>read-write</access>
8892            </field>
8893            <field>
8894              <name>HIB_WAKE_RTC</name>
8895              <description>When set, HIBERNATE will wakeup for a pending RTC interrupt.</description>
8896              <bitRange>[30:30]</bitRange>
8897              <access>read-write</access>
8898            </field>
8899            <field>
8900              <name>HIB_WAKE_WDT</name>
8901              <description>When set, HIBERNATE will wakeup for a pending WDT interrupt.</description>
8902              <bitRange>[31:31]</bitRange>
8903              <access>read-write</access>
8904            </field>
8905          </fields>
8906        </register>
8907        <register>
8908          <name>PWR_HIB_WAKE_CTL2</name>
8909          <description>Hibernate Wakeup Polarity Register</description>
8910          <addressOffset>0x8A4</addressOffset>
8911          <size>32</size>
8912          <access>read-write</access>
8913          <resetValue>0x0</resetValue>
8914          <resetMask>0xFFFFFF</resetMask>
8915          <fields>
8916            <field>
8917              <name>HIB_WAKE_SRC</name>
8918              <description>Each bit selects the polarity for the corresponding HIBERNATE wakeup source.  The number and assignment of wakeup sources are product-specific.
89190: Wakes when unmasked input is 0.
89201: Wakes when unmasked input is 1.</description>
8921              <bitRange>[23:0]</bitRange>
8922              <access>read-write</access>
8923            </field>
8924          </fields>
8925        </register>
8926        <register>
8927          <name>PWR_HIB_WAKE_CAUSE</name>
8928          <description>Hibernate Wakeup Cause Register</description>
8929          <addressOffset>0x8AC</addressOffset>
8930          <size>32</size>
8931          <access>read-write</access>
8932          <resetValue>0x0</resetValue>
8933          <resetMask>0xE0FFFFFF</resetMask>
8934          <fields>
8935            <field>
8936              <name>HIB_WAKE_SRC</name>
8937              <description>Each bit indicates a HIBERNATE wakeup cause.  The number and assigment of wakeup sources are product-specific.  For each bit, writing a 1 clears the cause flag.</description>
8938              <bitRange>[23:0]</bitRange>
8939              <access>read-write</access>
8940            </field>
8941            <field>
8942              <name>HIB_WAKE_CSV_BAK</name>
8943              <description>Indicates CSV_BAK wakeup cause.  The related fault must be handled before this bit can be cleared.</description>
8944              <bitRange>[29:29]</bitRange>
8945              <access>read-write</access>
8946            </field>
8947            <field>
8948              <name>HIB_WAKE_RTC</name>
8949              <description>Indicates RTC wakeup cause.  The RTC interrupt must be cleared before this bit can be cleared.</description>
8950              <bitRange>[30:30]</bitRange>
8951              <access>read-write</access>
8952            </field>
8953            <field>
8954              <name>HIB_WAKE_WDT</name>
8955              <description>Indicates WDT wakeup cause.  The WDT interrupt must be cleared before this bit can be cleared.</description>
8956              <bitRange>[31:31]</bitRange>
8957              <access>read-write</access>
8958            </field>
8959          </fields>
8960        </register>
8961        <register>
8962          <name>PWR_CTL</name>
8963          <description>Power Mode Control</description>
8964          <addressOffset>0x1000</addressOffset>
8965          <size>32</size>
8966          <access>read-only</access>
8967          <resetValue>0x0</resetValue>
8968          <resetMask>0x33</resetMask>
8969          <fields>
8970            <field>
8971              <name>POWER_MODE</name>
8972              <description>Current power mode of the device.  Note that this field cannot be read in all power modes on actual silicon.</description>
8973              <bitRange>[1:0]</bitRange>
8974              <access>read-only</access>
8975              <enumeratedValues>
8976                <enumeratedValue>
8977                  <name>RESET</name>
8978                  <description>System is resetting.</description>
8979                  <value>0</value>
8980                </enumeratedValue>
8981                <enumeratedValue>
8982                  <name>ACTIVE</name>
8983                  <description>At least one CPU is running.</description>
8984                  <value>1</value>
8985                </enumeratedValue>
8986                <enumeratedValue>
8987                  <name>SLEEP</name>
8988                  <description>No CPUs are running.  Peripherals may be running.</description>
8989                  <value>2</value>
8990                </enumeratedValue>
8991                <enumeratedValue>
8992                  <name>DEEPSLEEP</name>
8993                  <description>Main high-frequency clock is off; low speed clocks are available.  Communication interface clocks may be present.</description>
8994                  <value>3</value>
8995                </enumeratedValue>
8996              </enumeratedValues>
8997            </field>
8998            <field>
8999              <name>DEBUG_SESSION</name>
9000              <description>Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1)</description>
9001              <bitRange>[4:4]</bitRange>
9002              <access>read-only</access>
9003              <enumeratedValues>
9004                <enumeratedValue>
9005                  <name>NO_SESSION</name>
9006                  <description>No debug session active</description>
9007                  <value>0</value>
9008                </enumeratedValue>
9009                <enumeratedValue>
9010                  <name>SESSION_ACTIVE</name>
9011                  <description>Debug session is active.  Power modes behave differently to keep the debug session active, and current consumption may be higher than datasheet specification.</description>
9012                  <value>1</value>
9013                </enumeratedValue>
9014              </enumeratedValues>
9015            </field>
9016            <field>
9017              <name>LPM_READY</name>
9018              <description>Indicates whether certain low power functions are ready.  The low current circuits take longer to startup after XRES, HIBERNATE wakeup, or supply supervision reset wakeup than the normal mode circuits.  HIBERNATE mode may be entered regardless of this bit.
90190: If a low power circuit operation is requested, it will stay in its normal operating mode until it is ready.  If DEEPSLEEP is requested by all processors WFI/WFE, the device will instead enter SLEEP.  When low power circuits are ready, device will automatically enter the originally requested mode.
90201: Normal operation.  DEEPSLEEP and low power circuits operate as requested in other registers.</description>
9021              <bitRange>[5:5]</bitRange>
9022              <access>read-only</access>
9023            </field>
9024          </fields>
9025        </register>
9026        <register>
9027          <name>PWR_CTL2</name>
9028          <description>Power Mode Control 2</description>
9029          <addressOffset>0x1004</addressOffset>
9030          <size>32</size>
9031          <access>read-write</access>
9032          <resetValue>0x0</resetValue>
9033          <resetMask>0xDF331117</resetMask>
9034          <fields>
9035            <field>
9036              <name>LINREG_DIS</name>
9037              <description>Explicitly disable the linear Core Regulator.  Write zero for Traveo II devices.  This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset.
90380: Linear Core Regulator is not explicitly disabled.  Hardware disables it automatically for internal sequences, including for DEEPSLEEP, HIBERNATE, and XRES low power modes.
90391: Linear Core Regulator is explicitly disabled.  Only use this for special cases when another source supplies vccd during ACTIVE and SLEEP modes.  This setting is only legal when another source supplies vccd, but there is no special hardware protection for this case.</description>
9040              <bitRange>[0:0]</bitRange>
9041              <access>read-write</access>
9042            </field>
9043            <field>
9044              <name>LINREG_OK</name>
9045              <description>Status of the linear Core Regulator.</description>
9046              <bitRange>[1:1]</bitRange>
9047              <access>read-only</access>
9048            </field>
9049            <field>
9050              <name>LINREG_LPMODE</name>
9051              <description>Control the power mode of the Linear Regulator.  The value in this register is ignored and normal mode is used until LPM_READY==1.  This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset.
90520: Linear Regulator operates in normal mode.
90531: Linear Regulator operates in low power mode.  Load current capability is reduced, and firmware must ensure the current is kept within the limit.</description>
9054              <bitRange>[2:2]</bitRange>
9055              <access>read-write</access>
9056            </field>
9057            <field>
9058              <name>DPSLP_REG_DIS</name>
9059              <description>Explicity disable the DeepSleep regulator, including circuits shared with the Active Regulator.  This register must not be set except as part of an Infineon-provided sequence or API.  This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset.
90600: DeepSleep Regulator is not explicitly disabled.  This is the normal setting, and hardware automatically controls the DeepSleep regulator for most sequences, including for HIBERNATE and XRES low power modes.  This setting must be used if the Active Linear Regulator is used, because some circuitry is shared.
90611: DeepSleep Regulator is explicitly disabled.  Only use this for special cases as part of an Infineon-provided handoff to another supply source.  For example, this setting may be used when another source supplies vccdpslp during DEEPSLEEP mode and the Active Linear Regulator is not usedfor ACTIVE/SLEEP modes.</description>
9062              <bitRange>[4:4]</bitRange>
9063              <access>read-write</access>
9064            </field>
9065            <field>
9066              <name>RET_REG_DIS</name>
9067              <description>Explicitly disable the Retention regulator.  This field should normally be zero, except for special sequences provided by Infineon to use a different regulator.  This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset.
90680: Retention Regulator is not explicitly disabled.  Hardware disables it automatically for internal sequences, including for HIBERNATE and XRES low power modes.  Hardware keeps the Retention Regulator enabled during ACTIVE/SLEEP modes, so it is ready to enter DEEPSLEEP at any time.
90691: Retention Regulator is explicitly disabled.  Only use this for special cases when another source supplies vccret during DEEPSLEEP mode.  This setting is only legal when another source supplies vccret, but there is no special hardware protection for this case.</description>
9070              <bitRange>[8:8]</bitRange>
9071              <access>read-write</access>
9072            </field>
9073            <field>
9074              <name>NWELL_REG_DIS</name>
9075              <description>Explicitly disable the Nwell regulator.  This register should normally be zero, except for special sequences provided by Infineon to use a different regulator.  This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset.
90760: Nwell Regulator is on.  Hardware disables it automatically for internal sequences, including for HIBERNATE and XRES low power modes.  Hardware keeps the Nwell Regulator enabled during ACTIVE/SLEEP modes, so it is ready to enter DEEPSLEEP at any time.
90771: Nwell Regulator is explicitly disabled.  Only use this for special cases when another source supplies vnwell during DEEPSLEEP mode.  This setting is only legal when another source supplies vnwell, but there is no special hardware protection for this case.</description>
9078              <bitRange>[12:12]</bitRange>
9079              <access>read-write</access>
9080            </field>
9081            <field>
9082              <name>REFV_DIS</name>
9083              <description>N/A</description>
9084              <bitRange>[16:16]</bitRange>
9085              <access>read-write</access>
9086            </field>
9087            <field>
9088              <name>REFV_OK</name>
9089              <description>Indicates that the normal mode of the voltage reference is ready.</description>
9090              <bitRange>[17:17]</bitRange>
9091              <access>read-only</access>
9092            </field>
9093            <field>
9094              <name>REFVBUF_DIS</name>
9095              <description>Disable the voltage reference buffer.  Firmware should only disable the buffer when there is no connected circuit that is using it.  SRSS circuits that require it are the PLL and ECO.  A particular product may have circuits outside the SRSS that use the buffer.  This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset.</description>
9096              <bitRange>[20:20]</bitRange>
9097              <access>read-write</access>
9098            </field>
9099            <field>
9100              <name>REFVBUF_OK</name>
9101              <description>Indicates that the voltage reference buffer is ready.  Due to synchronization delays, it may take two IMO clock cycles for hardware to clear this bit after asserting REFVBUF_DIS=1.</description>
9102              <bitRange>[21:21]</bitRange>
9103              <access>read-only</access>
9104            </field>
9105            <field>
9106              <name>REFI_DIS</name>
9107              <description>N/A</description>
9108              <bitRange>[24:24]</bitRange>
9109              <access>read-write</access>
9110            </field>
9111            <field>
9112              <name>REFI_OK</name>
9113              <description>Indicates that the current reference is ready.  Due to synchronization delays, it may take two IMO clock cycles for hardware to clear this bit after asserting REFI_DIS=1.</description>
9114              <bitRange>[25:25]</bitRange>
9115              <access>read-only</access>
9116            </field>
9117            <field>
9118              <name>REFI_LPMODE</name>
9119              <description>Control the power mode of the reference current generator.  The value in this register is ignored and normal mode is used until LPM_READY==1.  This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset.
91200: Current reference generator operates in normal mode.
91211: Current reference generator operates in low power mode.  Response time is reduced to save current.</description>
9122              <bitRange>[26:26]</bitRange>
9123              <access>read-write</access>
9124            </field>
9125            <field>
9126              <name>PORBOD_LPMODE</name>
9127              <description>Control the power mode of the POR/BOD circuits.  The value in this register is ignored and normal mode is used until LPM_READY==1.  This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset.
91280: POR/BOD circuits operate in normal mode.
91291: POR/BOD circuits operate in low power mode.  Response time is reduced to save current.</description>
9130              <bitRange>[27:27]</bitRange>
9131              <access>read-write</access>
9132            </field>
9133            <field>
9134              <name>BGREF_LPMODE</name>
9135              <description>Control the circuit-level power mode of the Bandgap Reference circuits for higher operating modes than DEEPSLEEP.   This selects a second set of bandgap voltage and current generation circuits that are optimized for low current consumption.  The low current circuits are automatically used in DEEPSLEEP mode regardless of this bit.  The value in this register is ignored and higher-current mode is used until LPM_READY==1.   After this bit is set, the Active Reference circuit can be disabled to reduce current (ACT_REF_DIS=0).    Firmware is responsible to enable the Active Reference and ensure ACT_REF_OK==1 before changing back to higher current mode.  This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset.
91360: Bandgap Reference uses the normal settings.
91371: Bandgap Reference uses the low power DeepSleep circuits.  Power supply rejection is reduced to save current.</description>
9138              <bitRange>[28:28]</bitRange>
9139              <access>read-write</access>
9140            </field>
9141            <field>
9142              <name>FREEZE_DPSLP</name>
9143              <description>Controls whether mode and state of GPIOs and SIOs in the system are frozen.  This is intended to be used as part of the DEEPSLEEP-RAM and DEEPSLEEP-OFF entry and exit sequences.  It is set by HW while entering DEEPSLEEP-RAM and DEEPSLEEP-OFF modes.   Writing a 1 clears freeze and GPIOs and SIOs resume normal operation.</description>
9144              <bitRange>[30:30]</bitRange>
9145              <access>read-write</access>
9146            </field>
9147            <field>
9148              <name>PLL_LS_BYPASS</name>
9149              <description>Bypass level shifter inside the PLL.  Unused, if no PLL is present in the product.
91500: Do not bypass the level shifter.  This setting is ok for all operational modes and vccd target voltage.
91511: Bypass the level shifter.  This may reduce jitter on the PLL output clock, but can only be used when vccd is targeted to 1.1V nominal.  Otherwise, it can result in clock degradation and static current.</description>
9152              <bitRange>[31:31]</bitRange>
9153              <access>read-write</access>
9154            </field>
9155          </fields>
9156        </register>
9157        <register>
9158          <name>PWR_HIBERNATE</name>
9159          <description>HIBERNATE Mode Register</description>
9160          <addressOffset>0x1008</addressOffset>
9161          <size>32</size>
9162          <access>read-write</access>
9163          <resetValue>0x0</resetValue>
9164          <resetMask>0xEFFEFFFF</resetMask>
9165          <fields>
9166            <field>
9167              <name>TOKEN</name>
9168              <description>Contains a 8-bit token that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware to differentiate WAKEUP from a general RESET event.  Note that waking up from HIBERNATE using XRES will reset this register.</description>
9169              <bitRange>[7:0]</bitRange>
9170              <access>read-write</access>
9171            </field>
9172            <field>
9173              <name>UNLOCK</name>
9174              <description>This byte must be set to 0x3A for FREEZE or HIBERNATE fields to operate.  Any other value in this register will cause FREEZE/HIBERNATE to have no effect, except as noted in the FREEZE description.</description>
9175              <bitRange>[15:8]</bitRange>
9176              <access>read-write</access>
9177            </field>
9178            <field>
9179              <name>FREEZE</name>
9180              <description>Controls whether mode and state of GPIOs and SIOs in the system are frozen.  This is intended to be used as part of the HIBERNATE entry and exit sequences.  When entering HIBERNATE mode, the first write instructs DEEPSLEEP peripherals that they cannot ignore the upcoming freeze command.  This occurs even in the illegal condition where UNLOCK is not set.  If UNLOCK and HIBERNATE are properly set, the IOs actually freeze on the second write.  Supply supervision is disabled during HIBERNATE mode.  HIBERNATE peripherals ignore resets (excluding XRES) while FREEZE==1.</description>
9181              <bitRange>[17:17]</bitRange>
9182              <access>read-write</access>
9183            </field>
9184            <field>
9185              <name>MASK_HIBALARM</name>
9186              <description>Obsolete.  Use PWR_HIB_WAKE_CTL.HIB_WAKE_RTC for new designs.</description>
9187              <bitRange>[18:18]</bitRange>
9188              <access>read-write</access>
9189            </field>
9190            <field>
9191              <name>MASK_HIBWDT</name>
9192              <description>Obsolete.  Use PWR_HIB_WAKE_CTL.HIB_WAKE_WDT for new designs.</description>
9193              <bitRange>[19:19]</bitRange>
9194              <access>read-write</access>
9195            </field>
9196            <field>
9197              <name>POLARITY_HIBPIN</name>
9198              <description>Obsolete.  Use PWR_HIB_WAKE_CTL2.HIB_WAKE_SRC for new designs.</description>
9199              <bitRange>[23:20]</bitRange>
9200              <access>read-write</access>
9201            </field>
9202            <field>
9203              <name>MASK_HIBPIN</name>
9204              <description>Obsolete.  Use PWR_HIB_WAKE_CTL.HIB_WAKE_SRC for new designs.</description>
9205              <bitRange>[27:24]</bitRange>
9206              <access>read-write</access>
9207            </field>
9208            <field>
9209              <name>SENSE_MODE</name>
9210              <description>Power mode when wakeups are sensitive.  The default of this field is 0 for software compatibility with other products.  It is recommended to set this field to 1 for new/updated software.
92110: Wakeups are sensitive only during HIBERNATE mode.  A wakeup pulse that comes just before HIBERNATE entry may be missed.  Backward compatible.
92121: Wakeups are sensitive in HIBERNATE and higher modes.  Before entering HIBERNATE, software must clear all unmasked, pending wakeups in PWR_HIB_WAKE_CAUSE register.  An unmasked, pending wakeup causes HIBERNATE wakeup, even if it was pending from before HIBERNATE entry.  This prevents missed wakeups.</description>
9213              <bitRange>[29:29]</bitRange>
9214              <access>read-write</access>
9215            </field>
9216            <field>
9217              <name>HIBERNATE_DISABLE</name>
9218              <description>Hibernate disable bit.
92190: Normal operation, HIBERNATE works as described
92201: Further writes to this register are ignored
9221Note: This bit is a write-once bit until the next reset.  Avoid changing any other bits in this register while disabling HIBERNATE mode.  Also, it is recommended to clear the UNLOCK code, if it was previously written..</description>
9222              <bitRange>[30:30]</bitRange>
9223              <access>read-write</access>
9224            </field>
9225            <field>
9226              <name>HIBERNATE</name>
9227              <description>Firmware sets this bit to enter HIBERNATE mode.  The system will enter HIBERNATE mode immediately after writing to this bit and will wakeup only in response to XRES or WAKEUP.  Both UNLOCK and FREEZE must have been set correctly in a previous write operations.  Otherwise, it will not enter HIBERNATE.  External supplies must have been stable for 250us before entering HIBERNATE mode.</description>
9228              <bitRange>[31:31]</bitRange>
9229              <access>read-write</access>
9230            </field>
9231          </fields>
9232        </register>
9233        <register>
9234          <name>PWR_BUCK_CTL</name>
9235          <description>Buck Control Register</description>
9236          <addressOffset>0x1010</addressOffset>
9237          <size>32</size>
9238          <access>read-write</access>
9239          <resetValue>0x5</resetValue>
9240          <resetMask>0xC0000007</resetMask>
9241          <fields>
9242            <field>
9243              <name>BUCK_OUT1_SEL</name>
9244              <description>Voltage output selection for vccbuck1 output.  This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset.  When increasing the voltage, it can take up to 200us for the output voltage to settle.  When decreasing the voltage, the settling time depends on the load current.
92450: 0.85V
92461: 0.875V
92472: 0.90V
92483: 1.0V (SISO-MC), 0.95V (SISO-LC, SIMO-LC)
92494: 1.05V
92505: 1.10V
92516: 1.15V
92527: 1.20V</description>
9253              <bitRange>[2:0]</bitRange>
9254              <access>read-write</access>
9255            </field>
9256            <field>
9257              <name>BUCK_EN</name>
9258              <description>Master enable for buck converter.    This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset.</description>
9259              <bitRange>[30:30]</bitRange>
9260              <access>read-write</access>
9261            </field>
9262            <field>
9263              <name>BUCK_OUT1_EN</name>
9264              <description>Enable for vccbuck1 output.  The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1.    This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset.  The regulator takes up to 600us to charge the external capacitor.  If there is additional load current while charging, this will increase the startup time.  The TRM specifies the required sequence when transitioning vccd from the LDO to SIMO Buck output #1.</description>
9265              <bitRange>[31:31]</bitRange>
9266              <access>read-write</access>
9267            </field>
9268          </fields>
9269        </register>
9270        <register>
9271          <name>PWR_BUCK_CTL2</name>
9272          <description>Buck Control Register 2</description>
9273          <addressOffset>0x1014</addressOffset>
9274          <size>32</size>
9275          <access>read-write</access>
9276          <resetValue>0x0</resetValue>
9277          <resetMask>0xC0000007</resetMask>
9278          <fields>
9279            <field>
9280              <name>BUCK_OUT2_SEL</name>
9281              <description>Voltage output selection for vccbuck2 output.  When increasing the voltage, it can take up to 200us for the output voltage to settle.  When decreasing the voltage, the settling time depends on the load current.
92820: 1.15V
92831: 1.20V
92842: 1.25V
92853: 1.30V
92864: 1.35V
92875: 1.40V
92886: 1.45V
92897: 1.50V</description>
9290              <bitRange>[2:0]</bitRange>
9291              <access>read-write</access>
9292            </field>
9293            <field>
9294              <name>BUCK_OUT2_HW_SEL</name>
9295              <description>Hardware control for vccbuck2 output.  When this bit is set, the value in BUCK_OUT2_EN is ignored and a hardware signal is used instead.  If the product has supporting hardware, it can directly control the enable signal for vccbuck2.  The same charging time in BUCK_OUT2_EN applies.</description>
9296              <bitRange>[30:30]</bitRange>
9297              <access>read-write</access>
9298            </field>
9299            <field>
9300              <name>BUCK_OUT2_EN</name>
9301              <description>Enable for vccbuck2 output.  The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1.  The regulator takes up to 600us to charge the external capacitor.  If there is additional load current while charging, this will increase the startup time.</description>
9302              <bitRange>[31:31]</bitRange>
9303              <access>read-write</access>
9304            </field>
9305          </fields>
9306        </register>
9307        <register>
9308          <name>PWR_SSV_CTL</name>
9309          <description>Supply Supervision Control Register</description>
9310          <addressOffset>0x1018</addressOffset>
9311          <size>32</size>
9312          <access>read-write</access>
9313          <resetValue>0x8080808</resetValue>
9314          <resetMask>0x9D909D9</resetMask>
9315          <fields>
9316            <field>
9317              <name>BODVDDD_VSEL</name>
9318              <description>Selects the voltage threshold for BOD on vddd.  The BOD does not reliably monitor the supply during the transition.
93190: vddd&lt;2.7V
93201: vddd&lt;3.0V</description>
9321              <bitRange>[0:0]</bitRange>
9322              <access>read-write</access>
9323            </field>
9324            <field>
9325              <name>BODVDDD_ENABLE</name>
9326              <description>Enable for BOD on vddd.  This cannot be disabled during normal operation.</description>
9327              <bitRange>[3:3]</bitRange>
9328              <access>read-write</access>
9329            </field>
9330            <field>
9331              <name>BODVDDA_VSEL</name>
9332              <description>Selects the voltage threshold for BOD on vdda.  Ensure BODVDDA_ENABLE==0 before changing this setting to prevent false triggers.
93330: vdda&lt;2.7V
93341: vdda&lt;3.0V</description>
9335              <bitRange>[4:4]</bitRange>
9336              <access>read-write</access>
9337            </field>
9338            <field>
9339              <name>BODVDDA_ACTION</name>
9340              <description>Action taken when the BOD on vdda triggers.</description>
9341              <bitRange>[7:6]</bitRange>
9342              <access>read-write</access>
9343              <enumeratedValues>
9344                <enumeratedValue>
9345                  <name>NOTHING</name>
9346                  <description>No action</description>
9347                  <value>0</value>
9348                </enumeratedValue>
9349                <enumeratedValue>
9350                  <name>FAULT</name>
9351                  <description>Generate a fault</description>
9352                  <value>1</value>
9353                </enumeratedValue>
9354                <enumeratedValue>
9355                  <name>RESET</name>
9356                  <description>Reset the chip</description>
9357                  <value>2</value>
9358                </enumeratedValue>
9359              </enumeratedValues>
9360            </field>
9361            <field>
9362              <name>BODVDDA_ENABLE</name>
9363              <description>Enable for BOD on vdda.  BODVDDA_ACTION will be triggered when the BOD is disabled.  If no action is desired when disabling, firmware must first write BODVDDA_ACTION=NOTHING in a separate write cycle.</description>
9364              <bitRange>[8:8]</bitRange>
9365              <access>read-write</access>
9366            </field>
9367            <field>
9368              <name>BODVCCD_ENABLE</name>
9369              <description>Enable for BOD on vccd.  This cannot be disabled during normal operation.</description>
9370              <bitRange>[11:11]</bitRange>
9371              <access>read-write</access>
9372            </field>
9373            <field>
9374              <name>OVDVDDD_VSEL</name>
9375              <description>Selects the voltage threshold for OVD on vddd.  The OVD does not reliably monitor the supply during the transition.
93760: vddd&gt;5.5V
93771: vddd&gt;5.0V</description>
9378              <bitRange>[16:16]</bitRange>
9379              <access>read-write</access>
9380            </field>
9381            <field>
9382              <name>OVDVDDD_ENABLE</name>
9383              <description>Enable for OVD on vddd.  This cannot be disabled during normal operation.</description>
9384              <bitRange>[19:19]</bitRange>
9385              <access>read-write</access>
9386            </field>
9387            <field>
9388              <name>OVDVDDA_VSEL</name>
9389              <description>Selects the voltage threshold for OVD on vdda.  Ensure OVDVDDA_ENABLE==0 before changing this setting to prevent false triggers
93900: vddd&gt;5.5V
93911: vddd&gt;5.0V</description>
9392              <bitRange>[20:20]</bitRange>
9393              <access>read-write</access>
9394            </field>
9395            <field>
9396              <name>OVDVDDA_ACTION</name>
9397              <description>Action taken when the OVD on vdda triggers.</description>
9398              <bitRange>[23:22]</bitRange>
9399              <access>read-write</access>
9400              <enumeratedValues>
9401                <enumeratedValue>
9402                  <name>NOTHING</name>
9403                  <description>No action</description>
9404                  <value>0</value>
9405                </enumeratedValue>
9406                <enumeratedValue>
9407                  <name>FAULT</name>
9408                  <description>Generate a fault</description>
9409                  <value>1</value>
9410                </enumeratedValue>
9411                <enumeratedValue>
9412                  <name>RESET</name>
9413                  <description>Reset the chip</description>
9414                  <value>2</value>
9415                </enumeratedValue>
9416              </enumeratedValues>
9417            </field>
9418            <field>
9419              <name>OVDVDDA_ENABLE</name>
9420              <description>Enable for OVD on vdda.</description>
9421              <bitRange>[24:24]</bitRange>
9422              <access>read-write</access>
9423            </field>
9424            <field>
9425              <name>OVDVCCD_ENABLE</name>
9426              <description>Enable for OVD on vccd.  This cannot be disabled during normal operation.</description>
9427              <bitRange>[27:27]</bitRange>
9428              <access>read-write</access>
9429            </field>
9430          </fields>
9431        </register>
9432        <register>
9433          <name>PWR_SSV_STATUS</name>
9434          <description>Supply Supervision Status Register</description>
9435          <addressOffset>0x101C</addressOffset>
9436          <size>32</size>
9437          <access>read-only</access>
9438          <resetValue>0x30505</resetValue>
9439          <resetMask>0x30707</resetMask>
9440          <fields>
9441            <field>
9442              <name>BODVDDD_OK</name>
9443              <description>BOD indicates vddd is ok.  This will always read 1, because a detected brownout will reset the chip.</description>
9444              <bitRange>[0:0]</bitRange>
9445              <access>read-only</access>
9446            </field>
9447            <field>
9448              <name>BODVDDA_OK</name>
9449              <description>BOD indicates vdda is ok.</description>
9450              <bitRange>[1:1]</bitRange>
9451              <access>read-only</access>
9452            </field>
9453            <field>
9454              <name>BODVCCD_OK</name>
9455              <description>BOD indicates vccd is ok.  This will always read 1, because a detected brownout will reset the chip.</description>
9456              <bitRange>[2:2]</bitRange>
9457              <access>read-only</access>
9458            </field>
9459            <field>
9460              <name>OVDVDDD_OK</name>
9461              <description>OVD indicates vddd is ok.  This will always read 1, because a detected over-voltage condition will reset the chip.</description>
9462              <bitRange>[8:8]</bitRange>
9463              <access>read-only</access>
9464            </field>
9465            <field>
9466              <name>OVDVDDA_OK</name>
9467              <description>OVD indicates vdda is ok.</description>
9468              <bitRange>[9:9]</bitRange>
9469              <access>read-only</access>
9470            </field>
9471            <field>
9472              <name>OVDVCCD_OK</name>
9473              <description>OVD indicates vccd is ok.    This will always read 1, because a detected over-over-voltage condition will reset the chip.</description>
9474              <bitRange>[10:10]</bitRange>
9475              <access>read-only</access>
9476            </field>
9477            <field>
9478              <name>OCD_ACT_LINREG_OK</name>
9479              <description>OCD indicates the current drawn from the linear Active Regulator is ok.  This will always read 1, because a detected over-current condition will reset the chip.</description>
9480              <bitRange>[16:16]</bitRange>
9481              <access>read-only</access>
9482            </field>
9483            <field>
9484              <name>OCD_DPSLP_REG_OK</name>
9485              <description>OCD indicates the current drawn from the linear DeepSleep Regulator is ok.    This will always read 1, because a detected over-current condition will reset the chip.</description>
9486              <bitRange>[17:17]</bitRange>
9487              <access>read-only</access>
9488            </field>
9489          </fields>
9490        </register>
9491        <register>
9492          <name>PWR_LVD_CTL</name>
9493          <description>High Voltage / Low Voltage Detector (HVLVD) Configuration Register</description>
9494          <addressOffset>0x1020</addressOffset>
9495          <size>32</size>
9496          <access>read-write</access>
9497          <resetValue>0x0</resetValue>
9498          <resetMask>0x7DFFF</resetMask>
9499          <fields>
9500            <field>
9501              <name>HVLVD1_TRIPSEL</name>
9502              <description>Threshold selection for HVLVD1.  Disable the detector (HVLVD1_EN=0) before changing the threshold.
95030: rise=1.225V (nom), fall=1.2V (nom)
95041: rise=1.425V (nom), fall=1.4V (nom)
95052: rise=1.625V (nom), fall=1.6V (nom)
95063: rise=1.825V (nom), fall=1.8V (nom)
95074: rise=2.025V (nom), fall=2V (nom)
95085: rise=2.125V (nom), fall=2.1V (nom)
95096: rise=2.225V (nom), fall=2.2V (nom)
95107: rise=2.325V (nom), fall=2.3V (nom)
95118: rise=2.425V (nom), fall=2.4V (nom)
95129: rise=2.525V (nom), fall=2.5V (nom)
951310: rise=2.625V (nom), fall=2.6V (nom)
951411: rise=2.725V (nom), fall=2.7V (nom)
951512: rise=2.825V (nom), fall=2.8V (nom)
951613: rise=2.925V (nom), fall=2.9V (nom)
951714: rise=3.025V (nom), fall=3.0V (nom)
951815: rise=3.125V (nom), fall=3.1V (nom)</description>
9519              <bitRange>[3:0]</bitRange>
9520              <access>read-write</access>
9521            </field>
9522            <field>
9523              <name>HVLVD1_SRCSEL</name>
9524              <description>Source selection for HVLVD1</description>
9525              <bitRange>[6:4]</bitRange>
9526              <access>read-write</access>
9527              <enumeratedValues>
9528                <enumeratedValue>
9529                  <name>VDDD</name>
9530                  <description>Select VDDD</description>
9531                  <value>0</value>
9532                </enumeratedValue>
9533                <enumeratedValue>
9534                  <name>AMUXBUSA</name>
9535                  <description>Select AMUXBUSA (VDDD branch)</description>
9536                  <value>1</value>
9537                </enumeratedValue>
9538                <enumeratedValue>
9539                  <name>VBACKUP</name>
9540                  <description>Selects VBACKUP</description>
9541                  <value>2</value>
9542                </enumeratedValue>
9543                <enumeratedValue>
9544                  <name>VDDIO</name>
9545                  <description>N/A</description>
9546                  <value>3</value>
9547                </enumeratedValue>
9548                <enumeratedValue>
9549                  <name>AMUXBUSB</name>
9550                  <description>Select AMUXBUSB (VDDD branch)</description>
9551                  <value>4</value>
9552                </enumeratedValue>
9553              </enumeratedValues>
9554            </field>
9555            <field>
9556              <name>HVLVD1_EN</name>
9557              <description>Enable HVLVD1 voltage monitor.  HVLVD1 does not function during DEEPSLEEP, but it automatically returns to its configured setting after DEEPSLEEP wakeup.  Do not change other HVLVD1 settings when enabled.</description>
9558              <bitRange>[7:7]</bitRange>
9559              <access>read-write</access>
9560            </field>
9561            <field>
9562              <name>HVLVD1_TRIPSEL_HT</name>
9563              <description>N/A</description>
9564              <bitRange>[12:8]</bitRange>
9565              <access>read-write</access>
9566            </field>
9567            <field>
9568              <name>HVLVD1_DPSLP_EN_HT</name>
9569              <description>Keep HVLVD1 voltage monitor enabled during DEEPSLEEP mode.  This field is only used when HVLVD1_EN_HT==1.</description>
9570              <bitRange>[14:14]</bitRange>
9571              <access>read-write</access>
9572            </field>
9573            <field>
9574              <name>HVLVD1_EN_HT</name>
9575              <description>Enable HVLVD1 voltage monitor.  This detector monitors vddd only.  Do not change other HVLVD1 settings when enabled.</description>
9576              <bitRange>[15:15]</bitRange>
9577              <access>read-write</access>
9578            </field>
9579            <field>
9580              <name>HVLVD1_EDGE_SEL</name>
9581              <description>Sets which edge(s) will trigger an action when the threshold is crossed.</description>
9582              <bitRange>[17:16]</bitRange>
9583              <access>read-write</access>
9584              <enumeratedValues>
9585                <enumeratedValue>
9586                  <name>DISABLE</name>
9587                  <description>Disabled</description>
9588                  <value>0</value>
9589                </enumeratedValue>
9590                <enumeratedValue>
9591                  <name>RISING</name>
9592                  <description>Rising edge</description>
9593                  <value>1</value>
9594                </enumeratedValue>
9595                <enumeratedValue>
9596                  <name>FALLING</name>
9597                  <description>Falling edge</description>
9598                  <value>2</value>
9599                </enumeratedValue>
9600                <enumeratedValue>
9601                  <name>BOTH</name>
9602                  <description>Both rising and falling edges</description>
9603                  <value>3</value>
9604                </enumeratedValue>
9605              </enumeratedValues>
9606            </field>
9607            <field>
9608              <name>HVLVD1_ACTION</name>
9609              <description>Action taken when the threshold is crossed in the programmed directions(s)</description>
9610              <bitRange>[18:18]</bitRange>
9611              <access>read-write</access>
9612              <enumeratedValues>
9613                <enumeratedValue>
9614                  <name>INTERRUPT</name>
9615                  <description>Generate an interrupt</description>
9616                  <value>0</value>
9617                </enumeratedValue>
9618                <enumeratedValue>
9619                  <name>FAULT</name>
9620                  <description>N/A</description>
9621                  <value>1</value>
9622                </enumeratedValue>
9623              </enumeratedValues>
9624            </field>
9625          </fields>
9626        </register>
9627        <register>
9628          <name>PWR_LVD_CTL2</name>
9629          <description>High Voltage / Low Voltage Detector (HVLVD) Configuration Register #2</description>
9630          <addressOffset>0x1024</addressOffset>
9631          <size>32</size>
9632          <access>read-write</access>
9633          <resetValue>0x0</resetValue>
9634          <resetMask>0x7DF00</resetMask>
9635          <fields>
9636            <field>
9637              <name>HVLVD2_TRIPSEL_HT</name>
9638              <description>N/A</description>
9639              <bitRange>[12:8]</bitRange>
9640              <access>read-write</access>
9641            </field>
9642            <field>
9643              <name>HVLVD2_DPSLP_EN_HT</name>
9644              <description>Keep HVLVD2 voltage monitor enabled during DEEPSLEEP mode.  This field is only used when HVLVD1_EN_HT==1.</description>
9645              <bitRange>[14:14]</bitRange>
9646              <access>read-write</access>
9647            </field>
9648            <field>
9649              <name>HVLVD2_EN_HT</name>
9650              <description>Enable HVLVD2 voltage monitor.  This detector monitors vddd only.  Do not change other HVLVD2 settings when enabled.</description>
9651              <bitRange>[15:15]</bitRange>
9652              <access>read-write</access>
9653            </field>
9654            <field>
9655              <name>HVLVD2_EDGE_SEL</name>
9656              <description>Sets which edge(s) will trigger an action when the threshold is crossed.</description>
9657              <bitRange>[17:16]</bitRange>
9658              <access>read-write</access>
9659              <enumeratedValues>
9660                <enumeratedValue>
9661                  <name>DISABLE</name>
9662                  <description>Disabled</description>
9663                  <value>0</value>
9664                </enumeratedValue>
9665                <enumeratedValue>
9666                  <name>RISING</name>
9667                  <description>Rising edge</description>
9668                  <value>1</value>
9669                </enumeratedValue>
9670                <enumeratedValue>
9671                  <name>FALLING</name>
9672                  <description>Falling edge</description>
9673                  <value>2</value>
9674                </enumeratedValue>
9675                <enumeratedValue>
9676                  <name>BOTH</name>
9677                  <description>Both rising and falling edges</description>
9678                  <value>3</value>
9679                </enumeratedValue>
9680              </enumeratedValues>
9681            </field>
9682            <field>
9683              <name>HVLVD2_ACTION</name>
9684              <description>Action taken when the threshold is crossed in the programmed directions(s)</description>
9685              <bitRange>[18:18]</bitRange>
9686              <access>read-write</access>
9687              <enumeratedValues>
9688                <enumeratedValue>
9689                  <name>INTERRUPT</name>
9690                  <description>Generate an interrupt</description>
9691                  <value>0</value>
9692                </enumeratedValue>
9693                <enumeratedValue>
9694                  <name>FAULT</name>
9695                  <description>N/A</description>
9696                  <value>1</value>
9697                </enumeratedValue>
9698              </enumeratedValues>
9699            </field>
9700          </fields>
9701        </register>
9702        <register>
9703          <name>PWR_REGHC_CTL</name>
9704          <description>REGHC Control Register</description>
9705          <addressOffset>0x1028</addressOffset>
9706          <size>32</size>
9707          <access>read-write</access>
9708          <resetValue>0x40000104</resetValue>
9709          <resetMask>0xFFFF7DFD</resetMask>
9710          <fields>
9711            <field>
9712              <name>REGHC_MODE</name>
9713              <description>REGHC control mode:
97140: external transistor connected,
97151: external PMIC connected</description>
9716              <bitRange>[0:0]</bitRange>
9717              <access>read-write</access>
9718            </field>
9719            <field>
9720              <name>REGHC_PMIC_DRV_VOUT</name>
9721              <description>Setting for DRV_VOUT pin for PMIC mode.  See REGHC_VADJ for calculation of vadj.
97222'b00: DRV_VOUT=vccd*0.9/vadj;
97232'b01: DRV_VOUT=vccd*0.8/vadj;
97242'b10: DRV_VOUT=vccd*0.6/vadj;
97252'b11: DRV_VOUT=vccd</description>
9726              <bitRange>[3:2]</bitRange>
9727              <access>read-write</access>
9728            </field>
9729            <field>
9730              <name>REGHC_VADJ</name>
9731              <description>Regulator output trim according to the formula vadj=(1.020V + REGHC_VADJ*0.005V).  The default is 1.1V.  For transistor mode, REGHC will dynamically adjust DRV_VOUT so the supply targets the vadj voltage.  For PMIC mode, see REGHC_PMIC_DRV_VOUT.</description>
9732              <bitRange>[8:4]</bitRange>
9733              <access>read-write</access>
9734            </field>
9735            <field>
9736              <name>REGHC_PMIC_USE_LINREG</name>
9737              <description>For REGHC external PMIC mode, controls whether hardware sequencer keeps the internal Active Linear Regulator enabled to improve supply supervision of vccd.  When using this feature, if the PMIC fails to keep vccd above the internal regulator target, then the internal regulator will attempt to recover vccd.  If the regulator current is too high, the regulator triggers an over-current detector (OCD) reset.
97380: Internal Active Linear Regulator disabled after PMIC enabled.  OCD is disabled.;
97391: Internal Active Linear Regulator kept enabled.  See datasheet for minimum PMIC vccd input to prevent OCD.</description>
9740              <bitRange>[10:10]</bitRange>
9741              <access>read-write</access>
9742            </field>
9743            <field>
9744              <name>REGHC_PMIC_USE_RADJ</name>
9745              <description>Controls whether hardware sequencer enables reset voltage adjustment circuit when enabling a PMIC.</description>
9746              <bitRange>[11:11]</bitRange>
9747              <access>read-write</access>
9748            </field>
9749            <field>
9750              <name>REGHC_PMIC_RADJ</name>
9751              <description>Reset voltage adjustment for PMIC as a factor (Vfbk/Vref) where Vfbk is the feedback voltage and Vref is the PMIC internal reference.  The reset voltage adjustment circuit is enabled by the hardware sequencer if REGHC_PMIC_USE_RADJ=1.  PMIC have Vref of 0.8V or 0.9V, and the resulting reset voltage (Vreset) are precalculated in the table below:
97523'b000: Vfbk/Vref=1.0000, Vreset=.800V@(Vref=0.8V), .900V@(Vref=0.9V);
97533'b001: Vfbk/Vref=1.0556, Vreset=.844V@(Vref=0.8V), .950V@(Vref=0.9V);
97543'b010: Vfbk/Vref=1.1111, Vreset=.889V@(Vref=0.8V), 1.000V@(Vref=0.9V);
97553'b011: Vfbk/Vref=1.1250, Vreset=.900V@(Vref=0.8V), 1.013V@(Vref=0.9V);
97563'b100: Vfbk/Vref=1.1667, Vreset=.933V@(Vref=0.8V), 1.050V@(Vref=0.9V);
97573'b101: Vfbk/Vref=1.1875, Vreset=.950V@(Vref=0.8V), 1.069V@(Vref=0.9V);
97583'b110: Vfbk/Vref=1.2500, Vreset=1.000V@(Vref=0.8V), 1.125V@(Vref=0.9V);
97593'b111: Vfbk/Vref=1.3125, Vreset=1.050V@(Vref=0.8V), 1.181V@(Vref=0.9V);</description>
9760              <bitRange>[14:12]</bitRange>
9761              <access>read-write</access>
9762            </field>
9763            <field>
9764              <name>REGHC_PMIC_CTL_OUTEN</name>
9765              <description>Output enable for PMIC enable pin.  Set this bit high to enable the driver on this pin.</description>
9766              <bitRange>[16:16]</bitRange>
9767              <access>read-write</access>
9768            </field>
9769            <field>
9770              <name>REGHC_PMIC_CTL_POLARITY</name>
9771              <description>Polarity used to enable the PMIC.  The sequencer uses REGHC_PMIC_CTL_POLARITY to enable the PMIC, and it uses the complement to disable the PMIC.</description>
9772              <bitRange>[17:17]</bitRange>
9773              <access>read-write</access>
9774            </field>
9775            <field>
9776              <name>REGHC_PMIC_STATUS_INEN</name>
9777              <description>Input buffer enable for PMIC status input.  Set this bit high to enable the input receiver.</description>
9778              <bitRange>[18:18]</bitRange>
9779              <access>read-write</access>
9780            </field>
9781            <field>
9782              <name>REGHC_PMIC_STATUS_POLARITY</name>
9783              <description>The polarity used to trigger a reset action based on the PMIC status input.  The reset system triggers a reset when the unmasked PMIC status matches this value.</description>
9784              <bitRange>[19:19]</bitRange>
9785              <access>read-write</access>
9786            </field>
9787            <field>
9788              <name>REGHC_PMIC_STATUS_WAIT</name>
9789              <description>Wait count in 4us steps after PMIC status ok.  This is used by the hardware sequencer to allow additional settling time before disabling the internal regulator.  The LSB is 32 IMO periods which results in a nominal LSB step of 4us.</description>
9790              <bitRange>[29:20]</bitRange>
9791              <access>read-write</access>
9792            </field>
9793            <field>
9794              <name>REGHC_TRANS_USE_OCD</name>
9795              <description>N/A</description>
9796              <bitRange>[30:30]</bitRange>
9797              <access>read-write</access>
9798            </field>
9799            <field>
9800              <name>REGHC_CONFIGURED</name>
9801              <description>Indicates the REGHC has been configured.  This is used to know if REGHC should be enabled in response to a debug power up request.  Do not change REGHC settings after this bit is set high.</description>
9802              <bitRange>[31:31]</bitRange>
9803              <access>read-write</access>
9804            </field>
9805          </fields>
9806        </register>
9807        <register>
9808          <name>PWR_REGHC_STATUS</name>
9809          <description>REGHC Status Register</description>
9810          <addressOffset>0x102C</addressOffset>
9811          <size>32</size>
9812          <access>read-only</access>
9813          <resetValue>0x0</resetValue>
9814          <resetMask>0x80001307</resetMask>
9815          <fields>
9816            <field>
9817              <name>REGHC_ENABLED</name>
9818              <description>Indicates the state of the REGHC enable/disable sequencer.  This bit is only valid when REGHC_SEQ_BUSY==0.
98190: REGHC sequencer indicates REGHC is disabled.
98201: REGHC sequencer indicates REGHC is enabled.</description>
9821              <bitRange>[0:0]</bitRange>
9822              <access>read-only</access>
9823            </field>
9824            <field>
9825              <name>REGHC_OCD_OK</name>
9826              <description>Indicates the over-current detector is operating and the current drawn from REGHC is within limits.  OCD is only a choice for transistor mode, and it is disabled for PMIC mode.
98270: Current measurement exceeds limit or detector is OFF,
98281: Current measurement within limit</description>
9829              <bitRange>[1:1]</bitRange>
9830              <access>read-only</access>
9831            </field>
9832            <field>
9833              <name>REGHC_CKT_OK</name>
9834              <description>Indicates the REGHC circuit is enabled and operating.  It does not indicate that the voltage and current are within required limits for robust operation.
98350: REGHC circuit is not ready.  This can occur if the REGHC circuit is disabled or if it was recently enabled.
98361: REGHC circuit is enabled and operating.</description>
9837              <bitRange>[2:2]</bitRange>
9838              <access>read-only</access>
9839            </field>
9840            <field>
9841              <name>REGHC_UV_OUT</name>
9842              <description>N/A</description>
9843              <bitRange>[8:8]</bitRange>
9844              <access>read-only</access>
9845            </field>
9846            <field>
9847              <name>REGHC_OV_OUT</name>
9848              <description>N/A</description>
9849              <bitRange>[9:9]</bitRange>
9850              <access>read-only</access>
9851            </field>
9852            <field>
9853              <name>REGHC_PMIC_STATUS_OK</name>
9854              <description>Indicates the PMIC status is ok.  This includes polarity adjustment according to REGHC_PMIC_STATUS_POLARITY.
98550: PMIC status is not ok or PMIC input buffer is disabled (REGHC_PMIC_STATUS_INEN==0);
98561: PMIC status input buffer is enabled and indicates ok</description>
9857              <bitRange>[12:12]</bitRange>
9858              <access>read-only</access>
9859            </field>
9860            <field>
9861              <name>REGHC_SEQ_BUSY</name>
9862              <description>Indicates the REGHC enable/disable sequencer is busy transitioning to/from REGHC.
98630: Sequencer is not busy;
98641: Sequencer is busy either enabling or disabling REGHC.</description>
9865              <bitRange>[31:31]</bitRange>
9866              <access>read-only</access>
9867            </field>
9868          </fields>
9869        </register>
9870        <register>
9871          <name>PWR_REGHC_CTL2</name>
9872          <description>REGHC Control Register 2</description>
9873          <addressOffset>0x1030</addressOffset>
9874          <size>32</size>
9875          <access>read-write</access>
9876          <resetValue>0x0</resetValue>
9877          <resetMask>0x800000FF</resetMask>
9878          <fields>
9879            <field>
9880              <name>REGHC_PMIC_STATUS_TIMEOUT</name>
9881              <description>Timeout while waiting for REGHC_PMIC_STATUS_OK==1 when switching to PMIC.
98820: disables timeout.
9883&gt;0: enables timeout of REGHC_PMIC_STATUS_TIMEOUT*128us (nominal, clocked by IMO).  Timeout expiration triggers reset.</description>
9884              <bitRange>[7:0]</bitRange>
9885              <access>read-write</access>
9886            </field>
9887            <field>
9888              <name>REGHC_EN</name>
9889              <description>Enable REGHC.  This bit will not set if REGHC_CONFIGURED==0.  Use PWR_REGHC_STATUS.ENABLED to know the actual status of REGHC.  It will differ from this bit in the following cases:
9890A) Do not enter DEEPSLEEP while the sequencer is busy (see PWR_REGHC_STATUS.REGHC_SEQ_BUSY).  The hardware sequencer disables REGHC during DEEPSLEEP entry and enables it upon wakeup.
9891B) The debugger requests the chip remain powered up.  Hardware prevents REGHC from disabling when this bit is cleared.  Hardware does not automatically enable REGHC in response to debugger power up request.  If this bit is low when the debugger deasserts the power up request, the hardware sequencer will disable REGHC.</description>
9892              <bitRange>[31:31]</bitRange>
9893              <access>read-write</access>
9894            </field>
9895          </fields>
9896        </register>
9897        <register>
9898          <name>PWR_PMIC_CTL</name>
9899          <description>PMIC Control Register</description>
9900          <addressOffset>0x10C0</addressOffset>
9901          <size>32</size>
9902          <access>read-write</access>
9903          <resetValue>0x104</resetValue>
9904          <resetMask>0xBFFF85FC</resetMask>
9905          <fields>
9906            <field>
9907              <name>PMIC_VREF</name>
9908              <description>PMIC reference voltage setting.  This selects the scaling factor used to generate the output voltage (vout) given the feedback voltage (vfb) for the chosen PMIC.  For a PMIC that compares vfb to an internal reference voltage (vref) according to the formula vout=vref/vfb, select that vref below.  For a PMIC that contains an internal resistor divider and expects an unscaled feedback voltage, use the 'No scaling' choice.
99092'b00: Scale for vref=0.9V, use PMIC_VADJ to set the vccd target;
99102'b01: Scale for vref=0.8V, use PMIC_VADJ to set the vccd target;
99112'b10: Scale for vref=0.6V, use PMIC_VADJ to set the vccd target;
99122'b11: No scaling, PMIC_VADJ has no effect</description>
9913              <bitRange>[3:2]</bitRange>
9914              <access>read-write</access>
9915            </field>
9916            <field>
9917              <name>PMIC_VADJ</name>
9918              <description>Voltage adjustment output setting.  The lookup table in this field requires the proper setting in PMIC_VREF for the chosen PMIC.  This field has no effect when PMIC_VREF selects no scaling.  The feedback tap point is at a vccd pad inside the chip, so the voltage may be a little higher at the PMIC output.
99190x03: 1.040V, 0x04: 1.049V,
99200x05: 1.057V, 0x06: 1.066V,
99210x07: 1.074V, 0x08: 1.083V,
99220x09: 1.091V, 0x0A: 1.099V,
99230x0B: 1.108V, 0x0C: 1.116V,
99240x0D: 1.125V, 0x0E: 1.133V,
99250x0F: 1.142V, 0x10: 1.150V,
99260x11: 1.158V, 0x12: 1.167V,
99270x13: 1.175V, 0x14: 1.184V,
99280x15: 1.192V, 0x16: 1.201V,
99290x17: 1.209V, 0x18: 1.218V,
99300x19: 1.226V, 0x1A: 1.234V,
99310x1B: 1.243V, 0x1C: 1.251V,
9932others: Illegal.  Behavior is undefined.</description>
9933              <bitRange>[8:4]</bitRange>
9934              <access>read-write</access>
9935            </field>
9936            <field>
9937              <name>PMIC_USE_LINREG</name>
9938              <description>Controls whether hardware sequencer keeps the internal Active Linear Regulator enabled to improve supply supervision of vccd.  When using this feature, if the PMIC fails to keep vccd above the internal regulator target, then the internal regulator will attempt to recover vccd.  If the regulator current is too high, the regulator triggers an over-current detector (OCD) reset.
99390: Internal Active Linear Regulator disabled after PMIC enabled.  OCD is disabled.;
99401: Internal Active Linear Regulator kept enabled.  See datasheet for minimum PMIC vccd input to prevent OCD.</description>
9941              <bitRange>[10:10]</bitRange>
9942              <access>read-write</access>
9943            </field>
9944            <field>
9945              <name>PMIC_VADJ_BUF_EN</name>
9946              <description>Analog buffer enable on voltage adjust output.  Write this bit depending on the type of PMIC connected:
99470: Bypass buffer.  This connects the resistor divider directly to the output pin.  Use this setting for a PMIC with a high-impedance feedback input, such as those that support a resistor divider on the PCB.  This setting can also be used with a low-impedance PMIC with PMIC_VREF=2'b11 (no scaling).
99481: Use analog buffer.  This enables an analog buffer between the resistor divider output and the pin.  The buffer can drive a resistor divider on the PCB that feeds into the PMIC feedback input.  This allows targeting a different PMIC reference voltage from PMIC_VREF choices, while still supporting voltage adjustment using the internal divider.</description>
9949              <bitRange>[15:15]</bitRange>
9950              <access>read-write</access>
9951            </field>
9952            <field>
9953              <name>PMIC_CTL_OUTEN</name>
9954              <description>Output enable for PMIC enable pin.  Set this bit high to enable the driver on this pin.</description>
9955              <bitRange>[16:16]</bitRange>
9956              <access>read-write</access>
9957            </field>
9958            <field>
9959              <name>PMIC_CTL_POLARITY</name>
9960              <description>Polarity used to enable the PMIC.  The sequencer uses PMIC_CTL_POLARITY to enable the PMIC, and it uses the complement to disable the PMIC.</description>
9961              <bitRange>[17:17]</bitRange>
9962              <access>read-write</access>
9963            </field>
9964            <field>
9965              <name>PMIC_STATUS_INEN</name>
9966              <description>Input buffer enable for PMIC status input.  Set this bit high to enable the input receiver.</description>
9967              <bitRange>[18:18]</bitRange>
9968              <access>read-write</access>
9969            </field>
9970            <field>
9971              <name>PMIC_STATUS_POLARITY</name>
9972              <description>The polarity used to trigger a reset action based on the PMIC status input.  The reset system triggers a reset when the unmasked PMIC status matches this value.</description>
9973              <bitRange>[19:19]</bitRange>
9974              <access>read-write</access>
9975            </field>
9976            <field>
9977              <name>PMIC_STATUS_WAIT</name>
9978              <description>Wait count in 4us steps after PMIC status ok.  This is used by the hardware sequencer to allow additional settling time before disabling the internal regulator.  The LSB is 32 IMO periods which results in a nominal LSB step of 4us.</description>
9979              <bitRange>[29:20]</bitRange>
9980              <access>read-write</access>
9981            </field>
9982            <field>
9983              <name>PMIC_CONFIGURED</name>
9984              <description>Indicates the PMIC has been configured.  This is used to know if PMIC should be enabled in response to a debug power up request.  Do not change PMIC settings after this bit is set high.</description>
9985              <bitRange>[31:31]</bitRange>
9986              <access>read-write</access>
9987            </field>
9988          </fields>
9989        </register>
9990        <register>
9991          <name>PWR_PMIC_STATUS</name>
9992          <description>PMIC Status Register</description>
9993          <addressOffset>0x10C4</addressOffset>
9994          <size>32</size>
9995          <access>read-only</access>
9996          <resetValue>0x0</resetValue>
9997          <resetMask>0x80001001</resetMask>
9998          <fields>
9999            <field>
10000              <name>PMIC_ENABLED</name>
10001              <description>Indicates the state of the PMIC enable/disable sequencer.  This bit is only valid when PMIC_SEQ_BUSY==0.
100020: PMIC sequencer indicates PMIC is disabled.
100031: PMIC sequencer indicates PMIC is enabled.</description>
10004              <bitRange>[0:0]</bitRange>
10005              <access>read-only</access>
10006            </field>
10007            <field>
10008              <name>PMIC_STATUS_OK</name>
10009              <description>Indicates the PMIC status is ok.  This includes polarity adjustment according to PMIC_STATUS_POLARITY.
100100: PMIC status is not ok or PMIC input buffer is disabled (PMIC_STATUS_INEN==0);
100111: PMIC status input buffer is enabled and indicates ok</description>
10012              <bitRange>[12:12]</bitRange>
10013              <access>read-only</access>
10014            </field>
10015            <field>
10016              <name>PMIC_SEQ_BUSY</name>
10017              <description>Indicates the PMIC enable/disable sequencer is busy transitioning to/from PMIC.
100180: Sequencer is not busy;
100191: Sequencer is busy either enabling or disabling PMIC.</description>
10020              <bitRange>[31:31]</bitRange>
10021              <access>read-only</access>
10022            </field>
10023          </fields>
10024        </register>
10025        <register>
10026          <name>PWR_PMIC_CTL2</name>
10027          <description>PMIC Control Register 2</description>
10028          <addressOffset>0x10C8</addressOffset>
10029          <size>32</size>
10030          <access>read-write</access>
10031          <resetValue>0x0</resetValue>
10032          <resetMask>0x800000FF</resetMask>
10033          <fields>
10034            <field>
10035              <name>PMIC_STATUS_TIMEOUT</name>
10036              <description>Timeout while waiting for PMIC_STATUS_OK==1 when switching to PMIC.
100370: disables timeout.  Do not change this register after setting PWR_PMIC_CTL.PMIC_CONFIGURED.
10038&gt;0: enables timeout of PMIC_STATUS_TIMEOUT*128us (nominal, clocked by IMO).  Timeout expiration triggers reset.</description>
10039              <bitRange>[7:0]</bitRange>
10040              <access>read-write</access>
10041            </field>
10042            <field>
10043              <name>PMIC_EN</name>
10044              <description>Enable PMIC.  This bit will not set if PMIC_CONFIGURED==0.  Use PWR_PMIC_STATUS.ENABLED to know the actual status of PMIC.  It will differ from this bit in the following cases:
10045A) Do not enter DEEPSLEEP while the sequencer is busy (see PWR_PMIC_STATUS.PMIC_SEQ_BUSY).  The hardware sequencer disables PMIC during DEEPSLEEP entry and enables it upon wakeup.
10046B) The debugger requests the chip remain powered up.  Hardware prevents PMIC from disabling when this bit is cleared.  Hardware does not automatically enable PMIC in response to debugger power up request.  If this bit is low when the debugger deasserts the power up request, the hardware sequencer will disable PMIC.</description>
10047              <bitRange>[31:31]</bitRange>
10048              <access>read-write</access>
10049            </field>
10050          </fields>
10051        </register>
10052        <register>
10053          <name>PWR_PMIC_CTL4</name>
10054          <description>PMIC Control Register 4</description>
10055          <addressOffset>0x10D0</addressOffset>
10056          <size>32</size>
10057          <access>read-write</access>
10058          <resetValue>0x0</resetValue>
10059          <resetMask>0xC0000000</resetMask>
10060          <fields>
10061            <field>
10062              <name>PMIC_VADJ_DIS</name>
10063              <description>Disables the VADJ circuitry.  This can be used to decrease current consumption if the entire feedback network is outside the device.
100640: Device generates VADJ when PMIC is enabled.  This allows the feedback loop to compensate for voltage drops in the PCB and package.
100651: Device does not generate VADJ, and it must not be part of the PMIC feedback loop.  This reduces current by turning off the internal resistor divider that generates VADJ.</description>
10066              <bitRange>[30:30]</bitRange>
10067              <access>read-write</access>
10068            </field>
10069            <field>
10070              <name>PMIC_DPSLP</name>
10071              <description>Configures PMIC behavior during DEEPSLEEP.
100720: Device operates from internal regulators during DEEPSLEEP.  If PMIC is enabled at the beginning of the DEEPSLEEP transition, hardware changes to the internal regulators and disables the PMIC.
100731: DEEPSLEEP transition does not change PMIC enable.</description>
10074              <bitRange>[31:31]</bitRange>
10075              <access>read-write</access>
10076            </field>
10077          </fields>
10078        </register>
10079        <register>
10080          <dim>16</dim>
10081          <dimIncrement>4</dimIncrement>
10082          <name>CLK_PATH_SELECT[%s]</name>
10083          <description>Clock Path Select Register</description>
10084          <addressOffset>0x1200</addressOffset>
10085          <size>32</size>
10086          <access>read-write</access>
10087          <resetValue>0x0</resetValue>
10088          <resetMask>0x7</resetMask>
10089          <fields>
10090            <field>
10091              <name>PATH_MUX</name>
10092              <description>Selects a source for clock PATH&lt;i&gt;.  Note that not all products support all clock sources.  Selecting a clock source that is not supported will result in undefined behavior.  It takes four cycles of the originally selected clock to switch away from it.  Do not disable the original clock during this time.</description>
10093              <bitRange>[2:0]</bitRange>
10094              <access>read-write</access>
10095              <enumeratedValues>
10096                <enumeratedValue>
10097                  <name>IMO</name>
10098                  <description>IMO - Internal R/C Oscillator</description>
10099                  <value>0</value>
10100                </enumeratedValue>
10101                <enumeratedValue>
10102                  <name>EXTCLK</name>
10103                  <description>EXTCLK - External Clock Pin</description>
10104                  <value>1</value>
10105                </enumeratedValue>
10106                <enumeratedValue>
10107                  <name>ECO</name>
10108                  <description>ECO - External-Crystal Oscillator</description>
10109                  <value>2</value>
10110                </enumeratedValue>
10111                <enumeratedValue>
10112                  <name>ALTHF</name>
10113                  <description>ALTHF - Alternate High-Frequency clock input (product-specific clock)</description>
10114                  <value>3</value>
10115                </enumeratedValue>
10116                <enumeratedValue>
10117                  <name>DSI_MUX</name>
10118                  <description>DSI_MUX - Output of DSI mux for this path.  Using a DSI source directly as root of HFCLK will result in undefined behavior.</description>
10119                  <value>4</value>
10120                </enumeratedValue>
10121                <enumeratedValue>
10122                  <name>LPECO</name>
10123                  <description>LPECO - Low-Power External-Crystal Oscillator</description>
10124                  <value>5</value>
10125                </enumeratedValue>
10126                <enumeratedValue>
10127                  <name>IHO</name>
10128                  <description>IHO - Internal High-speed Oscillator</description>
10129                  <value>6</value>
10130                </enumeratedValue>
10131              </enumeratedValues>
10132            </field>
10133          </fields>
10134        </register>
10135        <register>
10136          <dim>16</dim>
10137          <dimIncrement>4</dimIncrement>
10138          <name>CLK_ROOT_SELECT[%s]</name>
10139          <description>Clock Root Select Register</description>
10140          <addressOffset>0x1240</addressOffset>
10141          <size>32</size>
10142          <access>read-write</access>
10143          <resetValue>0x0</resetValue>
10144          <resetMask>0x8000013F</resetMask>
10145          <fields>
10146            <field>
10147              <name>ROOT_MUX</name>
10148              <description>Selects a clock path for HFCLK&lt;k&gt; and SRSS DSI input &lt;k&gt;.  The output of this mux goes to the direct mux (see CLK_DIRECT_SELECT).  Use CLK_SELECT_PATH[i] to configure the desired path.  The number of clock paths is product-specific, and selecting an unimplemented path is not supported.  Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers.  Configure the FLL using CLK_FLL_CONFIG register.  Configure a PLL using the related CLK_PLL_CONFIG[k] register.  Note that not all products support all clock sources.  Selecting a clock source that is not supported will result in undefined behavior.  It takes four cycles of the originally selected clock to switch away from it.  Do not disable the original clock during this time.</description>
10149              <bitRange>[3:0]</bitRange>
10150              <access>read-write</access>
10151              <enumeratedValues>
10152                <enumeratedValue>
10153                  <name>PATH0</name>
10154                  <description>Select PATH0</description>
10155                  <value>0</value>
10156                </enumeratedValue>
10157                <enumeratedValue>
10158                  <name>PATH1</name>
10159                  <description>Select PATH1</description>
10160                  <value>1</value>
10161                </enumeratedValue>
10162                <enumeratedValue>
10163                  <name>PATH2</name>
10164                  <description>Select PATH2</description>
10165                  <value>2</value>
10166                </enumeratedValue>
10167                <enumeratedValue>
10168                  <name>PATH3</name>
10169                  <description>Select PATH3</description>
10170                  <value>3</value>
10171                </enumeratedValue>
10172                <enumeratedValue>
10173                  <name>PATH4</name>
10174                  <description>Select PATH4</description>
10175                  <value>4</value>
10176                </enumeratedValue>
10177                <enumeratedValue>
10178                  <name>PATH5</name>
10179                  <description>Select PATH5</description>
10180                  <value>5</value>
10181                </enumeratedValue>
10182                <enumeratedValue>
10183                  <name>PATH6</name>
10184                  <description>Select PATH6</description>
10185                  <value>6</value>
10186                </enumeratedValue>
10187                <enumeratedValue>
10188                  <name>PATH7</name>
10189                  <description>Select PATH7</description>
10190                  <value>7</value>
10191                </enumeratedValue>
10192                <enumeratedValue>
10193                  <name>PATH8</name>
10194                  <description>Select PATH8</description>
10195                  <value>8</value>
10196                </enumeratedValue>
10197                <enumeratedValue>
10198                  <name>PATH9</name>
10199                  <description>Select PATH9</description>
10200                  <value>9</value>
10201                </enumeratedValue>
10202                <enumeratedValue>
10203                  <name>PATH10</name>
10204                  <description>Select PATH10</description>
10205                  <value>10</value>
10206                </enumeratedValue>
10207                <enumeratedValue>
10208                  <name>PATH11</name>
10209                  <description>Select PATH11</description>
10210                  <value>11</value>
10211                </enumeratedValue>
10212                <enumeratedValue>
10213                  <name>PATH12</name>
10214                  <description>Select PATH12</description>
10215                  <value>12</value>
10216                </enumeratedValue>
10217                <enumeratedValue>
10218                  <name>PATH13</name>
10219                  <description>Select PATH13</description>
10220                  <value>13</value>
10221                </enumeratedValue>
10222                <enumeratedValue>
10223                  <name>PATH14</name>
10224                  <description>Select PATH14</description>
10225                  <value>14</value>
10226                </enumeratedValue>
10227                <enumeratedValue>
10228                  <name>PATH15</name>
10229                  <description>Select PATH15</description>
10230                  <value>15</value>
10231                </enumeratedValue>
10232              </enumeratedValues>
10233            </field>
10234            <field>
10235              <name>ROOT_DIV</name>
10236              <description>Selects predivider value for this clock root and DSI input.  This divider is after DIRECT_MUX.  For products with DSI, the output of this mux is routed to DSI for use as a signal.  For products with clock supervision, the output of this mux is the monitored clock for CSV_HF&lt;k&gt;.</description>
10237              <bitRange>[5:4]</bitRange>
10238              <access>read-write</access>
10239              <enumeratedValues>
10240                <enumeratedValue>
10241                  <name>NO_DIV</name>
10242                  <description>Transparent mode, feed through selected clock source w/o dividing.</description>
10243                  <value>0</value>
10244                </enumeratedValue>
10245                <enumeratedValue>
10246                  <name>DIV_BY_2</name>
10247                  <description>Divide selected clock source by 2</description>
10248                  <value>1</value>
10249                </enumeratedValue>
10250                <enumeratedValue>
10251                  <name>DIV_BY_4</name>
10252                  <description>Divide selected clock source by 4</description>
10253                  <value>2</value>
10254                </enumeratedValue>
10255                <enumeratedValue>
10256                  <name>DIV_BY_8</name>
10257                  <description>Divide selected clock source by 8</description>
10258                  <value>3</value>
10259                </enumeratedValue>
10260              </enumeratedValues>
10261            </field>
10262            <field>
10263              <name>DIRECT_MUX</name>
10264              <description>Deprecated.  This field is an alias for CLK_DIRECT_SELECT.DIRECT_MUX, which is preferred for new code.</description>
10265              <bitRange>[8:8]</bitRange>
10266              <access>read-write</access>
10267              <enumeratedValues>
10268                <enumeratedValue>
10269                  <name>IMO</name>
10270                  <description>Select IMO</description>
10271                  <value>0</value>
10272                </enumeratedValue>
10273                <enumeratedValue>
10274                  <name>ROOT_MUX</name>
10275                  <description>Select ROOT_MUX selection</description>
10276                  <value>1</value>
10277                </enumeratedValue>
10278              </enumeratedValues>
10279            </field>
10280            <field>
10281              <name>ENABLE</name>
10282              <description>Enable for this clock root.  All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.</description>
10283              <bitRange>[31:31]</bitRange>
10284              <access>read-write</access>
10285            </field>
10286          </fields>
10287        </register>
10288        <register>
10289          <dim>16</dim>
10290          <dimIncrement>4</dimIncrement>
10291          <name>CLK_DIRECT_SELECT[%s]</name>
10292          <description>Clock Root Direct Select Register</description>
10293          <addressOffset>0x1280</addressOffset>
10294          <size>32</size>
10295          <access>read-write</access>
10296          <resetValue>0x0</resetValue>
10297          <resetMask>0x100</resetMask>
10298          <fields>
10299            <field>
10300              <name>DIRECT_MUX</name>
10301              <description>Direct selection mux that allows IMO to bypass most of the clock mux structure.    For products with multiple regulators, this mux can be used to reduce current without requiring significant reconfiguration of the clocking network.  The default value of HFCLK&lt;0&gt;==ROOT_MUX, and the default value for other clock trees is product-specific.</description>
10302              <bitRange>[8:8]</bitRange>
10303              <access>read-write</access>
10304              <enumeratedValues>
10305                <enumeratedValue>
10306                  <name>IMO</name>
10307                  <description>Select IMO</description>
10308                  <value>0</value>
10309                </enumeratedValue>
10310                <enumeratedValue>
10311                  <name>ROOT_MUX</name>
10312                  <description>Select ROOT_MUX selection</description>
10313                  <value>1</value>
10314                </enumeratedValue>
10315              </enumeratedValues>
10316            </field>
10317          </fields>
10318        </register>
10319        <cluster>
10320          <name>CSV_HF</name>
10321          <description>Clock Supervisor (CSV) registers for Root clocks</description>
10322          <headerStructName>CSV_HF</headerStructName>
10323          <addressOffset>0x00001400</addressOffset>
10324          <cluster>
10325            <dim>16</dim>
10326            <dimIncrement>16</dimIncrement>
10327            <name>CSV[%s]</name>
10328            <description>Active domain Clock Supervisor (CSV) registers</description>
10329            <headerStructName>CSV_HF_CSV</headerStructName>
10330            <addressOffset>0x00000000</addressOffset>
10331            <register>
10332              <name>REF_CTL</name>
10333              <description>Clock Supervision Reference Control</description>
10334              <addressOffset>0x0</addressOffset>
10335              <size>32</size>
10336              <access>read-write</access>
10337              <resetValue>0x0</resetValue>
10338              <resetMask>0xC000FFFF</resetMask>
10339              <fields>
10340                <field>
10341                  <name>STARTUP</name>
10342                  <description>Startup delay time -1 (in reference clock cycles), after enable or DeepSleep wakeup, from reference clock start to monitored clock start.
10343At a minimum (both clocks running): STARTUP &gt;= (PERIOD +3) * FREQ_RATIO - UPPER, with FREQ_RATIO = (Reference frequency / Monitored frequency)
10344On top of that the actual clock startup delay and the margin for accuracy of both clocks must be added.</description>
10345                  <bitRange>[15:0]</bitRange>
10346                  <access>read-write</access>
10347                </field>
10348                <field>
10349                  <name>CSV_ACTION</name>
10350                  <description>Specifies the action taken when an anomaly is detected on the monitored clock.  CSV in DeepSleep domain always do a Fault report (which also wakes up the system).</description>
10351                  <bitRange>[30:30]</bitRange>
10352                  <access>read-write</access>
10353                  <enumeratedValues>
10354                    <enumeratedValue>
10355                      <name>FAULT</name>
10356                      <description>Generate a fault</description>
10357                      <value>0</value>
10358                    </enumeratedValue>
10359                    <enumeratedValue>
10360                      <name>RESET</name>
10361                      <description>Cause a power reset. This should only be used for clk_hf0.</description>
10362                      <value>1</value>
10363                    </enumeratedValue>
10364                  </enumeratedValues>
10365                </field>
10366                <field>
10367                  <name>CSV_EN</name>
10368                  <description>Enables clock supervision, both frequency and loss.
10369CSV in Active domain: Clock supervision is reset during DeepSleep and Hibernate modes.  When enabled it begins operating automatically after a DeepSleep wakeup, but it must be reconfigured after Hibernate wakeup.
10370CSV in DeepSleep domain: Clock supervision is reset during Hibernate mode.  It must be reconfigured after Hibernate wakeup.
10371
10372A CSV error detection is reported to the Fault structure, or instead it can generate a power reset.</description>
10373                  <bitRange>[31:31]</bitRange>
10374                  <access>read-write</access>
10375                </field>
10376              </fields>
10377            </register>
10378            <register>
10379              <name>REF_LIMIT</name>
10380              <description>Clock Supervision Reference Limits</description>
10381              <addressOffset>0x4</addressOffset>
10382              <size>32</size>
10383              <access>read-write</access>
10384              <resetValue>0x0</resetValue>
10385              <resetMask>0xFFFFFFFF</resetMask>
10386              <fields>
10387                <field>
10388                  <name>LOWER</name>
10389                  <description>Cycle time lower limit.  Set the lower limit -1, in reference clock cycles, before the next monitored clock event is allowed to happen.  If a monitored clock event happens before this limit is reached a CSV error is detected.
10390LOWER must be at least 1 less than UPPER. In case the clocks are asynchronous LOWER must be at least 3 less than UPPER.</description>
10391                  <bitRange>[15:0]</bitRange>
10392                  <access>read-write</access>
10393                </field>
10394                <field>
10395                  <name>UPPER</name>
10396                  <description>Cycle time upper limit.  Set the upper limit -1, in reference clock cycles, before (or same time) the next monitored clock event must happen.  If a monitored clock event does not happen before this limit is reached, or does not happen at all (clock loss), a CSV error is detected.</description>
10397                  <bitRange>[31:16]</bitRange>
10398                  <access>read-write</access>
10399                </field>
10400              </fields>
10401            </register>
10402            <register>
10403              <name>MON_CTL</name>
10404              <description>Clock Supervision Monitor Control</description>
10405              <addressOffset>0x8</addressOffset>
10406              <size>32</size>
10407              <access>read-write</access>
10408              <resetValue>0x0</resetValue>
10409              <resetMask>0xFFFF</resetMask>
10410              <fields>
10411                <field>
10412                  <name>PERIOD</name>
10413                  <description>Period time.  Set the Period -1, in monitored clock cycles, before the next monitored clock event happens.
10414PERIOD &lt;=  (UPPER+1) / FREQ_RATIO -1, with FREQ_RATIO = (Reference frequency / Monitored frequency)
10415In case the clocks are asynchronous: PERIOD &lt;=  UPPER / FREQ_RATIO -1
10416Additionally margin must be added for accuracy of both clocks.</description>
10417                  <bitRange>[15:0]</bitRange>
10418                  <access>read-write</access>
10419                </field>
10420              </fields>
10421            </register>
10422          </cluster>
10423        </cluster>
10424        <register>
10425          <name>CLK_SELECT</name>
10426          <description>Clock selection register</description>
10427          <addressOffset>0x1500</addressOffset>
10428          <size>32</size>
10429          <access>read-write</access>
10430          <resetValue>0x0</resetValue>
10431          <resetMask>0xFF07</resetMask>
10432          <fields>
10433            <field>
10434              <name>LFCLK_SEL</name>
10435              <description>Select source for LFCLK.  Note that not all products support all clock sources.  Selecting a clock source that is not supported will result in undefined behavior.  Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register.  It takes four cycles of the originally selected clock to switch away from it.  Do not disable the original clock during this time.</description>
10436              <bitRange>[2:0]</bitRange>
10437              <access>read-write</access>
10438              <enumeratedValues>
10439                <enumeratedValue>
10440                  <name>ILO</name>
10441                  <description>ILO - Internal Low-speed Oscillator</description>
10442                  <value>0</value>
10443                </enumeratedValue>
10444                <enumeratedValue>
10445                  <name>WCO</name>
10446                  <description>WCO - Watch-Crystal Oscillator.  Requires Backup domain to be present and properly configured (including external watch crystal, if used).</description>
10447                  <value>1</value>
10448                </enumeratedValue>
10449                <enumeratedValue>
10450                  <name>ALTLF</name>
10451                  <description>ALTLF - Alternate Low-Frequency Clock.  Capability is product-specific</description>
10452                  <value>2</value>
10453                </enumeratedValue>
10454                <enumeratedValue>
10455                  <name>PILO</name>
10456                  <description>PILO - Precision ILO, if present.</description>
10457                  <value>3</value>
10458                </enumeratedValue>
10459                <enumeratedValue>
10460                  <name>ILO1</name>
10461                  <description>ILO1 - Internal Low-speed Oscillator #1, if present.</description>
10462                  <value>4</value>
10463                </enumeratedValue>
10464                <enumeratedValue>
10465                  <name>ECO_PRESCALER</name>
10466                  <description>ECO_PRESCALER - External-Crystal Oscillator after prescaling, if present.  Does not work in DEEPSLEEP or HIBERNATE modes.  Intended for applications that operate in ACTIVE/SLEEP modes only.  This option is only valid when ECO is present in the product.</description>
10467                  <value>5</value>
10468                </enumeratedValue>
10469                <enumeratedValue>
10470                  <name>LPECO_PRESCALER</name>
10471                  <description>LPECO_PRESCALER - Low-Power External-Crystal Oscillator after prescaling, if present.  This choice works in ACTIVE/SLEEP/DEEPSLEEP modes.  This option is only valid when LPECO is present in the product.</description>
10472                  <value>6</value>
10473                </enumeratedValue>
10474              </enumeratedValues>
10475            </field>
10476            <field>
10477              <name>PUMP_SEL</name>
10478              <description>Selects clock PATH&lt;k&gt;, where k=PUMP_SEL.  The output of this mux goes to the PUMP_DIV to make PUMPCLK  Each product has a specific number of available clock paths.  Selecting a path that is not implemented on a product will result in undefined behavior.  Note that this is not a glitch free mux.</description>
10479              <bitRange>[11:8]</bitRange>
10480              <access>read-write</access>
10481            </field>
10482            <field>
10483              <name>PUMP_DIV</name>
10484              <description>Division ratio for PUMPCLK.  Uses selected PUMP_SEL clock as the source.</description>
10485              <bitRange>[14:12]</bitRange>
10486              <access>read-write</access>
10487              <enumeratedValues>
10488                <enumeratedValue>
10489                  <name>NO_DIV</name>
10490                  <description>Transparent mode, feed through selected clock source w/o dividing.</description>
10491                  <value>0</value>
10492                </enumeratedValue>
10493                <enumeratedValue>
10494                  <name>DIV_BY_2</name>
10495                  <description>Divide selected clock source by 2</description>
10496                  <value>1</value>
10497                </enumeratedValue>
10498                <enumeratedValue>
10499                  <name>DIV_BY_4</name>
10500                  <description>Divide selected clock source by 4</description>
10501                  <value>2</value>
10502                </enumeratedValue>
10503                <enumeratedValue>
10504                  <name>DIV_BY_8</name>
10505                  <description>Divide selected clock source by 8</description>
10506                  <value>3</value>
10507                </enumeratedValue>
10508                <enumeratedValue>
10509                  <name>DIV_BY_16</name>
10510                  <description>Divide selected clock source by 16</description>
10511                  <value>4</value>
10512                </enumeratedValue>
10513              </enumeratedValues>
10514            </field>
10515            <field>
10516              <name>PUMP_ENABLE</name>
10517              <description>Enable the pump clock.  PUMP_ENABLE and the PUMP_SEL mux are not glitch-free to minimize side-effects, avoid changing the PUMP_SEL and PUMP_DIV while changing PUMP_ENABLE.  To change the settings, do the following:
105181) If the pump clock is enabled, write PUMP_ENABLE=0 without changing PUMP_SEL and PUMP_DIV.
105192) Change PUMP_SEL and PUMP_DIV to desired settings with PUMP_ENABLE=0.
105203) Write PUMP_ENABLE=1 without changing PUMP_SEL and PUMP_DIV.</description>
10521              <bitRange>[15:15]</bitRange>
10522              <access>read-write</access>
10523            </field>
10524          </fields>
10525        </register>
10526        <register>
10527          <name>CLK_ILO0_CONFIG</name>
10528          <description>ILO0 Configuration</description>
10529          <addressOffset>0x1508</addressOffset>
10530          <size>32</size>
10531          <access>read-write</access>
10532          <resetValue>0x80000000</resetValue>
10533          <resetMask>0xC0000001</resetMask>
10534          <fields>
10535            <field>
10536              <name>ILO0_BACKUP</name>
10537              <description>This register indicates that ILO0 should stay enabled during XRES and HIBERNATE modes.  If backup voltage domain is implemented on the product, this bit also indicates if ILO0 should stay enabled through power-related resets on other supplies, e.g.. BOD on VDDD/VCCD.  Writes to this field are ignored unless the WDT is unlocked.  This register is reset when the backup logic resets.
105380: ILO0 turns off during XRES, HIBERNATE, and power-related resets.  ILO0 configuration and trims are reset by these events.
105391: ILO0 stays enabled, as described above.  ILO0 configuration and trims are not reset by these events.</description>
10540              <bitRange>[0:0]</bitRange>
10541              <access>read-write</access>
10542            </field>
10543            <field>
10544              <name>ILO0_MON_ENABLE</name>
10545              <description>N/A</description>
10546              <bitRange>[30:30]</bitRange>
10547              <access>read-write</access>
10548            </field>
10549            <field>
10550              <name>ENABLE</name>
10551              <description>Master enable for ILO.  Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register.
10552
10553HT-variant: This register will not clear unless PWR_CTL2.BGREF_LPMODE==0. After enabling, the first ILO0 cycle occurs within 12us and is +/-10 percent accuracy.  Thereafter, ILO0 is +/-5 percent accurate.</description>
10554              <bitRange>[31:31]</bitRange>
10555              <access>read-write</access>
10556            </field>
10557          </fields>
10558        </register>
10559        <register>
10560          <name>CLK_ILO1_CONFIG</name>
10561          <description>ILO1 Configuration</description>
10562          <addressOffset>0x150C</addressOffset>
10563          <size>32</size>
10564          <access>read-write</access>
10565          <resetValue>0x0</resetValue>
10566          <resetMask>0xC0000000</resetMask>
10567          <fields>
10568            <field>
10569              <name>ILO1_MON_ENABLE</name>
10570              <description>N/A</description>
10571              <bitRange>[30:30]</bitRange>
10572              <access>read-write</access>
10573            </field>
10574            <field>
10575              <name>ENABLE</name>
10576              <description>Master enable for ILO1.
10577
10578HT-variant: After enabling, the first ILO1 cycle occurs within 12us and is +/-10 percent accuracy.  Thereafter, ILO1 is +/-5 percent accurate.</description>
10579              <bitRange>[31:31]</bitRange>
10580              <access>read-write</access>
10581            </field>
10582          </fields>
10583        </register>
10584        <register>
10585          <name>CLK_IMO_CONFIG</name>
10586          <description>IMO Configuration</description>
10587          <addressOffset>0x1518</addressOffset>
10588          <size>32</size>
10589          <access>read-write</access>
10590          <resetValue>0x80000000</resetValue>
10591          <resetMask>0xC0000000</resetMask>
10592          <fields>
10593            <field>
10594              <name>DPSLP_ENABLE</name>
10595              <description>Enable for IMO during DEEPSLEEP.  This bit configures IMO behavior during DEEPSLEEP:
105960: IMO is automatically disabled during DEEPSLEEP and enables upon wakeup;
105971: IMO is kept enabled throughout DEEPSLEEP</description>
10598              <bitRange>[30:30]</bitRange>
10599              <access>read-write</access>
10600            </field>
10601            <field>
10602              <name>ENABLE</name>
10603              <description>Master enable for IMO oscillator.  This bit must be high at all times for all functions to work properly.  Hardware will automatically disable the IMO during HIBERNATE and XRES.  It will automatically disable during DEEPSLEEP if DPSLP_ENABLE==0.</description>
10604              <bitRange>[31:31]</bitRange>
10605              <access>read-write</access>
10606            </field>
10607          </fields>
10608        </register>
10609        <register>
10610          <name>CLK_ECO_CONFIG</name>
10611          <description>ECO Configuration Register</description>
10612          <addressOffset>0x151C</addressOffset>
10613          <size>32</size>
10614          <access>read-write</access>
10615          <resetValue>0x2</resetValue>
10616          <resetMask>0x98000002</resetMask>
10617          <fields>
10618            <field>
10619              <name>AGC_EN</name>
10620              <description>Automatic Gain Control (AGC) enable.  When set, the oscillation amplitude is controlled to the level selected by CLK_ECO_CONFIG2.ATRIM.  When low, the amplitude is not explicitly controlled and can be as high as the vddd supply.  WARNING: use care when disabling AGC because driving a crystal beyond its rated limit can permanently damage the crystal.</description>
10621              <bitRange>[1:1]</bitRange>
10622              <access>read-write</access>
10623            </field>
10624            <field>
10625              <name>ECO_DIV_DISABLE</name>
10626              <description>ECO prescaler disable command (mutually exclusive with ECO_DIV_ENABLE). SW sets this field to '1' and HW sets this field to '0'.
10627
10628HW sets ECO_DIV_DISABLE field to '0' immediately and HW sets CLK_ECO_PRESCALE.ECO_DIV_EN field to '0' immediately.</description>
10629              <bitRange>[27:27]</bitRange>
10630              <access>read-write</access>
10631            </field>
10632            <field>
10633              <name>ECO_DIV_ENABLE</name>
10634              <description>ECO prescaler enable command (mutually exclusive with ECO_DIV_DISABLE). ECO Prescaler only works in ACTIVE and SLEEP modes.  SW sets this field to '1' to enable the divider and HW sets this field to '0' to indicate that divider enabling has completed. When the divider is enabled, its integer and fractional counters are initialized to '0'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps:
106350: Disable the divider using the ECO_DIV_DISABLE field.
106361: Configure CLK_ECO_PRESCALE registers.
106372: Enable the divider using the ECO_DIV_ENABLE field.
10638
10639HW sets the ECO_DIV_ENABLE field to '0' when the enabling is performed and HW set CLK_ECO_PRESCALER.ENABLED to '1' when the enabling is performed.</description>
10640              <bitRange>[28:28]</bitRange>
10641              <access>read-write</access>
10642            </field>
10643            <field>
10644              <name>ECO_EN</name>
10645              <description>Master enable for ECO oscillator.  Configure the settings in CLK_ECO_CONFIG2 to work with the selected crystal, before enabling ECO.</description>
10646              <bitRange>[31:31]</bitRange>
10647              <access>read-write</access>
10648            </field>
10649          </fields>
10650        </register>
10651        <register>
10652          <name>CLK_ECO_PRESCALE</name>
10653          <description>ECO Prescaler Configuration Register</description>
10654          <addressOffset>0x1520</addressOffset>
10655          <size>32</size>
10656          <access>read-write</access>
10657          <resetValue>0x0</resetValue>
10658          <resetMask>0x3FFFF01</resetMask>
10659          <fields>
10660            <field>
10661              <name>ECO_DIV_ENABLED</name>
10662              <description>ECO prescaler enabled. HW sets this field to '1' as a result of an CLK_ECO_CONFIG.ECO_DIV_ENABLE command. HW sets this field to '0' as a result on a CLK_ECO_CONFIG.ECO_DIV_DISABLE command.  ECO prescaler is incompatible with DEEPSLEEP modes, and firmware must disable it before entering DEEPSLEEP.</description>
10663              <bitRange>[0:0]</bitRange>
10664              <access>read-only</access>
10665            </field>
10666            <field>
10667              <name>ECO_FRAC_DIV</name>
10668              <description>8-bit fractional value, sufficient to get prescaler output within the +/-65ppm calibration range.  Do not change this setting when ECO Prescaler is enabled.</description>
10669              <bitRange>[15:8]</bitRange>
10670              <access>read-write</access>
10671            </field>
10672            <field>
10673              <name>ECO_INT_DIV</name>
10674              <description>10-bit integer value allows for ECO frequencies up to 33.55MHz.  Subtract one from the desired divide value when writing this field.  For example, to divide by 1, write ECO_INT_DIV=0.  Do not change this setting when ECO Prescaler is enabled.</description>
10675              <bitRange>[25:16]</bitRange>
10676              <access>read-write</access>
10677            </field>
10678          </fields>
10679        </register>
10680        <register>
10681          <name>CLK_ECO_STATUS</name>
10682          <description>ECO Status Register</description>
10683          <addressOffset>0x1524</addressOffset>
10684          <size>32</size>
10685          <access>read-only</access>
10686          <resetValue>0x0</resetValue>
10687          <resetMask>0x3</resetMask>
10688          <fields>
10689            <field>
10690              <name>ECO_OK</name>
10691              <description>Indicates the ECO internal oscillator circuit has sufficient amplitude.  It may not meet the PPM accuracy or duty cycle spec.</description>
10692              <bitRange>[0:0]</bitRange>
10693              <access>read-only</access>
10694            </field>
10695            <field>
10696              <name>ECO_READY</name>
10697              <description>Indicates the ECO internal oscillator circuit has had enough time to fully stabilize.  This is the output of a counter since ECO was enabled, and it does not check the ECO output.  It is recommended to also confirm ECO_OK==1.</description>
10698              <bitRange>[1:1]</bitRange>
10699              <access>read-only</access>
10700            </field>
10701          </fields>
10702        </register>
10703        <register>
10704          <name>CLK_PILO_CONFIG</name>
10705          <description>Precision ILO Configuration Register</description>
10706          <addressOffset>0x1528</addressOffset>
10707          <size>32</size>
10708          <access>read-write</access>
10709          <resetValue>0x10000</resetValue>
10710          <resetMask>0x80010001</resetMask>
10711          <fields>
10712            <field>
10713              <name>PILO_BACKUP</name>
10714              <description>If backup domain is present on this product, this register indicates that PILO should stay enabled for use by backup domain during XRES, and HIBERNATE mode.    If backup voltage domain is implemented on the product, PILO should stay enabled through power-related resets on other supplies, e.g.. BOD on VDDD/VCCD.   If the PILO is the selected source for WDT, writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register.
107150: PILO turns off at XRES/BOD events.  (unless backup voltage domain is implemented on the product)
107161: PILO remains on if backup domain is present and powered even for XRES/BOD or HIBERNATE entry.</description>
10717              <bitRange>[0:0]</bitRange>
10718              <access>read-write</access>
10719            </field>
10720            <field>
10721              <name>PILO_TCSC_EN</name>
10722              <description>PILO second order temperature curvature correction enable.  If the PILO is the selected source for WDT, writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register.
107230: Disable second order temperature curvature correction.
107241: Enable second order temperature curvature correction.</description>
10725              <bitRange>[16:16]</bitRange>
10726              <access>read-write</access>
10727            </field>
10728            <field>
10729              <name>PILO_EN</name>
10730              <description>Enable PILO.  If the PILO is the selected source for WDT, writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register.</description>
10731              <bitRange>[31:31]</bitRange>
10732              <access>read-write</access>
10733            </field>
10734          </fields>
10735        </register>
10736        <register>
10737          <name>CLK_FLL_CONFIG</name>
10738          <description>FLL Configuration Register</description>
10739          <addressOffset>0x1530</addressOffset>
10740          <size>32</size>
10741          <access>read-write</access>
10742          <resetValue>0x1000000</resetValue>
10743          <resetMask>0x8103FFFF</resetMask>
10744          <fields>
10745            <field>
10746              <name>FLL_MULT</name>
10747              <description>Multiplier to determine CCO frequency in multiples of the frequency of the selected reference clock (Fref).
10748
10749Ffll = (FLL_MULT)  * (Fref / REFERENCE_DIV) / (OUTPUT_DIV+1)</description>
10750              <bitRange>[17:0]</bitRange>
10751              <access>read-write</access>
10752            </field>
10753            <field>
10754              <name>FLL_OUTPUT_DIV</name>
10755              <description>Control bits for Output divider.  Set the divide value before enabling the FLL, and do not change it while FLL is enabled.
107560: no division
107571: divide by 2</description>
10758              <bitRange>[24:24]</bitRange>
10759              <access>read-write</access>
10760            </field>
10761            <field>
10762              <name>FLL_ENABLE</name>
10763              <description>Master enable for FLL.  The FLL requires firmware sequencing when enabling and disabling.  Hardware handles sequencing automatically when entering/exiting DEEPSLEEP.
10764
10765To enable the FLL, use the following sequence:
107661) Configure FLL and CCO settings.  Do not modify CLK_FLL_CONFIG3.BYPASS_SEL (must be AUTO) or CLK_FLL_CONFIG.FLL_ENABLE (must be 0).
107672) Enable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=1
107683) Wait until CLK_FLL_STATUS.CCO_READY==1.
107694) Ensure the reference clock has stabilized.
107705) Write FLL_ENABLE=1.
107716) Optionally wait until CLK_FLL_STATUS.LOCKED==1.  The hardware automatically changes to the FLL output when LOCKED==1.
10772
10773To disable the FLL, use the following sequence:
107741) Write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF.
107752) Read CLK_FLL_CONFIG3.BYPASS_SEL to ensure the write completes (read is not optional).
107763) Wait at least ten cycles of either FLL reference clock or FLL output clock, whichever is slower.
107774) Disable FLL with FLL_ENABLE=0.
107785) Disable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=0.
107796) Write CLK_FLL_CONFIG3.BYPASS_SEL=AUTO.
107807) Read CLK_FLL_CONFIG3.BYPASS_SEL to ensure the write completes (read is not optional).
107818) Wait three cycles of FLL reference clock.
10782
107830: Block is powered off
107841: Block is powered on</description>
10785              <bitRange>[31:31]</bitRange>
10786              <access>read-write</access>
10787            </field>
10788          </fields>
10789        </register>
10790        <register>
10791          <name>CLK_FLL_CONFIG2</name>
10792          <description>FLL Configuration Register 2</description>
10793          <addressOffset>0x1534</addressOffset>
10794          <size>32</size>
10795          <access>read-write</access>
10796          <resetValue>0x20001</resetValue>
10797          <resetMask>0xFFFF1FFF</resetMask>
10798          <fields>
10799            <field>
10800              <name>FLL_REF_DIV</name>
10801              <description>Control bits for reference divider.  Set the divide value before enabling the FLL, and do not change it while FLL is enabled.
108020: illegal (undefined behavior)
108031: divide by 1
10804...
108058191: divide by 8191</description>
10806              <bitRange>[12:0]</bitRange>
10807              <access>read-write</access>
10808            </field>
10809            <field>
10810              <name>LOCK_TOL</name>
10811              <description>Lock tolerance sets the error threshold for when the FLL output is considered locked to the reference input.  A high tolerance can be used to lock more quickly or allow less accuracy.  The tolerance is the allowed difference between the count value for the ideal formula and the measured value.
108120: tolerate error of 1 count value
108131: tolerate error of 2 count values
10814...
10815255: tolerate error of 256 count values</description>
10816              <bitRange>[23:16]</bitRange>
10817              <access>read-write</access>
10818            </field>
10819            <field>
10820              <name>UPDATE_TOL</name>
10821              <description>Update tolerance sets the error threshold for when the FLL will update the CCO frequency settings.  The update tolerance is the allowed difference between the count value for the ideal formula and the measured value. UPDATE_TOL should be less than LOCK_TOL.</description>
10822              <bitRange>[31:24]</bitRange>
10823              <access>read-write</access>
10824            </field>
10825          </fields>
10826        </register>
10827        <register>
10828          <name>CLK_FLL_CONFIG3</name>
10829          <description>FLL Configuration Register 3</description>
10830          <addressOffset>0x1538</addressOffset>
10831          <size>32</size>
10832          <access>read-write</access>
10833          <resetValue>0x2800</resetValue>
10834          <resetMask>0x301FFFFF</resetMask>
10835          <fields>
10836            <field>
10837              <name>FLL_LF_IGAIN</name>
10838              <description>FLL Loop Filter Gain Setting #1.  The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN.
108390: 1/256
108401: 1/128
108412: 1/64
108423: 1/32
108434: 1/16
108445: 1/8
108456: 1/4
108467: 1/2
108478: 1.0
108489: 2.0
1084910: 4.0
1085011: 8.0
10851&gt;=12: illegal</description>
10852              <bitRange>[3:0]</bitRange>
10853              <access>read-write</access>
10854            </field>
10855            <field>
10856              <name>FLL_LF_PGAIN</name>
10857              <description>FLL Loop Filter Gain Setting #2.  The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN.
108580: 1/256
108591: 1/128
108602: 1/64
108613: 1/32
108624: 1/16
108635: 1/8
108646: 1/4
108657: 1/2
108668: 1.0
108679: 2.0
1086810: 4.0
1086911: 8.0
10870&gt;=12: illegal</description>
10871              <bitRange>[7:4]</bitRange>
10872              <access>read-write</access>
10873            </field>
10874            <field>
10875              <name>SETTLING_COUNT</name>
10876              <description>Number of undivided reference clock cycles to wait after changing the CCO trim until the loop measurement restarts.  A delay allows the CCO output to settle and gives a more accurate measurement.  The default is tuned to an 8MHz reference clock since the IMO is expected to be the most common use case.
108770: no settling time
108781: wait one reference clock cycle
10879...
108808191: wait 8191 reference clock cycles</description>
10881              <bitRange>[20:8]</bitRange>
10882              <access>read-write</access>
10883            </field>
10884            <field>
10885              <name>BYPASS_SEL</name>
10886              <description>Bypass mux located just after FLL output.  This register can be written while the FLL is enabled.  When changing BYPASS_SEL, do not turn off the reference clock or CCO clock for five cycles (whichever is slower).  Whenever BYPASS_SEL is changed, it is required to read CLK_FLL_CONFIG3 to ensure the change takes effect.</description>
10887              <bitRange>[29:28]</bitRange>
10888              <access>read-write</access>
10889              <enumeratedValues>
10890                <enumeratedValue>
10891                  <name>AUTO</name>
10892                  <description>Automatic using lock indicator.  When unlocked, automatically selects FLL reference input (bypass mode).  When locked, automatically selects FLL output.  This can allow some processing to occur while the FLL is locking, such as after DEEPSLEEP wakeup.  It is incompatible with clock supervision, because the frequency changes based on the lock signal.</description>
10893                  <value>0</value>
10894                </enumeratedValue>
10895                <enumeratedValue>
10896                  <name>LOCKED_OR_NOTHING</name>
10897                  <description>Similar to AUTO, except the clock is gated off when unlocked.  This is compatible with clock supervision, because the supervisors allow no clock during startup (until a timeout occurs), and the clock targets the proper frequency whenever it is running.</description>
10898                  <value>1</value>
10899                </enumeratedValue>
10900                <enumeratedValue>
10901                  <name>FLL_REF</name>
10902                  <description>Select FLL reference input (bypass mode).  Ignores lock indicator</description>
10903                  <value>2</value>
10904                </enumeratedValue>
10905                <enumeratedValue>
10906                  <name>FLL_OUT</name>
10907                  <description>Select FLL output.  Ignores lock indicator.</description>
10908                  <value>3</value>
10909                </enumeratedValue>
10910              </enumeratedValues>
10911            </field>
10912          </fields>
10913        </register>
10914        <register>
10915          <name>CLK_FLL_CONFIG4</name>
10916          <description>FLL Configuration Register 4</description>
10917          <addressOffset>0x153C</addressOffset>
10918          <size>32</size>
10919          <access>read-write</access>
10920          <resetValue>0xFF</resetValue>
10921          <resetMask>0xC1FF07FF</resetMask>
10922          <fields>
10923            <field>
10924              <name>CCO_LIMIT</name>
10925              <description>Maximum CCO offset allowed (used to prevent FLL dynamics from selecting an CCO frequency that the logic cannot support)</description>
10926              <bitRange>[7:0]</bitRange>
10927              <access>read-write</access>
10928            </field>
10929            <field>
10930              <name>CCO_RANGE</name>
10931              <description>Frequency range of CCO</description>
10932              <bitRange>[10:8]</bitRange>
10933              <access>read-write</access>
10934              <enumeratedValues>
10935                <enumeratedValue>
10936                  <name>RANGE0</name>
10937                  <description>Target frequency is in range [48, 64) MHz</description>
10938                  <value>0</value>
10939                </enumeratedValue>
10940                <enumeratedValue>
10941                  <name>RANGE1</name>
10942                  <description>Target frequency is in range [64, 85) MHz</description>
10943                  <value>1</value>
10944                </enumeratedValue>
10945                <enumeratedValue>
10946                  <name>RANGE2</name>
10947                  <description>Target frequency is in range [85, 113) MHz</description>
10948                  <value>2</value>
10949                </enumeratedValue>
10950                <enumeratedValue>
10951                  <name>RANGE3</name>
10952                  <description>Target frequency is in range [113, 150) MHz</description>
10953                  <value>3</value>
10954                </enumeratedValue>
10955                <enumeratedValue>
10956                  <name>RANGE4</name>
10957                  <description>Target frequency is in range [150, 200] MHz</description>
10958                  <value>4</value>
10959                </enumeratedValue>
10960              </enumeratedValues>
10961            </field>
10962            <field>
10963              <name>CCO_FREQ</name>
10964              <description>CCO frequency code.  This is updated by HW when the FLL is enabled.  It can be manually updated to use the CCO in an open loop configuration.  The meaning of each frequency code depends on the range.</description>
10965              <bitRange>[24:16]</bitRange>
10966              <access>read-write</access>
10967            </field>
10968            <field>
10969              <name>CCO_HW_UPDATE_DIS</name>
10970              <description>Disable CCO frequency update by FLL hardware
109710: Hardware update of CCO settings is allowed.  Use this setting for normal FLL operation.
109721: Hardware update of CCO settings is disabled.  Use this setting for open-loop FLL operation.</description>
10973              <bitRange>[30:30]</bitRange>
10974              <access>read-write</access>
10975            </field>
10976            <field>
10977              <name>CCO_ENABLE</name>
10978              <description>Enable the CCO.  It is required to enable the CCO before using the FLL.
109790: Block is powered off
109801: Block is powered on</description>
10981              <bitRange>[31:31]</bitRange>
10982              <access>read-write</access>
10983            </field>
10984          </fields>
10985        </register>
10986        <register>
10987          <name>CLK_FLL_STATUS</name>
10988          <description>FLL Status Register</description>
10989          <addressOffset>0x1540</addressOffset>
10990          <size>32</size>
10991          <access>read-write</access>
10992          <resetValue>0x0</resetValue>
10993          <resetMask>0x7</resetMask>
10994          <fields>
10995            <field>
10996              <name>LOCKED</name>
10997              <description>FLL Lock Indicator</description>
10998              <bitRange>[0:0]</bitRange>
10999              <access>read-only</access>
11000            </field>
11001            <field>
11002              <name>UNLOCK_OCCURRED</name>
11003              <description>This bit sets whenever the FLL is enabled and goes out of lock.  This bit stays set until cleared by firmware.</description>
11004              <bitRange>[1:1]</bitRange>
11005              <access>read-write</access>
11006            </field>
11007            <field>
11008              <name>CCO_READY</name>
11009              <description>This indicates that the CCO is internally settled and ready to use.</description>
11010              <bitRange>[2:2]</bitRange>
11011              <access>read-only</access>
11012            </field>
11013          </fields>
11014        </register>
11015        <register>
11016          <name>CLK_ECO_CONFIG2</name>
11017          <description>ECO Configuration Register 2</description>
11018          <addressOffset>0x1544</addressOffset>
11019          <size>32</size>
11020          <access>read-write</access>
11021          <resetValue>0x3</resetValue>
11022          <resetMask>0x7FF7</resetMask>
11023          <fields>
11024            <field>
11025              <name>WDTRIM</name>
11026              <description>Watch Dog Trim -  Delta voltage below steady state level
110270x0 - 50mV
110280x1 - 75mV
110290x2 - 100mV
110300x3 - 125mV
110310x4 - 150mV
110320x5 - 175mV
110330x6 - 200mV
110340x7 - 225mV</description>
11035              <bitRange>[2:0]</bitRange>
11036              <access>read-write</access>
11037            </field>
11038            <field>
11039              <name>ATRIM</name>
11040              <description>Amplitude trim to set the crystal drive level when ECO_CONFIG.AGC_EN=1.  WARNING: use care when setting this field because driving a crystal beyond its rated limit can permanently damage the crystal.
110410x0 - 150mV
110420x1 - 175mV
110430x2 - 200mV
110440x3 - 225mV
110450x4 - 250mV
110460x5 - 275mV
110470x6 - 300mV
110480x7 - 325mV
110490x8 - 350mV
110500x9 - 375mV
110510xA - 400mV
110520xB - 425mV
110530xC - 450mV
110540xD - 475mV
110550xE - 500mV
110560xF - 525mV</description>
11057              <bitRange>[7:4]</bitRange>
11058              <access>read-write</access>
11059            </field>
11060            <field>
11061              <name>FTRIM</name>
11062              <description>Filter Trim - 3rd harmonic oscillation</description>
11063              <bitRange>[9:8]</bitRange>
11064              <access>read-write</access>
11065            </field>
11066            <field>
11067              <name>RTRIM</name>
11068              <description>Feedback resistor Trim</description>
11069              <bitRange>[11:10]</bitRange>
11070              <access>read-write</access>
11071            </field>
11072            <field>
11073              <name>GTRIM</name>
11074              <description>Gain Trim - Startup time.</description>
11075              <bitRange>[14:12]</bitRange>
11076              <access>read-write</access>
11077            </field>
11078          </fields>
11079        </register>
11080        <register>
11081          <name>CLK_ILO_CONFIG</name>
11082          <description>ILO Configuration</description>
11083          <addressOffset>0x1548</addressOffset>
11084          <size>32</size>
11085          <access>read-write</access>
11086          <resetValue>0x80000000</resetValue>
11087          <resetMask>0x80000001</resetMask>
11088          <fields>
11089            <field>
11090              <name>ILO_BACKUP</name>
11091              <description>If backup domain is present on this product, this register indicates that ILO should stay enabled for use by backup domain during XRES, HIBERNATE mode, and through power-related resets like BOD on VDDD/VCCD.  Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register.
110920: ILO turns off at XRES/BOD event or HIBERNATE entry.
110931: ILO remains on if backup domain is present and powered even for XRES/BOD or HIBERNATE entry.</description>
11094              <bitRange>[0:0]</bitRange>
11095              <access>read-write</access>
11096            </field>
11097            <field>
11098              <name>ENABLE</name>
11099              <description>Master enable for ILO.  Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register.  After enabling, it takes at most two cycles to reach the accuracy spec.</description>
11100              <bitRange>[31:31]</bitRange>
11101              <access>read-write</access>
11102            </field>
11103          </fields>
11104        </register>
11105        <register>
11106          <name>CLK_TRIM_ILO_CTL</name>
11107          <description>ILO Trim Register</description>
11108          <addressOffset>0x154C</addressOffset>
11109          <size>32</size>
11110          <access>read-write</access>
11111          <resetValue>0x2C</resetValue>
11112          <resetMask>0x3F</resetMask>
11113          <fields>
11114            <field>
11115              <name>ILO_FTRIM</name>
11116              <description>IL0 frequency trims.  LSB step size is 1.5 percent (typical) of the frequency.</description>
11117              <bitRange>[5:0]</bitRange>
11118              <access>read-write</access>
11119            </field>
11120          </fields>
11121        </register>
11122        <register>
11123          <name>CLK_TRIM_ILO0_CTL</name>
11124          <description>ILO0 Trim Register</description>
11125          <addressOffset>0x1550</addressOffset>
11126          <size>32</size>
11127          <access>read-write</access>
11128          <resetValue>0x52C</resetValue>
11129          <resetMask>0xF3F</resetMask>
11130          <fields>
11131            <field>
11132              <name>ILO0_FTRIM</name>
11133              <description>ILO0 frequency trims.  LSB step size is 1.5 percent (typical) of the frequency.</description>
11134              <bitRange>[5:0]</bitRange>
11135              <access>read-write</access>
11136            </field>
11137            <field>
11138              <name>ILO0_MONTRIM</name>
11139              <description>ILO0 internal monitor trim.</description>
11140              <bitRange>[11:8]</bitRange>
11141              <access>read-write</access>
11142            </field>
11143          </fields>
11144        </register>
11145        <register>
11146          <name>CLK_MF_SELECT</name>
11147          <description>Medium Frequency Clock Select Register</description>
11148          <addressOffset>0x1554</addressOffset>
11149          <size>32</size>
11150          <access>read-write</access>
11151          <resetValue>0x0</resetValue>
11152          <resetMask>0x8000FF07</resetMask>
11153          <fields>
11154            <field>
11155              <name>MFCLK_SEL</name>
11156              <description>Select source for MFCLK (clk_mf).  Note that not all products support all clock sources.  Selecting a clock source that is not supported results in undefined behavior.</description>
11157              <bitRange>[2:0]</bitRange>
11158              <access>read-write</access>
11159              <enumeratedValues>
11160                <enumeratedValue>
11161                  <name>MFO</name>
11162                  <description>MFO - Medium Frequency Oscillator.  DEEPSLEEP compatibility is product-specific.  See CLK_MFO_CONFIG for capability of this product.</description>
11163                  <value>0</value>
11164                </enumeratedValue>
11165                <enumeratedValue>
11166                  <name>ILO</name>
11167                  <description>ILO - Internal Low-speed Oscillator.</description>
11168                  <value>1</value>
11169                </enumeratedValue>
11170                <enumeratedValue>
11171                  <name>WCO</name>
11172                  <description>WCO - Watch-Crystal Oscillator, if present.</description>
11173                  <value>2</value>
11174                </enumeratedValue>
11175                <enumeratedValue>
11176                  <name>ALTLF</name>
11177                  <description>ALTLF - Alternate Low-Frequency Clock.  Capability is product-specific</description>
11178                  <value>3</value>
11179                </enumeratedValue>
11180                <enumeratedValue>
11181                  <name>PILO</name>
11182                  <description>PILO - Precision ILO, if present.</description>
11183                  <value>4</value>
11184                </enumeratedValue>
11185                <enumeratedValue>
11186                  <name>ILO1</name>
11187                  <description>ILO1 - Internal Low-speed Oscillator #1, if present.</description>
11188                  <value>5</value>
11189                </enumeratedValue>
11190                <enumeratedValue>
11191                  <name>ECO_PRESCALER</name>
11192                  <description>ECO_PRESCALER - External-Crystal Oscillator, if present, after prescaling in CLK_ECO_PRESCALE.  Intended for applications that operate in ACTIVE/SLEEP modes only.  Does not work in DEEPSLEEP mode.</description>
11193                  <value>6</value>
11194                </enumeratedValue>
11195                <enumeratedValue>
11196                  <name>LPECO</name>
11197                  <description>LPECO - Low Power External Crystal Oscillator, if present.</description>
11198                  <value>7</value>
11199                </enumeratedValue>
11200              </enumeratedValues>
11201            </field>
11202            <field>
11203              <name>MFCLK_DIV</name>
11204              <description>Divide selected clock source by (1+MFCLK_DIV).  The output of this divider is MFCLK (clk_mf).  Allows for integer divisions in the range [1, 256].  Do not change this setting while ENABLE==1.</description>
11205              <bitRange>[15:8]</bitRange>
11206              <access>read-write</access>
11207            </field>
11208            <field>
11209              <name>ENABLE</name>
11210              <description>Enable for MFCLK (clk_mf).  When disabling clk_mf, do not disable the source until after 5 clk_mf periods.  clk_mf continues to operate in DEEPSLEEP for compatible sources.  Firmware must disable clk_mf before entering DEEPSLEEP if the source is not compatible with DEEPSLEEP mode.</description>
11211              <bitRange>[31:31]</bitRange>
11212              <access>read-write</access>
11213            </field>
11214          </fields>
11215        </register>
11216        <register>
11217          <name>CLK_MFO_CONFIG</name>
11218          <description>MFO Configuration Register</description>
11219          <addressOffset>0x1558</addressOffset>
11220          <size>32</size>
11221          <access>read-write</access>
11222          <resetValue>0x80000000</resetValue>
11223          <resetMask>0xC0000000</resetMask>
11224          <fields>
11225            <field>
11226              <name>DPSLP_ENABLE</name>
11227              <description>Enable for MFO during DEEPSLEEP.  This bit is ignored when ENABLE==0.  When ENABLE==1:
112280: MFO is automatically disabled during DEEPSLEEP and enables upon wakeup;
112291: MFO is kept enabled throughout DEEPSLEEP</description>
11230              <bitRange>[30:30]</bitRange>
11231              <access>read-write</access>
11232            </field>
11233            <field>
11234              <name>ENABLE</name>
11235              <description>Enable for Medium Frequency Oscillator (MFO) to generate clk_mf.  It is product-specific whether this is a separate component or implemented as a divided version of another clock (eg. IMO).</description>
11236              <bitRange>[31:31]</bitRange>
11237              <access>read-write</access>
11238            </field>
11239          </fields>
11240        </register>
11241        <register>
11242          <name>CLK_IHO_CONFIG</name>
11243          <description>IHO Configuration Register</description>
11244          <addressOffset>0x1560</addressOffset>
11245          <size>32</size>
11246          <access>read-write</access>
11247          <resetValue>0x80000000</resetValue>
11248          <resetMask>0x80000000</resetMask>
11249          <fields>
11250            <field>
11251              <name>ENABLE</name>
11252              <description>Enable for Internal High-speed Oscillator (IHO) to generate clk_iho.</description>
11253              <bitRange>[31:31]</bitRange>
11254              <access>read-write</access>
11255            </field>
11256          </fields>
11257        </register>
11258        <register>
11259          <name>CLK_ALTHF_CTL</name>
11260          <description>Alternate High Frequency Clock Control Register</description>
11261          <addressOffset>0x1564</addressOffset>
11262          <size>32</size>
11263          <access>read-write</access>
11264          <resetValue>0x0</resetValue>
11265          <resetMask>0x80000001</resetMask>
11266          <fields>
11267            <field>
11268              <name>ALTHF_ENABLED</name>
11269              <description>Indicates that ALTHF is actually enabled.  The delay between a transition on ALTHF_ENABLE and ALTHF_ENABLED is product specific.</description>
11270              <bitRange>[0:0]</bitRange>
11271              <access>read-only</access>
11272            </field>
11273            <field>
11274              <name>ALTHF_ENABLE</name>
11275              <description>Enable for ALTHF clock when used by SRSS.  There may be independent control of ALTHF by another subsystem, and this bit prevents ALTHF from being disabled when SRSS needs it.  SRSS automatically removes its enable request during DEEPSLEEP and lower modes.</description>
11276              <bitRange>[31:31]</bitRange>
11277              <access>read-write</access>
11278            </field>
11279          </fields>
11280        </register>
11281        <register>
11282          <dim>15</dim>
11283          <dimIncrement>4</dimIncrement>
11284          <name>CLK_PLL_CONFIG[%s]</name>
11285          <description>PLL Configuration Register</description>
11286          <addressOffset>0x1600</addressOffset>
11287          <size>32</size>
11288          <access>read-write</access>
11289          <resetValue>0x20116</resetValue>
11290          <resetMask>0xBE1F1F7F</resetMask>
11291          <fields>
11292            <field>
11293              <name>FEEDBACK_DIV</name>
11294              <description>Control bits for feedback divider.  Set the divide value before enabling the PLL, and do not change it while PLL is enabled.
112950-21: illegal (undefined behavior)
1129622: divide by 22
11297...
11298112: divide by 112
11299&gt;112: illegal (undefined behavior)</description>
11300              <bitRange>[6:0]</bitRange>
11301              <access>read-write</access>
11302            </field>
11303            <field>
11304              <name>REFERENCE_DIV</name>
11305              <description>Control bits for reference divider.  Set the divide value before enabling the PLL, and do not change it while PLL is enabled.
113060: illegal (undefined behavior)
113071: divide by 1
11308...
1130920: divide by 20
11310others: illegal (undefined behavior)</description>
11311              <bitRange>[12:8]</bitRange>
11312              <access>read-write</access>
11313            </field>
11314            <field>
11315              <name>OUTPUT_DIV</name>
11316              <description>Control bits for Output divider.  Set the divide value before enabling the PLL, and do not change it while PLL is enabled.
113170: illegal (undefined behavior)
113181: illegal (undefined behavior)
113192: divide by 2.  Suitable for direct usage as HFCLK source.
11320...
1132116: divide by 16.  Suitable for direct usage as HFCLK source.
11322&gt;16: illegal (undefined behavior)</description>
11323              <bitRange>[20:16]</bitRange>
11324              <access>read-write</access>
11325            </field>
11326            <field>
11327              <name>LOCK_DELAY</name>
11328              <description>N/A</description>
11329              <bitRange>[26:25]</bitRange>
11330              <access>read-write</access>
11331            </field>
11332            <field>
11333              <name>PLL_LF_MODE</name>
11334              <description>VCO frequency range selection.  Configure this bit according to the targeted VCO frequency.  Do not change this setting while the PLL is enabled.
113350: VCO frequency is [200MHz, 400MHz]
113361: VCO frequency is [170MHz, 200MHz)</description>
11337              <bitRange>[27:27]</bitRange>
11338              <access>read-write</access>
11339            </field>
11340            <field>
11341              <name>BYPASS_SEL</name>
11342              <description>Bypass mux located just after PLL output.  This selection is glitch-free and can be changed while the PLL is running.  When changing BYPASS_SEL, do not turn off the reference clock or PLL clock for five cycles (whichever is slower).</description>
11343              <bitRange>[29:28]</bitRange>
11344              <access>read-write</access>
11345              <enumeratedValues>
11346                <enumeratedValue>
11347                  <name>AUTO</name>
11348                  <description>Automatic using lock indicator.  When unlocked, automatically selects PLL reference input (bypass mode).  When locked, automatically selects PLL output.  If ENABLE=0, automatically selects PLL reference input.</description>
11349                  <value>0</value>
11350                </enumeratedValue>
11351                <enumeratedValue>
11352                  <name>LOCKED_OR_NOTHING</name>
11353                  <description>Similar to AUTO, except the clock is gated off when unlocked.  This is compatible with clock supervision, because the supervisors allow no clock during startup (until a timeout occurs), and the clock targets the proper frequency whenever it is running.  If ENABLE=0, no clock is output.</description>
11354                  <value>1</value>
11355                </enumeratedValue>
11356                <enumeratedValue>
11357                  <name>PLL_REF</name>
11358                  <description>Select PLL reference input (bypass mode).  Ignores lock indicator</description>
11359                  <value>2</value>
11360                </enumeratedValue>
11361                <enumeratedValue>
11362                  <name>PLL_OUT</name>
11363                  <description>Select PLL output.  Ignores lock indicator.  If ENABLE=0, no clock is output.</description>
11364                  <value>3</value>
11365                </enumeratedValue>
11366              </enumeratedValues>
11367            </field>
11368            <field>
11369              <name>ENABLE</name>
11370              <description>Master enable for PLL.  Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1.
11371
11372Fpll = (FEEDBACK_DIV)  * (Fref / REFERENCE_DIV) / (OUTPUT_DIV)
11373
113740: Block is disabled.  When the PLL disables, hardware controls the bypass mux as described in BYPASS_SEL, before disabling the PLL circuit.
113751: Block is enabled</description>
11376              <bitRange>[31:31]</bitRange>
11377              <access>read-write</access>
11378            </field>
11379          </fields>
11380        </register>
11381        <register>
11382          <dim>15</dim>
11383          <dimIncrement>4</dimIncrement>
11384          <name>CLK_PLL_STATUS[%s]</name>
11385          <description>PLL Status Register</description>
11386          <addressOffset>0x1640</addressOffset>
11387          <size>32</size>
11388          <access>read-write</access>
11389          <resetValue>0x0</resetValue>
11390          <resetMask>0x3</resetMask>
11391          <fields>
11392            <field>
11393              <name>LOCKED</name>
11394              <description>PLL Lock Indicator</description>
11395              <bitRange>[0:0]</bitRange>
11396              <access>read-only</access>
11397            </field>
11398            <field>
11399              <name>UNLOCK_OCCURRED</name>
11400              <description>This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.</description>
11401              <bitRange>[1:1]</bitRange>
11402              <access>read-write</access>
11403            </field>
11404          </fields>
11405        </register>
11406        <register>
11407          <name>CSV_REF_SEL</name>
11408          <description>Select CSV Reference clock for Active domain</description>
11409          <addressOffset>0x1700</addressOffset>
11410          <size>32</size>
11411          <access>read-write</access>
11412          <resetValue>0x0</resetValue>
11413          <resetMask>0x7</resetMask>
11414          <fields>
11415            <field>
11416              <name>REF_MUX</name>
11417              <description>Selects a source for clock clk_ref_hf.  Note that not all products support all clock sources.  Selecting a clock source that is not supported will result in undefined behavior.   It takes four cycles of the originally selected clock to switch away from it.  Do not disable the original clock during this time.</description>
11418              <bitRange>[2:0]</bitRange>
11419              <access>read-write</access>
11420              <enumeratedValues>
11421                <enumeratedValue>
11422                  <name>IMO</name>
11423                  <description>IMO - Internal R/C Oscillator</description>
11424                  <value>0</value>
11425                </enumeratedValue>
11426                <enumeratedValue>
11427                  <name>EXTCLK</name>
11428                  <description>EXTCLK - External Clock Pin</description>
11429                  <value>1</value>
11430                </enumeratedValue>
11431                <enumeratedValue>
11432                  <name>ECO</name>
11433                  <description>ECO - External-Crystal Oscillator</description>
11434                  <value>2</value>
11435                </enumeratedValue>
11436                <enumeratedValue>
11437                  <name>ALTHF</name>
11438                  <description>ALTHF - Alternate High-Frequency clock input (product-specific clock)</description>
11439                  <value>3</value>
11440                </enumeratedValue>
11441                <enumeratedValue>
11442                  <name>IHO</name>
11443                  <description>IHO - Internal High-speed Oscillator</description>
11444                  <value>4</value>
11445                </enumeratedValue>
11446              </enumeratedValues>
11447            </field>
11448          </fields>
11449        </register>
11450        <cluster>
11451          <name>CSV_REF</name>
11452          <description>CSV registers for the CSV Reference clock</description>
11453          <headerStructName>CSV_REF</headerStructName>
11454          <addressOffset>0x00001710</addressOffset>
11455          <cluster>
11456            <name>CSV</name>
11457            <description>Active domain Clock Supervisor (CSV) registers for CSV Reference clock</description>
11458            <headerStructName>CSV_REF_CSV</headerStructName>
11459            <addressOffset>0x00000000</addressOffset>
11460            <register>
11461              <name>REF_CTL</name>
11462              <description>Clock Supervision Reference Control</description>
11463              <addressOffset>0x0</addressOffset>
11464              <size>32</size>
11465              <access>read-write</access>
11466              <resetValue>0x0</resetValue>
11467              <resetMask>0xC000FFFF</resetMask>
11468              <fields>
11469                <field>
11470                  <name>STARTUP</name>
11471                  <description>Startup delay time -1 (in reference clock cycles), after enable or DeepSleep wakeup, from reference clock start to monitored clock start.
11472At a minimum (both clocks running): STARTUP &gt;= (PERIOD +3) * FREQ_RATIO - UPPER, with FREQ_RATIO = (Reference frequency / Monitored frequency)
11473On top of that the actual clock startup delay and the margin for accuracy of both clocks must be added.</description>
11474                  <bitRange>[15:0]</bitRange>
11475                  <access>read-write</access>
11476                </field>
11477                <field>
11478                  <name>CSV_ACTION</name>
11479                  <description>Specifies the action taken when an anomaly is detected on the monitored clock.  CSV in DeepSleep domain always do a Fault report (which also wakes up the system).</description>
11480                  <bitRange>[30:30]</bitRange>
11481                  <access>read-write</access>
11482                  <enumeratedValues>
11483                    <enumeratedValue>
11484                      <name>FAULT</name>
11485                      <description>Generate a fault</description>
11486                      <value>0</value>
11487                    </enumeratedValue>
11488                    <enumeratedValue>
11489                      <name>RESET</name>
11490                      <description>Cause a power reset. This should only be used for clk_hf0.</description>
11491                      <value>1</value>
11492                    </enumeratedValue>
11493                  </enumeratedValues>
11494                </field>
11495                <field>
11496                  <name>CSV_EN</name>
11497                  <description>Enables clock supervision, both frequency and loss.
11498CSV in Active domain: Clock supervision is reset during DeepSleep and Hibernate modes.  When enabled it begins operating automatically after a DeepSleep wakeup, but it must be reconfigured after Hibernate wakeup.
11499CSV in DeepSleep domain: Clock supervision is reset during Hibernate mode.  It must be reconfigured after Hibernate wakeup.
11500
11501A CSV error detection is reported to the Fault structure, or instead it can generate a power reset.</description>
11502                  <bitRange>[31:31]</bitRange>
11503                  <access>read-write</access>
11504                </field>
11505              </fields>
11506            </register>
11507            <register>
11508              <name>REF_LIMIT</name>
11509              <description>Clock Supervision Reference Limits</description>
11510              <addressOffset>0x4</addressOffset>
11511              <size>32</size>
11512              <access>read-write</access>
11513              <resetValue>0x0</resetValue>
11514              <resetMask>0xFFFFFFFF</resetMask>
11515              <fields>
11516                <field>
11517                  <name>LOWER</name>
11518                  <description>Cycle time lower limit.  Set the lower limit -1, in reference clock cycles, before the next monitored clock event is allowed to happen.  If a monitored clock event happens before this limit is reached a CSV error is detected.
11519LOWER must be at least 1 less than UPPER. In case the clocks are asynchronous LOWER must be at least 3 less than UPPER.</description>
11520                  <bitRange>[15:0]</bitRange>
11521                  <access>read-write</access>
11522                </field>
11523                <field>
11524                  <name>UPPER</name>
11525                  <description>Cycle time upper limit.  Set the upper limit -1, in reference clock cycles, before (or same time) the next monitored clock event must happen.  If a monitored clock event does not happen before this limit is reached, or does not happen at all (clock loss), a CSV error is detected.</description>
11526                  <bitRange>[31:16]</bitRange>
11527                  <access>read-write</access>
11528                </field>
11529              </fields>
11530            </register>
11531            <register>
11532              <name>MON_CTL</name>
11533              <description>Clock Supervision Monitor Control</description>
11534              <addressOffset>0x8</addressOffset>
11535              <size>32</size>
11536              <access>read-write</access>
11537              <resetValue>0x0</resetValue>
11538              <resetMask>0xFFFF</resetMask>
11539              <fields>
11540                <field>
11541                  <name>PERIOD</name>
11542                  <description>Period time.  Set the Period -1, in monitored clock cycles, before the next monitored clock event happens.
11543PERIOD &lt;=  (UPPER+1) / FREQ_RATIO -1, with FREQ_RATIO = (Reference frequency / Monitored frequency)
11544In case the clocks are asynchronous: PERIOD &lt;=  UPPER / FREQ_RATIO -1
11545Additionally margin must be added for accuracy of both clocks.</description>
11546                  <bitRange>[15:0]</bitRange>
11547                  <access>read-write</access>
11548                </field>
11549              </fields>
11550            </register>
11551          </cluster>
11552        </cluster>
11553        <cluster>
11554          <name>CSV_LF</name>
11555          <description>CSV registers for LF clock</description>
11556          <headerStructName>CSV_LF</headerStructName>
11557          <addressOffset>0x00001720</addressOffset>
11558          <cluster>
11559            <name>CSV</name>
11560            <description>LF clock Clock Supervisor registers</description>
11561            <headerStructName>CSV_LF_CSV</headerStructName>
11562            <addressOffset>0x00000000</addressOffset>
11563            <register>
11564              <name>REF_CTL</name>
11565              <description>Clock Supervision Reference Control</description>
11566              <addressOffset>0x0</addressOffset>
11567              <size>32</size>
11568              <access>read-write</access>
11569              <resetValue>0x0</resetValue>
11570              <resetMask>0x800000FF</resetMask>
11571              <fields>
11572                <field>
11573                  <name>STARTUP</name>
11574                  <description>Startup delay time -1 (in reference clock cycles), after enable, from reference clock start to monitored clock start.
11575At a minimum (both clocks running): STARTUP &gt;= (PERIOD +3) * FREQ_RATIO - UPPER, with FREQ_RATIO = (Reference frequency / Monitored frequency)
11576On top of that the actual clock startup delay and the margin for accuracy of both clocks must be added.</description>
11577                  <bitRange>[7:0]</bitRange>
11578                  <access>read-write</access>
11579                </field>
11580                <field>
11581                  <name>CSV_EN</name>
11582                  <description>Enables clock supervision, both frequency and loss.
11583CSV in Active domain: Clock supervision is reset during DeepSleep and Hibernate modes.  When enabled it begins operating automatically after a DeepSleep wakeup, but it must be reconfigured after Hibernate wakeup.
11584CSV in DeepSleep domain: Clock supervision is reset during Hibernate mode.  It must be reconfigured after Hibernate wakeup.
11585CSV in Backup domain: Clock supervision operates during Hibernate mode, can be configured to wake from Hibernate, and continues operating during reboot.
11586
11587A CSV error detection is reported to the Fault structure.</description>
11588                  <bitRange>[31:31]</bitRange>
11589                  <access>read-write</access>
11590                </field>
11591              </fields>
11592            </register>
11593            <register>
11594              <name>REF_LIMIT</name>
11595              <description>Clock Supervision Reference Limits</description>
11596              <addressOffset>0x4</addressOffset>
11597              <size>32</size>
11598              <access>read-write</access>
11599              <resetValue>0x0</resetValue>
11600              <resetMask>0xFF00FF</resetMask>
11601              <fields>
11602                <field>
11603                  <name>LOWER</name>
11604                  <description>Cycle time lower limit.  Set the lower limit -1, in reference clock cycles, before the next monitored clock event is allowed to happen.  If a monitored clock event happens before this limit is reached a CSV error is detected.
11605LOWER must be at least 1 less than UPPER. In case the clocks are asynchronous LOWER must be at least 3 less than UPPER.</description>
11606                  <bitRange>[7:0]</bitRange>
11607                  <access>read-write</access>
11608                </field>
11609                <field>
11610                  <name>UPPER</name>
11611                  <description>Cycle time upper limit.  Set the upper limit -1, in reference clock cycles, before (or same time) the next monitored clock event must happen.  If a monitored clock event does not happen before this limit is reached, or does not happen at all (clock loss), a CSV error is detected.</description>
11612                  <bitRange>[23:16]</bitRange>
11613                  <access>read-write</access>
11614                </field>
11615              </fields>
11616            </register>
11617            <register>
11618              <name>MON_CTL</name>
11619              <description>Clock Supervision Monitor Control</description>
11620              <addressOffset>0x8</addressOffset>
11621              <size>32</size>
11622              <access>read-write</access>
11623              <resetValue>0x0</resetValue>
11624              <resetMask>0xFF</resetMask>
11625              <fields>
11626                <field>
11627                  <name>PERIOD</name>
11628                  <description>Period time.  Set the Period -1, in monitored clock cycles, before the next monitored clock event happens.
11629PERIOD &lt;=  (UPPER+1) / FREQ_RATIO -1, with FREQ_RATIO = (Reference frequency / Monitored frequency)
11630In case the clocks are asynchronous: PERIOD &lt;=  UPPER / FREQ_RATIO -1
11631Additionally margin must be added for accuracy of both clocks.</description>
11632                  <bitRange>[7:0]</bitRange>
11633                  <access>read-write</access>
11634                </field>
11635              </fields>
11636            </register>
11637          </cluster>
11638        </cluster>
11639        <cluster>
11640          <name>CSV_ILO</name>
11641          <description>CSV registers for ILO clock</description>
11642          <headerStructName>CSV_ILO</headerStructName>
11643          <addressOffset>0x00001730</addressOffset>
11644          <cluster>
11645            <name>CSV</name>
11646            <description>HVILO clock DeepSleep domain Clock Supervisor registers</description>
11647            <headerStructName>CSV_ILO_CSV</headerStructName>
11648            <addressOffset>0x00000000</addressOffset>
11649            <register>
11650              <name>REF_CTL</name>
11651              <description>Clock Supervision Reference Control</description>
11652              <addressOffset>0x0</addressOffset>
11653              <size>32</size>
11654              <access>read-write</access>
11655              <resetValue>0x0</resetValue>
11656              <resetMask>0x800000FF</resetMask>
11657              <fields>
11658                <field>
11659                  <name>STARTUP</name>
11660                  <description>Startup delay time -1 (in reference clock cycles), after enable, from reference clock start to monitored clock start.
11661At a minimum (both clocks running): STARTUP &gt;= (PERIOD +3) * FREQ_RATIO - UPPER, with FREQ_RATIO = (Reference frequency / Monitored frequency)
11662On top of that the actual clock startup delay and the margin for accuracy of both clocks must be added.</description>
11663                  <bitRange>[7:0]</bitRange>
11664                  <access>read-write</access>
11665                </field>
11666                <field>
11667                  <name>CSV_EN</name>
11668                  <description>Enables clock supervision, both frequency and loss.
11669CSV in Active domain: Clock supervision is reset during DeepSleep and Hibernate modes.  When enabled it begins operating automatically after a DeepSleep wakeup, but it must be reconfigured after Hibernate wakeup.
11670CSV in DeepSleep domain: Clock supervision is reset during Hibernate mode.  It must be reconfigured after Hibernate wakeup.
11671CSV in Backup domain: Clock supervision operates during Hibernate mode, can be configured to wake from Hibernate, and continues operating during reboot.
11672
11673A CSV error detection is reported to the Fault structure.</description>
11674                  <bitRange>[31:31]</bitRange>
11675                  <access>read-write</access>
11676                </field>
11677              </fields>
11678            </register>
11679            <register>
11680              <name>REF_LIMIT</name>
11681              <description>Clock Supervision Reference Limits</description>
11682              <addressOffset>0x4</addressOffset>
11683              <size>32</size>
11684              <access>read-write</access>
11685              <resetValue>0x0</resetValue>
11686              <resetMask>0xFF00FF</resetMask>
11687              <fields>
11688                <field>
11689                  <name>LOWER</name>
11690                  <description>Cycle time lower limit.  Set the lower limit -1, in reference clock cycles, before the next monitored clock event is allowed to happen.  If a monitored clock event happens before this limit is reached a CSV error is detected.
11691LOWER must be at least 1 less than UPPER. In case the clocks are asynchronous LOWER must be at least 3 less than UPPER.</description>
11692                  <bitRange>[7:0]</bitRange>
11693                  <access>read-write</access>
11694                </field>
11695                <field>
11696                  <name>UPPER</name>
11697                  <description>Cycle time upper limit.  Set the upper limit -1, in reference clock cycles, before (or same time) the next monitored clock event must happen.  If a monitored clock event does not happen before this limit is reached, or does not happen at all (clock loss), a CSV error is detected.</description>
11698                  <bitRange>[23:16]</bitRange>
11699                  <access>read-write</access>
11700                </field>
11701              </fields>
11702            </register>
11703            <register>
11704              <name>MON_CTL</name>
11705              <description>Clock Supervision Monitor Control</description>
11706              <addressOffset>0x8</addressOffset>
11707              <size>32</size>
11708              <access>read-write</access>
11709              <resetValue>0x0</resetValue>
11710              <resetMask>0xFF</resetMask>
11711              <fields>
11712                <field>
11713                  <name>PERIOD</name>
11714                  <description>Period time.  Set the Period -1, in monitored clock cycles, before the next monitored clock event happens.
11715PERIOD &lt;=  (UPPER+1) / FREQ_RATIO -1, with FREQ_RATIO = (Reference frequency / Monitored frequency)
11716In case the clocks are asynchronous: PERIOD &lt;=  UPPER / FREQ_RATIO -1
11717Additionally margin must be added for accuracy of both clocks.</description>
11718                  <bitRange>[7:0]</bitRange>
11719                  <access>read-write</access>
11720                </field>
11721              </fields>
11722            </register>
11723          </cluster>
11724        </cluster>
11725        <register>
11726          <name>RES_CAUSE</name>
11727          <description>Reset Cause Observation Register</description>
11728          <addressOffset>0x1800</addressOffset>
11729          <size>32</size>
11730          <access>read-write</access>
11731          <resetValue>0x0</resetValue>
11732          <resetMask>0x1FF</resetMask>
11733          <fields>
11734            <field>
11735              <name>RESET_WDT</name>
11736              <description>A basic WatchDog Timer (WDT) reset has occurred since last power cycle.  ULP products: This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above).
11737
11738For products that support high-voltage cause detection, this bit blocks recording of other high-voltage cause bits, except RESET_PORVDDD.  Hardware clears this bit during POR.  This bit is not blocked by other HV cause bits.</description>
11739              <bitRange>[0:0]</bitRange>
11740              <access>read-write</access>
11741            </field>
11742            <field>
11743              <name>RESET_ACT_FAULT</name>
11744              <description>N/A</description>
11745              <bitRange>[1:1]</bitRange>
11746              <access>read-write</access>
11747            </field>
11748            <field>
11749              <name>RESET_DPSLP_FAULT</name>
11750              <description>N/A</description>
11751              <bitRange>[2:2]</bitRange>
11752              <access>read-write</access>
11753            </field>
11754            <field>
11755              <name>RESET_TC_DBGRESET</name>
11756              <description>Test controller or debugger asserted reset. Only resets debug domain.  This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above).</description>
11757              <bitRange>[3:3]</bitRange>
11758              <access>read-write</access>
11759            </field>
11760            <field>
11761              <name>RESET_SOFT</name>
11762              <description>A CPU requested a system reset through it's SYSRESETREQ.  This can be done via a debugger probe or in firmware.  This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above).</description>
11763              <bitRange>[4:4]</bitRange>
11764              <access>read-write</access>
11765            </field>
11766            <field>
11767              <name>RESET_MCWDT0</name>
11768              <description>Multi-Counter Watchdog timer reset #0.  This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above).</description>
11769              <bitRange>[5:5]</bitRange>
11770              <access>read-write</access>
11771            </field>
11772            <field>
11773              <name>RESET_MCWDT1</name>
11774              <description>Multi-Counter Watchdog timer reset #1.  This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above).</description>
11775              <bitRange>[6:6]</bitRange>
11776              <access>read-write</access>
11777            </field>
11778            <field>
11779              <name>RESET_MCWDT2</name>
11780              <description>Multi-Counter Watchdog timer reset #2.  This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above).</description>
11781              <bitRange>[7:7]</bitRange>
11782              <access>read-write</access>
11783            </field>
11784            <field>
11785              <name>RESET_MCWDT3</name>
11786              <description>Multi-Counter Watchdog timer reset #3.  This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above).</description>
11787              <bitRange>[8:8]</bitRange>
11788              <access>read-write</access>
11789            </field>
11790          </fields>
11791        </register>
11792        <register>
11793          <name>RES_CAUSE2</name>
11794          <description>Reset Cause Observation Register 2</description>
11795          <addressOffset>0x1804</addressOffset>
11796          <size>32</size>
11797          <access>read-write</access>
11798          <resetValue>0x0</resetValue>
11799          <resetMask>0x1FFFF</resetMask>
11800          <fields>
11801            <field>
11802              <name>RESET_CSV_HF</name>
11803              <description>Clock supervision logic requested a reset due to loss or frequency violation of a high-frequency clock.  Each bit index K corresponds to a HFCLK&lt;K&gt;.  Unimplemented clock bits return zero.</description>
11804              <bitRange>[15:0]</bitRange>
11805              <access>read-write</access>
11806            </field>
11807            <field>
11808              <name>RESET_CSV_REF</name>
11809              <description>Clock supervision logic requested a reset due to loss or frequency violation of the reference clock source that is used to monitor the other HF clock sources.</description>
11810              <bitRange>[16:16]</bitRange>
11811              <access>read-write</access>
11812            </field>
11813          </fields>
11814        </register>
11815        <register>
11816          <name>RES_CAUSE_EXTEND</name>
11817          <description>Extended Reset Cause Observation Register</description>
11818          <addressOffset>0x1808</addressOffset>
11819          <size>32</size>
11820          <access>read-write</access>
11821          <resetValue>0x40000000</resetValue>
11822          <resetMask>0x77FF0000</resetMask>
11823          <fields>
11824            <field>
11825              <name>RESET_XRES</name>
11826              <description>External XRES pin was asserted.  This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.  Hardware clears this bit during POR.  This bit is not blocked by other HV cause bits.</description>
11827              <bitRange>[16:16]</bitRange>
11828              <access>read-write</access>
11829            </field>
11830            <field>
11831              <name>RESET_BODVDDD</name>
11832              <description>External VDDD supply crossed brown-out limit.  Note that this cause will only be observable as long as the VDDD supply does not go below the POR (power on reset) detection limit.  Below this limit it is not possible to reliably retain information in the device.  This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.  Hardware clears this bit during POR.</description>
11833              <bitRange>[17:17]</bitRange>
11834              <access>read-write</access>
11835            </field>
11836            <field>
11837              <name>RESET_BODVDDA</name>
11838              <description>External VDDA supply crossed the brown-out limit.  This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.  Hardware clears this bit during POR.</description>
11839              <bitRange>[18:18]</bitRange>
11840              <access>read-write</access>
11841            </field>
11842            <field>
11843              <name>RESET_BODVCCD</name>
11844              <description>Internal VCCD core supply crossed the brown-out limit.  Note that this detector will detect gross issues with the internal core supply, but may not catch all brown-out conditions.  Functional and timing supervision (CSV, WDT) is provided to create fully failsafe internal crash detection.  This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.  Hardware clears this bit during POR.</description>
11845              <bitRange>[19:19]</bitRange>
11846              <access>read-write</access>
11847            </field>
11848            <field>
11849              <name>RESET_OVDVDDD</name>
11850              <description>Overvoltage detection on the external VDDD supply.  This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.  Hardware clears this bit during POR.</description>
11851              <bitRange>[20:20]</bitRange>
11852              <access>read-write</access>
11853            </field>
11854            <field>
11855              <name>RESET_OVDVDDA</name>
11856              <description>Overvoltage detection on the external VDDA supply.  This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.  Hardware clears this bit during POR.</description>
11857              <bitRange>[21:21]</bitRange>
11858              <access>read-write</access>
11859            </field>
11860            <field>
11861              <name>RESET_OVDVCCD</name>
11862              <description>Overvoltage detection on the internal core VCCD supply.  This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.  Hardware clears this bit during POR.</description>
11863              <bitRange>[22:22]</bitRange>
11864              <access>read-write</access>
11865            </field>
11866            <field>
11867              <name>RESET_OCD_ACT_LINREG</name>
11868              <description>Overcurrent detection on the internal VCCD supply when supplied by the ACTIVE power mode linear regulator.  This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.  Hardware clears this bit during POR.</description>
11869              <bitRange>[23:23]</bitRange>
11870              <access>read-write</access>
11871            </field>
11872            <field>
11873              <name>RESET_OCD_DPSLP_LINREG</name>
11874              <description>Overcurrent detection on the internal VCCD supply when supplied by the DEEPSLEEP power mode linear regulator.  This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.  Hardware clears this bit during POR.</description>
11875              <bitRange>[24:24]</bitRange>
11876              <access>read-write</access>
11877            </field>
11878            <field>
11879              <name>RESET_OCD_REGHC</name>
11880              <description>Overcurrent detection from REGHC (if present).  If REGHC is not present, hardware will never set this bit.  This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.  Hardware clears this bit during POR.</description>
11881              <bitRange>[25:25]</bitRange>
11882              <access>read-write</access>
11883            </field>
11884            <field>
11885              <name>RESET_PMIC</name>
11886              <description>PMIC status triggered a reset.  If PMIC control is not present, hardware will never set this bit.  This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.  Hardware clears this bit during POR.</description>
11887              <bitRange>[26:26]</bitRange>
11888              <access>read-write</access>
11889            </field>
11890            <field>
11891              <name>RESET_PXRES</name>
11892              <description>PXRES triggered.  This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.  Hardware clears this bit during POR.  This bit is not blocked by other HV cause bits.</description>
11893              <bitRange>[28:28]</bitRange>
11894              <access>read-write</access>
11895            </field>
11896            <field>
11897              <name>RESET_STRUCT_XRES</name>
11898              <description>Structural reset was asserted.  This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.  Hardware clears this bit during POR.  This bit is not blocked by other HV cause bits.</description>
11899              <bitRange>[29:29]</bitRange>
11900              <access>read-write</access>
11901            </field>
11902            <field>
11903              <name>RESET_PORVDDD</name>
11904              <description>Indicator that a POR occurred.  This is a high-voltage cause bit, and hardware clears the other bits when this one is set.  It does not block further recording of other high-voltage causes.</description>
11905              <bitRange>[30:30]</bitRange>
11906              <access>read-write</access>
11907            </field>
11908          </fields>
11909        </register>
11910        <register>
11911          <name>RES_PXRES_CTL</name>
11912          <description>Programmable XRES Control Register</description>
11913          <addressOffset>0x1814</addressOffset>
11914          <size>32</size>
11915          <access>write-only</access>
11916          <resetValue>0x0</resetValue>
11917          <resetMask>0x1</resetMask>
11918          <fields>
11919            <field>
11920              <name>PXRES_TRIGGER</name>
11921              <description>Triggers PXRES.  This causes a full-scope reset and reboot.</description>
11922              <bitRange>[0:0]</bitRange>
11923              <access>write-only</access>
11924            </field>
11925          </fields>
11926        </register>
11927        <cluster>
11928          <dim>15</dim>
11929          <dimIncrement>16</dimIncrement>
11930          <name>CLK_PLL400M[%s]</name>
11931          <description>400MHz PLL Configuration Register</description>
11932          <headerStructName>CLK_PLL400M</headerStructName>
11933          <addressOffset>0x00001900</addressOffset>
11934          <register>
11935            <name>CONFIG</name>
11936            <description>400MHz PLL Configuration Register</description>
11937            <addressOffset>0x0</addressOffset>
11938            <size>32</size>
11939            <access>read-write</access>
11940            <resetValue>0x20116</resetValue>
11941            <resetMask>0xB61F1FFF</resetMask>
11942            <fields>
11943              <field>
11944                <name>FEEDBACK_DIV</name>
11945                <description>Control bits for feedback divider.  Set the divide value before enabling the PLL, and do not change it while PLL is enabled.
119460-15: illegal (undefined behavior)
1194716: divide by 16
11948...
11949200: divide by 200
11950&gt;200: illegal (undefined behavior)
11951
11952When using fractional mode, the jitter specs are met over the restricted range of 27 to 47, inclusive.</description>
11953                <bitRange>[7:0]</bitRange>
11954                <access>read-write</access>
11955              </field>
11956              <field>
11957                <name>REFERENCE_DIV</name>
11958                <description>Control bits for reference divider.  Set the divide value before enabling the PLL, and do not change it while PLL is enabled.
119590: illegal (undefined behavior)
119601: divide by 1
11961...
1196216: divide by 16
11963others: illegal (undefined behavior)
11964
11965When using fractional mode, the jitter specs are met over the restricted range of 1 to 4, inclusive.</description>
11966                <bitRange>[12:8]</bitRange>
11967                <access>read-write</access>
11968              </field>
11969              <field>
11970                <name>OUTPUT_DIV</name>
11971                <description>Control bits for Output divider.  Set the divide value before enabling the PLL, and do not change it while PLL is enabled.
119720: illegal (undefined behavior)
119731: illegal (undefined behavior)
119742: divide by 2.  Suitable for direct usage as HFCLK source.
11975...
1197616: divide by 16.  Suitable for direct usage as HFCLK source.
11977&gt;16: illegal (undefined behavior)</description>
11978                <bitRange>[20:16]</bitRange>
11979                <access>read-write</access>
11980              </field>
11981              <field>
11982                <name>LOCK_DELAY</name>
11983                <description>N/A</description>
11984                <bitRange>[26:25]</bitRange>
11985                <access>read-write</access>
11986              </field>
11987              <field>
11988                <name>BYPASS_SEL</name>
11989                <description>Bypass mux located just after PLL output.  This selection is glitch-free and can be changed while the PLL is running.  When changing BYPASS_SEL, do not turn off the reference clock or PLL clock for five cycles (whichever is slower).</description>
11990                <bitRange>[29:28]</bitRange>
11991                <access>read-write</access>
11992                <enumeratedValues>
11993                  <enumeratedValue>
11994                    <name>AUTO</name>
11995                    <description>Automatic using lock indicator.  When unlocked, automatically selects PLL reference input (bypass mode).  When locked, automatically selects PLL output.  If ENABLE=0, automatically selects PLL reference input.</description>
11996                    <value>0</value>
11997                  </enumeratedValue>
11998                  <enumeratedValue>
11999                    <name>LOCKED_OR_NOTHING</name>
12000                    <description>Similar to AUTO, except the clock is gated off when unlocked.  This is compatible with clock supervision, because the supervisors allow no clock during startup (until a timeout occurs), and the clock targets the proper frequency whenever it is running.  If ENABLE=0, no clock is output.</description>
12001                    <value>1</value>
12002                  </enumeratedValue>
12003                  <enumeratedValue>
12004                    <name>PLL_BYPASS</name>
12005                    <description>Select PLL reference input (bypass mode).  Ignores lock indicator</description>
12006                    <value>2</value>
12007                  </enumeratedValue>
12008                  <enumeratedValue>
12009                    <name>PLL_OUT</name>
12010                    <description>Select PLL output.  Ignores lock indicator.  If ENABLE=0, no clock is output.</description>
12011                    <value>3</value>
12012                  </enumeratedValue>
12013                </enumeratedValues>
12014              </field>
12015              <field>
12016                <name>ENABLE</name>
12017                <description>Master enable for PLL.  Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1.
12018
12019fOUT = (FEEDBACK_DIV + FRAC_EN*FRAC_DIV/2^24)  * (fREF / REFERENCE_DIV) / (OUTPUT_DIV)
12020
120210: Block is disabled.  When the PLL disables, hardware controls the bypass mux as described in BYPASS_SEL, before disabling the PLL circuit.
120221: Block is enabled</description>
12023                <bitRange>[31:31]</bitRange>
12024                <access>read-write</access>
12025              </field>
12026            </fields>
12027          </register>
12028          <register>
12029            <name>CONFIG2</name>
12030            <description>400MHz PLL Configuration Register 2</description>
12031            <addressOffset>0x4</addressOffset>
12032            <size>32</size>
12033            <access>read-write</access>
12034            <resetValue>0x0</resetValue>
12035            <resetMask>0xF0FFFFFF</resetMask>
12036            <fields>
12037              <field>
12038                <name>FRAC_DIV</name>
12039                <description>Control bits for fractional divider.  This value is interpreted as a fraction of the PFD frequency, i.e. fPFD * (FRAC_DIV/2^24).  This field can be dynamically updated within the 1000ppm control limit. It takes up to 115 AHB cycles to transfer the setting to the PLL, and writes that occur faster may be silently ignored and require the application to write again after the previous update has finished.  Reading the register returns the accepted value.  The PLL will start targeting the new value, but it may take significant time (milliseconds) to stabilize at the new average value.  Do not change the FRAC_DIV setting while the PLL is initially locking.</description>
12040                <bitRange>[23:0]</bitRange>
12041                <access>read-write</access>
12042              </field>
12043              <field>
12044                <name>FRAC_DITHER_EN</name>
12045                <description>N/A</description>
12046                <bitRange>[30:28]</bitRange>
12047                <access>read-write</access>
12048              </field>
12049              <field>
12050                <name>FRAC_EN</name>
12051                <description>Enables fractional division mode.  When using fractional division mode, see CLK_PLL400M_CONFIG.LOCK_DELAY for an additional configuration requirement.</description>
12052                <bitRange>[31:31]</bitRange>
12053                <access>read-write</access>
12054              </field>
12055            </fields>
12056          </register>
12057          <register>
12058            <name>CONFIG3</name>
12059            <description>400MHz PLL Configuration Register 3</description>
12060            <addressOffset>0x8</addressOffset>
12061            <size>32</size>
12062            <access>read-write</access>
12063            <resetValue>0x0</resetValue>
12064            <resetMask>0x910703FF</resetMask>
12065            <fields>
12066              <field>
12067                <name>SSCG_DEPTH</name>
12068                <description>N/A</description>
12069                <bitRange>[9:0]</bitRange>
12070                <access>read-write</access>
12071              </field>
12072              <field>
12073                <name>SSCG_RATE</name>
12074                <description>N/A</description>
12075                <bitRange>[18:16]</bitRange>
12076                <access>read-write</access>
12077              </field>
12078              <field>
12079                <name>SSCG_DITHER_EN</name>
12080                <description>Enables dithering during spreading.
120810: disabled
120821: enabled</description>
12083                <bitRange>[24:24]</bitRange>
12084                <access>read-write</access>
12085              </field>
12086              <field>
12087                <name>SSCG_MODE</name>
12088                <description>N/A</description>
12089                <bitRange>[28:28]</bitRange>
12090                <access>read-write</access>
12091              </field>
12092              <field>
12093                <name>SSCG_EN</name>
12094                <description>Enables spreading mode.  When using spreading, see CLK_PLL400M_CONFIG.LOCK_DELAY for an additional configuration requirement.</description>
12095                <bitRange>[31:31]</bitRange>
12096                <access>read-write</access>
12097              </field>
12098            </fields>
12099          </register>
12100          <register>
12101            <name>STATUS</name>
12102            <description>400MHz PLL Status Register</description>
12103            <addressOffset>0xC</addressOffset>
12104            <size>32</size>
12105            <access>read-write</access>
12106            <resetValue>0x0</resetValue>
12107            <resetMask>0x3</resetMask>
12108            <fields>
12109              <field>
12110                <name>LOCKED</name>
12111                <description>PLL Lock Indicator</description>
12112                <bitRange>[0:0]</bitRange>
12113                <access>read-only</access>
12114              </field>
12115              <field>
12116                <name>UNLOCK_OCCURRED</name>
12117                <description>This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.</description>
12118                <bitRange>[1:1]</bitRange>
12119                <access>read-write</access>
12120              </field>
12121            </fields>
12122          </register>
12123        </cluster>
12124        <register>
12125          <name>PWR_CBUCK_CTL</name>
12126          <description>Core Buck Control Register</description>
12127          <addressOffset>0x1C00</addressOffset>
12128          <size>32</size>
12129          <access>read-write</access>
12130          <resetValue>0x1114</resetValue>
12131          <resetMask>0x1F1F</resetMask>
12132          <fields>
12133            <field>
12134              <name>CBUCK_VSEL</name>
12135              <description>Voltage output selection.  This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset.   The actual CBUCK voltage is the maximum of this setting, the settings for all enabled step-down regulators (see PWR_SDR*_CTL), and the minimum DEEPSLEEP setting (which is not user configurable).  These settings follow the formula (0.76+0.02*CBUCK_VSEL).
121360: 0.76V, 1: 0.78V, 2: 0.80V, 3: 0.82V, 4: 0.84V, 5: 0.86V, 6: 0.88V, 7: 0.90V, 8: 0.92V, 9: 0.94V, 10: 0.96V, 11: 0.98V, 12: 1.00V, 13: 1.02V, 14: 1.04V, 15: 1.06V, 16: 1.08V, 17: 1.10V, 18: 1.12V, 19: 1.14V, 20: 1.16V, 21: 1.18V, 22: 1.20V, 23: 1.22V, 24: 1.24V, 25: 1.26V, 26: 1.28V, 27: 1.30V, 28: 1.32V, 29: 1.34V, 30: 1.36V, 31: 1.38V.</description>
12137              <bitRange>[4:0]</bitRange>
12138              <access>read-write</access>
12139            </field>
12140            <field>
12141              <name>CBUCK_MODE</name>
12142              <description>CBUCK mode.  Low ripple (high power) modes are intended for analog that needs low ripple.  Low power mode is suitable for digital processing.
12143The CBUCK mode is defined as = {mode*_sr_mode, mode*_sr_hp_submode[1:0], mode*_sr_lp_submode[1:0]}
12144The actual CBUCK mode is the maximum of this setting and the settings of all enabled step-down regulators.
121450x11: HP, PFM Auto, High-Low (default Active)
121460x01: LP, PFM Auto, High-Low (DeepSleep)
12147See s40power BROS for other settings</description>
12148              <bitRange>[12:8]</bitRange>
12149              <access>read-write</access>
12150            </field>
12151          </fields>
12152        </register>
12153        <register>
12154          <name>PWR_CBUCK_CTL2</name>
12155          <description>Core Buck Control Register 2</description>
12156          <addressOffset>0x1C04</addressOffset>
12157          <size>32</size>
12158          <access>read-write</access>
12159          <resetValue>0x0</resetValue>
12160          <resetMask>0xF0000000</resetMask>
12161          <fields>
12162            <field>
12163              <name>CBUCK_OVERRIDE</name>
12164              <description>Forces the CBUCK to use the settings in PWR_CBUCK_CTL register, ignoring the other hardware requests.  This can be used as part of a firmware algorithm to change the voltage of an enabled stepdown regulator.  This bit is cleared by any reset.</description>
12165              <bitRange>[28:28]</bitRange>
12166              <access>read-write</access>
12167            </field>
12168            <field>
12169              <name>CBUCK_PAUSE</name>
12170              <description>Pauses new dynamic CBUCK transitions.  An already started transition will complete, but new dynamic transitions are paused.  This can be used as part of a firmware sequence to change the voltage setting of an enabled stepdown regulator.</description>
12171              <bitRange>[29:29]</bitRange>
12172              <access>read-write</access>
12173            </field>
12174            <field>
12175              <name>CBUCK_COPY_SETTINGS</name>
12176              <description>Copies the current CBUCK composite state to the fields in  PWR_CBUCK_CTL register (CBUCK_VSEL and CBUCK_MODE).  It is recommended to pause transitions using CBUCK_PAUSE to ensure the state does not change near the copy.  After it is copied, the CBUCK_OVERRIDE bit can be used to hold the CBUCK in the current state.  Note, reading this bit always returns 0.
121770: no change
121781: copy settings.</description>
12179              <bitRange>[30:30]</bitRange>
12180              <access>read-write</access>
12181            </field>
12182            <field>
12183              <name>CBUCK_USE_SETTINGS</name>
12184              <description>Causes the settings in  PWR_CBUCK_CTL register to be included in the CBUCK setting decision.  Can be used to override the normal hardware voltage behavior.  Regardless of this bit, the extra settings in  PWR_CBUCK_CTL register are not used during DEEPSLEEP.</description>
12185              <bitRange>[31:31]</bitRange>
12186              <access>read-write</access>
12187            </field>
12188          </fields>
12189        </register>
12190        <register>
12191          <name>PWR_CBUCK_CTL3</name>
12192          <description>Core Buck Control Register 3</description>
12193          <addressOffset>0x1C08</addressOffset>
12194          <size>32</size>
12195          <access>read-write</access>
12196          <resetValue>0x0</resetValue>
12197          <resetMask>0x80000000</resetMask>
12198          <fields>
12199            <field>
12200              <name>CBUCK_INRUSH_SEL</name>
12201              <description>CBUCK inrush limit selection.
122020: 10mA limit.
122031: 100mA limit.</description>
12204              <bitRange>[31:31]</bitRange>
12205              <access>read-write</access>
12206            </field>
12207          </fields>
12208        </register>
12209        <register>
12210          <name>PWR_CBUCK_STATUS</name>
12211          <description>Core Buck Status Register</description>
12212          <addressOffset>0x1C0C</addressOffset>
12213          <size>32</size>
12214          <access>read-only</access>
12215          <resetValue>0x0</resetValue>
12216          <resetMask>0x80000000</resetMask>
12217          <fields>
12218            <field>
12219              <name>PMU_DONE</name>
12220              <description>Indicates the power management unit is finished with a transition.
122210: PMU busy
122221: PMU done</description>
12223              <bitRange>[31:31]</bitRange>
12224              <access>read-only</access>
12225            </field>
12226          </fields>
12227        </register>
12228        <register>
12229          <name>PWR_SDR0_CTL</name>
12230          <description>Step Down Regulator 0 Control Register</description>
12231          <addressOffset>0x1C10</addressOffset>
12232          <size>32</size>
12233          <access>read-write</access>
12234          <resetValue>0x8A09E34</resetValue>
12235          <resetMask>0xBCFFFFFF</resetMask>
12236          <fields>
12237            <field>
12238              <name>SDR0_CBUCK_VSEL</name>
12239              <description>Minimum voltage selection of CBUCK when using this SDR0 (see PWR_CBUCK_CTL for voltage table).  The voltage must be 60mV higher than the SDR output or the regulator output may bypass.</description>
12240              <bitRange>[4:0]</bitRange>
12241              <access>read-write</access>
12242            </field>
12243            <field>
12244              <name>SDR0_CBUCK_MODE</name>
12245              <description>Minimum CBUCK mode when using SDR0 (see PWR_CBUCK_CTL for mode table).
12246Default Active</description>
12247              <bitRange>[9:5]</bitRange>
12248              <access>read-write</access>
12249            </field>
12250            <field>
12251              <name>SDR0_CBUCK_DPSLP_VSEL</name>
12252              <description>DeepSleep voltage selection of CBUCK (see PWR_CBUCK_CTL for voltage table).  The voltage must be 60mV higher than the SDR output or the regulator output may bypass.</description>
12253              <bitRange>[14:10]</bitRange>
12254              <access>read-write</access>
12255            </field>
12256            <field>
12257              <name>SDR0_CBUCK_DPSLP_MODE</name>
12258              <description>DeepSleep CBUCK mode when using SDR0 (see PWR_CBUCK_CTL for mode table).
12259Default DeepSleep</description>
12260              <bitRange>[19:15]</bitRange>
12261              <access>read-write</access>
12262            </field>
12263            <field>
12264              <name>SDR0_VSEL</name>
12265              <description>SDR0 output voltage.
122660: 0.850V, 1: 0.875V, 2: 0.900V, 3: 0.925V, 4: 0.950V, 5: 0.975V, 6: 1.000V, 7: 1.025V, 8: 1.050V, 9: 1.075V, 10: 1.100V, 11: 1.125V, 12: 1.150V, 13: 1.175V, 14: 1.200V, 15: 1.225V</description>
12267              <bitRange>[23:20]</bitRange>
12268              <access>read-write</access>
12269            </field>
12270            <field>
12271              <name>SDR0_DPSLP_VSEL</name>
12272              <description>SDR0 output voltage during DeepSleep.  (See SDR0_VSEL for voltage table).</description>
12273              <bitRange>[29:26]</bitRange>
12274              <access>read-write</access>
12275            </field>
12276            <field>
12277              <name>SDR0_ALLOW_BYPASS</name>
12278              <description>SDR0 bypass control.
122790: Force SDR0 to regulate.
122801: Allow SDR0 to bypass if the actual CBUCK voltage matches SDR0_CBUCK_VSEL.</description>
12281              <bitRange>[31:31]</bitRange>
12282              <access>read-write</access>
12283            </field>
12284          </fields>
12285        </register>
12286        <register>
12287          <name>PWR_SDR1_CTL</name>
12288          <description>Step Down Regulator 1 Control Register</description>
12289          <addressOffset>0x1C14</addressOffset>
12290          <size>32</size>
12291          <access>read-write</access>
12292          <resetValue>0x400A1114</resetValue>
12293          <resetMask>0xC00F1F1F</resetMask>
12294          <fields>
12295            <field>
12296              <name>SDR1_CBUCK_VSEL</name>
12297              <description>Minimum voltage selection of CBUCK when using this SDR1 (see PWR_CBUCK_CTL for voltage table).  The voltage must be 60mV higher than the SDR output or the regulator output may bypass.</description>
12298              <bitRange>[4:0]</bitRange>
12299              <access>read-write</access>
12300            </field>
12301            <field>
12302              <name>SDR1_CBUCK_MODE</name>
12303              <description>Minimum CBUCK mode when using SDR1 (see PWR_CBUCK_CTL for mode table).</description>
12304              <bitRange>[12:8]</bitRange>
12305              <access>read-write</access>
12306            </field>
12307            <field>
12308              <name>SDR1_VSEL</name>
12309              <description>SDR1 output voltage.
123100: 0.850V, 1: 0.875V, 2: 0.900V, 3: 0.925V, 4: 0.950V, 5: 0.975V, 6: 1.000V, 7: 1.025V, 8: 1.050V, 9: 1.075V, 10: 1.100V, 11: 1.125V, 12: 1.150V, 13: 1.175V, 14: 1.200V, 15: 1.225V</description>
12311              <bitRange>[19:16]</bitRange>
12312              <access>read-write</access>
12313            </field>
12314            <field>
12315              <name>SDR1_HW_SEL</name>
12316              <description>Selects hardware control for SDR1.
123170: SDR1_ENABLE controls SDR1.  Hardware controls are ignored.
123181: SDR1_ENABLE is ignored and a hardware signal is used instead.  Selecting this on products that don't have supporting hardware will disable SDR1.</description>
12319              <bitRange>[30:30]</bitRange>
12320              <access>read-write</access>
12321            </field>
12322            <field>
12323              <name>SDR1_ENABLE</name>
12324              <description>Enable for SDR1.</description>
12325              <bitRange>[31:31]</bitRange>
12326              <access>read-write</access>
12327            </field>
12328          </fields>
12329        </register>
12330        <register>
12331          <name>PWR_HVLDO0_CTL</name>
12332          <description>HVLDO0 Control Register</description>
12333          <addressOffset>0x1C30</addressOffset>
12334          <size>32</size>
12335          <access>read-write</access>
12336          <resetValue>0x40000007</resetValue>
12337          <resetMask>0xC000000F</resetMask>
12338          <fields>
12339            <field>
12340              <name>HVLDO0_VSEL</name>
12341              <description>HVLDO0 output voltage.
123420: 1.8V, 1: 1.9V, 2: 2.0V, 3: 2.1V, 4: 2.2V, 5: 2.3V, 6: 2.4V, 7: 2.5V, 8: 2.6V, 9: 2.7V, 10: 2.8V, 11: 2.9V, 12: 3.0V, 13: 3.1V, 14: 3.2V, 15: 3.3V</description>
12343              <bitRange>[3:0]</bitRange>
12344              <access>read-write</access>
12345            </field>
12346            <field>
12347              <name>HVLDO0_HW_SEL</name>
12348              <description>Selects hardware control for HVLDO0.
123490: HVLDO0_ENABLE controls SDR1.  Hardware controls are ignored.
123501: HVLDO0_ENABLE is ignored and a hardware signal is used instead.  Selecting this on products that don't have supporting hardware will disable HVLDO0.</description>
12351              <bitRange>[30:30]</bitRange>
12352              <access>read-write</access>
12353            </field>
12354            <field>
12355              <name>HVLDO0_ENABLE</name>
12356              <description>HVLDO0 enable</description>
12357              <bitRange>[31:31]</bitRange>
12358              <access>read-write</access>
12359            </field>
12360          </fields>
12361        </register>
12362        <register>
12363          <name>TST_XRES_SECURE</name>
12364          <description>SECURE TEST and FIRMWARE TEST Key control register</description>
12365          <addressOffset>0x2054</addressOffset>
12366          <size>32</size>
12367          <access>read-write</access>
12368          <resetValue>0x0</resetValue>
12369          <resetMask>0xE00F0FFF</resetMask>
12370          <fields>
12371            <field>
12372              <name>DATA8</name>
12373              <description>Data byte to be set into either SECURE TEST or FIRMWARE TEST key.  Must not be changed in the same write that is toggling any of the *_WR bits below,</description>
12374              <bitRange>[7:0]</bitRange>
12375              <access>read-write</access>
12376            </field>
12377            <field>
12378              <name>FW_WR</name>
12379              <description>Latch enables for each of the 4 bytes in the 32-bit FIRMWARE TEST key.  Must be toggled high and then low while keeping DATA8 to the correct value.</description>
12380              <bitRange>[11:8]</bitRange>
12381              <access>read-write</access>
12382            </field>
12383            <field>
12384              <name>SECURE_WR</name>
12385              <description>Latch enables for each of the 4 bytes in the 32-bit SECURE TEST key.  Must be toggled high and then low while keeping DATA8 to the correct value.</description>
12386              <bitRange>[19:16]</bitRange>
12387              <access>read-write</access>
12388            </field>
12389            <field>
12390              <name>FW_KEY_OK</name>
12391              <description>Indicates that the 32-bit FIRMWARE TEST key is observing the correct key.  Firmware key is reset by (A)XRES and STRUCT_XRES.</description>
12392              <bitRange>[29:29]</bitRange>
12393              <access>read-only</access>
12394            </field>
12395            <field>
12396              <name>SECURE_KEY_OK</name>
12397              <description>Indicates that the 32-bit SECURE TEST key is observing the correct key.  Secure key is not reset, but it will establish low after a deep power cycle that causes it to lose its written state.</description>
12398              <bitRange>[30:30]</bitRange>
12399              <access>read-only</access>
12400            </field>
12401            <field>
12402              <name>SECURE_DISABLE</name>
12403              <description>Disables the SECURE TEST key entry capability until next reset.   Must not be set in the same write when any of the above *_WR bits are set or toggling.</description>
12404              <bitRange>[31:31]</bitRange>
12405              <access>read-write</access>
12406            </field>
12407          </fields>
12408        </register>
12409        <register>
12410          <name>PWR_TRIM_CBUCK_CTL</name>
12411          <description>CBUCK Trim Register</description>
12412          <addressOffset>0x20AC</addressOffset>
12413          <size>32</size>
12414          <access>read-write</access>
12415          <resetValue>0x107</resetValue>
12416          <resetMask>0x1F1F</resetMask>
12417          <fields>
12418            <field>
12419              <name>CBUCK_DPSLP_VSEL</name>
12420              <description>The CBUCK voltage setting to use during DEEPSLEEP.</description>
12421              <bitRange>[4:0]</bitRange>
12422              <access>read-write</access>
12423            </field>
12424            <field>
12425              <name>CBUCK_DPSLP_MODE</name>
12426              <description>The CBUCK mode setting to use during DEEPSLEEP.</description>
12427              <bitRange>[12:8]</bitRange>
12428              <access>read-write</access>
12429            </field>
12430          </fields>
12431        </register>
12432        <register>
12433          <name>CLK_TRIM_ECO_CTL</name>
12434          <description>ECO Trim Register</description>
12435          <addressOffset>0x301C</addressOffset>
12436          <size>32</size>
12437          <access>read-write</access>
12438          <resetValue>0x1F0000</resetValue>
12439          <resetMask>0x3F0000</resetMask>
12440          <fields>
12441            <field>
12442              <name>ITRIM</name>
12443              <description>Current Trim</description>
12444              <bitRange>[21:16]</bitRange>
12445              <access>read-write</access>
12446            </field>
12447          </fields>
12448        </register>
12449        <register>
12450          <name>CLK_TRIM_ILO1_CTL</name>
12451          <description>ILO1 Trim Register</description>
12452          <addressOffset>0x3220</addressOffset>
12453          <size>32</size>
12454          <access>read-write</access>
12455          <resetValue>0x52C</resetValue>
12456          <resetMask>0xF3F</resetMask>
12457          <fields>
12458            <field>
12459              <name>ILO1_FTRIM</name>
12460              <description>ILO1 frequency trims.  LSB step size is 1.5 percent (typical) of the frequency.</description>
12461              <bitRange>[5:0]</bitRange>
12462              <access>read-write</access>
12463            </field>
12464            <field>
12465              <name>ILO1_MONTRIM</name>
12466              <description>ILO1 internal monitor trim.</description>
12467              <bitRange>[11:8]</bitRange>
12468              <access>read-write</access>
12469            </field>
12470          </fields>
12471        </register>
12472        <register>
12473          <name>WDT_CTL</name>
12474          <description>Watchdog Counter Control Register (Type A)</description>
12475          <addressOffset>0xC000</addressOffset>
12476          <size>32</size>
12477          <access>read-write</access>
12478          <resetValue>0xC0000001</resetValue>
12479          <resetMask>0xC0000031</resetMask>
12480          <fields>
12481            <field>
12482              <name>WDT_EN</name>
12483              <description>Enable this watchdog timer.  This field is retained during DEEPSLEEP and HIBERNATE modes.</description>
12484              <bitRange>[0:0]</bitRange>
12485              <access>read-write</access>
12486            </field>
12487            <field>
12488              <name>WDT_CLK_SEL</name>
12489              <description>Select source for WDT.  Not all products support all clock sources.  Selecting a clock source that is not supported will result in undefined behavior.  Writes to this field are ignored unless the WDT is unlock using WDT_LOCK register.  It takes four cycles of the originally selected clock to switch away from it.  Do not disable the original clock during this time.</description>
12490              <bitRange>[5:4]</bitRange>
12491              <access>read-write</access>
12492              <enumeratedValues>
12493                <enumeratedValue>
12494                  <name>ILO</name>
12495                  <description>ILO - Internal Low-speed Oscillator</description>
12496                  <value>0</value>
12497                </enumeratedValue>
12498                <enumeratedValue>
12499                  <name>PILO</name>
12500                  <description>PILO - Precision ILO. If present, if present</description>
12501                  <value>1</value>
12502                </enumeratedValue>
12503                <enumeratedValue>
12504                  <name>BAK</name>
12505                  <description>BAK - Selected clk_bak source, if present.  See BACKUP_CTL.  This choice is not recommended for applications that rely upon the watchdog timer for safety or security, unless the product supports clock supervision of clk_bak (CSV_BAK).  Generation of clk_bak is not protected by WDT_LOCK and is in a different memory region with potentially different security attributes.</description>
12506                  <value>2</value>
12507                </enumeratedValue>
12508              </enumeratedValues>
12509            </field>
12510            <field>
12511              <name>WDT_LOCK</name>
12512              <description>Prohibits writing to WDT_*, CLK_ILO_CONFIG, CLK_SELECT.LFCLK_SEL, and CLK_TRIM_ILO_CTL registers when not equal 0.  Requires at least two different writes to unlock.  A change in WDT_LOCK takes effect beginning with the next write cycle.
12513Note that this field is 2 bits to force multiple writes only.  It represents only a single write protect signal protecting all those registers at the same time.  WDT will lock on any reset.  This field is not retained during DEEPSLEEP or HIBERNATE mode, so the WDT will be locked after wakeup from these modes.</description>
12514              <bitRange>[31:30]</bitRange>
12515              <access>read-write</access>
12516              <enumeratedValues>
12517                <enumeratedValue>
12518                  <name>NO_CHG</name>
12519                  <description>No effect</description>
12520                  <value>0</value>
12521                </enumeratedValue>
12522                <enumeratedValue>
12523                  <name>CLR0</name>
12524                  <description>Clears bit 0</description>
12525                  <value>1</value>
12526                </enumeratedValue>
12527                <enumeratedValue>
12528                  <name>CLR1</name>
12529                  <description>Clears bit 1</description>
12530                  <value>2</value>
12531                </enumeratedValue>
12532                <enumeratedValue>
12533                  <name>SET01</name>
12534                  <description>Sets both bits 0 and 1</description>
12535                  <value>3</value>
12536                </enumeratedValue>
12537              </enumeratedValues>
12538            </field>
12539          </fields>
12540        </register>
12541        <register>
12542          <name>WDT_CNT</name>
12543          <description>Watchdog Counter Count Register (Type A)</description>
12544          <addressOffset>0xC004</addressOffset>
12545          <size>32</size>
12546          <access>read-write</access>
12547          <resetValue>0x0</resetValue>
12548          <resetMask>0xFFFFFFFF</resetMask>
12549          <fields>
12550            <field>
12551              <name>COUNTER</name>
12552              <description>Current value of WDT Counter.  The write feature of this register is for engineering use (DfV), have no synchronization, and can only be applied when the WDT is fully off.  When writing, the value is updated immediately in the WDT counter, but it will read back as the old value until this register resynchronizes just after the negedge of ILO.  Writes will be ignored if they occur when the WDT is enabled.</description>
12553              <bitRange>[31:0]</bitRange>
12554              <access>read-write</access>
12555            </field>
12556          </fields>
12557        </register>
12558        <register>
12559          <name>WDT_MATCH</name>
12560          <description>Watchdog Counter Match Register (Type A)</description>
12561          <addressOffset>0xC008</addressOffset>
12562          <size>32</size>
12563          <access>read-write</access>
12564          <resetValue>0x1000</resetValue>
12565          <resetMask>0xFFFFFFFF</resetMask>
12566          <fields>
12567            <field>
12568              <name>MATCH</name>
12569              <description>Match value for Watchdog counter.  Every time WDT_COUNTER reaches MATCH an interrupt is generated.  Two unserviced interrupts will lead to a system reset (i.e. at the third match).</description>
12570              <bitRange>[31:0]</bitRange>
12571              <access>read-write</access>
12572            </field>
12573          </fields>
12574        </register>
12575        <register>
12576          <name>WDT_MATCH2</name>
12577          <description>Watchdog Counter Match Register 2 (Type A)</description>
12578          <addressOffset>0xC00C</addressOffset>
12579          <size>32</size>
12580          <access>read-write</access>
12581          <resetValue>0x1F</resetValue>
12582          <resetMask>0x1F</resetMask>
12583          <fields>
12584            <field>
12585              <name>IGNORE_BITS_ABOVE</name>
12586              <description>The bit index to be considered the MSB for matching.  Bit indices above this setting are NOT checked against MATCH.  This value provides control over the time-to-reset of the watchdog (which happens after 3 successive matches).  The four LSBs cannot be ignored for matching.  Settings &lt;3 behave like a setting of 3.  If the setting is higher than the number of bits in the WDT counter, all actual bits in the counter are matched.</description>
12587              <bitRange>[4:0]</bitRange>
12588              <access>read-write</access>
12589            </field>
12590          </fields>
12591        </register>
12592        <cluster>
12593          <name>MCWDT_STRUCT</name>
12594          <description>Multi-Counter Watchdog Timer (Type A)</description>
12595          <headerStructName>MCWDT_STRUCT</headerStructName>
12596          <addressOffset>0x0000D000</addressOffset>
12597          <register>
12598            <name>MCWDT_CNTLOW</name>
12599            <description>Multi-Counter Watchdog Sub-counters 0/1</description>
12600            <addressOffset>0x4</addressOffset>
12601            <size>32</size>
12602            <access>read-write</access>
12603            <resetValue>0x0</resetValue>
12604            <resetMask>0xFFFFFFFF</resetMask>
12605            <fields>
12606              <field>
12607                <name>WDT_CTR0</name>
12608                <description>Current value of sub-counter 0 for this MCWDT.  Software writes are ignored when the sub-counter is enabled.</description>
12609                <bitRange>[15:0]</bitRange>
12610                <access>read-write</access>
12611              </field>
12612              <field>
12613                <name>WDT_CTR1</name>
12614                <description>Current value of sub-counter 1 for this MCWDT.  Software writes are ignored when the sub-counter is enabled</description>
12615                <bitRange>[31:16]</bitRange>
12616                <access>read-write</access>
12617              </field>
12618            </fields>
12619          </register>
12620          <register>
12621            <name>MCWDT_CNTHIGH</name>
12622            <description>Multi-Counter Watchdog Sub-counter 2</description>
12623            <addressOffset>0x8</addressOffset>
12624            <size>32</size>
12625            <access>read-write</access>
12626            <resetValue>0x0</resetValue>
12627            <resetMask>0xFFFFFFFF</resetMask>
12628            <fields>
12629              <field>
12630                <name>WDT_CTR2</name>
12631                <description>Current value of sub-counter 2 for this MCWDT.  Software writes are ignored when the sub-counter is enabled</description>
12632                <bitRange>[31:0]</bitRange>
12633                <access>read-write</access>
12634              </field>
12635            </fields>
12636          </register>
12637          <register>
12638            <name>MCWDT_MATCH</name>
12639            <description>Multi-Counter Watchdog Counter Match Register</description>
12640            <addressOffset>0xC</addressOffset>
12641            <size>32</size>
12642            <access>read-write</access>
12643            <resetValue>0x0</resetValue>
12644            <resetMask>0xFFFFFFFF</resetMask>
12645            <fields>
12646              <field>
12647                <name>WDT_MATCH0</name>
12648                <description>Match value for sub-counter 0 of this MCWDT</description>
12649                <bitRange>[15:0]</bitRange>
12650                <access>read-write</access>
12651              </field>
12652              <field>
12653                <name>WDT_MATCH1</name>
12654                <description>Match value for sub-counter 1 of this MCWDT</description>
12655                <bitRange>[31:16]</bitRange>
12656                <access>read-write</access>
12657              </field>
12658            </fields>
12659          </register>
12660          <register>
12661            <name>MCWDT_CONFIG</name>
12662            <description>Multi-Counter Watchdog Counter Configuration</description>
12663            <addressOffset>0x10</addressOffset>
12664            <size>32</size>
12665            <access>read-write</access>
12666            <resetValue>0x0</resetValue>
12667            <resetMask>0x1F01FFFF</resetMask>
12668            <fields>
12669              <field>
12670                <name>WDT_MODE0</name>
12671                <description>Watchdog Counter Action on Match.  Action is taken on the next increment after the values match (WDT_CTR0=WDT_MATCH0).</description>
12672                <bitRange>[1:0]</bitRange>
12673                <access>read-write</access>
12674                <enumeratedValues>
12675                  <enumeratedValue>
12676                    <name>NOTHING</name>
12677                    <description>Do nothing</description>
12678                    <value>0</value>
12679                  </enumeratedValue>
12680                  <enumeratedValue>
12681                    <name>INT</name>
12682                    <description>Assert WDT_INTx</description>
12683                    <value>1</value>
12684                  </enumeratedValue>
12685                  <enumeratedValue>
12686                    <name>RESET</name>
12687                    <description>Assert WDT Reset</description>
12688                    <value>2</value>
12689                  </enumeratedValue>
12690                  <enumeratedValue>
12691                    <name>INT_THEN_RESET</name>
12692                    <description>Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt</description>
12693                    <value>3</value>
12694                  </enumeratedValue>
12695                </enumeratedValues>
12696              </field>
12697              <field>
12698                <name>WDT_CLEAR0</name>
12699                <description>Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0. In other words WDT_CTR0 divides LFCLK by (WDT_MATCH0+1).
127000: Free running counter
127011: Clear on match.  In this mode, the minimum legal setting of WDT_MATCH0 is 1.</description>
12702                <bitRange>[2:2]</bitRange>
12703                <access>read-write</access>
12704              </field>
12705              <field>
12706                <name>WDT_CASCADE0_1</name>
12707                <description>Cascade Watchdog Counters 0,1.  Counter 1 increments the cycle after WDT_CTR0=WDT_MATCH0.
127080: Independent counters
127091: Cascaded counters</description>
12710                <bitRange>[3:3]</bitRange>
12711                <access>read-write</access>
12712              </field>
12713              <field>
12714                <name>WDT_LOWER_MODE0</name>
12715                <description>Watchdog Counter Action on service before lower limit.</description>
12716                <bitRange>[5:4]</bitRange>
12717                <access>read-write</access>
12718                <enumeratedValues>
12719                  <enumeratedValue>
12720                    <name>NOTHING</name>
12721                    <description>Do nothing</description>
12722                    <value>0</value>
12723                  </enumeratedValue>
12724                  <enumeratedValue>
12725                    <name>INT</name>
12726                    <description>Assert WDT_INTx</description>
12727                    <value>1</value>
12728                  </enumeratedValue>
12729                  <enumeratedValue>
12730                    <name>RESET</name>
12731                    <description>Assert WDT Reset</description>
12732                    <value>2</value>
12733                  </enumeratedValue>
12734                </enumeratedValues>
12735              </field>
12736              <field>
12737                <name>WDT_CARRY0_1</name>
12738                <description>Carry out behavior that applies when WDT_CASCADE0_1==1.  This bit is not used when WDT_CASCADE0_1==0.
127390: carry out on counter 0 match.
127401: carry out on counter 0 roll-over.</description>
12741                <bitRange>[6:6]</bitRange>
12742                <access>read-write</access>
12743              </field>
12744              <field>
12745                <name>WDT_MATCH0_1</name>
12746                <description>Specifies matching behavior when WDT_CASCADE0_1==1.  When WDT_CASCADE0_1==0, this bit is not used and match is based on counter 1 alone.
127470: Match based on counter 1 alone.
127481: Match based on counter 1 and counter 0 matching simultaneously.</description>
12749                <bitRange>[7:7]</bitRange>
12750                <access>read-write</access>
12751              </field>
12752              <field>
12753                <name>WDT_MODE1</name>
12754                <description>Watchdog Counter Action on Match.  Action is taken on the next increment after the values match (WDT_CTR1=WDT_MATCH1).</description>
12755                <bitRange>[9:8]</bitRange>
12756                <access>read-write</access>
12757                <enumeratedValues>
12758                  <enumeratedValue>
12759                    <name>NOTHING</name>
12760                    <description>Do nothing</description>
12761                    <value>0</value>
12762                  </enumeratedValue>
12763                  <enumeratedValue>
12764                    <name>INT</name>
12765                    <description>Assert WDT_INTx</description>
12766                    <value>1</value>
12767                  </enumeratedValue>
12768                  <enumeratedValue>
12769                    <name>RESET</name>
12770                    <description>Assert WDT Reset</description>
12771                    <value>2</value>
12772                  </enumeratedValue>
12773                  <enumeratedValue>
12774                    <name>INT_THEN_RESET</name>
12775                    <description>Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt</description>
12776                    <value>3</value>
12777                  </enumeratedValue>
12778                </enumeratedValues>
12779              </field>
12780              <field>
12781                <name>WDT_CLEAR1</name>
12782                <description>Clear Watchdog Counter when WDT_CTR1==WDT_MATCH1. In other words WDT_CTR1 divides LFCLK by (WDT_MATCH1+1).
127830: Free running counter
127841: Clear on match.  In this mode, the minimum legal setting of WDT_MATCH1 is 1.</description>
12785                <bitRange>[10:10]</bitRange>
12786                <access>read-write</access>
12787              </field>
12788              <field>
12789                <name>WDT_CASCADE1_2</name>
12790                <description>Cascade Watchdog Counters 1,2.  Counter 2 increments the cycle after WDT_CTR1=WDT_MATCH1.  It is allowed to cascade all three WDT counters.
127910: Independent counters
127921: Cascaded counters.  When cascading all three counters, WDT_CLEAR1 must be 1.</description>
12793                <bitRange>[11:11]</bitRange>
12794                <access>read-write</access>
12795              </field>
12796              <field>
12797                <name>WDT_LOWER_MODE1</name>
12798                <description>Watchdog Counter Action on service before lower limit.</description>
12799                <bitRange>[13:12]</bitRange>
12800                <access>read-write</access>
12801                <enumeratedValues>
12802                  <enumeratedValue>
12803                    <name>NOTHING</name>
12804                    <description>Do nothing</description>
12805                    <value>0</value>
12806                  </enumeratedValue>
12807                  <enumeratedValue>
12808                    <name>INT</name>
12809                    <description>Assert WDT_INTx</description>
12810                    <value>1</value>
12811                  </enumeratedValue>
12812                  <enumeratedValue>
12813                    <name>RESET</name>
12814                    <description>Assert WDT Reset</description>
12815                    <value>2</value>
12816                  </enumeratedValue>
12817                </enumeratedValues>
12818              </field>
12819              <field>
12820                <name>WDT_CARRY1_2</name>
12821                <description>Carry out behavior that applies when WDT_CASCADE1_2==1.  This bit is not used when WDT_CASCADE1_2==0.
128220: carry out on counter 1 match.
128231: carry out on counter 1 roll-over.</description>
12824                <bitRange>[14:14]</bitRange>
12825                <access>read-write</access>
12826              </field>
12827              <field>
12828                <name>WDT_MATCH1_2</name>
12829                <description>Specifies matching behavior when WDT_CASCADE1_2==1.  When WDT_CASCADE1_2==0, this bit is not used and match is based on counter 2 alone.
128300: Match based on counter 2 alone.
128311: Match based on counter 2 and counter 1 matching simultaneously.</description>
12832                <bitRange>[15:15]</bitRange>
12833                <access>read-write</access>
12834              </field>
12835              <field>
12836                <name>WDT_MODE2</name>
12837                <description>Watchdog Counter 2 Mode.</description>
12838                <bitRange>[16:16]</bitRange>
12839                <access>read-write</access>
12840                <enumeratedValues>
12841                  <enumeratedValue>
12842                    <name>NOTHING</name>
12843                    <description>Free running counter with no interrupt requests</description>
12844                    <value>0</value>
12845                  </enumeratedValue>
12846                  <enumeratedValue>
12847                    <name>INT</name>
12848                    <description>Free running counter with interrupt request that occurs one LFCLK cycle after the specified bit in CTR2 toggles (see WDT_BITS2).</description>
12849                    <value>1</value>
12850                  </enumeratedValue>
12851                </enumeratedValues>
12852              </field>
12853              <field>
12854                <name>WDT_BITS2</name>
12855                <description>Bit to observe for WDT_INT2:
128560: Assert after bit0 of WDT_CTR2 toggles (one int every tick)
12857...
1285831: Assert after bit31 of WDT_CTR2 toggles (one int every 2^31 ticks)</description>
12859                <bitRange>[28:24]</bitRange>
12860                <access>read-write</access>
12861              </field>
12862            </fields>
12863          </register>
12864          <register>
12865            <name>MCWDT_CTL</name>
12866            <description>Multi-Counter Watchdog Counter Control</description>
12867            <addressOffset>0x14</addressOffset>
12868            <size>32</size>
12869            <access>read-write</access>
12870            <resetValue>0x0</resetValue>
12871            <resetMask>0xB0B0B</resetMask>
12872            <fields>
12873              <field>
12874                <name>WDT_ENABLE0</name>
12875                <description>Enable subcounter 0.  May take up to 2 LFCLK cycles to take effect.
128760: Counter is disabled (not clocked)
128771: Counter is enabled (counting up)</description>
12878                <bitRange>[0:0]</bitRange>
12879                <access>read-write</access>
12880              </field>
12881              <field>
12882                <name>WDT_ENABLED0</name>
12883                <description>Indicates actual state of counter.  May lag WDT_ENABLE0 by up to two LFCLK cycles.</description>
12884                <bitRange>[1:1]</bitRange>
12885                <access>read-only</access>
12886              </field>
12887              <field>
12888                <name>WDT_RESET0</name>
12889                <description>Resets counter 0 back to 0000.  Hardware will reset this bit after counter was reset.  This will take up to one LFCLK cycle to take effect.</description>
12890                <bitRange>[3:3]</bitRange>
12891                <access>read-write</access>
12892              </field>
12893              <field>
12894                <name>WDT_ENABLE1</name>
12895                <description>Enable subcounter 1.  May take up to 2 LFCLK cycles to take effect.
128960: Counter is disabled (not clocked)
128971: Counter is enabled (counting up)</description>
12898                <bitRange>[8:8]</bitRange>
12899                <access>read-write</access>
12900              </field>
12901              <field>
12902                <name>WDT_ENABLED1</name>
12903                <description>Indicates actual state of counter.  May lag WDT_ENABLE1 by up to two LFCLK cycles.</description>
12904                <bitRange>[9:9]</bitRange>
12905                <access>read-only</access>
12906              </field>
12907              <field>
12908                <name>WDT_RESET1</name>
12909                <description>Resets counter 1 back to 0000.  Hardware will reset this bit after counter was reset.  This will take up to one LFCLK cycle to take effect.</description>
12910                <bitRange>[11:11]</bitRange>
12911                <access>read-write</access>
12912              </field>
12913              <field>
12914                <name>WDT_ENABLE2</name>
12915                <description>Enable subcounter 2.  May take up to 2 LFCLK cycles to take effect.
129160: Counter is disabled (not clocked)
129171: Counter is enabled (counting up)</description>
12918                <bitRange>[16:16]</bitRange>
12919                <access>read-write</access>
12920              </field>
12921              <field>
12922                <name>WDT_ENABLED2</name>
12923                <description>Indicates actual state of counter.  May lag WDT_ENABLE2 by up to two LFCLK cycles.</description>
12924                <bitRange>[17:17]</bitRange>
12925                <access>read-only</access>
12926              </field>
12927              <field>
12928                <name>WDT_RESET2</name>
12929                <description>Resets counter 2 back to 0000.  Hardware will reset this bit after counter was reset.  This will take up to one LFCLK cycle to take effect.</description>
12930                <bitRange>[19:19]</bitRange>
12931                <access>read-write</access>
12932              </field>
12933            </fields>
12934          </register>
12935          <register>
12936            <name>MCWDT_INTR</name>
12937            <description>Multi-Counter Watchdog Counter Interrupt Register</description>
12938            <addressOffset>0x18</addressOffset>
12939            <size>32</size>
12940            <access>read-write</access>
12941            <resetValue>0x0</resetValue>
12942            <resetMask>0x7</resetMask>
12943            <fields>
12944              <field>
12945                <name>MCWDT_INT0</name>
12946                <description>MCWDT Interrupt Request for sub-counter 0.  This bit is set by hardware as configured by this registers.  This bit must be cleared by firmware.  Clearing this bit also prevents Reset from happening when WDT_MODE0=3.</description>
12947                <bitRange>[0:0]</bitRange>
12948                <access>read-write</access>
12949              </field>
12950              <field>
12951                <name>MCWDT_INT1</name>
12952                <description>MCWDT Interrupt Request for sub-counter 1.  This bit is set by hardware as configured by this registers.  This bit must be cleared by firmware.  Clearing this bit also prevents Reset from happening when WDT_MODE1=3.</description>
12953                <bitRange>[1:1]</bitRange>
12954                <access>read-write</access>
12955              </field>
12956              <field>
12957                <name>MCWDT_INT2</name>
12958                <description>MCWDT Interrupt Request for sub-counter 2.  This bit is set by hardware as configured by this registers.  This bit must be cleared by firmware.  Clearing this bit also prevents Reset from happening when WDT_MODE2=3.</description>
12959                <bitRange>[2:2]</bitRange>
12960                <access>read-write</access>
12961              </field>
12962            </fields>
12963          </register>
12964          <register>
12965            <name>MCWDT_INTR_SET</name>
12966            <description>Multi-Counter Watchdog Counter Interrupt Set Register</description>
12967            <addressOffset>0x1C</addressOffset>
12968            <size>32</size>
12969            <access>read-write</access>
12970            <resetValue>0x0</resetValue>
12971            <resetMask>0x7</resetMask>
12972            <fields>
12973              <field>
12974                <name>MCWDT_INT0</name>
12975                <description>Set interrupt for MCWDT_INT0</description>
12976                <bitRange>[0:0]</bitRange>
12977                <access>read-write</access>
12978              </field>
12979              <field>
12980                <name>MCWDT_INT1</name>
12981                <description>Set interrupt for MCWDT_INT1</description>
12982                <bitRange>[1:1]</bitRange>
12983                <access>read-write</access>
12984              </field>
12985              <field>
12986                <name>MCWDT_INT2</name>
12987                <description>Set interrupt for MCWDT_INT2</description>
12988                <bitRange>[2:2]</bitRange>
12989                <access>read-write</access>
12990              </field>
12991            </fields>
12992          </register>
12993          <register>
12994            <name>MCWDT_INTR_MASK</name>
12995            <description>Multi-Counter Watchdog Counter Interrupt Mask Register</description>
12996            <addressOffset>0x20</addressOffset>
12997            <size>32</size>
12998            <access>read-write</access>
12999            <resetValue>0x0</resetValue>
13000            <resetMask>0x7</resetMask>
13001            <fields>
13002              <field>
13003                <name>MCWDT_INT0</name>
13004                <description>Mask for sub-counter 0. This controls if the interrupt is forwarded to the CPU.
130050: Interrupt is masked (not forwarded).
130061: Interrupt is forwarded.</description>
13007                <bitRange>[0:0]</bitRange>
13008                <access>read-write</access>
13009              </field>
13010              <field>
13011                <name>MCWDT_INT1</name>
13012                <description>Mask for sub-counter 1. This controls if the interrupt is forwarded to the CPU.
130130: Interrupt is masked (not forwarded).
130141: Interrupt is forwarded.</description>
13015                <bitRange>[1:1]</bitRange>
13016                <access>read-write</access>
13017              </field>
13018              <field>
13019                <name>MCWDT_INT2</name>
13020                <description>Mask for sub-counter 2. This controls if the interrupt is forwarded to the CPU.
130210: Interrupt is masked (not forwarded).
130221: Interrupt is forwarded.</description>
13023                <bitRange>[2:2]</bitRange>
13024                <access>read-write</access>
13025              </field>
13026            </fields>
13027          </register>
13028          <register>
13029            <name>MCWDT_INTR_MASKED</name>
13030            <description>Multi-Counter Watchdog Counter Interrupt Masked Register</description>
13031            <addressOffset>0x24</addressOffset>
13032            <size>32</size>
13033            <access>read-only</access>
13034            <resetValue>0x0</resetValue>
13035            <resetMask>0x7</resetMask>
13036            <fields>
13037              <field>
13038                <name>MCWDT_INT0</name>
13039                <description>Logical and of corresponding request and mask bits.</description>
13040                <bitRange>[0:0]</bitRange>
13041                <access>read-only</access>
13042              </field>
13043              <field>
13044                <name>MCWDT_INT1</name>
13045                <description>Logical and of corresponding request and mask bits.</description>
13046                <bitRange>[1:1]</bitRange>
13047                <access>read-only</access>
13048              </field>
13049              <field>
13050                <name>MCWDT_INT2</name>
13051                <description>Logical and of corresponding request and mask bits.</description>
13052                <bitRange>[2:2]</bitRange>
13053                <access>read-only</access>
13054              </field>
13055            </fields>
13056          </register>
13057          <register>
13058            <name>MCWDT_LOCK</name>
13059            <description>Multi-Counter Watchdog Counter Lock Register</description>
13060            <addressOffset>0x28</addressOffset>
13061            <size>32</size>
13062            <access>read-write</access>
13063            <resetValue>0x0</resetValue>
13064            <resetMask>0xC0000000</resetMask>
13065            <fields>
13066              <field>
13067                <name>MCWDT_LOCK</name>
13068                <description>Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions).  Requires at least two different writes to unlock.
13069Note that this field is 2 bits to force multiple writes only.  Each MCWDT has a separate local lock.  LFCLK settings are locked by the global WDT_LOCK register, and this register has no effect on that.</description>
13070                <bitRange>[31:30]</bitRange>
13071                <access>read-write</access>
13072                <enumeratedValues>
13073                  <enumeratedValue>
13074                    <name>NO_CHG</name>
13075                    <description>No effect</description>
13076                    <value>0</value>
13077                  </enumeratedValue>
13078                  <enumeratedValue>
13079                    <name>CLR0</name>
13080                    <description>Clears bit 0</description>
13081                    <value>1</value>
13082                  </enumeratedValue>
13083                  <enumeratedValue>
13084                    <name>CLR1</name>
13085                    <description>Clears bit 1</description>
13086                    <value>2</value>
13087                  </enumeratedValue>
13088                  <enumeratedValue>
13089                    <name>SET01</name>
13090                    <description>Sets both bits 0 and 1</description>
13091                    <value>3</value>
13092                  </enumeratedValue>
13093                </enumeratedValues>
13094              </field>
13095            </fields>
13096          </register>
13097          <register>
13098            <name>MCWDT_LOWER_LIMIT</name>
13099            <description>Multi-Counter Watchdog Counter Lower Limit Register</description>
13100            <addressOffset>0x2C</addressOffset>
13101            <size>32</size>
13102            <access>read-write</access>
13103            <resetValue>0x0</resetValue>
13104            <resetMask>0xFFFFFFFF</resetMask>
13105            <fields>
13106              <field>
13107                <name>WDT_LOWER_LIMIT0</name>
13108                <description>Lower limit for sub-counter 0 of this MCWDT</description>
13109                <bitRange>[15:0]</bitRange>
13110                <access>read-write</access>
13111              </field>
13112              <field>
13113                <name>WDT_LOWER_LIMIT1</name>
13114                <description>Lower limit for sub-counter 1 of this MCWDT</description>
13115                <bitRange>[31:16]</bitRange>
13116                <access>read-write</access>
13117              </field>
13118            </fields>
13119          </register>
13120        </cluster>
13121      </registers>
13122    </peripheral>
13123    <peripheral>
13124      <name>PWRMODE</name>
13125      <description>SRSS Power Mode Control Registers</description>
13126      <baseAddress>0x40210000</baseAddress>
13127      <addressBlock>
13128        <offset>0</offset>
13129        <size>65536</size>
13130        <usage>registers</usage>
13131      </addressBlock>
13132      <registers>
13133        <cluster>
13134          <dim>16</dim>
13135          <dimIncrement>16</dimIncrement>
13136          <name>PD[%s]</name>
13137          <description>Power Domain Dependency Sense Register</description>
13138          <addressOffset>0x00000000</addressOffset>
13139          <register>
13140            <name>PD_SENSE</name>
13141            <description>Dependency Sense Register</description>
13142            <addressOffset>0x0</addressOffset>
13143            <size>32</size>
13144            <access>read-write</access>
13145            <resetValue>0x0</resetValue>
13146            <resetMask>0x0</resetMask>
13147            <fields>
13148              <field>
13149                <name>PD_ON</name>
13150                <description>Each bit &lt;i&gt; indicates whether PD&lt;j&gt; is directly kept on when PD&lt;i&gt; is on.  Indirect dependency is still possible if multiple direct dependencies work together to create a transitive relationship.  For example, if PD1 depends upon PD2; and PD2 dpends upon PD3; then PD1 indirectly depends upon PD3 regardless of whether there is a direct dependency from PD3 to PD1.  Some bits are implemented as constants, and some bits are implemented as user-configurable registers.  Refer to PD_SPT register to see how each bit is implemented.</description>
13151                <bitRange>[15:0]</bitRange>
13152                <access>read-write</access>
13153              </field>
13154            </fields>
13155          </register>
13156          <register>
13157            <name>PD_SPT</name>
13158            <description>Dependency Support Register</description>
13159            <addressOffset>0x4</addressOffset>
13160            <size>32</size>
13161            <access>read-only</access>
13162            <resetValue>0x0</resetValue>
13163            <resetMask>0x0</resetMask>
13164            <fields>
13165              <field>
13166                <name>PD_FORCE_ON</name>
13167                <description>Each bit &lt;i&gt; indicates whether PD&lt;j&gt; is always kept on when PD&lt;i&gt; is on for sense bits that are not configurable.  For configurable bits, this indicates the reset value of the configurable bit.</description>
13168                <bitRange>[15:0]</bitRange>
13169                <access>read-only</access>
13170              </field>
13171              <field>
13172                <name>PD_CONFIG_ON</name>
13173                <description>Each bit &lt;i&gt; indicates whether PD&lt;j&gt; can be configured on when PD&lt;i&gt; is on.</description>
13174                <bitRange>[31:16]</bitRange>
13175                <access>read-only</access>
13176              </field>
13177            </fields>
13178          </register>
13179        </cluster>
13180        <cluster>
13181          <name>PPU_MAIN</name>
13182          <description>Power Policy Unit for Active Domain</description>
13183          <addressOffset>0x00001000</addressOffset>
13184          <cluster>
13185            <name>PPU_MAIN</name>
13186            <description>Power Policy Unit Registers for the main power domain (VCCACT_PD)</description>
13187            <addressOffset>0x00000000</addressOffset>
13188            <register>
13189              <name>PWPR</name>
13190              <description>Power Policy Register</description>
13191              <addressOffset>0x0</addressOffset>
13192              <size>32</size>
13193              <access>read-write</access>
13194              <resetValue>0x108</resetValue>
13195              <resetMask>0x10F110F</resetMask>
13196              <fields>
13197                <field>
13198                  <name>PWR_POLICY</name>
13199                  <description>Power mode policy.  When static power mode transitions are enabled, PWR_DYN_EN is set to 0, this is the target power mode for the PPU.  When dynamic power mode transitions are enabled, PWR_DYN_EN is set to 1, this is the minimum power mode for the PPU.
13200
13201This PPU supports the following modes: OFF(0), MEM_RET(2), FULL_RET(5), ON(8).  Do not use WARM_RST(9) or other unsupported modes.</description>
13202                  <bitRange>[3:0]</bitRange>
13203                  <access>read-write</access>
13204                </field>
13205                <field>
13206                  <name>PWR_DYN_EN</name>
13207                  <description>Power mode dynamic transition enable.  For main PPU, keep this bit 1.</description>
13208                  <bitRange>[8:8]</bitRange>
13209                  <access>read-write</access>
13210                </field>
13211                <field>
13212                  <name>LOCK_EN</name>
13213                  <description>N/A</description>
13214                  <bitRange>[12:12]</bitRange>
13215                  <access>read-write</access>
13216                </field>
13217                <field>
13218                  <name>OP_POLICY</name>
13219                  <description>N/A</description>
13220                  <bitRange>[19:16]</bitRange>
13221                  <access>read-write</access>
13222                </field>
13223                <field>
13224                  <name>OP_DYN_EN</name>
13225                  <description>N/A</description>
13226                  <bitRange>[24:24]</bitRange>
13227                  <access>read-write</access>
13228                </field>
13229              </fields>
13230            </register>
13231            <register>
13232              <name>PMER</name>
13233              <description>Power Mode Emulation Register</description>
13234              <addressOffset>0x4</addressOffset>
13235              <size>32</size>
13236              <access>read-write</access>
13237              <resetValue>0x0</resetValue>
13238              <resetMask>0x1</resetMask>
13239              <fields>
13240                <field>
13241                  <name>EMU_EN</name>
13242                  <description>N/A</description>
13243                  <bitRange>[0:0]</bitRange>
13244                  <access>read-write</access>
13245                </field>
13246              </fields>
13247            </register>
13248            <register>
13249              <name>PWSR</name>
13250              <description>Power Status Register</description>
13251              <addressOffset>0x8</addressOffset>
13252              <size>32</size>
13253              <access>read-only</access>
13254              <resetValue>0x0</resetValue>
13255              <resetMask>0x10F110F</resetMask>
13256              <fields>
13257                <field>
13258                  <name>PWR_STATUS</name>
13259                  <description>Power mode status.  These bits reflect the current power mode of the PPU.  See PPU_PWPR.PWR_POLICY for power mode enumeration.</description>
13260                  <bitRange>[3:0]</bitRange>
13261                  <access>read-only</access>
13262                </field>
13263                <field>
13264                  <name>PWR_DYN_STATUS</name>
13265                  <description>Power mode dynamic transition status.  When set to 1 power mode dynamic transitions are enabled.  There might be a delay in dynamic transitions becoming active or inactive if the PPU is transitioning when PWR_DYN_EN is programmed.</description>
13266                  <bitRange>[8:8]</bitRange>
13267                  <access>read-only</access>
13268                </field>
13269                <field>
13270                  <name>LOCK_STATUS</name>
13271                  <description>N/A</description>
13272                  <bitRange>[12:12]</bitRange>
13273                  <access>read-only</access>
13274                </field>
13275                <field>
13276                  <name>OP_STATUS</name>
13277                  <description>N/A</description>
13278                  <bitRange>[19:16]</bitRange>
13279                  <access>read-only</access>
13280                </field>
13281                <field>
13282                  <name>OP_DYN_STATUS</name>
13283                  <description>N/A</description>
13284                  <bitRange>[24:24]</bitRange>
13285                  <access>read-only</access>
13286                </field>
13287              </fields>
13288            </register>
13289            <register>
13290              <name>DISR</name>
13291              <description>Device Interface Input Current Status Register</description>
13292              <addressOffset>0x10</addressOffset>
13293              <size>32</size>
13294              <access>read-only</access>
13295              <resetValue>0x0</resetValue>
13296              <resetMask>0xFF0007FF</resetMask>
13297              <fields>
13298                <field>
13299                  <name>PWR_DEVACTIVE_STATUS</name>
13300                  <description>Status of the power mode DEVACTIVE inputs.
13301
13302There is one bit for each device interface Q-Channel DEVQACTIVE.  For example, bit 0 is for Q-channel device 0 DEVQACTIVE.  Refer to PPU_IDR0.DEVCHAN for device channel enumeration.</description>
13303                  <bitRange>[10:0]</bitRange>
13304                  <access>read-only</access>
13305                </field>
13306                <field>
13307                  <name>OP_DEVACTIVE_STATUS</name>
13308                  <description>N/A</description>
13309                  <bitRange>[31:24]</bitRange>
13310                  <access>read-only</access>
13311                </field>
13312              </fields>
13313            </register>
13314            <register>
13315              <name>MISR</name>
13316              <description>Miscellaneous Input Current Status Register</description>
13317              <addressOffset>0x14</addressOffset>
13318              <size>32</size>
13319              <access>read-only</access>
13320              <resetValue>0x0</resetValue>
13321              <resetMask>0xFFFF01</resetMask>
13322              <fields>
13323                <field>
13324                  <name>PCSMPACCEPT_STATUS</name>
13325                  <description>The status of the PCSMPACCEPT input.</description>
13326                  <bitRange>[0:0]</bitRange>
13327                  <access>read-only</access>
13328                </field>
13329                <field>
13330                  <name>DEVACCEPT_STATUS</name>
13331                  <description>Status of the device interface DEVACCEPT inputs.
13332
13333There is one bit for each device interface DEVQACCEPTn.  For example, bit 8 is for Q-Channel 0 DEVQACCEPTn and bit 9 for Q-Channel 1 DEVQACCEPTn.   Refer to PPU_IDR0.DEVCHAN for device channel enumeration.</description>
13334                  <bitRange>[15:8]</bitRange>
13335                  <access>read-only</access>
13336                </field>
13337                <field>
13338                  <name>DEVDENY_STATUS</name>
13339                  <description>Status of the device interface DEVDENY inputs.
13340
13341There is one bit for each device interface DEVQDENY.  For example, bit 16 is for Q-Channel 0 DEVQDENY, and bit 17 for Q-Channel 1 DEVQDENY.  Refer to PPU_IDR0.DEVCHAN for device channel enumeration.</description>
13342                  <bitRange>[23:16]</bitRange>
13343                  <access>read-only</access>
13344                </field>
13345              </fields>
13346            </register>
13347            <register>
13348              <name>STSR</name>
13349              <description>Stored Status Register</description>
13350              <addressOffset>0x18</addressOffset>
13351              <size>32</size>
13352              <access>read-only</access>
13353              <resetValue>0x0</resetValue>
13354              <resetMask>0xFF</resetMask>
13355              <fields>
13356                <field>
13357                  <name>STORED_DEVDENY</name>
13358                  <description>Status of the DEVDENY signals from the last device interface Q-Channel transition.  For Q-Channel:  There is one bit for each device interface DEVQDENY.  For example, bit 0 is for Q-Channel 0 DEVQDENY, and bit 1 for Q-Channel 1 DEVQDENY.  Refer to PPU_DISR.PWR_DEVACTIVE_STATUS for device enumeration.</description>
13359                  <bitRange>[7:0]</bitRange>
13360                  <access>read-only</access>
13361                </field>
13362              </fields>
13363            </register>
13364            <register>
13365              <name>UNLK</name>
13366              <description>Unlock register</description>
13367              <addressOffset>0x1C</addressOffset>
13368              <size>32</size>
13369              <access>read-write</access>
13370              <resetValue>0x0</resetValue>
13371              <resetMask>0x1</resetMask>
13372              <fields>
13373                <field>
13374                  <name>UNLOCK</name>
13375                  <description>N/A</description>
13376                  <bitRange>[0:0]</bitRange>
13377                  <access>read-write</access>
13378                </field>
13379              </fields>
13380            </register>
13381            <register>
13382              <name>PWCR</name>
13383              <description>Power Configuration Register</description>
13384              <addressOffset>0x20</addressOffset>
13385              <size>32</size>
13386              <access>read-write</access>
13387              <resetValue>0x101</resetValue>
13388              <resetMask>0xFF07FFFF</resetMask>
13389              <fields>
13390                <field>
13391                  <name>DEVREQEN</name>
13392                  <description>When set to 1 enables the device interface handshake for transitions.  All available bits are reset to 1.
13393
13394There is one bit for each device interface channel.  For example, bit 0 is for Q-Channel 0, and bit 1 is for Q-Channel 1.  Refer to PPU_IDR0.DEVCHAN for device channel enumeration.</description>
13395                  <bitRange>[7:0]</bitRange>
13396                  <access>read-write</access>
13397                </field>
13398                <field>
13399                  <name>PWR_DEVACTIVEEN</name>
13400                  <description>These bits enable the power mode DEVACTIVE inputs.  When a bit is to 1 the related DEVACTIVE input is enabled, when set to 0 it is disabled.  All available bits are reset to 1.
13401
13402There is one bit for each device interface Q-Channel DEVQACTIVE.  For example, bit 8 is for the Q-Channel 0 DEVQACTIVE, and bit 9 for the Q-Channel 1 DEVQACTIVE.  Refer to PPU_IDR0.DEVCHAN for device channel enumeration.</description>
13403                  <bitRange>[18:8]</bitRange>
13404                  <access>read-write</access>
13405                </field>
13406                <field>
13407                  <name>OP_DEVACTIVEEN</name>
13408                  <description>N/A</description>
13409                  <bitRange>[31:24]</bitRange>
13410                  <access>read-write</access>
13411                </field>
13412              </fields>
13413            </register>
13414            <register>
13415              <name>PTCR</name>
13416              <description>Power Mode Transition Configuration Register</description>
13417              <addressOffset>0x24</addressOffset>
13418              <size>32</size>
13419              <access>read-write</access>
13420              <resetValue>0x0</resetValue>
13421              <resetMask>0x3</resetMask>
13422              <fields>
13423                <field>
13424                  <name>WARM_RST_DEVREQEN</name>
13425                  <description>Transition behavior between ON and WARM_RST.  This bit should not be modified when the PPU is in WARM_RST, or if the PPU is performing a transition, otherwise PPU behavior is UNPREDICTABLE.
134260:  The PPU does not perform a device interface handshake when transitioning between ON and WARM_RST.
134271:  The PPU performs a device interface handshake when transitioning between ON and WARM_RST.  This disables all Q-Channels for this transition.</description>
13428                  <bitRange>[0:0]</bitRange>
13429                  <access>read-write</access>
13430                </field>
13431                <field>
13432                  <name>DBG_RECOV_PORST_EN</name>
13433                  <description>N/A</description>
13434                  <bitRange>[1:1]</bitRange>
13435                  <access>read-write</access>
13436                </field>
13437              </fields>
13438            </register>
13439            <register>
13440              <name>IMR</name>
13441              <description>Interrupt Mask Register</description>
13442              <addressOffset>0x30</addressOffset>
13443              <size>32</size>
13444              <access>read-write</access>
13445              <resetValue>0x2</resetValue>
13446              <resetMask>0x3F</resetMask>
13447              <fields>
13448                <field>
13449                  <name>STA_POLICY_TRN_IRQ_MASK</name>
13450                  <description>Static full policy transition completion event mask.  For main PPU, this bit has no function because no static transitions are supported (see PWPR.PWR_DYN_EN).</description>
13451                  <bitRange>[0:0]</bitRange>
13452                  <access>read-write</access>
13453                </field>
13454                <field>
13455                  <name>STA_ACCEPT_IRQ_MASK</name>
13456                  <description>Static transition acceptance event mask.  For main PPU, keep this bit 1 to mask the event, otherwise the interrupt may trigger a wakeup.</description>
13457                  <bitRange>[1:1]</bitRange>
13458                  <access>read-write</access>
13459                </field>
13460                <field>
13461                  <name>STA_DENY_IRQ_MASK</name>
13462                  <description>Static transition denial event mask.</description>
13463                  <bitRange>[2:2]</bitRange>
13464                  <access>read-write</access>
13465                </field>
13466                <field>
13467                  <name>EMU_ACCEPT_IRQ_MASK</name>
13468                  <description>N/A</description>
13469                  <bitRange>[3:3]</bitRange>
13470                  <access>read-write</access>
13471                </field>
13472                <field>
13473                  <name>EMU_DENY_IRQ_MASK</name>
13474                  <description>N/A</description>
13475                  <bitRange>[4:4]</bitRange>
13476                  <access>read-write</access>
13477                </field>
13478                <field>
13479                  <name>LOCKED_IRQ_MASK</name>
13480                  <description>N/A</description>
13481                  <bitRange>[5:5]</bitRange>
13482                  <access>read-write</access>
13483                </field>
13484              </fields>
13485            </register>
13486            <register>
13487              <name>AIMR</name>
13488              <description>Additional Interrupt Mask Register</description>
13489              <addressOffset>0x34</addressOffset>
13490              <size>32</size>
13491              <access>read-write</access>
13492              <resetValue>0x6</resetValue>
13493              <resetMask>0x1F</resetMask>
13494              <fields>
13495                <field>
13496                  <name>UNSPT_POLICY_IRQ_MASK</name>
13497                  <description>Unsupported Policy event mask.</description>
13498                  <bitRange>[0:0]</bitRange>
13499                  <access>read-write</access>
13500                </field>
13501                <field>
13502                  <name>DYN_ACCEPT_IRQ_MASK</name>
13503                  <description>Dynamic transition acceptance event mask.  For main PPU, keep this bit 1 to mask the event, otherwise the interrupt that occurs when entering a low power mode may trigger a wakeup.</description>
13504                  <bitRange>[1:1]</bitRange>
13505                  <access>read-write</access>
13506                </field>
13507                <field>
13508                  <name>DYN_DENY_IRQ_MASK</name>
13509                  <description>Dynamic transition denial event mask.</description>
13510                  <bitRange>[2:2]</bitRange>
13511                  <access>read-write</access>
13512                </field>
13513                <field>
13514                  <name>STA_POLICY_PWR_IRQ_MASK</name>
13515                  <description>N/A</description>
13516                  <bitRange>[3:3]</bitRange>
13517                  <access>read-write</access>
13518                </field>
13519                <field>
13520                  <name>STA_POLICY_OP_IRQ_MASK</name>
13521                  <description>N/A</description>
13522                  <bitRange>[4:4]</bitRange>
13523                  <access>read-write</access>
13524                </field>
13525              </fields>
13526            </register>
13527            <register>
13528              <name>ISR</name>
13529              <description>Interrupt Status Register</description>
13530              <addressOffset>0x38</addressOffset>
13531              <size>32</size>
13532              <access>read-write</access>
13533              <resetValue>0x0</resetValue>
13534              <resetMask>0xFF07FFBF</resetMask>
13535              <fields>
13536                <field>
13537                  <name>STA_POLICY_TRN_IRQ</name>
13538                  <description>Static full policy transition completion event status.</description>
13539                  <bitRange>[0:0]</bitRange>
13540                  <access>read-write</access>
13541                </field>
13542                <field>
13543                  <name>STA_ACCEPT_IRQ</name>
13544                  <description>Static transition acceptance event status.</description>
13545                  <bitRange>[1:1]</bitRange>
13546                  <access>read-write</access>
13547                </field>
13548                <field>
13549                  <name>STA_DENY_IRQ</name>
13550                  <description>Static transition denial event status.</description>
13551                  <bitRange>[2:2]</bitRange>
13552                  <access>read-write</access>
13553                </field>
13554                <field>
13555                  <name>EMU_ACCEPT_IRQ</name>
13556                  <description>N/A</description>
13557                  <bitRange>[3:3]</bitRange>
13558                  <access>read-write</access>
13559                </field>
13560                <field>
13561                  <name>EMU_DENY_IRQ</name>
13562                  <description>N/A</description>
13563                  <bitRange>[4:4]</bitRange>
13564                  <access>read-write</access>
13565                </field>
13566                <field>
13567                  <name>LOCKED_IRQ</name>
13568                  <description>N/A</description>
13569                  <bitRange>[5:5]</bitRange>
13570                  <access>read-write</access>
13571                </field>
13572                <field>
13573                  <name>OTHER_IRQ</name>
13574                  <description>Indicates there is an interrupt event pending in the Additional Interrupt Status Register (PPU_AISR).</description>
13575                  <bitRange>[7:7]</bitRange>
13576                  <access>read-only</access>
13577                </field>
13578                <field>
13579                  <name>PWR_ACTIVE_EDGE_IRQ</name>
13580                  <description>N/A</description>
13581                  <bitRange>[18:8]</bitRange>
13582                  <access>read-write</access>
13583                </field>
13584                <field>
13585                  <name>OP_ACTIVE_EDGE_IRQ</name>
13586                  <description>N/A</description>
13587                  <bitRange>[31:24]</bitRange>
13588                  <access>read-write</access>
13589                </field>
13590              </fields>
13591            </register>
13592            <register>
13593              <name>AISR</name>
13594              <description>Additional Interrupt Status Register</description>
13595              <addressOffset>0x3C</addressOffset>
13596              <size>32</size>
13597              <access>read-write</access>
13598              <resetValue>0x0</resetValue>
13599              <resetMask>0x1F</resetMask>
13600              <fields>
13601                <field>
13602                  <name>UNSPT_POLICY_IRQ</name>
13603                  <description>Unsupported Policy event status.</description>
13604                  <bitRange>[0:0]</bitRange>
13605                  <access>read-write</access>
13606                </field>
13607                <field>
13608                  <name>DYN_ACCEPT_IRQ</name>
13609                  <description>Dynamic transition acceptance event status.</description>
13610                  <bitRange>[1:1]</bitRange>
13611                  <access>read-write</access>
13612                </field>
13613                <field>
13614                  <name>DYN_DENY_IRQ</name>
13615                  <description>Dynamic transition denial event status.</description>
13616                  <bitRange>[2:2]</bitRange>
13617                  <access>read-write</access>
13618                </field>
13619                <field>
13620                  <name>STA_POLICY_PWR_IRQ</name>
13621                  <description>N/A</description>
13622                  <bitRange>[3:3]</bitRange>
13623                  <access>read-write</access>
13624                </field>
13625                <field>
13626                  <name>STA_POLICY_OP_IRQ</name>
13627                  <description>N/A</description>
13628                  <bitRange>[4:4]</bitRange>
13629                  <access>read-write</access>
13630                </field>
13631              </fields>
13632            </register>
13633            <register>
13634              <name>IESR</name>
13635              <description>Input Edge Sensitivity Register</description>
13636              <addressOffset>0x40</addressOffset>
13637              <size>32</size>
13638              <access>read-write</access>
13639              <resetValue>0x0</resetValue>
13640              <resetMask>0x3FFFFF</resetMask>
13641              <fields>
13642                <field>
13643                  <name>DEVACTIVE00_EDGE</name>
13644                  <description>DEVACTIVE 0 edge sensitivity.</description>
13645                  <bitRange>[1:0]</bitRange>
13646                  <access>read-write</access>
13647                </field>
13648                <field>
13649                  <name>DEVACTIVE01_EDGE</name>
13650                  <description>DEVACTIVE 1 edge sensitivity.</description>
13651                  <bitRange>[3:2]</bitRange>
13652                  <access>read-write</access>
13653                </field>
13654                <field>
13655                  <name>DEVACTIVE02_EDGE</name>
13656                  <description>DEVACTIVE 2 edge sensitivity.</description>
13657                  <bitRange>[5:4]</bitRange>
13658                  <access>read-write</access>
13659                </field>
13660                <field>
13661                  <name>DEVACTIVE03_EDGE</name>
13662                  <description>N/A</description>
13663                  <bitRange>[7:6]</bitRange>
13664                  <access>read-write</access>
13665                </field>
13666                <field>
13667                  <name>DEVACTIVE04_EDGE</name>
13668                  <description>N/A</description>
13669                  <bitRange>[9:8]</bitRange>
13670                  <access>read-write</access>
13671                </field>
13672                <field>
13673                  <name>DEVACTIVE05_EDGE</name>
13674                  <description>N/A</description>
13675                  <bitRange>[11:10]</bitRange>
13676                  <access>read-write</access>
13677                </field>
13678                <field>
13679                  <name>DEVACTIVE06_EDGE</name>
13680                  <description>N/A</description>
13681                  <bitRange>[13:12]</bitRange>
13682                  <access>read-write</access>
13683                </field>
13684                <field>
13685                  <name>DEVACTIVE07_EDGE</name>
13686                  <description>N/A</description>
13687                  <bitRange>[15:14]</bitRange>
13688                  <access>read-write</access>
13689                </field>
13690                <field>
13691                  <name>DEVACTIVE08_EDGE</name>
13692                  <description>N/A</description>
13693                  <bitRange>[17:16]</bitRange>
13694                  <access>read-write</access>
13695                </field>
13696                <field>
13697                  <name>DEVACTIVE09_EDGE</name>
13698                  <description>N/A</description>
13699                  <bitRange>[19:18]</bitRange>
13700                  <access>read-write</access>
13701                </field>
13702                <field>
13703                  <name>DEVACTIVE10_EDGE</name>
13704                  <description>N/A</description>
13705                  <bitRange>[21:20]</bitRange>
13706                  <access>read-write</access>
13707                </field>
13708              </fields>
13709            </register>
13710            <register>
13711              <name>OPSR</name>
13712              <description>Operating Mode Active Edge Sensitivity Register</description>
13713              <addressOffset>0x44</addressOffset>
13714              <size>32</size>
13715              <access>read-write</access>
13716              <resetValue>0x0</resetValue>
13717              <resetMask>0xFFFF</resetMask>
13718              <fields>
13719                <field>
13720                  <name>DEVACTIVE16_EDGE</name>
13721                  <description>N/A</description>
13722                  <bitRange>[1:0]</bitRange>
13723                  <access>read-write</access>
13724                </field>
13725                <field>
13726                  <name>DEVACTIVE17_EDGE</name>
13727                  <description>N/A</description>
13728                  <bitRange>[3:2]</bitRange>
13729                  <access>read-write</access>
13730                </field>
13731                <field>
13732                  <name>DEVACTIVE18_EDGE</name>
13733                  <description>N/A</description>
13734                  <bitRange>[5:4]</bitRange>
13735                  <access>read-write</access>
13736                </field>
13737                <field>
13738                  <name>DEVACTIVE19_EDGE</name>
13739                  <description>N/A</description>
13740                  <bitRange>[7:6]</bitRange>
13741                  <access>read-write</access>
13742                </field>
13743                <field>
13744                  <name>DEVACTIVE20_EDGE</name>
13745                  <description>N/A</description>
13746                  <bitRange>[9:8]</bitRange>
13747                  <access>read-write</access>
13748                </field>
13749                <field>
13750                  <name>DEVACTIVE21_EDGE</name>
13751                  <description>N/A</description>
13752                  <bitRange>[11:10]</bitRange>
13753                  <access>read-write</access>
13754                </field>
13755                <field>
13756                  <name>DEVACTIVE22_EDGE</name>
13757                  <description>N/A</description>
13758                  <bitRange>[13:12]</bitRange>
13759                  <access>read-write</access>
13760                </field>
13761                <field>
13762                  <name>DEVACTIVE23_EDGE</name>
13763                  <description>N/A</description>
13764                  <bitRange>[15:14]</bitRange>
13765                  <access>read-write</access>
13766                </field>
13767              </fields>
13768            </register>
13769            <register>
13770              <name>FUNRR</name>
13771              <description>Functional Retention RAM Configuration Register</description>
13772              <addressOffset>0x50</addressOffset>
13773              <size>32</size>
13774              <access>read-write</access>
13775              <resetValue>0x0</resetValue>
13776              <resetMask>0xFF</resetMask>
13777              <fields>
13778                <field>
13779                  <name>FUNC_RET_RAM_CFG</name>
13780                  <description>N/A</description>
13781                  <bitRange>[7:0]</bitRange>
13782                  <access>read-write</access>
13783                </field>
13784              </fields>
13785            </register>
13786            <register>
13787              <name>FULRR</name>
13788              <description>Full Retention RAM Configuration Register</description>
13789              <addressOffset>0x54</addressOffset>
13790              <size>32</size>
13791              <access>read-write</access>
13792              <resetValue>0x0</resetValue>
13793              <resetMask>0xFF</resetMask>
13794              <fields>
13795                <field>
13796                  <name>FULL_RET_RAM_CFG</name>
13797                  <description>N/A</description>
13798                  <bitRange>[7:0]</bitRange>
13799                  <access>read-write</access>
13800                </field>
13801              </fields>
13802            </register>
13803            <register>
13804              <name>MEMRR</name>
13805              <description>Memory Retention RAM Configuration Register</description>
13806              <addressOffset>0x58</addressOffset>
13807              <size>32</size>
13808              <access>read-write</access>
13809              <resetValue>0x0</resetValue>
13810              <resetMask>0xFF</resetMask>
13811              <fields>
13812                <field>
13813                  <name>MEM_RET_RAM_CFG</name>
13814                  <description>N/A</description>
13815                  <bitRange>[7:0]</bitRange>
13816                  <access>read-write</access>
13817                </field>
13818              </fields>
13819            </register>
13820            <register>
13821              <name>EDTR0</name>
13822              <description>Power Mode Entry Delay Register 0</description>
13823              <addressOffset>0x160</addressOffset>
13824              <size>32</size>
13825              <access>read-write</access>
13826              <resetValue>0x0</resetValue>
13827              <resetMask>0xFFFFFFFF</resetMask>
13828              <fields>
13829                <field>
13830                  <name>OFF_DEL</name>
13831                  <description>N/A</description>
13832                  <bitRange>[7:0]</bitRange>
13833                  <access>read-write</access>
13834                </field>
13835                <field>
13836                  <name>MEM_RET_DEL</name>
13837                  <description>N/A</description>
13838                  <bitRange>[15:8]</bitRange>
13839                  <access>read-write</access>
13840                </field>
13841                <field>
13842                  <name>LOGIC_RET_DEL</name>
13843                  <description>N/A</description>
13844                  <bitRange>[23:16]</bitRange>
13845                  <access>read-write</access>
13846                </field>
13847                <field>
13848                  <name>FULL_RET_DEL</name>
13849                  <description>N/A</description>
13850                  <bitRange>[31:24]</bitRange>
13851                  <access>read-write</access>
13852                </field>
13853              </fields>
13854            </register>
13855            <register>
13856              <name>EDTR1</name>
13857              <description>Power Mode Entry Delay Register 1</description>
13858              <addressOffset>0x164</addressOffset>
13859              <size>32</size>
13860              <access>read-write</access>
13861              <resetValue>0x0</resetValue>
13862              <resetMask>0xFFFF</resetMask>
13863              <fields>
13864                <field>
13865                  <name>MEM_OFF_DEL</name>
13866                  <description>N/A</description>
13867                  <bitRange>[7:0]</bitRange>
13868                  <access>read-write</access>
13869                </field>
13870                <field>
13871                  <name>FUNC_RET_DEL</name>
13872                  <description>N/A</description>
13873                  <bitRange>[15:8]</bitRange>
13874                  <access>read-write</access>
13875                </field>
13876              </fields>
13877            </register>
13878            <register>
13879              <name>DCDR0</name>
13880              <description>Device Control Delay Configuration Register 0</description>
13881              <addressOffset>0x170</addressOffset>
13882              <size>32</size>
13883              <access>read-only</access>
13884              <resetValue>0x0</resetValue>
13885              <resetMask>0xFFFFFF</resetMask>
13886              <fields>
13887                <field>
13888                  <name>CLKEN_RST_DLY</name>
13889                  <description>N/A</description>
13890                  <bitRange>[7:0]</bitRange>
13891                  <access>read-only</access>
13892                </field>
13893                <field>
13894                  <name>ISO_CLKEN_DLY</name>
13895                  <description>N/A</description>
13896                  <bitRange>[15:8]</bitRange>
13897                  <access>read-only</access>
13898                </field>
13899                <field>
13900                  <name>RST_HWSTAT_DLY</name>
13901                  <description>N/A</description>
13902                  <bitRange>[23:16]</bitRange>
13903                  <access>read-only</access>
13904                </field>
13905              </fields>
13906            </register>
13907            <register>
13908              <name>DCDR1</name>
13909              <description>Device Control Delay Configuration Register 1</description>
13910              <addressOffset>0x174</addressOffset>
13911              <size>32</size>
13912              <access>read-only</access>
13913              <resetValue>0x0</resetValue>
13914              <resetMask>0xFFFF</resetMask>
13915              <fields>
13916                <field>
13917                  <name>ISO_RST_DLY</name>
13918                  <description>N/A</description>
13919                  <bitRange>[7:0]</bitRange>
13920                  <access>read-only</access>
13921                </field>
13922                <field>
13923                  <name>CLKEN_ISO_DLY</name>
13924                  <description>N/A</description>
13925                  <bitRange>[15:8]</bitRange>
13926                  <access>read-only</access>
13927                </field>
13928              </fields>
13929            </register>
13930            <register>
13931              <name>IDR0</name>
13932              <description>PPU Identification Register 0</description>
13933              <addressOffset>0xFB0</addressOffset>
13934              <size>32</size>
13935              <access>read-only</access>
13936              <resetValue>0x14534501</resetValue>
13937              <resetMask>0x3FF7FFFF</resetMask>
13938              <fields>
13939                <field>
13940                  <name>DEVCHAN</name>
13941                  <description>No. of Device Interface Channels.
139420: This is a P-Channel PPU.  Refer to PPU_IDR1.OP_ACTIVE for the number of DEVPACTIVE inputs and their meaning.
13943non-zero: The value is the number of Q-Channels.
13944
13945The device enumeration is:
13946Device 0: PDCM</description>
13947                  <bitRange>[3:0]</bitRange>
13948                  <access>read-only</access>
13949                </field>
13950                <field>
13951                  <name>NUM_OPMODE</name>
13952                  <description>No. of operating modes supported is NUM_OPMODE + 1.</description>
13953                  <bitRange>[7:4]</bitRange>
13954                  <access>read-only</access>
13955                </field>
13956                <field>
13957                  <name>STA_OFF_SPT</name>
13958                  <description>OFF support.</description>
13959                  <bitRange>[8:8]</bitRange>
13960                  <access>read-only</access>
13961                </field>
13962                <field>
13963                  <name>STA_OFF_EMU_SPT</name>
13964                  <description>OFF_EMU support.</description>
13965                  <bitRange>[9:9]</bitRange>
13966                  <access>read-only</access>
13967                </field>
13968                <field>
13969                  <name>STA_MEM_RET_SPT</name>
13970                  <description>MEM_RET support.</description>
13971                  <bitRange>[10:10]</bitRange>
13972                  <access>read-only</access>
13973                </field>
13974                <field>
13975                  <name>STA_MEM_RET_EMU_SPT</name>
13976                  <description>MEM_RET_EMU support.</description>
13977                  <bitRange>[11:11]</bitRange>
13978                  <access>read-only</access>
13979                </field>
13980                <field>
13981                  <name>STA_LGC_RET_SPT</name>
13982                  <description>LOGIC_RET support.</description>
13983                  <bitRange>[12:12]</bitRange>
13984                  <access>read-only</access>
13985                </field>
13986                <field>
13987                  <name>STA_MEM_OFF_SPT</name>
13988                  <description>MEM_OFF support.</description>
13989                  <bitRange>[13:13]</bitRange>
13990                  <access>read-only</access>
13991                </field>
13992                <field>
13993                  <name>STA_FULL_RET_SPT</name>
13994                  <description>FULL_RET support.</description>
13995                  <bitRange>[14:14]</bitRange>
13996                  <access>read-only</access>
13997                </field>
13998                <field>
13999                  <name>STA_FUNC_RET_SPT</name>
14000                  <description>FUNC_RET support.</description>
14001                  <bitRange>[15:15]</bitRange>
14002                  <access>read-only</access>
14003                </field>
14004                <field>
14005                  <name>STA_ON_SPT</name>
14006                  <description>ON support.</description>
14007                  <bitRange>[16:16]</bitRange>
14008                  <access>read-only</access>
14009                </field>
14010                <field>
14011                  <name>STA_WRM_RST_SPT</name>
14012                  <description>WARM_RST support.  Ignore this bit.  Do not use WARM_RST.</description>
14013                  <bitRange>[17:17]</bitRange>
14014                  <access>read-only</access>
14015                </field>
14016                <field>
14017                  <name>STA_DBG_RECOV_SPT</name>
14018                  <description>DBG_RECOV support.</description>
14019                  <bitRange>[18:18]</bitRange>
14020                  <access>read-only</access>
14021                </field>
14022                <field>
14023                  <name>DYN_OFF_SPT</name>
14024                  <description>Dynamic OFF support.</description>
14025                  <bitRange>[20:20]</bitRange>
14026                  <access>read-only</access>
14027                </field>
14028                <field>
14029                  <name>DYN_OFF_EMU_SPT</name>
14030                  <description>Dynamic OFF_EMU support.</description>
14031                  <bitRange>[21:21]</bitRange>
14032                  <access>read-only</access>
14033                </field>
14034                <field>
14035                  <name>DYN_MEM_RET_SPT</name>
14036                  <description>Dynamic MEM_RET support.</description>
14037                  <bitRange>[22:22]</bitRange>
14038                  <access>read-only</access>
14039                </field>
14040                <field>
14041                  <name>DYN_MEM_RET_EMU_SPT</name>
14042                  <description>Dynamic MEM_RET_EMU support</description>
14043                  <bitRange>[23:23]</bitRange>
14044                  <access>read-only</access>
14045                </field>
14046                <field>
14047                  <name>DYN_LGC_RET_SPT</name>
14048                  <description>Dynamic LOGIC_RET support.</description>
14049                  <bitRange>[24:24]</bitRange>
14050                  <access>read-only</access>
14051                </field>
14052                <field>
14053                  <name>DYN_MEM_OFF_SPT</name>
14054                  <description>Dynamic MEM_OFF support.</description>
14055                  <bitRange>[25:25]</bitRange>
14056                  <access>read-only</access>
14057                </field>
14058                <field>
14059                  <name>DYN_FULL_RET_SPT</name>
14060                  <description>Dynamic FULL_RET support.</description>
14061                  <bitRange>[26:26]</bitRange>
14062                  <access>read-only</access>
14063                </field>
14064                <field>
14065                  <name>DYN_FUNC_RET_SPT</name>
14066                  <description>Dynamic FUNC_RET support.</description>
14067                  <bitRange>[27:27]</bitRange>
14068                  <access>read-only</access>
14069                </field>
14070                <field>
14071                  <name>DYN_ON_SPT</name>
14072                  <description>Dynamic ON support.</description>
14073                  <bitRange>[28:28]</bitRange>
14074                  <access>read-only</access>
14075                </field>
14076                <field>
14077                  <name>DYN_WRM_RST_SPT</name>
14078                  <description>Dynamic WARM_RST support.</description>
14079                  <bitRange>[29:29]</bitRange>
14080                  <access>read-only</access>
14081                </field>
14082              </fields>
14083            </register>
14084            <register>
14085              <name>IDR1</name>
14086              <description>PPU Identification Register 1</description>
14087              <addressOffset>0xFB4</addressOffset>
14088              <size>32</size>
14089              <access>read-only</access>
14090              <resetValue>0x0</resetValue>
14091              <resetMask>0x1777</resetMask>
14092              <fields>
14093                <field>
14094                  <name>PWR_MODE_ENTRY_DEL_SPT</name>
14095                  <description>Power mode entry delay support.</description>
14096                  <bitRange>[0:0]</bitRange>
14097                  <access>read-only</access>
14098                </field>
14099                <field>
14100                  <name>SW_DEV_DEL_SPT</name>
14101                  <description>Software device delay control configuration support.</description>
14102                  <bitRange>[1:1]</bitRange>
14103                  <access>read-only</access>
14104                </field>
14105                <field>
14106                  <name>LOCK_SPT</name>
14107                  <description>Lock and the lock interrupt event are supported.</description>
14108                  <bitRange>[2:2]</bitRange>
14109                  <access>read-only</access>
14110                </field>
14111                <field>
14112                  <name>MEM_RET_RAM_REG</name>
14113                  <description>N/A</description>
14114                  <bitRange>[4:4]</bitRange>
14115                  <access>read-only</access>
14116                </field>
14117                <field>
14118                  <name>FULL_RET_RAM_REG</name>
14119                  <description>N/A</description>
14120                  <bitRange>[5:5]</bitRange>
14121                  <access>read-only</access>
14122                </field>
14123                <field>
14124                  <name>FUNC_RET_RAM_REG</name>
14125                  <description>N/A</description>
14126                  <bitRange>[6:6]</bitRange>
14127                  <access>read-only</access>
14128                </field>
14129                <field>
14130                  <name>STA_POLICY_PWR_IRQ_SPT</name>
14131                  <description>Power policy transition completion event status.</description>
14132                  <bitRange>[8:8]</bitRange>
14133                  <access>read-only</access>
14134                </field>
14135                <field>
14136                  <name>STA_POLICY_OP_IRQ_SPT</name>
14137                  <description>Operating policy transition completion event status.</description>
14138                  <bitRange>[9:9]</bitRange>
14139                  <access>read-only</access>
14140                </field>
14141                <field>
14142                  <name>OP_ACTIVE</name>
14143                  <description>N/A</description>
14144                  <bitRange>[10:10]</bitRange>
14145                  <access>read-only</access>
14146                </field>
14147                <field>
14148                  <name>OFF_MEM_RET_TRANS</name>
14149                  <description>OFF to MEM_RET direct transition.  Indicates if direct transitions from OFF to MEM_RET and from OFF_EMU to MEM_RET_EMU are supported.</description>
14150                  <bitRange>[12:12]</bitRange>
14151                  <access>read-only</access>
14152                </field>
14153              </fields>
14154            </register>
14155            <register>
14156              <name>IIDR</name>
14157              <description>Implementation Identification Register</description>
14158              <addressOffset>0xFC8</addressOffset>
14159              <size>32</size>
14160              <access>read-only</access>
14161              <resetValue>0xB50043B</resetValue>
14162              <resetMask>0xFFFFFFFF</resetMask>
14163              <fields>
14164                <field>
14165                  <name>IMPLEMENTER</name>
14166                  <description>Implementer identification.  [11:8] The JEP106 continuation code of the implementer.  [7] Always 0.  [6:0] The JEP106 identity code of the implementer.  For an Arm implementation, bits [11:0] are 0x43B.</description>
14167                  <bitRange>[11:0]</bitRange>
14168                  <access>read-only</access>
14169                </field>
14170                <field>
14171                  <name>REVISION</name>
14172                  <description>Minor revision of the product.</description>
14173                  <bitRange>[15:12]</bitRange>
14174                  <access>read-only</access>
14175                </field>
14176                <field>
14177                  <name>VARIANT</name>
14178                  <description>Major revision of the product.</description>
14179                  <bitRange>[19:16]</bitRange>
14180                  <access>read-only</access>
14181                </field>
14182                <field>
14183                  <name>PRODUCT_ID</name>
14184                  <description>PPU part identification.</description>
14185                  <bitRange>[31:20]</bitRange>
14186                  <access>read-only</access>
14187                </field>
14188              </fields>
14189            </register>
14190            <register>
14191              <name>AIDR</name>
14192              <description>Architecture Identification Register</description>
14193              <addressOffset>0xFCC</addressOffset>
14194              <size>32</size>
14195              <access>read-only</access>
14196              <resetValue>0x11</resetValue>
14197              <resetMask>0xFF</resetMask>
14198              <fields>
14199                <field>
14200                  <name>ARCH_REV_MINOR</name>
14201                  <description>N/A</description>
14202                  <bitRange>[3:0]</bitRange>
14203                  <access>read-only</access>
14204                </field>
14205                <field>
14206                  <name>ARCH_REV_MAJOR</name>
14207                  <description>N/A</description>
14208                  <bitRange>[7:4]</bitRange>
14209                  <access>read-only</access>
14210                </field>
14211              </fields>
14212            </register>
14213          </cluster>
14214        </cluster>
14215        <register>
14216          <name>CLK_SELECT</name>
14217          <description>Clock Selection for Power Mode Components</description>
14218          <addressOffset>0x2000</addressOffset>
14219          <size>32</size>
14220          <access>read-write</access>
14221          <resetValue>0x0</resetValue>
14222          <resetMask>0x300FF</resetMask>
14223          <fields>
14224            <field>
14225              <name>CLK_PWR_DIV</name>
14226              <description>clk_pwr is generated by dividing the CLK_PWR_MUX selection by (CLK_PWR_DIV+1).</description>
14227              <bitRange>[7:0]</bitRange>
14228              <access>read-write</access>
14229            </field>
14230            <field>
14231              <name>CLK_PWR_MUX</name>
14232              <description>Selects a source for the clock used by power control components.  Note that not all products support all clock sources.  Selecting a clock source that is not supported will result in undefined behavior.  It takes four cycles of the originally selected clock to switch away from it.  Do not disable the original clock during this time.</description>
14233              <bitRange>[17:16]</bitRange>
14234              <access>read-write</access>
14235              <enumeratedValues>
14236                <enumeratedValue>
14237                  <name>IMO</name>
14238                  <description>IMO - Internal R/C Oscillator</description>
14239                  <value>0</value>
14240                </enumeratedValue>
14241                <enumeratedValue>
14242                  <name>IHO</name>
14243                  <description>IHO - Internal High-speed Oscillator</description>
14244                  <value>1</value>
14245                </enumeratedValue>
14246                <enumeratedValue>
14247                  <name>RSVD</name>
14248                  <description>N/A</description>
14249                  <value>2</value>
14250                </enumeratedValue>
14251              </enumeratedValues>
14252            </field>
14253          </fields>
14254        </register>
14255      </registers>
14256    </peripheral>
14257    <peripheral>
14258      <name>BACKUP</name>
14259      <description>SRSS Backup Registers</description>
14260      <baseAddress>0x40220000</baseAddress>
14261      <addressBlock>
14262        <offset>0</offset>
14263        <size>65536</size>
14264        <usage>registers</usage>
14265      </addressBlock>
14266      <registers>
14267        <register>
14268          <name>CTL</name>
14269          <description>Control</description>
14270          <addressOffset>0x0</addressOffset>
14271          <size>32</size>
14272          <access>read-write</access>
14273          <resetValue>0x0</resetValue>
14274          <resetMask>0xFF0F3708</resetMask>
14275          <fields>
14276            <field>
14277              <name>WCO_EN</name>
14278              <description>Watch-crystal oscillator (WCO) enable.  If there is a write in progress when this bit is cleared, the WCO will be internally kept on until the write completes.
14279After enabling the WCO software must wait until STATUS.WCO_OK=1 before configuring any component that depends on clk_lf/clk_bak, like for example RTC or WDTs.  Follow the procedure in BACKUP_RTC_RW to access this bit.</description>
14280              <bitRange>[3:3]</bitRange>
14281              <access>read-write</access>
14282            </field>
14283            <field>
14284              <name>CLK_SEL</name>
14285              <description>Clock select for RTC clock</description>
14286              <bitRange>[10:8]</bitRange>
14287              <access>read-write</access>
14288              <enumeratedValues>
14289                <enumeratedValue>
14290                  <name>WCO</name>
14291                  <description>Watch-crystal oscillator input, available in Active, DeepSleep, Hibernate, and XRES.  For products with an independent vbackup supply, it can continue operating in OFF w/Backup mode.</description>
14292                  <value>0</value>
14293                </enumeratedValue>
14294                <enumeratedValue>
14295                  <name>ALTBAK</name>
14296                  <description>This allows to use the LFCLK selection as an alternate backup domain clock. Note that LFCLK is only available in Active and DeepSleep power modes.
14297Note that LFCLK clock glitches can propagate into the backup logic when the clock is stopped.  For this reason, if the WCO or ILO is intended as the clock source then choose it directly instead of routing through LFCLK.</description>
14298                  <value>1</value>
14299                </enumeratedValue>
14300                <enumeratedValue>
14301                  <name>ILO</name>
14302                  <description>Internal Low frequency Oscillator, available in Active, DeepSleep, Hibernate, and XRES.  For products with an independent vbackup supply, it can continue operating in OFF w/Backup mode.
14303For Hibernate operation CLK_ILO0_CONFIG. ILO_BACKUP must be set.  If there are multiple ILO, this is ILO0.</description>
14304                  <value>2</value>
14305                </enumeratedValue>
14306                <enumeratedValue>
14307                  <name>LPECO_PRESCALER</name>
14308                  <description>Low-power external crystal oscillator prescaler output, available in Active, DeepSleep, Hibernate, and XRES.  For products with an independent vbackup supply, it can continue operating in OFF w/Backup mode.</description>
14309                  <value>3</value>
14310                </enumeratedValue>
14311                <enumeratedValue>
14312                  <name>PILO</name>
14313                  <description>Precision internal low-speed oscillator, available in Active, DeepSleep, Hibernate, and XRES.  For products with an independent vbackup supply, it can continue operating in OFF w/Backup mode.</description>
14314                  <value>4</value>
14315                </enumeratedValue>
14316              </enumeratedValues>
14317            </field>
14318            <field>
14319              <name>PRESCALER</name>
14320              <description>N/A</description>
14321              <bitRange>[13:12]</bitRange>
14322              <access>read-write</access>
14323            </field>
14324            <field>
14325              <name>WCO_BYPASS</name>
14326              <description>Configures the WCO for different board-level connections to the WCO pins.  For example, this can be used to connect an external watch crystal oscillator instead of a watch crystal.   In all cases, the two related GPIO pins (WCO input and output pins) must be configured as analog connections using GPIO registers, and they must be hooked at the board level as described below.  Configure this field before enabling the WCO, and do not change this setting when WCO_EN=1.
143270: Watch crystal.  Connect a 32.768 kHz watch crystal between WCO input and output pins.
143281: Clock signal, either a square wave or sine wave.  See PRESCALER field for connection information.</description>
14329              <bitRange>[16:16]</bitRange>
14330              <access>read-write</access>
14331            </field>
14332            <field>
14333              <name>VDDBAK_CTL</name>
14334              <description>Controls the behavior of the switch that generates vddbak from vbackup or vddd.
143350: automatically select vddd if its brownout detector says it is valid.  If the brownout says its not valid, then use vmax which is the highest of vddd or vbackup.
143361,2,3: force vddbak and vmax to select vbackup, regardless of its voltage.</description>
14337              <bitRange>[18:17]</bitRange>
14338              <access>read-write</access>
14339            </field>
14340            <field>
14341              <name>VBACKUP_MEAS</name>
14342              <description>Connect vbackup supply to the vbackup_meas output for measurement by an ADC attached to amuxbusa_adft_vddd.  The vbackup_meas signal is scaled to 10 percent of vbackup, so it is within the supply range of the ADC.</description>
14343              <bitRange>[19:19]</bitRange>
14344              <access>read-write</access>
14345            </field>
14346            <field>
14347              <name>EN_CHARGE_KEY</name>
14348              <description>When set to 3C, the supercap charger circuit is enabled.  Any other code disables the supercap charger.  THIS CHARGING CIRCUIT IS FOR A SUPERCAP ONLY AND CANNOT SAFELY CHARGE A BATTERY.  DO NOT WRITE THIS KEY WHEN VBACKUP IS CONNECTED TO A BATTERY.</description>
14349              <bitRange>[31:24]</bitRange>
14350              <access>read-write</access>
14351            </field>
14352          </fields>
14353        </register>
14354        <register>
14355          <name>RTC_RW</name>
14356          <description>RTC Read Write register</description>
14357          <addressOffset>0x8</addressOffset>
14358          <size>32</size>
14359          <access>read-write</access>
14360          <resetValue>0x0</resetValue>
14361          <resetMask>0x3</resetMask>
14362          <fields>
14363            <field>
14364              <name>READ</name>
14365              <description>Read bit
14366When this bit is set the RTC registers will be copied to user registers and frozen so that a coherent RTC value can safely be read. The RTC will keep on running.
14367Do not set the read bit if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Write bit is set. Do not set the Read bit at the same time that the Write bit is cleared.</description>
14368              <bitRange>[0:0]</bitRange>
14369              <access>read-write</access>
14370            </field>
14371            <field>
14372              <name>WRITE</name>
14373              <description>Write bit
14374Only when this bit is set can the RTC registers be written to (otherwise writes are ignored). This bit cannot be set if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Read bit is set or getting set.
14375The user writes to the RTC user registers, when the Write bit is cleared by the user then the user registers content is copied to the actual RTC registers.
14376Only user RTC registers that were written to will get copied, others will not be affected.
14377When the SECONDS field is updated then TICKS will also be reset (WDT is not affected).
14378When the Write bit is cleared by a reset (brown out/DeepSleep) then the RTC update will be ignored/lost.
14379Do not set the Write bit if the RTC if the RTC is still busy with a previous update (see RTC_BUSY).  Do not set the Write bit at the same time that the Read bit is cleared.</description>
14380              <bitRange>[1:1]</bitRange>
14381              <access>read-write</access>
14382            </field>
14383          </fields>
14384        </register>
14385        <register>
14386          <name>CAL_CTL</name>
14387          <description>Oscillator calibration for absolute frequency</description>
14388          <addressOffset>0xC</addressOffset>
14389          <size>32</size>
14390          <access>read-write</access>
14391          <resetValue>0x0</resetValue>
14392          <resetMask>0xB003007F</resetMask>
14393          <fields>
14394            <field>
14395              <name>CALIB_VAL</name>
14396              <description>Calibration value for absolute frequency (at a fixed temperature).  Each step causes 128 ticks to be added or removed each hour.  Effectively that means that each step is 1.085ppm (= 128/(60*60*32,768)) when CAL_COMP_PER_MIN is set at default value.
14397Positive values 0x01-0x3c (1..60) add pulses, negative values remove pulses, thus giving a range of +/-65.1 ppm (limited by 60 minutes per hour, not the range of this field) when CAL_COMP_PER_MIN is set at default value .
14398
14399Calibration is performed hourly, starting at 59 minutes and 59 seconds, and applied as 64 ticks every 30 seconds until there have been 2*CALIB_VAL adjustments when CAL_COMP_PER_MIN is set at default value .</description>
14400              <bitRange>[5:0]</bitRange>
14401              <access>read-write</access>
14402            </field>
14403            <field>
14404              <name>CALIB_SIGN</name>
14405              <description>Calibration sign:
144060= Negative sign: remove pulses (it takes more clock ticks to count one second)
144071= Positive sign: add pulses (it takes less clock ticks to count one second)</description>
14408              <bitRange>[6:6]</bitRange>
14409              <access>read-write</access>
14410            </field>
14411            <field>
14412              <name>CAL_COMP_PER_MIN</name>
14413              <description>Select how many time calibration is performed per minute  per step of 64 , each time a 64 step is added or substracted one unit 2/4/8/16*CALIB_VAL is substracted.</description>
14414              <bitRange>[17:16]</bitRange>
14415              <access>read-write</access>
14416              <enumeratedValues>
14417                <enumeratedValue>
14418                  <name>2</name>
14419                  <description>Calibration of 64 each is performed twice per minute for 2*CALIB_VAL per hour</description>
14420                  <value>0</value>
14421                </enumeratedValue>
14422                <enumeratedValue>
14423                  <name>4</name>
14424                  <description>Calibration of 64 each is performed four times per minute for 4*CALIB_VAL per hour</description>
14425                  <value>1</value>
14426                </enumeratedValue>
14427                <enumeratedValue>
14428                  <name>8</name>
14429                  <description>Calibration of 64 each is performed eight  times per minute for 8*CALIB_VAL per hour</description>
14430                  <value>2</value>
14431                </enumeratedValue>
14432                <enumeratedValue>
14433                  <name>16</name>
14434                  <description>Calibration of 64 each is performed sixteen times per minute for 16*CALIB_VAL per hour</description>
14435                  <value>3</value>
14436                </enumeratedValue>
14437              </enumeratedValues>
14438            </field>
14439            <field>
14440              <name>CAL_SEL</name>
14441              <description>Select calibration wave output signal</description>
14442              <bitRange>[29:28]</bitRange>
14443              <access>read-write</access>
14444              <enumeratedValues>
14445                <enumeratedValue>
14446                  <name>CAL512</name>
14447                  <description>512Hz wave, not affected by calibration setting (not supported for 50/60Hz input clock: CTL.PRESCALER!=0)</description>
14448                  <value>0</value>
14449                </enumeratedValue>
14450                <enumeratedValue>
14451                  <name>RSVD</name>
14452                  <description>N/A</description>
14453                  <value>1</value>
14454                </enumeratedValue>
14455                <enumeratedValue>
14456                  <name>CAL2</name>
14457                  <description>2Hz wave, includes the effect of the calibration setting, (not supported for 50/60Hz input clock: CTL.PRESCALER!=0)</description>
14458                  <value>2</value>
14459                </enumeratedValue>
14460                <enumeratedValue>
14461                  <name>CAL1</name>
14462                  <description>1Hz wave, includes the effect of the calibration setting (supported for all input clocks)</description>
14463                  <value>3</value>
14464                </enumeratedValue>
14465              </enumeratedValues>
14466            </field>
14467            <field>
14468              <name>CAL_OUT</name>
14469              <description>Output enable for wave signal for calibration and allow CALIB_VAL to be written.</description>
14470              <bitRange>[31:31]</bitRange>
14471              <access>read-write</access>
14472            </field>
14473          </fields>
14474        </register>
14475        <register>
14476          <name>STATUS</name>
14477          <description>Status</description>
14478          <addressOffset>0x10</addressOffset>
14479          <size>32</size>
14480          <access>read-only</access>
14481          <resetValue>0x0</resetValue>
14482          <resetMask>0x5</resetMask>
14483          <fields>
14484            <field>
14485              <name>RTC_BUSY</name>
14486              <description>Pending RTC write</description>
14487              <bitRange>[0:0]</bitRange>
14488              <access>read-only</access>
14489            </field>
14490            <field>
14491              <name>WCO_OK</name>
14492              <description>Obsolete.  Use WCO_STATUS.WCO_OK for future designs.</description>
14493              <bitRange>[2:2]</bitRange>
14494              <access>read-only</access>
14495            </field>
14496          </fields>
14497        </register>
14498        <register>
14499          <name>RTC_TIME</name>
14500          <description>Calendar Seconds, Minutes, Hours, Day of Week</description>
14501          <addressOffset>0x14</addressOffset>
14502          <size>32</size>
14503          <access>read-write</access>
14504          <resetValue>0x1000000</resetValue>
14505          <resetMask>0x75F3F3F</resetMask>
14506          <fields>
14507            <field>
14508              <name>RTC_SEC</name>
14509              <description>Calendar seconds, 0-59</description>
14510              <bitRange>[5:0]</bitRange>
14511              <access>read-write</access>
14512            </field>
14513            <field>
14514              <name>RTC_MIN</name>
14515              <description>Calendar minutes, 0-59</description>
14516              <bitRange>[13:8]</bitRange>
14517              <access>read-write</access>
14518            </field>
14519            <field>
14520              <name>RTC_HOUR</name>
14521              <description>Calendar hours, value depending on 12/24HR mode
145220=24HR: [20:16]=0-23
145231=12HR: [20]:0=AM, 1=PM, [19:16]=1-12</description>
14524              <bitRange>[20:16]</bitRange>
14525              <access>read-write</access>
14526            </field>
14527            <field>
14528              <name>CTRL_12HR</name>
14529              <description>Select 12/24HR mode: 1=12HR, 0=24HR</description>
14530              <bitRange>[22:22]</bitRange>
14531              <access>read-write</access>
14532            </field>
14533            <field>
14534              <name>RTC_DAY</name>
14535              <description>Calendar Day of the week, 1-7
14536It is up to the user to define the meaning of the values, but 1=Monday is recommended</description>
14537              <bitRange>[26:24]</bitRange>
14538              <access>read-write</access>
14539            </field>
14540          </fields>
14541        </register>
14542        <register>
14543          <name>RTC_DATE</name>
14544          <description>Calendar Day of Month, Month,  Year</description>
14545          <addressOffset>0x18</addressOffset>
14546          <size>32</size>
14547          <access>read-write</access>
14548          <resetValue>0x101</resetValue>
14549          <resetMask>0x7F0F1F</resetMask>
14550          <fields>
14551            <field>
14552              <name>RTC_DATE</name>
14553              <description>Calendar Day of the Month, 1-31
14554Automatic Leap Year Correction</description>
14555              <bitRange>[4:0]</bitRange>
14556              <access>read-write</access>
14557            </field>
14558            <field>
14559              <name>RTC_MON</name>
14560              <description>Calendar Month, 1-12</description>
14561              <bitRange>[11:8]</bitRange>
14562              <access>read-write</access>
14563            </field>
14564            <field>
14565              <name>RTC_YEAR</name>
14566              <description>Calendar year, 0-99</description>
14567              <bitRange>[22:16]</bitRange>
14568              <access>read-write</access>
14569            </field>
14570          </fields>
14571        </register>
14572        <register>
14573          <name>ALM1_TIME</name>
14574          <description>Alarm 1 Seconds, Minute, Hours, Day of Week</description>
14575          <addressOffset>0x1C</addressOffset>
14576          <size>32</size>
14577          <access>read-write</access>
14578          <resetValue>0x1000000</resetValue>
14579          <resetMask>0x879FBFBF</resetMask>
14580          <fields>
14581            <field>
14582              <name>ALM_SEC</name>
14583              <description>Alarm seconds, 0-59</description>
14584              <bitRange>[5:0]</bitRange>
14585              <access>read-write</access>
14586            </field>
14587            <field>
14588              <name>ALM_SEC_EN</name>
14589              <description>Alarm second enable: 0=ignore, 1=match</description>
14590              <bitRange>[7:7]</bitRange>
14591              <access>read-write</access>
14592            </field>
14593            <field>
14594              <name>ALM_MIN</name>
14595              <description>Alarm minutes, 0-59</description>
14596              <bitRange>[13:8]</bitRange>
14597              <access>read-write</access>
14598            </field>
14599            <field>
14600              <name>ALM_MIN_EN</name>
14601              <description>Alarm minutes enable: 0=ignore, 1=match</description>
14602              <bitRange>[15:15]</bitRange>
14603              <access>read-write</access>
14604            </field>
14605            <field>
14606              <name>ALM_HOUR</name>
14607              <description>Alarm hours, value depending on 12/24HR mode
1460824HR: [4:0]=0-23
1460912HR: [4]:0=AM, 1=PM, [3:0]=1-12</description>
14610              <bitRange>[20:16]</bitRange>
14611              <access>read-write</access>
14612            </field>
14613            <field>
14614              <name>ALM_HOUR_EN</name>
14615              <description>Alarm hour enable: 0=ignore, 1=match</description>
14616              <bitRange>[23:23]</bitRange>
14617              <access>read-write</access>
14618            </field>
14619            <field>
14620              <name>ALM_DAY</name>
14621              <description>Alarm Day of the week, 1-7
14622It is up to the user to define the meaning of the values, but 1=Monday is recommended</description>
14623              <bitRange>[26:24]</bitRange>
14624              <access>read-write</access>
14625            </field>
14626            <field>
14627              <name>ALM_DAY_EN</name>
14628              <description>Alarm Day of the Week enable: 0=ignore, 1=match</description>
14629              <bitRange>[31:31]</bitRange>
14630              <access>read-write</access>
14631            </field>
14632          </fields>
14633        </register>
14634        <register>
14635          <name>ALM1_DATE</name>
14636          <description>Alarm 1 Day of Month, Month</description>
14637          <addressOffset>0x20</addressOffset>
14638          <size>32</size>
14639          <access>read-write</access>
14640          <resetValue>0x101</resetValue>
14641          <resetMask>0x80008F9F</resetMask>
14642          <fields>
14643            <field>
14644              <name>ALM_DATE</name>
14645              <description>Alarm Day of the Month, 1-31
14646Leap Year corrected</description>
14647              <bitRange>[4:0]</bitRange>
14648              <access>read-write</access>
14649            </field>
14650            <field>
14651              <name>ALM_DATE_EN</name>
14652              <description>Alarm Day of the Month enable: 0=ignore, 1=match</description>
14653              <bitRange>[7:7]</bitRange>
14654              <access>read-write</access>
14655            </field>
14656            <field>
14657              <name>ALM_MON</name>
14658              <description>Alarm Month, 1-12</description>
14659              <bitRange>[11:8]</bitRange>
14660              <access>read-write</access>
14661            </field>
14662            <field>
14663              <name>ALM_MON_EN</name>
14664              <description>Alarm Month enable: 0=ignore, 1=match</description>
14665              <bitRange>[15:15]</bitRange>
14666              <access>read-write</access>
14667            </field>
14668            <field>
14669              <name>ALM_EN</name>
14670              <description>Master enable for alarm 1.
146710: Alarm 1 is disabled.  Fields for date and time are ignored.
146721: Alarm 1 is enabled.  Alarm triggers whenever the new date and time matches all the enabled date and time fields, which can happen more than once depending on configuration.  If none of the date and time fields are enabled, then this alarm triggers once every second.</description>
14673              <bitRange>[31:31]</bitRange>
14674              <access>read-write</access>
14675            </field>
14676          </fields>
14677        </register>
14678        <register>
14679          <name>ALM2_TIME</name>
14680          <description>Alarm 2 Seconds, Minute, Hours, Day of Week</description>
14681          <addressOffset>0x24</addressOffset>
14682          <size>32</size>
14683          <access>read-write</access>
14684          <resetValue>0x1000000</resetValue>
14685          <resetMask>0x879FBFBF</resetMask>
14686          <fields>
14687            <field>
14688              <name>ALM_SEC</name>
14689              <description>Alarm seconds, 0-59</description>
14690              <bitRange>[5:0]</bitRange>
14691              <access>read-write</access>
14692            </field>
14693            <field>
14694              <name>ALM_SEC_EN</name>
14695              <description>Alarm second enable: 0=ignore, 1=match</description>
14696              <bitRange>[7:7]</bitRange>
14697              <access>read-write</access>
14698            </field>
14699            <field>
14700              <name>ALM_MIN</name>
14701              <description>Alarm minutes, 0-59</description>
14702              <bitRange>[13:8]</bitRange>
14703              <access>read-write</access>
14704            </field>
14705            <field>
14706              <name>ALM_MIN_EN</name>
14707              <description>Alarm minutes enable: 0=ignore, 1=match</description>
14708              <bitRange>[15:15]</bitRange>
14709              <access>read-write</access>
14710            </field>
14711            <field>
14712              <name>ALM_HOUR</name>
14713              <description>Alarm hours, value depending on 12/24HR mode
1471424HR: [4:0]=0-23
1471512HR: [4]:0=AM, 1=PM, [3:0]=1-12</description>
14716              <bitRange>[20:16]</bitRange>
14717              <access>read-write</access>
14718            </field>
14719            <field>
14720              <name>ALM_HOUR_EN</name>
14721              <description>Alarm hour enable: 0=ignore, 1=match</description>
14722              <bitRange>[23:23]</bitRange>
14723              <access>read-write</access>
14724            </field>
14725            <field>
14726              <name>ALM_DAY</name>
14727              <description>Alarm Day of the week, 1-7
14728It is up to the user to define the meaning of the values, but 1=Monday is recommended</description>
14729              <bitRange>[26:24]</bitRange>
14730              <access>read-write</access>
14731            </field>
14732            <field>
14733              <name>ALM_DAY_EN</name>
14734              <description>Alarm Day of the Week enable: 0=ignore, 1=match</description>
14735              <bitRange>[31:31]</bitRange>
14736              <access>read-write</access>
14737            </field>
14738          </fields>
14739        </register>
14740        <register>
14741          <name>ALM2_DATE</name>
14742          <description>Alarm 2 Day of Month, Month</description>
14743          <addressOffset>0x28</addressOffset>
14744          <size>32</size>
14745          <access>read-write</access>
14746          <resetValue>0x101</resetValue>
14747          <resetMask>0x80008F9F</resetMask>
14748          <fields>
14749            <field>
14750              <name>ALM_DATE</name>
14751              <description>Alarm Day of the Month, 1-31
14752Leap Year corrected</description>
14753              <bitRange>[4:0]</bitRange>
14754              <access>read-write</access>
14755            </field>
14756            <field>
14757              <name>ALM_DATE_EN</name>
14758              <description>Alarm Day of the Month enable: 0=ignore, 1=match</description>
14759              <bitRange>[7:7]</bitRange>
14760              <access>read-write</access>
14761            </field>
14762            <field>
14763              <name>ALM_MON</name>
14764              <description>Alarm Month, 1-12</description>
14765              <bitRange>[11:8]</bitRange>
14766              <access>read-write</access>
14767            </field>
14768            <field>
14769              <name>ALM_MON_EN</name>
14770              <description>Alarm Month enable: 0=ignore, 1=match</description>
14771              <bitRange>[15:15]</bitRange>
14772              <access>read-write</access>
14773            </field>
14774            <field>
14775              <name>ALM_EN</name>
14776              <description>Master enable for alarm 2.
147770: Alarm 2 is disabled.  Fields for date and time are ignored.
147781: Alarm 2 is enabled.  Alarm triggers whenever the new date and time matches all the enabled date and time fields, which can happen more than once depending on configuration.  If none of the date and time fields are enabled, then this alarm triggers once every second.</description>
14779              <bitRange>[31:31]</bitRange>
14780              <access>read-write</access>
14781            </field>
14782          </fields>
14783        </register>
14784        <register>
14785          <name>INTR</name>
14786          <description>Interrupt request register</description>
14787          <addressOffset>0x2C</addressOffset>
14788          <size>32</size>
14789          <access>read-write</access>
14790          <resetValue>0x0</resetValue>
14791          <resetMask>0x7</resetMask>
14792          <fields>
14793            <field>
14794              <name>ALARM1</name>
14795              <description>Alarm 1 Interrupt</description>
14796              <bitRange>[0:0]</bitRange>
14797              <access>read-write</access>
14798            </field>
14799            <field>
14800              <name>ALARM2</name>
14801              <description>Alarm 2 Interrupt</description>
14802              <bitRange>[1:1]</bitRange>
14803              <access>read-write</access>
14804            </field>
14805            <field>
14806              <name>CENTURY</name>
14807              <description>Century overflow interrupt</description>
14808              <bitRange>[2:2]</bitRange>
14809              <access>read-write</access>
14810            </field>
14811          </fields>
14812        </register>
14813        <register>
14814          <name>INTR_SET</name>
14815          <description>Interrupt set request register</description>
14816          <addressOffset>0x30</addressOffset>
14817          <size>32</size>
14818          <access>read-write</access>
14819          <resetValue>0x0</resetValue>
14820          <resetMask>0x7</resetMask>
14821          <fields>
14822            <field>
14823              <name>ALARM1</name>
14824              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
14825              <bitRange>[0:0]</bitRange>
14826              <access>read-write</access>
14827            </field>
14828            <field>
14829              <name>ALARM2</name>
14830              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
14831              <bitRange>[1:1]</bitRange>
14832              <access>read-write</access>
14833            </field>
14834            <field>
14835              <name>CENTURY</name>
14836              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
14837              <bitRange>[2:2]</bitRange>
14838              <access>read-write</access>
14839            </field>
14840          </fields>
14841        </register>
14842        <register>
14843          <name>INTR_MASK</name>
14844          <description>Interrupt mask register</description>
14845          <addressOffset>0x34</addressOffset>
14846          <size>32</size>
14847          <access>read-write</access>
14848          <resetValue>0x0</resetValue>
14849          <resetMask>0x7</resetMask>
14850          <fields>
14851            <field>
14852              <name>ALARM1</name>
14853              <description>Mask bit for corresponding bit in interrupt request register.</description>
14854              <bitRange>[0:0]</bitRange>
14855              <access>read-write</access>
14856            </field>
14857            <field>
14858              <name>ALARM2</name>
14859              <description>Mask bit for corresponding bit in interrupt request register.</description>
14860              <bitRange>[1:1]</bitRange>
14861              <access>read-write</access>
14862            </field>
14863            <field>
14864              <name>CENTURY</name>
14865              <description>Mask bit for corresponding bit in interrupt request register.</description>
14866              <bitRange>[2:2]</bitRange>
14867              <access>read-write</access>
14868            </field>
14869          </fields>
14870        </register>
14871        <register>
14872          <name>INTR_MASKED</name>
14873          <description>Interrupt masked request register</description>
14874          <addressOffset>0x38</addressOffset>
14875          <size>32</size>
14876          <access>read-only</access>
14877          <resetValue>0x0</resetValue>
14878          <resetMask>0x7</resetMask>
14879          <fields>
14880            <field>
14881              <name>ALARM1</name>
14882              <description>Logical and of corresponding request and mask bits.</description>
14883              <bitRange>[0:0]</bitRange>
14884              <access>read-only</access>
14885            </field>
14886            <field>
14887              <name>ALARM2</name>
14888              <description>Logical and of corresponding request and mask bits.</description>
14889              <bitRange>[1:1]</bitRange>
14890              <access>read-only</access>
14891            </field>
14892            <field>
14893              <name>CENTURY</name>
14894              <description>Logical and of corresponding request and mask bits.</description>
14895              <bitRange>[2:2]</bitRange>
14896              <access>read-only</access>
14897            </field>
14898          </fields>
14899        </register>
14900        <register>
14901          <name>RESET</name>
14902          <description>Backup reset register</description>
14903          <addressOffset>0x48</addressOffset>
14904          <size>32</size>
14905          <access>read-write</access>
14906          <resetValue>0x0</resetValue>
14907          <resetMask>0x80000000</resetMask>
14908          <fields>
14909            <field>
14910              <name>RESET</name>
14911              <description>Writing 1 to this register resets the backup logic.  Hardware clears it when the reset is complete.  After setting this register, firmware should confirm it reads as 0 before attempting to write other backup registers.</description>
14912              <bitRange>[31:31]</bitRange>
14913              <access>read-write</access>
14914            </field>
14915          </fields>
14916        </register>
14917        <register>
14918          <name>WCO_STATUS</name>
14919          <description>WCO Status Register</description>
14920          <addressOffset>0x90</addressOffset>
14921          <size>32</size>
14922          <access>read-only</access>
14923          <resetValue>0x0</resetValue>
14924          <resetMask>0x4</resetMask>
14925          <fields>
14926            <field>
14927              <name>WCO_OK</name>
14928              <description>Indicates that output has transitioned.</description>
14929              <bitRange>[2:2]</bitRange>
14930              <access>read-only</access>
14931            </field>
14932          </fields>
14933        </register>
14934        <register>
14935          <dim>4</dim>
14936          <dimIncrement>4</dimIncrement>
14937          <name>BREG_SET0[%s]</name>
14938          <description>Backup register region 0</description>
14939          <addressOffset>0x1000</addressOffset>
14940          <size>32</size>
14941          <access>read-write</access>
14942          <resetValue>0x0</resetValue>
14943          <resetMask>0xFFFFFFFF</resetMask>
14944          <fields>
14945            <field>
14946              <name>BREG</name>
14947              <description>Backup memory that contains application-specific data.  Memory is retained on vbackup supply.</description>
14948              <bitRange>[31:0]</bitRange>
14949              <access>read-write</access>
14950            </field>
14951          </fields>
14952        </register>
14953        <register>
14954          <dim>4</dim>
14955          <dimIncrement>4</dimIncrement>
14956          <name>BREG_SET1[%s]</name>
14957          <description>Backup register region 1</description>
14958          <addressOffset>0x1010</addressOffset>
14959          <size>32</size>
14960          <access>read-write</access>
14961          <resetValue>0x0</resetValue>
14962          <resetMask>0xFFFFFFFF</resetMask>
14963          <fields>
14964            <field>
14965              <name>BREG</name>
14966              <description>Backup memory that contains application-specific data.  Memory is retained on vbackup supply.</description>
14967              <bitRange>[31:0]</bitRange>
14968              <access>read-write</access>
14969            </field>
14970          </fields>
14971        </register>
14972        <register>
14973          <dim>8</dim>
14974          <dimIncrement>4</dimIncrement>
14975          <name>BREG_SET2[%s]</name>
14976          <description>Backup register region 2</description>
14977          <addressOffset>0x1020</addressOffset>
14978          <size>32</size>
14979          <access>read-write</access>
14980          <resetValue>0x0</resetValue>
14981          <resetMask>0xFFFFFFFF</resetMask>
14982          <fields>
14983            <field>
14984              <name>BREG</name>
14985              <description>Backup memory that contains application-specific data.  Memory is retained on vbackup supply.</description>
14986              <bitRange>[31:0]</bitRange>
14987              <access>read-write</access>
14988            </field>
14989          </fields>
14990        </register>
14991      </registers>
14992    </peripheral>
14993    <peripheral>
14994      <name>CRYPTOLITE</name>
14995      <description>N/A</description>
14996      <baseAddress>0x40230000</baseAddress>
14997      <addressBlock>
14998        <offset>0</offset>
14999        <size>65536</size>
15000        <usage>registers</usage>
15001      </addressBlock>
15002      <registers>
15003        <register>
15004          <name>CTL</name>
15005          <description>Control</description>
15006          <addressOffset>0x0</addressOffset>
15007          <size>32</size>
15008          <access>read-only</access>
15009          <resetValue>0x0</resetValue>
15010          <resetMask>0xF00</resetMask>
15011          <fields>
15012            <field>
15013              <name>P</name>
15014              <description>User/privileged access control:
15015'0': user mode.
15016'1': privileged mode.
15017
15018This field is set with the user/privileged access control of the transaction that writes any (including possible memory holes in the IP aperture) of the CRYPTO component registers; i.e. the access control is inherited from the write transaction and not specified by the transaction write data.
15019
15020All CRYPTO component master transactions use the P field for the user/privileged access control ('hprot[1]').</description>
15021              <bitRange>[0:0]</bitRange>
15022              <access>read-only</access>
15023            </field>
15024            <field>
15025              <name>NS</name>
15026              <description>Secure/on-secure access control:
15027'0': secure.
15028'1': non-secure.
15029
15030This field is set with the secure/non-secure access control of the transaction that writes  any (including possible memory holes in the IP aperture) of the CRYPTO component registers; i.e. the access control is inherited from the write transaction and not specified by the transaction write data.
15031
15032All CRYPTO component master transactions use the NS field for the secure/non-secure access control ('hprot[4]').</description>
15033              <bitRange>[1:1]</bitRange>
15034              <access>read-only</access>
15035            </field>
15036            <field>
15037              <name>PC</name>
15038              <description>Protection context.
15039
15040This field is set with the protection context of the transaction that writes any (including possible memory holes in the IP aperture) of the CRYPTO component registers; i.e. the context is inherited from the write transaction and not specified by the transaction write data.
15041
15042All CRYPTO component master transactions use the PC field for the protection context.</description>
15043              <bitRange>[7:4]</bitRange>
15044              <access>read-only</access>
15045            </field>
15046            <field>
15047              <name>MS</name>
15048              <description>Master identifier of the cryptography IP. This is a design time configurable parameter.</description>
15049              <bitRange>[11:8]</bitRange>
15050              <access>read-only</access>
15051            </field>
15052          </fields>
15053        </register>
15054        <register>
15055          <name>STATUS</name>
15056          <description>Status</description>
15057          <addressOffset>0x4</addressOffset>
15058          <size>32</size>
15059          <access>read-only</access>
15060          <resetValue>0x0</resetValue>
15061          <resetMask>0x1</resetMask>
15062          <fields>
15063            <field>
15064              <name>BUSY</name>
15065              <description>Busy indication:
15066'0': IP not busy.
15067'1': IP busy (AES, SHA or VU functionality (TRNG functionality NOT included)).</description>
15068              <bitRange>[0:0]</bitRange>
15069              <access>read-only</access>
15070            </field>
15071          </fields>
15072        </register>
15073        <register>
15074          <name>AES_DESCR</name>
15075          <description>AES descriptor pointer</description>
15076          <addressOffset>0x40</addressOffset>
15077          <size>32</size>
15078          <access>read-write</access>
15079          <resetValue>0x0</resetValue>
15080          <resetMask>0x0</resetMask>
15081          <fields>
15082            <field>
15083              <name>PTR</name>
15084              <description>AES descriptor pointer. The descriptor points to a structure with 32-bit words:
15085Word 0: Pointer to a 128-bit AES key.
15086Word 1: Pointer to a 128-bit source/plaintext.
15087Word 2: Pointer to a 128-bit destination/ciphertext.
15088
15089A write to this register automatically starts a 128-bit AES encryption in ECB mode. The write ONLY takes effect when the IP is NOT busy (STATUS.BUSY is '0'). The write will be made pending/blocked as long as the IP is busy.
15090
15091Note: the pointers must be 4B aligned.
15092
15093Note: HW updates this field when the AES engine is busy.</description>
15094              <bitRange>[31:2]</bitRange>
15095              <access>read-write</access>
15096            </field>
15097          </fields>
15098        </register>
15099        <register>
15100          <name>VU_DESCR</name>
15101          <description>VU descriptor pointer</description>
15102          <addressOffset>0x80</addressOffset>
15103          <size>32</size>
15104          <access>read-write</access>
15105          <resetValue>0x0</resetValue>
15106          <resetMask>0x0</resetMask>
15107          <fields>
15108            <field>
15109              <name>PTR</name>
15110              <description>VU descriptor pointer. The descriptor points to a structure with 32-bit words:
15111Word 0: Control word. Specifies operand size in 32-bit word multiples.
15112- WORD[7:0]: Source operand 0 32-bit words (minus 1).
15113- WORD[15:8]: Source operand 1 32-bit words (minus 1).
15114- WORD[24:16]: Destination operand 32-bit words (minus 1).
15115- WORD[31:28]: Opcode. '0': multiplication (MUL), '1': addition (ADD), '2': subtraction (SUB), '3': exclusive or (XOR), '4': binary multiplication (XMUL), '5': logical shift right by 1 (LSR1), '6': logical shift left by 1 (LSL1), '7': logical shift right (LSR), '8': conditional syubtraction (COND_SUB). '9': move (MOV).
15116Word 1: Pointer to source 0.
15117Word 2: Pointer to source 1.
15118Word 3: Pointer to destination.
15119
15120A write to this register automatically starts a VU operation. The write ONLY takes effect when the IP is NOT busy (STATUS.BUSY is '0'). The write will be made pending/blocked as long as the IP is busy.
15121
15122Note: the pointers must be 4B aligned.
15123
15124Note: HW updates this field when the VU engine is busy.</description>
15125              <bitRange>[31:2]</bitRange>
15126              <access>read-write</access>
15127            </field>
15128          </fields>
15129        </register>
15130        <register>
15131          <name>SHA_DESCR</name>
15132          <description>SHA descriptor pointer</description>
15133          <addressOffset>0xC0</addressOffset>
15134          <size>32</size>
15135          <access>read-write</access>
15136          <resetValue>0x0</resetValue>
15137          <resetMask>0x0</resetMask>
15138          <fields>
15139            <field>
15140              <name>PTR</name>
15141              <description>SHA-256 descriptor pointer. The descriptor points to a structure with 32-bit words:
15142For message schedule function:
15143Word 0: Control word.
15144- WORD0[28]: '0' for message schedule function.
15145Word 1: Pointer to 512 b message chunk (input).
15146Word 2: Pointer to 64 * 32 b word message schedule array (output).
15147For process function:
15148Word 0: Control word.
15149- WORD0[28]: '1' for process function.
15150Word 1: Pointer to 8 * 32 b word current hash value (input) and new hash value (output).
15151Word 2: Pointer to 64 * 32 b word message schedule array (input).
15152
15153A write to this register automatically starts a SHA-256 operation. The write ONLY takes effect when the IP is NOT busy (STATUS.BUSY is '0'). The write will be made pending/blocked as long as the IP is busy.
15154
15155Note: the pointers must be 32-bit word aligned.
15156
15157Note: HW updates this field when the SHA-256 engine is busy.</description>
15158              <bitRange>[31:2]</bitRange>
15159              <access>read-write</access>
15160            </field>
15161          </fields>
15162        </register>
15163        <register>
15164          <name>INTR_ERROR</name>
15165          <description>Error interrupt</description>
15166          <addressOffset>0xF0</addressOffset>
15167          <size>32</size>
15168          <access>read-write</access>
15169          <resetValue>0x0</resetValue>
15170          <resetMask>0x1</resetMask>
15171          <fields>
15172            <field>
15173              <name>BUS_ERROR</name>
15174              <description>AHB-Lite master interface bus error or ECC error. Note that the IP terminates its AES, SHA or VU functionality when it detects an error.
15175
15176Note: The error is sticky. This allows SW to check for an error after a series of operations, rather than checking after every individual operation.</description>
15177              <bitRange>[0:0]</bitRange>
15178              <access>read-write</access>
15179            </field>
15180          </fields>
15181        </register>
15182        <register>
15183          <name>INTR_ERROR_SET</name>
15184          <description>Error interrupt set</description>
15185          <addressOffset>0xF4</addressOffset>
15186          <size>32</size>
15187          <access>read-write</access>
15188          <resetValue>0x0</resetValue>
15189          <resetMask>0x1</resetMask>
15190          <fields>
15191            <field>
15192              <name>BUS_ERROR</name>
15193              <description>Write this field with '1' to set corresponding INTR_ERROR field to '1' (a write of '0' has no effect).</description>
15194              <bitRange>[0:0]</bitRange>
15195              <access>read-write</access>
15196            </field>
15197          </fields>
15198        </register>
15199        <register>
15200          <name>INTR_ERROR_MASK</name>
15201          <description>Error interrupt mask</description>
15202          <addressOffset>0xF8</addressOffset>
15203          <size>32</size>
15204          <access>read-write</access>
15205          <resetValue>0x0</resetValue>
15206          <resetMask>0x1</resetMask>
15207          <fields>
15208            <field>
15209              <name>BUS_ERROR</name>
15210              <description>Mask for corresponding field in INTR_ERROR register.</description>
15211              <bitRange>[0:0]</bitRange>
15212              <access>read-write</access>
15213            </field>
15214          </fields>
15215        </register>
15216        <register>
15217          <name>INTR_ERROR_MASKED</name>
15218          <description>Error interrupt masked</description>
15219          <addressOffset>0xFC</addressOffset>
15220          <size>32</size>
15221          <access>read-only</access>
15222          <resetValue>0x0</resetValue>
15223          <resetMask>0x1</resetMask>
15224          <fields>
15225            <field>
15226              <name>BUS_ERROR</name>
15227              <description>Logical and of corresponding INTR_ERROR and INTR_ERROR_MASK fields.</description>
15228              <bitRange>[0:0]</bitRange>
15229              <access>read-only</access>
15230            </field>
15231          </fields>
15232        </register>
15233        <register>
15234          <name>TRNG_CTL0</name>
15235          <description>TRNG control 0</description>
15236          <addressOffset>0x100</addressOffset>
15237          <size>32</size>
15238          <access>read-write</access>
15239          <resetValue>0x33030000</resetValue>
15240          <resetMask>0x33FFFFFF</resetMask>
15241          <fields>
15242            <field>
15243              <name>SAMPLE_CLOCK_DIV</name>
15244              <description>Specifies the clock divider that is used to sample oscillator data. This clock divider is wrt. The IP clock.
15245'0': sample clock is the IP clock.
15246'1': sample clock is the IP clock divided by 2.
15247...
15248'255': sample clock is the IP clock divided by 256.</description>
15249              <bitRange>[7:0]</bitRange>
15250              <access>read-write</access>
15251            </field>
15252            <field>
15253              <name>RED_CLOCK_DIV</name>
15254              <description>Specifies the clock divider that is used to produce reduced bits.
15255'0': 1 reduced bit is produced for each sample.
15256'1': 1 reduced bit is produced for each 2 samples.
15257...
15258'255': 1 reduced bit is produced for each 256 samples.
15259
15260The reduced bits are considered random bits and shifted into TRNG_RESULT.DATA.</description>
15261              <bitRange>[15:8]</bitRange>
15262              <access>read-write</access>
15263            </field>
15264            <field>
15265              <name>INIT_DELAY</name>
15266              <description>Specifies an initialization delay: number of removed/dropped samples before reduced bits are generated. This field should be programmed in the range [1, 255]. After starting the oscillators, at least the first 2 samples should be removed/dropped to clear the state of internal synchronizers. In addition, it is advised to drop at least the second 2 samples from the oscillators (to circumvent the semi-predictable oscillator startup behavior). This result in the default field value of '3'. Field encoding is as follows:
15267'0': 1 sample is dropped.
15268'1': 2 samples are dropped.
15269...
15270'255': 256 samples are dropped.
15271
15272The INTR.INITIALIZED interrupt cause is set to '1', when the initialization delay is passed.</description>
15273              <bitRange>[23:16]</bitRange>
15274              <access>read-write</access>
15275            </field>
15276            <field>
15277              <name>VON_NEUMANN_CORR</name>
15278              <description>Specifies if the 'von Neumann corrector' is disabled or enabled:
15279'0': disabled.
15280'1': enabled.
15281The 'von Neumann corrector' post-processes the reduced bits to remove a '0' or '1' bias. The corrector operates on reduced bit pairs ('oldest bit, newest bit'):
15282'00': no bit is produced.
15283'01': '0' bit is produced (oldest bit).
15284'10': '1' bit is produced (oldest bit).
15285'11': no bit is produced.
15286Note that the corrector produces bits at a random pace and at a frequency that is 1/4 of the reduced bit frequency (reduced bits are processed in pairs, and half of the pairs do NOT produce a bit).</description>
15287              <bitRange>[24:24]</bitRange>
15288              <access>read-write</access>
15289            </field>
15290            <field>
15291              <name>FEEDBACK_EN</name>
15292              <description>Specifies if the feedback of the reducution state is enabled:
15293'0': Disabled.
15294'1': Enabled.
15295
15296Note: This field is added in the 'mxcryptolite' IP to address CDT#337111, in which it was observed that the reduction state feedback reduces  the effectiveness of the 'von Neumann corrector'. The default value is '1' to provide backward compatibility.</description>
15297              <bitRange>[25:25]</bitRange>
15298              <access>read-write</access>
15299            </field>
15300            <field>
15301              <name>STOP_ON_AP_DETECT</name>
15302              <description>Specifies if TRNG functionality is stopped on an adaptive proportion test detection (when HW sets INTR_ERROR.TRNG_AP_DETECT to '1'):
15303'0': Functionality is NOT stopped.
15304'1': Functionality is stopped (TRNG_CTL1 fields are set to '0' by HW). The DAS bitstream is set to '0'.</description>
15305              <bitRange>[28:28]</bitRange>
15306              <access>read-write</access>
15307            </field>
15308            <field>
15309              <name>STOP_ON_RC_DETECT</name>
15310              <description>Specifies if TRNG functionality is stopped on a repetition count test detection (when HW sets INTR_ERROR.TRNG_RC_DETECT to '1'):
15311'0': Functionality is NOT stopped.
15312'1': Functionality is stopped (TRNG_CTL1 fields are set to '0' by HW). The DAS bitstream is set to '0'.</description>
15313              <bitRange>[29:29]</bitRange>
15314              <access>read-write</access>
15315            </field>
15316          </fields>
15317        </register>
15318        <register>
15319          <name>TRNG_CTL1</name>
15320          <description>TRNG control 1</description>
15321          <addressOffset>0x104</addressOffset>
15322          <size>32</size>
15323          <access>read-write</access>
15324          <resetValue>0x0</resetValue>
15325          <resetMask>0x3F</resetMask>
15326          <fields>
15327            <field>
15328              <name>RO11_EN</name>
15329              <description>FW sets this field to '1' to enable the ring oscillator with 11 inverters.</description>
15330              <bitRange>[0:0]</bitRange>
15331              <access>read-write</access>
15332            </field>
15333            <field>
15334              <name>RO15_EN</name>
15335              <description>FW sets this field to '1' to enable the ring oscillator with 15 inverters.</description>
15336              <bitRange>[1:1]</bitRange>
15337              <access>read-write</access>
15338            </field>
15339            <field>
15340              <name>GARO15_EN</name>
15341              <description>FW sets this field to '1' to enable the fixed Galois ring oscillator with 15 inverters.</description>
15342              <bitRange>[2:2]</bitRange>
15343              <access>read-write</access>
15344            </field>
15345            <field>
15346              <name>GARO31_EN</name>
15347              <description>FW sets this field to '1' to enable the programmable Galois ring oscillator with up to 31 inverters. The TRNG_GARO_CTL register specifies the programmable polynomial.</description>
15348              <bitRange>[3:3]</bitRange>
15349              <access>read-write</access>
15350            </field>
15351            <field>
15352              <name>FIRO15_EN</name>
15353              <description>FW sets this field to '1' to enable the fixed Fibonacci ring oscillator with 15 inverters.</description>
15354              <bitRange>[4:4]</bitRange>
15355              <access>read-write</access>
15356            </field>
15357            <field>
15358              <name>FIRO31_EN</name>
15359              <description>FW sets this field to '1' to enable the programmable Fibonacci ring oscillator with up to 31 inverters. The TRNG_FIRO_CTL register specifies the programmable polynomial.</description>
15360              <bitRange>[5:5]</bitRange>
15361              <access>read-write</access>
15362            </field>
15363          </fields>
15364        </register>
15365        <register>
15366          <name>TRNG_STATUS</name>
15367          <description>TRNG status</description>
15368          <addressOffset>0x10C</addressOffset>
15369          <size>32</size>
15370          <access>read-only</access>
15371          <resetValue>0x0</resetValue>
15372          <resetMask>0x1</resetMask>
15373          <fields>
15374            <field>
15375              <name>INITIALIZED</name>
15376              <description>Reflects the state of the true random number generator:
15377'0': Not initialized (TRNG_CTL0.INIT_DELAY has NOT passed).
15378'1': Initialized (TRNG_CTL0.INIT_DELAY has passed).</description>
15379              <bitRange>[0:0]</bitRange>
15380              <access>read-only</access>
15381            </field>
15382          </fields>
15383        </register>
15384        <register>
15385          <name>TRNG_RESULT</name>
15386          <description>TRNG result</description>
15387          <addressOffset>0x110</addressOffset>
15388          <size>32</size>
15389          <access>read-only</access>
15390          <resetValue>0x0</resetValue>
15391          <resetMask>0x0</resetMask>
15392          <fields>
15393            <field>
15394              <name>DATA</name>
15395              <description>Generated 32-bit true random number. The INTR.DATA_AVAILABLE interrupt cause is activated when the number is generated.</description>
15396              <bitRange>[31:0]</bitRange>
15397              <access>read-only</access>
15398            </field>
15399          </fields>
15400        </register>
15401        <register>
15402          <name>TRNG_GARO_CTL</name>
15403          <description>TRNG GARO control</description>
15404          <addressOffset>0x120</addressOffset>
15405          <size>32</size>
15406          <access>read-write</access>
15407          <resetValue>0x21F81910</resetValue>
15408          <resetMask>0x7FFFFFFF</resetMask>
15409          <fields>
15410            <field>
15411              <name>POLYNOMIAL</name>
15412              <description>Polynomial for programmable Galois ring oscillator. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned such that the more significant bits (bit 30 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's.
15413
15414Note: Default value per GESC#113.</description>
15415              <bitRange>[30:0]</bitRange>
15416              <access>read-write</access>
15417            </field>
15418          </fields>
15419        </register>
15420        <register>
15421          <name>TRNG_FIRO_CTL</name>
15422          <description>TRNG FIRO control</description>
15423          <addressOffset>0x124</addressOffset>
15424          <size>32</size>
15425          <access>read-write</access>
15426          <resetValue>0x696F0221</resetValue>
15427          <resetMask>0x7FFFFFFF</resetMask>
15428          <fields>
15429            <field>
15430              <name>POLYNOMIAL</name>
15431              <description>Polynomial for programmable Fibonacci ring oscillator. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned such that the more significant bits (bit 30 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's.
15432
15433Note: Default value per GESC#113.</description>
15434              <bitRange>[30:0]</bitRange>
15435              <access>read-write</access>
15436            </field>
15437          </fields>
15438        </register>
15439        <register>
15440          <name>TRNG_MON_CTL</name>
15441          <description>TRNG monitor control</description>
15442          <addressOffset>0x140</addressOffset>
15443          <size>32</size>
15444          <access>read-write</access>
15445          <resetValue>0x2</resetValue>
15446          <resetMask>0x303</resetMask>
15447          <fields>
15448            <field>
15449              <name>BITSTREAM_SEL</name>
15450              <description>Selection of the bitstream:
15451'0': DAS bitstream.
15452'1': RED bitstream.
15453'2': TR bitstream.
15454'3': Undefined.</description>
15455              <bitRange>[1:0]</bitRange>
15456              <access>read-write</access>
15457            </field>
15458            <field>
15459              <name>AP</name>
15460              <description>Adaptive proportion (AP) test enable:
15461'0': Disabled.
15462'1': Enabled.
15463
15464On a AP detection, HW sets this field to '0' and sets INTR_ERROR.TRNG_AP_DETECT to '1.</description>
15465              <bitRange>[8:8]</bitRange>
15466              <access>read-write</access>
15467            </field>
15468            <field>
15469              <name>RC</name>
15470              <description>Repetition count (RC) test enable:
15471'0': Disabled.
15472'1': Enabled.
15473
15474On a RC detection, HW sets this field to '0' and sets INTR_ERROR.TRNG_RC_DETECT to '1.</description>
15475              <bitRange>[9:9]</bitRange>
15476              <access>read-write</access>
15477            </field>
15478          </fields>
15479        </register>
15480        <register>
15481          <name>TRNG_MON_RC_CTL</name>
15482          <description>TRNG monitor RC control</description>
15483          <addressOffset>0x150</addressOffset>
15484          <size>32</size>
15485          <access>read-write</access>
15486          <resetValue>0xFF</resetValue>
15487          <resetMask>0xFF</resetMask>
15488          <fields>
15489            <field>
15490              <name>CUTOFF_COUNT8</name>
15491              <description>Cutoff count (legal range is [1, 255]):
15492'0': Illegal.
15493'1': 1 repetition.
15494...
15495'255': 255 repetitions.</description>
15496              <bitRange>[7:0]</bitRange>
15497              <access>read-write</access>
15498            </field>
15499          </fields>
15500        </register>
15501        <register>
15502          <name>TRNG_MON_RC_STATUS0</name>
15503          <description>TRNG monitor RC status 0</description>
15504          <addressOffset>0x158</addressOffset>
15505          <size>32</size>
15506          <access>read-only</access>
15507          <resetValue>0x0</resetValue>
15508          <resetMask>0x1</resetMask>
15509          <fields>
15510            <field>
15511              <name>BIT</name>
15512              <description>Current active bit value:
15513'0': '0'.
15514'1': '1'.
15515
15516This field is only valid when TRNG_MON_RC_STATUS1.REP_COUNT is NOT equal to '0'.</description>
15517              <bitRange>[0:0]</bitRange>
15518              <access>read-only</access>
15519            </field>
15520          </fields>
15521        </register>
15522        <register>
15523          <name>TRNG_MON_RC_STATUS1</name>
15524          <description>TRNG monitor RC status 1</description>
15525          <addressOffset>0x15C</addressOffset>
15526          <size>32</size>
15527          <access>read-only</access>
15528          <resetValue>0x0</resetValue>
15529          <resetMask>0xFF</resetMask>
15530          <fields>
15531            <field>
15532              <name>REP_COUNT</name>
15533              <description>Number of repetitions of the current active bit counter:
15534'0': 0 repetitions.
15535...
15536'255': 255 repetitions.</description>
15537              <bitRange>[7:0]</bitRange>
15538              <access>read-only</access>
15539            </field>
15540          </fields>
15541        </register>
15542        <register>
15543          <name>TRNG_MON_AP_CTL</name>
15544          <description>TRNG monitor AP control</description>
15545          <addressOffset>0x160</addressOffset>
15546          <size>32</size>
15547          <access>read-write</access>
15548          <resetValue>0xFFFFFFFF</resetValue>
15549          <resetMask>0xFFFFFFFF</resetMask>
15550          <fields>
15551            <field>
15552              <name>CUTOFF_COUNT16</name>
15553              <description>Cutoff count (legal range is [1, 65535]).
15554'0': Illegal.
15555'1': 1 occurrence.
15556...
15557'65535': 65535 occurrences.</description>
15558              <bitRange>[15:0]</bitRange>
15559              <access>read-write</access>
15560            </field>
15561            <field>
15562              <name>WINDOW_SIZE</name>
15563              <description>Window size (minus 1) :
15564'0': 1 bit.
15565...
15566'65535': 65536 bits.</description>
15567              <bitRange>[31:16]</bitRange>
15568              <access>read-write</access>
15569            </field>
15570          </fields>
15571        </register>
15572        <register>
15573          <name>TRNG_MON_AP_STATUS0</name>
15574          <description>TRNG monitor AP status 0</description>
15575          <addressOffset>0x168</addressOffset>
15576          <size>32</size>
15577          <access>read-only</access>
15578          <resetValue>0x0</resetValue>
15579          <resetMask>0x1</resetMask>
15580          <fields>
15581            <field>
15582              <name>BIT</name>
15583              <description>Current active bit value:
15584'0': '0'.
15585'1': '1'.
15586
15587This field is only valid when TRNG_MON_AP_STATUS1.OCC_COUNT is NOT equal to '0'.</description>
15588              <bitRange>[0:0]</bitRange>
15589              <access>read-only</access>
15590            </field>
15591          </fields>
15592        </register>
15593        <register>
15594          <name>TRNG_MON_AP_STATUS1</name>
15595          <description>TRNG monitor AP status 1</description>
15596          <addressOffset>0x16C</addressOffset>
15597          <size>32</size>
15598          <access>read-only</access>
15599          <resetValue>0x0</resetValue>
15600          <resetMask>0xFFFFFFFF</resetMask>
15601          <fields>
15602            <field>
15603              <name>OCC_COUNT</name>
15604              <description>Number of occurrences of the current active bit counter:
15605'0': 0 occurrences
15606...
15607'65535': 65535 occurrences</description>
15608              <bitRange>[15:0]</bitRange>
15609              <access>read-only</access>
15610            </field>
15611            <field>
15612              <name>WINDOW_INDEX</name>
15613              <description>Counter to keep track of the current index in the window (counts from '0' to TRNG_MON_AP_CTL.WINDOW_SIZE to '0').</description>
15614              <bitRange>[31:16]</bitRange>
15615              <access>read-only</access>
15616            </field>
15617          </fields>
15618        </register>
15619        <register>
15620          <name>INTR_TRNG</name>
15621          <description>TRNG interrupt</description>
15622          <addressOffset>0x1F0</addressOffset>
15623          <size>32</size>
15624          <access>read-write</access>
15625          <resetValue>0x0</resetValue>
15626          <resetMask>0xF</resetMask>
15627          <fields>
15628            <field>
15629              <name>INITIALIZED</name>
15630              <description>This interrupt cause is activated (HW sets the field to '1') when the TRNG is initialized.</description>
15631              <bitRange>[0:0]</bitRange>
15632              <access>read-write</access>
15633            </field>
15634            <field>
15635              <name>DATA_AVAILABLE</name>
15636              <description>This interrupt cause is activated (HW sets the field to '1') when 32 bits of TRNG data becomes available in TRNG_RESULT.</description>
15637              <bitRange>[1:1]</bitRange>
15638              <access>read-write</access>
15639            </field>
15640            <field>
15641              <name>AP_DETECT</name>
15642              <description>This interrupt cause is activated (HW sets the field to '1') when the TRNG monitor detects an 'adaptive proportion' error.</description>
15643              <bitRange>[2:2]</bitRange>
15644              <access>read-write</access>
15645            </field>
15646            <field>
15647              <name>RC_DETECT</name>
15648              <description>This interrupt cause is activated (HW sets the field to '1') when the TRNG monitor detects an 'repetition count' error.</description>
15649              <bitRange>[3:3]</bitRange>
15650              <access>read-write</access>
15651            </field>
15652          </fields>
15653        </register>
15654        <register>
15655          <name>INTR_TRNG_SET</name>
15656          <description>TRNG Interrupt set</description>
15657          <addressOffset>0x1F4</addressOffset>
15658          <size>32</size>
15659          <access>read-write</access>
15660          <resetValue>0x0</resetValue>
15661          <resetMask>0xF</resetMask>
15662          <fields>
15663            <field>
15664              <name>INITIALIZED</name>
15665              <description>SW writes a '1' to this field to set the corresponding field in interrupt request register.</description>
15666              <bitRange>[0:0]</bitRange>
15667              <access>read-write</access>
15668            </field>
15669            <field>
15670              <name>DATA_AVAILABLE</name>
15671              <description>SW writes a '1' to this field to set the corresponding field in interrupt request register.</description>
15672              <bitRange>[1:1]</bitRange>
15673              <access>read-write</access>
15674            </field>
15675            <field>
15676              <name>AP_DETECT</name>
15677              <description>SW writes a '1' to this field to set the corresponding field in interrupt request register.</description>
15678              <bitRange>[2:2]</bitRange>
15679              <access>read-write</access>
15680            </field>
15681            <field>
15682              <name>RC_DETECT</name>
15683              <description>SW writes a '1' to this field to set the corresponding field in interrupt request register.</description>
15684              <bitRange>[3:3]</bitRange>
15685              <access>read-write</access>
15686            </field>
15687          </fields>
15688        </register>
15689        <register>
15690          <name>INTR_TRNG_MASK</name>
15691          <description>TRNG Interrupt mask</description>
15692          <addressOffset>0x1F8</addressOffset>
15693          <size>32</size>
15694          <access>read-write</access>
15695          <resetValue>0x0</resetValue>
15696          <resetMask>0xF</resetMask>
15697          <fields>
15698            <field>
15699              <name>INITIALIZED</name>
15700              <description>Mask bit for corresponding field in interrupt request register.</description>
15701              <bitRange>[0:0]</bitRange>
15702              <access>read-write</access>
15703            </field>
15704            <field>
15705              <name>DATA_AVAILABLE</name>
15706              <description>Mask bit for corresponding field in interrupt request register.</description>
15707              <bitRange>[1:1]</bitRange>
15708              <access>read-write</access>
15709            </field>
15710            <field>
15711              <name>AP_DETECT</name>
15712              <description>Mask bit for corresponding field in interrupt request register.</description>
15713              <bitRange>[2:2]</bitRange>
15714              <access>read-write</access>
15715            </field>
15716            <field>
15717              <name>RC_DETECT</name>
15718              <description>Mask bit for corresponding field in interrupt request register.</description>
15719              <bitRange>[3:3]</bitRange>
15720              <access>read-write</access>
15721            </field>
15722          </fields>
15723        </register>
15724        <register>
15725          <name>INTR_TRNG_MASKED</name>
15726          <description>TRNG Interrupt masked</description>
15727          <addressOffset>0x1FC</addressOffset>
15728          <size>32</size>
15729          <access>read-only</access>
15730          <resetValue>0x0</resetValue>
15731          <resetMask>0xF</resetMask>
15732          <fields>
15733            <field>
15734              <name>INITIALIZED</name>
15735              <description>Logical and of corresponding request and mask bits.</description>
15736              <bitRange>[0:0]</bitRange>
15737              <access>read-only</access>
15738            </field>
15739            <field>
15740              <name>DATA_AVAILABLE</name>
15741              <description>Logical and of corresponding request and mask bits.</description>
15742              <bitRange>[1:1]</bitRange>
15743              <access>read-only</access>
15744            </field>
15745            <field>
15746              <name>AP_DETECT</name>
15747              <description>Logical and of corresponding request and mask bits.</description>
15748              <bitRange>[2:2]</bitRange>
15749              <access>read-only</access>
15750            </field>
15751            <field>
15752              <name>RC_DETECT</name>
15753              <description>Logical and of corresponding request and mask bits.</description>
15754              <bitRange>[3:3]</bitRange>
15755              <access>read-only</access>
15756            </field>
15757          </fields>
15758        </register>
15759      </registers>
15760    </peripheral>
15761    <peripheral>
15762      <name>HSIOM</name>
15763      <description>IO Matrix (IOM)</description>
15764      <baseAddress>0x40400000</baseAddress>
15765      <addressBlock>
15766        <offset>0</offset>
15767        <size>16384</size>
15768        <usage>registers</usage>
15769      </addressBlock>
15770      <registers>
15771        <cluster>
15772          <dim>6</dim>
15773          <dimIncrement>16</dimIncrement>
15774          <name>PRT[%s]</name>
15775          <description>HSIOM port registers</description>
15776          <addressOffset>0x00000000</addressOffset>
15777          <register>
15778            <name>PORT_SEL0</name>
15779            <description>Port selection 0</description>
15780            <addressOffset>0x0</addressOffset>
15781            <size>32</size>
15782            <access>read-write</access>
15783            <resetValue>0x0</resetValue>
15784            <resetMask>0x1F1F1F1F</resetMask>
15785            <fields>
15786              <field>
15787                <name>IO0_SEL</name>
15788                <description>Selects connection for IO pin 0 route.</description>
15789                <bitRange>[4:0]</bitRange>
15790                <access>read-write</access>
15791                <enumeratedValues>
15792                  <enumeratedValue>
15793                    <name>GPIO</name>
15794                    <description>GPIO controls 'out'</description>
15795                    <value>0</value>
15796                  </enumeratedValue>
15797                  <enumeratedValue>
15798                    <name>GPIO_DSI</name>
15799                    <description>GPIO controls 'out', DSI controls 'output enable'</description>
15800                    <value>1</value>
15801                  </enumeratedValue>
15802                  <enumeratedValue>
15803                    <name>DSI_DSI</name>
15804                    <description>DSI controls 'out' and 'output enable'</description>
15805                    <value>2</value>
15806                  </enumeratedValue>
15807                  <enumeratedValue>
15808                    <name>DSI_GPIO</name>
15809                    <description>DSI controls 'out', GPIO controls 'output enable'</description>
15810                    <value>3</value>
15811                  </enumeratedValue>
15812                  <enumeratedValue>
15813                    <name>AMUXA</name>
15814                    <description>Analog mux bus A</description>
15815                    <value>4</value>
15816                  </enumeratedValue>
15817                  <enumeratedValue>
15818                    <name>AMUXB</name>
15819                    <description>Analog mux bus B</description>
15820                    <value>5</value>
15821                  </enumeratedValue>
15822                  <enumeratedValue>
15823                    <name>AMUXA_DSI</name>
15824                    <description>Analog mux bus A, DSI control</description>
15825                    <value>6</value>
15826                  </enumeratedValue>
15827                  <enumeratedValue>
15828                    <name>AMUXB_DSI</name>
15829                    <description>Analog mux bus B, DSI control</description>
15830                    <value>7</value>
15831                  </enumeratedValue>
15832                  <enumeratedValue>
15833                    <name>ACT_0</name>
15834                    <description>Active functionality 0</description>
15835                    <value>8</value>
15836                  </enumeratedValue>
15837                  <enumeratedValue>
15838                    <name>ACT_1</name>
15839                    <description>Active functionality 1</description>
15840                    <value>9</value>
15841                  </enumeratedValue>
15842                  <enumeratedValue>
15843                    <name>ACT_2</name>
15844                    <description>Active functionality 2</description>
15845                    <value>10</value>
15846                  </enumeratedValue>
15847                  <enumeratedValue>
15848                    <name>ACT_3</name>
15849                    <description>Active functionality 3</description>
15850                    <value>11</value>
15851                  </enumeratedValue>
15852                  <enumeratedValue>
15853                    <name>DS_0</name>
15854                    <description>DeepSleep functionality 0</description>
15855                    <value>12</value>
15856                  </enumeratedValue>
15857                  <enumeratedValue>
15858                    <name>DS_1</name>
15859                    <description>DeepSleep functionality 1</description>
15860                    <value>13</value>
15861                  </enumeratedValue>
15862                  <enumeratedValue>
15863                    <name>DS_2</name>
15864                    <description>DeepSleep functionality 2</description>
15865                    <value>14</value>
15866                  </enumeratedValue>
15867                  <enumeratedValue>
15868                    <name>DS_3</name>
15869                    <description>DeepSleep functionality 3</description>
15870                    <value>15</value>
15871                  </enumeratedValue>
15872                  <enumeratedValue>
15873                    <name>ACT_4</name>
15874                    <description>Active functionality 4</description>
15875                    <value>16</value>
15876                  </enumeratedValue>
15877                  <enumeratedValue>
15878                    <name>ACT_5</name>
15879                    <description>Active functionality 5</description>
15880                    <value>17</value>
15881                  </enumeratedValue>
15882                  <enumeratedValue>
15883                    <name>ACT_6</name>
15884                    <description>Active functionality 6</description>
15885                    <value>18</value>
15886                  </enumeratedValue>
15887                  <enumeratedValue>
15888                    <name>ACT_7</name>
15889                    <description>Active functionality 7</description>
15890                    <value>19</value>
15891                  </enumeratedValue>
15892                  <enumeratedValue>
15893                    <name>ACT_8</name>
15894                    <description>Active functionality 8</description>
15895                    <value>20</value>
15896                  </enumeratedValue>
15897                  <enumeratedValue>
15898                    <name>ACT_9</name>
15899                    <description>Active functionality 9</description>
15900                    <value>21</value>
15901                  </enumeratedValue>
15902                  <enumeratedValue>
15903                    <name>ACT_10</name>
15904                    <description>Active functionality 10</description>
15905                    <value>22</value>
15906                  </enumeratedValue>
15907                  <enumeratedValue>
15908                    <name>ACT_11</name>
15909                    <description>Active functionality 11</description>
15910                    <value>23</value>
15911                  </enumeratedValue>
15912                  <enumeratedValue>
15913                    <name>ACT_12</name>
15914                    <description>Active functionality 12</description>
15915                    <value>24</value>
15916                  </enumeratedValue>
15917                  <enumeratedValue>
15918                    <name>ACT_13</name>
15919                    <description>Active functionality 13</description>
15920                    <value>25</value>
15921                  </enumeratedValue>
15922                  <enumeratedValue>
15923                    <name>ACT_14</name>
15924                    <description>Active functionality 14</description>
15925                    <value>26</value>
15926                  </enumeratedValue>
15927                  <enumeratedValue>
15928                    <name>ACT_15</name>
15929                    <description>Active functionality 15</description>
15930                    <value>27</value>
15931                  </enumeratedValue>
15932                  <enumeratedValue>
15933                    <name>DS_4</name>
15934                    <description>DeepSleep functionality 4</description>
15935                    <value>28</value>
15936                  </enumeratedValue>
15937                  <enumeratedValue>
15938                    <name>DS_5</name>
15939                    <description>DeepSleep functionality 5</description>
15940                    <value>29</value>
15941                  </enumeratedValue>
15942                  <enumeratedValue>
15943                    <name>DS_6</name>
15944                    <description>DeepSleep functionality 6</description>
15945                    <value>30</value>
15946                  </enumeratedValue>
15947                  <enumeratedValue>
15948                    <name>DS_7</name>
15949                    <description>DeepSleep functionality 7</description>
15950                    <value>31</value>
15951                  </enumeratedValue>
15952                </enumeratedValues>
15953              </field>
15954              <field>
15955                <name>IO1_SEL</name>
15956                <description>Selects connection for IO pin 1 route.</description>
15957                <bitRange>[12:8]</bitRange>
15958                <access>read-write</access>
15959              </field>
15960              <field>
15961                <name>IO2_SEL</name>
15962                <description>Selects connection for IO pin 2 route.</description>
15963                <bitRange>[20:16]</bitRange>
15964                <access>read-write</access>
15965              </field>
15966              <field>
15967                <name>IO3_SEL</name>
15968                <description>Selects connection for IO pin 3 route.</description>
15969                <bitRange>[28:24]</bitRange>
15970                <access>read-write</access>
15971              </field>
15972            </fields>
15973          </register>
15974          <register>
15975            <name>PORT_SEL1</name>
15976            <description>Port selection 1</description>
15977            <addressOffset>0x4</addressOffset>
15978            <size>32</size>
15979            <access>read-write</access>
15980            <resetValue>0x0</resetValue>
15981            <resetMask>0x1F1F1F1F</resetMask>
15982            <fields>
15983              <field>
15984                <name>IO4_SEL</name>
15985                <description>Selects connection for IO pin 4 route.
15986See PORT_SEL0 for connection details.</description>
15987                <bitRange>[4:0]</bitRange>
15988                <access>read-write</access>
15989              </field>
15990              <field>
15991                <name>IO5_SEL</name>
15992                <description>Selects connection for IO pin 5 route.</description>
15993                <bitRange>[12:8]</bitRange>
15994                <access>read-write</access>
15995              </field>
15996              <field>
15997                <name>IO6_SEL</name>
15998                <description>Selects connection for IO pin 6 route.</description>
15999                <bitRange>[20:16]</bitRange>
16000                <access>read-write</access>
16001              </field>
16002              <field>
16003                <name>IO7_SEL</name>
16004                <description>Selects connection for IO pin 7 route.</description>
16005                <bitRange>[28:24]</bitRange>
16006                <access>read-write</access>
16007              </field>
16008            </fields>
16009          </register>
16010        </cluster>
16011        <register>
16012          <name>MONITOR_CTL_0</name>
16013          <description>Power/Ground Monitor cell control 0</description>
16014          <addressOffset>0x2200</addressOffset>
16015          <size>32</size>
16016          <access>read-write</access>
16017          <resetValue>0x0</resetValue>
16018          <resetMask>0xFFFFFFFF</resetMask>
16019          <fields>
16020            <field>
16021              <name>MONITOR_EN</name>
16022              <description>control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:
16023'0': switch open.
16024'1': switch closed.</description>
16025              <bitRange>[31:0]</bitRange>
16026              <access>read-write</access>
16027            </field>
16028          </fields>
16029        </register>
16030        <register>
16031          <name>MONITOR_CTL_1</name>
16032          <description>Power/Ground Monitor cell control 1</description>
16033          <addressOffset>0x2204</addressOffset>
16034          <size>32</size>
16035          <access>read-write</access>
16036          <resetValue>0x0</resetValue>
16037          <resetMask>0xFFFFFFFF</resetMask>
16038          <fields>
16039            <field>
16040              <name>MONITOR_EN</name>
16041              <description>control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:
16042'0': switch open.
16043'1': switch closed.</description>
16044              <bitRange>[31:0]</bitRange>
16045              <access>read-write</access>
16046            </field>
16047          </fields>
16048        </register>
16049        <register>
16050          <name>MONITOR_CTL_2</name>
16051          <description>Power/Ground Monitor cell control 2</description>
16052          <addressOffset>0x2208</addressOffset>
16053          <size>32</size>
16054          <access>read-write</access>
16055          <resetValue>0x0</resetValue>
16056          <resetMask>0xFFFFFFFF</resetMask>
16057          <fields>
16058            <field>
16059              <name>MONITOR_EN</name>
16060              <description>control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:
16061'0': switch open.
16062'1': switch closed.</description>
16063              <bitRange>[31:0]</bitRange>
16064              <access>read-write</access>
16065            </field>
16066          </fields>
16067        </register>
16068        <register>
16069          <name>MONITOR_CTL_3</name>
16070          <description>Power/Ground Monitor cell control 3</description>
16071          <addressOffset>0x220C</addressOffset>
16072          <size>32</size>
16073          <access>read-write</access>
16074          <resetValue>0x0</resetValue>
16075          <resetMask>0xFFFFFFFF</resetMask>
16076          <fields>
16077            <field>
16078              <name>MONITOR_EN</name>
16079              <description>control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:
16080'0': switch open.
16081'1': switch closed.</description>
16082              <bitRange>[31:0]</bitRange>
16083              <access>read-write</access>
16084            </field>
16085          </fields>
16086        </register>
16087      </registers>
16088    </peripheral>
16089    <peripheral>
16090      <name>GPIO</name>
16091      <description>IO port control/configuration</description>
16092      <baseAddress>0x40410000</baseAddress>
16093      <addressBlock>
16094        <offset>0</offset>
16095        <size>65536</size>
16096        <usage>registers</usage>
16097      </addressBlock>
16098      <registers>
16099        <cluster>
16100          <dim>6</dim>
16101          <dimIncrement>128</dimIncrement>
16102          <name>PRT[%s]</name>
16103          <description>GPIO port registers</description>
16104          <addressOffset>0x00000000</addressOffset>
16105          <register>
16106            <name>OUT</name>
16107            <description>Port output data register</description>
16108            <addressOffset>0x0</addressOffset>
16109            <size>32</size>
16110            <access>read-write</access>
16111            <resetValue>0x0</resetValue>
16112            <resetMask>0xFF</resetMask>
16113            <fields>
16114              <field>
16115                <name>OUT0</name>
16116                <description>IO output data for pin 0
16117'0': Output state set to '0'
16118'1': Output state set to '1'</description>
16119                <bitRange>[0:0]</bitRange>
16120                <access>read-write</access>
16121              </field>
16122              <field>
16123                <name>OUT1</name>
16124                <description>IO output data for pin 1</description>
16125                <bitRange>[1:1]</bitRange>
16126                <access>read-write</access>
16127              </field>
16128              <field>
16129                <name>OUT2</name>
16130                <description>IO output data for pin 2</description>
16131                <bitRange>[2:2]</bitRange>
16132                <access>read-write</access>
16133              </field>
16134              <field>
16135                <name>OUT3</name>
16136                <description>IO output data for pin 3</description>
16137                <bitRange>[3:3]</bitRange>
16138                <access>read-write</access>
16139              </field>
16140              <field>
16141                <name>OUT4</name>
16142                <description>IO output data for pin 4</description>
16143                <bitRange>[4:4]</bitRange>
16144                <access>read-write</access>
16145              </field>
16146              <field>
16147                <name>OUT5</name>
16148                <description>IO output data for pin 5</description>
16149                <bitRange>[5:5]</bitRange>
16150                <access>read-write</access>
16151              </field>
16152              <field>
16153                <name>OUT6</name>
16154                <description>IO output data for pin 6</description>
16155                <bitRange>[6:6]</bitRange>
16156                <access>read-write</access>
16157              </field>
16158              <field>
16159                <name>OUT7</name>
16160                <description>IO output data for pin 7</description>
16161                <bitRange>[7:7]</bitRange>
16162                <access>read-write</access>
16163              </field>
16164            </fields>
16165          </register>
16166          <register>
16167            <name>OUT_CLR</name>
16168            <description>Port output data clear register</description>
16169            <addressOffset>0x4</addressOffset>
16170            <size>32</size>
16171            <access>read-write</access>
16172            <resetValue>0x0</resetValue>
16173            <resetMask>0xFF</resetMask>
16174            <fields>
16175              <field>
16176                <name>OUT0</name>
16177                <description>IO clear output for pin 0:
16178'0': Output state not affected.
16179'1': Output state set to '0'.</description>
16180                <bitRange>[0:0]</bitRange>
16181                <access>read-write</access>
16182              </field>
16183              <field>
16184                <name>OUT1</name>
16185                <description>IO clear output for pin 1</description>
16186                <bitRange>[1:1]</bitRange>
16187                <access>read-write</access>
16188              </field>
16189              <field>
16190                <name>OUT2</name>
16191                <description>IO clear output for pin 2</description>
16192                <bitRange>[2:2]</bitRange>
16193                <access>read-write</access>
16194              </field>
16195              <field>
16196                <name>OUT3</name>
16197                <description>IO clear output for pin 3</description>
16198                <bitRange>[3:3]</bitRange>
16199                <access>read-write</access>
16200              </field>
16201              <field>
16202                <name>OUT4</name>
16203                <description>IO clear output for pin 4</description>
16204                <bitRange>[4:4]</bitRange>
16205                <access>read-write</access>
16206              </field>
16207              <field>
16208                <name>OUT5</name>
16209                <description>IO clear output for pin 5</description>
16210                <bitRange>[5:5]</bitRange>
16211                <access>read-write</access>
16212              </field>
16213              <field>
16214                <name>OUT6</name>
16215                <description>IO clear output for pin 6</description>
16216                <bitRange>[6:6]</bitRange>
16217                <access>read-write</access>
16218              </field>
16219              <field>
16220                <name>OUT7</name>
16221                <description>IO clear output for pin 7</description>
16222                <bitRange>[7:7]</bitRange>
16223                <access>read-write</access>
16224              </field>
16225            </fields>
16226          </register>
16227          <register>
16228            <name>OUT_SET</name>
16229            <description>Port output data set register</description>
16230            <addressOffset>0x8</addressOffset>
16231            <size>32</size>
16232            <access>read-write</access>
16233            <resetValue>0x0</resetValue>
16234            <resetMask>0xFF</resetMask>
16235            <fields>
16236              <field>
16237                <name>OUT0</name>
16238                <description>IO set output for pin 0:
16239'0': Output state not affected.
16240'1': Output state set to '1'.</description>
16241                <bitRange>[0:0]</bitRange>
16242                <access>read-write</access>
16243              </field>
16244              <field>
16245                <name>OUT1</name>
16246                <description>IO set output for pin 1</description>
16247                <bitRange>[1:1]</bitRange>
16248                <access>read-write</access>
16249              </field>
16250              <field>
16251                <name>OUT2</name>
16252                <description>IO set output for pin 2</description>
16253                <bitRange>[2:2]</bitRange>
16254                <access>read-write</access>
16255              </field>
16256              <field>
16257                <name>OUT3</name>
16258                <description>IO set output for pin 3</description>
16259                <bitRange>[3:3]</bitRange>
16260                <access>read-write</access>
16261              </field>
16262              <field>
16263                <name>OUT4</name>
16264                <description>IO set output for pin 4</description>
16265                <bitRange>[4:4]</bitRange>
16266                <access>read-write</access>
16267              </field>
16268              <field>
16269                <name>OUT5</name>
16270                <description>IO set output for pin 5</description>
16271                <bitRange>[5:5]</bitRange>
16272                <access>read-write</access>
16273              </field>
16274              <field>
16275                <name>OUT6</name>
16276                <description>IO set output for pin 6</description>
16277                <bitRange>[6:6]</bitRange>
16278                <access>read-write</access>
16279              </field>
16280              <field>
16281                <name>OUT7</name>
16282                <description>IO set output for pin 7</description>
16283                <bitRange>[7:7]</bitRange>
16284                <access>read-write</access>
16285              </field>
16286            </fields>
16287          </register>
16288          <register>
16289            <name>OUT_INV</name>
16290            <description>Port output data invert register</description>
16291            <addressOffset>0xC</addressOffset>
16292            <size>32</size>
16293            <access>read-write</access>
16294            <resetValue>0x0</resetValue>
16295            <resetMask>0xFF</resetMask>
16296            <fields>
16297              <field>
16298                <name>OUT0</name>
16299                <description>IO invert output for pin 0:
16300'0': Output state not affected.
16301'1': Output state inverted ('0' =&gt; '1', '1' =&gt; '0').</description>
16302                <bitRange>[0:0]</bitRange>
16303                <access>read-write</access>
16304              </field>
16305              <field>
16306                <name>OUT1</name>
16307                <description>IO invert output for pin 1</description>
16308                <bitRange>[1:1]</bitRange>
16309                <access>read-write</access>
16310              </field>
16311              <field>
16312                <name>OUT2</name>
16313                <description>IO invert output for pin 2</description>
16314                <bitRange>[2:2]</bitRange>
16315                <access>read-write</access>
16316              </field>
16317              <field>
16318                <name>OUT3</name>
16319                <description>IO invert output for pin 3</description>
16320                <bitRange>[3:3]</bitRange>
16321                <access>read-write</access>
16322              </field>
16323              <field>
16324                <name>OUT4</name>
16325                <description>IO invert output for pin 4</description>
16326                <bitRange>[4:4]</bitRange>
16327                <access>read-write</access>
16328              </field>
16329              <field>
16330                <name>OUT5</name>
16331                <description>IO invert output for pin 5</description>
16332                <bitRange>[5:5]</bitRange>
16333                <access>read-write</access>
16334              </field>
16335              <field>
16336                <name>OUT6</name>
16337                <description>IO invert output for pin 6</description>
16338                <bitRange>[6:6]</bitRange>
16339                <access>read-write</access>
16340              </field>
16341              <field>
16342                <name>OUT7</name>
16343                <description>IO invert output for pin 7</description>
16344                <bitRange>[7:7]</bitRange>
16345                <access>read-write</access>
16346              </field>
16347            </fields>
16348          </register>
16349          <register>
16350            <name>IN</name>
16351            <description>Port input state register</description>
16352            <addressOffset>0x10</addressOffset>
16353            <size>32</size>
16354            <access>read-only</access>
16355            <resetValue>0x0</resetValue>
16356            <resetMask>0x1FF</resetMask>
16357            <fields>
16358              <field>
16359                <name>IN0</name>
16360                <description>IO pin state for pin 0
16361'0': Low logic level present on pin.
16362'1': High logic level present on pin.
16363On reset assertion , IN register will get reset. The Pad value takes 2 clock cycles to be reflected into IN Register.  The default value is transient.</description>
16364                <bitRange>[0:0]</bitRange>
16365                <access>read-only</access>
16366              </field>
16367              <field>
16368                <name>IN1</name>
16369                <description>IO pin state for pin 1</description>
16370                <bitRange>[1:1]</bitRange>
16371                <access>read-only</access>
16372              </field>
16373              <field>
16374                <name>IN2</name>
16375                <description>IO pin state for pin 2</description>
16376                <bitRange>[2:2]</bitRange>
16377                <access>read-only</access>
16378              </field>
16379              <field>
16380                <name>IN3</name>
16381                <description>IO pin state for pin 3</description>
16382                <bitRange>[3:3]</bitRange>
16383                <access>read-only</access>
16384              </field>
16385              <field>
16386                <name>IN4</name>
16387                <description>IO pin state for pin 4</description>
16388                <bitRange>[4:4]</bitRange>
16389                <access>read-only</access>
16390              </field>
16391              <field>
16392                <name>IN5</name>
16393                <description>IO pin state for pin 5</description>
16394                <bitRange>[5:5]</bitRange>
16395                <access>read-only</access>
16396              </field>
16397              <field>
16398                <name>IN6</name>
16399                <description>IO pin state for pin 6</description>
16400                <bitRange>[6:6]</bitRange>
16401                <access>read-only</access>
16402              </field>
16403              <field>
16404                <name>IN7</name>
16405                <description>IO pin state for pin 7</description>
16406                <bitRange>[7:7]</bitRange>
16407                <access>read-only</access>
16408              </field>
16409              <field>
16410                <name>FLT_IN</name>
16411                <description>Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register.</description>
16412                <bitRange>[8:8]</bitRange>
16413                <access>read-only</access>
16414              </field>
16415            </fields>
16416          </register>
16417          <register>
16418            <name>INTR</name>
16419            <description>Port interrupt status register</description>
16420            <addressOffset>0x14</addressOffset>
16421            <size>32</size>
16422            <access>read-write</access>
16423            <resetValue>0x0</resetValue>
16424            <resetMask>0x1FF01FF</resetMask>
16425            <fields>
16426              <field>
16427                <name>EDGE0</name>
16428                <description>Edge detect for IO pin 0
16429'0': No edge was detected on pin.
16430'1': An edge was detected on pin.</description>
16431                <bitRange>[0:0]</bitRange>
16432                <access>read-write</access>
16433              </field>
16434              <field>
16435                <name>EDGE1</name>
16436                <description>Edge detect for IO pin 1</description>
16437                <bitRange>[1:1]</bitRange>
16438                <access>read-write</access>
16439              </field>
16440              <field>
16441                <name>EDGE2</name>
16442                <description>Edge detect for IO pin 2</description>
16443                <bitRange>[2:2]</bitRange>
16444                <access>read-write</access>
16445              </field>
16446              <field>
16447                <name>EDGE3</name>
16448                <description>Edge detect for IO pin 3</description>
16449                <bitRange>[3:3]</bitRange>
16450                <access>read-write</access>
16451              </field>
16452              <field>
16453                <name>EDGE4</name>
16454                <description>Edge detect for IO pin 4</description>
16455                <bitRange>[4:4]</bitRange>
16456                <access>read-write</access>
16457              </field>
16458              <field>
16459                <name>EDGE5</name>
16460                <description>Edge detect for IO pin 5</description>
16461                <bitRange>[5:5]</bitRange>
16462                <access>read-write</access>
16463              </field>
16464              <field>
16465                <name>EDGE6</name>
16466                <description>Edge detect for IO pin 6</description>
16467                <bitRange>[6:6]</bitRange>
16468                <access>read-write</access>
16469              </field>
16470              <field>
16471                <name>EDGE7</name>
16472                <description>Edge detect for IO pin 7</description>
16473                <bitRange>[7:7]</bitRange>
16474                <access>read-write</access>
16475              </field>
16476              <field>
16477                <name>FLT_EDGE</name>
16478                <description>Edge detected on filtered pin selected by INTR_CFG.FLT_SEL</description>
16479                <bitRange>[8:8]</bitRange>
16480                <access>read-write</access>
16481              </field>
16482              <field>
16483                <name>IN_IN0</name>
16484                <description>IO pin state for pin 0</description>
16485                <bitRange>[16:16]</bitRange>
16486                <access>read-only</access>
16487              </field>
16488              <field>
16489                <name>IN_IN1</name>
16490                <description>IO pin state for pin 1</description>
16491                <bitRange>[17:17]</bitRange>
16492                <access>read-only</access>
16493              </field>
16494              <field>
16495                <name>IN_IN2</name>
16496                <description>IO pin state for pin 2</description>
16497                <bitRange>[18:18]</bitRange>
16498                <access>read-only</access>
16499              </field>
16500              <field>
16501                <name>IN_IN3</name>
16502                <description>IO pin state for pin 3</description>
16503                <bitRange>[19:19]</bitRange>
16504                <access>read-only</access>
16505              </field>
16506              <field>
16507                <name>IN_IN4</name>
16508                <description>IO pin state for pin 4</description>
16509                <bitRange>[20:20]</bitRange>
16510                <access>read-only</access>
16511              </field>
16512              <field>
16513                <name>IN_IN5</name>
16514                <description>IO pin state for pin 5</description>
16515                <bitRange>[21:21]</bitRange>
16516                <access>read-only</access>
16517              </field>
16518              <field>
16519                <name>IN_IN6</name>
16520                <description>IO pin state for pin 6</description>
16521                <bitRange>[22:22]</bitRange>
16522                <access>read-only</access>
16523              </field>
16524              <field>
16525                <name>IN_IN7</name>
16526                <description>IO pin state for pin 7</description>
16527                <bitRange>[23:23]</bitRange>
16528                <access>read-only</access>
16529              </field>
16530              <field>
16531                <name>FLT_IN_IN</name>
16532                <description>Filtered pin state for pin selected by INTR_CFG.FLT_SEL</description>
16533                <bitRange>[24:24]</bitRange>
16534                <access>read-only</access>
16535              </field>
16536            </fields>
16537          </register>
16538          <register>
16539            <name>INTR_MASK</name>
16540            <description>Port interrupt mask register</description>
16541            <addressOffset>0x18</addressOffset>
16542            <size>32</size>
16543            <access>read-write</access>
16544            <resetValue>0x0</resetValue>
16545            <resetMask>0x1FF</resetMask>
16546            <fields>
16547              <field>
16548                <name>EDGE0</name>
16549                <description>Masks edge interrupt on IO pin 0
16550'0': Pin interrupt forwarding disabled
16551'1': Pin interrupt forwarding enabled</description>
16552                <bitRange>[0:0]</bitRange>
16553                <access>read-write</access>
16554              </field>
16555              <field>
16556                <name>EDGE1</name>
16557                <description>Masks edge interrupt on IO pin 1</description>
16558                <bitRange>[1:1]</bitRange>
16559                <access>read-write</access>
16560              </field>
16561              <field>
16562                <name>EDGE2</name>
16563                <description>Masks edge interrupt on IO pin 2</description>
16564                <bitRange>[2:2]</bitRange>
16565                <access>read-write</access>
16566              </field>
16567              <field>
16568                <name>EDGE3</name>
16569                <description>Masks edge interrupt on IO pin 3</description>
16570                <bitRange>[3:3]</bitRange>
16571                <access>read-write</access>
16572              </field>
16573              <field>
16574                <name>EDGE4</name>
16575                <description>Masks edge interrupt on IO pin 4</description>
16576                <bitRange>[4:4]</bitRange>
16577                <access>read-write</access>
16578              </field>
16579              <field>
16580                <name>EDGE5</name>
16581                <description>Masks edge interrupt on IO pin 5</description>
16582                <bitRange>[5:5]</bitRange>
16583                <access>read-write</access>
16584              </field>
16585              <field>
16586                <name>EDGE6</name>
16587                <description>Masks edge interrupt on IO pin 6</description>
16588                <bitRange>[6:6]</bitRange>
16589                <access>read-write</access>
16590              </field>
16591              <field>
16592                <name>EDGE7</name>
16593                <description>Masks edge interrupt on IO pin 7</description>
16594                <bitRange>[7:7]</bitRange>
16595                <access>read-write</access>
16596              </field>
16597              <field>
16598                <name>FLT_EDGE</name>
16599                <description>Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL</description>
16600                <bitRange>[8:8]</bitRange>
16601                <access>read-write</access>
16602              </field>
16603            </fields>
16604          </register>
16605          <register>
16606            <name>INTR_MASKED</name>
16607            <description>Port interrupt masked status register</description>
16608            <addressOffset>0x1C</addressOffset>
16609            <size>32</size>
16610            <access>read-only</access>
16611            <resetValue>0x0</resetValue>
16612            <resetMask>0x1FF</resetMask>
16613            <fields>
16614              <field>
16615                <name>EDGE0</name>
16616                <description>Edge detected AND masked on IO pin 0
16617'0': Interrupt was not forwarded to CPU
16618'1': Interrupt occurred and was forwarded to CPU</description>
16619                <bitRange>[0:0]</bitRange>
16620                <access>read-only</access>
16621              </field>
16622              <field>
16623                <name>EDGE1</name>
16624                <description>Edge detected and masked on IO pin 1</description>
16625                <bitRange>[1:1]</bitRange>
16626                <access>read-only</access>
16627              </field>
16628              <field>
16629                <name>EDGE2</name>
16630                <description>Edge detected and masked on IO pin 2</description>
16631                <bitRange>[2:2]</bitRange>
16632                <access>read-only</access>
16633              </field>
16634              <field>
16635                <name>EDGE3</name>
16636                <description>Edge detected and masked on IO pin 3</description>
16637                <bitRange>[3:3]</bitRange>
16638                <access>read-only</access>
16639              </field>
16640              <field>
16641                <name>EDGE4</name>
16642                <description>Edge detected and masked on IO pin 4</description>
16643                <bitRange>[4:4]</bitRange>
16644                <access>read-only</access>
16645              </field>
16646              <field>
16647                <name>EDGE5</name>
16648                <description>Edge detected and masked on IO pin 5</description>
16649                <bitRange>[5:5]</bitRange>
16650                <access>read-only</access>
16651              </field>
16652              <field>
16653                <name>EDGE6</name>
16654                <description>Edge detected and masked on IO pin 6</description>
16655                <bitRange>[6:6]</bitRange>
16656                <access>read-only</access>
16657              </field>
16658              <field>
16659                <name>EDGE7</name>
16660                <description>Edge detected and masked on IO pin 7</description>
16661                <bitRange>[7:7]</bitRange>
16662                <access>read-only</access>
16663              </field>
16664              <field>
16665                <name>FLT_EDGE</name>
16666                <description>Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL</description>
16667                <bitRange>[8:8]</bitRange>
16668                <access>read-only</access>
16669              </field>
16670            </fields>
16671          </register>
16672          <register>
16673            <name>INTR_SET</name>
16674            <description>Port interrupt set register</description>
16675            <addressOffset>0x20</addressOffset>
16676            <size>32</size>
16677            <access>read-write</access>
16678            <resetValue>0x0</resetValue>
16679            <resetMask>0x1FF</resetMask>
16680            <fields>
16681              <field>
16682                <name>EDGE0</name>
16683                <description>Sets edge detect interrupt for IO pin 0
16684'0': Interrupt state not affected
16685'1': Interrupt set</description>
16686                <bitRange>[0:0]</bitRange>
16687                <access>read-write</access>
16688              </field>
16689              <field>
16690                <name>EDGE1</name>
16691                <description>Sets edge detect interrupt for IO pin 1</description>
16692                <bitRange>[1:1]</bitRange>
16693                <access>read-write</access>
16694              </field>
16695              <field>
16696                <name>EDGE2</name>
16697                <description>Sets edge detect interrupt for IO pin 2</description>
16698                <bitRange>[2:2]</bitRange>
16699                <access>read-write</access>
16700              </field>
16701              <field>
16702                <name>EDGE3</name>
16703                <description>Sets edge detect interrupt for IO pin 3</description>
16704                <bitRange>[3:3]</bitRange>
16705                <access>read-write</access>
16706              </field>
16707              <field>
16708                <name>EDGE4</name>
16709                <description>Sets edge detect interrupt for IO pin 4</description>
16710                <bitRange>[4:4]</bitRange>
16711                <access>read-write</access>
16712              </field>
16713              <field>
16714                <name>EDGE5</name>
16715                <description>Sets edge detect interrupt for IO pin 5</description>
16716                <bitRange>[5:5]</bitRange>
16717                <access>read-write</access>
16718              </field>
16719              <field>
16720                <name>EDGE6</name>
16721                <description>Sets edge detect interrupt for IO pin 6</description>
16722                <bitRange>[6:6]</bitRange>
16723                <access>read-write</access>
16724              </field>
16725              <field>
16726                <name>EDGE7</name>
16727                <description>Sets edge detect interrupt for IO pin 7</description>
16728                <bitRange>[7:7]</bitRange>
16729                <access>read-write</access>
16730              </field>
16731              <field>
16732                <name>FLT_EDGE</name>
16733                <description>Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL</description>
16734                <bitRange>[8:8]</bitRange>
16735                <access>read-write</access>
16736              </field>
16737            </fields>
16738          </register>
16739          <register>
16740            <name>INTR_CFG</name>
16741            <description>Port interrupt configuration register</description>
16742            <addressOffset>0x40</addressOffset>
16743            <size>32</size>
16744            <access>read-write</access>
16745            <resetValue>0x0</resetValue>
16746            <resetMask>0x1FFFFF</resetMask>
16747            <fields>
16748              <field>
16749                <name>EDGE0_SEL</name>
16750                <description>Sets which edge will trigger an IRQ for IO pin 0</description>
16751                <bitRange>[1:0]</bitRange>
16752                <access>read-write</access>
16753                <enumeratedValues>
16754                  <enumeratedValue>
16755                    <name>DISABLE</name>
16756                    <description>Disabled</description>
16757                    <value>0</value>
16758                  </enumeratedValue>
16759                  <enumeratedValue>
16760                    <name>RISING</name>
16761                    <description>Rising edge</description>
16762                    <value>1</value>
16763                  </enumeratedValue>
16764                  <enumeratedValue>
16765                    <name>FALLING</name>
16766                    <description>Falling edge</description>
16767                    <value>2</value>
16768                  </enumeratedValue>
16769                  <enumeratedValue>
16770                    <name>BOTH</name>
16771                    <description>Both rising and falling edges</description>
16772                    <value>3</value>
16773                  </enumeratedValue>
16774                </enumeratedValues>
16775              </field>
16776              <field>
16777                <name>EDGE1_SEL</name>
16778                <description>Sets which edge will trigger an IRQ for IO pin 1</description>
16779                <bitRange>[3:2]</bitRange>
16780                <access>read-write</access>
16781              </field>
16782              <field>
16783                <name>EDGE2_SEL</name>
16784                <description>Sets which edge will trigger an IRQ for IO pin 2</description>
16785                <bitRange>[5:4]</bitRange>
16786                <access>read-write</access>
16787              </field>
16788              <field>
16789                <name>EDGE3_SEL</name>
16790                <description>Sets which edge will trigger an IRQ for IO pin 3</description>
16791                <bitRange>[7:6]</bitRange>
16792                <access>read-write</access>
16793              </field>
16794              <field>
16795                <name>EDGE4_SEL</name>
16796                <description>Sets which edge will trigger an IRQ for IO pin 4</description>
16797                <bitRange>[9:8]</bitRange>
16798                <access>read-write</access>
16799              </field>
16800              <field>
16801                <name>EDGE5_SEL</name>
16802                <description>Sets which edge will trigger an IRQ for IO pin 5</description>
16803                <bitRange>[11:10]</bitRange>
16804                <access>read-write</access>
16805              </field>
16806              <field>
16807                <name>EDGE6_SEL</name>
16808                <description>Sets which edge will trigger an IRQ for IO pin 6</description>
16809                <bitRange>[13:12]</bitRange>
16810                <access>read-write</access>
16811              </field>
16812              <field>
16813                <name>EDGE7_SEL</name>
16814                <description>Sets which edge will trigger an IRQ for IO pin 7</description>
16815                <bitRange>[15:14]</bitRange>
16816                <access>read-write</access>
16817              </field>
16818              <field>
16819                <name>FLT_EDGE_SEL</name>
16820                <description>Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL</description>
16821                <bitRange>[17:16]</bitRange>
16822                <access>read-write</access>
16823                <enumeratedValues>
16824                  <enumeratedValue>
16825                    <name>DISABLE</name>
16826                    <description>Disabled</description>
16827                    <value>0</value>
16828                  </enumeratedValue>
16829                  <enumeratedValue>
16830                    <name>RISING</name>
16831                    <description>Rising edge</description>
16832                    <value>1</value>
16833                  </enumeratedValue>
16834                  <enumeratedValue>
16835                    <name>FALLING</name>
16836                    <description>Falling edge</description>
16837                    <value>2</value>
16838                  </enumeratedValue>
16839                  <enumeratedValue>
16840                    <name>BOTH</name>
16841                    <description>Both rising and falling edges</description>
16842                    <value>3</value>
16843                  </enumeratedValue>
16844                </enumeratedValues>
16845              </field>
16846              <field>
16847                <name>FLT_SEL</name>
16848                <description>Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt.</description>
16849                <bitRange>[20:18]</bitRange>
16850                <access>read-write</access>
16851              </field>
16852            </fields>
16853          </register>
16854          <register>
16855            <name>CFG</name>
16856            <description>Port configuration register</description>
16857            <addressOffset>0x44</addressOffset>
16858            <size>32</size>
16859            <access>read-write</access>
16860            <resetValue>0x0</resetValue>
16861            <resetMask>0xFFFFFFFF</resetMask>
16862            <fields>
16863              <field>
16864                <name>DRIVE_MODE0</name>
16865                <description>The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode.
16866Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured  before turning the IO on here to avoid producing glitches on the bus.
16867Note: that peripherals other than GPIO &amp; UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0').
16868Note: D_OUT, D_OUT_EN are pins of GPIO cell.</description>
16869                <bitRange>[2:0]</bitRange>
16870                <access>read-write</access>
16871                <enumeratedValues>
16872                  <enumeratedValue>
16873                    <name>HIGHZ</name>
16874                    <description>Output buffer is off creating a high impedance input
16875D_OUT = '0': High Impedance
16876D_OUT = '1': High Impedance</description>
16877                    <value>0</value>
16878                  </enumeratedValue>
16879                  <enumeratedValue>
16880                    <name>RSVD</name>
16881                    <description>N/A</description>
16882                    <value>1</value>
16883                  </enumeratedValue>
16884                  <enumeratedValue>
16885                    <name>PULLUP</name>
16886                    <description>Resistive pull up
16887
16888For GPIO &amp; UDB/DSI peripherals:
16889When D_OUT_EN = 1:
16890   D_OUT = '0': Strong pull down
16891   D_OUT = '1': Weak/resistive pull up
16892When D_OUT_EN = 0:
16893   D_OUT = '0': High impedance
16894   D_OUT = '1': High impedance
16895
16896For peripherals other than GPIO &amp; UDB/DSI:
16897When D_OUT_EN = 1:
16898   D_OUT = '0': Strong pull down
16899   D_OUT = '1': Strong pull up
16900When D_OUT_EN = 0:
16901   D_OUT = '0': Weak/resistive pull up
16902   D_OUT = '1': Weak/resistive pull up</description>
16903                    <value>2</value>
16904                  </enumeratedValue>
16905                  <enumeratedValue>
16906                    <name>PULLDOWN</name>
16907                    <description>Resistive pull down
16908
16909For GPIO &amp; UDB/DSI peripherals:
16910When D_OUT_EN = 1:
16911   D_OUT = '0': Weak/resistive pull down
16912   D_OUT = '1': Strong pull up
16913When D_OUT_EN = 0:
16914   D_OUT = '0': High impedance
16915   D_OUT = '1': High impedance
16916
16917For peripherals other than GPIO &amp; UDB/DSI:
16918When D_OUT_EN = 1:
16919   D_OUT = '0': Strong pull down
16920   D_OUT = '1': Strong pull up
16921When D_OUT_EN = 0:
16922   D_OUT = '0': Weak/resistive pull down
16923   D_OUT = '1': Weak/resistive pull down</description>
16924                    <value>3</value>
16925                  </enumeratedValue>
16926                  <enumeratedValue>
16927                    <name>OD_DRIVESLOW</name>
16928                    <description>Open drain, drives low
16929
16930For GPIO &amp; UDB/DSI peripherals:
16931When D_OUT_EN = 1:
16932   D_OUT = '0': Strong pull down
16933   D_OUT = '1': High Impedance
16934When D_OUT_EN = 0:
16935   D_OUT = '0': High impedance
16936   D_OUT = '1': High impedance
16937
16938For peripherals other than GPIO &amp; UDB/DSI:
16939When D_OUT_EN = 1:
16940   D_OUT = '0': Strong pull down
16941   D_OUT = '1': Strong pull up
16942When D_OUT_EN = 0:
16943   D_OUT = '0': High Impedance
16944   D_OUT = '1': High Impedance</description>
16945                    <value>4</value>
16946                  </enumeratedValue>
16947                  <enumeratedValue>
16948                    <name>OD_DRIVESHIGH</name>
16949                    <description>Open drain, drives high
16950
16951For GPIO &amp; UDB/DSI peripherals:
16952When D_OUT_EN = 1:
16953   D_OUT = '0': High Impedance
16954   D_OUT = '1': Strong pull up
16955When D_OUT_EN = 0:
16956   D_OUT = '0': High impedance
16957   D_OUT = '1': High impedance
16958
16959For peripherals other than GPIO &amp; UDB/DSI:
16960When D_OUT_EN = 1:
16961   D_OUT = '0': Strong pull down
16962   D_OUT = '1': Strong pull up
16963When D_OUT_EN = 0:
16964   D_OUT = '0': High Impedance
16965   D_OUT = '1': High Impedance</description>
16966                    <value>5</value>
16967                  </enumeratedValue>
16968                  <enumeratedValue>
16969                    <name>STRONG</name>
16970                    <description>Strong D_OUTput buffer
16971
16972For GPIO &amp; UDB/DSI peripherals:
16973When D_OUT_EN = 1:
16974   D_OUT = '0': Strong pull down
16975   D_OUT = '1': Strong pull up
16976When D_OUT_EN = 0:
16977   D_OUT = '0': High impedance
16978   D_OUT = '1': High impedance
16979
16980For peripherals other than GPIO &amp; UDB/DSI:
16981When D_OUT_EN = 1:
16982   D_OUT = '0': Strong pull down
16983   D_OUT = '1': Strong pull up
16984When D_OUT_EN = 0:
16985   D_OUT = '0': High Impedance
16986   D_OUT = '1': High Impedance</description>
16987                    <value>6</value>
16988                  </enumeratedValue>
16989                  <enumeratedValue>
16990                    <name>PULLUP_DOWN</name>
16991                    <description>Pull up or pull down
16992
16993For GPIO &amp; UDB/DSI peripherals:
16994When D_OUT_EN = '0':
16995    GPIO_DSI_OUT = '0': Weak/resistive pull down
16996    GPIO_DSI_OUT = '1': Weak/resistive pull up
16997where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT &amp; DSI_DATA_OUT.
16998
16999For peripherals other than GPIO &amp; UDB/DSI:
17000When D_OUT_EN = 1:
17001   D_OUT = '0': Strong pull down
17002   D_OUT = '1': Strong pull up
17003When D_OUT_EN = 0:
17004    D_OUT = '0': Weak/resistive pull down
17005    D_OUT = '1': Weak/resistive pull up</description>
17006                    <value>7</value>
17007                  </enumeratedValue>
17008                </enumeratedValues>
17009              </field>
17010              <field>
17011                <name>IN_EN0</name>
17012                <description>Enables the input buffer for IO pin 0.  This bit should be cleared when analog signals are present on the pin to avoid crowbar currents.  The output buffer can be used to drive analog signals high or low without issue.
17013'0': Input buffer disabled
17014'1': Input buffer enabled</description>
17015                <bitRange>[3:3]</bitRange>
17016                <access>read-write</access>
17017              </field>
17018              <field>
17019                <name>DRIVE_MODE1</name>
17020                <description>The GPIO drive mode for IO pin 1</description>
17021                <bitRange>[6:4]</bitRange>
17022                <access>read-write</access>
17023              </field>
17024              <field>
17025                <name>IN_EN1</name>
17026                <description>Enables the input buffer for IO pin 1</description>
17027                <bitRange>[7:7]</bitRange>
17028                <access>read-write</access>
17029              </field>
17030              <field>
17031                <name>DRIVE_MODE2</name>
17032                <description>The GPIO drive mode for IO pin 2</description>
17033                <bitRange>[10:8]</bitRange>
17034                <access>read-write</access>
17035              </field>
17036              <field>
17037                <name>IN_EN2</name>
17038                <description>Enables the input buffer for IO pin 2</description>
17039                <bitRange>[11:11]</bitRange>
17040                <access>read-write</access>
17041              </field>
17042              <field>
17043                <name>DRIVE_MODE3</name>
17044                <description>The GPIO drive mode for IO pin 3</description>
17045                <bitRange>[14:12]</bitRange>
17046                <access>read-write</access>
17047              </field>
17048              <field>
17049                <name>IN_EN3</name>
17050                <description>Enables the input buffer for IO pin 3</description>
17051                <bitRange>[15:15]</bitRange>
17052                <access>read-write</access>
17053              </field>
17054              <field>
17055                <name>DRIVE_MODE4</name>
17056                <description>The GPIO drive mode for IO pin4</description>
17057                <bitRange>[18:16]</bitRange>
17058                <access>read-write</access>
17059              </field>
17060              <field>
17061                <name>IN_EN4</name>
17062                <description>Enables the input buffer for IO pin 4</description>
17063                <bitRange>[19:19]</bitRange>
17064                <access>read-write</access>
17065              </field>
17066              <field>
17067                <name>DRIVE_MODE5</name>
17068                <description>The GPIO drive mode for IO pin 5</description>
17069                <bitRange>[22:20]</bitRange>
17070                <access>read-write</access>
17071              </field>
17072              <field>
17073                <name>IN_EN5</name>
17074                <description>Enables the input buffer for IO pin 5</description>
17075                <bitRange>[23:23]</bitRange>
17076                <access>read-write</access>
17077              </field>
17078              <field>
17079                <name>DRIVE_MODE6</name>
17080                <description>The GPIO drive mode for IO pin 6</description>
17081                <bitRange>[26:24]</bitRange>
17082                <access>read-write</access>
17083              </field>
17084              <field>
17085                <name>IN_EN6</name>
17086                <description>Enables the input buffer for IO pin 6</description>
17087                <bitRange>[27:27]</bitRange>
17088                <access>read-write</access>
17089              </field>
17090              <field>
17091                <name>DRIVE_MODE7</name>
17092                <description>The GPIO drive mode for IO pin 7</description>
17093                <bitRange>[30:28]</bitRange>
17094                <access>read-write</access>
17095              </field>
17096              <field>
17097                <name>IN_EN7</name>
17098                <description>Enables the input buffer for IO pin 7</description>
17099                <bitRange>[31:31]</bitRange>
17100                <access>read-write</access>
17101              </field>
17102            </fields>
17103          </register>
17104          <register>
17105            <name>CFG_IN</name>
17106            <description>Port input buffer configuration register</description>
17107            <addressOffset>0x48</addressOffset>
17108            <size>32</size>
17109            <access>read-write</access>
17110            <resetValue>0x0</resetValue>
17111            <resetMask>0xFF</resetMask>
17112            <fields>
17113              <field>
17114                <name>VTRIP_SEL0_0</name>
17115                <description>Configures the pin 0 input buffer mode (trip points and hysteresis)</description>
17116                <bitRange>[0:0]</bitRange>
17117                <access>read-write</access>
17118                <enumeratedValues>
17119                  <enumeratedValue>
17120                    <name>CMOS</name>
17121                    <description>Input buffer compatible with CMOS and I2C interfaces</description>
17122                    <value>0</value>
17123                  </enumeratedValue>
17124                  <enumeratedValue>
17125                    <name>TTL</name>
17126                    <description>Input buffer compatible with TTL and MediaLB interfaces</description>
17127                    <value>1</value>
17128                  </enumeratedValue>
17129                </enumeratedValues>
17130              </field>
17131              <field>
17132                <name>VTRIP_SEL1_0</name>
17133                <description>Configures the pin 1 input buffer mode (trip points and hysteresis)</description>
17134                <bitRange>[1:1]</bitRange>
17135                <access>read-write</access>
17136              </field>
17137              <field>
17138                <name>VTRIP_SEL2_0</name>
17139                <description>Configures the pin 2 input buffer mode (trip points and hysteresis)</description>
17140                <bitRange>[2:2]</bitRange>
17141                <access>read-write</access>
17142              </field>
17143              <field>
17144                <name>VTRIP_SEL3_0</name>
17145                <description>Configures the pin 3 input buffer mode (trip points and hysteresis)</description>
17146                <bitRange>[3:3]</bitRange>
17147                <access>read-write</access>
17148              </field>
17149              <field>
17150                <name>VTRIP_SEL4_0</name>
17151                <description>Configures the pin 4 input buffer mode (trip points and hysteresis)</description>
17152                <bitRange>[4:4]</bitRange>
17153                <access>read-write</access>
17154              </field>
17155              <field>
17156                <name>VTRIP_SEL5_0</name>
17157                <description>Configures the pin 5 input buffer mode (trip points and hysteresis)</description>
17158                <bitRange>[5:5]</bitRange>
17159                <access>read-write</access>
17160              </field>
17161              <field>
17162                <name>VTRIP_SEL6_0</name>
17163                <description>Configures the pin 6 input buffer mode (trip points and hysteresis)</description>
17164                <bitRange>[6:6]</bitRange>
17165                <access>read-write</access>
17166              </field>
17167              <field>
17168                <name>VTRIP_SEL7_0</name>
17169                <description>Configures the pin 7 input buffer mode (trip points and hysteresis)</description>
17170                <bitRange>[7:7]</bitRange>
17171                <access>read-write</access>
17172              </field>
17173            </fields>
17174          </register>
17175          <register>
17176            <name>CFG_OUT</name>
17177            <description>Port output buffer configuration register</description>
17178            <addressOffset>0x4C</addressOffset>
17179            <size>32</size>
17180            <access>read-write</access>
17181            <resetValue>0x0</resetValue>
17182            <resetMask>0xFFFF00FF</resetMask>
17183            <fields>
17184              <field>
17185                <name>SLOW0</name>
17186                <description>Enables slow slew rate for IO pin 0
17187'0': Fast slew rate
17188'1': Slow slew rate</description>
17189                <bitRange>[0:0]</bitRange>
17190                <access>read-write</access>
17191              </field>
17192              <field>
17193                <name>SLOW1</name>
17194                <description>Enables slow slew rate for IO pin 1</description>
17195                <bitRange>[1:1]</bitRange>
17196                <access>read-write</access>
17197              </field>
17198              <field>
17199                <name>SLOW2</name>
17200                <description>Enables slow slew rate for IO pin 2</description>
17201                <bitRange>[2:2]</bitRange>
17202                <access>read-write</access>
17203              </field>
17204              <field>
17205                <name>SLOW3</name>
17206                <description>Enables slow slew rate for IO pin 3</description>
17207                <bitRange>[3:3]</bitRange>
17208                <access>read-write</access>
17209              </field>
17210              <field>
17211                <name>SLOW4</name>
17212                <description>Enables slow slew rate for IO pin 4</description>
17213                <bitRange>[4:4]</bitRange>
17214                <access>read-write</access>
17215              </field>
17216              <field>
17217                <name>SLOW5</name>
17218                <description>Enables slow slew rate for IO pin 5</description>
17219                <bitRange>[5:5]</bitRange>
17220                <access>read-write</access>
17221              </field>
17222              <field>
17223                <name>SLOW6</name>
17224                <description>Enables slow slew rate for IO pin 6</description>
17225                <bitRange>[6:6]</bitRange>
17226                <access>read-write</access>
17227              </field>
17228              <field>
17229                <name>SLOW7</name>
17230                <description>Enables slow slew rate for IO pin 7</description>
17231                <bitRange>[7:7]</bitRange>
17232                <access>read-write</access>
17233              </field>
17234              <field>
17235                <name>DRIVE_SEL0</name>
17236                <description>Sets the GPIO drive strength for IO pin 0</description>
17237                <bitRange>[17:16]</bitRange>
17238                <access>read-write</access>
17239                <enumeratedValues>
17240                  <enumeratedValue>
17241                    <name>DRIVE_SEL_ZERO</name>
17242                    <description>N/A</description>
17243                    <value>0</value>
17244                  </enumeratedValue>
17245                  <enumeratedValue>
17246                    <name>DRIVE_SEL_ONE</name>
17247                    <description>N/A</description>
17248                    <value>1</value>
17249                  </enumeratedValue>
17250                  <enumeratedValue>
17251                    <name>DRIVE_SEL_TWO</name>
17252                    <description>N/A</description>
17253                    <value>2</value>
17254                  </enumeratedValue>
17255                  <enumeratedValue>
17256                    <name>DRIVE_SEL_THREE</name>
17257                    <description>N/A</description>
17258                    <value>3</value>
17259                  </enumeratedValue>
17260                </enumeratedValues>
17261              </field>
17262              <field>
17263                <name>DRIVE_SEL1</name>
17264                <description>Sets the GPIO drive strength for IO pin 1</description>
17265                <bitRange>[19:18]</bitRange>
17266                <access>read-write</access>
17267              </field>
17268              <field>
17269                <name>DRIVE_SEL2</name>
17270                <description>Sets the GPIO drive strength for IO pin 2</description>
17271                <bitRange>[21:20]</bitRange>
17272                <access>read-write</access>
17273              </field>
17274              <field>
17275                <name>DRIVE_SEL3</name>
17276                <description>Sets the GPIO drive strength for IO pin 3</description>
17277                <bitRange>[23:22]</bitRange>
17278                <access>read-write</access>
17279              </field>
17280              <field>
17281                <name>DRIVE_SEL4</name>
17282                <description>Sets the GPIO drive strength for IO pin 4</description>
17283                <bitRange>[25:24]</bitRange>
17284                <access>read-write</access>
17285              </field>
17286              <field>
17287                <name>DRIVE_SEL5</name>
17288                <description>Sets the GPIO drive strength for IO pin 5</description>
17289                <bitRange>[27:26]</bitRange>
17290                <access>read-write</access>
17291              </field>
17292              <field>
17293                <name>DRIVE_SEL6</name>
17294                <description>Sets the GPIO drive strength for IO pin 6</description>
17295                <bitRange>[29:28]</bitRange>
17296                <access>read-write</access>
17297              </field>
17298              <field>
17299                <name>DRIVE_SEL7</name>
17300                <description>Sets the GPIO drive strength for IO pin 7</description>
17301                <bitRange>[31:30]</bitRange>
17302                <access>read-write</access>
17303              </field>
17304            </fields>
17305          </register>
17306          <register>
17307            <name>CFG_SIO</name>
17308            <description>Port SIO configuration register</description>
17309            <addressOffset>0x50</addressOffset>
17310            <size>32</size>
17311            <access>read-write</access>
17312            <resetValue>0x0</resetValue>
17313            <resetMask>0xFFFFFFFF</resetMask>
17314            <fields>
17315              <field>
17316                <name>VREG_EN01</name>
17317                <description>Selects the output buffer mode:
17318'0': Unregulated output buffer
17319'1': Regulated output buffer
17320The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode. If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used.</description>
17321                <bitRange>[0:0]</bitRange>
17322                <access>read-write</access>
17323              </field>
17324              <field>
17325                <name>IBUF_SEL01</name>
17326                <description>Selects the input buffer mode:
173270: Singled ended input buffer
173281: Differential input buffer</description>
17329                <bitRange>[1:1]</bitRange>
17330                <access>read-write</access>
17331              </field>
17332              <field>
17333                <name>VTRIP_SEL01</name>
17334                <description>Selects the input buffer trip-point in single ended input buffer mode (IBUF_SEL = '0'):
17335'0': Input buffer functions as a CMOS input buffer.
17336'1': Input buffer functions as a TTL input buffer.
17337In differential input buffer mode (IBUF_SEL = '1')
17338'0': Trip-point is 0.5*Vddio or 0.5*Voh (depends on VREF_SEL/VOH_SEL)
17339'1': Trip-point is 0.4*Vddio or 1.0*Vref  (depends on VREF_SEL)</description>
17340                <bitRange>[2:2]</bitRange>
17341                <access>read-write</access>
17342              </field>
17343              <field>
17344                <name>VREF_SEL01</name>
17345                <description>Selects reference voltage (Vref) trip-point of the input buffer:
17346'0': Trip-point reference from pin_ref
17347'1': Trip-point reference of SRSS internal reference Vref (1.2 V)
17348'2': Trip-point reference of AMUXBUS_A
17349'3': Trip-point reference of AMUXBUS_B</description>
17350                <bitRange>[4:3]</bitRange>
17351                <access>read-write</access>
17352              </field>
17353              <field>
17354                <name>VOH_SEL01</name>
17355                <description>Selects the regulated Voh output level and trip point of the input buffer for a specific SIO pin pair. Voh depends on the selected reference voltage (VREF_SEL).
17356'0': Voh = 1*reference; e.g. reference at 1.2V -&gt; Voh = 1.2V
17357'1': Voh = 1.25*reference; e.g. reference at 1.2V -&gt; Voh = 1.5V
17358'2': Voh = 1.49*reference; e.g. reference at 1.2V -&gt; Voh = ~1.8V
17359'3': Voh = 1.67*reference; e.g. reference at 1.2V -&gt; Voh = 2V
17360'4': Voh = 2.08*reference; e.g. reference at 1.2V -&gt; Voh = 2.5V
17361'5': Voh = 2.5*reference; e.g. reference at 1.2V -&gt; Voh = 3V
17362'6': Voh = 2.78*reference; e.g. reference at 1.2V -&gt; Voh = ~3.3V
17363'7': Voh = 4.16*reference; e.g. reference at 1.2V -&gt; Voh = 5.0V
17364Note: The upper value on Voh is limited to Vddio - 400mV</description>
17365                <bitRange>[7:5]</bitRange>
17366                <access>read-write</access>
17367              </field>
17368              <field>
17369                <name>VREG_EN23</name>
17370                <description>See corresponding definition for IO pins 0 and 1</description>
17371                <bitRange>[8:8]</bitRange>
17372                <access>read-write</access>
17373              </field>
17374              <field>
17375                <name>IBUF_SEL23</name>
17376                <description>See corresponding definition for IO pins 0 and 1</description>
17377                <bitRange>[9:9]</bitRange>
17378                <access>read-write</access>
17379              </field>
17380              <field>
17381                <name>VTRIP_SEL23</name>
17382                <description>See corresponding definition for IO pins 0 and 1</description>
17383                <bitRange>[10:10]</bitRange>
17384                <access>read-write</access>
17385              </field>
17386              <field>
17387                <name>VREF_SEL23</name>
17388                <description>See corresponding definition for IO pins 0 and 1</description>
17389                <bitRange>[12:11]</bitRange>
17390                <access>read-write</access>
17391              </field>
17392              <field>
17393                <name>VOH_SEL23</name>
17394                <description>See corresponding definition for IO pins 0 and 1</description>
17395                <bitRange>[15:13]</bitRange>
17396                <access>read-write</access>
17397              </field>
17398              <field>
17399                <name>VREG_EN45</name>
17400                <description>See corresponding definition for IO pins 0 and 1</description>
17401                <bitRange>[16:16]</bitRange>
17402                <access>read-write</access>
17403              </field>
17404              <field>
17405                <name>IBUF_SEL45</name>
17406                <description>See corresponding definition for IO pins 0 and 1</description>
17407                <bitRange>[17:17]</bitRange>
17408                <access>read-write</access>
17409              </field>
17410              <field>
17411                <name>VTRIP_SEL45</name>
17412                <description>See corresponding definition for IO pins 0 and 1</description>
17413                <bitRange>[18:18]</bitRange>
17414                <access>read-write</access>
17415              </field>
17416              <field>
17417                <name>VREF_SEL45</name>
17418                <description>See corresponding definition for IO pins 0 and 1</description>
17419                <bitRange>[20:19]</bitRange>
17420                <access>read-write</access>
17421              </field>
17422              <field>
17423                <name>VOH_SEL45</name>
17424                <description>See corresponding definition for IO pins 0 and 1</description>
17425                <bitRange>[23:21]</bitRange>
17426                <access>read-write</access>
17427              </field>
17428              <field>
17429                <name>VREG_EN67</name>
17430                <description>See corresponding definition for IO pins 0 and 1</description>
17431                <bitRange>[24:24]</bitRange>
17432                <access>read-write</access>
17433              </field>
17434              <field>
17435                <name>IBUF_SEL67</name>
17436                <description>See corresponding definition for IO pins 0 and 1</description>
17437                <bitRange>[25:25]</bitRange>
17438                <access>read-write</access>
17439              </field>
17440              <field>
17441                <name>VTRIP_SEL67</name>
17442                <description>See corresponding definition for IO pins 0 and 1</description>
17443                <bitRange>[26:26]</bitRange>
17444                <access>read-write</access>
17445              </field>
17446              <field>
17447                <name>VREF_SEL67</name>
17448                <description>See corresponding definition for IO pins 0 and 1</description>
17449                <bitRange>[28:27]</bitRange>
17450                <access>read-write</access>
17451              </field>
17452              <field>
17453                <name>VOH_SEL67</name>
17454                <description>See corresponding definition for IO pins 0 and 1</description>
17455                <bitRange>[31:29]</bitRange>
17456                <access>read-write</access>
17457              </field>
17458            </fields>
17459          </register>
17460          <register>
17461            <name>CFG_IN_AUTOLVL</name>
17462            <description>Port input buffer AUTOLVL configuration register for S40E GPIO</description>
17463            <addressOffset>0x58</addressOffset>
17464            <size>32</size>
17465            <access>read-write</access>
17466            <resetValue>0x0</resetValue>
17467            <resetMask>0xFF</resetMask>
17468            <fields>
17469              <field>
17470                <name>VTRIP_SEL0_1</name>
17471                <description>Configures the input buffer mode (trip points and hysteresis) for S40E GPIO upper bit.  Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field.  This field is used along with CFG_IN.VTRIP_SEL0_0 field as below:
17472{CFG_IN_AUTOLVL.VTRIP_SEL0_1,CFG_IN.VTRIP_SEL0_0}:
174730,0: CMOS
174740,1: TTL
174751,0: input buffer is compatible with automotive.
174761,1: input buffer is compatible with MediaLB.</description>
17477                <bitRange>[0:0]</bitRange>
17478                <access>read-write</access>
17479                <enumeratedValues>
17480                  <enumeratedValue>
17481                    <name>CMOS_OR_TTL</name>
17482                    <description>Input buffer compatible with CMOS/TTL interfaces as described in CFG_IN.VTRIP_SEL0_0.</description>
17483                    <value>0</value>
17484                  </enumeratedValue>
17485                  <enumeratedValue>
17486                    <name>AUTO_OR_MediaLB</name>
17487                    <description>Input buffer compatible with AUTO/MediaLB (elevated Vil) interfaces when used along with CFG_IN.VTRIP_SEL0_0.</description>
17488                    <value>1</value>
17489                  </enumeratedValue>
17490                </enumeratedValues>
17491              </field>
17492              <field>
17493                <name>VTRIP_SEL1_1</name>
17494                <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
17495                <bitRange>[1:1]</bitRange>
17496                <access>read-write</access>
17497              </field>
17498              <field>
17499                <name>VTRIP_SEL2_1</name>
17500                <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
17501                <bitRange>[2:2]</bitRange>
17502                <access>read-write</access>
17503              </field>
17504              <field>
17505                <name>VTRIP_SEL3_1</name>
17506                <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
17507                <bitRange>[3:3]</bitRange>
17508                <access>read-write</access>
17509              </field>
17510              <field>
17511                <name>VTRIP_SEL4_1</name>
17512                <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
17513                <bitRange>[4:4]</bitRange>
17514                <access>read-write</access>
17515              </field>
17516              <field>
17517                <name>VTRIP_SEL5_1</name>
17518                <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
17519                <bitRange>[5:5]</bitRange>
17520                <access>read-write</access>
17521              </field>
17522              <field>
17523                <name>VTRIP_SEL6_1</name>
17524                <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
17525                <bitRange>[6:6]</bitRange>
17526                <access>read-write</access>
17527              </field>
17528              <field>
17529                <name>VTRIP_SEL7_1</name>
17530                <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
17531                <bitRange>[7:7]</bitRange>
17532                <access>read-write</access>
17533              </field>
17534            </fields>
17535          </register>
17536          <register>
17537            <name>CFG_OUT2</name>
17538            <description>Port output buffer configuration register 2</description>
17539            <addressOffset>0x60</addressOffset>
17540            <size>32</size>
17541            <access>read-write</access>
17542            <resetValue>0x0</resetValue>
17543            <resetMask>0xFFFFFF</resetMask>
17544            <fields>
17545              <field>
17546                <name>DS_TRIM0</name>
17547                <description>Sets the Drive Select Trim for  IO pin 0
175480 - Default (50ohms)
175491 - 120ohms
175502 - 90ohms
175513 - 60ohms
175524 - 50ohms
175535 - 30ohms
175546 - 20ohms
175557 - 15ohms</description>
17556                <bitRange>[2:0]</bitRange>
17557                <access>read-write</access>
17558                <enumeratedValues>
17559                  <enumeratedValue>
17560                    <name>DEFAULT</name>
17561                    <description>N/A</description>
17562                    <value>0</value>
17563                  </enumeratedValue>
17564                  <enumeratedValue>
17565                    <name>DS_120OHM</name>
17566                    <description>N/A</description>
17567                    <value>1</value>
17568                  </enumeratedValue>
17569                  <enumeratedValue>
17570                    <name>DS_90OHM</name>
17571                    <description>N/A</description>
17572                    <value>2</value>
17573                  </enumeratedValue>
17574                  <enumeratedValue>
17575                    <name>DS_60OHM</name>
17576                    <description>N/A</description>
17577                    <value>3</value>
17578                  </enumeratedValue>
17579                  <enumeratedValue>
17580                    <name>DS_50OHM</name>
17581                    <description>N/A</description>
17582                    <value>4</value>
17583                  </enumeratedValue>
17584                  <enumeratedValue>
17585                    <name>DS_30OHM</name>
17586                    <description>N/A</description>
17587                    <value>5</value>
17588                  </enumeratedValue>
17589                  <enumeratedValue>
17590                    <name>DS_20OHM</name>
17591                    <description>N/A</description>
17592                    <value>6</value>
17593                  </enumeratedValue>
17594                  <enumeratedValue>
17595                    <name>DS_15OHM</name>
17596                    <description>N/A</description>
17597                    <value>7</value>
17598                  </enumeratedValue>
17599                </enumeratedValues>
17600              </field>
17601              <field>
17602                <name>DS_TRIM1</name>
17603                <description>Sets the Drive Select Trim for IO pin 1</description>
17604                <bitRange>[5:3]</bitRange>
17605                <access>read-write</access>
17606              </field>
17607              <field>
17608                <name>DS_TRIM2</name>
17609                <description>Sets the Drive Select Trim for IO pin 2</description>
17610                <bitRange>[8:6]</bitRange>
17611                <access>read-write</access>
17612              </field>
17613              <field>
17614                <name>DS_TRIM3</name>
17615                <description>Sets the Drive Select Trim for IO pin 3</description>
17616                <bitRange>[11:9]</bitRange>
17617                <access>read-write</access>
17618              </field>
17619              <field>
17620                <name>DS_TRIM4</name>
17621                <description>Sets the Drive Select Trim for IO pin 4</description>
17622                <bitRange>[14:12]</bitRange>
17623                <access>read-write</access>
17624              </field>
17625              <field>
17626                <name>DS_TRIM5</name>
17627                <description>Sets the Drive Select Trim for IO pin 5</description>
17628                <bitRange>[17:15]</bitRange>
17629                <access>read-write</access>
17630              </field>
17631              <field>
17632                <name>DS_TRIM6</name>
17633                <description>Sets the Drive Select Trim for IO pin 6</description>
17634                <bitRange>[20:18]</bitRange>
17635                <access>read-write</access>
17636              </field>
17637              <field>
17638                <name>DS_TRIM7</name>
17639                <description>Sets the Drive Select Trim for IO pin 7</description>
17640                <bitRange>[23:21]</bitRange>
17641                <access>read-write</access>
17642              </field>
17643            </fields>
17644          </register>
17645          <register>
17646            <name>CFG_SLEW_EXT</name>
17647            <description>Port output buffer slew extension configuration register</description>
17648            <addressOffset>0x64</addressOffset>
17649            <size>32</size>
17650            <access>read-write</access>
17651            <resetValue>0x0</resetValue>
17652            <resetMask>0x77777777</resetMask>
17653            <fields>
17654              <field>
17655                <name>SLEW0</name>
17656                <description>Enables slow slew rate for IO pin 0
17657'0': Fast slew rate
17658'1': Slow slew rate</description>
17659                <bitRange>[2:0]</bitRange>
17660                <access>read-write</access>
17661              </field>
17662              <field>
17663                <name>SLEW1</name>
17664                <description>Slew rate for IO pin 1</description>
17665                <bitRange>[6:4]</bitRange>
17666                <access>read-write</access>
17667              </field>
17668              <field>
17669                <name>SLEW2</name>
17670                <description>Slew rate for IO pin 2</description>
17671                <bitRange>[10:8]</bitRange>
17672                <access>read-write</access>
17673              </field>
17674              <field>
17675                <name>SLEW3</name>
17676                <description>Slew rate for IO pin 3</description>
17677                <bitRange>[14:12]</bitRange>
17678                <access>read-write</access>
17679              </field>
17680              <field>
17681                <name>SLEW4</name>
17682                <description>Slew rate for IO pin 4</description>
17683                <bitRange>[18:16]</bitRange>
17684                <access>read-write</access>
17685              </field>
17686              <field>
17687                <name>SLEW5</name>
17688                <description>Slew rate for IO pin 5</description>
17689                <bitRange>[22:20]</bitRange>
17690                <access>read-write</access>
17691              </field>
17692              <field>
17693                <name>SLEW6</name>
17694                <description>Slew rate for IO pin 6</description>
17695                <bitRange>[26:24]</bitRange>
17696                <access>read-write</access>
17697              </field>
17698              <field>
17699                <name>SLEW7</name>
17700                <description>Slew rate for IO pin 7</description>
17701                <bitRange>[30:28]</bitRange>
17702                <access>read-write</access>
17703              </field>
17704            </fields>
17705          </register>
17706          <register>
17707            <name>CFG_DRIVE_EXT0</name>
17708            <description>Port output buffer drive sel extension configuration register</description>
17709            <addressOffset>0x68</addressOffset>
17710            <size>32</size>
17711            <access>read-write</access>
17712            <resetValue>0x0</resetValue>
17713            <resetMask>0x1F1F1F1F</resetMask>
17714            <fields>
17715              <field>
17716                <name>DRIVE_SEL_EXT0</name>
17717                <description>Sets the GPIO drive strength for IO pin 0</description>
17718                <bitRange>[4:0]</bitRange>
17719                <access>read-write</access>
17720              </field>
17721              <field>
17722                <name>DRIVE_SEL_EXT1</name>
17723                <description>Sets the GPIO drive strength for IO pin 1</description>
17724                <bitRange>[12:8]</bitRange>
17725                <access>read-write</access>
17726              </field>
17727              <field>
17728                <name>DRIVE_SEL_EXT2</name>
17729                <description>Sets the GPIO drive strength for IO pin 2</description>
17730                <bitRange>[20:16]</bitRange>
17731                <access>read-write</access>
17732              </field>
17733              <field>
17734                <name>DRIVE_SEL_EXT3</name>
17735                <description>Sets the GPIO drive strength for IO pin 3</description>
17736                <bitRange>[28:24]</bitRange>
17737                <access>read-write</access>
17738              </field>
17739            </fields>
17740          </register>
17741          <register>
17742            <name>CFG_DRIVE_EXT1</name>
17743            <description>Port output buffer drive sel extension configuration register</description>
17744            <addressOffset>0x6C</addressOffset>
17745            <size>32</size>
17746            <access>read-write</access>
17747            <resetValue>0x0</resetValue>
17748            <resetMask>0x1F1F1F1F</resetMask>
17749            <fields>
17750              <field>
17751                <name>DRIVE_SEL_EXT4</name>
17752                <description>Sets the GPIO drive strength for IO pin 4</description>
17753                <bitRange>[4:0]</bitRange>
17754                <access>read-write</access>
17755              </field>
17756              <field>
17757                <name>DRIVE_SEL_EXT5</name>
17758                <description>Sets the GPIO drive strength for IO pin 5</description>
17759                <bitRange>[12:8]</bitRange>
17760                <access>read-write</access>
17761              </field>
17762              <field>
17763                <name>DRIVE_SEL_EXT6</name>
17764                <description>Sets the GPIO drive strength for IO pin 6</description>
17765                <bitRange>[20:16]</bitRange>
17766                <access>read-write</access>
17767              </field>
17768              <field>
17769                <name>DRIVE_SEL_EXT7</name>
17770                <description>Sets the GPIO drive strength for IO pin 7</description>
17771                <bitRange>[28:24]</bitRange>
17772                <access>read-write</access>
17773              </field>
17774            </fields>
17775          </register>
17776        </cluster>
17777        <register>
17778          <name>INTR_CAUSE0</name>
17779          <description>Interrupt port cause register 0</description>
17780          <addressOffset>0x8000</addressOffset>
17781          <size>32</size>
17782          <access>read-only</access>
17783          <resetValue>0x0</resetValue>
17784          <resetMask>0xFFFFFFFF</resetMask>
17785          <fields>
17786            <field>
17787              <name>PORT_INT</name>
17788              <description>Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PRT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt.
17789'0': Port has no pending interrupt
17790'1': Port has pending interrupt</description>
17791              <bitRange>[31:0]</bitRange>
17792              <access>read-only</access>
17793            </field>
17794          </fields>
17795        </register>
17796        <register>
17797          <name>INTR_CAUSE1</name>
17798          <description>Interrupt port cause register 1</description>
17799          <addressOffset>0x8004</addressOffset>
17800          <size>32</size>
17801          <access>read-only</access>
17802          <resetValue>0x0</resetValue>
17803          <resetMask>0xFFFFFFFF</resetMask>
17804          <fields>
17805            <field>
17806              <name>PORT_INT</name>
17807              <description>Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt.
17808'0': Port has no pending interrupt
17809'1': Port has pending interrupt</description>
17810              <bitRange>[31:0]</bitRange>
17811              <access>read-only</access>
17812            </field>
17813          </fields>
17814        </register>
17815        <register>
17816          <name>INTR_CAUSE2</name>
17817          <description>Interrupt port cause register 2</description>
17818          <addressOffset>0x8008</addressOffset>
17819          <size>32</size>
17820          <access>read-only</access>
17821          <resetValue>0x0</resetValue>
17822          <resetMask>0xFFFFFFFF</resetMask>
17823          <fields>
17824            <field>
17825              <name>PORT_INT</name>
17826              <description>Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt.
17827'0': Port has no pending interrupt
17828'1': Port has pending interrupt</description>
17829              <bitRange>[31:0]</bitRange>
17830              <access>read-only</access>
17831            </field>
17832          </fields>
17833        </register>
17834        <register>
17835          <name>INTR_CAUSE3</name>
17836          <description>Interrupt port cause register 3</description>
17837          <addressOffset>0x800C</addressOffset>
17838          <size>32</size>
17839          <access>read-only</access>
17840          <resetValue>0x0</resetValue>
17841          <resetMask>0xFFFFFFFF</resetMask>
17842          <fields>
17843            <field>
17844              <name>PORT_INT</name>
17845              <description>Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt.
17846'0': Port has no pending interrupt
17847'1': Port has pending interrupt</description>
17848              <bitRange>[31:0]</bitRange>
17849              <access>read-only</access>
17850            </field>
17851          </fields>
17852        </register>
17853        <register>
17854          <name>VDD_ACTIVE</name>
17855          <description>Extern power supply detection register</description>
17856          <addressOffset>0x8010</addressOffset>
17857          <size>32</size>
17858          <access>read-only</access>
17859          <resetValue>0x0</resetValue>
17860          <resetMask>0xC000FFFF</resetMask>
17861          <fields>
17862            <field>
17863              <name>VDDIO_ACTIVE</name>
17864              <description>Indicates presence or absence of VDDIO supplies (i.e. other than VDDD, VDDA) on the device (supplies are numbered 0..n-1).  Note that VDDIO supplies have basic (crude) supply detectors only.  If separate, robust, brown-out detection is desired on IO supplies, on-chip or off-chip analog resources need to provide it.  For these bits to work reliable, the supply must be within valid spec range (per datasheet) or held at ground.  Any in-between voltage has an undefined result.
17865'0': Supply is not present
17866'1': Supply is present
17867
17868When multiple VDDIO supplies are present, they will be assigned in alphanumeric ascending order to these bits during implementation.
17869For example 'vddusb, vddio_0, vddio_a, vbackup, vddio_r, vddio_1' are present then they will be assigned to these bits as below:
178700: vbackup,
178711: vddio_0,
178722: vddio_1,
178733: vddio_a,
178744: vddio_r,
178755: vddusb'</description>
17876              <bitRange>[15:0]</bitRange>
17877              <access>read-only</access>
17878            </field>
17879            <field>
17880              <name>VDDA_ACTIVE</name>
17881              <description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
17882              <bitRange>[30:30]</bitRange>
17883              <access>read-only</access>
17884            </field>
17885            <field>
17886              <name>VDDD_ACTIVE</name>
17887              <description>This bit indicates presence of the VDDD supply.  This bit will always read-back 1.  The VDDD supply has robust brown-out protection monitoring and it is not possible to read back this register without a valid supply. (This bit is used in certain test-modes to observe the brown-out detector status.)</description>
17888              <bitRange>[31:31]</bitRange>
17889              <access>read-only</access>
17890            </field>
17891          </fields>
17892        </register>
17893        <register>
17894          <name>VDD_INTR</name>
17895          <description>Supply detection interrupt register</description>
17896          <addressOffset>0x8014</addressOffset>
17897          <size>32</size>
17898          <access>read-write</access>
17899          <resetValue>0x0</resetValue>
17900          <resetMask>0xC000FFFF</resetMask>
17901          <fields>
17902            <field>
17903              <name>VDDIO_ACTIVE</name>
17904              <description>Supply state change detected.
17905'0': No change to supply detected
17906'1': Change to supply detected</description>
17907              <bitRange>[15:0]</bitRange>
17908              <access>read-write</access>
17909            </field>
17910            <field>
17911              <name>VDDA_ACTIVE</name>
17912              <description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
17913              <bitRange>[30:30]</bitRange>
17914              <access>read-write</access>
17915            </field>
17916            <field>
17917              <name>VDDD_ACTIVE</name>
17918              <description>The VDDD supply is always present during operation so a supply transition can not occur. This bit will always read back '1'.</description>
17919              <bitRange>[31:31]</bitRange>
17920              <access>read-write</access>
17921            </field>
17922          </fields>
17923        </register>
17924        <register>
17925          <name>VDD_INTR_MASK</name>
17926          <description>Supply detection interrupt mask register</description>
17927          <addressOffset>0x8018</addressOffset>
17928          <size>32</size>
17929          <access>read-write</access>
17930          <resetValue>0x0</resetValue>
17931          <resetMask>0xC000FFFF</resetMask>
17932          <fields>
17933            <field>
17934              <name>VDDIO_ACTIVE</name>
17935              <description>Masks supply interrupt on VDDIO.
17936'0': VDDIO interrupt forwarding disabled
17937'1': VDDIO interrupt forwarding enabled</description>
17938              <bitRange>[15:0]</bitRange>
17939              <access>read-write</access>
17940            </field>
17941            <field>
17942              <name>VDDA_ACTIVE</name>
17943              <description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
17944              <bitRange>[30:30]</bitRange>
17945              <access>read-write</access>
17946            </field>
17947            <field>
17948              <name>VDDD_ACTIVE</name>
17949              <description>Same as VDDIO_ACTIVE for the digital supply VDDD.</description>
17950              <bitRange>[31:31]</bitRange>
17951              <access>read-write</access>
17952            </field>
17953          </fields>
17954        </register>
17955        <register>
17956          <name>VDD_INTR_MASKED</name>
17957          <description>Supply detection interrupt masked register</description>
17958          <addressOffset>0x801C</addressOffset>
17959          <size>32</size>
17960          <access>read-only</access>
17961          <resetValue>0x0</resetValue>
17962          <resetMask>0xC000FFFF</resetMask>
17963          <fields>
17964            <field>
17965              <name>VDDIO_ACTIVE</name>
17966              <description>Supply transition detected AND masked
17967'0': Interrupt was not forwarded to CPU
17968'1': Interrupt occurred and was forwarded to CPU</description>
17969              <bitRange>[15:0]</bitRange>
17970              <access>read-only</access>
17971            </field>
17972            <field>
17973              <name>VDDA_ACTIVE</name>
17974              <description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
17975              <bitRange>[30:30]</bitRange>
17976              <access>read-only</access>
17977            </field>
17978            <field>
17979              <name>VDDD_ACTIVE</name>
17980              <description>Same as VDDIO_ACTIVE for the digital supply VDDD.</description>
17981              <bitRange>[31:31]</bitRange>
17982              <access>read-only</access>
17983            </field>
17984          </fields>
17985        </register>
17986        <register>
17987          <name>VDD_INTR_SET</name>
17988          <description>Supply detection interrupt set register</description>
17989          <addressOffset>0x8020</addressOffset>
17990          <size>32</size>
17991          <access>read-write</access>
17992          <resetValue>0x0</resetValue>
17993          <resetMask>0xC000FFFF</resetMask>
17994          <fields>
17995            <field>
17996              <name>VDDIO_ACTIVE</name>
17997              <description>Sets supply interrupt.
17998'0': Interrupt state not affected
17999'1': Interrupt set</description>
18000              <bitRange>[15:0]</bitRange>
18001              <access>read-write</access>
18002            </field>
18003            <field>
18004              <name>VDDA_ACTIVE</name>
18005              <description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
18006              <bitRange>[30:30]</bitRange>
18007              <access>read-write</access>
18008            </field>
18009            <field>
18010              <name>VDDD_ACTIVE</name>
18011              <description>Same as VDDIO_ACTIVE for the digital supply VDDD.</description>
18012              <bitRange>[31:31]</bitRange>
18013              <access>read-write</access>
18014            </field>
18015          </fields>
18016        </register>
18017      </registers>
18018    </peripheral>
18019    <peripheral>
18020      <name>SMARTIO</name>
18021      <description>Programmable IO configuration</description>
18022      <baseAddress>0x40420000</baseAddress>
18023      <addressBlock>
18024        <offset>0</offset>
18025        <size>65536</size>
18026        <usage>registers</usage>
18027      </addressBlock>
18028      <registers>
18029        <cluster>
18030          <dim>4</dim>
18031          <dimIncrement>256</dimIncrement>
18032          <name>PRT[%s]</name>
18033          <description>Programmable IO port registers</description>
18034          <addressOffset>0x00000000</addressOffset>
18035          <register>
18036            <name>CTL</name>
18037            <description>Control register</description>
18038            <addressOffset>0x0</addressOffset>
18039            <size>32</size>
18040            <access>read-write</access>
18041            <resetValue>0x2001400</resetValue>
18042            <resetMask>0x82001F00</resetMask>
18043            <fields>
18044              <field>
18045                <name>BYPASS</name>
18046                <description>Bypass of the programmable IO, one bit for each IO pin: BYPASS[i] is for IO pin i. When ENABLED is '1', this field is used. When ENABLED is '0', this field is NOT used and SMARTIO fabric is always bypassed.
18047'0': No bypass (programmable SMARTIO fabric is exposed).
18048'1': Bypass (programmable SMARTIOIO fabric is hidden).</description>
18049                <bitRange>[7:0]</bitRange>
18050                <access>read-write</access>
18051              </field>
18052              <field>
18053                <name>CLOCK_SRC</name>
18054                <description>Clock ('clk_fabric') and reset ('rst_fabric_n') source selection:
18055'0': io_data_in[0]/'1'.
18056...
18057'7': io_data_in[7]/'1'.
18058'8': chip_data[0]/'1'.
18059...
18060'15': chip_data[7]/'1'.
18061'16': clk_smartio/rst_sys_act_n. Used for both Active functionality synchronous logic on 'clk_smartio'. This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_smartio_pos_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'.
18062'17': clk_smartio/rst_sys_dpslp_n. Used for both DeepSleep functionality synchronous logic on 'clk_smartio' (note that 'clk_smartio' is NOT available in DeepSleep and Hibernate power modes).  This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_smartio_pos_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'.
18063'18': Same as '17'. Note that the M0S8 SMARTIO version used the Hibernate reset for this value, but the MXS40 SMARTIO version does not support Hibernate functionality.
18064'19': clk_lf/rst_lf_dpslp_n (note that 'clk_lf' is available in DeepSleep power mode). This selection is intended for synchronous operation on'clk_lf'. Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to other 'clk_lf' clocked elements.
18065'20'-'30': Clock source is constant '0'. Any of these clock sources should be selected when the IP is disabled to ensure low power consumption.
18066'31': asynchronous mode/'1'.  Select this when clockless operation is configured.
18067
18068NOTE: Two positive edges of the selected clock are required for the block to be enabled (to deactivate reset).  In asynchronous (clockless) mode clk_sys is used to enable the block, but is not available for clocking.</description>
18069                <bitRange>[12:8]</bitRange>
18070                <access>read-write</access>
18071              </field>
18072              <field>
18073                <name>HLD_OVR</name>
18074                <description>IO cell hold override functionality. In DeepSleep power mode, the HSIOM holds the IO cell output and output enable signals if Active functionality is connected to the IO pads. This is undesirable if the SMARTIO is supposed to deliver DeepSleep output functionality on these IO pads. This field is used to control the hold override functionality from the SMARTIO:
18075'0': The HSIOM controls the IO cell hold override functionality ('hsiom_hld_ovr').
18076'1': The SMARTIO controls the IO cel hold override functionality:
18077- In bypass mode (ENABLED is '0' or BYPASS[i] is '1'), the HSIOM control is used.
18078- In NON bypass mode (ENABLED is '1' and BYPASS[i] is '0'), the SMARTIO sets hold override to 'pwr_hld_ovr_hib' to enable SMARTIO functionality in DeepSleep power mode (but disables it in Hibernate or Stop power mode).</description>
18079                <bitRange>[24:24]</bitRange>
18080                <access>read-write</access>
18081              </field>
18082              <field>
18083                <name>PIPELINE_EN</name>
18084                <description>Enable for pipeline register:
18085'0': Disabled (register is bypassed).
18086'1': Enabled.</description>
18087                <bitRange>[25:25]</bitRange>
18088                <access>read-write</access>
18089              </field>
18090              <field>
18091                <name>ENABLED</name>
18092                <description>Enable for programmable IO. Should only be set to '1' when the programmable IO is completely configured:
18093'0': Disabled (signals are bypassed; behavior as if BYPASS is 0xFF). When disabled, the fabric (data unit and LUTs) reset is activated.
18094
18095If the IP is disabled:
18096- The PIPELINE_EN register field should be set to '1', to ensure low power consumption by preventing combinatorial loops.
18097- The CLOCK_SRC register field should be set to '20'-'30' (clock is constant '0'), to ensure low power consumption.
18098
18099'1': Enabled. Once enabled, it takes 3 'clk_fabric' clock cycles till the fabric reset is de-activated and the fabric becomes fully functional. This ensures that the IO pins' input synchronizer states are flushed when the fabric is fully functional.</description>
18100                <bitRange>[31:31]</bitRange>
18101                <access>read-write</access>
18102              </field>
18103            </fields>
18104          </register>
18105          <register>
18106            <name>SYNC_CTL</name>
18107            <description>Synchronization control register</description>
18108            <addressOffset>0x10</addressOffset>
18109            <size>32</size>
18110            <access>read-write</access>
18111            <resetValue>0x0</resetValue>
18112            <resetMask>0x0</resetMask>
18113            <fields>
18114              <field>
18115                <name>IO_SYNC_EN</name>
18116                <description>Synchronization of the IO pin input signals to 'clk_fabric', one bit for each IO pin: IO_SYNC_EN[i] is for IO pin i.
18117'0': No synchronization.
18118'1': Synchronization.</description>
18119                <bitRange>[7:0]</bitRange>
18120                <access>read-write</access>
18121              </field>
18122              <field>
18123                <name>CHIP_SYNC_EN</name>
18124                <description>Synchronization of the chip input signals to 'clk_fabric', one bit for each input: CHIP_SYNC_EN[i] is for input i.
18125'0': No synchronization.
18126'1': Synchronization.</description>
18127                <bitRange>[15:8]</bitRange>
18128                <access>read-write</access>
18129              </field>
18130            </fields>
18131          </register>
18132          <register>
18133            <dim>8</dim>
18134            <dimIncrement>4</dimIncrement>
18135            <name>LUT_SEL[%s]</name>
18136            <description>LUT component input selection</description>
18137            <addressOffset>0x20</addressOffset>
18138            <size>32</size>
18139            <access>read-write</access>
18140            <resetValue>0x0</resetValue>
18141            <resetMask>0x0</resetMask>
18142            <fields>
18143              <field>
18144                <name>LUT_TR0_SEL</name>
18145                <description>LUT input signal 'tr0_in' source selection:
18146'0': Data unit output.
18147'1': LUT 1 output.
18148'2': LUT 2 output.
18149'3': LUT 3 output.
18150'4': LUT 4 output.
18151'5': LUT 5 output.
18152'6': LUT 6 output.
18153'7': LUT 7 output.
18154'8': chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7).
18155'9': chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7).
18156'10': chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7).
18157'11': chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7).
18158'12': io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7).
18159'13': io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7).
18160'14': io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7).
18161'15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7).</description>
18162                <bitRange>[3:0]</bitRange>
18163                <access>read-write</access>
18164              </field>
18165              <field>
18166                <name>LUT_TR1_SEL</name>
18167                <description>LUT input signal 'tr1_in' source selection:
18168'0': LUT 0 output.
18169'1': LUT 1 output.
18170'2': LUT 2 output.
18171'3': LUT 3 output.
18172'4': LUT 4 output.
18173'5': LUT 5 output.
18174'6': LUT 6 output.
18175'7': LUT 7 output.
18176'8': chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7).
18177'9': chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7).
18178'10': chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7).
18179'11': chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7).
18180'12': io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7).
18181'13': io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7).
18182'14': io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7).
18183'15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7).</description>
18184                <bitRange>[11:8]</bitRange>
18185                <access>read-write</access>
18186              </field>
18187              <field>
18188                <name>LUT_TR2_SEL</name>
18189                <description>LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL.</description>
18190                <bitRange>[19:16]</bitRange>
18191                <access>read-write</access>
18192              </field>
18193            </fields>
18194          </register>
18195          <register>
18196            <dim>8</dim>
18197            <dimIncrement>4</dimIncrement>
18198            <name>LUT_CTL[%s]</name>
18199            <description>LUT component control register</description>
18200            <addressOffset>0x40</addressOffset>
18201            <size>32</size>
18202            <access>read-write</access>
18203            <resetValue>0x0</resetValue>
18204            <resetMask>0x0</resetMask>
18205            <fields>
18206              <field>
18207                <name>LUT</name>
18208                <description>LUT configuration. Depending on the LUT opcode LUT_OPC, the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in, tr1_in, tr2_in, the LUT configuration is used to determine the LUT output signal and the next sequential state (lut_reg).</description>
18209                <bitRange>[7:0]</bitRange>
18210                <access>read-write</access>
18211              </field>
18212              <field>
18213                <name>LUT_OPC</name>
18214                <description>LUT opcode specifies the LUT operation:
18215'0': Combinatoral output, no feedback.
18216   tr_out   = LUT[{tr2_in, tr1_in, tr0_in}].
18217'1': Combinatorial output, feedback.
18218   tr_out   = LUT[{lut_reg, tr1_in, tr0_in}].
18219On clock:
18220    lut_reg &lt;= tr_in2.
18221'2': Sequential output, no feedback.
18222   temp    = LUT[{tr2_in, tr1_in, tr0_in}].
18223   tr_out   = lut_reg.
18224On clock:
18225   lut_reg &lt;= temp.
18226'3': Register with asynchronous set and reset.
18227   tr_out           = lut_reg.
18228   enable          = (tr2_in ^ LUT[4]) | LUT[5].
18229   set               = enable &amp; (tr1_in ^ LUT[2]) &amp; LUT[3].
18230   clr                = enable &amp; (tr0_in ^ LUT[0]) &amp; LUT[1].
18231Asynchronously (no clock required):
18232   lut_reg         &lt;= if (clr) '0' else if (set) '1'</description>
18233                <bitRange>[9:8]</bitRange>
18234                <access>read-write</access>
18235              </field>
18236            </fields>
18237          </register>
18238          <register>
18239            <name>DU_SEL</name>
18240            <description>Data unit component input selection</description>
18241            <addressOffset>0xC0</addressOffset>
18242            <size>32</size>
18243            <access>read-write</access>
18244            <resetValue>0x0</resetValue>
18245            <resetMask>0x0</resetMask>
18246            <fields>
18247              <field>
18248                <name>DU_TR0_SEL</name>
18249                <description>Data unit input signal 'tr0_in' source selection:
18250'0': Constant '0'.
18251'1': Constant '1'.
18252'2': Data unit output.
18253'10-3': LUT 7 - 0 outputs.
18254Otherwise: Undefined.</description>
18255                <bitRange>[3:0]</bitRange>
18256                <access>read-write</access>
18257              </field>
18258              <field>
18259                <name>DU_TR1_SEL</name>
18260                <description>Data unit input signal 'tr1_in' source selection. Encoding is the same as for DU_TR0_SEL.</description>
18261                <bitRange>[11:8]</bitRange>
18262                <access>read-write</access>
18263              </field>
18264              <field>
18265                <name>DU_TR2_SEL</name>
18266                <description>Data unit input signal 'tr2_in' source selection. Encoding is the same as for DU_TR0_SEL.</description>
18267                <bitRange>[19:16]</bitRange>
18268                <access>read-write</access>
18269              </field>
18270              <field>
18271                <name>DU_DATA0_SEL</name>
18272                <description>Data unit input data 'data0_in' source selection:
18273'0': Constant '0'.
18274'1': chip_data[7:0].
18275'2': io_data_in[7:0].
18276'3': DATA.DATA MMIO register field.</description>
18277                <bitRange>[25:24]</bitRange>
18278                <access>read-write</access>
18279              </field>
18280              <field>
18281                <name>DU_DATA1_SEL</name>
18282                <description>Data unit input data 'data1_in' source selection. Encoding is the same as for DU_DATA0_SEL.</description>
18283                <bitRange>[29:28]</bitRange>
18284                <access>read-write</access>
18285              </field>
18286            </fields>
18287          </register>
18288          <register>
18289            <name>DU_CTL</name>
18290            <description>Data unit component control register</description>
18291            <addressOffset>0xC4</addressOffset>
18292            <size>32</size>
18293            <access>read-write</access>
18294            <resetValue>0x0</resetValue>
18295            <resetMask>0x0</resetMask>
18296            <fields>
18297              <field>
18298                <name>DU_SIZE</name>
18299                <description>Size/width of the data unit data operands (in bits) is DU_SIZE+1. E.g., if DU_SIZE is 7, the width is 8 bits.</description>
18300                <bitRange>[2:0]</bitRange>
18301                <access>read-write</access>
18302              </field>
18303              <field>
18304                <name>DU_OPC</name>
18305                <description>Data unit opcode specifies the data unit operation:
18306'1': INCR
18307'2': DECR
18308'3': INCR_WRAP
18309'4': DECR_WRAP
18310'5': INCR_DECR
18311'6': INCR_DECR_WRAP
18312'7': ROR
18313'8': SHR
18314'9': AND_OR
18315'10': SHR_MAJ3
18316'11': SHR_EQL.
18317Otherwise: Undefined.</description>
18318                <bitRange>[11:8]</bitRange>
18319                <access>read-write</access>
18320              </field>
18321            </fields>
18322          </register>
18323          <register>
18324            <name>DATA</name>
18325            <description>Data register</description>
18326            <addressOffset>0xF0</addressOffset>
18327            <size>32</size>
18328            <access>read-write</access>
18329            <resetValue>0x0</resetValue>
18330            <resetMask>0x0</resetMask>
18331            <fields>
18332              <field>
18333                <name>DATA</name>
18334                <description>Data unit input data source.</description>
18335                <bitRange>[7:0]</bitRange>
18336                <access>read-write</access>
18337              </field>
18338            </fields>
18339          </register>
18340        </cluster>
18341      </registers>
18342    </peripheral>
18343    <peripheral>
18344      <name>LIN0</name>
18345      <description>LIN</description>
18346      <headerStructName>LIN</headerStructName>
18347      <baseAddress>0x40430000</baseAddress>
18348      <addressBlock>
18349        <offset>0</offset>
18350        <size>65536</size>
18351        <usage>registers</usage>
18352      </addressBlock>
18353      <registers>
18354        <register>
18355          <name>ERROR_CTL</name>
18356          <description>Error control</description>
18357          <addressOffset>0x0</addressOffset>
18358          <size>32</size>
18359          <access>read-write</access>
18360          <resetValue>0x0</resetValue>
18361          <resetMask>0x80EF001F</resetMask>
18362          <fields>
18363            <field>
18364              <name>CH_IDX</name>
18365              <description>Specifies the channel index of the channel to which HW  injected channel transmitter errors applies.</description>
18366              <bitRange>[4:0]</bitRange>
18367              <access>read-write</access>
18368            </field>
18369            <field>
18370              <name>TX_SYNC_ERROR</name>
18371              <description>The synchronization field is changed from 0x55 to 0x00.
18372
18373At the receiver, this should result in INTR.RX_HEADER_SYNC_ERROR activation.</description>
18374              <bitRange>[16:16]</bitRange>
18375              <access>read-write</access>
18376            </field>
18377            <field>
18378              <name>TX_SYNC_STOP_ERROR</name>
18379              <description>The synchronization field STOP bits are inverted to '0'.
18380
18381At the receiver, this should result in INTR.RX_HEADER_SYNC_ERROR or INTR.RX_HEADER_FRAME_ERROR activation.</description>
18382              <bitRange>[17:17]</bitRange>
18383              <access>read-write</access>
18384            </field>
18385            <field>
18386              <name>TX_PARITY_ERROR</name>
18387              <description>In LIN mode, the PID parity bit P[1] is inverted from !(ID[5] ^ ID[4] ^ ID[3] ^ ID[1]) to (ID[5] ^ ID[4] ^ ID[3] ^ ID[1]).
18388
18389At the receiver, this should result in INTR.RX_HEADER_PARITY_ERROR activation.
18390
18391In UART mode, a data field's parity bit is inverted.</description>
18392              <bitRange>[18:18]</bitRange>
18393              <access>read-write</access>
18394            </field>
18395            <field>
18396              <name>TX_PID_STOP_ERROR</name>
18397              <description>The PID field STOP bits are inverted to '0'.
18398
18399At the receiver, this should result in INTR.RX_HEADER_FRAME_ERROR activation.</description>
18400              <bitRange>[19:19]</bitRange>
18401              <access>read-write</access>
18402            </field>
18403            <field>
18404              <name>TX_DATA_STOP_ERROR</name>
18405              <description>The data field STOP bits are inverted to '0'.
18406
18407At the receiver, this should result in INTR.RX_RESPONSE_FRAME_ERROR activation.
18408
18409Note: Used in UART mode.</description>
18410              <bitRange>[21:21]</bitRange>
18411              <access>read-write</access>
18412            </field>
18413            <field>
18414              <name>TX_CHECKSUM_ERROR</name>
18415              <description>The checksum field is inverted.
18416
18417At the receiver, this should result in INTR.RX_RESPONSE_CHECKSUM_ERROR activation.</description>
18418              <bitRange>[22:22]</bitRange>
18419              <access>read-write</access>
18420            </field>
18421            <field>
18422              <name>TX_CHECKSUM_STOP_ERROR</name>
18423              <description>The checksum field STOP bits are inverted to '0'.
18424
18425At the receiver, this should result in INTR.RX_RESPONSE_FRAME_ERROR activation.</description>
18426              <bitRange>[23:23]</bitRange>
18427              <access>read-write</access>
18428            </field>
18429            <field>
18430              <name>ENABLED</name>
18431              <description>Error injection enable:
18432'0': Disabled.
18433'1': Enabled.</description>
18434              <bitRange>[31:31]</bitRange>
18435              <access>read-write</access>
18436            </field>
18437          </fields>
18438        </register>
18439        <register>
18440          <name>TEST_CTL</name>
18441          <description>Test control</description>
18442          <addressOffset>0x4</addressOffset>
18443          <size>32</size>
18444          <access>read-write</access>
18445          <resetValue>0x0</resetValue>
18446          <resetMask>0x8001001F</resetMask>
18447          <fields>
18448            <field>
18449              <name>CH_IDX</name>
18450              <description>Specifies the channel index of the channel to which test applies. The channel IO signals of channel indices CH_IDX and CH_NR-1 are connected as specified by MODE. CH_IDX should be in the range [0, CH_NR-2], as channel index CH_NR-1 is always involved in test and cannot be connected to itself. The test mode allows BOTH of the two connected channels to be tested.
18451
18452Note: this testing functionality simplifies SW development, but may also be used in the field to verify correct channel functionality.</description>
18453              <bitRange>[4:0]</bitRange>
18454              <access>read-write</access>
18455            </field>
18456            <field>
18457              <name>MODE</name>
18458              <description>Test mode:
18459'0': Partial disconnect from IOSS. This mode's isolation allows for device test without relying on an external LIN transceiver. The IOSS 'tx' IO cell can be used to observe messages outside of the device.
18460- tx_in[CH_IDX] = IOSS lin_tx_in[CH_IDX].
18461- tx_in[CH_NR-1] = IOSS lin_tx_in[CH_IDX].
18462- rx_in[CH_IDX] = IOSS lin_tx_in[CH_IDX].
18463- rx_in[CH_NR-1] = IOSS lin_tx_in[CH_IDX].
18464- lin_tx_out[CH_IDX] = tx_out[CH_IDX] &amp; tx_out[CH_NR-1].
18465- lin_tx_out[CH_NR-1] = tx_out[CH_IDX] &amp; tx_out[CH_NR-1].
18466
18467'1': Full disconnect from IOSS (the IOSS/HSIOM should disconnect 'tx_out' from the 'tx' IO cell). This mode's isolation allows for device test without effecting an operational LIN cluster.
18468- tx_in[CH_IDX] = lin_tx_out[CH_IDX].
18469- tx_in[CH_NR-1] = lin_tx_out[CH_IDX].
18470- rx_in[CH_IDX] = lin_tx_out[CH_IDX].
18471- rx_in[CH_NR-1] = lin_tx_out[CH_IDX].
18472- lin_tx_out[CH_IDX] = tx_out[CH_IDX] &amp; tx_out[CH_NR-1].
18473- lin_tx_out[CH_NR-1] = tx_out[CH_IDX] &amp; tx_out[CH_NR-1].</description>
18474              <bitRange>[16:16]</bitRange>
18475              <access>read-write</access>
18476            </field>
18477            <field>
18478              <name>ENABLED</name>
18479              <description>Test enable:
18480'0': Disabled. Functional mode.
18481- tx_in[CH_IDX] = IOSS lin_tx_in[CH_IDX].
18482- tx_in[CH_NR-1] = IOSS lin_tx_in[CH_NR-1].
18483- rx_in[CH_IDX] = IOSS lin_rx_in[CH_IDX].
18484- rx_in[CH_NR-1] = IOSS lin_rx_in[CH_NR-1].
18485- lin_tx_out[CH_IDX] = tx_out[CH_IDX].
18486- lin_tx_out[CH_NR-1] = tx_out[CH_NR-1].
18487'1': Enabled. Test mode, specific test mode is specified by MODE.</description>
18488              <bitRange>[31:31]</bitRange>
18489              <access>read-write</access>
18490            </field>
18491          </fields>
18492        </register>
18493        <cluster>
18494          <dim>2</dim>
18495          <dimIncrement>256</dimIncrement>
18496          <name>CH[%s]</name>
18497          <description>LIN channel structure</description>
18498          <addressOffset>0x00008000</addressOffset>
18499          <register>
18500            <name>CTL0</name>
18501            <description>Control 0</description>
18502            <addressOffset>0x0</addressOffset>
18503            <size>32</size>
18504            <access>read-write</access>
18505            <resetValue>0x400C0101</resetValue>
18506            <resetMask>0xF91F0313</resetMask>
18507            <fields>
18508              <field>
18509                <name>STOP_BITS</name>
18510                <description>STOP bit periods:
18511'0': 1/2 bit period.
18512'1': 1 bit period.
18513'2': 1 1/2 bit period.
18514'3': 2 bit periods.
18515
18516
18517In LIN mode, this field should be set to '1' (the default value) .
18518
18519In UART mode, this field can be programmed as desired.
18520
18521Note: receiver STOP bit frame errors can only be detected if the number of STOP bit periods is 1 or more bit period.</description>
18522                <bitRange>[1:0]</bitRange>
18523                <access>read-write</access>
18524              </field>
18525              <field>
18526                <name>AUTO_EN</name>
18527                <description>LIN transceiver auto enable:
18528'0': Disabled.
18529'1': Enabled. The TX_RX_STATUS.EN_OUT field is controlled by HW.</description>
18530                <bitRange>[4:4]</bitRange>
18531                <access>read-write</access>
18532              </field>
18533              <field>
18534                <name>BREAK_DELIMITER_LENGTH</name>
18535                <description>In LIN mode, this field specifies the break delimiter length:
18536(used in header transmission, not used in header reception).
18537'0': 1 bit period.
18538'1': 2 bit periods (default value).
18539'2': 3 bit periods.
18540'3': 4 bit periods.
18541
18542In UART mode, this field specifies the data field size:
18543'0': 5 bit data field.
18544'1': 6 bit data field.
18545'2': 7 bit data field.
18546'3': 8 bit data field.
18547When the data field size is less than 8 bits, the most significant (unused) bits of the DATAx.DATAy[7:0] fields should be set to '0' for the transmitter.</description>
18548                <bitRange>[9:8]</bitRange>
18549                <access>read-write</access>
18550              </field>
18551              <field>
18552                <name>BREAK_WAKEUP_LENGTH</name>
18553                <description>Break/wakeup length (minus 1) in bit periods:
18554'0': 1 bit period.
18555...
18556'10': 11 bit periods (break length for slave nodes)
18557...
18558'12': 13 bit periods (break length for master nodes)
18559...
18560'30': 31 bit periods.
18561'31': Illegal (should NOT be used!!!)
18562
18563This field is used for transmission/reception of BOTH break and wakeup signals. Note that these functions are mutually exclusive:
18564- When CMD.TX_HEADER is '1', the field specifies the transmitted break field.
18565- When CMD.TX_WAKEUP is '1', the field specifies the transmitted wakeup field.
18566- When CMD.RX_HEADER is '1', the field specifies the to be received break field.
18567- Otherwise, the field specifies the to be received wakeup field.
18568
18569Per the standard, the master wakeup duration is between 250 us and 5 ms. To support uncalibrated slaves, a slave has a detection threshold of 150 us (3 bit periods at 20 kbps). After transmission of a break or wakeup signal, the INTR.TX_BREAK_WAKEUP_DONE interrupt cause is activated. After reception of a wakeup signal, the INTR.RX_BREAK_WAKEUP_DONE interrupt cause is activated.
18570
18571To specify longer wakeup signals in terms of absolute time (us/ms rather than bit periods), the associated PERI clock divider value can be (temporarily) increased to make the LIN bit period longer.
18572
18573Note: entering bus sleep mode is achieved with the 'go-to-sleep' command.</description>
18574                <bitRange>[20:16]</bitRange>
18575                <access>read-write</access>
18576              </field>
18577              <field>
18578                <name>MODE</name>
18579                <description>Mode of operation:
18580'0': LIN mode.
18581'1': UART mode.</description>
18582                <bitRange>[24:24]</bitRange>
18583                <access>read-write</access>
18584                <enumeratedValues>
18585                  <enumeratedValue>
18586                    <name>LIN</name>
18587                    <description>LIN mode.</description>
18588                    <value>0</value>
18589                  </enumeratedValue>
18590                  <enumeratedValue>
18591                    <name>UART</name>
18592                    <description>UART mode.</description>
18593                    <value>1</value>
18594                  </enumeratedValue>
18595                </enumeratedValues>
18596              </field>
18597              <field>
18598                <name>BIT_ERROR_IGNORE</name>
18599                <description>Specifies behavior on a detected bit error during header or response transmission:
18600'0': Message transfer is aborted.
18601'1': Message transfer is NOT aborted.
18602
18603Note: this field does NOT effect the reporting of the bit error through INTR/STATUS.TX_HEADER/RESPONSE_BIT_ERROR; i.e. bit errors are always reported.</description>
18604                <bitRange>[27:27]</bitRange>
18605                <access>read-write</access>
18606              </field>
18607              <field>
18608                <name>PARITY</name>
18609                <description>Parity mode:
18610'0': Even parity: even number of '1' bits (including parity).
18611'1': Odd parity.
18612
18613Note: Used in UART mode only.</description>
18614                <bitRange>[28:28]</bitRange>
18615                <access>read-write</access>
18616              </field>
18617              <field>
18618                <name>PARITY_EN</name>
18619                <description>Parity generation enable:
18620'0': Disabled. No parity bit is transferred.
18621'1': Enabled. The parity bit is transferred after the last (most significant) data field bit.
18622
18623Note: Used in UART mode only.</description>
18624                <bitRange>[29:29]</bitRange>
18625                <access>read-write</access>
18626              </field>
18627              <field>
18628                <name>FILTER_EN</name>
18629                <description>RX filter (for 'lin_rx_in'):
18630'0': No filter.
18631'1': Median 3 (default value) operates on the last three 'lin_rx_in' values. The sequences '000', '001', '010' and '100' result in a filtered value '0'. The sequences '111', '110', '101' and '011' result in a filtered value '1'.</description>
18632                <bitRange>[30:30]</bitRange>
18633                <access>read-write</access>
18634              </field>
18635              <field>
18636                <name>ENABLED</name>
18637                <description>Channel enable:
18638'0': Disabled. If a channel is disabled, all non-retained MMIO registers (e.g. the TX_RX_STATUS, and INTR registers) have their fields reset to their default value.
18639'1': Enabled.</description>
18640                <bitRange>[31:31]</bitRange>
18641                <access>read-write</access>
18642              </field>
18643            </fields>
18644          </register>
18645          <register>
18646            <name>CTL1</name>
18647            <description>Control 1</description>
18648            <addressOffset>0x4</addressOffset>
18649            <size>32</size>
18650            <access>read-write</access>
18651            <resetValue>0x0</resetValue>
18652            <resetMask>0x3000000</resetMask>
18653            <fields>
18654              <field>
18655                <name>DATA_NR</name>
18656                <description>Number of data fields (minus 1) in the response (not including the checksum):
18657'0': 1 data field.
18658'1': 2 data fields.
18659...
18660'7': 8 data fields.
18661
18662Note: master and slave nodes need to agree upon the number of data fields before message transfer.
18663In RX_RESPONSE case, When PID (header) is received, firmware has the time of one response data byte, to modify CTL1.DATA_NR.</description>
18664                <bitRange>[2:0]</bitRange>
18665                <access>read-write</access>
18666              </field>
18667              <field>
18668                <name>CHECKSUM_ENHANCED</name>
18669                <description>Checksum mode:
18670'0': Classic mode. PID field is NOT included in the checksum calculation.
18671'1': Enhanced mode. PID field is included in the checksum calculation. This mode requires special attention when the master node transmits the header and a (different) slave node transmits the response: the slave node will use the calculated partial checksum over the received PID field as a starting point for the calculation over the to be transmitted data fields.
18672
18673Note: If the frame identifier ID[5:0] is 0x3c or 0x3d, the classic mode will ALWAYS be used for transmission and assumed for reception, independent of the CHECKSUM_ENHANCED value.</description>
18674                <bitRange>[8:8]</bitRange>
18675                <access>read-write</access>
18676              </field>
18677              <field>
18678                <name>FRAME_TIMEOUT</name>
18679                <description>Specifies the maximum allowed length (timeout value) for a frame, frame header or frame response in bit periods. The LIN specification prescribes to set the maximum length to 1.4x the nominal length (Theader_max = 1.4 x Theader_nom and Tresponse_max = 1.4 x Tresponse_nom). The nominal header length Theader_nom is 34 bit periods and the nominal response length Tresponse_nom is 10 * (data_nr + 1) bit periods (data_nr is the number of data fields)
18680
18681Note: the LIN specification specifies the following: 'Tools and tests shall check the Tframe_max (= Theader_max + Tresponse_max). Nodes shall not check this time. The receiving node of the frame shall accept the frame up to the next frame slot (i.e. next break field), even if it is longer then Tframe_max).'</description>
18682                <bitRange>[23:16]</bitRange>
18683                <access>read-write</access>
18684              </field>
18685              <field>
18686                <name>FRAME_TIMEOUT_SEL</name>
18687                <description>Specifies the frame timeout mode:
18688'0': No timeout functionality (default value).
18689'1': Frame mode: detects timeout from the start of break field to checksum field STOP bits (inclusive). The minimum FRAME_TIMEOUT value is 34+20 bit periods (header and a response with 1 data field).
18690'2': Frame header mode: detects timeout from the start of break field to PID field STOP bits (inclusive). The minimum FRAME_TIMEOUT value is 34 bit periods (header).
18691'3': Frame response mode: detects timeout from the PID field STOP bits (exclusive) to checksum field STOP bits (the response space is included in the frame response). The minimum FRAME_TIMEOUT value is 20 bit periods (response with 1 data field).</description>
18692                <bitRange>[25:24]</bitRange>
18693                <access>read-write</access>
18694              </field>
18695            </fields>
18696          </register>
18697          <register>
18698            <name>STATUS</name>
18699            <description>Status</description>
18700            <addressOffset>0x8</addressOffset>
18701            <size>32</size>
18702            <access>read-only</access>
18703            <resetValue>0x0</resetValue>
18704            <resetMask>0x1F03333F</resetMask>
18705            <fields>
18706              <field>
18707                <name>DATA_IDX</name>
18708                <description>Number of transferred data and checksum fields in the response (also acts as an index/address into response data field and checksum field registers (DATA0, DATA1, PID_CHECKSUM)) :
18709'0': No data fields transferred.
18710'1': Data field 1 transferred.
18711...
18712'7': Data fields 1, 2, 3, ... and 7 transferred.
18713'8':  Data fields 1, 2, 3, ... and 8 transferred.
18714'9': Data fields 1, 2, 3, ..., 8 and checksum field transferred.
18715'10'-'15': Unused.
18716
18717Set to '0' on the start of a TX_HEADER or RX_HEADER command.</description>
18718                <bitRange>[3:0]</bitRange>
18719                <access>read-only</access>
18720              </field>
18721              <field>
18722                <name>HEADER_RESPONSE</name>
18723                <description>Frame header / response identifier (only valid when TX_BUSY or RX_BUSY is '1'):
18724'0': Frame header being transferred.
18725'1': Frame response being transferred.</description>
18726                <bitRange>[4:4]</bitRange>
18727                <access>read-only</access>
18728              </field>
18729              <field>
18730                <name>RX_DATA0_FRAME_ERROR</name>
18731                <description>Frame response, first data field frame error. HW sets this field to '1'  when the received STOP bits of the first response data field have an unexpected value (only after a RX_HEADER command), and this data byte is 0x00. HW clears this field to '0' at the falling edge of SYNC start bit (after INTR.RX_HEADER_BREAK_WAKEUP_DONE). This field is used together with INTR.RX_RESPONSE_FRAME_ERROR to distinguish 'no response', 'error response' and 'correct response' scenarios.
18732
18733Note: The ongoing message transfer is NOT aborted.</description>
18734                <bitRange>[5:5]</bitRange>
18735                <access>read-only</access>
18736              </field>
18737              <field>
18738                <name>TX_BUSY</name>
18739                <description>Transmitter busy.
18740- Set to '1' on the start of the following commands: TX_HEADER, TX_RESPONSE, TX_WAKEUP.
18741- Set to '0' on successful completion of previous commands or when an error is detected.
18742   In 'TX_HEADER, RX_RESPONSE' case, set to '0' at the start bit falling edge in the first response data byte, after header transmission</description>
18743                <bitRange>[8:8]</bitRange>
18744                <access>read-only</access>
18745              </field>
18746              <field>
18747                <name>RX_BUSY</name>
18748                <description>Receiver busy.
18749- Set to '1' on the start of the following commands: RX_HEADER, RX_RESPONSE.
18750   in RX_HEADER case, set at Break filed rising edge.
18751   in RX_RESPONSE case, set at the start bit falling edge in the first response data byte.
18752
18753- Set to '0' on successful completion of previous commands or when an error is detected.</description>
18754                <bitRange>[9:9]</bitRange>
18755                <access>read-only</access>
18756              </field>
18757              <field>
18758                <name>TX_DONE</name>
18759                <description>Transmitter done:
18760- Set to '0' on the start of a new command.
18761- Set to '1' on successful completion of the following command sequences (if CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble):
18762- TX_HEADER.
18763- TX_HEADER, TX_RESPONSE.
18764- RX_HEADER, TX_RESPONSE.
18765- TX_WAKEUP.</description>
18766                <bitRange>[12:12]</bitRange>
18767                <access>read-only</access>
18768              </field>
18769              <field>
18770                <name>RX_DONE</name>
18771                <description>Receiver done:
18772- Set to '0' on the start of a new command.
18773- Set to '1' on successful completion of the following command sequences (if CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble):
18774- RX_HEADER, RX_RESPONSE.
18775- TX_HEADER, RX_RESPONSE.</description>
18776                <bitRange>[13:13]</bitRange>
18777                <access>read-only</access>
18778              </field>
18779              <field>
18780                <name>TX_HEADER_BIT_ERROR</name>
18781                <description>Copy of INTR.TX_HEADER_BIT_ERROR.</description>
18782                <bitRange>[16:16]</bitRange>
18783                <access>read-only</access>
18784              </field>
18785              <field>
18786                <name>TX_RESPONSE_BIT_ERROR</name>
18787                <description>Copy of INTR.TX_RESPONSE_BIT_ERROR.</description>
18788                <bitRange>[17:17]</bitRange>
18789                <access>read-only</access>
18790              </field>
18791              <field>
18792                <name>RX_HEADER_FRAME_ERROR</name>
18793                <description>Copy of INTR.RX_HEADER_FRAME_ERROR.</description>
18794                <bitRange>[24:24]</bitRange>
18795                <access>read-only</access>
18796              </field>
18797              <field>
18798                <name>RX_HEADER_SYNC_ERROR</name>
18799                <description>Copy of INTR.RX_HEADER_SYNC_ERROR.</description>
18800                <bitRange>[25:25]</bitRange>
18801                <access>read-only</access>
18802              </field>
18803              <field>
18804                <name>RX_HEADER_PARITY_ERROR</name>
18805                <description>Copy of INTR.RX_HEADER_PARITY_ERROR.</description>
18806                <bitRange>[26:26]</bitRange>
18807                <access>read-only</access>
18808              </field>
18809              <field>
18810                <name>RX_RESPONSE_FRAME_ERROR</name>
18811                <description>Copy of INTR.RX_RESPONSE_FRAME_ERROR.</description>
18812                <bitRange>[27:27]</bitRange>
18813                <access>read-only</access>
18814              </field>
18815              <field>
18816                <name>RX_RESPONSE_CHECKSUM_ERROR</name>
18817                <description>Copy of INTR.RX_RESPONSE_CHECKSUM_ERROR.</description>
18818                <bitRange>[28:28]</bitRange>
18819                <access>read-only</access>
18820              </field>
18821            </fields>
18822          </register>
18823          <register>
18824            <name>CMD</name>
18825            <description>Command</description>
18826            <addressOffset>0x10</addressOffset>
18827            <size>32</size>
18828            <access>read-write</access>
18829            <resetValue>0x0</resetValue>
18830            <resetMask>0x307</resetMask>
18831            <fields>
18832              <field>
18833                <name>TX_HEADER</name>
18834                <description>SW sets this field to '1' to transmit a header. HW sets this field to '0' on successful completion of ANY of the following legal command sequences (also set to '0' when an error is detected):
18835- TX_HEADER
18836- TX_HEADER, TX_RESPONSE.
18837- TX_HEADER, RX_RESPONSE.
18838- RX_HEADER, TX_RESPONSE.
18839- RX_HEADER, RX_RESPONSE.
18840- TX_WAKEUP.
18841
18842The header is transmitted when the PID field STOP bits are transmitted (INTR.TX_HEADER_DONE).
18843
18844HW sets this field to '1', when the 'tr_cmd_tx_header' input trigger is activated. This allows for time triggered LIN message transfer. HW driven time triggered transfer eliminates the jitter that is typically associated with SW driven transfer.
18845
18846In UART mode, a single data field (DATA0.DATA1) is transmitted.</description>
18847                <bitRange>[0:0]</bitRange>
18848                <access>read-write</access>
18849              </field>
18850              <field>
18851                <name>TX_RESPONSE</name>
18852                <description>SW sets this field to '1' to transmit a response. HW sets this field to '0' on successful completion of ANY of the legal command sequences (also set to '0' when an error is detected).
18853
18854The response is transmitted when the checksum field STOP bits are transmitted (INTR.TX_RESPONSE_DONE).</description>
18855                <bitRange>[1:1]</bitRange>
18856                <access>read-write</access>
18857              </field>
18858              <field>
18859                <name>TX_WAKEUP</name>
18860                <description>SW sets this field to '1' to transmit a wakeup signal. HW sets this field to '0' on successful completion of ANY of the legal command sequences (also set to '0' when an error is detected).
18861
18862The command generates CTL.BREAK_WAKEUP_LENGTH bit periods in the dominant state (low/'0') and transitions to the recessive state (high/'1') (INTR.TX_WAKEUP_DONE).</description>
18863                <bitRange>[2:2]</bitRange>
18864                <access>read-write</access>
18865              </field>
18866              <field>
18867                <name>RX_HEADER</name>
18868                <description>SW sets this field to '1' to receive a header. HW sets this field to '0' on successful completion of the ANY of the legal command sequences (NOT set to '0' when an error is detected in LIN mode).
18869
18870The header is received when the PID field STOP bits are received (INTR.RX_HEADER_DONE).
18871
18872Typically, a slave node SW sets both RX_HEADER and RX_RESPONSE to '1', anticipating a transfer of a response from the master node to this slave node. After receipt of the header PID field (INTR.RX_HEADER_PID_DONE is activated), the slave node may decide to set TX_RESPONSE to '1' (which has a higher priority than RX_RESPONSE) to transmit a response.
18873
18874the Break detection is performed regardless of CMD.RX_HEADER.
18875INTR.RX_BREAK_WAKEUP_DONE will trigger at LIN_RX rising edge, when the low pulse meet CTL0.BREAK_WAKEUP_LENGTH. when Break is detected, HW check CMD.RX_HEADER before entering SYNC byte processing state. when RX_HEADER is cleared, SW has at least 11 bit times to set RX_HEADER again, before next Break is detected (RX_BREAK_WAKEUP_DONE). in this case, there is no gap, Break will never be missed.
18876
18877
18878In UART mode, a single data field in received (in DATA0.DATA1). HW set this field to '0' when the data field is received, or when an error is detected.</description>
18879                <bitRange>[8:8]</bitRange>
18880                <access>read-write</access>
18881              </field>
18882              <field>
18883                <name>RX_RESPONSE</name>
18884                <description>SW sets this field to '1' to receive a response. HW sets this field to '0' on successful completion of ANY of the legal command sequences (NOT set to '0' when an error is detected).
18885
18886The response is received when the checksum field STOP bits are received (INTR.RX_RESPONSE_DONE).</description>
18887                <bitRange>[9:9]</bitRange>
18888                <access>read-write</access>
18889              </field>
18890            </fields>
18891          </register>
18892          <register>
18893            <name>TX_RX_STATUS</name>
18894            <description>TX/RX status</description>
18895            <addressOffset>0x60</addressOffset>
18896            <size>32</size>
18897            <access>read-write</access>
18898            <resetValue>0x5000000</resetValue>
18899            <resetMask>0x5000000</resetMask>
18900            <fields>
18901              <field>
18902                <name>SYNC_COUNTER</name>
18903                <description>Synchronization counter in LIN channel clock periods. After the receipt of a synchronization field, this fields reflects the duration of the synchronization field. Ideally, SYNC_COUNTER = 8*16 = 128 (the synchronization fields consists of eight bit period of 16 LIN channel clock periods each).
18904- If SYNC_COUNTER is less than 128, the LIN channel clock is too slow and the PERI/PCLK divider value should be decreased.
18905- If SYNC_COUNTER is greater than 128, the LIN channel clock is too fast and the PERI/PCLK divider value should be increased.
18906
18907The biggest master-slave clock discrepancy occurs when the master is slow and the slave is fast or vice versa. At a 0.5 percent master inaccuracy and a 14 percent slave inaccuracy, this results in the extreme synchronization values of (.86 * 128) / 1.005 = 109.5 and (1.14 *128) / 0.995 = 146.6. We add a little margin for a valid range of [106, 152].
18908
18909Note: Only slave nodes with imprecise clocks require clock resynchronization. Master and slave nodes with precise clocks do NOT require clock resynchronization.</description>
18910                <bitRange>[7:0]</bitRange>
18911                <access>read-only</access>
18912              </field>
18913              <field>
18914                <name>TX_IN</name>
18915                <description>LIN transmitter input ('tx_in', 'lin_tx_in' in functional mode). TX_IN and RX_IN can be used to determine a wakeup source. Note that wakeup source detection relies on the external transceiver functionality.</description>
18916                <bitRange>[16:16]</bitRange>
18917                <access>read-only</access>
18918              </field>
18919              <field>
18920                <name>RX_IN</name>
18921                <description>LIN receiver input ('rx_in', 'lin_rx_in' in functional mode).</description>
18922                <bitRange>[17:17]</bitRange>
18923                <access>read-only</access>
18924              </field>
18925              <field>
18926                <name>TX_OUT</name>
18927                <description>LIN transmitter output ('tx_out', 'lin_tx_out').</description>
18928                <bitRange>[24:24]</bitRange>
18929                <access>read-only</access>
18930              </field>
18931              <field>
18932                <name>EN_OUT</name>
18933                <description>LIN transceiver enable ('en_out', 'lin_en_out'). This field controls the enable (or low active sleep enable) of the external transceiver:
18934'0': Disabled.
18935'1': Enabled.
18936
18937If CTL.AUTO_EN is '0', SW controls this field to enable the external transceiver. If CTL.AUTO_EN is '1', HW controls this field to enable the external transceiver:
18938- Before a legal command sequence, HW sets this field to '1', if it is '0'. The start of the command sequence is effectively postponed by a 4-bit period preamble.
18939- After a legal command sequence, HW clears this field to '0'. The end of the command sequence is effectively postponed by a 4-bit period postamble.
18940
18941Note: external transceivers require a 'power up' or 'power down' period of 1 or 2 bit periods, so a 4-bit period suffices for all known transceivers.</description>
18942                <bitRange>[26:26]</bitRange>
18943                <access>read-write</access>
18944              </field>
18945            </fields>
18946          </register>
18947          <register>
18948            <name>PID_CHECKSUM</name>
18949            <description>PID and checksum</description>
18950            <addressOffset>0x80</addressOffset>
18951            <size>32</size>
18952            <access>read-write</access>
18953            <resetValue>0x0</resetValue>
18954            <resetMask>0x0</resetMask>
18955            <fields>
18956              <field>
18957                <name>PID</name>
18958                <description>Header protected identifier (PID).
18959- Bits 5 down to 0: frame identifier ID[5:0].
18960Frame identifier 0x3c is for a 'master request' frame, 0x3d is for a 'slave response' frame, 0x3e and 0x3f are for future LIN enhancements. Frame identifier ID[5:4] is optionally used for length control; i.e. specifies the number of response data fields.
18961- Bits 1 down to 0: parity bits P[1] and P[0].
18962  - P[1] = ! (ID[5] ^ ID[4] ^ ID[3] ^ ID[1])
18963  - P[0] = (ID[4] ^ ID[2] ^ ID[1] ^ ID[0])
18964
18965Transmission: To be transmitted PID field. SW needs to calculate the PID field parity bits P[1] and P[0].
18966
18967Reception: Received PID field. Slave node SW uses the PID field to determine how to handle the response for a received frame header: TX_RESPONSE or  RX_RESPONSE.</description>
18968                <bitRange>[7:0]</bitRange>
18969                <access>read-write</access>
18970              </field>
18971              <field>
18972                <name>CHECKSUM</name>
18973                <description>Checksum.
18974
18975Transmission: HW calculated checksum (SW does not need to calculate the checksum) over the transmitted PID field (optional per CTL.CHECKSUM_ENHANCED) and data fields.
18976
18977Reception: Received checksum. Note that in case of a RX_CHECKSUM_ERROR, SW can use the received PID field and the  received data fields to calculate the correct checksum value.</description>
18978                <bitRange>[15:8]</bitRange>
18979                <access>read-only</access>
18980              </field>
18981            </fields>
18982          </register>
18983          <register>
18984            <name>DATA0</name>
18985            <description>Response data 0</description>
18986            <addressOffset>0x84</addressOffset>
18987            <size>32</size>
18988            <access>read-write</access>
18989            <resetValue>0x0</resetValue>
18990            <resetMask>0x0</resetMask>
18991            <fields>
18992              <field>
18993                <name>DATA1</name>
18994                <description>Data field 1.
18995
18996Transmission: To be transmitted data field. SW provides data field.
18997
18998Reception: Received data field. SW uses the data field.</description>
18999                <bitRange>[7:0]</bitRange>
19000                <access>read-write</access>
19001              </field>
19002              <field>
19003                <name>DATA2</name>
19004                <description>Data field 2.</description>
19005                <bitRange>[15:8]</bitRange>
19006                <access>read-write</access>
19007              </field>
19008              <field>
19009                <name>DATA3</name>
19010                <description>Data field 3.</description>
19011                <bitRange>[23:16]</bitRange>
19012                <access>read-write</access>
19013              </field>
19014              <field>
19015                <name>DATA4</name>
19016                <description>Data field 4.</description>
19017                <bitRange>[31:24]</bitRange>
19018                <access>read-write</access>
19019              </field>
19020            </fields>
19021          </register>
19022          <register>
19023            <name>DATA1</name>
19024            <description>Response data 1</description>
19025            <addressOffset>0x88</addressOffset>
19026            <size>32</size>
19027            <access>read-write</access>
19028            <resetValue>0x0</resetValue>
19029            <resetMask>0x0</resetMask>
19030            <fields>
19031              <field>
19032                <name>DATA5</name>
19033                <description>Data field 5.</description>
19034                <bitRange>[7:0]</bitRange>
19035                <access>read-write</access>
19036              </field>
19037              <field>
19038                <name>DATA6</name>
19039                <description>Data field 6.</description>
19040                <bitRange>[15:8]</bitRange>
19041                <access>read-write</access>
19042              </field>
19043              <field>
19044                <name>DATA7</name>
19045                <description>Data field 7.</description>
19046                <bitRange>[23:16]</bitRange>
19047                <access>read-write</access>
19048              </field>
19049              <field>
19050                <name>DATA8</name>
19051                <description>Data field 8.</description>
19052                <bitRange>[31:24]</bitRange>
19053                <access>read-write</access>
19054              </field>
19055            </fields>
19056          </register>
19057          <register>
19058            <name>INTR</name>
19059            <description>Interrupt</description>
19060            <addressOffset>0xC0</addressOffset>
19061            <size>32</size>
19062            <access>read-write</access>
19063            <resetValue>0x0</resetValue>
19064            <resetMask>0x1F036F07</resetMask>
19065            <fields>
19066              <field>
19067                <name>TX_HEADER_DONE</name>
19068                <description>HW sets this field to '1', when a frame header (break field, synchronization field and PID field) is transmitted (the CMD.TX_HEADER is completed). Specifically:
19069- When followed by CMD.TX_RESPONSE or CMD.RX_RESPONSE, this field is set to '1' after completion of the frame header transfer.
19070- When not followed by a response command, this field is set to '1' after completion of the frame header transfer. If CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble.
19071
19072Note: used in UART mode.</description>
19073                <bitRange>[0:0]</bitRange>
19074                <access>read-write</access>
19075              </field>
19076              <field>
19077                <name>TX_RESPONSE_DONE</name>
19078                <description>HW sets this field to '1', when a frame response (data fields and checksum field) is transmitted (the CMD.TX_RESPONSE is completed). If CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble.</description>
19079                <bitRange>[1:1]</bitRange>
19080                <access>read-write</access>
19081              </field>
19082              <field>
19083                <name>TX_WAKEUP_DONE</name>
19084                <description>HW sets this field to '1', when a wakeup signal is transmitted (per CTL.BREAK_WAKEUP_LENGTH). This cause is activated on a transition from dominant/'0' state to recessive/'1' state; i.e. at the end of the wakeup signal.</description>
19085                <bitRange>[2:2]</bitRange>
19086                <access>read-write</access>
19087              </field>
19088              <field>
19089                <name>RX_HEADER_DONE</name>
19090                <description>HW sets this field to '1', when a frame header (break field, synchronization field and PID field) is received (the CMD.RX_HEADER is completed). Specifically:
19091- When followed by CMD.TX_RESPONSE or CMD.RX_RESPONSE, this field is set to '1' after completion of the frame header transfer.
19092- When not followed by a response command, this field is set to '1' after completion of the frame header transfer. If CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble.
19093
19094Note: used in UART mode.</description>
19095                <bitRange>[8:8]</bitRange>
19096                <access>read-write</access>
19097              </field>
19098              <field>
19099                <name>RX_RESPONSE_DONE</name>
19100                <description>HW sets this field to '1', when a frame response (data fields and checksum field) is received (the CMD.RX_RESPONSE is completed). If CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble.
19101
19102Note: activation implies that RX_RESPONSE_FRAME_ERROR and RX_RESPONSE_CHECKSUM_ERROR are not activated during response reception</description>
19103                <bitRange>[9:9]</bitRange>
19104                <access>read-write</access>
19105              </field>
19106              <field>
19107                <name>RX_BREAK_WAKEUP_DONE</name>
19108                <description>HW sets this field to '1', when a break or wakeup signal is received (per CTL.BREAK_WAKEUP_LENGTH). This cause is activated on a transition from dominant/'0' state to recessive/'1' state; i.e. at the end of the wakeup signal.
19109
19110The break or wakeup detection is always enabled, regardless of CMD register setting.</description>
19111                <bitRange>[10:10]</bitRange>
19112                <access>read-write</access>
19113              </field>
19114              <field>
19115                <name>RX_HEADER_SYNC_DONE</name>
19116                <description>HW sets this field to '1', when a synchronization field is received (including trailing STOP bits).</description>
19117                <bitRange>[11:11]</bitRange>
19118                <access>read-write</access>
19119              </field>
19120              <field>
19121                <name>RX_NOISE_DETECT</name>
19122                <description>HW sets this field to '1', when isolated '0' or '1' 'in_rx_in' values are observed or when during sampling the last three 'lin_rx_in' values do NOT all have the same value. This mismatch is an indication of noise on the LIN line.
19123
19124Note: The ongoing frame transfer is NOT aborted.
19125
19126Note: Used in UART mode.</description>
19127                <bitRange>[13:13]</bitRange>
19128                <access>read-write</access>
19129              </field>
19130              <field>
19131                <name>TIMEOUT</name>
19132                <description>HW sets this field to '1', when a frame, frame header or frame response timeout is detected (per CTL.FRAME_TIMEOUT_SEL).
19133
19134Note: The ongoing frame transfer is NOT aborted.</description>
19135                <bitRange>[14:14]</bitRange>
19136                <access>read-write</access>
19137              </field>
19138              <field>
19139                <name>TX_HEADER_BIT_ERROR</name>
19140                <description>HW sets this field to '1', when a transmitted 'lin_tx_out' value does NOT match a received 'lin_rx_in' value (during header transmission). This specific test allows for delay through the external transceiver. This mismatch is an indication of bus collisions on the LIN line.
19141
19142The match is performed for the Wakeup, Break, SYNC and the PID fields (for the START bit, data Byte and STOP bit).
19143
19144Note: When CTL.BIT_ERROR_IGNORE is '0', the ongoing message transfer is aborted (INTR.TX_HEADER_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'.
19145
19146Note: Used in UART mode.</description>
19147                <bitRange>[16:16]</bitRange>
19148                <access>read-write</access>
19149              </field>
19150              <field>
19151                <name>TX_RESPONSE_BIT_ERROR</name>
19152                <description>HW sets this field to '1', when a transmitted 'lin_tx_out' value does NOT match a received 'lin_rx_in' value (during response transmission).
19153
19154The match is performed for the data fields and the checksum field (for the START bit, data Byte and STOP bit).
19155
19156Note: When CTL.BIT_ERROR_IGNORE is '0', the ongoing message transfer is aborted (INTR.TX_RESPONSE_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'.</description>
19157                <bitRange>[17:17]</bitRange>
19158                <access>read-write</access>
19159              </field>
19160              <field>
19161                <name>RX_HEADER_FRAME_ERROR</name>
19162                <description>HW sets this field to '1', when the received START or STOP bits have an unexpected value (during header reception).
19163
19164Note: The ongoing message transfer is aborted (INTR.RX_HEADER_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'.
19165
19166Note: Used in UART mode.</description>
19167                <bitRange>[24:24]</bitRange>
19168                <access>read-write</access>
19169              </field>
19170              <field>
19171                <name>RX_HEADER_SYNC_ERROR</name>
19172                <description>HW sets this field to '1', when the received synchronization field is not received within the synchronization counter range [106, 152] (see TX_RX_STATUS.SYNC_COUNTER).
19173
19174Note: The ongoing message transfer is aborted (INTR.RX_HEADER_SYNC_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'.</description>
19175                <bitRange>[25:25]</bitRange>
19176                <access>read-write</access>
19177              </field>
19178              <field>
19179                <name>RX_HEADER_PARITY_ERROR</name>
19180                <description>HW sets this field to '1', when the received PID field has a parity error.
19181
19182Note: The ongoing message transfer is aborted (INTR.RX_PID_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'.
19183
19184+G119 HW sets this field to '1', when the received data field has a parity error (when CTL0.PARITY_EN is '1').</description>
19185                <bitRange>[26:26]</bitRange>
19186                <access>read-write</access>
19187              </field>
19188              <field>
19189                <name>RX_RESPONSE_FRAME_ERROR</name>
19190                <description>HW sets this field to '1', when the received START or STOP bits have an unexpected value (during response reception). HW does NOT use this field for the STOP bits of the first data field after a RX_HEADER command, if the received data byte is 0x00. (STATUS.RX_DATA0_FRAME_ERROR is used instead).
19191
19192Note: The ongoing message transfer is aborted (INTR.RX_RESPONSE_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'.</description>
19193                <bitRange>[27:27]</bitRange>
19194                <access>read-write</access>
19195              </field>
19196              <field>
19197                <name>RX_RESPONSE_CHECKSUM_ERROR</name>
19198                <description>HW sets this field to '1', when the calculated checksum over the received PID and data fields is not the same as the received checksum.
19199
19200Note: The ongoing message transfer is aborted (INTR.RX_RESPONSE_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'.</description>
19201                <bitRange>[28:28]</bitRange>
19202                <access>read-write</access>
19203              </field>
19204            </fields>
19205          </register>
19206          <register>
19207            <name>INTR_SET</name>
19208            <description>Interrupt set</description>
19209            <addressOffset>0xC4</addressOffset>
19210            <size>32</size>
19211            <access>read-write</access>
19212            <resetValue>0x0</resetValue>
19213            <resetMask>0x1F036F07</resetMask>
19214            <fields>
19215              <field>
19216                <name>TX_HEADER_DONE</name>
19217                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
19218                <bitRange>[0:0]</bitRange>
19219                <access>read-write</access>
19220              </field>
19221              <field>
19222                <name>TX_RESPONSE_DONE</name>
19223                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
19224                <bitRange>[1:1]</bitRange>
19225                <access>read-write</access>
19226              </field>
19227              <field>
19228                <name>TX_WAKEUP_DONE</name>
19229                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
19230                <bitRange>[2:2]</bitRange>
19231                <access>read-write</access>
19232              </field>
19233              <field>
19234                <name>RX_HEADER_DONE</name>
19235                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
19236                <bitRange>[8:8]</bitRange>
19237                <access>read-write</access>
19238              </field>
19239              <field>
19240                <name>RX_RESPONSE_DONE</name>
19241                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
19242                <bitRange>[9:9]</bitRange>
19243                <access>read-write</access>
19244              </field>
19245              <field>
19246                <name>RX_BREAK_WAKEUP_DONE</name>
19247                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
19248                <bitRange>[10:10]</bitRange>
19249                <access>read-write</access>
19250              </field>
19251              <field>
19252                <name>RX_HEADER_SYNC_DONE</name>
19253                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
19254                <bitRange>[11:11]</bitRange>
19255                <access>read-write</access>
19256              </field>
19257              <field>
19258                <name>RX_NOISE_DETECT</name>
19259                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
19260                <bitRange>[13:13]</bitRange>
19261                <access>read-write</access>
19262              </field>
19263              <field>
19264                <name>TIMEOUT</name>
19265                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
19266                <bitRange>[14:14]</bitRange>
19267                <access>read-write</access>
19268              </field>
19269              <field>
19270                <name>TX_HEADER_BIT_ERROR</name>
19271                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
19272                <bitRange>[16:16]</bitRange>
19273                <access>read-write</access>
19274              </field>
19275              <field>
19276                <name>TX_RESPONSE_BIT_ERROR</name>
19277                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
19278                <bitRange>[17:17]</bitRange>
19279                <access>read-write</access>
19280              </field>
19281              <field>
19282                <name>RX_HEADER_FRAME_ERROR</name>
19283                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
19284                <bitRange>[24:24]</bitRange>
19285                <access>read-write</access>
19286              </field>
19287              <field>
19288                <name>RX_HEADER_SYNC_ERROR</name>
19289                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
19290                <bitRange>[25:25]</bitRange>
19291                <access>read-write</access>
19292              </field>
19293              <field>
19294                <name>RX_HEADER_PARITY_ERROR</name>
19295                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
19296                <bitRange>[26:26]</bitRange>
19297                <access>read-write</access>
19298              </field>
19299              <field>
19300                <name>RX_RESPONSE_FRAME_ERROR</name>
19301                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
19302                <bitRange>[27:27]</bitRange>
19303                <access>read-write</access>
19304              </field>
19305              <field>
19306                <name>RX_RESPONSE_CHECKSUM_ERROR</name>
19307                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
19308                <bitRange>[28:28]</bitRange>
19309                <access>read-write</access>
19310              </field>
19311            </fields>
19312          </register>
19313          <register>
19314            <name>INTR_MASK</name>
19315            <description>Interrupt mask</description>
19316            <addressOffset>0xC8</addressOffset>
19317            <size>32</size>
19318            <access>read-write</access>
19319            <resetValue>0x0</resetValue>
19320            <resetMask>0x1F036F07</resetMask>
19321            <fields>
19322              <field>
19323                <name>TX_HEADER_DONE</name>
19324                <description>Mask for corresponding field in INTR register.</description>
19325                <bitRange>[0:0]</bitRange>
19326                <access>read-write</access>
19327              </field>
19328              <field>
19329                <name>TX_RESPONSE_DONE</name>
19330                <description>Mask for corresponding field in INTR register.</description>
19331                <bitRange>[1:1]</bitRange>
19332                <access>read-write</access>
19333              </field>
19334              <field>
19335                <name>TX_WAKEUP_DONE</name>
19336                <description>Mask for corresponding field in INTR register.</description>
19337                <bitRange>[2:2]</bitRange>
19338                <access>read-write</access>
19339              </field>
19340              <field>
19341                <name>RX_HEADER_DONE</name>
19342                <description>Mask for corresponding field in INTR register.</description>
19343                <bitRange>[8:8]</bitRange>
19344                <access>read-write</access>
19345              </field>
19346              <field>
19347                <name>RX_RESPONSE_DONE</name>
19348                <description>Mask for corresponding field in INTR register.</description>
19349                <bitRange>[9:9]</bitRange>
19350                <access>read-write</access>
19351              </field>
19352              <field>
19353                <name>RX_BREAK_WAKEUP_DONE</name>
19354                <description>Mask for corresponding field in INTR register.</description>
19355                <bitRange>[10:10]</bitRange>
19356                <access>read-write</access>
19357              </field>
19358              <field>
19359                <name>RX_HEADER_SYNC_DONE</name>
19360                <description>Mask for corresponding field in INTR register.</description>
19361                <bitRange>[11:11]</bitRange>
19362                <access>read-write</access>
19363              </field>
19364              <field>
19365                <name>RX_NOISE_DETECT</name>
19366                <description>Mask for corresponding field in INTR register.</description>
19367                <bitRange>[13:13]</bitRange>
19368                <access>read-write</access>
19369              </field>
19370              <field>
19371                <name>TIMEOUT</name>
19372                <description>Mask for corresponding field in INTR register.</description>
19373                <bitRange>[14:14]</bitRange>
19374                <access>read-write</access>
19375              </field>
19376              <field>
19377                <name>TX_HEADER_BIT_ERROR</name>
19378                <description>Mask for corresponding field in INTR register.</description>
19379                <bitRange>[16:16]</bitRange>
19380                <access>read-write</access>
19381              </field>
19382              <field>
19383                <name>TX_RESPONSE_BIT_ERROR</name>
19384                <description>Mask for corresponding field in INTR register.</description>
19385                <bitRange>[17:17]</bitRange>
19386                <access>read-write</access>
19387              </field>
19388              <field>
19389                <name>RX_HEADER_FRAME_ERROR</name>
19390                <description>Mask for corresponding field in INTR register.</description>
19391                <bitRange>[24:24]</bitRange>
19392                <access>read-write</access>
19393              </field>
19394              <field>
19395                <name>RX_HEADER_SYNC_ERROR</name>
19396                <description>Mask for corresponding field in INTR register.</description>
19397                <bitRange>[25:25]</bitRange>
19398                <access>read-write</access>
19399              </field>
19400              <field>
19401                <name>RX_HEADER_PARITY_ERROR</name>
19402                <description>Mask for corresponding field in INTR register.</description>
19403                <bitRange>[26:26]</bitRange>
19404                <access>read-write</access>
19405              </field>
19406              <field>
19407                <name>RX_RESPONSE_FRAME_ERROR</name>
19408                <description>Mask for corresponding field in INTR register.</description>
19409                <bitRange>[27:27]</bitRange>
19410                <access>read-write</access>
19411              </field>
19412              <field>
19413                <name>RX_RESPONSE_CHECKSUM_ERROR</name>
19414                <description>Mask for corresponding field in INTR register.</description>
19415                <bitRange>[28:28]</bitRange>
19416                <access>read-write</access>
19417              </field>
19418            </fields>
19419          </register>
19420          <register>
19421            <name>INTR_MASKED</name>
19422            <description>Interrupt masked</description>
19423            <addressOffset>0xCC</addressOffset>
19424            <size>32</size>
19425            <access>read-only</access>
19426            <resetValue>0x0</resetValue>
19427            <resetMask>0x1F036F07</resetMask>
19428            <fields>
19429              <field>
19430                <name>TX_HEADER_DONE</name>
19431                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
19432                <bitRange>[0:0]</bitRange>
19433                <access>read-only</access>
19434              </field>
19435              <field>
19436                <name>TX_RESPONSE_DONE</name>
19437                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
19438                <bitRange>[1:1]</bitRange>
19439                <access>read-only</access>
19440              </field>
19441              <field>
19442                <name>TX_WAKEUP_DONE</name>
19443                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
19444                <bitRange>[2:2]</bitRange>
19445                <access>read-only</access>
19446              </field>
19447              <field>
19448                <name>RX_HEADER_DONE</name>
19449                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
19450                <bitRange>[8:8]</bitRange>
19451                <access>read-only</access>
19452              </field>
19453              <field>
19454                <name>RX_RESPONSE_DONE</name>
19455                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
19456                <bitRange>[9:9]</bitRange>
19457                <access>read-only</access>
19458              </field>
19459              <field>
19460                <name>RX_BREAK_WAKEUP_DONE</name>
19461                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
19462                <bitRange>[10:10]</bitRange>
19463                <access>read-only</access>
19464              </field>
19465              <field>
19466                <name>RX_HEADER_SYNC_DONE</name>
19467                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
19468                <bitRange>[11:11]</bitRange>
19469                <access>read-only</access>
19470              </field>
19471              <field>
19472                <name>RX_NOISE_DETECT</name>
19473                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
19474                <bitRange>[13:13]</bitRange>
19475                <access>read-only</access>
19476              </field>
19477              <field>
19478                <name>TIMEOUT</name>
19479                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
19480                <bitRange>[14:14]</bitRange>
19481                <access>read-only</access>
19482              </field>
19483              <field>
19484                <name>TX_HEADER_BIT_ERROR</name>
19485                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
19486                <bitRange>[16:16]</bitRange>
19487                <access>read-only</access>
19488              </field>
19489              <field>
19490                <name>TX_RESPONSE_BIT_ERROR</name>
19491                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
19492                <bitRange>[17:17]</bitRange>
19493                <access>read-only</access>
19494              </field>
19495              <field>
19496                <name>RX_HEADER_FRAME_ERROR</name>
19497                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
19498                <bitRange>[24:24]</bitRange>
19499                <access>read-only</access>
19500              </field>
19501              <field>
19502                <name>RX_HEADER_SYNC_ERROR</name>
19503                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
19504                <bitRange>[25:25]</bitRange>
19505                <access>read-only</access>
19506              </field>
19507              <field>
19508                <name>RX_HEADER_PARITY_ERROR</name>
19509                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
19510                <bitRange>[26:26]</bitRange>
19511                <access>read-only</access>
19512              </field>
19513              <field>
19514                <name>RX_RESPONSE_FRAME_ERROR</name>
19515                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
19516                <bitRange>[27:27]</bitRange>
19517                <access>read-only</access>
19518              </field>
19519              <field>
19520                <name>RX_RESPONSE_CHECKSUM_ERROR</name>
19521                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
19522                <bitRange>[28:28]</bitRange>
19523                <access>read-only</access>
19524              </field>
19525            </fields>
19526          </register>
19527        </cluster>
19528      </registers>
19529    </peripheral>
19530    <peripheral>
19531      <name>CANFD0</name>
19532      <description>CAN Controller</description>
19533      <headerStructName>CANFD</headerStructName>
19534      <baseAddress>0x40440000</baseAddress>
19535      <addressBlock>
19536        <offset>0</offset>
19537        <size>131072</size>
19538        <usage>registers</usage>
19539      </addressBlock>
19540      <registers>
19541        <cluster>
19542          <name>CH</name>
19543          <description>FIFO wrapper around M_TTCAN 3PIP, to enable DMA</description>
19544          <addressOffset>0x00000000</addressOffset>
19545          <cluster>
19546            <name>M_TTCAN</name>
19547            <description>TTCAN 3PIP, includes FD</description>
19548            <addressOffset>0x00000000</addressOffset>
19549            <register>
19550              <name>CREL</name>
19551              <description>Core Release Register</description>
19552              <addressOffset>0x0</addressOffset>
19553              <size>32</size>
19554              <access>read-only</access>
19555              <resetValue>0x32380609</resetValue>
19556              <resetMask>0xFFFFFFFF</resetMask>
19557              <fields>
19558                <field>
19559                  <name>DAY</name>
19560                  <description>Time Stamp Day
19561Two digits, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis.</description>
19562                  <bitRange>[7:0]</bitRange>
19563                  <access>read-only</access>
19564                </field>
19565                <field>
19566                  <name>MON</name>
19567                  <description>Time Stamp Month
19568Two digits, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis.</description>
19569                  <bitRange>[15:8]</bitRange>
19570                  <access>read-only</access>
19571                </field>
19572                <field>
19573                  <name>YEAR</name>
19574                  <description>Time Stamp Year
19575One digit, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis.</description>
19576                  <bitRange>[19:16]</bitRange>
19577                  <access>read-only</access>
19578                </field>
19579                <field>
19580                  <name>SUBSTEP</name>
19581                  <description>Sub-step of Core Release
19582One digit, BCD-coded.</description>
19583                  <bitRange>[23:20]</bitRange>
19584                  <access>read-only</access>
19585                </field>
19586                <field>
19587                  <name>STEP</name>
19588                  <description>Step of Core Release
19589One digit, BCD-coded.</description>
19590                  <bitRange>[27:24]</bitRange>
19591                  <access>read-only</access>
19592                </field>
19593                <field>
19594                  <name>REL</name>
19595                  <description>Core Release
19596One digit, BCD-coded.</description>
19597                  <bitRange>[31:28]</bitRange>
19598                  <access>read-only</access>
19599                </field>
19600              </fields>
19601            </register>
19602            <register>
19603              <name>ENDN</name>
19604              <description>Endian Register</description>
19605              <addressOffset>0x4</addressOffset>
19606              <size>32</size>
19607              <access>read-only</access>
19608              <resetValue>0x87654321</resetValue>
19609              <resetMask>0xFFFFFFFF</resetMask>
19610              <fields>
19611                <field>
19612                  <name>ETV</name>
19613                  <description>Endianness Test Value
19614The endianness test value is 0x87654321.</description>
19615                  <bitRange>[31:0]</bitRange>
19616                  <access>read-only</access>
19617                </field>
19618              </fields>
19619            </register>
19620            <register>
19621              <name>DBTP</name>
19622              <description>Data Bit Timing &amp; Prescaler Register</description>
19623              <addressOffset>0xC</addressOffset>
19624              <size>32</size>
19625              <access>read-write</access>
19626              <resetValue>0xA33</resetValue>
19627              <resetMask>0x9F1FFF</resetMask>
19628              <fields>
19629                <field>
19630                  <name>DSJW</name>
19631                  <description>Data (Re)Synchronization Jump Width
196320x0-0xF Valid values are 0 to 15. The actual interpretation by the hardware of this value is
19633such that one more than the value programmed here is used.</description>
19634                  <bitRange>[3:0]</bitRange>
19635                  <access>read-write</access>
19636                </field>
19637                <field>
19638                  <name>DTSEG2</name>
19639                  <description>Data time segment after sample point
196400x0-0xF Valid values are 0 to 15. The actual interpretation by the hardware of this value is
19641such that one more than the programmed value is used.</description>
19642                  <bitRange>[7:4]</bitRange>
19643                  <access>read-write</access>
19644                </field>
19645                <field>
19646                  <name>DTSEG1</name>
19647                  <description>Data time segment before sample point
196480x00-0x1F Valid values are 0 to 31. The actual interpretation by the hardware of this value is
19649such that one more than the programmed value is used.</description>
19650                  <bitRange>[12:8]</bitRange>
19651                  <access>read-write</access>
19652                </field>
19653                <field>
19654                  <name>DBRP</name>
19655                  <description>Data Bit Rate Prescaler
196560x00-0x1F The value by which the oscillator frequency is divided for generating the bit time
19657quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit
19658Rate Prescaler are 0 to 31. The actual interpretation by the hardware of this value is
19659such that one more than the value programmed here is used.</description>
19660                  <bitRange>[20:16]</bitRange>
19661                  <access>read-write</access>
19662                </field>
19663                <field>
19664                  <name>TDC</name>
19665                  <description>Transmitter Delay Compensation
196660= Transmitter Delay Compensation disabled
196671= Transmitter Delay Compensation enabled</description>
19668                  <bitRange>[23:23]</bitRange>
19669                  <access>read-write</access>
19670                </field>
19671              </fields>
19672            </register>
19673            <register>
19674              <name>TEST</name>
19675              <description>Test Register</description>
19676              <addressOffset>0x10</addressOffset>
19677              <size>32</size>
19678              <access>read-write</access>
19679              <resetValue>0x0</resetValue>
19680              <resetMask>0x7F</resetMask>
19681              <fields>
19682                <field>
19683                  <name>TAM</name>
19684                  <description>ASC is not supported by M_TTCAN
19685Test ASC Multiplexer Control
19686Controls output pin m_ttcan_ascm in test mode, ORed with the signal from the FSE
196870= Level at pin m_ttcan_ascm controlled by FSE
196881= Level at pin m_ttcan_ascm = '1'</description>
19689                  <bitRange>[0:0]</bitRange>
19690                  <access>read-write</access>
19691                </field>
19692                <field>
19693                  <name>TAT</name>
19694                  <description>ASC is not supported by M_TTCAN
19695Test ASC Transmit Control
19696Controls output pin m_ttcan_asct in test mode, ORed with the signal from the FSE
196970= Level at pin m_ttcan_asct controlled by FSE
196981= Level at pin m_ttcan_asct = '1'</description>
19699                  <bitRange>[1:1]</bitRange>
19700                  <access>read-write</access>
19701                </field>
19702                <field>
19703                  <name>CAM</name>
19704                  <description>ASC is not supported by M_TTCAN
19705Check ASC Multiplexer Control
19706Monitors level at output pin m_ttcan_ascm.
197070= Output pin m_ttcan_ascm = '0'
197081= Output pin m_ttcan_ascm = '1'</description>
19709                  <bitRange>[2:2]</bitRange>
19710                  <access>read-write</access>
19711                </field>
19712                <field>
19713                  <name>CAT</name>
19714                  <description>ASC is not supported by M_TTCAN
19715Check ASC Transmit Control
19716Monitors level at output pin m_ttcan_asct.
197170= Output pin m_ttcan_asct = '0'</description>
19718                  <bitRange>[3:3]</bitRange>
19719                  <access>read-write</access>
19720                </field>
19721                <field>
19722                  <name>LBCK</name>
19723                  <description>Loop Back Mode
197240= Reset value, Loop Back Mode is disabled
197251= Loop Back Mode is enabled (see Section 3.1.9, Test Modes)</description>
19726                  <bitRange>[4:4]</bitRange>
19727                  <access>read-write</access>
19728                </field>
19729                <field>
19730                  <name>TX</name>
19731                  <description>Control of Transmit Pin
1973200 Reset value, m_ttcan_tx controlled by the CAN Core, updated at the end of the CAN bit time
1973301 Sample Point can be monitored at pin m_ttcan_tx
1973410 Dominant ('0') level at pin m_ttcan_tx
1973511 Recessive ('1') at pin m_ttcan_tx</description>
19736                  <bitRange>[6:5]</bitRange>
19737                  <access>read-write</access>
19738                </field>
19739                <field>
19740                  <name>RX</name>
19741                  <description>Receive Pin
19742Monitors the actual value of pin m_ttcan_rx
197430= The CAN bus is dominant (m_ttcan_rx = '0')
197441= The CAN bus is recessive (m_ttcan_rx = '1')</description>
19745                  <bitRange>[7:7]</bitRange>
19746                  <access>read-only</access>
19747                </field>
19748              </fields>
19749            </register>
19750            <register>
19751              <name>RWD</name>
19752              <description>RAM Watchdog</description>
19753              <addressOffset>0x14</addressOffset>
19754              <size>32</size>
19755              <access>read-write</access>
19756              <resetValue>0x0</resetValue>
19757              <resetMask>0xFFFF</resetMask>
19758              <fields>
19759                <field>
19760                  <name>WDC</name>
19761                  <description>Watchdog Configuration
19762Start value of the Message RAM Watchdog Counter. With the reset value of '00' the counter is
19763disabled.</description>
19764                  <bitRange>[7:0]</bitRange>
19765                  <access>read-write</access>
19766                </field>
19767                <field>
19768                  <name>WDV</name>
19769                  <description>Watchdog Value
19770Actual Message RAM Watchdog Counter Value.</description>
19771                  <bitRange>[15:8]</bitRange>
19772                  <access>read-only</access>
19773                </field>
19774              </fields>
19775            </register>
19776            <register>
19777              <name>CCCR</name>
19778              <description>CC Control Register</description>
19779              <addressOffset>0x18</addressOffset>
19780              <size>32</size>
19781              <access>read-write</access>
19782              <resetValue>0x1</resetValue>
19783              <resetMask>0xF3FF</resetMask>
19784              <fields>
19785                <field>
19786                  <name>INIT</name>
19787                  <description>Initialization
197880= Normal Operation
197891= Initialization is started</description>
19790                  <bitRange>[0:0]</bitRange>
19791                  <access>read-write</access>
19792                </field>
19793                <field>
19794                  <name>CCE</name>
19795                  <description>Configuration Change Enable
197960= The CPU has no write access to the protected configuration registers
197971= The CPU has write access to the protected configuration registers (while CCCR.INIT = '1')</description>
19798                  <bitRange>[1:1]</bitRange>
19799                  <access>read-write</access>
19800                </field>
19801                <field>
19802                  <name>ASM</name>
19803                  <description>Restricted Operation Mode
19804Bit ASM can only be set by the Host when both CCE and INIT are set to '1'. The bit can be reset by
19805the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5.
198060= Normal CAN operation
198071= Restricted Operation Mode active</description>
19808                  <bitRange>[2:2]</bitRange>
19809                  <access>read-write</access>
19810                </field>
19811                <field>
19812                  <name>CSA</name>
19813                  <description>Clock Stop Acknowledge
198140= No clock stop acknowledged
198151= M_TTCAN may be set in power down by stopping m_ttcan_hclk and m_ttcan_cclk</description>
19816                  <bitRange>[3:3]</bitRange>
19817                  <access>read-write</access>
19818                </field>
19819                <field>
19820                  <name>CSR</name>
19821                  <description>Clock Stop Request, not supported by M_TTCAN use CTL.STOP_REQ at the group level instead.
198220= No clock stop is requested
198231= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after
19824all pending transfer requests have been completed and the CAN bus reached idle.</description>
19825                  <bitRange>[4:4]</bitRange>
19826                  <access>read-write</access>
19827                </field>
19828                <field>
19829                  <name>MON_</name>
19830                  <description>Bus Monitoring Mode
19831Bit MON can only be set by the Host when both CCE and INIT are set to '1'. The bit can be reset by
19832the Host at any time.
198330= Bus Monitoring Mode is disabled
198341= Bus Monitoring Mode is enabled</description>
19835                  <bitRange>[5:5]</bitRange>
19836                  <access>read-write</access>
19837                </field>
19838                <field>
19839                  <name>DAR</name>
19840                  <description>Disable Automatic Retransmission
198410= Automatic retransmission of messages not transmitted successfully enabled
198421= Automatic retransmission disabled</description>
19843                  <bitRange>[6:6]</bitRange>
19844                  <access>read-write</access>
19845                </field>
19846                <field>
19847                  <name>TEST</name>
19848                  <description>Test Mode Enable
198490= Normal operation, register TEST holds reset values
198501= Test Mode, write access to register TEST enabled</description>
19851                  <bitRange>[7:7]</bitRange>
19852                  <access>read-write</access>
19853                </field>
19854                <field>
19855                  <name>FDOE</name>
19856                  <description>FD Operation Enable
198570= FD operation disabled
198581= FD operation enabled</description>
19859                  <bitRange>[8:8]</bitRange>
19860                  <access>read-write</access>
19861                </field>
19862                <field>
19863                  <name>BRSE</name>
19864                  <description>Bit Rate Switch Enable
198650= Bit rate switching for transmissions disabled
198661= Bit rate switching for transmissions enabled</description>
19867                  <bitRange>[9:9]</bitRange>
19868                  <access>read-write</access>
19869                </field>
19870                <field>
19871                  <name>PXHD</name>
19872                  <description>Protocol Exception Handling Disable
198730= Protocol exception handling enabled
198741= Protocol exception handling disabled</description>
19875                  <bitRange>[12:12]</bitRange>
19876                  <access>read-write</access>
19877                </field>
19878                <field>
19879                  <name>EFBI</name>
19880                  <description>Edge Filtering during Bus Integration
198810= Edge filtering disabled
198821= Two consecutive dominant tq required to detect an edge for hard synchronization</description>
19883                  <bitRange>[13:13]</bitRange>
19884                  <access>read-write</access>
19885                </field>
19886                <field>
19887                  <name>TXP</name>
19888                  <description>Transmit Pause
19889If this bit is set, the M_TTCAN pauses for two CAN bit times before starting the next transmission
19890after itself has successfully transmitted a frame (see Section 3.5).
198910= Transmit pause disabled
198921= Transmit pause enabled</description>
19893                  <bitRange>[14:14]</bitRange>
19894                  <access>read-write</access>
19895                </field>
19896                <field>
19897                  <name>NISO</name>
19898                  <description>Non ISO Operation
19899If this bit is set, the M_TTCAN uses the CAN FD frame format as specified by the Bosch CAN FD
19900Specification V1.0.
199010= CAN FD frame format according to ISO 11898-1:2015
199021= CAN FD frame format according to Bosch CAN FD Specification V1.0 addressing the non-ISO CAN FD</description>
19903                  <bitRange>[15:15]</bitRange>
19904                  <access>read-write</access>
19905                </field>
19906              </fields>
19907            </register>
19908            <register>
19909              <name>NBTP</name>
19910              <description>Nominal Bit Timing &amp; Prescaler Register</description>
19911              <addressOffset>0x1C</addressOffset>
19912              <size>32</size>
19913              <access>read-write</access>
19914              <resetValue>0x6000A03</resetValue>
19915              <resetMask>0xFFFFFF7F</resetMask>
19916              <fields>
19917                <field>
19918                  <name>NTSEG2</name>
19919                  <description>Nominal Time segment after sample point
199200x01-0x7F Valid values are 1 to 127. The actual interpretation by the hardware of this value is
19921such that one more than the programmed value is used.</description>
19922                  <bitRange>[6:0]</bitRange>
19923                  <access>read-write</access>
19924                </field>
19925                <field>
19926                  <name>NTSEG1</name>
19927                  <description>Nominal Time segment before sample point
199280x01-0xFF Valid values are 1 to 255. The actual interpretation by the hardware of this value is
19929such that one more than the programmed value is used.</description>
19930                  <bitRange>[15:8]</bitRange>
19931                  <access>read-write</access>
19932                </field>
19933                <field>
19934                  <name>NBRP</name>
19935                  <description>Nominal Bit Rate Prescaler
199360x000-0x1FFThe value by which the oscillator frequency is divided for generating the bit time
19937quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit
19938Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is
19939such that one more than the value programmed here is used.</description>
19940                  <bitRange>[24:16]</bitRange>
19941                  <access>read-write</access>
19942                </field>
19943                <field>
19944                  <name>NSJW</name>
19945                  <description>Nominal (Re)Synchronization Jump Width
199460x00-0x7F Valid values are 0 to 127. The actual interpretation by the hardware of this value is
19947such that one more than the value programmed here is used.</description>
19948                  <bitRange>[31:25]</bitRange>
19949                  <access>read-write</access>
19950                </field>
19951              </fields>
19952            </register>
19953            <register>
19954              <name>TSCC</name>
19955              <description>Timestamp Counter Configuration</description>
19956              <addressOffset>0x20</addressOffset>
19957              <size>32</size>
19958              <access>read-write</access>
19959              <resetValue>0x0</resetValue>
19960              <resetMask>0xF0003</resetMask>
19961              <fields>
19962                <field>
19963                  <name>TSS</name>
19964                  <description>Timestamp Select, should always be set to external timestamp counter
1996500= Timestamp counter value always 0x0000
1996601= Timestamp counter value incremented according to TCP
1996710= External timestamp counter value used
1996811= Same as '00'</description>
19969                  <bitRange>[1:0]</bitRange>
19970                  <access>read-write</access>
19971                </field>
19972                <field>
19973                  <name>TCP</name>
19974                  <description>Timestamp Counter Prescaler (still used for TOCC)
199750x0-0xF Configures the timestamp and timeout counters time unit in multiples of CAN bit times
19976[1...16]. The actual interpretation by the hardware of this value is such that one more
19977than the value programmed here is used.</description>
19978                  <bitRange>[19:16]</bitRange>
19979                  <access>read-write</access>
19980                </field>
19981              </fields>
19982            </register>
19983            <register>
19984              <name>TSCV</name>
19985              <description>Timestamp Counter Value</description>
19986              <addressOffset>0x24</addressOffset>
19987              <size>32</size>
19988              <access>read-write</access>
19989              <resetValue>0x0</resetValue>
19990              <resetMask>0xFFFF</resetMask>
19991              <fields>
19992                <field>
19993                  <name>TSC</name>
19994                  <description>Timestamp Counter, not used for M_TTCAN
19995The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx).
19996When TSCC.TSS = '01', the Timestamp Counter is incremented in multiples of CAN bit times
19997[1...16] depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW.
19998Write access resets the counter to zero. When TSCC.TSS = '10', TSC reflects the external
19999Timestamp Counter value. A write access has no impact.</description>
20000                  <bitRange>[15:0]</bitRange>
20001                  <access>read-write</access>
20002                </field>
20003              </fields>
20004            </register>
20005            <register>
20006              <name>TOCC</name>
20007              <description>Timeout Counter Configuration</description>
20008              <addressOffset>0x28</addressOffset>
20009              <size>32</size>
20010              <access>read-write</access>
20011              <resetValue>0xFFFF0000</resetValue>
20012              <resetMask>0xFFFF0007</resetMask>
20013              <fields>
20014                <field>
20015                  <name>ETOC</name>
20016                  <description>Enable Timeout Counter
200170= Timeout Counter disabled
200181= Timeout Counter enabled</description>
20019                  <bitRange>[0:0]</bitRange>
20020                  <access>read-write</access>
20021                </field>
20022                <field>
20023                  <name>TOS</name>
20024                  <description>Timeout Select
20025When operating in Continuous mode, a write to TOCV presets the counter to the value configured
20026by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the
20027FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting
20028is started when the first FIFO element is stored.
2002900= Continuous operation
2003001= Timeout controlled by Tx Event FIFO
2003110= Timeout controlled by Rx FIFO 0
2003211= Timeout controlled by Rx FIFO 1</description>
20033                  <bitRange>[2:1]</bitRange>
20034                  <access>read-write</access>
20035                </field>
20036                <field>
20037                  <name>TOP</name>
20038                  <description>Timeout Period
20039Start value of the Timeout Counter (down-counter). Configures the Timeout Period.</description>
20040                  <bitRange>[31:16]</bitRange>
20041                  <access>read-write</access>
20042                </field>
20043              </fields>
20044            </register>
20045            <register>
20046              <name>TOCV</name>
20047              <description>Timeout Counter Value</description>
20048              <addressOffset>0x2C</addressOffset>
20049              <size>32</size>
20050              <access>read-write</access>
20051              <resetValue>0xFFFF</resetValue>
20052              <resetMask>0xFFFF</resetMask>
20053              <fields>
20054                <field>
20055                  <name>TOC</name>
20056                  <description>Timeout Counter
20057The Timeout Counter is decremented in multiples of CAN bit times [1...16] depending on the
20058configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the
20059Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS.</description>
20060                  <bitRange>[15:0]</bitRange>
20061                  <access>read-write</access>
20062                </field>
20063              </fields>
20064            </register>
20065            <register>
20066              <name>ECR</name>
20067              <description>Error Counter Register</description>
20068              <addressOffset>0x40</addressOffset>
20069              <size>32</size>
20070              <access>read-only</access>
20071              <resetValue>0x0</resetValue>
20072              <resetMask>0xFFFFFF</resetMask>
20073              <fields>
20074                <field>
20075                  <name>TEC</name>
20076                  <description>Transmit Error Counter
20077Actual state of the Transmit Error Counter, values between 0 and 255</description>
20078                  <bitRange>[7:0]</bitRange>
20079                  <access>read-only</access>
20080                </field>
20081                <field>
20082                  <name>REC</name>
20083                  <description>Receive Error Counter
20084Actual state of the Receive Error Counter, values between 0 and 127</description>
20085                  <bitRange>[14:8]</bitRange>
20086                  <access>read-only</access>
20087                </field>
20088                <field>
20089                  <name>RP</name>
20090                  <description>Receive Error Passive
200910= The Receive Error Counter is below the error passive level of 128
200921= The Receive Error Counter has reached the error passive level of 128</description>
20093                  <bitRange>[15:15]</bitRange>
20094                  <access>read-only</access>
20095                </field>
20096                <field>
20097                  <name>CEL</name>
20098                  <description>CAN Error Logging
20099The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter
20100or the Receive Error Counter to be incremented. It is reset by read access to CEL. The counter stops
20101at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO.</description>
20102                  <bitRange>[23:16]</bitRange>
20103                  <access>read-only</access>
20104                </field>
20105              </fields>
20106            </register>
20107            <register>
20108              <name>PSR</name>
20109              <description>Protocol Status Register</description>
20110              <addressOffset>0x44</addressOffset>
20111              <size>32</size>
20112              <access>read-only</access>
20113              <resetValue>0x707</resetValue>
20114              <resetMask>0x7F7FFF</resetMask>
20115              <fields>
20116                <field>
20117                  <name>LEC</name>
20118                  <description>Last Error Code,
20119Set on Read0
20120The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0'
20121when a message has been transferred (reception or transmission) without error.
20122
201230= No Error: No error occurred since LEC has been reset by successful reception or transmission.
201241= Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.
201252= Form Error: A fixed format part of a received frame has the wrong format.
201263= AckError: The message transmitted by the M_TTCAN was not acknowledged by another node.
201274= Bit1Error: During the transmission of a message (with the exception of the arbitration field),
20128the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus
20129 value was dominant.
201305= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or
20131overload flag), the device wanted to send a dominant level (data or identifier bit logical value
201320'), but the monitored bus value was recessive. During Bus_Off recovery this status is set
20133each time a sequence of 11 recessive bits has been monitored. This enables the CPU to
20134monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at
20135dominant or continuously disturbed).
201366= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming
20137message does not match with the CRC calculated from the received data.
201387= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to '7'.
20139When the LEC shows the value '7', no CAN bus event was detected since the last CPU read
20140access to the Protocol Status Register.</description>
20141                  <bitRange>[2:0]</bitRange>
20142                  <access>read-only</access>
20143                </field>
20144                <field>
20145                  <name>ACT</name>
20146                  <description>Activity
20147Monitors the module's CAN communication state.
2014800= Synchronizing - node is synchronizing on CAN communication
2014901= Idle - node is neither receiver nor transmitter
2015010= Receiver - node is operating as receiver
2015111= Transmitter - node is operating as transmitter</description>
20152                  <bitRange>[4:3]</bitRange>
20153                  <access>read-only</access>
20154                </field>
20155                <field>
20156                  <name>EP</name>
20157                  <description>Error Passive
201580= The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected
201591= The M_CAN is in the Error_Passive state</description>
20160                  <bitRange>[5:5]</bitRange>
20161                  <access>read-only</access>
20162                </field>
20163                <field>
20164                  <name>EW</name>
20165                  <description>Warning Status
201660= Both error counters are below the Error_Warning limit of 96
201671= At least one of error counter has reached the Error_Warning limit of 96</description>
20168                  <bitRange>[6:6]</bitRange>
20169                  <access>read-only</access>
20170                </field>
20171                <field>
20172                  <name>BO</name>
20173                  <description>Bus_Off Status
201740= The M_CAN is not Bus_Off
201751= The M_CAN is in Bus_Off state</description>
20176                  <bitRange>[7:7]</bitRange>
20177                  <access>read-only</access>
20178                </field>
20179                <field>
20180                  <name>DLEC</name>
20181                  <description>Data Phase Last Error Code
20182, Set on Read
20183Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error.</description>
20184                  <bitRange>[10:8]</bitRange>
20185                  <access>read-only</access>
20186                </field>
20187                <field>
20188                  <name>RESI</name>
20189                  <description>ESI flag of last received CAN FD Message
20190, Reset on Read
20191This bit is set together with RFDF, independent of acceptance filtering.
201920= Last received CAN FD message did not have its ESI flag set
201931= Last received CAN FD message had its ESI flag set</description>
20194                  <bitRange>[11:11]</bitRange>
20195                  <access>read-only</access>
20196                </field>
20197                <field>
20198                  <name>RBRS</name>
20199                  <description>BRS flag of last received CAN FD Message
20200, Reset on Read
20201This bit is set together with RFDF, independent of acceptance filtering.
202020= Last received CAN FD message did not have its BRS flag set
202031= Last received CAN FD message had its BRS flag set</description>
20204                  <bitRange>[12:12]</bitRange>
20205                  <access>read-only</access>
20206                </field>
20207                <field>
20208                  <name>RFDF</name>
20209                  <description>Received a CAN FD Message
20210, Reset on Read
20211This bit is set independent of acceptance filtering.
202120= Since this bit was reset by the CPU, no CAN FD message has been received
202131= Message in CAN FD format with FDF flag set has been received</description>
20214                  <bitRange>[13:13]</bitRange>
20215                  <access>read-only</access>
20216                </field>
20217                <field>
20218                  <name>PXE</name>
20219                  <description>Protocol Exception Event
20220, Reset on Read
202210= No protocol exception event occurred since last read access
202221= Protocol exception event occurred</description>
20223                  <bitRange>[14:14]</bitRange>
20224                  <access>read-only</access>
20225                </field>
20226                <field>
20227                  <name>TDCV</name>
20228                  <description>Transmitter Delay Compensation Value
202290x00-0x7F Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq.</description>
20230                  <bitRange>[22:16]</bitRange>
20231                  <access>read-only</access>
20232                </field>
20233              </fields>
20234            </register>
20235            <register>
20236              <name>TDCR</name>
20237              <description>Transmitter Delay Compensation Register</description>
20238              <addressOffset>0x48</addressOffset>
20239              <size>32</size>
20240              <access>read-write</access>
20241              <resetValue>0x0</resetValue>
20242              <resetMask>0x7F7F</resetMask>
20243              <fields>
20244                <field>
20245                  <name>TDCF</name>
20246                  <description>Transmitter Delay Compensation Filter Window Length
202470x00-0x7F Defines the minimum value for the SSP position, dominant edges on m_ttcan_rx
20248that would result in an earlier SSP position are ignored for transmitter delay measurement.
20249The feature is enabled when TDCF is configured to a value greater than
20250TDCO. Valid values are 0 to 127 mtq</description>
20251                  <bitRange>[6:0]</bitRange>
20252                  <access>read-write</access>
20253                </field>
20254                <field>
20255                  <name>TDCO</name>
20256                  <description>Transmitter Delay Compensation Offset
202570x00-0x7F Offset value defining the distance between the measured delay from m_ttcan_tx to
20258m_ttcan_rx and the secondary sample point. Valid values are 0 to 127 mtq.</description>
20259                  <bitRange>[14:8]</bitRange>
20260                  <access>read-write</access>
20261                </field>
20262              </fields>
20263            </register>
20264            <register>
20265              <name>IR</name>
20266              <description>Interrupt Register</description>
20267              <addressOffset>0x50</addressOffset>
20268              <size>32</size>
20269              <access>read-write</access>
20270              <resetValue>0x0</resetValue>
20271              <resetMask>0x3FFFFFFF</resetMask>
20272              <fields>
20273                <field>
20274                  <name>RF0N</name>
20275                  <description>Rx FIFO 0 New Message
202760= No new message written to Rx FIFO 0
202771= New message written to Rx FIFO 0</description>
20278                  <bitRange>[0:0]</bitRange>
20279                  <access>read-write</access>
20280                </field>
20281                <field>
20282                  <name>RF0W</name>
20283                  <description>Rx FIFO 0 Watermark Reached
202840= Rx FIFO 0 fill level below watermark
202851= Rx FIFO 0 fill level reached watermark</description>
20286                  <bitRange>[1:1]</bitRange>
20287                  <access>read-write</access>
20288                </field>
20289                <field>
20290                  <name>RF0F</name>
20291                  <description>Rx FIFO 0 Full
202920= Rx FIFO 0 not full
202931= Rx FIFO 0 full</description>
20294                  <bitRange>[2:2]</bitRange>
20295                  <access>read-write</access>
20296                </field>
20297                <field>
20298                  <name>RF0L_</name>
20299                  <description>Rx FIFO 0 Message Lost
203000= No Rx FIFO 0 message lost
203011= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero</description>
20302                  <bitRange>[3:3]</bitRange>
20303                  <access>read-write</access>
20304                </field>
20305                <field>
20306                  <name>RF1N</name>
20307                  <description>Rx FIFO 1 New Message
203080= No new message written to Rx FIFO 1
203091= New message written to Rx FIFO 1</description>
20310                  <bitRange>[4:4]</bitRange>
20311                  <access>read-write</access>
20312                </field>
20313                <field>
20314                  <name>RF1W</name>
20315                  <description>Rx FIFO 1 Watermark Reached
203160= Rx FIFO 1 fill level below watermark
203171= Rx FIFO 1 fill level reached watermark</description>
20318                  <bitRange>[5:5]</bitRange>
20319                  <access>read-write</access>
20320                </field>
20321                <field>
20322                  <name>RF1F</name>
20323                  <description>Rx FIFO 1 Full
203240= Rx FIFO 1 not full
203251= Rx FIFO 1 full</description>
20326                  <bitRange>[6:6]</bitRange>
20327                  <access>read-write</access>
20328                </field>
20329                <field>
20330                  <name>RF1L_</name>
20331                  <description>Rx FIFO 1 Message Lost
203320= No Rx FIFO 1 message lost
203331= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero</description>
20334                  <bitRange>[7:7]</bitRange>
20335                  <access>read-write</access>
20336                </field>
20337                <field>
20338                  <name>HPM</name>
20339                  <description>High Priority Message
203400= No high priority message received
203411= High priority message received</description>
20342                  <bitRange>[8:8]</bitRange>
20343                  <access>read-write</access>
20344                </field>
20345                <field>
20346                  <name>TC</name>
20347                  <description>Transmission Completed
203480= No transmission completed
203491= Transmission completed</description>
20350                  <bitRange>[9:9]</bitRange>
20351                  <access>read-write</access>
20352                </field>
20353                <field>
20354                  <name>TCF</name>
20355                  <description>Transmission Cancellation Finished
203560= No transmission cancellation finished
203571= Transmission cancellation finished</description>
20358                  <bitRange>[10:10]</bitRange>
20359                  <access>read-write</access>
20360                </field>
20361                <field>
20362                  <name>TFE</name>
20363                  <description>Tx FIFO Empty
203640= Tx FIFO non-empty
203651= Tx FIFO empty</description>
20366                  <bitRange>[11:11]</bitRange>
20367                  <access>read-write</access>
20368                </field>
20369                <field>
20370                  <name>TEFN</name>
20371                  <description>Tx Event FIFO New Entry
203720= Tx Event FIFO unchanged
203731= Tx Handler wrote Tx Event FIFO element</description>
20374                  <bitRange>[12:12]</bitRange>
20375                  <access>read-write</access>
20376                </field>
20377                <field>
20378                  <name>TEFW</name>
20379                  <description>Tx Event FIFO Watermark Reached
203800= Tx Event FIFO fill level below watermark
203811= Tx Event FIFO fill level reached watermark</description>
20382                  <bitRange>[13:13]</bitRange>
20383                  <access>read-write</access>
20384                </field>
20385                <field>
20386                  <name>TEFF</name>
20387                  <description>Tx Event FIFO Full
203880= Tx Event FIFO not full
203891= Tx Event FIFO full</description>
20390                  <bitRange>[14:14]</bitRange>
20391                  <access>read-write</access>
20392                </field>
20393                <field>
20394                  <name>TEFL_</name>
20395                  <description>Tx Event FIFO Element Lost
203960= No Tx Event FIFO element lost
203971= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero</description>
20398                  <bitRange>[15:15]</bitRange>
20399                  <access>read-write</access>
20400                </field>
20401                <field>
20402                  <name>TSW</name>
20403                  <description>Timestamp Wraparound
204040= No timestamp counter wrap-around
204051= Timestamp counter wrapped around</description>
20406                  <bitRange>[16:16]</bitRange>
20407                  <access>read-write</access>
20408                </field>
20409                <field>
20410                  <name>MRAF</name>
20411                  <description>Message RAM Access Failure
20412The flag is set, when the Rx Handler
20413- has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message.
20414- was not able to write a message to the Message RAM. In this case message storage is aborted.
20415In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location.
20416The flag is also set when the Tx Handler was not able to read a message from the Message RAM
20417in time. In this case message transmission is aborted. In case of a Tx Handler access failure the
20418M_TTCAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted
20419Operation Mode, the Host CPU has to reset CCCR.ASM.
204200= No Message RAM access failure occurred
204211= Message RAM access failure occurred</description>
20422                  <bitRange>[17:17]</bitRange>
20423                  <access>read-write</access>
20424                </field>
20425                <field>
20426                  <name>TOO</name>
20427                  <description>Timeout Occurred
204280= No timeout
204291= Timeout reached</description>
20430                  <bitRange>[18:18]</bitRange>
20431                  <access>read-write</access>
20432                </field>
20433                <field>
20434                  <name>DRX</name>
20435                  <description>Message stored to Dedicated Rx Buffer
20436The flag is set whenever a received message has been stored into a dedicated Rx Buffer.
204370= No Rx Buffer updated
204381= At least one received message stored into a Rx Buffer</description>
20439                  <bitRange>[19:19]</bitRange>
20440                  <access>read-write</access>
20441                </field>
20442                <field>
20443                  <name>BEC</name>
20444                  <description>M_TTCAN reports correctable ECC fault to the generic fault structure, this bit always reads as 0.
20445Bit Error Corrected
20446Message RAM bit error detected and corrected. Controlled by input signal m_ttcan_aeim_berr[0]
20447generated by an optional external parity / ECC logic attached to the Message RAM.
204480= No bit error detected when reading from Message RAM
204491= Bit error detected and corrected (e.g. ECC)</description>
20450                  <bitRange>[20:20]</bitRange>
20451                  <access>read-write</access>
20452                </field>
20453                <field>
20454                  <name>BEU</name>
20455                  <description>Bit Error Uncorrected
20456Message RAM bit error detected, uncorrected. Controlled by input signal m_ttcan_aeim_berr[1]
20457generated by an optional external parity / ECC logic attached to the Message RAM. An uncorrected
20458Message RAM bit error sets CCCR.INIT to '1'. This is done to avoid transmission of corrupted data.
204590= No bit error detected when reading from Message RAM
204601= Bit error detected, uncorrected (e.g. parity logic)</description>
20461                  <bitRange>[21:21]</bitRange>
20462                  <access>read-write</access>
20463                </field>
20464                <field>
20465                  <name>ELO</name>
20466                  <description>Error Logging Overflow
204670= CAN Error Logging Counter did not overflow
204681= Overflow of CAN Error Logging Counter occurred</description>
20469                  <bitRange>[22:22]</bitRange>
20470                  <access>read-write</access>
20471                </field>
20472                <field>
20473                  <name>EP_</name>
20474                  <description>Error Passive
204750= Error_Passive status unchanged
204761= Error_Passive status changed</description>
20477                  <bitRange>[23:23]</bitRange>
20478                  <access>read-write</access>
20479                </field>
20480                <field>
20481                  <name>EW_</name>
20482                  <description>Warning Status
204830= Error_Warning status unchanged
204841= Error_Warning status changed</description>
20485                  <bitRange>[24:24]</bitRange>
20486                  <access>read-write</access>
20487                </field>
20488                <field>
20489                  <name>BO_</name>
20490                  <description>Bus_Off Status
204910= Bus_Off status unchanged
204921= Bus_Off status changed</description>
20493                  <bitRange>[25:25]</bitRange>
20494                  <access>read-write</access>
20495                </field>
20496                <field>
20497                  <name>WDI</name>
20498                  <description>Watchdog Interrupt
204990= No Message RAM Watchdog event occurred
205001= Message RAM Watchdog event due to missing READY</description>
20501                  <bitRange>[26:26]</bitRange>
20502                  <access>read-write</access>
20503                </field>
20504                <field>
20505                  <name>PEA</name>
20506                  <description>Protocol Error in Arbitration Phase (Nominal Bit Time is used)
205070= No protocol error in arbitration phase
205081= Protocol error in arbitration phase detected (PSR.LEC != 0,7)</description>
20509                  <bitRange>[27:27]</bitRange>
20510                  <access>read-write</access>
20511                </field>
20512                <field>
20513                  <name>PED</name>
20514                  <description>Protocol Error in Data Phase (Data Bit Time is used)
205150= No protocol error in data phase
205161= Protocol error in data phase detected (PSR.DLEC != 0,7)</description>
20517                  <bitRange>[28:28]</bitRange>
20518                  <access>read-write</access>
20519                </field>
20520                <field>
20521                  <name>ARA</name>
20522                  <description>N/A</description>
20523                  <bitRange>[29:29]</bitRange>
20524                  <access>read-write</access>
20525                </field>
20526              </fields>
20527            </register>
20528            <register>
20529              <name>IE</name>
20530              <description>Interrupt Enable</description>
20531              <addressOffset>0x54</addressOffset>
20532              <size>32</size>
20533              <access>read-write</access>
20534              <resetValue>0x0</resetValue>
20535              <resetMask>0x3FFFFFFF</resetMask>
20536              <fields>
20537                <field>
20538                  <name>RF0NE</name>
20539                  <description>Rx FIFO 0 New Message Interrupt Enable</description>
20540                  <bitRange>[0:0]</bitRange>
20541                  <access>read-write</access>
20542                </field>
20543                <field>
20544                  <name>RF0WE</name>
20545                  <description>Rx FIFO 0 Watermark Reached Interrupt Enable</description>
20546                  <bitRange>[1:1]</bitRange>
20547                  <access>read-write</access>
20548                </field>
20549                <field>
20550                  <name>RF0FE</name>
20551                  <description>Rx FIFO 0 Full Interrupt Enable</description>
20552                  <bitRange>[2:2]</bitRange>
20553                  <access>read-write</access>
20554                </field>
20555                <field>
20556                  <name>RF0LE</name>
20557                  <description>Rx FIFO 0 Message Lost Interrupt Enable</description>
20558                  <bitRange>[3:3]</bitRange>
20559                  <access>read-write</access>
20560                </field>
20561                <field>
20562                  <name>RF1NE</name>
20563                  <description>Rx FIFO 1 New Message Interrupt Enable</description>
20564                  <bitRange>[4:4]</bitRange>
20565                  <access>read-write</access>
20566                </field>
20567                <field>
20568                  <name>RF1WE</name>
20569                  <description>Rx FIFO 1 Watermark Reached Interrupt Enable</description>
20570                  <bitRange>[5:5]</bitRange>
20571                  <access>read-write</access>
20572                </field>
20573                <field>
20574                  <name>RF1FE</name>
20575                  <description>Rx FIFO 1 Full Interrupt Enable</description>
20576                  <bitRange>[6:6]</bitRange>
20577                  <access>read-write</access>
20578                </field>
20579                <field>
20580                  <name>RF1LE</name>
20581                  <description>Rx FIFO 1 Message Lost Interrupt Enable</description>
20582                  <bitRange>[7:7]</bitRange>
20583                  <access>read-write</access>
20584                </field>
20585                <field>
20586                  <name>HPME</name>
20587                  <description>High Priority Message Interrupt Enable</description>
20588                  <bitRange>[8:8]</bitRange>
20589                  <access>read-write</access>
20590                </field>
20591                <field>
20592                  <name>TCE</name>
20593                  <description>Transmission Completed Interrupt Enable</description>
20594                  <bitRange>[9:9]</bitRange>
20595                  <access>read-write</access>
20596                </field>
20597                <field>
20598                  <name>TCFE</name>
20599                  <description>Transmission Cancellation Finished Interrupt Enable</description>
20600                  <bitRange>[10:10]</bitRange>
20601                  <access>read-write</access>
20602                </field>
20603                <field>
20604                  <name>TFEE</name>
20605                  <description>Tx FIFO Empty Interrupt Enable</description>
20606                  <bitRange>[11:11]</bitRange>
20607                  <access>read-write</access>
20608                </field>
20609                <field>
20610                  <name>TEFNE</name>
20611                  <description>Tx Event FIDO New Entry Interrupt Enable</description>
20612                  <bitRange>[12:12]</bitRange>
20613                  <access>read-write</access>
20614                </field>
20615                <field>
20616                  <name>TEFWE</name>
20617                  <description>Tx Event FIFO Watermark Reached Interrupt Enable</description>
20618                  <bitRange>[13:13]</bitRange>
20619                  <access>read-write</access>
20620                </field>
20621                <field>
20622                  <name>TEFFE</name>
20623                  <description>Tx Event FIFO Full Interrupt Enable</description>
20624                  <bitRange>[14:14]</bitRange>
20625                  <access>read-write</access>
20626                </field>
20627                <field>
20628                  <name>TEFLE</name>
20629                  <description>Tx Event FIFO Event Lost Interrupt Enable</description>
20630                  <bitRange>[15:15]</bitRange>
20631                  <access>read-write</access>
20632                </field>
20633                <field>
20634                  <name>TSWE</name>
20635                  <description>Timestamp Wraparound Interrupt Enable</description>
20636                  <bitRange>[16:16]</bitRange>
20637                  <access>read-write</access>
20638                </field>
20639                <field>
20640                  <name>MRAFE</name>
20641                  <description>Message RAM Access Failure Interrupt Enable</description>
20642                  <bitRange>[17:17]</bitRange>
20643                  <access>read-write</access>
20644                </field>
20645                <field>
20646                  <name>TOOE</name>
20647                  <description>Timeout Occurred Interrupt Enable</description>
20648                  <bitRange>[18:18]</bitRange>
20649                  <access>read-write</access>
20650                </field>
20651                <field>
20652                  <name>DRXE</name>
20653                  <description>Message stored to Dedicated Rx Buffer Interrupt Enable</description>
20654                  <bitRange>[19:19]</bitRange>
20655                  <access>read-write</access>
20656                </field>
20657                <field>
20658                  <name>BECE</name>
20659                  <description>Bit Error Corrected Interrupt Enable (not used in M_TTCAN)</description>
20660                  <bitRange>[20:20]</bitRange>
20661                  <access>read-write</access>
20662                </field>
20663                <field>
20664                  <name>BEUE</name>
20665                  <description>Bit Error Uncorrected Interrupt Enable</description>
20666                  <bitRange>[21:21]</bitRange>
20667                  <access>read-write</access>
20668                </field>
20669                <field>
20670                  <name>ELOE</name>
20671                  <description>Error Logging Overflow Interrupt Enable</description>
20672                  <bitRange>[22:22]</bitRange>
20673                  <access>read-write</access>
20674                </field>
20675                <field>
20676                  <name>EPE</name>
20677                  <description>Error Passive Interrupt Enable</description>
20678                  <bitRange>[23:23]</bitRange>
20679                  <access>read-write</access>
20680                </field>
20681                <field>
20682                  <name>EWE</name>
20683                  <description>Warning Status Interrupt Enable</description>
20684                  <bitRange>[24:24]</bitRange>
20685                  <access>read-write</access>
20686                </field>
20687                <field>
20688                  <name>BOE</name>
20689                  <description>Bus_Off Status Interrupt Enable</description>
20690                  <bitRange>[25:25]</bitRange>
20691                  <access>read-write</access>
20692                </field>
20693                <field>
20694                  <name>WDIE</name>
20695                  <description>Watchdog Interrupt Enable</description>
20696                  <bitRange>[26:26]</bitRange>
20697                  <access>read-write</access>
20698                </field>
20699                <field>
20700                  <name>PEAE</name>
20701                  <description>Protocol Error in Arbitration Phase Enable</description>
20702                  <bitRange>[27:27]</bitRange>
20703                  <access>read-write</access>
20704                </field>
20705                <field>
20706                  <name>PEDE</name>
20707                  <description>Protocol Error in Data Phase Enable</description>
20708                  <bitRange>[28:28]</bitRange>
20709                  <access>read-write</access>
20710                </field>
20711                <field>
20712                  <name>ARAE</name>
20713                  <description>N/A</description>
20714                  <bitRange>[29:29]</bitRange>
20715                  <access>read-write</access>
20716                </field>
20717              </fields>
20718            </register>
20719            <register>
20720              <name>ILS</name>
20721              <description>Interrupt Line Select</description>
20722              <addressOffset>0x58</addressOffset>
20723              <size>32</size>
20724              <access>read-write</access>
20725              <resetValue>0x0</resetValue>
20726              <resetMask>0x3FFFFFFF</resetMask>
20727              <fields>
20728                <field>
20729                  <name>RF0NL</name>
20730                  <description>Rx FIFO 0 New Message Interrupt Line</description>
20731                  <bitRange>[0:0]</bitRange>
20732                  <access>read-write</access>
20733                </field>
20734                <field>
20735                  <name>RF0WL</name>
20736                  <description>Rx FIFO 0 Watermark Reached Interrupt Line</description>
20737                  <bitRange>[1:1]</bitRange>
20738                  <access>read-write</access>
20739                </field>
20740                <field>
20741                  <name>RF0FL</name>
20742                  <description>Rx FIFO 0 Full Interrupt Line</description>
20743                  <bitRange>[2:2]</bitRange>
20744                  <access>read-write</access>
20745                </field>
20746                <field>
20747                  <name>RF0LL</name>
20748                  <description>Rx FIFO 0 Message Lost Interrupt Line</description>
20749                  <bitRange>[3:3]</bitRange>
20750                  <access>read-write</access>
20751                </field>
20752                <field>
20753                  <name>RF1NL</name>
20754                  <description>Rx FIFO 1 New Message Interrupt Line</description>
20755                  <bitRange>[4:4]</bitRange>
20756                  <access>read-write</access>
20757                </field>
20758                <field>
20759                  <name>RF1WL</name>
20760                  <description>Rx FIFO 1 Watermark Reached Interrupt Line</description>
20761                  <bitRange>[5:5]</bitRange>
20762                  <access>read-write</access>
20763                </field>
20764                <field>
20765                  <name>RF1FL</name>
20766                  <description>Rx FIFO 1 Full Interrupt Line</description>
20767                  <bitRange>[6:6]</bitRange>
20768                  <access>read-write</access>
20769                </field>
20770                <field>
20771                  <name>RF1LL</name>
20772                  <description>Rx FIFO 1 Message Lost Interrupt Line</description>
20773                  <bitRange>[7:7]</bitRange>
20774                  <access>read-write</access>
20775                </field>
20776                <field>
20777                  <name>HPML</name>
20778                  <description>High Priority Message Interrupt Line</description>
20779                  <bitRange>[8:8]</bitRange>
20780                  <access>read-write</access>
20781                </field>
20782                <field>
20783                  <name>TCL</name>
20784                  <description>Transmission Completed Interrupt Line</description>
20785                  <bitRange>[9:9]</bitRange>
20786                  <access>read-write</access>
20787                </field>
20788                <field>
20789                  <name>TCFL</name>
20790                  <description>Transmission Cancellation Finished Interrupt Line</description>
20791                  <bitRange>[10:10]</bitRange>
20792                  <access>read-write</access>
20793                </field>
20794                <field>
20795                  <name>TFEL</name>
20796                  <description>Tx FIFO Empty Interrupt Line</description>
20797                  <bitRange>[11:11]</bitRange>
20798                  <access>read-write</access>
20799                </field>
20800                <field>
20801                  <name>TEFNL</name>
20802                  <description>Tx Event FIFO New Entry Interrupt Line</description>
20803                  <bitRange>[12:12]</bitRange>
20804                  <access>read-write</access>
20805                </field>
20806                <field>
20807                  <name>TEFWL</name>
20808                  <description>Tx Event FIFO Watermark Reached Interrupt Line</description>
20809                  <bitRange>[13:13]</bitRange>
20810                  <access>read-write</access>
20811                </field>
20812                <field>
20813                  <name>TEFFL</name>
20814                  <description>Tx Event FIFO Full Interrupt Line</description>
20815                  <bitRange>[14:14]</bitRange>
20816                  <access>read-write</access>
20817                </field>
20818                <field>
20819                  <name>TEFLL</name>
20820                  <description>Tx Event FIFO Event Lost Interrupt Line</description>
20821                  <bitRange>[15:15]</bitRange>
20822                  <access>read-write</access>
20823                </field>
20824                <field>
20825                  <name>TSWL</name>
20826                  <description>Timestamp Wraparound Interrupt Line</description>
20827                  <bitRange>[16:16]</bitRange>
20828                  <access>read-write</access>
20829                </field>
20830                <field>
20831                  <name>MRAFL</name>
20832                  <description>Message RAM Access Failure Interrupt Line</description>
20833                  <bitRange>[17:17]</bitRange>
20834                  <access>read-write</access>
20835                </field>
20836                <field>
20837                  <name>TOOL</name>
20838                  <description>Timeout Occurred Interrupt Line</description>
20839                  <bitRange>[18:18]</bitRange>
20840                  <access>read-write</access>
20841                </field>
20842                <field>
20843                  <name>DRXL</name>
20844                  <description>Message stored to Dedicated Rx Buffer Interrupt Line</description>
20845                  <bitRange>[19:19]</bitRange>
20846                  <access>read-write</access>
20847                </field>
20848                <field>
20849                  <name>BECL</name>
20850                  <description>Bit Error Corrected Interrupt Line  (not used in M_TTCAN)</description>
20851                  <bitRange>[20:20]</bitRange>
20852                  <access>read-write</access>
20853                </field>
20854                <field>
20855                  <name>BEUL</name>
20856                  <description>Bit Error Uncorrected Interrupt Line</description>
20857                  <bitRange>[21:21]</bitRange>
20858                  <access>read-write</access>
20859                </field>
20860                <field>
20861                  <name>ELOL</name>
20862                  <description>Error Logging Overflow Interrupt Line</description>
20863                  <bitRange>[22:22]</bitRange>
20864                  <access>read-write</access>
20865                </field>
20866                <field>
20867                  <name>EPL</name>
20868                  <description>Error Passive Interrupt Line</description>
20869                  <bitRange>[23:23]</bitRange>
20870                  <access>read-write</access>
20871                </field>
20872                <field>
20873                  <name>EWL</name>
20874                  <description>Warning Status Interrupt Line</description>
20875                  <bitRange>[24:24]</bitRange>
20876                  <access>read-write</access>
20877                </field>
20878                <field>
20879                  <name>BOL</name>
20880                  <description>Bus_Off Status Interrupt Line</description>
20881                  <bitRange>[25:25]</bitRange>
20882                  <access>read-write</access>
20883                </field>
20884                <field>
20885                  <name>WDIL</name>
20886                  <description>Watchdog Interrupt Line</description>
20887                  <bitRange>[26:26]</bitRange>
20888                  <access>read-write</access>
20889                </field>
20890                <field>
20891                  <name>PEAL</name>
20892                  <description>Protocol Error in Arbitration Phase Line</description>
20893                  <bitRange>[27:27]</bitRange>
20894                  <access>read-write</access>
20895                </field>
20896                <field>
20897                  <name>PEDL</name>
20898                  <description>Protocol Error in Data Phase Line</description>
20899                  <bitRange>[28:28]</bitRange>
20900                  <access>read-write</access>
20901                </field>
20902                <field>
20903                  <name>ARAL</name>
20904                  <description>N/A</description>
20905                  <bitRange>[29:29]</bitRange>
20906                  <access>read-write</access>
20907                </field>
20908              </fields>
20909            </register>
20910            <register>
20911              <name>ILE</name>
20912              <description>Interrupt Line Enable</description>
20913              <addressOffset>0x5C</addressOffset>
20914              <size>32</size>
20915              <access>read-write</access>
20916              <resetValue>0x0</resetValue>
20917              <resetMask>0x3</resetMask>
20918              <fields>
20919                <field>
20920                  <name>EINT0</name>
20921                  <description>Enable Interrupt Line 0
209220= Interrupt line m_ttcan_int0 disabled
209231= Interrupt line m_ttcan_int0 enabled</description>
20924                  <bitRange>[0:0]</bitRange>
20925                  <access>read-write</access>
20926                </field>
20927                <field>
20928                  <name>EINT1</name>
20929                  <description>Enable Interrupt Line 1
209300= Interrupt line m_ttcan_int1 disabled
209311= Interrupt line m_ttcan_int1 enabled</description>
20932                  <bitRange>[1:1]</bitRange>
20933                  <access>read-write</access>
20934                </field>
20935              </fields>
20936            </register>
20937            <register>
20938              <name>GFC</name>
20939              <description>Global Filter Configuration</description>
20940              <addressOffset>0x80</addressOffset>
20941              <size>32</size>
20942              <access>read-write</access>
20943              <resetValue>0x0</resetValue>
20944              <resetMask>0x3F</resetMask>
20945              <fields>
20946                <field>
20947                  <name>RRFE</name>
20948                  <description>Reject Remote Frames Extended
209490= Filter remote frames with 29-bit extended IDs
209501= Reject all remote frames with 29-bit extended IDs</description>
20951                  <bitRange>[0:0]</bitRange>
20952                  <access>read-write</access>
20953                </field>
20954                <field>
20955                  <name>RRFS</name>
20956                  <description>Reject Remote Frames Standard
209570= Filter remote frames with 11-bit standard IDs
209581= Reject all remote frames with 11-bit standard IDs</description>
20959                  <bitRange>[1:1]</bitRange>
20960                  <access>read-write</access>
20961                </field>
20962                <field>
20963                  <name>ANFE</name>
20964                  <description>Accept Non-matching Frames Extended
20965Defines how received messages with 29-bit IDs that do not match any element of the filter list are
20966treated.
2096700= Accept in Rx FIFO 0
2096801= Accept in Rx FIFO 1
2096910= Reject
2097011= Reject</description>
20971                  <bitRange>[3:2]</bitRange>
20972                  <access>read-write</access>
20973                </field>
20974                <field>
20975                  <name>ANFS</name>
20976                  <description>Accept Non-matching Frames Standard
20977Defines how received messages with 11-bit IDs that do not match any element of the filter list are
20978treated.
2097900= Accept in Rx FIFO 0
2098001= Accept in Rx FIFO 1
2098110= Reject
2098211= Reject</description>
20983                  <bitRange>[5:4]</bitRange>
20984                  <access>read-write</access>
20985                </field>
20986              </fields>
20987            </register>
20988            <register>
20989              <name>SIDFC</name>
20990              <description>Standard ID Filter Configuration</description>
20991              <addressOffset>0x84</addressOffset>
20992              <size>32</size>
20993              <access>read-write</access>
20994              <resetValue>0x0</resetValue>
20995              <resetMask>0xFFFFFC</resetMask>
20996              <fields>
20997                <field>
20998                  <name>FLSSA</name>
20999                  <description>Filter List Standard Start Address
21000Start address of standard Message ID filter list (32-bit word address, see Figure 2).</description>
21001                  <bitRange>[15:2]</bitRange>
21002                  <access>read-write</access>
21003                </field>
21004                <field>
21005                  <name>LSS</name>
21006                  <description>List Size Standard
210070= No standard Message ID filter
210081-128= Number of standard Message ID filter elements
21009128= Values greater than 128 are interpreted as 128</description>
21010                  <bitRange>[23:16]</bitRange>
21011                  <access>read-write</access>
21012                </field>
21013              </fields>
21014            </register>
21015            <register>
21016              <name>XIDFC</name>
21017              <description>Extended ID Filter Configuration</description>
21018              <addressOffset>0x88</addressOffset>
21019              <size>32</size>
21020              <access>read-write</access>
21021              <resetValue>0x0</resetValue>
21022              <resetMask>0x7FFFFC</resetMask>
21023              <fields>
21024                <field>
21025                  <name>FLESA</name>
21026                  <description>Filter List Extended Start Address
21027Start address of extended Message ID filter list (32-bit word address, see Figure 2).</description>
21028                  <bitRange>[15:2]</bitRange>
21029                  <access>read-write</access>
21030                </field>
21031                <field>
21032                  <name>LSE</name>
21033                  <description>List Size Extended
210340= No extended Message ID filter
210351-64= Number of extended Message ID filter elements
2103664= Values greater than 64 are interpreted as 64</description>
21037                  <bitRange>[22:16]</bitRange>
21038                  <access>read-write</access>
21039                </field>
21040              </fields>
21041            </register>
21042            <register>
21043              <name>XIDAM</name>
21044              <description>Extended ID AND Mask</description>
21045              <addressOffset>0x90</addressOffset>
21046              <size>32</size>
21047              <access>read-write</access>
21048              <resetValue>0x1FFFFFFF</resetValue>
21049              <resetMask>0x1FFFFFFF</resetMask>
21050              <fields>
21051                <field>
21052                  <name>EIDM</name>
21053                  <description>Extended ID Mask
21054For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message
21055ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all
21056bits set to one the mask is not active.</description>
21057                  <bitRange>[28:0]</bitRange>
21058                  <access>read-write</access>
21059                </field>
21060              </fields>
21061            </register>
21062            <register>
21063              <name>HPMS</name>
21064              <description>High Priority Message Status</description>
21065              <addressOffset>0x94</addressOffset>
21066              <size>32</size>
21067              <access>read-only</access>
21068              <resetValue>0x0</resetValue>
21069              <resetMask>0xFFFF</resetMask>
21070              <fields>
21071                <field>
21072                  <name>BIDX</name>
21073                  <description>Buffer Index
21074Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = '1'.</description>
21075                  <bitRange>[5:0]</bitRange>
21076                  <access>read-only</access>
21077                </field>
21078                <field>
21079                  <name>MSI</name>
21080                  <description>Message Storage Indicator
2108100= No FIFO selected
2108201= FIFO message lost
2108310= Message stored in FIFO 0
2108411= Message stored in FIFO 1</description>
21085                  <bitRange>[7:6]</bitRange>
21086                  <access>read-only</access>
21087                </field>
21088                <field>
21089                  <name>FIDX</name>
21090                  <description>Filter Index
21091Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1.</description>
21092                  <bitRange>[14:8]</bitRange>
21093                  <access>read-only</access>
21094                </field>
21095                <field>
21096                  <name>FLST</name>
21097                  <description>Filter List
21098Indicates the filter list of the matching filter element.
210990= Standard Filter List
211001= Extended Filter List</description>
21101                  <bitRange>[15:15]</bitRange>
21102                  <access>read-only</access>
21103                </field>
21104              </fields>
21105            </register>
21106            <register>
21107              <name>NDAT1</name>
21108              <description>New Data 1</description>
21109              <addressOffset>0x98</addressOffset>
21110              <size>32</size>
21111              <access>read-write</access>
21112              <resetValue>0x0</resetValue>
21113              <resetMask>0xFFFFFFFF</resetMask>
21114              <fields>
21115                <field>
21116                  <name>ND</name>
21117                  <description>New Data
21118The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective
21119Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them.
21120A flag is cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. A hard
21121reset will clear the register.
211220= Rx Buffer not updated
211231= Rx Buffer updated from new message</description>
21124                  <bitRange>[31:0]</bitRange>
21125                  <access>read-write</access>
21126                </field>
21127              </fields>
21128            </register>
21129            <register>
21130              <name>NDAT2</name>
21131              <description>New Data 2</description>
21132              <addressOffset>0x9C</addressOffset>
21133              <size>32</size>
21134              <access>read-write</access>
21135              <resetValue>0x0</resetValue>
21136              <resetMask>0xFFFFFFFF</resetMask>
21137              <fields>
21138                <field>
21139                  <name>ND</name>
21140                  <description>New Data
21141The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective
21142Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them.
21143A flag is cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. A hard
21144reset will clear the register.
211450= Rx Buffer not updated
211461= Rx Buffer updated from new message</description>
21147                  <bitRange>[31:0]</bitRange>
21148                  <access>read-write</access>
21149                </field>
21150              </fields>
21151            </register>
21152            <register>
21153              <name>RXF0C</name>
21154              <description>Rx FIFO 0 Configuration</description>
21155              <addressOffset>0xA0</addressOffset>
21156              <size>32</size>
21157              <access>read-write</access>
21158              <resetValue>0x0</resetValue>
21159              <resetMask>0xFF7FFFFC</resetMask>
21160              <fields>
21161                <field>
21162                  <name>F0SA</name>
21163                  <description>Rx FIFO 0 Start Address
21164Start address of Rx FIFO 0 in Message RAM (32-bit word address, see Figure 2).</description>
21165                  <bitRange>[15:2]</bitRange>
21166                  <access>read-write</access>
21167                </field>
21168                <field>
21169                  <name>F0S</name>
21170                  <description>Rx FIFO 0 Size
211710= No Rx FIFO 0
211721-64= Number of Rx FIFO 0 elements
2117364= Values greater than 64 are interpreted as 64
21174The Rx FIFO 0 elements are indexed from 0 to F0S-1</description>
21175                  <bitRange>[22:16]</bitRange>
21176                  <access>read-write</access>
21177                </field>
21178                <field>
21179                  <name>F0WM</name>
21180                  <description>Rx FIFO 0 Watermark
211810= Watermark interrupt disabled
211821-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W)
2118364= Watermark interrupt disabled</description>
21184                  <bitRange>[30:24]</bitRange>
21185                  <access>read-write</access>
21186                </field>
21187                <field>
21188                  <name>F0OM</name>
21189                  <description>FIFO 0 Operation Mode
21190FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2).
211910= FIFO 0 blocking mode
211921= FIFO 0 overwrite mode</description>
21193                  <bitRange>[31:31]</bitRange>
21194                  <access>read-write</access>
21195                </field>
21196              </fields>
21197            </register>
21198            <register>
21199              <name>RXF0S</name>
21200              <description>Rx FIFO 0 Status</description>
21201              <addressOffset>0xA4</addressOffset>
21202              <size>32</size>
21203              <access>read-only</access>
21204              <resetValue>0x0</resetValue>
21205              <resetMask>0x33F3F7F</resetMask>
21206              <fields>
21207                <field>
21208                  <name>F0FL</name>
21209                  <description>Rx FIFO 0 Fill Level
21210Number of elements stored in Rx FIFO 0, range 0 to 64.
21211When the software reading the value immediately after writing to RXF0A.F0AI, this value should be read twice to ensure that the update is reflected.</description>
21212                  <bitRange>[6:0]</bitRange>
21213                  <access>read-only</access>
21214                </field>
21215                <field>
21216                  <name>F0GI</name>
21217                  <description>Rx FIFO 0 Get Index
21218Rx FIFO 0 read index pointer, range 0 to 63.
21219This field is updated by the software writing to RXF0A.F0AI.
21220When the software reading the value immediately after writing to RXF0A.F0AI, this value should be read twice to ensure that the update is reflected.</description>
21221                  <bitRange>[13:8]</bitRange>
21222                  <access>read-only</access>
21223                </field>
21224                <field>
21225                  <name>F0PI</name>
21226                  <description>Rx FIFO 0 Put Index
21227Rx FIFO 0 write index pointer, range 0 to 63.</description>
21228                  <bitRange>[21:16]</bitRange>
21229                  <access>read-only</access>
21230                </field>
21231                <field>
21232                  <name>F0F</name>
21233                  <description>Rx FIFO 0 Full
212340= Rx FIFO 0 not full
212351= Rx FIFO 0 full</description>
21236                  <bitRange>[24:24]</bitRange>
21237                  <access>read-only</access>
21238                </field>
21239                <field>
21240                  <name>RF0L</name>
21241                  <description>Rx FIFO 0 Message Lost
21242This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset.
212430= No Rx FIFO 0 message lost
212441= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero</description>
21245                  <bitRange>[25:25]</bitRange>
21246                  <access>read-only</access>
21247                </field>
21248              </fields>
21249            </register>
21250            <register>
21251              <name>RXF0A</name>
21252              <description>Rx FIFO 0 Acknowledge</description>
21253              <addressOffset>0xA8</addressOffset>
21254              <size>32</size>
21255              <access>read-write</access>
21256              <resetValue>0x0</resetValue>
21257              <resetMask>0x3F</resetMask>
21258              <fields>
21259                <field>
21260                  <name>F0AI</name>
21261                  <description>Rx FIFO 0 Acknowledge Index
21262After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the
21263 buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index
21264 RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL.</description>
21265                  <bitRange>[5:0]</bitRange>
21266                  <access>read-write</access>
21267                </field>
21268              </fields>
21269            </register>
21270            <register>
21271              <name>RXBC</name>
21272              <description>Rx Buffer Configuration</description>
21273              <addressOffset>0xAC</addressOffset>
21274              <size>32</size>
21275              <access>read-write</access>
21276              <resetValue>0x0</resetValue>
21277              <resetMask>0xFFFC</resetMask>
21278              <fields>
21279                <field>
21280                  <name>RBSA</name>
21281                  <description>Rx Buffer Start Address
21282Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address).
21283Also used to reference debug messages A,B,C.</description>
21284                  <bitRange>[15:2]</bitRange>
21285                  <access>read-write</access>
21286                </field>
21287              </fields>
21288            </register>
21289            <register>
21290              <name>RXF1C</name>
21291              <description>Rx FIFO 1 Configuration</description>
21292              <addressOffset>0xB0</addressOffset>
21293              <size>32</size>
21294              <access>read-write</access>
21295              <resetValue>0x0</resetValue>
21296              <resetMask>0xFF7FFFFC</resetMask>
21297              <fields>
21298                <field>
21299                  <name>F1SA</name>
21300                  <description>Rx FIFO 1 Start Address
21301Start address of Rx FIFO 1 in Message RAM (32-bit word address, see Figure 2).</description>
21302                  <bitRange>[15:2]</bitRange>
21303                  <access>read-write</access>
21304                </field>
21305                <field>
21306                  <name>F1S</name>
21307                  <description>Rx FIFO 1 Size
213080= No Rx FIFO 1
213091-64= Number of Rx FIFO 1 elements
2131064= Values greater than 64 are interpreted as 64
21311The Rx FIFO 1 elements are indexed from 0 to F1S - 1</description>
21312                  <bitRange>[22:16]</bitRange>
21313                  <access>read-write</access>
21314                </field>
21315                <field>
21316                  <name>F1WM</name>
21317                  <description>Rx FIFO 1 Watermark
213180= Watermark interrupt disabled
213191-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W)
2132064= Watermark interrupt disabled</description>
21321                  <bitRange>[30:24]</bitRange>
21322                  <access>read-write</access>
21323                </field>
21324                <field>
21325                  <name>F1OM</name>
21326                  <description>FIFO 1 Operation Mode
21327FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2).
213280= FIFO 1 blocking mode
213291= FIFO 1 overwrite mode</description>
21330                  <bitRange>[31:31]</bitRange>
21331                  <access>read-write</access>
21332                </field>
21333              </fields>
21334            </register>
21335            <register>
21336              <name>RXF1S</name>
21337              <description>Rx FIFO 1 Status</description>
21338              <addressOffset>0xB4</addressOffset>
21339              <size>32</size>
21340              <access>read-only</access>
21341              <resetValue>0x0</resetValue>
21342              <resetMask>0xC33F3F7F</resetMask>
21343              <fields>
21344                <field>
21345                  <name>F1FL</name>
21346                  <description>Rx FIFO 1 Fill Level
21347Number of elements stored in Rx FIFO 1, range 0 to 64.
21348When the software reading the value immediately after writing to RXF1A.F1AI, this value should be read twice to ensure that the update is reflected.</description>
21349                  <bitRange>[6:0]</bitRange>
21350                  <access>read-only</access>
21351                </field>
21352                <field>
21353                  <name>F1GI</name>
21354                  <description>Rx FIFO 1 Get Index
21355Rx FIFO 1 read index pointer, range 0 to 63.
21356This field is updated by the software writing to RXF1A.F1AI.
21357When the software reading the value immediately after writing to RXF1A.F1AI, this value should be read twice to ensure that the update is reflected.</description>
21358                  <bitRange>[13:8]</bitRange>
21359                  <access>read-only</access>
21360                </field>
21361                <field>
21362                  <name>F1PI</name>
21363                  <description>Rx FIFO 1 Put Index
21364Rx FIFO 1 write index pointer, range 0 to 63.</description>
21365                  <bitRange>[21:16]</bitRange>
21366                  <access>read-only</access>
21367                </field>
21368                <field>
21369                  <name>F1F</name>
21370                  <description>Rx FIFO 1 Full
213710= Rx FIFO 1 not full
213721= Rx FIFO 1 full</description>
21373                  <bitRange>[24:24]</bitRange>
21374                  <access>read-only</access>
21375                </field>
21376                <field>
21377                  <name>RF1L</name>
21378                  <description>Rx FIFO 1 Message Lost
21379This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset.
213800= No Rx FIFO 1 message lost
213811= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero</description>
21382                  <bitRange>[25:25]</bitRange>
21383                  <access>read-only</access>
21384                </field>
21385                <field>
21386                  <name>DMS</name>
21387                  <description>Debug Message Status
2138800= Idle state, wait for reception of debug messages, DMA request is cleared
2138901= Debug message A received
2139010= Debug messages A, B received
2139111= Debug messages A, B, C received, DMA request is set</description>
21392                  <bitRange>[31:30]</bitRange>
21393                  <access>read-only</access>
21394                </field>
21395              </fields>
21396            </register>
21397            <register>
21398              <name>RXF1A</name>
21399              <description>Rx FIFO 1 Acknowledge</description>
21400              <addressOffset>0xB8</addressOffset>
21401              <size>32</size>
21402              <access>read-write</access>
21403              <resetValue>0x0</resetValue>
21404              <resetMask>0x3F</resetMask>
21405              <fields>
21406                <field>
21407                  <name>F1AI</name>
21408                  <description>Rx FIFO 1 Acknowledge Index
21409After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the
21410 buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index
21411 RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL.</description>
21412                  <bitRange>[5:0]</bitRange>
21413                  <access>read-write</access>
21414                </field>
21415              </fields>
21416            </register>
21417            <register>
21418              <name>RXESC</name>
21419              <description>Rx Buffer / FIFO Element Size Configuration</description>
21420              <addressOffset>0xBC</addressOffset>
21421              <size>32</size>
21422              <access>read-write</access>
21423              <resetValue>0x0</resetValue>
21424              <resetMask>0x777</resetMask>
21425              <fields>
21426                <field>
21427                  <name>F0DS</name>
21428                  <description>Rx FIFO 0 Data Field Size
21429000= 8 byte data field
21430001= 12 byte data field
21431010= 16 byte data field
21432011= 20 byte data field
21433100= 24 byte data field
21434101= 32 byte data field
21435110= 48 byte data field
21436111= 64 byte data field</description>
21437                  <bitRange>[2:0]</bitRange>
21438                  <access>read-write</access>
21439                </field>
21440                <field>
21441                  <name>F1DS</name>
21442                  <description>Rx FIFO 1 Data Field Size
21443000= 8 byte data field
21444001= 12 byte data field
21445010= 16 byte data field
21446011= 20 byte data field
21447100= 24 byte data field
21448101= 32 byte data field
21449110= 48 byte data field
21450111= 64 byte data field</description>
21451                  <bitRange>[6:4]</bitRange>
21452                  <access>read-write</access>
21453                </field>
21454                <field>
21455                  <name>RBDS</name>
21456                  <description>Rx Buffer Data Field Size
21457000= 8 byte data field
21458001= 12 byte data field
21459010= 16 byte data field
21460011= 20 byte data field
21461100= 24 byte data field
21462101= 32 byte data field
21463110= 48 byte data field
21464111= 64 byte data field</description>
21465                  <bitRange>[10:8]</bitRange>
21466                  <access>read-write</access>
21467                </field>
21468              </fields>
21469            </register>
21470            <register>
21471              <name>TXBC</name>
21472              <description>Tx Buffer Configuration</description>
21473              <addressOffset>0xC0</addressOffset>
21474              <size>32</size>
21475              <access>read-write</access>
21476              <resetValue>0x0</resetValue>
21477              <resetMask>0x7F3FFFFC</resetMask>
21478              <fields>
21479                <field>
21480                  <name>TBSA</name>
21481                  <description>Tx Buffers Start Address
21482Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2).</description>
21483                  <bitRange>[15:2]</bitRange>
21484                  <access>read-write</access>
21485                </field>
21486                <field>
21487                  <name>NDTB</name>
21488                  <description>Number of Dedicated Transmit Buffers
214890= No Dedicated Tx Buffers
214901-32= Number of Dedicated Tx Buffers
2149132= Values greater than 32 are interpreted as 32</description>
21492                  <bitRange>[21:16]</bitRange>
21493                  <access>read-write</access>
21494                </field>
21495                <field>
21496                  <name>TFQS</name>
21497                  <description>Transmit FIFO/Queue Size
214980= No Tx FIFO/Queue
214991-32= Number of Tx Buffers used for Tx FIFO/Queue
2150032= Values greater than 32 are interpreted as 32</description>
21501                  <bitRange>[29:24]</bitRange>
21502                  <access>read-write</access>
21503                </field>
21504                <field>
21505                  <name>TFQM</name>
21506                  <description>Tx FIFO/Queue Mode
215070= Tx FIFO operation
215081= Tx Queue operation</description>
21509                  <bitRange>[30:30]</bitRange>
21510                  <access>read-write</access>
21511                </field>
21512              </fields>
21513            </register>
21514            <register>
21515              <name>TXFQS</name>
21516              <description>Tx FIFO/Queue Status</description>
21517              <addressOffset>0xC4</addressOffset>
21518              <size>32</size>
21519              <access>read-only</access>
21520              <resetValue>0x0</resetValue>
21521              <resetMask>0x3F1F3F</resetMask>
21522              <fields>
21523                <field>
21524                  <name>TFFL</name>
21525                  <description>Tx FIFO Free Level
21526Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when
21527Tx Queue operation is configured (TXBC.TFQM = '1')</description>
21528                  <bitRange>[5:0]</bitRange>
21529                  <access>read-only</access>
21530                </field>
21531                <field>
21532                  <name>TFGI</name>
21533                  <description>Tx FIFO Get Index
21534Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured
21535TXBC.TFQM = '1').</description>
21536                  <bitRange>[12:8]</bitRange>
21537                  <access>read-only</access>
21538                </field>
21539                <field>
21540                  <name>TFQPI</name>
21541                  <description>Tx FIFO/Queue Put Index
21542Tx FIFO/Queue write index pointer, range 0 to 31.</description>
21543                  <bitRange>[20:16]</bitRange>
21544                  <access>read-only</access>
21545                </field>
21546                <field>
21547                  <name>TFQF</name>
21548                  <description>Tx FIFO/Queue Full
215490= Tx FIFO/Queue not full
215501= Tx FIFO/Queue full</description>
21551                  <bitRange>[21:21]</bitRange>
21552                  <access>read-only</access>
21553                </field>
21554              </fields>
21555            </register>
21556            <register>
21557              <name>TXESC</name>
21558              <description>Tx Buffer Element Size Configuration</description>
21559              <addressOffset>0xC8</addressOffset>
21560              <size>32</size>
21561              <access>read-write</access>
21562              <resetValue>0x0</resetValue>
21563              <resetMask>0x7</resetMask>
21564              <fields>
21565                <field>
21566                  <name>TBDS</name>
21567                  <description>Tx Buffer Data Field Size
21568000= 8 byte data field
21569001= 12 byte data field
21570010= 16 byte data field
21571011= 20 byte data field
21572100= 24 byte data field
21573101= 32 byte data field
21574110= 48 byte data field
21575111= 64 byte data field</description>
21576                  <bitRange>[2:0]</bitRange>
21577                  <access>read-write</access>
21578                </field>
21579              </fields>
21580            </register>
21581            <register>
21582              <name>TXBRP</name>
21583              <description>Tx Buffer Request Pending</description>
21584              <addressOffset>0xCC</addressOffset>
21585              <size>32</size>
21586              <access>read-only</access>
21587              <resetValue>0x0</resetValue>
21588              <resetMask>0xFFFFFFFF</resetMask>
21589              <fields>
21590                <field>
21591                  <name>TRP</name>
21592                  <description>Transmission Request Pending
21593Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR.
21594The bits are reset after a requested transmission has completed or has been cancelled via register
21595TXBCR.
21596TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set,
21597a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the
21598highest priority (Tx Buffer with lowest Message ID).
21599A cancellation request resets the corresponding transmission request pending bit of register
21600TXBRP. In case a transmission has already been started when a cancellation is requested, this is
21601done at the end of the transmission, regardless whether the transmission was successful or not. The
21602cancellation request bits are reset directly after the corresponding TXBRP bit has been reset.
21603After a cancellation has been requested, a finished cancellation is signaled via TXBCF
21604after successful transmission together with the corresponding TXBTO bit
21605when the transmission has not yet been started at the point of cancellation
21606when the transmission has been aborted due to lost arbitration
21607when an error occurred during frame transmission
21608In DAR mode all transmissions are automatically cancelled if they are not successful. The
21609corresponding TXBCF bit is set for all unsuccessful transmissions.
216100= No transmission request pending
216111= Transmission request pending</description>
21612                  <bitRange>[31:0]</bitRange>
21613                  <access>read-only</access>
21614                </field>
21615              </fields>
21616            </register>
21617            <register>
21618              <name>TXBAR</name>
21619              <description>Tx Buffer Add Request</description>
21620              <addressOffset>0xD0</addressOffset>
21621              <size>32</size>
21622              <access>read-write</access>
21623              <resetValue>0x0</resetValue>
21624              <resetMask>0xFFFFFFFF</resetMask>
21625              <fields>
21626                <field>
21627                  <name>AR</name>
21628                  <description>Add Request
21629Each Tx Buffer has its own Add Request bit. Writing a '1' will set the corresponding Add Request
21630bit; writing a '0' has no impact. This enables the Host to set transmission requests for multiple Tx
21631Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC.
21632When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan
21633process has completed.
216340= No transmission request added
216351= Transmission requested added</description>
21636                  <bitRange>[31:0]</bitRange>
21637                  <access>read-write</access>
21638                </field>
21639              </fields>
21640            </register>
21641            <register>
21642              <name>TXBCR</name>
21643              <description>Tx Buffer Cancellation Request</description>
21644              <addressOffset>0xD4</addressOffset>
21645              <size>32</size>
21646              <access>read-write</access>
21647              <resetValue>0x0</resetValue>
21648              <resetMask>0xFFFFFFFF</resetMask>
21649              <fields>
21650                <field>
21651                  <name>CR</name>
21652                  <description>Cancellation Request
21653Each Tx Buffer has its own Cancellation Request bit. Writing a '1' will set the corresponding
21654Cancellation Request bit; writing a '0' has no impact. This enables the Host to set cancellation
21655requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx
21656Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset.
216570= No cancellation pending
216581= Cancellation pending</description>
21659                  <bitRange>[31:0]</bitRange>
21660                  <access>read-write</access>
21661                </field>
21662              </fields>
21663            </register>
21664            <register>
21665              <name>TXBTO</name>
21666              <description>Tx Buffer Transmission Occurred</description>
21667              <addressOffset>0xD8</addressOffset>
21668              <size>32</size>
21669              <access>read-only</access>
21670              <resetValue>0x0</resetValue>
21671              <resetMask>0xFFFFFFFF</resetMask>
21672              <fields>
21673                <field>
21674                  <name>TO</name>
21675                  <description>Transmission Occurred
21676Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding
21677TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission
21678is requested by writing a '1' to the corresponding bit of register TXBAR.
216790= No transmission occurred
216801= Transmission occurred</description>
21681                  <bitRange>[31:0]</bitRange>
21682                  <access>read-only</access>
21683                </field>
21684              </fields>
21685            </register>
21686            <register>
21687              <name>TXBCF</name>
21688              <description>Tx Buffer Cancellation Finished</description>
21689              <addressOffset>0xDC</addressOffset>
21690              <size>32</size>
21691              <access>read-only</access>
21692              <resetValue>0x0</resetValue>
21693              <resetMask>0xFFFFFFFF</resetMask>
21694              <fields>
21695                <field>
21696                  <name>CF</name>
21697                  <description>Cancellation Finished
21698Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding
21699TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding
21700TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a
21701new transmission is requested by writing a '1' to the corresponding bit of register TXBAR.
217020= No transmit buffer cancellation
217031= Transmit buffer cancellation finished</description>
21704                  <bitRange>[31:0]</bitRange>
21705                  <access>read-only</access>
21706                </field>
21707              </fields>
21708            </register>
21709            <register>
21710              <name>TXBTIE</name>
21711              <description>Tx Buffer Transmission Interrupt Enable</description>
21712              <addressOffset>0xE0</addressOffset>
21713              <size>32</size>
21714              <access>read-write</access>
21715              <resetValue>0x0</resetValue>
21716              <resetMask>0xFFFFFFFF</resetMask>
21717              <fields>
21718                <field>
21719                  <name>TIE</name>
21720                  <description>Transmission Interrupt Enable
21721Each Tx Buffer has its own Transmission Interrupt Enable bit.
217220= Transmission interrupt disabled
217231= Transmission interrupt enable</description>
21724                  <bitRange>[31:0]</bitRange>
21725                  <access>read-write</access>
21726                </field>
21727              </fields>
21728            </register>
21729            <register>
21730              <name>TXBCIE</name>
21731              <description>Tx Buffer Cancellation Finished Interrupt Enable</description>
21732              <addressOffset>0xE4</addressOffset>
21733              <size>32</size>
21734              <access>read-write</access>
21735              <resetValue>0x0</resetValue>
21736              <resetMask>0xFFFFFFFF</resetMask>
21737              <fields>
21738                <field>
21739                  <name>CFIE</name>
21740                  <description>Cancellation Finished Interrupt Enable
21741Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
217420= Cancellation finished interrupt disabled
217431= Cancellation finished interrupt enabled</description>
21744                  <bitRange>[31:0]</bitRange>
21745                  <access>read-write</access>
21746                </field>
21747              </fields>
21748            </register>
21749            <register>
21750              <name>TXEFC</name>
21751              <description>Tx Event FIFO Configuration</description>
21752              <addressOffset>0xF0</addressOffset>
21753              <size>32</size>
21754              <access>read-write</access>
21755              <resetValue>0x0</resetValue>
21756              <resetMask>0x3F3FFFFC</resetMask>
21757              <fields>
21758                <field>
21759                  <name>EFSA</name>
21760                  <description>Event FIFO Start Address
21761Start address of Tx Event FIFO in Message RAM (32-bit word address, see Figure 2).</description>
21762                  <bitRange>[15:2]</bitRange>
21763                  <access>read-write</access>
21764                </field>
21765                <field>
21766                  <name>EFS</name>
21767                  <description>Event FIFO Size
217680= Tx Event FIFO disabled
217691-32= Number of Tx Event FIFO elements
2177032= Values greater than 32 are interpreted as 32
21771The Tx Event FIFO elements are indexed from 0 to EFS-1</description>
21772                  <bitRange>[21:16]</bitRange>
21773                  <access>read-write</access>
21774                </field>
21775                <field>
21776                  <name>EFWM</name>
21777                  <description>Event FIFO Watermark
217780= Watermark interrupt disabled
217791-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW)
2178032= Watermark interrupt disabled</description>
21781                  <bitRange>[29:24]</bitRange>
21782                  <access>read-write</access>
21783                </field>
21784              </fields>
21785            </register>
21786            <register>
21787              <name>TXEFS</name>
21788              <description>Tx Event FIFO Status</description>
21789              <addressOffset>0xF4</addressOffset>
21790              <size>32</size>
21791              <access>read-only</access>
21792              <resetValue>0x0</resetValue>
21793              <resetMask>0x31F1F3F</resetMask>
21794              <fields>
21795                <field>
21796                  <name>EFFL</name>
21797                  <description>Event FIFO Fill Level
21798Number of elements stored in Tx Event FIFO, range 0 to 32.
21799When the software reading the value immediately after writing to TXEFA.EFAI, this value should be read twice to ensure that the update is reflected.</description>
21800                  <bitRange>[5:0]</bitRange>
21801                  <access>read-only</access>
21802                </field>
21803                <field>
21804                  <name>EFGI</name>
21805                  <description>Event FIFO Get Index
21806Tx Event FIFO read index pointer, range 0 to 31.
21807This field is updated by the software writing to TXEFA.EFAI.
21808When the software reading the value immediately after writing to TXEFA.EFAI, this value should be read twice to ensure that the update is reflected.</description>
21809                  <bitRange>[12:8]</bitRange>
21810                  <access>read-only</access>
21811                </field>
21812                <field>
21813                  <name>EFPI</name>
21814                  <description>Event FIFO Put Index
21815Tx Event FIFO write index pointer, range 0 to 31.</description>
21816                  <bitRange>[20:16]</bitRange>
21817                  <access>read-only</access>
21818                </field>
21819                <field>
21820                  <name>EFF</name>
21821                  <description>Event FIFO Full
218220= Tx Event FIFO not full
218231= Tx Event FIFO full</description>
21824                  <bitRange>[24:24]</bitRange>
21825                  <access>read-only</access>
21826                </field>
21827                <field>
21828                  <name>TEFL</name>
21829                  <description>Tx Event FIFO Element Lost
21830This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset.
218310= No Tx Event FIFO element lost
218321= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero.</description>
21833                  <bitRange>[25:25]</bitRange>
21834                  <access>read-only</access>
21835                </field>
21836              </fields>
21837            </register>
21838            <register>
21839              <name>TXEFA</name>
21840              <description>Tx Event FIFO Acknowledge</description>
21841              <addressOffset>0xF8</addressOffset>
21842              <size>32</size>
21843              <access>read-write</access>
21844              <resetValue>0x0</resetValue>
21845              <resetMask>0x1F</resetMask>
21846              <fields>
21847                <field>
21848                  <name>EFAI</name>
21849                  <description>Event FIFO Acknowledge Index
21850After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write
21851the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get
21852Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL.</description>
21853                  <bitRange>[4:0]</bitRange>
21854                  <access>read-write</access>
21855                </field>
21856              </fields>
21857            </register>
21858            <register>
21859              <name>TTTMC</name>
21860              <description>TT Trigger Memory Configuration</description>
21861              <addressOffset>0x100</addressOffset>
21862              <size>32</size>
21863              <access>read-write</access>
21864              <resetValue>0x0</resetValue>
21865              <resetMask>0x7FFFFC</resetMask>
21866              <fields>
21867                <field>
21868                  <name>TMSA</name>
21869                  <description>Trigger Memory Start Address
21870Start address of Trigger Memory in Message RAM (32-bit word address, see Figure 2).</description>
21871                  <bitRange>[15:2]</bitRange>
21872                  <access>read-write</access>
21873                </field>
21874                <field>
21875                  <name>TME</name>
21876                  <description>Trigger Memory Elements
218770= No Trigger Memory
218781-64= Number of Trigger Memory elements
2187964= Values greater than 64 are interpreted as 64</description>
21880                  <bitRange>[22:16]</bitRange>
21881                  <access>read-write</access>
21882                </field>
21883              </fields>
21884            </register>
21885            <register>
21886              <name>TTRMC</name>
21887              <description>TT Reference Message Configuration</description>
21888              <addressOffset>0x104</addressOffset>
21889              <size>32</size>
21890              <access>read-write</access>
21891              <resetValue>0x0</resetValue>
21892              <resetMask>0xDFFFFFFF</resetMask>
21893              <fields>
21894                <field>
21895                  <name>RID</name>
21896                  <description>Reference Identifier
21897Identifier transmitted with reference message and used for reference message filtering. Standard or
21898extended reference identifier depending on bit XTD. A standard identifier has to be written to
21899ID[28:18].</description>
21900                  <bitRange>[28:0]</bitRange>
21901                  <access>read-write</access>
21902                </field>
21903                <field>
21904                  <name>XTD</name>
21905                  <description>Extended Identifier
219060= 11-bit standard identifier
219071= 29-bit extended identifier</description>
21908                  <bitRange>[30:30]</bitRange>
21909                  <access>read-write</access>
21910                </field>
21911                <field>
21912                  <name>RMPS</name>
21913                  <description>Reference Message Payload Select
21914Ignored in case of time slaves.
219150= Reference message has no additional payload
219161= The following elements are taken from Tx Buffer 0:
21917Message Marker MM, Event FIFO Control EFC, Data Length Code DLC, Data Bytes DB
21918Level 1: bytes 2-8, Level 0,2: bytes 5-8)</description>
21919                  <bitRange>[31:31]</bitRange>
21920                  <access>read-write</access>
21921                </field>
21922              </fields>
21923            </register>
21924            <register>
21925              <name>TTOCF</name>
21926              <description>TT Operation Configuration</description>
21927              <addressOffset>0x108</addressOffset>
21928              <size>32</size>
21929              <access>read-write</access>
21930              <resetValue>0x10000</resetValue>
21931              <resetMask>0x7FFFFFB</resetMask>
21932              <fields>
21933                <field>
21934                  <name>OM</name>
21935                  <description>Operation Mode
2193600= Event-driven CAN communication, default
2193701= TTCAN level 1
2193810= TTCAN level 2
2193911= TTCAN level 0</description>
21940                  <bitRange>[1:0]</bitRange>
21941                  <access>read-write</access>
21942                </field>
21943                <field>
21944                  <name>GEN</name>
21945                  <description>Gap Enable
219460= Strictly time-triggered operation
219471= External event-synchronized time-triggered operation</description>
21948                  <bitRange>[3:3]</bitRange>
21949                  <access>read-write</access>
21950                </field>
21951                <field>
21952                  <name>TM</name>
21953                  <description>Time Master
219540= Time Master function disabled
219551= Potential Time Master</description>
21956                  <bitRange>[4:4]</bitRange>
21957                  <access>read-write</access>
21958                </field>
21959                <field>
21960                  <name>LDSDL</name>
21961                  <description>LD of Synchronization Deviation Limit
21962The Synchronization Deviation Limit SDL is configured by its dual logarithm LDSDL with SDL =
219632(LDSDL + 5). It should not exceed the clock tolerance given by the CAN bit timing configuration.
219640x0-7 LD of Synchronization Deviation Limit (SDL &lt;= 32...4096)</description>
21965                  <bitRange>[7:5]</bitRange>
21966                  <access>read-write</access>
21967                </field>
21968                <field>
21969                  <name>IRTO</name>
21970                  <description>Initial Reference Trigger Offset
219710x00-7F Positive offset, range from 0 to 127</description>
21972                  <bitRange>[14:8]</bitRange>
21973                  <access>read-write</access>
21974                </field>
21975                <field>
21976                  <name>EECS</name>
21977                  <description>Enable External Clock Synchronization
21978If enabled, TUR configuration (TURCF.NCL only) may be updated during TTCAN operation.
219790= External clock synchronization in TTCAN Level 0,2 disabled
219801= External clock synchronization in TTCAN Level 0,2 enabled</description>
21981                  <bitRange>[15:15]</bitRange>
21982                  <access>read-write</access>
21983                </field>
21984                <field>
21985                  <name>AWL</name>
21986                  <description>Application Watchdog Limit
21987The application watchdog can be disabled by programming AWL to 0x00.
219880x00-FF Maximum time after which the application has to serve the application watchdog.
21989The application watchdog is incremented once each 256 NTUs.</description>
21990                  <bitRange>[23:16]</bitRange>
21991                  <access>read-write</access>
21992                </field>
21993                <field>
21994                  <name>EGTF</name>
21995                  <description>Enable Global Time Filtering
219960= Global time filtering in TTCAN Level 0,2 is disabled
219971= Global time filtering in TTCAN Level 0,2 is enabled</description>
21998                  <bitRange>[24:24]</bitRange>
21999                  <access>read-write</access>
22000                </field>
22001                <field>
22002                  <name>ECC</name>
22003                  <description>Enable Clock Calibration
220040= Automatic clock calibration in TTCAN Level 0,2 is disabled
220051= Automatic clock calibration in TTCAN Level 0,2 is enabled</description>
22006                  <bitRange>[25:25]</bitRange>
22007                  <access>read-write</access>
22008                </field>
22009                <field>
22010                  <name>EVTP</name>
22011                  <description>Event Trigger Polarity
220120= Rising edge trigger
220131= Falling edge trigger</description>
22014                  <bitRange>[26:26]</bitRange>
22015                  <access>read-write</access>
22016                </field>
22017              </fields>
22018            </register>
22019            <register>
22020              <name>TTMLM</name>
22021              <description>TT Matrix Limits</description>
22022              <addressOffset>0x10C</addressOffset>
22023              <size>32</size>
22024              <access>read-write</access>
22025              <resetValue>0x0</resetValue>
22026              <resetMask>0xFFF0FFF</resetMask>
22027              <fields>
22028                <field>
22029                  <name>CCM</name>
22030                  <description>N/A</description>
22031                  <bitRange>[5:0]</bitRange>
22032                  <access>read-write</access>
22033                </field>
22034                <field>
22035                  <name>CSS</name>
22036                  <description>N/A</description>
22037                  <bitRange>[7:6]</bitRange>
22038                  <access>read-write</access>
22039                </field>
22040                <field>
22041                  <name>TXEW</name>
22042                  <description>Tx Enable Window
220430x0-F Length of Tx enable window, 1-16 NTU cycles</description>
22044                  <bitRange>[11:8]</bitRange>
22045                  <access>read-write</access>
22046                </field>
22047                <field>
22048                  <name>ENTT</name>
22049                  <description>Expected Number of Tx Triggers
220500x000-FFF Expected number of Tx Triggers in one Matrix Cycle</description>
22051                  <bitRange>[27:16]</bitRange>
22052                  <access>read-write</access>
22053                </field>
22054              </fields>
22055            </register>
22056            <register>
22057              <name>TURCF</name>
22058              <description>TUR Configuration</description>
22059              <addressOffset>0x110</addressOffset>
22060              <size>32</size>
22061              <access>read-write</access>
22062              <resetValue>0x10000000</resetValue>
22063              <resetMask>0xBFFFFFFF</resetMask>
22064              <fields>
22065                <field>
22066                  <name>NCL</name>
22067                  <description>Numerator Configuration Low
22068Write access to the TUR Numerator Configuration Low is only possible during configuration with
22069TURCF.ELT = '0' or if TTOCF.EECS (external clock synchronization enabled) is set. When a new
22070value for NCL is written outside TT Configuration Mode, the new value takes effect when
22071TTOST.WECS is cleared to '0'. NCL is locked TTOST.WECS is '1'.
220720x0000-FFFF Numerator Configuration Low</description>
22073                  <bitRange>[15:0]</bitRange>
22074                  <access>read-write</access>
22075                </field>
22076                <field>
22077                  <name>DC</name>
22078                  <description>Denominator Configuration
220790x0000 Illegal value
220800x0001-3FFF Denominator Configuration</description>
22081                  <bitRange>[29:16]</bitRange>
22082                  <access>read-write</access>
22083                </field>
22084                <field>
22085                  <name>ELT</name>
22086                  <description>Enable Local Time
220870= Local time is stopped, default
220881= Local time is enabled</description>
22089                  <bitRange>[31:31]</bitRange>
22090                  <access>read-write</access>
22091                </field>
22092              </fields>
22093            </register>
22094            <register>
22095              <name>TTOCN</name>
22096              <description>TT Operation Control</description>
22097              <addressOffset>0x114</addressOffset>
22098              <size>32</size>
22099              <access>read-write</access>
22100              <resetValue>0x0</resetValue>
22101              <resetMask>0xBFFF</resetMask>
22102              <fields>
22103                <field>
22104                  <name>SGT</name>
22105                  <description>Set Global time
22106Writing a '1' to SGT sets TTOST.WGDT if the node is the actual Time Master. SGT is reset after one
22107Host clock period. The global time preset takes effect when the node transmits the next reference
22108message with the Master_Ref_Mark modified by the preset value written to TTGTP.</description>
22109                  <bitRange>[0:0]</bitRange>
22110                  <access>read-write</access>
22111                </field>
22112                <field>
22113                  <name>ECS</name>
22114                  <description>External Clock Synchronization
22115Writing a '1' to ECS sets TTOST.WECS if the node is the actual Time Master. ECS is reset after one
22116Host clock period. The external clock synchronization takes effect at the start of the next basic cycle.</description>
22117                  <bitRange>[1:1]</bitRange>
22118                  <access>read-write</access>
22119                </field>
22120                <field>
22121                  <name>SWP</name>
22122                  <description>Stop Watch Polarity
221230= Rising edge trigger
221241= Falling edge trigger</description>
22125                  <bitRange>[2:2]</bitRange>
22126                  <access>read-write</access>
22127                </field>
22128                <field>
22129                  <name>SWS</name>
22130                  <description>Stop Watch Source
2213100= Stop Watch disabled
2213201= Actual value of cycle time is copied to TTCPT.SWV
2213310= Actual value of local time is copied to TTCPT.SWV
2213411= Actual value of global time is copied to TTCPT.SWV</description>
22135                  <bitRange>[4:3]</bitRange>
22136                  <access>read-write</access>
22137                </field>
22138                <field>
22139                  <name>RTIE</name>
22140                  <description>Register Time Mark Interrupt Pulse Enable
22141Register time mark interrupts are configured by register TTTMK. A register time mark interrupt pulse
22142with the length of one NTU is generated when the time referenced by TTOCN.TMC (cycle, local, or
22143global) equals TTTMK.TM, independent of the synchronization state.
221440= Register Time Mark Interrupt output m_ttcan_rtp disabled
221451= Register Time Mark Interrupt output m_ttcan_rtp enabled</description>
22146                  <bitRange>[5:5]</bitRange>
22147                  <access>read-write</access>
22148                </field>
22149                <field>
22150                  <name>TMC</name>
22151                  <description>Register Time Mark Compare
2215200= No Register Time Mark Interrupt generated
2215301= Register Time Mark Interrupt if Time Mark = cycle time
2215410= Register Time Mark Interrupt if Time Mark = local time
2215511= Register Time Mark Interrupt if Time Mark = global time</description>
22156                  <bitRange>[7:6]</bitRange>
22157                  <access>read-write</access>
22158                </field>
22159                <field>
22160                  <name>TTIE</name>
22161                  <description>Trigger Time Mark Interrupt Pulse Enable
22162External time mark events are configured by trigger memory element TMEX (see Section 2.4.7). A
22163trigger time mark interrupt pulse is generated when the trigger memory element becomes active,
22164and the M_TTCAN is in synchronization state In_Schedule or In_Gap.
221650= Trigger Time Mark Interrupt output m_ttcan_tmp disabled
221661= Trigger Time Mark Interrupt output m_ttcan_tmp enabled</description>
22167                  <bitRange>[8:8]</bitRange>
22168                  <access>read-write</access>
22169                </field>
22170                <field>
22171                  <name>GCS</name>
22172                  <description>Gap Control Select
221730= Gap control independent from m_ttcan_evt
221741= Gap control by input pin m_ttcan_evt</description>
22175                  <bitRange>[9:9]</bitRange>
22176                  <access>read-write</access>
22177                </field>
22178                <field>
22179                  <name>FGP</name>
22180                  <description>Finish Gap
22181Set by the CPU, reset by each reference message
221820= No reference message requested
221831= Application requested start of reference message</description>
22184                  <bitRange>[10:10]</bitRange>
22185                  <access>read-write</access>
22186                </field>
22187                <field>
22188                  <name>TMG</name>
22189                  <description>Time Mark Gap
221900= Reset by each reference message
221911= Next reference message started when Register Time Mark interrupt TTIR.RTMI is activated</description>
22192                  <bitRange>[11:11]</bitRange>
22193                  <access>read-write</access>
22194                </field>
22195                <field>
22196                  <name>NIG</name>
22197                  <description>Next is Gap
22198This bit can only be set when the M_TTCAN is the actual Time Master and when it is configured for
22199external event-synchronized time-triggered operation (TTOCF.GEN = '1')
222000= No action, reset by reception of any reference message
222011= Transmit next reference message with Next_is_Gap = '1'</description>
22202                  <bitRange>[12:12]</bitRange>
22203                  <access>read-write</access>
22204                </field>
22205                <field>
22206                  <name>ESCN</name>
22207                  <description>External Synchronization Control
22208If enabled the M_TTCAN synchronizes its cycle time phase to an external event signaled by a rising
22209edge at pin m_ttcan_evt (see Section 4.11).
222100= External synchronization disabled
222111= External synchronization enabled</description>
22212                  <bitRange>[13:13]</bitRange>
22213                  <access>read-write</access>
22214                </field>
22215                <field>
22216                  <name>LCKC</name>
22217                  <description>TT Operation Control Register Locked
22218Set by a write access to register TTOCN. Reset when the updated configuration has been
22219synchronized into the CAN clock domain.
222200= Write access to TTOCN enabled
222211= Write access to TTOCN locked</description>
22222                  <bitRange>[15:15]</bitRange>
22223                  <access>read-only</access>
22224                </field>
22225              </fields>
22226            </register>
22227            <register>
22228              <name>TTGTP</name>
22229              <description>TT Global Time Preset</description>
22230              <addressOffset>0x118</addressOffset>
22231              <size>32</size>
22232              <access>read-write</access>
22233              <resetValue>0x0</resetValue>
22234              <resetMask>0xFFFFFFFF</resetMask>
22235              <fields>
22236                <field>
22237                  <name>TP</name>
22238                  <description>N/A</description>
22239                  <bitRange>[15:0]</bitRange>
22240                  <access>read-write</access>
22241                </field>
22242                <field>
22243                  <name>CTP</name>
22244                  <description>Cycle Time Target Phase
22245CTP is write-protected while TTOCN.ESCN or TTOST.SPL are set (see Section 4.11).
222460x0000-FFFF Defines target value of cycle time when a rising edge of m_ttcan_evt is expected</description>
22247                  <bitRange>[31:16]</bitRange>
22248                  <access>read-write</access>
22249                </field>
22250              </fields>
22251            </register>
22252            <register>
22253              <name>TTTMK</name>
22254              <description>TT Time Mark</description>
22255              <addressOffset>0x11C</addressOffset>
22256              <size>32</size>
22257              <access>read-write</access>
22258              <resetValue>0x0</resetValue>
22259              <resetMask>0x807FFFFF</resetMask>
22260              <fields>
22261                <field>
22262                  <name>TM_</name>
22263                  <description>Time Mark
222640x0000-FFFF Time Mark</description>
22265                  <bitRange>[15:0]</bitRange>
22266                  <access>read-write</access>
22267                </field>
22268                <field>
22269                  <name>TICC</name>
22270                  <description>Time Mark Cycle Code
22271Cycle count for which the time mark is valid.
222720b000000x valid for all cycles
222730b000001c valid every second cycle at cycle count mod2 = c
222740b00001cc valid every fourth cycle at cycle count mod4 = cc
222750b0001ccc valid every eighth cycle at cycle count mod8 = ccc
222760b001cccc valid every sixteenth cycle at cycle count mod16 = cccc
222770b01ccccc valid every thirty-second cycle at cycle count mod32 = ccccc
222780b1cccccc valid every sixty-fourth cycle at cycle count mod64 = cccccc</description>
22279                  <bitRange>[22:16]</bitRange>
22280                  <access>read-write</access>
22281                </field>
22282                <field>
22283                  <name>LCKM</name>
22284                  <description>TT Time Mark Register Locked
22285Always set by a write access to registers TTOCN. Set by write access to register TTTMK when
22286TTOCN.TMC != '00'. Reset when the registers have been synchronized into the CAN clock domain.
222870= Write access to TTTMK enabled
222881= Write access to TTTMK locked</description>
22289                  <bitRange>[31:31]</bitRange>
22290                  <access>read-only</access>
22291                </field>
22292              </fields>
22293            </register>
22294            <register>
22295              <name>TTIR</name>
22296              <description>TT Interrupt Register</description>
22297              <addressOffset>0x120</addressOffset>
22298              <size>32</size>
22299              <access>read-write</access>
22300              <resetValue>0x0</resetValue>
22301              <resetMask>0x7FFFF</resetMask>
22302              <fields>
22303                <field>
22304                  <name>SBC</name>
22305                  <description>Start of Basic Cycle
223060= No Basic Cycle started since bit has been reset
223071= Basic Cycle started</description>
22308                  <bitRange>[0:0]</bitRange>
22309                  <access>read-write</access>
22310                </field>
22311                <field>
22312                  <name>SMC</name>
22313                  <description>Start of Matrix Cycle
223140= No Matrix Cycle started since bit has been reset
223151= Matrix Cycle started</description>
22316                  <bitRange>[1:1]</bitRange>
22317                  <access>read-write</access>
22318                </field>
22319                <field>
22320                  <name>CSM_</name>
22321                  <description>Change of Synchronization Mode
223220= No change in master to slave relation or schedule synchronization
223231= Master to slave relation or schedule synchronization changed,
22324also set when TTOST.SPL is reset</description>
22325                  <bitRange>[2:2]</bitRange>
22326                  <access>read-write</access>
22327                </field>
22328                <field>
22329                  <name>SOG</name>
22330                  <description>Start of Gap
223310= No reference message seen with Next_is_Gap bit set
223321= Reference message with Next_is_Gap bit set becomes valid</description>
22333                  <bitRange>[3:3]</bitRange>
22334                  <access>read-write</access>
22335                </field>
22336                <field>
22337                  <name>RTMI</name>
22338                  <description>Register Time Mark Interrupt
22339Set when time referenced by TTOCN.TMC (cycle, local, or global) equals TTTMK.TM, independent
22340of the synchronization state.
223410= Time mark not reached
223421= Time mark reached</description>
22343                  <bitRange>[4:4]</bitRange>
22344                  <access>read-write</access>
22345                </field>
22346                <field>
22347                  <name>TTMI</name>
22348                  <description>Trigger Time Mark Event Internal
22349Internal time mark events are configured by trigger memory element TMIN (see Section 2.4.7). Set
22350when the trigger memory element becomes active, and the M_TTCAN is in synchronization state
22351In_Gap or In_Schedule.
223520= Time mark not reached
223531= Time mark reached (Level 0: cycle time TTOCF.IRTO * 0x200)</description>
22354                  <bitRange>[5:5]</bitRange>
22355                  <access>read-write</access>
22356                </field>
22357                <field>
22358                  <name>SWE</name>
22359                  <description>Stop Watch Event
223600= No rising/falling edge at stop watch trigger pin m_ttcan_swt detected
223611= Rising/falling edge at stop watch trigger pin m_ttcan_swt detected</description>
22362                  <bitRange>[6:6]</bitRange>
22363                  <access>read-write</access>
22364                </field>
22365                <field>
22366                  <name>GTW</name>
22367                  <description>Global Time Wrap
223680= No global time wrap occurred
223691= Global time wrap from 0xFFFF to 0x0000 occurred</description>
22370                  <bitRange>[7:7]</bitRange>
22371                  <access>read-write</access>
22372                </field>
22373                <field>
22374                  <name>GTD</name>
22375                  <description>Global Time Discontinuity
223760= No discontinuity of global time
223771= Discontinuity of global time</description>
22378                  <bitRange>[8:8]</bitRange>
22379                  <access>read-write</access>
22380                </field>
22381                <field>
22382                  <name>GTE</name>
22383                  <description>Global Time Error
22384Synchronization deviation SD exceeds limit specified by TTOCF.LDSDL, TTCAN Level 0,2 only.
223850= Synchronization deviation within limit
223861= Synchronization deviation exceeded limit</description>
22387                  <bitRange>[9:9]</bitRange>
22388                  <access>read-write</access>
22389                </field>
22390                <field>
22391                  <name>TXU</name>
22392                  <description>Tx Count Underflow
223930= Number of Tx Trigger as expected
223941= Less Tx trigger than expected in one matrix cycle</description>
22395                  <bitRange>[10:10]</bitRange>
22396                  <access>read-write</access>
22397                </field>
22398                <field>
22399                  <name>TXO</name>
22400                  <description>Tx Count Overflow
224010= Number of Tx Trigger as expected
224021= More Tx trigger than expected in one matrix cycle</description>
22403                  <bitRange>[11:11]</bitRange>
22404                  <access>read-write</access>
22405                </field>
22406                <field>
22407                  <name>SE1</name>
22408                  <description>Scheduling Error 1
224090= No scheduling error 1
224101= Scheduling error 1 occurred</description>
22411                  <bitRange>[12:12]</bitRange>
22412                  <access>read-write</access>
22413                </field>
22414                <field>
22415                  <name>SE2</name>
22416                  <description>Scheduling Error 2
224170= No scheduling error 2
224181= Scheduling error 2 occurred</description>
22419                  <bitRange>[13:13]</bitRange>
22420                  <access>read-write</access>
22421                </field>
22422                <field>
22423                  <name>ELC</name>
22424                  <description>Error Level Changed
22425Not set when error level changed during initialization.
224260= No change in error level
224271= Error level changed</description>
22428                  <bitRange>[14:14]</bitRange>
22429                  <access>read-write</access>
22430                </field>
22431                <field>
22432                  <name>IWT</name>
22433                  <description>Initialization Watch Trigger
22434The initialization is restarted by resetting IWT.
224350= No missing reference message during system startup
224361= No system startup due to missing reference message</description>
22437                  <bitRange>[15:15]</bitRange>
22438                  <access>read-write</access>
22439                </field>
22440                <field>
22441                  <name>WT</name>
22442                  <description>Watch Trigger
224430= No missing reference message
224441= Missing reference message (Level 0: cycle time 0xFF00)</description>
22445                  <bitRange>[16:16]</bitRange>
22446                  <access>read-write</access>
22447                </field>
22448                <field>
22449                  <name>AW</name>
22450                  <description>Application Watchdog
224510= Application watchdog served in time
224521= Application watchdog not served in time</description>
22453                  <bitRange>[17:17]</bitRange>
22454                  <access>read-write</access>
22455                </field>
22456                <field>
22457                  <name>CER</name>
22458                  <description>Configuration Error
22459Trigger out of order.
224600= No error found in trigger list
224611= Error found in trigger list</description>
22462                  <bitRange>[18:18]</bitRange>
22463                  <access>read-write</access>
22464                </field>
22465              </fields>
22466            </register>
22467            <register>
22468              <name>TTIE</name>
22469              <description>TT Interrupt Enable</description>
22470              <addressOffset>0x124</addressOffset>
22471              <size>32</size>
22472              <access>read-write</access>
22473              <resetValue>0x0</resetValue>
22474              <resetMask>0x7FFFF</resetMask>
22475              <fields>
22476                <field>
22477                  <name>SBCE</name>
22478                  <description>Start of Basic Cycle Interrupt Enable</description>
22479                  <bitRange>[0:0]</bitRange>
22480                  <access>read-write</access>
22481                </field>
22482                <field>
22483                  <name>SMCE</name>
22484                  <description>Start of Matrix Cycle Interrupt Enable</description>
22485                  <bitRange>[1:1]</bitRange>
22486                  <access>read-write</access>
22487                </field>
22488                <field>
22489                  <name>CSME</name>
22490                  <description>Change of Synchronization Mode Interrupt Enable</description>
22491                  <bitRange>[2:2]</bitRange>
22492                  <access>read-write</access>
22493                </field>
22494                <field>
22495                  <name>SOGE</name>
22496                  <description>Start of Gap Interrupt Enable</description>
22497                  <bitRange>[3:3]</bitRange>
22498                  <access>read-write</access>
22499                </field>
22500                <field>
22501                  <name>RTMIE</name>
22502                  <description>Register Time Mark Interrupt Enable</description>
22503                  <bitRange>[4:4]</bitRange>
22504                  <access>read-write</access>
22505                </field>
22506                <field>
22507                  <name>TTMIE</name>
22508                  <description>Trigger Time Mark Event Internal Enable</description>
22509                  <bitRange>[5:5]</bitRange>
22510                  <access>read-write</access>
22511                </field>
22512                <field>
22513                  <name>SWEE</name>
22514                  <description>Stop Watch Event Interrupt Enable</description>
22515                  <bitRange>[6:6]</bitRange>
22516                  <access>read-write</access>
22517                </field>
22518                <field>
22519                  <name>GTWE</name>
22520                  <description>Global Time Wrap Interrupt Enable</description>
22521                  <bitRange>[7:7]</bitRange>
22522                  <access>read-write</access>
22523                </field>
22524                <field>
22525                  <name>GTDE</name>
22526                  <description>Global Time Discontinuity Interrupt Enable</description>
22527                  <bitRange>[8:8]</bitRange>
22528                  <access>read-write</access>
22529                </field>
22530                <field>
22531                  <name>GTEE</name>
22532                  <description>Global Time Error Interrupt Enable</description>
22533                  <bitRange>[9:9]</bitRange>
22534                  <access>read-write</access>
22535                </field>
22536                <field>
22537                  <name>TXUE</name>
22538                  <description>Tx Count Underflow Interrupt Enable</description>
22539                  <bitRange>[10:10]</bitRange>
22540                  <access>read-write</access>
22541                </field>
22542                <field>
22543                  <name>TXOE</name>
22544                  <description>Tx Count Overflow Interrupt Enable</description>
22545                  <bitRange>[11:11]</bitRange>
22546                  <access>read-write</access>
22547                </field>
22548                <field>
22549                  <name>SE1E</name>
22550                  <description>Scheduling Error 1 Interrupt Enable</description>
22551                  <bitRange>[12:12]</bitRange>
22552                  <access>read-write</access>
22553                </field>
22554                <field>
22555                  <name>SE2E</name>
22556                  <description>Scheduling Error 2 Interrupt Enable</description>
22557                  <bitRange>[13:13]</bitRange>
22558                  <access>read-write</access>
22559                </field>
22560                <field>
22561                  <name>ELCE</name>
22562                  <description>Change Error Level Interrupt Enable</description>
22563                  <bitRange>[14:14]</bitRange>
22564                  <access>read-write</access>
22565                </field>
22566                <field>
22567                  <name>IWTE</name>
22568                  <description>Initialization Watch Trigger Interrupt Enable</description>
22569                  <bitRange>[15:15]</bitRange>
22570                  <access>read-write</access>
22571                </field>
22572                <field>
22573                  <name>WTE</name>
22574                  <description>Watch Trigger Interrupt Enable</description>
22575                  <bitRange>[16:16]</bitRange>
22576                  <access>read-write</access>
22577                </field>
22578                <field>
22579                  <name>AWE_</name>
22580                  <description>Application Watchdog Interrupt Enable</description>
22581                  <bitRange>[17:17]</bitRange>
22582                  <access>read-write</access>
22583                </field>
22584                <field>
22585                  <name>CERE</name>
22586                  <description>Configuration Error Interrupt Enable</description>
22587                  <bitRange>[18:18]</bitRange>
22588                  <access>read-write</access>
22589                </field>
22590              </fields>
22591            </register>
22592            <register>
22593              <name>TTILS</name>
22594              <description>TT Interrupt Line Select</description>
22595              <addressOffset>0x128</addressOffset>
22596              <size>32</size>
22597              <access>read-write</access>
22598              <resetValue>0x0</resetValue>
22599              <resetMask>0x7FFFF</resetMask>
22600              <fields>
22601                <field>
22602                  <name>SBCL</name>
22603                  <description>Start of Basic Cycle Interrupt Line</description>
22604                  <bitRange>[0:0]</bitRange>
22605                  <access>read-write</access>
22606                </field>
22607                <field>
22608                  <name>SMCL</name>
22609                  <description>Start of Matrix Cycle Interrupt Line</description>
22610                  <bitRange>[1:1]</bitRange>
22611                  <access>read-write</access>
22612                </field>
22613                <field>
22614                  <name>CSML</name>
22615                  <description>Change of Synchronization Mode Interrupt Line</description>
22616                  <bitRange>[2:2]</bitRange>
22617                  <access>read-write</access>
22618                </field>
22619                <field>
22620                  <name>SOGL</name>
22621                  <description>Start of Gap Interrupt Line</description>
22622                  <bitRange>[3:3]</bitRange>
22623                  <access>read-write</access>
22624                </field>
22625                <field>
22626                  <name>RTMIL</name>
22627                  <description>Register Time Mark Interrupt Line</description>
22628                  <bitRange>[4:4]</bitRange>
22629                  <access>read-write</access>
22630                </field>
22631                <field>
22632                  <name>TTMIL</name>
22633                  <description>Trigger Time Mark Event Internal Line</description>
22634                  <bitRange>[5:5]</bitRange>
22635                  <access>read-write</access>
22636                </field>
22637                <field>
22638                  <name>SWEL</name>
22639                  <description>Stop Watch Event Interrupt Line</description>
22640                  <bitRange>[6:6]</bitRange>
22641                  <access>read-write</access>
22642                </field>
22643                <field>
22644                  <name>GTWL</name>
22645                  <description>Global Time Wrap Interrupt Line</description>
22646                  <bitRange>[7:7]</bitRange>
22647                  <access>read-write</access>
22648                </field>
22649                <field>
22650                  <name>GTDL</name>
22651                  <description>Global Time Discontinuity Interrupt Line</description>
22652                  <bitRange>[8:8]</bitRange>
22653                  <access>read-write</access>
22654                </field>
22655                <field>
22656                  <name>GTEL</name>
22657                  <description>Global Time Error Interrupt Line</description>
22658                  <bitRange>[9:9]</bitRange>
22659                  <access>read-write</access>
22660                </field>
22661                <field>
22662                  <name>TXUL</name>
22663                  <description>Tx Count Underflow Interrupt Line</description>
22664                  <bitRange>[10:10]</bitRange>
22665                  <access>read-write</access>
22666                </field>
22667                <field>
22668                  <name>TXOL</name>
22669                  <description>Tx Count Overflow Interrupt Line</description>
22670                  <bitRange>[11:11]</bitRange>
22671                  <access>read-write</access>
22672                </field>
22673                <field>
22674                  <name>SE1L</name>
22675                  <description>Scheduling Error 1 Interrupt Line</description>
22676                  <bitRange>[12:12]</bitRange>
22677                  <access>read-write</access>
22678                </field>
22679                <field>
22680                  <name>SE2L</name>
22681                  <description>Scheduling Error 2 Interrupt Line</description>
22682                  <bitRange>[13:13]</bitRange>
22683                  <access>read-write</access>
22684                </field>
22685                <field>
22686                  <name>ELCL</name>
22687                  <description>Change Error Level Interrupt Line</description>
22688                  <bitRange>[14:14]</bitRange>
22689                  <access>read-write</access>
22690                </field>
22691                <field>
22692                  <name>IWTL</name>
22693                  <description>Initialization Watch Trigger Interrupt Line</description>
22694                  <bitRange>[15:15]</bitRange>
22695                  <access>read-write</access>
22696                </field>
22697                <field>
22698                  <name>WTL</name>
22699                  <description>Watch Trigger Interrupt Line</description>
22700                  <bitRange>[16:16]</bitRange>
22701                  <access>read-write</access>
22702                </field>
22703                <field>
22704                  <name>AWL_</name>
22705                  <description>Application Watchdog Interrupt Line</description>
22706                  <bitRange>[17:17]</bitRange>
22707                  <access>read-write</access>
22708                </field>
22709                <field>
22710                  <name>CERL</name>
22711                  <description>Configuration Error Interrupt Line</description>
22712                  <bitRange>[18:18]</bitRange>
22713                  <access>read-write</access>
22714                </field>
22715              </fields>
22716            </register>
22717            <register>
22718              <name>TTOST</name>
22719              <description>TT Operation Status</description>
22720              <addressOffset>0x12C</addressOffset>
22721              <size>32</size>
22722              <access>read-only</access>
22723              <resetValue>0x80</resetValue>
22724              <resetMask>0xFFC0FFFF</resetMask>
22725              <fields>
22726                <field>
22727                  <name>EL</name>
22728                  <description>Error Level
2272900= Severity 0 - No Error
2273001= Severity 1 - Warning
2273110= Severity 2 - Error
2273211= Severity 3 - Severe Error</description>
22733                  <bitRange>[1:0]</bitRange>
22734                  <access>read-only</access>
22735                </field>
22736                <field>
22737                  <name>MS</name>
22738                  <description>Master State
2273900= Master_Off, no master properties relevant
2274001= Operating as Time Slave
2274110= Operating as Backup Time Master
2274211= Operating as current Time Master</description>
22743                  <bitRange>[3:2]</bitRange>
22744                  <access>read-only</access>
22745                </field>
22746                <field>
22747                  <name>SYS</name>
22748                  <description>Synchronization State
2274900= Out of Synchronization
2275001= Synchronizing to TTCAN communication
2275110= Schedule suspended by Gap (In_Gap)
2275211= Synchronized to schedule (In_Schedule)</description>
22753                  <bitRange>[5:4]</bitRange>
22754                  <access>read-only</access>
22755                </field>
22756                <field>
22757                  <name>QGTP</name>
22758                  <description>Quality of Global Time Phase
22759Only relevant in TTCAN Level 0 and Level 2, otherwise fixed to '0'.
227600= Global time not valid
227611= Global time in phase with Time Master</description>
22762                  <bitRange>[6:6]</bitRange>
22763                  <access>read-only</access>
22764                </field>
22765                <field>
22766                  <name>QCS</name>
22767                  <description>Quality of Clock Speed
22768Only relevant in TTCAN Level 0 and Level 2, otherwise fixed to '1'.
227690= Local clock speed not synchronized to Time Master clock speed
227701= Synchronization Deviation &lt;= SDL</description>
22771                  <bitRange>[7:7]</bitRange>
22772                  <access>read-only</access>
22773                </field>
22774                <field>
22775                  <name>RTO</name>
22776                  <description>Reference Trigger Offset
22777The Reference Trigger Offset value is a signed integer with a range from -127 (0x81) to 127 (0x7F).
22778There is no notification when the lower limit of -127 is reached. In case the M_TTCAN becomes
22779Time Master (MS[1:0] = '11'), the reset of RTO is delayed due to synchronization between Host and
22780CAN clock domain. For time slaves the value configured by TTOCF.IRTO is read.
227810x00-FF Actual Reference Trigger offset value</description>
22782                  <bitRange>[15:8]</bitRange>
22783                  <access>read-only</access>
22784                </field>
22785                <field>
22786                  <name>WGTD</name>
22787                  <description>Wait for Global Time Discontinuity
227880= No global time preset pending
227891= Node waits for the global time preset to take effect. The bit is reset when the node has transmitted
22790a reference message with Disc_Bit = '1' or after it received a reference message.</description>
22791                  <bitRange>[22:22]</bitRange>
22792                  <access>read-only</access>
22793                </field>
22794                <field>
22795                  <name>GFI</name>
22796                  <description>Gap Finished Indicator
22797Set when the CPU writes TTOCN.FGP, or by a time mark interrupt if TMG = '1', or via input pin
22798m_ttcan_evt if TTOCN.GCS = '1'. Not set by Ref_Trigger_Gap or when Gap is finished by another
22799node sending a reference message.
228000= Reset at the end of each reference message
228011= Gap finished by M_TTCAN</description>
22802                  <bitRange>[23:23]</bitRange>
22803                  <access>read-only</access>
22804                </field>
22805                <field>
22806                  <name>TMP</name>
22807                  <description>Time Master Priority
228080x0-7 Priority of actual Time Master</description>
22809                  <bitRange>[26:24]</bitRange>
22810                  <access>read-only</access>
22811                </field>
22812                <field>
22813                  <name>GSI</name>
22814                  <description>Gap Started Indicator
228150= No Gap in schedule, reset by each reference message and for all time slaves
228161= Gap time after Basic Cycle has started</description>
22817                  <bitRange>[27:27]</bitRange>
22818                  <access>read-only</access>
22819                </field>
22820                <field>
22821                  <name>WFE</name>
22822                  <description>Wait for Event
228230= No Gap announced, reset by a reference message with Next_is_Gap = '0'
228241= Reference message with Next_is_Gap = '1' received</description>
22825                  <bitRange>[28:28]</bitRange>
22826                  <access>read-only</access>
22827                </field>
22828                <field>
22829                  <name>AWE</name>
22830                  <description>Application Watchdog Event
22831The application watchdog is served by reading TTOST. When the watchdog is not served in time,
22832bit AWE is set, all TTCAN communication is stopped, and the M_TTCAN is set into Bus Monitoring
22833Mode.
228340= Application Watchdog served in time
228351= Failed to serve Application Watchdog in time</description>
22836                  <bitRange>[29:29]</bitRange>
22837                  <access>read-only</access>
22838                </field>
22839                <field>
22840                  <name>WECS</name>
22841                  <description>Wait for External Clock Synchronization
228420= No external clock synchronization pending
228431= Node waits for external clock synchronization to take effect. The bit is reset at the start of the
22844next basic cycle.</description>
22845                  <bitRange>[30:30]</bitRange>
22846                  <access>read-only</access>
22847                </field>
22848                <field>
22849                  <name>SPL</name>
22850                  <description>Schedule Phase Lock
22851The bit is valid only when external synchronization is enabled (TTOCN.ESCN = '1'). In this case it
22852signals that the difference between cycle time configured by TTGTP.CTP and the cycle time at the
22853rising edge at pin m_ttcan_evt is less or equal 9 NTU (see Section 4.11).
228540= Phase outside range
228551= Phase inside range</description>
22856                  <bitRange>[31:31]</bitRange>
22857                  <access>read-only</access>
22858                </field>
22859              </fields>
22860            </register>
22861            <register>
22862              <name>TURNA</name>
22863              <description>TUR Numerator Actual</description>
22864              <addressOffset>0x130</addressOffset>
22865              <size>32</size>
22866              <access>read-only</access>
22867              <resetValue>0x10000</resetValue>
22868              <resetMask>0x3FFFF</resetMask>
22869              <fields>
22870                <field>
22871                  <name>NAV</name>
22872                  <description>N/A</description>
22873                  <bitRange>[17:0]</bitRange>
22874                  <access>read-only</access>
22875                </field>
22876              </fields>
22877            </register>
22878            <register>
22879              <name>TTLGT</name>
22880              <description>TT Local &amp; Global Time</description>
22881              <addressOffset>0x134</addressOffset>
22882              <size>32</size>
22883              <access>read-only</access>
22884              <resetValue>0x0</resetValue>
22885              <resetMask>0xFFFFFFFF</resetMask>
22886              <fields>
22887                <field>
22888                  <name>LT</name>
22889                  <description>Local Time
22890Non-fractional part of local time, incremented once each local NTU (see Section 4.5).
228910x0000-FFFF Local time value of TTCAN node</description>
22892                  <bitRange>[15:0]</bitRange>
22893                  <access>read-only</access>
22894                </field>
22895                <field>
22896                  <name>GT</name>
22897                  <description>Global Time
22898Non-fractional part of the sum of the node's local time and its local offset (see Section 4.5).
228990x0000-FFFF Global time value of TTCAN network</description>
22900                  <bitRange>[31:16]</bitRange>
22901                  <access>read-only</access>
22902                </field>
22903              </fields>
22904            </register>
22905            <register>
22906              <name>TTCTC</name>
22907              <description>TT Cycle Time &amp; Count</description>
22908              <addressOffset>0x138</addressOffset>
22909              <size>32</size>
22910              <access>read-only</access>
22911              <resetValue>0x3F0000</resetValue>
22912              <resetMask>0x3FFFFF</resetMask>
22913              <fields>
22914                <field>
22915                  <name>CT</name>
22916                  <description>Cycle Time
22917Non-fractional part of the difference of the node's local time and Ref_Mark (see Section 4.5).
229180x0000-FFFF Cycle time value of TTCAN Basic Cycle</description>
22919                  <bitRange>[15:0]</bitRange>
22920                  <access>read-only</access>
22921                </field>
22922                <field>
22923                  <name>CC</name>
22924                  <description>Cycle Count
229250x00-3F Number of actual Basic Cycle in the System Matrix</description>
22926                  <bitRange>[21:16]</bitRange>
22927                  <access>read-only</access>
22928                </field>
22929              </fields>
22930            </register>
22931            <register>
22932              <name>TTCPT</name>
22933              <description>TT Capture Time</description>
22934              <addressOffset>0x13C</addressOffset>
22935              <size>32</size>
22936              <access>read-only</access>
22937              <resetValue>0x0</resetValue>
22938              <resetMask>0xFFFF003F</resetMask>
22939              <fields>
22940                <field>
22941                  <name>CCV</name>
22942                  <description>Cycle Count Value
22943Cycle count value captured together with SWV.
229440x00-3F Captured cycle count value</description>
22945                  <bitRange>[5:0]</bitRange>
22946                  <access>read-only</access>
22947                </field>
22948                <field>
22949                  <name>SWV</name>
22950                  <description>Stop Watch Value
22951On a rising/falling edge (as configured via TTOCN.SWP) at the Stop Watch Trigger pin m_ttcan_swt, when TTOCN.SWS is != '00' and TTIR.SWE is '0', the actual time value as selected
22952by TTOCN.SWS (cycle, local, global) is copied to SWV and TTIR.SWE will be set to '1'. Capturing of the next stop watch value is enabled by resetting TTIR.SWE.
229530x0000-FFFF Captured Stop Watch value</description>
22954                  <bitRange>[31:16]</bitRange>
22955                  <access>read-only</access>
22956                </field>
22957              </fields>
22958            </register>
22959            <register>
22960              <name>TTCSM</name>
22961              <description>TT Cycle Sync Mark</description>
22962              <addressOffset>0x140</addressOffset>
22963              <size>32</size>
22964              <access>read-only</access>
22965              <resetValue>0x0</resetValue>
22966              <resetMask>0xFFFF</resetMask>
22967              <fields>
22968                <field>
22969                  <name>CSM</name>
22970                  <description>Cycle Sync Mark
22971The Cycle Sync Mark is measured</description>
22972                  <bitRange>[15:0]</bitRange>
22973                  <access>read-only</access>
22974                </field>
22975              </fields>
22976            </register>
22977          </cluster>
22978          <register>
22979            <name>RXFTOP_CTL</name>
22980            <description>Receive FIFO Top control</description>
22981            <addressOffset>0x180</addressOffset>
22982            <size>32</size>
22983            <access>read-write</access>
22984            <resetValue>0x0</resetValue>
22985            <resetMask>0x3</resetMask>
22986            <fields>
22987              <field>
22988                <name>F0TPE</name>
22989                <description>FIFO 0 Top Pointer Enable.
22990This enables the FIFO top pointer logic to set the FIFO Top Address (FnTA) and message word counter.
22991This logic is also disabled when the IP is being reconfigured (CCCR.CCE=1).
22992When this logic is disabled a Read from RXFTOP0_DATA is undefined.</description>
22993                <bitRange>[0:0]</bitRange>
22994                <access>read-write</access>
22995              </field>
22996              <field>
22997                <name>F1TPE</name>
22998                <description>FIFO 1 Top Pointer Enable.</description>
22999                <bitRange>[1:1]</bitRange>
23000                <access>read-write</access>
23001              </field>
23002            </fields>
23003          </register>
23004          <register>
23005            <name>RXFTOP0_STAT</name>
23006            <description>Receive FIFO 0 Top Status</description>
23007            <addressOffset>0x1A0</addressOffset>
23008            <size>32</size>
23009            <access>read-only</access>
23010            <resetValue>0x0</resetValue>
23011            <resetMask>0xFFFF</resetMask>
23012            <fields>
23013              <field>
23014                <name>F0TA</name>
23015                <description>Current FIFO 0 Top Address.
23016This is a pointer to the next word in the message buffer defined by the FIFO Start Address (FnSA), Get Index (FnGI), the FIFO message size (FnDS) and the message word counter (FnMWC)
23017FnTA = FnSA + FnGI * msg_size[FnDS] + FnMWC</description>
23018                <bitRange>[15:0]</bitRange>
23019                <access>read-only</access>
23020              </field>
23021            </fields>
23022          </register>
23023          <register>
23024            <name>RXFTOP0_DATA</name>
23025            <description>Receive FIFO 0 Top Data</description>
23026            <addressOffset>0x1A8</addressOffset>
23027            <size>32</size>
23028            <access>read-only</access>
23029            <resetValue>0x0</resetValue>
23030            <resetMask>0x0</resetMask>
23031            <fields>
23032              <field>
23033                <name>F0TD</name>
23034                <description>When enabled (F0TPE=1) read data from MRAM at location FnTA. This register can have a read side effect if the following conditions are met:
23035- M_TTCAN not being reconfigured (CCCR.CCE=0)
23036- FIFO Top Pointer logic is enabled (FnTPE=1)
23037- FIFO is not empty (FnFL!=0)
23038The read side effect is as follows:
23039- if FnMWC pointed to the last word of the message (as indicated by FnDS) then the corresponding message index (FnGI) is automatically acknowledge by a write to FnAI
23040- FnMWC is incremented (or restarted if FnMWC pointed to the last word of the message)
23041- the FIFO top address FnTA is incremented (with FIFO wrap around)
23042When this logic is disabled (F0TPE=0) a Read from this register returns undefined data.</description>
23043                <bitRange>[31:0]</bitRange>
23044                <access>read-only</access>
23045              </field>
23046            </fields>
23047          </register>
23048          <register>
23049            <name>RXFTOP1_STAT</name>
23050            <description>Receive FIFO 1 Top Status</description>
23051            <addressOffset>0x1B0</addressOffset>
23052            <size>32</size>
23053            <access>read-only</access>
23054            <resetValue>0x0</resetValue>
23055            <resetMask>0xFFFF</resetMask>
23056            <fields>
23057              <field>
23058                <name>F1TA</name>
23059                <description>See F0TA description</description>
23060                <bitRange>[15:0]</bitRange>
23061                <access>read-only</access>
23062              </field>
23063            </fields>
23064          </register>
23065          <register>
23066            <name>RXFTOP1_DATA</name>
23067            <description>Receive FIFO 1 Top Data</description>
23068            <addressOffset>0x1B8</addressOffset>
23069            <size>32</size>
23070            <access>read-only</access>
23071            <resetValue>0x0</resetValue>
23072            <resetMask>0x0</resetMask>
23073            <fields>
23074              <field>
23075                <name>F1TD</name>
23076                <description>See F0TD description</description>
23077                <bitRange>[31:0]</bitRange>
23078                <access>read-only</access>
23079              </field>
23080            </fields>
23081          </register>
23082        </cluster>
23083        <register>
23084          <name>CTL</name>
23085          <description>Global CAN control register</description>
23086          <addressOffset>0x1000</addressOffset>
23087          <size>32</size>
23088          <access>read-write</access>
23089          <resetValue>0x0</resetValue>
23090          <resetMask>0x800000FF</resetMask>
23091          <fields>
23092            <field>
23093              <name>STOP_REQ</name>
23094              <description>Clock Stop Request for each TTCAN IP .
23095The m_ttcan_clkstop_req of each TTCAN IP is directly driven by these bits.</description>
23096              <bitRange>[7:0]</bitRange>
23097              <access>read-write</access>
23098            </field>
23099            <field>
23100              <name>MRAM_OFF</name>
23101              <description>MRAM off
231020= Default MRAM on (with MRAM retained in DeepSleep).
231031= Switch MRAM off (not retained) to save power. Before setting this bit all the CAN channels have to be powered down using the STOP_REQ/ACK bits.
23104When the MRAM is off any access attempt to it is considered an address error (as if MRAM_SIZE=0).
23105After switching the MRAM on again software needs to allow for a certain power up time before MRAM can be used, i.e. before STOP_REQ can be de-asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register.
23106
23107To meet S8 platform requirements, MRAM_OFF should be set to 0 prior to transitioning to Hibernate mode.</description>
23108              <bitRange>[31:31]</bitRange>
23109              <access>read-write</access>
23110            </field>
23111          </fields>
23112        </register>
23113        <register>
23114          <name>STATUS</name>
23115          <description>Global CAN status register</description>
23116          <addressOffset>0x1004</addressOffset>
23117          <size>32</size>
23118          <access>read-only</access>
23119          <resetValue>0x0</resetValue>
23120          <resetMask>0xFF</resetMask>
23121          <fields>
23122            <field>
23123              <name>STOP_ACK</name>
23124              <description>Clock Stop Acknowledge for each TTCAN IP.
23125These bits are directly driven by m_ttcan_clkstop_ack of each TTCAN IP.
23126When this bit is set the corresponding TTCAN IP clocks will be gated off, except HCLK will enabled for each AHB write</description>
23127              <bitRange>[7:0]</bitRange>
23128              <access>read-only</access>
23129            </field>
23130          </fields>
23131        </register>
23132        <register>
23133          <name>INTR0_CAUSE</name>
23134          <description>Consolidated interrupt0 cause register</description>
23135          <addressOffset>0x1010</addressOffset>
23136          <size>32</size>
23137          <access>read-only</access>
23138          <resetValue>0x0</resetValue>
23139          <resetMask>0xFF</resetMask>
23140          <fields>
23141            <field>
23142              <name>INT0</name>
23143              <description>Show pending m_ttcan_int0 of each channel</description>
23144              <bitRange>[7:0]</bitRange>
23145              <access>read-only</access>
23146            </field>
23147          </fields>
23148        </register>
23149        <register>
23150          <name>INTR1_CAUSE</name>
23151          <description>Consolidated interrupt1 cause register</description>
23152          <addressOffset>0x1014</addressOffset>
23153          <size>32</size>
23154          <access>read-only</access>
23155          <resetValue>0x0</resetValue>
23156          <resetMask>0xFF</resetMask>
23157          <fields>
23158            <field>
23159              <name>INT1</name>
23160              <description>Show pending m_ttcan_int1 of each channel</description>
23161              <bitRange>[7:0]</bitRange>
23162              <access>read-only</access>
23163            </field>
23164          </fields>
23165        </register>
23166        <register>
23167          <name>TS_CTL</name>
23168          <description>Time Stamp control register</description>
23169          <addressOffset>0x1020</addressOffset>
23170          <size>32</size>
23171          <access>read-write</access>
23172          <resetValue>0x0</resetValue>
23173          <resetMask>0x8000FFFF</resetMask>
23174          <fields>
23175            <field>
23176              <name>PRESCALE</name>
23177              <description>Time Stamp counter prescale value.
23178When enabled divide the Host clock (HCLK) by PRESCALE+1 to create Time Stamp clock ticks.</description>
23179              <bitRange>[15:0]</bitRange>
23180              <access>read-write</access>
23181            </field>
23182            <field>
23183              <name>ENABLED</name>
23184              <description>Counter enable bit
231850 = Count disabled. Stop counting up and keep the counter value
231861 = Count enabled. Start counting up from the current value</description>
23187              <bitRange>[31:31]</bitRange>
23188              <access>read-write</access>
23189            </field>
23190          </fields>
23191        </register>
23192        <register>
23193          <name>TS_CNT</name>
23194          <description>Time Stamp counter value</description>
23195          <addressOffset>0x1024</addressOffset>
23196          <size>32</size>
23197          <access>read-write</access>
23198          <resetValue>0x0</resetValue>
23199          <resetMask>0xFFFF</resetMask>
23200          <fields>
23201            <field>
23202              <name>VALUE</name>
23203              <description>The counter value of the Time Stamp Counter.
23204When enabled this counter will count Time Stamp clock ticks from the pre-scaler.
23205When written this counter and the pre-scaler will reset to 0 (write data is ignored).</description>
23206              <bitRange>[15:0]</bitRange>
23207              <access>read-write</access>
23208            </field>
23209          </fields>
23210        </register>
23211      </registers>
23212    </peripheral>
23213    <peripheral>
23214      <name>TCPWM0</name>
23215      <description>Timer/Counter/PWM</description>
23216      <headerStructName>TCPWM</headerStructName>
23217      <baseAddress>0x404A0000</baseAddress>
23218      <addressBlock>
23219        <offset>0</offset>
23220        <size>131072</size>
23221        <usage>registers</usage>
23222      </addressBlock>
23223      <registers>
23224        <cluster>
23225          <dim>2</dim>
23226          <dimIncrement>32768</dimIncrement>
23227          <name>GRP[%s]</name>
23228          <description>Group of counters</description>
23229          <addressOffset>0x00000000</addressOffset>
23230          <cluster>
23231            <dim>7</dim>
23232            <dimIncrement>128</dimIncrement>
23233            <name>CNT[%s]</name>
23234            <description>Timer/Counter/PWM Counter Module</description>
23235            <addressOffset>0x00000000</addressOffset>
23236            <register>
23237              <name>CTRL</name>
23238              <description>Counter control register</description>
23239              <addressOffset>0x0</addressOffset>
23240              <size>32</size>
23241              <access>read-write</access>
23242              <resetValue>0xF0</resetValue>
23243              <resetMask>0xC73737FF</resetMask>
23244              <fields>
23245                <field>
23246                  <name>AUTO_RELOAD_CC0</name>
23247                  <description>Specifies switching of the CC0 and buffered CC0 values. This field has a function in TIMER, QUAD (QUAD_RANGE0_CMP, QUAD_RANGE1_CMP range modes), SR, PWM, PWM_DT and PWM_PR modes.
23248Timer, QUAD, SR modes:
23249'0': never switch.
23250'1': switch on a compare match 0 event.
23251PWM, PWM_DT, PWM_PR modes:
23252'0: never switch.
23253'1': switch on a terminal count event with an actively pending switch event.</description>
23254                  <bitRange>[0:0]</bitRange>
23255                  <access>read-write</access>
23256                </field>
23257                <field>
23258                  <name>AUTO_RELOAD_CC1</name>
23259                  <description>Specifies switching of the CC1 and buffered CC1 values. This field has a function in TIMER, QUAD (QUAD_RANGE0_CMP, QUAD_RANGE1_CMP range modes), SR, PWM, PWM_DT and PWM_PR modes.
23260Timer, QUAD, SR modes:
23261'0': never switch.
23262'1': switch on a compare match 1 event.
23263PWM, PWM_DT, PWM_PR modes:
23264'0: never switch.
23265'1': switch on a terminal count event with an actively pending switch event.</description>
23266                  <bitRange>[1:1]</bitRange>
23267                  <access>read-write</access>
23268                </field>
23269                <field>
23270                  <name>AUTO_RELOAD_PERIOD</name>
23271                  <description>Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM and PWM_DT modes.
23272'0': never switch.
23273'1': switch on a terminal count event with and actively pending switch event.
23274
23275In QUAD mode, QUAD_RANGE0_CMP range mode this field is used to select the index / wrap-around capture function.
23276'0': Captures on index (reload) event. The counter value is copied to the PERIOD register on an index (reload) event.
23277'1': Captures when COUNTER equals 0 or 0xffff. The counter value is copied to the PERIOD register when COUNTER equals 0 or 0xffff.</description>
23278                  <bitRange>[2:2]</bitRange>
23279                  <access>read-write</access>
23280                </field>
23281                <field>
23282                  <name>AUTO_RELOAD_LINE_SEL</name>
23283                  <description>Specifies switching of the LINE_SEL and LINE_BUFF_SEL values. This field has a function in PWM and PWM_PR modes.
23284'0': never switch.
23285'1': switch on a terminal count event with and actively pending switch event.</description>
23286                  <bitRange>[3:3]</bitRange>
23287                  <access>read-write</access>
23288                </field>
23289                <field>
23290                  <name>CC0_MATCH_UP_EN</name>
23291                  <description>Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode.
23292'0': compare match 0 event generation disabled when counting up
23293'1': compare match 0 event generation enabled when counting up
23294
23295This field has a function in PWM and PWM_DT modes only.</description>
23296                  <bitRange>[4:4]</bitRange>
23297                  <access>read-write</access>
23298                </field>
23299                <field>
23300                  <name>CC0_MATCH_DOWN_EN</name>
23301                  <description>Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode.
23302'0': compare match 0 event generation disabled when counting down
23303'1': compare match 0 event generation enabled when counting down
23304
23305This field has a function in PWM and PWM_DT modes only.</description>
23306                  <bitRange>[5:5]</bitRange>
23307                  <access>read-write</access>
23308                </field>
23309                <field>
23310                  <name>CC1_MATCH_UP_EN</name>
23311                  <description>Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode.
23312'0': compare match 1 event generation disabled when counting up
23313'1': compare match 1 event generation enabled when counting up
23314
23315This field has a function in PWM and PWM_DT modes only.</description>
23316                  <bitRange>[6:6]</bitRange>
23317                  <access>read-write</access>
23318                </field>
23319                <field>
23320                  <name>CC1_MATCH_DOWN_EN</name>
23321                  <description>Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode.
23322'0': compare match 1 event generation disabled when counting down
23323'1': compare match 1 event generation enabled when counting down
23324
23325This field has a function in PWM and PWM_DT modes only.</description>
23326                  <bitRange>[7:7]</bitRange>
23327                  <access>read-write</access>
23328                </field>
23329                <field>
23330                  <name>PWM_IMM_KILL</name>
23331                  <description>Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter').
23332'0': synchronous kill activation. Deactivates the 'dt_line_out' and 'dt_line_compl_out' signals with the next module clock ('active count' pre-scaled 'clk_counter').
23333'1': immediate kill activation. Immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals.
23334
23335This field has a function in PWM, PWM_DT and PWM_PR modes only.</description>
23336                  <bitRange>[8:8]</bitRange>
23337                  <access>read-write</access>
23338                </field>
23339                <field>
23340                  <name>PWM_STOP_ON_KILL</name>
23341                  <description>Specifies whether the counter stops on a kill events:
23342'0': kill event does NOT stop counter.
23343'1': kill event stops counter.
23344
23345This field has a function in PWM, PWM_DT and PWM_PR modes only.</description>
23346                  <bitRange>[9:9]</bitRange>
23347                  <access>read-write</access>
23348                </field>
23349                <field>
23350                  <name>PWM_SYNC_KILL</name>
23351                  <description>Specifies asynchronous/synchronous kill behavior:
23352'1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should  be RISING_EDGE.
23353'0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET.
23354
23355This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.</description>
23356                  <bitRange>[10:10]</bitRange>
23357                  <access>read-write</access>
23358                </field>
23359                <field>
23360                  <name>PWM_DISABLE_MODE</name>
23361                  <description>Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped.
23362
23363Note: The output signal of this selection can be further modified by the immediate kill logic and line_out polarity settings (CTRL.QUAD_ENCODING_MODE).</description>
23364                  <bitRange>[13:12]</bitRange>
23365                  <access>read-write</access>
23366                  <enumeratedValues>
23367                    <enumeratedValue>
23368                      <name>Z</name>
23369                      <description>The behavior is the same is in previous mxtcpwm (version 1).
23370
23371When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are NOT driven by the TCPWM. Instead the port default level configuration applies, e.g. 'Z' (high impedance).
23372Note: This is realized by driving the TCPWM output 'line_out_en' to 0.
23373
23374When the counter is stopped upon a stop event the PWM outputs are deactivated (to the polarity defined by CTL.QUAD_ENCODING_MODE).</description>
23375                      <value>0</value>
23376                    </enumeratedValue>
23377                    <enumeratedValue>
23378                      <name>RETAIN</name>
23379                      <description>When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are driven by the TCPWM.
23380When the counter is disabled or stopped upon a stop event the PWM outputs are retained (keep their previous levels).
23381While the counter is disabled or stopped the PWM outputs can be changed via LINE_SEL (when parameter GRP_SMC_PRESENT = 1).</description>
23382                      <value>1</value>
23383                    </enumeratedValue>
23384                    <enumeratedValue>
23385                      <name>L</name>
23386                      <description>When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are driven by the TCPWM.
23387When the counter is disabled or stopped upon a stop event the PWM output 'line_out' is driven as a fixed '0' and the PWM output 'line_compl_out' is driven as a fixed '1'.</description>
23388                      <value>2</value>
23389                    </enumeratedValue>
23390                    <enumeratedValue>
23391                      <name>H</name>
23392                      <description>When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are driven by the TCPWM.
23393When the counter is disabled or stopped upon a stop event the PWM output 'line_out' is driven as a fixed '1' and the PWM output 'line_compl_out' is driven as a fixed '0'.</description>
23394                      <value>3</value>
23395                    </enumeratedValue>
23396                  </enumeratedValues>
23397                </field>
23398                <field>
23399                  <name>UP_DOWN_MODE</name>
23400                  <description>Determines counter direction.
23401
23402In QUAD mode this field acts as QUAD_RANGE_MODE field selecting between different counter range, reload value and compare / capture behavior.</description>
23403                  <bitRange>[17:16]</bitRange>
23404                  <access>read-write</access>
23405                  <enumeratedValues>
23406                    <enumeratedValue>
23407                      <name>COUNT_UP</name>
23408                      <description>Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.</description>
23409                      <value>0</value>
23410                    </enumeratedValue>
23411                    <enumeratedValue>
23412                      <name>COUNT_DOWN</name>
23413                      <description>Count down (to '0'). An underflow event is generated when  the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.</description>
23414                      <value>1</value>
23415                    </enumeratedValue>
23416                    <enumeratedValue>
23417                      <name>COUNT_UPDN1</name>
23418                      <description>Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.</description>
23419                      <value>2</value>
23420                    </enumeratedValue>
23421                    <enumeratedValue>
23422                      <name>COUNT_UPDN2</name>
23423                      <description>Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).</description>
23424                      <value>3</value>
23425                    </enumeratedValue>
23426                  </enumeratedValues>
23427                </field>
23428                <field>
23429                  <name>ONE_SHOT</name>
23430                  <description>When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.</description>
23431                  <bitRange>[18:18]</bitRange>
23432                  <access>read-write</access>
23433                </field>
23434                <field>
23435                  <name>QUAD_ENCODING_MODE</name>
23436                  <description>In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode.
23437In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'.  Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUAD_ENCODING_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUAD_ENCODING_MODE[1].</description>
23438                  <bitRange>[21:20]</bitRange>
23439                  <access>read-write</access>
23440                  <enumeratedValues>
23441                    <enumeratedValue>
23442                      <name>X1</name>
23443                      <description>X1 encoding (QUAD mode)
23444This encoding is identical with an up / down counting functionality of the following way: Rising edges of input phiA increment or decrement the counter depending on the state of input phiB (direction input).</description>
23445                      <value>0</value>
23446                    </enumeratedValue>
23447                    <enumeratedValue>
23448                      <name>X2</name>
23449                      <description>X2 encoding (QUAD mode)</description>
23450                      <value>1</value>
23451                    </enumeratedValue>
23452                    <enumeratedValue>
23453                      <name>X4</name>
23454                      <description>X4 encoding (QUAD mode)</description>
23455                      <value>2</value>
23456                    </enumeratedValue>
23457                    <enumeratedValue>
23458                      <name>UP_DOWN</name>
23459                      <description>Up / Down rotary counting mode. Input phiA increments the counter, input phiB decrements the counter. The trigger edge detection settings apply.</description>
23460                      <value>3</value>
23461                    </enumeratedValue>
23462                  </enumeratedValues>
23463                </field>
23464                <field>
23465                  <name>MODE</name>
23466                  <description>Counter mode.</description>
23467                  <bitRange>[26:24]</bitRange>
23468                  <access>read-write</access>
23469                  <enumeratedValues>
23470                    <enumeratedValue>
23471                      <name>TIMER</name>
23472                      <description>Timer mode</description>
23473                      <value>0</value>
23474                    </enumeratedValue>
23475                    <enumeratedValue>
23476                      <name>RSVD1</name>
23477                      <description>N/A</description>
23478                      <value>1</value>
23479                    </enumeratedValue>
23480                    <enumeratedValue>
23481                      <name>CAPTURE</name>
23482                      <description>Capture mode</description>
23483                      <value>2</value>
23484                    </enumeratedValue>
23485                    <enumeratedValue>
23486                      <name>QUAD</name>
23487                      <description>Quadrature mode
23488
23489Different encoding modes can be selected by QUAD_ENCODING_MODE including up/down count functionality.
23490Different counter range, reload value and capture behavior can be selected by QUAD_RANGE_MODE (overloaded field UP_DOWN_MODE).</description>
23491                      <value>3</value>
23492                    </enumeratedValue>
23493                    <enumeratedValue>
23494                      <name>PWM</name>
23495                      <description>Pulse width modulation (PWM) mode</description>
23496                      <value>4</value>
23497                    </enumeratedValue>
23498                    <enumeratedValue>
23499                      <name>PWM_DT</name>
23500                      <description>PWM with deadtime insertion mode</description>
23501                      <value>5</value>
23502                    </enumeratedValue>
23503                    <enumeratedValue>
23504                      <name>PWM_PR</name>
23505                      <description>Pseudo random pulse width modulation</description>
23506                      <value>6</value>
23507                    </enumeratedValue>
23508                    <enumeratedValue>
23509                      <name>SR</name>
23510                      <description>Shift register mode.</description>
23511                      <value>7</value>
23512                    </enumeratedValue>
23513                  </enumeratedValues>
23514                </field>
23515                <field>
23516                  <name>DBG_FREEZE_EN</name>
23517                  <description>Specifies the counter behavior in debug mode.
23518'0': The counter operation continues in debug mode.
23519'1': The counter operation freezes in debug mode.</description>
23520                  <bitRange>[30:30]</bitRange>
23521                  <access>read-write</access>
23522                </field>
23523                <field>
23524                  <name>ENABLED</name>
23525                  <description>Counter enable.
23526'0': counter disabled.
23527'1': counter enabled.
23528Counter static configuration information (e.g. CTRL.MODE, all TR_IN_SEL, TR_IN_EDGE_SEL, TR_PWM_CTRL and TR_OUT_SEL register fields) should only be modified when the counter is disabled. When a counter is disabled, command and status information associated to the counter is cleared by HW, this includes:
23529- the associated counter triggers in the CMD register are set to '0'.
23530- the counter's interrupt cause fields in counter's INTR register.
23531- the counter's status fields in counter's STATUS register..
23532- the counter's trigger outputs ('tr_out0' and tr_out1').
23533- the counter's line outputs ('line_out' and 'line_compl_out').</description>
23534                  <bitRange>[31:31]</bitRange>
23535                  <access>read-write</access>
23536                </field>
23537              </fields>
23538            </register>
23539            <register>
23540              <name>STATUS</name>
23541              <description>Counter status register</description>
23542              <addressOffset>0x4</addressOffset>
23543              <size>32</size>
23544              <access>read-only</access>
23545              <resetValue>0x20</resetValue>
23546              <resetMask>0xFFFF8FF1</resetMask>
23547              <fields>
23548                <field>
23549                  <name>DOWN</name>
23550                  <description>When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.</description>
23551                  <bitRange>[0:0]</bitRange>
23552                  <access>read-only</access>
23553                </field>
23554                <field>
23555                  <name>TR_CAPTURE0</name>
23556                  <description>Indicates the actual level of the selected capture 0 trigger.</description>
23557                  <bitRange>[4:4]</bitRange>
23558                  <access>read-only</access>
23559                </field>
23560                <field>
23561                  <name>TR_COUNT</name>
23562                  <description>Indicates the actual level of the selected count trigger.</description>
23563                  <bitRange>[5:5]</bitRange>
23564                  <access>read-only</access>
23565                </field>
23566                <field>
23567                  <name>TR_RELOAD</name>
23568                  <description>Indicates the actual level of the selected reload trigger.</description>
23569                  <bitRange>[6:6]</bitRange>
23570                  <access>read-only</access>
23571                </field>
23572                <field>
23573                  <name>TR_STOP</name>
23574                  <description>Indicates the actual level of the selected stop trigger.</description>
23575                  <bitRange>[7:7]</bitRange>
23576                  <access>read-only</access>
23577                </field>
23578                <field>
23579                  <name>TR_START</name>
23580                  <description>Indicates the actual level of the selected start trigger.</description>
23581                  <bitRange>[8:8]</bitRange>
23582                  <access>read-only</access>
23583                </field>
23584                <field>
23585                  <name>TR_CAPTURE1</name>
23586                  <description>Indicates the actual level of the selected capture 1 trigger.</description>
23587                  <bitRange>[9:9]</bitRange>
23588                  <access>read-only</access>
23589                </field>
23590                <field>
23591                  <name>LINE_OUT</name>
23592                  <description>Indicates the actual level of the PWM line output signal.</description>
23593                  <bitRange>[10:10]</bitRange>
23594                  <access>read-only</access>
23595                </field>
23596                <field>
23597                  <name>LINE_COMPL_OUT</name>
23598                  <description>Indicates the actual level of the complementary PWM line output signal.</description>
23599                  <bitRange>[11:11]</bitRange>
23600                  <access>read-only</access>
23601                </field>
23602                <field>
23603                  <name>RUNNING</name>
23604                  <description>When '0', the counter is NOT running. When '1', the counter is running.
23605
23606This field is used to indicate that the counter is running after a start/reload event and that the counter is stopped after a stop event.
23607When a running counter operation is paused in debug state (see CTRL.DBG_PAUSE) then the RUNNING bit is still '1'.</description>
23608                  <bitRange>[15:15]</bitRange>
23609                  <access>read-only</access>
23610                </field>
23611                <field>
23612                  <name>DT_CNT_L</name>
23613                  <description>Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion (8bit dead time counter or low byte of 16-bit dead time counter).
23614In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.</description>
23615                  <bitRange>[23:16]</bitRange>
23616                  <access>read-only</access>
23617                </field>
23618                <field>
23619                  <name>DT_CNT_H</name>
23620                  <description>High byte of 16-bit dead time counter. In PWM_DT mode, this counter is used for dead time insertion.
23621In all other modes, this field has no effect.
23622
23623Note: This field only exists when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8bit wide and the only the field DT_CNT_L is used as dead time counter.</description>
23624                  <bitRange>[31:24]</bitRange>
23625                  <access>read-only</access>
23626                </field>
23627              </fields>
23628            </register>
23629            <register>
23630              <name>COUNTER</name>
23631              <description>Counter count register</description>
23632              <addressOffset>0x8</addressOffset>
23633              <size>32</size>
23634              <access>read-write</access>
23635              <resetValue>0x0</resetValue>
23636              <resetMask>0xFFFFFFFF</resetMask>
23637              <fields>
23638                <field>
23639                  <name>COUNTER</name>
23640                  <description>16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running.</description>
23641                  <bitRange>[31:0]</bitRange>
23642                  <access>read-write</access>
23643                </field>
23644              </fields>
23645            </register>
23646            <register>
23647              <name>CC0</name>
23648              <description>Counter compare/capture 0 register</description>
23649              <addressOffset>0x10</addressOffset>
23650              <size>32</size>
23651              <access>read-write</access>
23652              <resetValue>0xFFFFFFFF</resetValue>
23653              <resetMask>0xFFFFFFFF</resetMask>
23654              <fields>
23655                <field>
23656                  <name>CC</name>
23657                  <description>In CAPTURE mode, captures the counter value. In other modes, compared to counter value.</description>
23658                  <bitRange>[31:0]</bitRange>
23659                  <access>read-write</access>
23660                </field>
23661              </fields>
23662            </register>
23663            <register>
23664              <name>CC0_BUFF</name>
23665              <description>Counter buffered compare/capture 0 register</description>
23666              <addressOffset>0x14</addressOffset>
23667              <size>32</size>
23668              <access>read-write</access>
23669              <resetValue>0xFFFFFFFF</resetValue>
23670              <resetMask>0xFFFFFFFF</resetMask>
23671              <fields>
23672                <field>
23673                  <name>CC</name>
23674                  <description>Additional buffer for counter CC register.</description>
23675                  <bitRange>[31:0]</bitRange>
23676                  <access>read-write</access>
23677                </field>
23678              </fields>
23679            </register>
23680            <register>
23681              <name>CC1</name>
23682              <description>Counter compare/capture 1 register</description>
23683              <addressOffset>0x18</addressOffset>
23684              <size>32</size>
23685              <access>read-write</access>
23686              <resetValue>0xFFFFFFFF</resetValue>
23687              <resetMask>0xFFFFFFFF</resetMask>
23688              <fields>
23689                <field>
23690                  <name>CC</name>
23691                  <description>In CAPTURE mode, captures the counter value. In other modes, compared to counter value.</description>
23692                  <bitRange>[31:0]</bitRange>
23693                  <access>read-write</access>
23694                </field>
23695              </fields>
23696            </register>
23697            <register>
23698              <name>CC1_BUFF</name>
23699              <description>Counter buffered compare/capture 1 register</description>
23700              <addressOffset>0x1C</addressOffset>
23701              <size>32</size>
23702              <access>read-write</access>
23703              <resetValue>0xFFFFFFFF</resetValue>
23704              <resetMask>0xFFFFFFFF</resetMask>
23705              <fields>
23706                <field>
23707                  <name>CC</name>
23708                  <description>Additional buffer for counter CC1 register.</description>
23709                  <bitRange>[31:0]</bitRange>
23710                  <access>read-write</access>
23711                </field>
23712              </fields>
23713            </register>
23714            <register>
23715              <name>PERIOD</name>
23716              <description>Counter period register</description>
23717              <addressOffset>0x20</addressOffset>
23718              <size>32</size>
23719              <access>read-write</access>
23720              <resetValue>0xFFFFFFFF</resetValue>
23721              <resetMask>0xFFFFFFFF</resetMask>
23722              <fields>
23723                <field>
23724                  <name>PERIOD</name>
23725                  <description>Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.</description>
23726                  <bitRange>[31:0]</bitRange>
23727                  <access>read-write</access>
23728                </field>
23729              </fields>
23730            </register>
23731            <register>
23732              <name>PERIOD_BUFF</name>
23733              <description>Counter buffered period register</description>
23734              <addressOffset>0x24</addressOffset>
23735              <size>32</size>
23736              <access>read-write</access>
23737              <resetValue>0xFFFFFFFF</resetValue>
23738              <resetMask>0xFFFFFFFF</resetMask>
23739              <fields>
23740                <field>
23741                  <name>PERIOD</name>
23742                  <description>Additional buffer for counter PERIOD register.
23743
23744In PWM_PR mode PEROD_BUFF defines the LFSR polynomial. Each bit represents a tap of the shift register which can be feed back to the MSB via an XOR tree.
23745Examples for GRP_CNT_WIDTH = 16:
23746- Maximum length 16bit LFSR
23747  - polynomial x^16 + x^14 + x^13 + x^11 + 1
23748  - taps 0,2,3,5 -&gt; PERIOD = 0x002d
23749  - period is 2^16-1 = 65535 cycles
23750- Maximum length 8bit LFSR:
23751  - polynomial x^8 + x^6 + x^5 + x^4 + 1
23752  - taps 8,10,11,12 (realized in 8 MSBs of 16bit LFSR)
23753  - period is 2^8-1 = 255 cycles
23754
23755In SR mode PERIOD_BUFF defines which tap of the shift register generates the PWM output signals. For a delay of n cycles (from capture event to PWM output) the bit CNT_WIDTH-n should be set to '1'. For a shift register function only one tap should be use, i.e. a one-hot value must be written to PERIOD_BUFF. If multiple bits in PERIOD_BUFF are set then the taps are XOR combined.</description>
23756                  <bitRange>[31:0]</bitRange>
23757                  <access>read-write</access>
23758                </field>
23759              </fields>
23760            </register>
23761            <register>
23762              <name>LINE_SEL</name>
23763              <description>Counter line selection register</description>
23764              <addressOffset>0x28</addressOffset>
23765              <size>32</size>
23766              <access>read-write</access>
23767              <resetValue>0x32</resetValue>
23768              <resetMask>0x77</resetMask>
23769              <fields>
23770                <field>
23771                  <name>OUT_SEL</name>
23772                  <description>Selects the source for the output signal 'line_out'. Default setting is the PWM signal 'line'. Other settings are useful for Stepper Motor Control.
23773This field has a function in PWM and PWM_PR modes only.
23774
23775Note: The output signal of this selection can be further modified by the stop / kill logic and line_out polarity setting (CTRL.QUAD_ENCODING_MODE[0]).</description>
23776                  <bitRange>[2:0]</bitRange>
23777                  <access>read-write</access>
23778                  <enumeratedValues>
23779                    <enumeratedValue>
23780                      <name>L</name>
23781                      <description>fixed '0'</description>
23782                      <value>0</value>
23783                    </enumeratedValue>
23784                    <enumeratedValue>
23785                      <name>H</name>
23786                      <description>fixed '1'</description>
23787                      <value>1</value>
23788                    </enumeratedValue>
23789                    <enumeratedValue>
23790                      <name>PWM</name>
23791                      <description>PWM signal 'line'</description>
23792                      <value>2</value>
23793                    </enumeratedValue>
23794                    <enumeratedValue>
23795                      <name>PWM_INV</name>
23796                      <description>inverted PWM signal 'line'</description>
23797                      <value>3</value>
23798                    </enumeratedValue>
23799                    <enumeratedValue>
23800                      <name>Z</name>
23801                      <description>The output 'line_out' is not driven by the TCPWM. Instead the port default level configuration applies, e.g. 'Z' (high impedance).
23802
23803Note: This is realized by driving the output 'line_out_en' to 0.</description>
23804                      <value>4</value>
23805                    </enumeratedValue>
23806                    <enumeratedValue>
23807                      <name>RSVD5</name>
23808                      <description>N/A</description>
23809                      <value>5</value>
23810                    </enumeratedValue>
23811                    <enumeratedValue>
23812                      <name>RSVD6</name>
23813                      <description>N/A</description>
23814                      <value>6</value>
23815                    </enumeratedValue>
23816                    <enumeratedValue>
23817                      <name>RSVD7</name>
23818                      <description>N/A</description>
23819                      <value>7</value>
23820                    </enumeratedValue>
23821                  </enumeratedValues>
23822                </field>
23823                <field>
23824                  <name>COMPL_OUT_SEL</name>
23825                  <description>Selects the source for the output signal 'line_compl_out'. Default setting is the inverted PWM signal 'line'. Other settings are useful for Stepper Motor Control.
23826This field has a function in PWM and PWM_PR modes only.
23827
23828Note: The output signal of this selection can be further modified by the stop / kill logic and line_compl_out polarity setting (CTRL.QUAD_ENCODING_MODE[1]).</description>
23829                  <bitRange>[6:4]</bitRange>
23830                  <access>read-write</access>
23831                  <enumeratedValues>
23832                    <enumeratedValue>
23833                      <name>L</name>
23834                      <description>fixed '0'</description>
23835                      <value>0</value>
23836                    </enumeratedValue>
23837                    <enumeratedValue>
23838                      <name>H</name>
23839                      <description>fixed '1'</description>
23840                      <value>1</value>
23841                    </enumeratedValue>
23842                    <enumeratedValue>
23843                      <name>PWM</name>
23844                      <description>PWM signal 'line'</description>
23845                      <value>2</value>
23846                    </enumeratedValue>
23847                    <enumeratedValue>
23848                      <name>PWM_INV</name>
23849                      <description>inverted PWM signal 'line'</description>
23850                      <value>3</value>
23851                    </enumeratedValue>
23852                    <enumeratedValue>
23853                      <name>Z</name>
23854                      <description>The output 'line_compl_out' is not driven by the TCPWM. Instead the port default level configuration applies, e.g. 'Z' (high impedance).
23855
23856Note: This is realized by driving the output 'line_compl_out_en' to 0.</description>
23857                      <value>4</value>
23858                    </enumeratedValue>
23859                    <enumeratedValue>
23860                      <name>RSVD5</name>
23861                      <description>N/A</description>
23862                      <value>5</value>
23863                    </enumeratedValue>
23864                    <enumeratedValue>
23865                      <name>RSVD6</name>
23866                      <description>N/A</description>
23867                      <value>6</value>
23868                    </enumeratedValue>
23869                    <enumeratedValue>
23870                      <name>RSVD7</name>
23871                      <description>N/A</description>
23872                      <value>7</value>
23873                    </enumeratedValue>
23874                  </enumeratedValues>
23875                </field>
23876              </fields>
23877            </register>
23878            <register>
23879              <name>LINE_SEL_BUFF</name>
23880              <description>Counter buffered line selection register</description>
23881              <addressOffset>0x2C</addressOffset>
23882              <size>32</size>
23883              <access>read-write</access>
23884              <resetValue>0x32</resetValue>
23885              <resetMask>0x77</resetMask>
23886              <fields>
23887                <field>
23888                  <name>OUT_SEL</name>
23889                  <description>Buffer for LINE_SEL.OUT_SEL.
23890Can be exchanged with LINE_SEL.LINE_OUT_SEL on a terminal count event with an actively pending switch event.
23891
23892This field has a function in PWM and PWM_PR modes only.</description>
23893                  <bitRange>[2:0]</bitRange>
23894                  <access>read-write</access>
23895                </field>
23896                <field>
23897                  <name>COMPL_OUT_SEL</name>
23898                  <description>Buffer for LINE_SEL.COMPL.OUT_SEL.
23899Can be exchanged with LINE_SEL.LINE_COMPL_OUT_SEL on a terminal count event with an actively pending switch event.
23900
23901This field has a function in PWM and PWM_PR modes only.</description>
23902                  <bitRange>[6:4]</bitRange>
23903                  <access>read-write</access>
23904                </field>
23905              </fields>
23906            </register>
23907            <register>
23908              <name>DT</name>
23909              <description>Counter PWM dead time register</description>
23910              <addressOffset>0x30</addressOffset>
23911              <size>32</size>
23912              <access>read-write</access>
23913              <resetValue>0x0</resetValue>
23914              <resetMask>0xFFFFFFFF</resetMask>
23915              <fields>
23916                <field>
23917                  <name>DT_LINE_OUT_L</name>
23918                  <description>In PWM_DT mode, this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain.
23919In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.
23920
23921Note: This field determines the low byte of the 16-bit dead time before activating 'line_out' when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8 bit wide and the same dead time specified by this DT_LINE_OUT_L field is used before activating 'line_out' and 'line_compl_out'.</description>
23922                  <bitRange>[7:0]</bitRange>
23923                  <access>read-write</access>
23924                </field>
23925                <field>
23926                  <name>DT_LINE_OUT_H</name>
23927                  <description>In PWM_DT mode, this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain.
23928In all other modes, this field  has no effect.
23929
23930Note: This field only exists when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8 bit wide and the same dead time specified by field DT_LINE_OUT_L is used before activating 'line_out' and 'line_compl_out'.</description>
23931                  <bitRange>[15:8]</bitRange>
23932                  <access>read-write</access>
23933                </field>
23934                <field>
23935                  <name>DT_LINE_COMPL_OUT</name>
23936                  <description>In PWM_DT mode, this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain.
23937In all other modes, this field  has no effect.
23938
23939Note: This field only exists when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8 bit wide and the same dead time specified by field DT_LINE_OUT_L is used before activating 'line_out' and 'line_compl_out'.</description>
23940                  <bitRange>[31:16]</bitRange>
23941                  <access>read-write</access>
23942                </field>
23943              </fields>
23944            </register>
23945            <register>
23946              <name>TR_CMD</name>
23947              <description>Counter trigger command register</description>
23948              <addressOffset>0x40</addressOffset>
23949              <size>32</size>
23950              <access>read-write</access>
23951              <resetValue>0x0</resetValue>
23952              <resetMask>0x3D</resetMask>
23953              <fields>
23954                <field>
23955                  <name>CAPTURE0</name>
23956                  <description>SW capture 0 trigger. When written with '1', a capture 0 trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled through CTRL.ENABLED, the field is immediately set to '0'.</description>
23957                  <bitRange>[0:0]</bitRange>
23958                  <access>read-write</access>
23959                </field>
23960                <field>
23961                  <name>RELOAD</name>
23962                  <description>SW reload trigger. For HW behavior, see COUNTER_CAPTURE0 field.</description>
23963                  <bitRange>[2:2]</bitRange>
23964                  <access>read-write</access>
23965                </field>
23966                <field>
23967                  <name>STOP</name>
23968                  <description>SW stop trigger. For HW behavior, see COUNTER_CAPTURE0 field.</description>
23969                  <bitRange>[3:3]</bitRange>
23970                  <access>read-write</access>
23971                </field>
23972                <field>
23973                  <name>START</name>
23974                  <description>SW start trigger. For HW behavior, see COUNTER_CAPTURE0 field.</description>
23975                  <bitRange>[4:4]</bitRange>
23976                  <access>read-write</access>
23977                </field>
23978                <field>
23979                  <name>CAPTURE1</name>
23980                  <description>SW capture 1 trigger. For HW behavior, see COUNTER_CAPTURE0 field.</description>
23981                  <bitRange>[5:5]</bitRange>
23982                  <access>read-write</access>
23983                </field>
23984              </fields>
23985            </register>
23986            <register>
23987              <name>TR_IN_SEL0</name>
23988              <description>Counter input trigger selection register 0</description>
23989              <addressOffset>0x44</addressOffset>
23990              <size>32</size>
23991              <access>read-write</access>
23992              <resetValue>0x100</resetValue>
23993              <resetMask>0xFFFFFFFF</resetMask>
23994              <fields>
23995                <field>
23996                  <name>CAPTURE0_SEL</name>
23997                  <description>Selects one of the up to 256 input triggers as a capture0 trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. If existing, the one-to-one trigger inputs 'tr_one_cnt_in' (different to each counter) are selected by setting 2 and above. The settings above are used for the general purpose trigger inputs 'tr_all_cnt_in' connected to all counters selected.
23998In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.</description>
23999                  <bitRange>[7:0]</bitRange>
24000                  <access>read-write</access>
24001                </field>
24002                <field>
24003                  <name>COUNT_SEL</name>
24004                  <description>Selects one of the 256 input triggers as a count trigger.
24005In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.
24006
24007Note: In the modes: TIMER, CAPTURE, PWM, PWM_DT, and SR, If the counter is externally triggered ( COUNT_SEL &gt; 1), an external trigger will be required for each TR_CMD to execute. For example, a write to TR_CMD.START will not start the counter until the trigger selected by COUNT_SEL asserts. The next trigger will increment the counter since the counter is now running. This goes for all TR_CMD fields.</description>
24008                  <bitRange>[15:8]</bitRange>
24009                  <access>read-write</access>
24010                </field>
24011                <field>
24012                  <name>RELOAD_SEL</name>
24013                  <description>Selects one of the 256 input triggers as a reload trigger.
24014In QUAD mode, this is the index or revolution pulse. In these modes, it will update the counter with 0x8000 (counter midpoint) or 0x0000 depending on the QUAD_RANGE_MODE.</description>
24015                  <bitRange>[23:16]</bitRange>
24016                  <access>read-write</access>
24017                </field>
24018                <field>
24019                  <name>STOP_SEL</name>
24020                  <description>Selects one of the 256 input triggers as a stop trigger.
24021In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be  asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.</description>
24022                  <bitRange>[31:24]</bitRange>
24023                  <access>read-write</access>
24024                </field>
24025              </fields>
24026            </register>
24027            <register>
24028              <name>TR_IN_SEL1</name>
24029              <description>Counter input trigger selection register 1</description>
24030              <addressOffset>0x48</addressOffset>
24031              <size>32</size>
24032              <access>read-write</access>
24033              <resetValue>0x0</resetValue>
24034              <resetMask>0xFFFF</resetMask>
24035              <fields>
24036                <field>
24037                  <name>START_SEL</name>
24038                  <description>Selects one of the 256 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).</description>
24039                  <bitRange>[7:0]</bitRange>
24040                  <access>read-write</access>
24041                </field>
24042                <field>
24043                  <name>CAPTURE1_SEL</name>
24044                  <description>Selects one of the 256 input triggers as a capture 1 trigger.</description>
24045                  <bitRange>[15:8]</bitRange>
24046                  <access>read-write</access>
24047                </field>
24048              </fields>
24049            </register>
24050            <register>
24051              <name>TR_IN_EDGE_SEL</name>
24052              <description>Counter input trigger edge selection register</description>
24053              <addressOffset>0x4C</addressOffset>
24054              <size>32</size>
24055              <access>read-write</access>
24056              <resetValue>0xFFF</resetValue>
24057              <resetMask>0xFFF</resetMask>
24058              <fields>
24059                <field>
24060                  <name>CAPTURE0_EDGE</name>
24061                  <description>A capture 0 event will copy the counter value into the CC0 register.</description>
24062                  <bitRange>[1:0]</bitRange>
24063                  <access>read-write</access>
24064                  <enumeratedValues>
24065                    <enumeratedValue>
24066                      <name>RISING_EDGE</name>
24067                      <description>Rising edge. Any rising edge generates an event.</description>
24068                      <value>0</value>
24069                    </enumeratedValue>
24070                    <enumeratedValue>
24071                      <name>FALLING_EDGE</name>
24072                      <description>Falling edge. Any falling edge generates an event.</description>
24073                      <value>1</value>
24074                    </enumeratedValue>
24075                    <enumeratedValue>
24076                      <name>ANY_EDGE</name>
24077                      <description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
24078                      <value>2</value>
24079                    </enumeratedValue>
24080                    <enumeratedValue>
24081                      <name>NO_EDGE_DET</name>
24082                      <description>No edge detection, use trigger as is.</description>
24083                      <value>3</value>
24084                    </enumeratedValue>
24085                  </enumeratedValues>
24086                </field>
24087                <field>
24088                  <name>COUNT_EDGE</name>
24089                  <description>A counter event will increase or decrease the counter by '1'.</description>
24090                  <bitRange>[3:2]</bitRange>
24091                  <access>read-write</access>
24092                  <enumeratedValues>
24093                    <enumeratedValue>
24094                      <name>RISING_EDGE</name>
24095                      <description>Rising edge. Any rising edge generates an event.</description>
24096                      <value>0</value>
24097                    </enumeratedValue>
24098                    <enumeratedValue>
24099                      <name>FALLING_EDGE</name>
24100                      <description>Falling edge. Any falling edge generates an event.</description>
24101                      <value>1</value>
24102                    </enumeratedValue>
24103                    <enumeratedValue>
24104                      <name>ANY_EDGE</name>
24105                      <description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
24106                      <value>2</value>
24107                    </enumeratedValue>
24108                    <enumeratedValue>
24109                      <name>NO_EDGE_DET</name>
24110                      <description>No edge detection, use trigger as is.</description>
24111                      <value>3</value>
24112                    </enumeratedValue>
24113                  </enumeratedValues>
24114                </field>
24115                <field>
24116                  <name>RELOAD_EDGE</name>
24117                  <description>A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.</description>
24118                  <bitRange>[5:4]</bitRange>
24119                  <access>read-write</access>
24120                  <enumeratedValues>
24121                    <enumeratedValue>
24122                      <name>RISING_EDGE</name>
24123                      <description>Rising edge. Any rising edge generates an event.</description>
24124                      <value>0</value>
24125                    </enumeratedValue>
24126                    <enumeratedValue>
24127                      <name>FALLING_EDGE</name>
24128                      <description>Falling edge. Any falling edge generates an event.</description>
24129                      <value>1</value>
24130                    </enumeratedValue>
24131                    <enumeratedValue>
24132                      <name>ANY_EDGE</name>
24133                      <description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
24134                      <value>2</value>
24135                    </enumeratedValue>
24136                    <enumeratedValue>
24137                      <name>NO_EDGE_DET</name>
24138                      <description>No edge detection, use trigger as is.</description>
24139                      <value>3</value>
24140                    </enumeratedValue>
24141                  </enumeratedValues>
24142                </field>
24143                <field>
24144                  <name>STOP_EDGE</name>
24145                  <description>A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter.</description>
24146                  <bitRange>[7:6]</bitRange>
24147                  <access>read-write</access>
24148                  <enumeratedValues>
24149                    <enumeratedValue>
24150                      <name>RISING_EDGE</name>
24151                      <description>Rising edge. Any rising edge generates an event.</description>
24152                      <value>0</value>
24153                    </enumeratedValue>
24154                    <enumeratedValue>
24155                      <name>FALLING_EDGE</name>
24156                      <description>Falling edge. Any falling edge generates an event.</description>
24157                      <value>1</value>
24158                    </enumeratedValue>
24159                    <enumeratedValue>
24160                      <name>ANY_EDGE</name>
24161                      <description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
24162                      <value>2</value>
24163                    </enumeratedValue>
24164                    <enumeratedValue>
24165                      <name>NO_EDGE_DET</name>
24166                      <description>No edge detection, use trigger as is.</description>
24167                      <value>3</value>
24168                    </enumeratedValue>
24169                  </enumeratedValues>
24170                </field>
24171                <field>
24172                  <name>START_EDGE</name>
24173                  <description>A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.</description>
24174                  <bitRange>[9:8]</bitRange>
24175                  <access>read-write</access>
24176                  <enumeratedValues>
24177                    <enumeratedValue>
24178                      <name>RISING_EDGE</name>
24179                      <description>Rising edge. Any rising edge generates an event.</description>
24180                      <value>0</value>
24181                    </enumeratedValue>
24182                    <enumeratedValue>
24183                      <name>FALLING_EDGE</name>
24184                      <description>Falling edge. Any falling edge generates an event.</description>
24185                      <value>1</value>
24186                    </enumeratedValue>
24187                    <enumeratedValue>
24188                      <name>ANY_EDGE</name>
24189                      <description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
24190                      <value>2</value>
24191                    </enumeratedValue>
24192                    <enumeratedValue>
24193                      <name>NO_EDGE_DET</name>
24194                      <description>No edge detection, use trigger as is.</description>
24195                      <value>3</value>
24196                    </enumeratedValue>
24197                  </enumeratedValues>
24198                </field>
24199                <field>
24200                  <name>CAPTURE1_EDGE</name>
24201                  <description>A capture 1 event will copy the counter value into the CC1 register.</description>
24202                  <bitRange>[11:10]</bitRange>
24203                  <access>read-write</access>
24204                  <enumeratedValues>
24205                    <enumeratedValue>
24206                      <name>RISING_EDGE</name>
24207                      <description>Rising edge. Any rising edge generates an event.</description>
24208                      <value>0</value>
24209                    </enumeratedValue>
24210                    <enumeratedValue>
24211                      <name>FALLING_EDGE</name>
24212                      <description>Falling edge. Any falling edge generates an event.</description>
24213                      <value>1</value>
24214                    </enumeratedValue>
24215                    <enumeratedValue>
24216                      <name>ANY_EDGE</name>
24217                      <description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
24218                      <value>2</value>
24219                    </enumeratedValue>
24220                    <enumeratedValue>
24221                      <name>NO_EDGE_DET</name>
24222                      <description>No edge detection, use trigger as is.</description>
24223                      <value>3</value>
24224                    </enumeratedValue>
24225                  </enumeratedValues>
24226                </field>
24227              </fields>
24228            </register>
24229            <register>
24230              <name>TR_PWM_CTRL</name>
24231              <description>Counter trigger PWM control register</description>
24232              <addressOffset>0x50</addressOffset>
24233              <size>32</size>
24234              <access>read-write</access>
24235              <resetValue>0xFF</resetValue>
24236              <resetMask>0xFF</resetMask>
24237              <fields>
24238                <field>
24239                  <name>CC0_MATCH_MODE</name>
24240                  <description>Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals.  Note that INVERT is especially useful for center aligned pulse width modulation.
24241To generate a duty cycle of 0 percent, the counter CC0 register should be set to '0'. For a 100 percent duty cycle, the counter CC0 register should be set to larger than the counter PERIOD register.</description>
24242                  <bitRange>[1:0]</bitRange>
24243                  <access>read-write</access>
24244                  <enumeratedValues>
24245                    <enumeratedValue>
24246                      <name>SET</name>
24247                      <description>Set to '1'</description>
24248                      <value>0</value>
24249                    </enumeratedValue>
24250                    <enumeratedValue>
24251                      <name>CLEAR</name>
24252                      <description>Set to '0'</description>
24253                      <value>1</value>
24254                    </enumeratedValue>
24255                    <enumeratedValue>
24256                      <name>INVERT</name>
24257                      <description>Invert</description>
24258                      <value>2</value>
24259                    </enumeratedValue>
24260                    <enumeratedValue>
24261                      <name>NO_CHANGE</name>
24262                      <description>No Change</description>
24263                      <value>3</value>
24264                    </enumeratedValue>
24265                  </enumeratedValues>
24266                </field>
24267                <field>
24268                  <name>OVERFLOW_MODE</name>
24269                  <description>Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.</description>
24270                  <bitRange>[3:2]</bitRange>
24271                  <access>read-write</access>
24272                  <enumeratedValues>
24273                    <enumeratedValue>
24274                      <name>SET</name>
24275                      <description>Set to '1'</description>
24276                      <value>0</value>
24277                    </enumeratedValue>
24278                    <enumeratedValue>
24279                      <name>CLEAR</name>
24280                      <description>Set to '0'</description>
24281                      <value>1</value>
24282                    </enumeratedValue>
24283                    <enumeratedValue>
24284                      <name>INVERT</name>
24285                      <description>Invert</description>
24286                      <value>2</value>
24287                    </enumeratedValue>
24288                    <enumeratedValue>
24289                      <name>NO_CHANGE</name>
24290                      <description>No Change</description>
24291                      <value>3</value>
24292                    </enumeratedValue>
24293                  </enumeratedValues>
24294                </field>
24295                <field>
24296                  <name>UNDERFLOW_MODE</name>
24297                  <description>Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.</description>
24298                  <bitRange>[5:4]</bitRange>
24299                  <access>read-write</access>
24300                  <enumeratedValues>
24301                    <enumeratedValue>
24302                      <name>SET</name>
24303                      <description>Set to '1'</description>
24304                      <value>0</value>
24305                    </enumeratedValue>
24306                    <enumeratedValue>
24307                      <name>CLEAR</name>
24308                      <description>Set to '0'</description>
24309                      <value>1</value>
24310                    </enumeratedValue>
24311                    <enumeratedValue>
24312                      <name>INVERT</name>
24313                      <description>Invert</description>
24314                      <value>2</value>
24315                    </enumeratedValue>
24316                    <enumeratedValue>
24317                      <name>NO_CHANGE</name>
24318                      <description>No Change</description>
24319                      <value>3</value>
24320                    </enumeratedValue>
24321                  </enumeratedValues>
24322                </field>
24323                <field>
24324                  <name>CC1_MATCH_MODE</name>
24325                  <description>Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals.</description>
24326                  <bitRange>[7:6]</bitRange>
24327                  <access>read-write</access>
24328                  <enumeratedValues>
24329                    <enumeratedValue>
24330                      <name>SET</name>
24331                      <description>Set to '1'</description>
24332                      <value>0</value>
24333                    </enumeratedValue>
24334                    <enumeratedValue>
24335                      <name>CLEAR</name>
24336                      <description>Set to '0'</description>
24337                      <value>1</value>
24338                    </enumeratedValue>
24339                    <enumeratedValue>
24340                      <name>INVERT</name>
24341                      <description>Invert</description>
24342                      <value>2</value>
24343                    </enumeratedValue>
24344                    <enumeratedValue>
24345                      <name>NO_CHANGE</name>
24346                      <description>No Change</description>
24347                      <value>3</value>
24348                    </enumeratedValue>
24349                  </enumeratedValues>
24350                </field>
24351              </fields>
24352            </register>
24353            <register>
24354              <name>TR_OUT_SEL</name>
24355              <description>Counter output trigger selection register</description>
24356              <addressOffset>0x54</addressOffset>
24357              <size>32</size>
24358              <access>read-write</access>
24359              <resetValue>0x32</resetValue>
24360              <resetMask>0x77</resetMask>
24361              <fields>
24362                <field>
24363                  <name>OUT0</name>
24364                  <description>Selects one of the internal events to generate the output trigger 0. Default setting selects the terminal count event.</description>
24365                  <bitRange>[2:0]</bitRange>
24366                  <access>read-write</access>
24367                  <enumeratedValues>
24368                    <enumeratedValue>
24369                      <name>OVERFLOW</name>
24370                      <description>Overflow event</description>
24371                      <value>0</value>
24372                    </enumeratedValue>
24373                    <enumeratedValue>
24374                      <name>UNDERFLOW</name>
24375                      <description>Underflow event</description>
24376                      <value>1</value>
24377                    </enumeratedValue>
24378                    <enumeratedValue>
24379                      <name>TC</name>
24380                      <description>Terminal count event (default selection)</description>
24381                      <value>2</value>
24382                    </enumeratedValue>
24383                    <enumeratedValue>
24384                      <name>CC0_MATCH</name>
24385                      <description>Compare match 0 event</description>
24386                      <value>3</value>
24387                    </enumeratedValue>
24388                    <enumeratedValue>
24389                      <name>CC1_MATCH</name>
24390                      <description>Compare match 1 event</description>
24391                      <value>4</value>
24392                    </enumeratedValue>
24393                    <enumeratedValue>
24394                      <name>LINE_OUT</name>
24395                      <description>PWM output signal 'line_out'</description>
24396                      <value>5</value>
24397                    </enumeratedValue>
24398                    <enumeratedValue>
24399                      <name>RSVD6</name>
24400                      <description>N/A</description>
24401                      <value>6</value>
24402                    </enumeratedValue>
24403                    <enumeratedValue>
24404                      <name>Disabled</name>
24405                      <description>Output trigger disabled.</description>
24406                      <value>7</value>
24407                    </enumeratedValue>
24408                  </enumeratedValues>
24409                </field>
24410                <field>
24411                  <name>OUT1</name>
24412                  <description>Selects one of the internal events to generate the output trigger 1. Default setting selects the compare match 0 event.</description>
24413                  <bitRange>[6:4]</bitRange>
24414                  <access>read-write</access>
24415                  <enumeratedValues>
24416                    <enumeratedValue>
24417                      <name>OVERFLOW</name>
24418                      <description>Overflow event</description>
24419                      <value>0</value>
24420                    </enumeratedValue>
24421                    <enumeratedValue>
24422                      <name>UNDERFLOW</name>
24423                      <description>Underflow event</description>
24424                      <value>1</value>
24425                    </enumeratedValue>
24426                    <enumeratedValue>
24427                      <name>TC</name>
24428                      <description>Terminal count event</description>
24429                      <value>2</value>
24430                    </enumeratedValue>
24431                    <enumeratedValue>
24432                      <name>CC0_MATCH</name>
24433                      <description>Compare match 0 event (default selection)</description>
24434                      <value>3</value>
24435                    </enumeratedValue>
24436                    <enumeratedValue>
24437                      <name>CC1_MATCH</name>
24438                      <description>Compare match 1 event</description>
24439                      <value>4</value>
24440                    </enumeratedValue>
24441                    <enumeratedValue>
24442                      <name>LINE_OUT</name>
24443                      <description>PWM output signal 'line_out'</description>
24444                      <value>5</value>
24445                    </enumeratedValue>
24446                    <enumeratedValue>
24447                      <name>RSVD6</name>
24448                      <description>N/A</description>
24449                      <value>6</value>
24450                    </enumeratedValue>
24451                    <enumeratedValue>
24452                      <name>Disabled</name>
24453                      <description>Output trigger disabled.</description>
24454                      <value>7</value>
24455                    </enumeratedValue>
24456                  </enumeratedValues>
24457                </field>
24458              </fields>
24459            </register>
24460            <register>
24461              <name>INTR</name>
24462              <description>Interrupt request register</description>
24463              <addressOffset>0x70</addressOffset>
24464              <size>32</size>
24465              <access>read-write</access>
24466              <resetValue>0x0</resetValue>
24467              <resetMask>0x7</resetMask>
24468              <fields>
24469                <field>
24470                  <name>TC</name>
24471                  <description>Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.</description>
24472                  <bitRange>[0:0]</bitRange>
24473                  <access>read-write</access>
24474                </field>
24475                <field>
24476                  <name>CC0_MATCH</name>
24477                  <description>Counter matches CC0 register event. Set to '1', when event is detected. Write with '1' to clear bit.</description>
24478                  <bitRange>[1:1]</bitRange>
24479                  <access>read-write</access>
24480                </field>
24481                <field>
24482                  <name>CC1_MATCH</name>
24483                  <description>Counter matches CC1 register event. Set to '1', when event is detected. Write with '1' to clear bit.</description>
24484                  <bitRange>[2:2]</bitRange>
24485                  <access>read-write</access>
24486                </field>
24487              </fields>
24488            </register>
24489            <register>
24490              <name>INTR_SET</name>
24491              <description>Interrupt set request register</description>
24492              <addressOffset>0x74</addressOffset>
24493              <size>32</size>
24494              <access>read-write</access>
24495              <resetValue>0x0</resetValue>
24496              <resetMask>0x7</resetMask>
24497              <fields>
24498                <field>
24499                  <name>TC</name>
24500                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
24501                  <bitRange>[0:0]</bitRange>
24502                  <access>read-write</access>
24503                </field>
24504                <field>
24505                  <name>CC0_MATCH</name>
24506                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
24507                  <bitRange>[1:1]</bitRange>
24508                  <access>read-write</access>
24509                </field>
24510                <field>
24511                  <name>CC1_MATCH</name>
24512                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
24513                  <bitRange>[2:2]</bitRange>
24514                  <access>read-write</access>
24515                </field>
24516              </fields>
24517            </register>
24518            <register>
24519              <name>INTR_MASK</name>
24520              <description>Interrupt mask register</description>
24521              <addressOffset>0x78</addressOffset>
24522              <size>32</size>
24523              <access>read-write</access>
24524              <resetValue>0x0</resetValue>
24525              <resetMask>0x7</resetMask>
24526              <fields>
24527                <field>
24528                  <name>TC</name>
24529                  <description>Mask bit for corresponding bit in interrupt request register.</description>
24530                  <bitRange>[0:0]</bitRange>
24531                  <access>read-write</access>
24532                </field>
24533                <field>
24534                  <name>CC0_MATCH</name>
24535                  <description>Mask bit for corresponding bit in interrupt request register.</description>
24536                  <bitRange>[1:1]</bitRange>
24537                  <access>read-write</access>
24538                </field>
24539                <field>
24540                  <name>CC1_MATCH</name>
24541                  <description>Mask bit for corresponding bit in interrupt request register.</description>
24542                  <bitRange>[2:2]</bitRange>
24543                  <access>read-write</access>
24544                </field>
24545              </fields>
24546            </register>
24547            <register>
24548              <name>INTR_MASKED</name>
24549              <description>Interrupt masked request register</description>
24550              <addressOffset>0x7C</addressOffset>
24551              <size>32</size>
24552              <access>read-only</access>
24553              <resetValue>0x0</resetValue>
24554              <resetMask>0x7</resetMask>
24555              <fields>
24556                <field>
24557                  <name>TC</name>
24558                  <description>Logical and of corresponding request and mask bits.</description>
24559                  <bitRange>[0:0]</bitRange>
24560                  <access>read-only</access>
24561                </field>
24562                <field>
24563                  <name>CC0_MATCH</name>
24564                  <description>Logical and of corresponding request and mask bits.</description>
24565                  <bitRange>[1:1]</bitRange>
24566                  <access>read-only</access>
24567                </field>
24568                <field>
24569                  <name>CC1_MATCH</name>
24570                  <description>Logical and of corresponding request and mask bits.</description>
24571                  <bitRange>[2:2]</bitRange>
24572                  <access>read-only</access>
24573                </field>
24574              </fields>
24575            </register>
24576          </cluster>
24577        </cluster>
24578      </registers>
24579    </peripheral>
24580    <peripheral>
24581      <name>MXS40ADCMIC0</name>
24582      <description>ADC</description>
24583      <headerStructName>MXS40ADCMIC</headerStructName>
24584      <baseAddress>0x40520000</baseAddress>
24585      <addressBlock>
24586        <offset>0</offset>
24587        <size>65536</size>
24588        <usage>registers</usage>
24589      </addressBlock>
24590      <registers>
24591        <register>
24592          <name>ADCMIC_CTRL</name>
24593          <description>Control the operation of the ADCMIC block including clock generation,clock selection and pdm data latching</description>
24594          <addressOffset>0x0</addressOffset>
24595          <size>32</size>
24596          <access>read-write</access>
24597          <resetValue>0x10542</resetValue>
24598          <resetMask>0x9FFFFFFF</resetMask>
24599          <fields>
24600            <field>
24601              <name>ADC_DIV_RATIO</name>
24602              <description>Divide ratio to divide clk_hf to yield clk_adc to process pdm_data</description>
24603              <bitRange>[4:0]</bitRange>
24604              <access>read-write</access>
24605            </field>
24606            <field>
24607              <name>PDM_DIV_RATIO</name>
24608              <description>Divide ratio to divide clk_hf to generate clk_pdm to receive pdm_data</description>
24609              <bitRange>[9:5]</bitRange>
24610              <access>read-write</access>
24611            </field>
24612            <field>
24613              <name>ADC_RESET</name>
24614              <description>Reset for the adc domain
24615 1: Out of reset and synchronized to clk_adc
24616 0: In reset</description>
24617              <bitRange>[10:10]</bitRange>
24618              <access>read-write</access>
24619            </field>
24620            <field>
24621              <name>PDM_LATCH_NEG_EDGE</name>
24622              <description>Edge of clk_hf used to latch pdm_data
24623 1: Latch on negative edge
24624 0: Latch on positive edge</description>
24625              <bitRange>[11:11]</bitRange>
24626              <access>read-write</access>
24627            </field>
24628            <field>
24629              <name>PDM_DATA</name>
24630              <description>pdm data synchronuzed to clkc_sys</description>
24631              <bitRange>[12:12]</bitRange>
24632              <access>read-only</access>
24633            </field>
24634            <field>
24635              <name>CLK_GATE_EN</name>
24636              <description>Two bit clock gate control that enables the mxtk_clk_gate cells
24637 Bit 0: Controls clk_hf clock gate
24638 Bit 1: Controls the clk_adc_syn from the ADC block</description>
24639              <bitRange>[14:13]</bitRange>
24640              <access>read-write</access>
24641            </field>
24642            <field>
24643              <name>PDM_LATCH_DELAY</name>
24644              <description>Number of clk_hf cycles from edge of clk_pdm to latch the pdm_data
24645 When pdm_latch_neg_edge is 0 valid values are 2 through 8
24646 When pdm_latch_neg_edge is 1 valid values are 3 through 9</description>
24647              <bitRange>[19:15]</bitRange>
24648              <access>read-write</access>
24649            </field>
24650            <field>
24651              <name>CLKS_ACTIVE_ADC</name>
24652              <description>clk sel for clk_adc - one hot encoded
24653 00000 : No clocks selected - clock is gated off
24654 00001 : clk_adc from local clk_divder is selected
24655 00010 : Inverted clk_adc from local clk_divder is selected
24656 00100 : clk_adc received from adc is used
24657 01000 : Inverted clk_adc received from adc is used
24658 10000 : clk_pdm_int is used as clk_adc</description>
24659              <bitRange>[24:20]</bitRange>
24660              <access>read-write</access>
24661            </field>
24662            <field>
24663              <name>CLKS_ACTIVE_PDM</name>
24664              <description>clk sel for clk_pdm - one hot encoded but the lower 2 bits and the upper 2 bits are independent of each other
24665 0000 : No clocks selected - clock is gated off
24666 XX01 : clk_pdm from local clk_divder is selected  for external clk_pdm
24667 XX10 : Inverted clk_pdm from local clk_divder is selected  for external clk_pdm
24668 01XX : clk_pdm from local clk_divder is selected  as internal clk_adc to process pdm_data
24669 10XX : Inverted clk_pdm from local clk_divder is selected  as internal clk_adc to latch pdm_data</description>
24670              <bitRange>[28:25]</bitRange>
24671              <access>read-write</access>
24672            </field>
24673            <field>
24674              <name>ADCMIC_EN</name>
24675              <description>Enables the adcmic operation
24676 This bit controls the pdm data being latched to begin the adcmic operation.</description>
24677              <bitRange>[31:31]</bitRange>
24678              <access>read-write</access>
24679            </field>
24680          </fields>
24681        </register>
24682        <register>
24683          <name>ADCMIC_PAD_CTRL</name>
24684          <description>Control the pads in the ADCMIC block</description>
24685          <addressOffset>0x4</addressOffset>
24686          <size>32</size>
24687          <access>read-write</access>
24688          <resetValue>0x0</resetValue>
24689          <resetMask>0x1</resetMask>
24690          <fields>
24691            <field>
24692              <name>CLK_PDM_OE</name>
24693              <description>Output enable for pdm clock</description>
24694              <bitRange>[0:0]</bitRange>
24695              <access>read-write</access>
24696            </field>
24697          </fields>
24698        </register>
24699        <register>
24700          <name>ADCMIC_FIFO_CTRL</name>
24701          <description>Controls the operation of the fifo</description>
24702          <addressOffset>0x8</addressOffset>
24703          <size>32</size>
24704          <access>read-write</access>
24705          <resetValue>0xE00707</resetValue>
24706          <resetMask>0x80FFFF3F</resetMask>
24707          <fields>
24708            <field>
24709              <name>PGMBLE_FULL</name>
24710              <description>Number of programmable words to indicate distance to fifo_full and will trigger programmable full level (afifo_pgmble_full)</description>
24711              <bitRange>[5:0]</bitRange>
24712              <access>read-write</access>
24713            </field>
24714            <field>
24715              <name>PGMBLE_EMPTY</name>
24716              <description>Number of programmable words to indicate distance to fifo_empty and will trigger programmable empty level (afifo_pgmble_empty)</description>
24717              <bitRange>[13:8]</bitRange>
24718              <access>read-write</access>
24719            </field>
24720            <field>
24721              <name>FIFO_RESET</name>
24722              <description>[0] : fifo write reset when 0 and when 1 its out of reset
24723 [1] : fifo_read reset when 0 and when 1 its out of reset</description>
24724              <bitRange>[15:14]</bitRange>
24725              <access>read-write</access>
24726            </field>
24727            <field>
24728              <name>FIFO_STATUS</name>
24729              <description>Indicates fifo status of the fifo that stores pcm data. The almost empty and almost full indicates there is 1 location before being full or empty and pgmble indiates the level is half the depth of the fifo that has a total depth of 64.
24730 fifo_status[7] = afifo_empty
24731 fifo_status[6] = afifo_almost_empty
24732 fifo_status[5] = afifo_pgmble_empty
24733 fifo_status[4] = afifo_underflow
24734 fifo_status[3] = afifo_full
24735 fifo_status[2] = afifo_almost_full
24736 fifo_status[1] = afifo_pgmble_full
24737 fifo_status[0] = afifo_overflow</description>
24738              <bitRange>[23:16]</bitRange>
24739              <access>read-only</access>
24740            </field>
24741            <field>
24742              <name>FIFO_WR_BYPASS</name>
24743              <description>This is a bit set for debug where the data written into the fifo comes from the lfsr register</description>
24744              <bitRange>[31:31]</bitRange>
24745              <access>read-write</access>
24746            </field>
24747          </fields>
24748        </register>
24749        <register>
24750          <name>ADCMIC_LFSR_CTRL</name>
24751          <description>Controls the operation of the LFSR</description>
24752          <addressOffset>0xC</addressOffset>
24753          <size>32</size>
24754          <access>read-write</access>
24755          <resetValue>0x80622EE0</resetValue>
24756          <resetMask>0xFFFFBFFF</resetMask>
24757          <fields>
24758            <field>
24759              <name>LFSR_EN</name>
24760              <description>Write a 1 to this bit to begin the lfsr operation</description>
24761              <bitRange>[0:0]</bitRange>
24762              <access>read-write</access>
24763            </field>
24764            <field>
24765              <name>LFSR_SET</name>
24766              <description>When this bit is 1 then the lfsr register resets to 32'hFFFFFFFF</description>
24767              <bitRange>[1:1]</bitRange>
24768              <access>read-write</access>
24769            </field>
24770            <field>
24771              <name>LFSR_MODE</name>
24772              <description>N/A</description>
24773              <bitRange>[3:2]</bitRange>
24774              <access>read-write</access>
24775            </field>
24776            <field>
24777              <name>LFSR_VALID_CNTR_LIMIT</name>
24778              <description>The valid pulse for the lfsr_data dictates validity on a cycle basis. By default there is a new pattern every 750(0x2EE) cycles</description>
24779              <bitRange>[13:4]</bitRange>
24780              <access>read-write</access>
24781            </field>
24782            <field>
24783              <name>LFSR_CLR</name>
24784              <description>When this bit is 1 then the lfsr register resets to 32'h00000000</description>
24785              <bitRange>[15:15]</bitRange>
24786              <access>read-write</access>
24787            </field>
24788            <field>
24789              <name>LFSR_TAPS</name>
24790              <description>This field provides the tap points for the LFSR wuth lfsr_taps[15:8] corresponds to tap points [31:24] of the lfsr register while lfsr_taps[7:0] corresponds to tap points [7:0] of the lfsr register.</description>
24791              <bitRange>[31:16]</bitRange>
24792              <access>read-write</access>
24793            </field>
24794          </fields>
24795        </register>
24796        <register>
24797          <name>ADCMIC_TRIGGER</name>
24798          <description>Register to control Trigger</description>
24799          <addressOffset>0x10</addressOffset>
24800          <size>32</size>
24801          <access>read-only</access>
24802          <resetValue>0x0</resetValue>
24803          <resetMask>0x3</resetMask>
24804          <fields>
24805            <field>
24806              <name>TR_DC</name>
24807              <description>Trigger when timer fires for DC measurement</description>
24808              <bitRange>[0:0]</bitRange>
24809              <access>read-only</access>
24810            </field>
24811            <field>
24812              <name>TR_DATA</name>
24813              <description>Trigger when output fifo has valid data</description>
24814              <bitRange>[1:1]</bitRange>
24815              <access>read-only</access>
24816            </field>
24817          </fields>
24818        </register>
24819        <register>
24820          <name>ADCMIC_TRIGGER_CLR</name>
24821          <description>Register to clear Trigger</description>
24822          <addressOffset>0x14</addressOffset>
24823          <size>32</size>
24824          <access>read-write</access>
24825          <resetValue>0x0</resetValue>
24826          <resetMask>0x3</resetMask>
24827          <fields>
24828            <field>
24829              <name>TR_DC</name>
24830              <description>Activate functionality:
248310: No effect.
248321: Bit is set to 0.</description>
24833              <bitRange>[0:0]</bitRange>
24834              <access>read-write</access>
24835            </field>
24836            <field>
24837              <name>TR_DATA</name>
24838              <description>Activate functionality:
248390: No effect.
248401: Bit is set to 0.</description>
24841              <bitRange>[1:1]</bitRange>
24842              <access>read-write</access>
24843            </field>
24844          </fields>
24845        </register>
24846        <register>
24847          <name>ADCMIC_TRIGGER_SET</name>
24848          <description>Register to set Trigger</description>
24849          <addressOffset>0x18</addressOffset>
24850          <size>32</size>
24851          <access>read-write</access>
24852          <resetValue>0x0</resetValue>
24853          <resetMask>0x3</resetMask>
24854          <fields>
24855            <field>
24856              <name>TR_DC</name>
24857              <description>Activate functionality:
248580: No effect.
248591: Bit is set to 1.</description>
24860              <bitRange>[0:0]</bitRange>
24861              <access>read-write</access>
24862            </field>
24863            <field>
24864              <name>TR_DATA</name>
24865              <description>Activate functionality:
248660: No effect.
248671: Bit is set to 1.</description>
24868              <bitRange>[1:1]</bitRange>
24869              <access>read-write</access>
24870            </field>
24871          </fields>
24872        </register>
24873        <register>
24874          <name>ADCMIC_TRIGGER_MASK</name>
24875          <description>Register to mask Trigger</description>
24876          <addressOffset>0x1C</addressOffset>
24877          <size>32</size>
24878          <access>read-write</access>
24879          <resetValue>0x0</resetValue>
24880          <resetMask>0x3</resetMask>
24881          <fields>
24882            <field>
24883              <name>TR_DC</name>
24884              <description>Mask for corresponding field in ADCMIC_TRIGGER register.</description>
24885              <bitRange>[0:0]</bitRange>
24886              <access>read-write</access>
24887            </field>
24888            <field>
24889              <name>TR_DATA</name>
24890              <description>Mask for corresponding field in ADCMIC_TRIGGER register.</description>
24891              <bitRange>[1:1]</bitRange>
24892              <access>read-write</access>
24893            </field>
24894          </fields>
24895        </register>
24896        <register>
24897          <name>ADCMIC_INTR</name>
24898          <description>Register to cause Interrupt</description>
24899          <addressOffset>0x20</addressOffset>
24900          <size>32</size>
24901          <access>read-write</access>
24902          <resetValue>0x0</resetValue>
24903          <resetMask>0x3</resetMask>
24904          <fields>
24905            <field>
24906              <name>INTERRUPT_DC</name>
24907              <description>HW sets this field to 1, when dc measurement is done.</description>
24908              <bitRange>[0:0]</bitRange>
24909              <access>read-write</access>
24910            </field>
24911            <field>
24912              <name>INTERRUPT_DATA</name>
24913              <description>HW sets this field to 1, when fifo has valid data</description>
24914              <bitRange>[1:1]</bitRange>
24915              <access>read-write</access>
24916            </field>
24917          </fields>
24918        </register>
24919        <register>
24920          <name>ADCMIC_INTR_SET</name>
24921          <description>Register to set Interrupt</description>
24922          <addressOffset>0x24</addressOffset>
24923          <size>32</size>
24924          <access>read-write</access>
24925          <resetValue>0x0</resetValue>
24926          <resetMask>0x3</resetMask>
24927          <fields>
24928            <field>
24929              <name>INTERRUPT_DC</name>
24930              <description>Write this field with '1' to set corresponding ADCMIC_INTR field (a write of '0' has no effect).</description>
24931              <bitRange>[0:0]</bitRange>
24932              <access>read-write</access>
24933            </field>
24934            <field>
24935              <name>INTERRUPT_DATA</name>
24936              <description>Write this field with '1' to set corresponding ADCMIC_INTR field (a write of '0' has no effect).</description>
24937              <bitRange>[1:1]</bitRange>
24938              <access>read-write</access>
24939            </field>
24940          </fields>
24941        </register>
24942        <register>
24943          <name>ADCMIC_INTR_MASK</name>
24944          <description>Register to mask Interrupt</description>
24945          <addressOffset>0x28</addressOffset>
24946          <size>32</size>
24947          <access>read-write</access>
24948          <resetValue>0x0</resetValue>
24949          <resetMask>0x3</resetMask>
24950          <fields>
24951            <field>
24952              <name>INTERRUPT_DC</name>
24953              <description>Mask for corresponding field in ADCMIC_INTR register.</description>
24954              <bitRange>[0:0]</bitRange>
24955              <access>read-write</access>
24956            </field>
24957            <field>
24958              <name>INTERRUPT_DATA</name>
24959              <description>Mask for corresponding field in ADCMIC_INTR register.</description>
24960              <bitRange>[1:1]</bitRange>
24961              <access>read-write</access>
24962            </field>
24963          </fields>
24964        </register>
24965        <register>
24966          <name>ADCMIC_INTR_MASKED</name>
24967          <description>Register to and intr_mask Intr to crreate the interrupt</description>
24968          <addressOffset>0x2C</addressOffset>
24969          <size>32</size>
24970          <access>read-only</access>
24971          <resetValue>0x0</resetValue>
24972          <resetMask>0x3</resetMask>
24973          <fields>
24974            <field>
24975              <name>INTERRUPT_DC</name>
24976              <description>Logical AND of corresponding ADCMIC_INTR and ADCMIC_INTR_MASK fields.</description>
24977              <bitRange>[0:0]</bitRange>
24978              <access>read-only</access>
24979            </field>
24980            <field>
24981              <name>INTERRUPT_DATA</name>
24982              <description>Logical AND of corresponding ADCMIC_INTR and ADCMIC_INTR_MASK fields.</description>
24983              <bitRange>[1:1]</bitRange>
24984              <access>read-only</access>
24985            </field>
24986          </fields>
24987        </register>
24988        <register>
24989          <name>ADCMIC_TRIG_INTRPT_TIMER_CTRL</name>
24990          <description>Controls the timer for the generation of triggers and interrupts for dc measurement in the block</description>
24991          <addressOffset>0x30</addressOffset>
24992          <size>32</size>
24993          <access>read-write</access>
24994          <resetValue>0x40000960</resetValue>
24995          <resetMask>0xC000FFFF</resetMask>
24996          <fields>
24997            <field>
24998              <name>TIMER_LIMIT</name>
24999              <description>At 96Mhz this count will generate interrupt to indicate that 25us has lapsed and the ADC core digital voltage is valid.</description>
25000              <bitRange>[15:0]</bitRange>
25001              <access>read-write</access>
25002            </field>
25003            <field>
25004              <name>TIMER_CLR</name>
25005              <description>When high clk_timer is cleared</description>
25006              <bitRange>[30:30]</bitRange>
25007              <access>read-write</access>
25008            </field>
25009            <field>
25010              <name>TIMER_INC</name>
25011              <description>Enable the timer to begin counting on every clk_sys cycle to timer_limit and then generate the interrupt.
25012 1: Counts up every clk_sys cycle
25013 0: Counts when cic is updated</description>
25014              <bitRange>[31:31]</bitRange>
25015              <access>read-write</access>
25016            </field>
25017          </fields>
25018        </register>
25019        <register>
25020          <name>ADCMIC_TP</name>
25021          <description>Data used for DFT test for setting and observing test points</description>
25022          <addressOffset>0x34</addressOffset>
25023          <size>32</size>
25024          <access>read-write</access>
25025          <resetValue>0x0</resetValue>
25026          <resetMask>0xFFFF00FF</resetMask>
25027          <fields>
25028            <field>
25029              <name>TEST_POINT_SET_DATA</name>
25030              <description>Bits to control tests points</description>
25031              <bitRange>[7:0]</bitRange>
25032              <access>read-write</access>
25033            </field>
25034            <field>
25035              <name>TEST_POINT_OBSERVE_DATA</name>
25036              <description>Bits to observe tests points</description>
25037              <bitRange>[31:16]</bitRange>
25038              <access>read-only</access>
25039            </field>
25040          </fields>
25041        </register>
25042        <register>
25043          <name>ADCMIC_DATA</name>
25044          <description>N/A</description>
25045          <addressOffset>0x40</addressOffset>
25046          <size>32</size>
25047          <access>read-only</access>
25048          <resetValue>0x0</resetValue>
25049          <resetMask>0xFFFFFFFF</resetMask>
25050          <fields>
25051            <field>
25052              <name>FIFO_DATA</name>
25053              <description>Data from the FIFO which contains two pcm data samples of 16 bits with the first sample in the lower half and the next sample in the upper half</description>
25054              <bitRange>[31:0]</bitRange>
25055              <access>read-only</access>
25056            </field>
25057          </fields>
25058        </register>
25059        <register>
25060          <name>ADC_CLK_CTRL</name>
25061          <description>Control the clocks in the ADC block</description>
25062          <addressOffset>0x100</addressOffset>
25063          <size>32</size>
25064          <access>read-write</access>
25065          <resetValue>0x0</resetValue>
25066          <resetMask>0x39</resetMask>
25067          <fields>
25068            <field>
25069              <name>ADC_SYN_CLK_PHASE</name>
25070              <description>Output synchronization clock phase control
25071 0: non-inverted clock phase
25072 1: inverted clock phase</description>
25073              <bitRange>[0:0]</bitRange>
25074              <access>read-write</access>
25075            </field>
25076            <field>
25077              <name>ADC_CLK_GATE_EN</name>
25078              <description>Clock gate control to enable the clock to ADC
25079 0: Clock is Disabled
25080 1: Clock is Enabled</description>
25081              <bitRange>[3:3]</bitRange>
25082              <access>read-write</access>
25083            </field>
25084            <field>
25085              <name>ADC_DATA_OUT</name>
25086              <description>Two bit PDM data from ADC that is latched
25087 3-level ADC data outputs:
25088 11 High
25089 01 Mid
25090 00 Low</description>
25091              <bitRange>[5:4]</bitRange>
25092              <access>read-only</access>
25093            </field>
25094          </fields>
25095        </register>
25096        <register>
25097          <name>ADC_GPIO_CTRL</name>
25098          <description>GPIO control for ADC</description>
25099          <addressOffset>0x104</addressOffset>
25100          <size>32</size>
25101          <access>read-write</access>
25102          <resetValue>0x0</resetValue>
25103          <resetMask>0x1F</resetMask>
25104          <fields>
25105            <field>
25106              <name>ADC_DCIN_MUX</name>
25107              <description>ADC DC input selection (32-to-1 MUX) but only the lower 8 GPIO's are enabled so the selection is limited to GPIO 0 through 7:
25108 01111 ADC reference ground (ADC_REFGND)
25109 01110 ADC BG REF (ADC_BGREF)
25110 01101 Core supply (VDDC)
25111 01100 Battery/IO supply (VBAT/VDDIO)
25112 01011 GPIO 27
25113 01010 GPIO 26
25114 01001 GPIO 25
25115 01000 GPIO 24
25116 00111 GPIO 23
25117 00110 GPIO 22
25118 00101 GPIO 21
25119 00100 GPIO 20
25120 00011 GPIO 19
25121 00010 GPIO 18
25122 00001 GPIO 17
25123 00000 GPIO 16
25124 11111 GPIO 15
25125 11110 GPIO 14
25126 11101 GPIO 13
25127 11100 GPIO 12
25128 11011 GPIO 11
25129 11010 GPIO 10
25130 11001 GPIO 9
25131 11000 GPIO 8
25132 10111 GPIO 7
25133 10110 GPIO 6
25134 10101 GPIO 5
25135 10100 GPIO 4
25136 10011 GPIO 3
25137 10010 GPIO 2
25138 10001 GPIO 1
25139 10000 GPIO 0</description>
25140              <bitRange>[4:0]</bitRange>
25141              <access>read-write</access>
25142            </field>
25143          </fields>
25144        </register>
25145        <register>
25146          <name>ADC_PD_CTRL</name>
25147          <description>Control the  power down controls in the ADC block.</description>
25148          <addressOffset>0x108</addressOffset>
25149          <size>32</size>
25150          <access>read-write</access>
25151          <resetValue>0x0</resetValue>
25152          <resetMask>0x3FF</resetMask>
25153          <fields>
25154            <field>
25155              <name>ADC_EN_VBAT</name>
25156              <description>ADC IP level enable control from avddBAT supply domain:
25157 0: power down all the blocks supplied by VBAT when the
25158 core supply is not ready
25159 1: ADC power up/down controlled by 1.2V power up/down signals
25160 Enable control signal in 1.6V-3.6V avddBAT supply domain</description>
25161              <bitRange>[0:0]</bitRange>
25162              <access>read-write</access>
25163            </field>
25164            <field>
25165              <name>ADC_PWRUP</name>
25166              <description>ADC IP level main power up/down control:
25167 0: power down whole ADC IP (Default)
25168 1: power up</description>
25169              <bitRange>[1:1]</bitRange>
25170              <access>read-write</access>
25171            </field>
25172            <field>
25173              <name>ADC_REF_PWRUP</name>
25174              <description>ADC BG &amp; REF power up/down:
25175 0: power down BG and REF (Default)
25176 1: power up</description>
25177              <bitRange>[2:2]</bitRange>
25178              <access>read-write</access>
25179            </field>
25180            <field>
25181              <name>ADC_CORE_PWRUP</name>
25182              <description>ADC core power up/down:
25183 0: power down ADC Core (Default)
25184 1: power up</description>
25185              <bitRange>[3:3]</bitRange>
25186              <access>read-write</access>
25187            </field>
25188            <field>
25189              <name>MIC_PWRUP</name>
25190              <description>ADC MIC (Audio) path power up/down control:
25191 0: power down MIC bias and PGA (Default)
25192 1: power up</description>
25193              <bitRange>[4:4]</bitRange>
25194              <access>read-write</access>
25195            </field>
25196            <field>
25197              <name>MIC_CLAMP_EN</name>
25198              <description>MIC PGA clamping enable/disable:
25199 0: disable MIC PGA clamping (Default)
25200 1: enable MIC PGA clamping</description>
25201              <bitRange>[5:5]</bitRange>
25202              <access>read-write</access>
25203            </field>
25204            <field>
25205              <name>MICBIAS_PWRUP</name>
25206              <description>MIC bias power up/down:
25207 0: power down MIC Bias(Default)
25208 1: Power up</description>
25209              <bitRange>[6:6]</bitRange>
25210              <access>read-write</access>
25211            </field>
25212            <field>
25213              <name>ADC_MODE</name>
25214              <description>MIC (Audio) input and DC measurement input selection:
25215 0 ADC in DC Measurement Mode;
25216 DC measurement path enabled;
25217 MIC path powered down
25218 1 ADC in Audio application Mode;
25219 MIC path enabled. DC input is gated</description>
25220              <bitRange>[7:7]</bitRange>
25221              <access>read-write</access>
25222            </field>
25223            <field>
25224              <name>ADC_MIC_PDSLT</name>
25225              <description>MIC path power up/down control selection in DC measurement mode:
25226 0: Power down MIC Bias and PGA in DC measurement Mode
25227 1: MIC path power up/down controlled by its pwrdn signal</description>
25228              <bitRange>[8:8]</bitRange>
25229              <access>read-write</access>
25230            </field>
25231            <field>
25232              <name>IDDQ</name>
25233              <description>Chip global power down control:
25234 0: power up (Default)
25235 1: power down</description>
25236              <bitRange>[9:9]</bitRange>
25237              <access>read-write</access>
25238            </field>
25239          </fields>
25240        </register>
25241        <register>
25242          <name>ADC_BG_REF_CTRL</name>
25243          <description>Control the Band Gap and Reference Voltages of the ADC</description>
25244          <addressOffset>0x10C</addressOffset>
25245          <size>32</size>
25246          <access>read-write</access>
25247          <resetValue>0x0</resetValue>
25248          <resetMask>0x1FFFF</resetMask>
25249          <fields>
25250            <field>
25251              <name>ADC_BG_PTAT_CTRL</name>
25252              <description>BG PTAT current adjustment:
25253 011  3.62 percent
25254 010  2.32 percent
25255 001  1.11 percent
25256 000  0.00 percent
25257 111 -1.11 percent
25258 110 -2.17 percent
25259 101 -3.19 percent
25260 100 -4.10 percent</description>
25261              <bitRange>[2:0]</bitRange>
25262              <access>read-write</access>
25263            </field>
25264            <field>
25265              <name>ADC_BG_CTAT_CTRL</name>
25266              <description>BG CTAT current adjustment:
25267 011  3.02 percent
25268 010  1.92 percent
25269 001  0.92 percent
25270 000  0.00 percent
25271 111 -0.93 percent
25272 110 -1.82 percent
25273 101 -2.68 percent
25274 100 -3.51 percent</description>
25275              <bitRange>[5:3]</bitRange>
25276              <access>read-write</access>
25277            </field>
25278            <field>
25279              <name>ADC_REF_CTRL</name>
25280              <description>ADC reference voltage programmability:
25281 [3:0] Vref(mV)
25282 0000 850.0
25283 0001 856.1
25284 0010 862.1
25285 0011 868.2
25286 0100 874.3
25287 0101 880.4
25288 0110 886.4
25289 0111 892.5
25290 1000 801.4
25291 1001 807.5
25292 1010 813.6
25293 1011 819.6
25294 1100 825.7
25295 1101 831.8
25296 1110 837.9
25297 1111 843.9</description>
25298              <bitRange>[9:6]</bitRange>
25299              <access>read-write</access>
25300            </field>
25301            <field>
25302              <name>ADC_SCF_CLKDIV</name>
25303              <description>Switch cap filter clock frequency selection:
25304 00: 50KHz (default)
25305 01: 25KHz
25306 10: 100KHz
25307 11: 1.6MHz</description>
25308              <bitRange>[11:10]</bitRange>
25309              <access>read-write</access>
25310            </field>
25311            <field>
25312              <name>ADC_SCF_BYPASS</name>
25313              <description>BG REF switch cap filter bypass
25314 0: enable switch cap filter
25315 1: bypass switch cap filter</description>
25316              <bitRange>[12:12]</bitRange>
25317              <access>read-write</access>
25318            </field>
25319            <field>
25320              <name>ADC_SCF_BYPASS_SEQ</name>
25321              <description>External power up sequence for BG SCF bypass</description>
25322              <bitRange>[13:13]</bitRange>
25323              <access>read-write</access>
25324            </field>
25325            <field>
25326              <name>ADC_SCF_SEQ_SLT</name>
25327              <description>Internal/External BG SCF power up sequence selection:
25328 0: use internal power up sequence
25329 1: use external power up sequence</description>
25330              <bitRange>[14:14]</bitRange>
25331              <access>read-write</access>
25332            </field>
25333            <field>
25334              <name>ADC_BIAS_CTRL</name>
25335              <description>Global bias current programmability
25336 10: 3.0uA
25337 11: 2.5uA
25338 00: 2.5uA
25339 01: 2.0uA</description>
25340              <bitRange>[16:15]</bitRange>
25341              <access>read-write</access>
25342            </field>
25343          </fields>
25344        </register>
25345        <register>
25346          <name>ADC_CORE_CTRL</name>
25347          <description>Control the clocks in the ADC block</description>
25348          <addressOffset>0x110</addressOffset>
25349          <size>32</size>
25350          <access>read-write</access>
25351          <resetValue>0x0</resetValue>
25352          <resetMask>0x3F</resetMask>
25353          <fields>
25354            <field>
25355              <name>ADC_DITH_CTRL</name>
25356              <description>Dither Sequence control
25357 00: No dither
25358 01: prbs15
25359 10: prbs23
25360 11: prbs31</description>
25361              <bitRange>[1:0]</bitRange>
25362              <access>read-write</access>
25363            </field>
25364            <field>
25365              <name>ADC_SHUFF_EN</name>
25366              <description>Disable the shuffler:
25367 0: disabled
25368 1: enabled</description>
25369              <bitRange>[2:2]</bitRange>
25370              <access>read-write</access>
25371            </field>
25372            <field>
25373              <name>ADC_RESET_EN</name>
25374              <description>Disable reset function in DC measurement:
25375 0: disabled
25376 1: enabled</description>
25377              <bitRange>[3:3]</bitRange>
25378              <access>read-write</access>
25379            </field>
25380            <field>
25381              <name>ADC_DCINPUT_RANGE</name>
25382              <description>ADC input range selection for DC measurement path:
25383 0: 0-3.6V
25384 1: 0-1.8V</description>
25385              <bitRange>[4:4]</bitRange>
25386              <access>read-write</access>
25387            </field>
25388            <field>
25389              <name>ADC_CLK_DIV2</name>
25390              <description>ADC internal clock division:
25391 0: disable divide-by-2; ADC sampling clock at 12MHz
25392 1: enable divide-by-2; ADC sampling clock at 6MHz</description>
25393              <bitRange>[5:5]</bitRange>
25394              <access>read-write</access>
25395            </field>
25396          </fields>
25397        </register>
25398        <register>
25399          <name>ADC_MIC_BIAS_PGA_CTRL</name>
25400          <description>Control the BIAS and PGA of ADC block</description>
25401          <addressOffset>0x114</addressOffset>
25402          <size>32</size>
25403          <access>read-write</access>
25404          <resetValue>0x0</resetValue>
25405          <resetMask>0xFFFFFF</resetMask>
25406          <fields>
25407            <field>
25408              <name>MIC_BIAS_REF_CTRL</name>
25409              <description>MIC bias reference voltage programmability:
25410 00: 75 percent of Audio Supply (default)
25411 10: 80 percent of Audio Supply
25412 01 / 11: 70 percent of Audio Supply</description>
25413              <bitRange>[1:0]</bitRange>
25414              <access>read-write</access>
25415            </field>
25416            <field>
25417              <name>MIC_BIAS_CTRL</name>
25418              <description>MIC bias output voltage programmability:
25419 00: 1.12 X Reference Voltage (default)
25420 01: 1.14 X Reference voltage
25421 10: 1.17 X Reference voltage
25422 11: 1.10 X Reference voltage</description>
25423              <bitRange>[3:2]</bitRange>
25424              <access>read-write</access>
25425            </field>
25426            <field>
25427              <name>MIC_REF_SLT</name>
25428              <description>MIC bias reference selection:
25429 0: supply as MIC bias reference. MIC bias output voltage
25430 scaled with supply voltage
25431 1: BG voltage as MIC bias reference to have constant MIC
25432 bias output voltage</description>
25433              <bitRange>[4:4]</bitRange>
25434              <access>read-write</access>
25435            </field>
25436            <field>
25437              <name>MIC_SCF_CLK_CTRL</name>
25438              <description>MIC bias reference filter clock programmability:
25439 00: 50KHz (default)
25440 01: 25KHz
25441 10: 100KHz
25442 11: 1.6MHz</description>
25443              <bitRange>[6:5]</bitRange>
25444              <access>read-write</access>
25445            </field>
25446            <field>
25447              <name>MIC_SCF_BYPASS</name>
25448              <description>MIC bias switch cap filter bypass
25449 0: enable switch cap filter
25450 1: bypass switch cap filter</description>
25451              <bitRange>[7:7]</bitRange>
25452              <access>read-write</access>
25453            </field>
25454            <field>
25455              <name>MIC_SCF_BYPASS_SEQ</name>
25456              <description>External power up sequence for MIC bias SCF bypass</description>
25457              <bitRange>[8:8]</bitRange>
25458              <access>read-write</access>
25459            </field>
25460            <field>
25461              <name>MIC_SCF_SEQ_SLT</name>
25462              <description>Internal/External MIC bias SCF power up sequence selection:
25463 0: use internal power up sequence
25464 1: use external power up sequence</description>
25465              <bitRange>[9:9]</bitRange>
25466              <access>read-write</access>
25467            </field>
25468            <field>
25469              <name>MIC_BIAS_LZ</name>
25470              <description>MIC bias low/high output impedance control during power down mode:
25471 0: MIC bias output is HZ in power down mode (default)
25472 1: MIC bias output is LZ in power down mode</description>
25473              <bitRange>[10:10]</bitRange>
25474              <access>read-write</access>
25475            </field>
25476            <field>
25477              <name>MIC_PGA_GAIN_CTRL</name>
25478              <description>MIC PGA gain control: 1dB steps
25479 000000 : 0  dB
25480 000001 : 1  dB
25481 000010 : 2  dB
25482 000011 : 3  dB
25483 000100 : 4  dB
25484 000101 : 5  dB
25485 000110 : 6  dB
25486 000111 : 7  dB
25487 001000 : 8  dB
25488 001001 : 9  dB
25489 001010 : 10 dB
25490 001011 : 11 dB
25491 001100 : 12 dB
25492 001101 : 13 dB
25493 001110 : 14 dB
25494 001111 : 15 dB
25495 010000 : 16 dB
25496 010001 : 17 dB
25497 010010 : 18 dB
25498 010011 : 19 dB
25499 010100 : 20 dB
25500 010101 : 21 dB
25501 010110 : 22 dB
25502 010111 : 23 dB
25503 011000 : 24 dB
25504 011001 : 25 dB
25505 011010 : 26 dB
25506 011011 : 27 dB
25507 011100 : 28 dB
25508 011101 : 29 dB
25509 011110 : 30 dB
25510 011111 : 31 dB
25511 100000 : 32 dB
25512 100001 : 33 dB
25513 100010 : 34 dB
25514 100011 : 35 dB
25515 100100 : 36 dB
25516 100101 : 37 dB
25517 100110 : 38 dB
25518 100111 : 39 dB
25519 101000 : 40 dB
25520 101001 : 41 dB
25521 101010 : 42 dB</description>
25522              <bitRange>[16:11]</bitRange>
25523              <access>read-write</access>
25524            </field>
25525            <field>
25526              <name>MIC_PGA_INCM_CTRL</name>
25527              <description>PGA input common mode control 01 : 0.45 * avdd 00 : 0.4 * avdd 10 : 0.35 * avdd</description>
25528              <bitRange>[18:17]</bitRange>
25529              <access>read-write</access>
25530            </field>
25531            <field>
25532              <name>MIC_PGA_OUTCM_CTRL</name>
25533              <description>PGA output common mode control
25534 01 : 0.7
25535 00 : 0.6
25536 10 : 0.5</description>
25537              <bitRange>[20:19]</bitRange>
25538              <access>read-write</access>
25539            </field>
25540            <field>
25541              <name>MIC_PGA_CLAMPVREF_CTRL</name>
25542              <description>PGA clamp threshold voltage control
25543 01 : 0.92  V
25544 00 : 0.95  V
25545 10 : 0.975 V
25546 11 : 1     V</description>
25547              <bitRange>[22:21]</bitRange>
25548              <access>read-write</access>
25549            </field>
25550            <field>
25551              <name>MIC_NEG_INPUT_SLT</name>
25552              <description>N/A</description>
25553              <bitRange>[23:23]</bitRange>
25554              <access>read-write</access>
25555            </field>
25556          </fields>
25557        </register>
25558        <register>
25559          <name>ADC_SPARE</name>
25560          <description>Spare registers in the ADC block</description>
25561          <addressOffset>0x118</addressOffset>
25562          <size>32</size>
25563          <access>read-write</access>
25564          <resetValue>0x0</resetValue>
25565          <resetMask>0x3FF</resetMask>
25566          <fields>
25567            <field>
25568              <name>ADC_SPARE</name>
25569              <description>Spare Bits
25570 adc_spare[7] External reset of ADC
25571 0: Disabled
25572 1: Enabled</description>
25573              <bitRange>[9:0]</bitRange>
25574              <access>read-write</access>
25575            </field>
25576          </fields>
25577        </register>
25578        <register>
25579          <name>AUXADC_CTRL</name>
25580          <description>Register to control AuxAdcDecim operation</description>
25581          <addressOffset>0x200</addressOffset>
25582          <size>32</size>
25583          <access>read-write</access>
25584          <resetValue>0x4300</resetValue>
25585          <resetMask>0xFF7D</resetMask>
25586          <fields>
25587            <field>
25588              <name>EN</name>
25589              <description>When 1 enable the aux_adc block</description>
25590              <bitRange>[0:0]</bitRange>
25591              <access>read-write</access>
25592            </field>
25593            <field>
25594              <name>DF3_BYPASS</name>
25595              <description>When 1 bypass df3 FIR completely else FIR is enabled</description>
25596              <bitRange>[2:2]</bitRange>
25597              <access>read-write</access>
25598            </field>
25599            <field>
25600              <name>BIQUAD_BYPASS</name>
25601              <description>When 1 bypass biquad completely else biquad is enabled</description>
25602              <bitRange>[3:3]</bitRange>
25603              <access>read-write</access>
25604            </field>
25605            <field>
25606              <name>DFMODE</name>
25607              <description>Mode of Operation
25608 0 : DC mode, 480kHz, fast:   with DC convergence time of 10^-6 seconds
25609 1 : DC mode, 480kHz, medium: with DC convergence time of 15^-6 seconds
25610 2 : DC mode, 480kHz, slow:   with DC convergence time of 20^-6 seconds
25611 3 : Audio mode, 16kHz, analog mic
25612 4 : Audio mode, 16kHz, digital mic
25613 5 : Audio mode, 8kHz, analog mic
25614 6 : Audio mode, 8kHz, digital mic</description>
25615              <bitRange>[6:4]</bitRange>
25616              <access>read-write</access>
25617            </field>
25618            <field>
25619              <name>MPR0</name>
25620              <description>Mapping bits mpr0 that maps to ADC data 00 or PDM data 0</description>
25621              <bitRange>[9:8]</bitRange>
25622              <access>read-write</access>
25623            </field>
25624            <field>
25625              <name>MPR1</name>
25626              <description>Mapping bits mpr1 that maps to ADC data 01</description>
25627              <bitRange>[11:10]</bitRange>
25628              <access>read-write</access>
25629            </field>
25630            <field>
25631              <name>MPR2</name>
25632              <description>Mapping bits mpr2 that maps to ADC data 10</description>
25633              <bitRange>[13:12]</bitRange>
25634              <access>read-write</access>
25635            </field>
25636            <field>
25637              <name>MPR3</name>
25638              <description>Mapping bits mpr3 that maps to ADC data 11 or PDM data 1</description>
25639              <bitRange>[15:14]</bitRange>
25640              <access>read-write</access>
25641            </field>
25642          </fields>
25643        </register>
25644        <register>
25645          <name>AUXADC_CIC_CTRL</name>
25646          <description>Register to control CIC operation in AuxAdcDecim block</description>
25647          <addressOffset>0x204</addressOffset>
25648          <size>32</size>
25649          <access>read-write</access>
25650          <resetValue>0x0</resetValue>
25651          <resetMask>0xFFFF</resetMask>
25652          <fields>
25653            <field>
25654              <name>CIC_GAIN</name>
25655              <description>CIC gain value that will be used only during override. This will be used only when AUXADC_OVERRIDE[22] is set</description>
25656              <bitRange>[15:0]</bitRange>
25657              <access>read-write</access>
25658            </field>
25659          </fields>
25660        </register>
25661        <register>
25662          <name>AUXADC_OVERRIDE</name>
25663          <description>Register that holds the override values for AuxAdcDecim block</description>
25664          <addressOffset>0x208</addressOffset>
25665          <size>32</size>
25666          <access>read-write</access>
25667          <resetValue>0x0</resetValue>
25668          <resetMask>0x7FFFFF</resetMask>
25669          <fields>
25670            <field>
25671              <name>OVERRIDE</name>
25672              <description>Override Values for Auxadc. When override[22] is set then the remaining buts will override the default values within the matlab model generated RTL code
25673 Bit  22    When set the values below are used to configure the auxAdcDecim block otherwise it defaults to the default values within the matlab generated code
25674 The cic gain is picked from the AUXADC_CIC_CTRL register when this is set. In the matlab model this is based on dfmode as follows:
25675 dfmode 000     : 16'h68DC
25676 dfmode 001     : 16'h8638
25677 dfmode 010     : 16'h2CBD
25678 dfmode 011     : 16'hD1B7
25679 dfmode 100     : 16'h51EC
25680 dfmode 101     : 16'h346E
25681 dfmode default : 16'hA3D7
25682 Bits 21:16 Sets up counters for various modes of operation - In the matlab model this is based on dfmode as follows:
25683 dfmode 000     : 6'b000100
25684 dfmode 001     : 6'b000100
25685 dfmode 010     : 6'b000100
25686 dfmode 011     : 6'b000100
25687 dfmode 100     : 6'b000100
25688 dfmode 101     : 6'b001001
25689 dfmode default : 6'b001001
25690 Bits 15:13 Sets up counters for CIC integrator to sample input - is a constant 3'b100 in the matlab model and is used when pdm is not enabled
25691 Bits 12:10 The gain in the CIC integrator. In the matlab model this is based on dfmode as follows:
25692 dfmode 000     : 3'b011
25693 dfmode 001     : 3'b101
25694 dfmode 010     : 3'b101
25695 dfmode 011     : 3'b011
25696 dfmode 100     : 3'b001
25697 dfmode 101     : 3'b011
25698 dfmode default : 3'b010
25699 Bits 09    Used for enabling pdm mode. In the matlab model this is set to 1 if dfmode is 4 or 6 and is the select of a mux that selects the pulse to sample pdm data.
25700 Bits 08    This bit when set bypasses the 3rd stage of the integration in CIC. In the matlab model this is based on dfmode as follows:
25701 dfmode 000     : 1'b1
25702 dfmode 001     : 1'b0
25703 dfmode 010     : 1'b0
25704 dfmode 011     : 1'b1
25705 dfmode 100     : 1'b1
25706 dfmode 101     : 1'b1
25707 dfmode default : 1'b1
25708 Bits 07:06 The delay in the first stage of CIC differntiator. In the matlab model this is based on dfmode as follows:
25709 dfmode 000     : 2'b01
25710 dfmode 001     : 2'b01
25711 dfmode 010     : 2'b11
25712 dfmode 011     : 2'b00
25713 dfmode 100     : 2'b00
25714 dfmode 101     : 2'b00
25715 dfmode default : 2'b00
25716 Bits 05:04 The delay in the second stage of CIC differntiator. In the matlab model this is based on dfmode as follows:
25717 dfmode 000     : 2'b00
25718 dfmode 001     : 2'b01
25719 dfmode 010     : 2'b10
25720 dfmode 011     : 2'b00
25721 dfmode 100     : 2'b00
25722 dfmode 101     : 2'b00
25723 dfmode default : 2'b00
25724 Bits 03    The delay in the third stage of CIC differntiator. In the matlab model this is constant 0 irrespective of dfmode
25725 Bits 02:0  Enables various filters in the design.
25726 If the value is &gt;=1 then df1 is enabled
25727 if &gt;=2 then df2 is enabled
25728 if &gt;=3 then df3 is enabled
25729 if &gt;=4 then biquad is enabled.
25730 In the matlab model this is based on dfmode as follows:
25731 dfmode 000     : 3'b000
25732 dfmode 001     : 3'b000
25733 dfmode 010     : 3'b000
25734 dfmode 011     : 3'b100
25735 dfmode 100     : 3'b100
25736 dfmode 101     : 3'b100
25737 dfmode default : 3'b100</description>
25738              <bitRange>[22:0]</bitRange>
25739              <access>read-write</access>
25740            </field>
25741          </fields>
25742        </register>
25743        <register>
25744          <name>AUXADC_DF3_COEFF</name>
25745          <description>Register that controls the RAM operation for writing DF3 Coefficients into the RAM</description>
25746          <addressOffset>0x20C</addressOffset>
25747          <size>32</size>
25748          <access>read-write</access>
25749          <resetValue>0x8000</resetValue>
25750          <resetMask>0xFFFF81F7</resetMask>
25751          <fields>
25752            <field>
25753              <name>DF3_COEFF_SEL</name>
25754              <description>Sel for selecting Coefficient of df3 from the ram during the filtering at this stage</description>
25755              <bitRange>[0:0]</bitRange>
25756              <access>read-write</access>
25757            </field>
25758            <field>
25759              <name>DF3_COEFF_PGM_EN</name>
25760              <description>Enable this bit before the df3_coeff ram can be programmed</description>
25761              <bitRange>[1:1]</bitRange>
25762              <access>read-write</access>
25763            </field>
25764            <field>
25765              <name>DF3_COEFF_WREN</name>
25766              <description>Write Enable for writing Coefficient of df3</description>
25767              <bitRange>[2:2]</bitRange>
25768              <access>read-write</access>
25769            </field>
25770            <field>
25771              <name>DF3_COEFF_ADDR</name>
25772              <description>Address for writing Coefficient of df3</description>
25773              <bitRange>[8:4]</bitRange>
25774              <access>read-write</access>
25775            </field>
25776            <field>
25777              <name>DF3_ACCESS_DONE</name>
25778              <description>Hardware sets this bit when the operation is done while software clears this bit to start operation</description>
25779              <bitRange>[15:15]</bitRange>
25780              <access>read-write</access>
25781            </field>
25782            <field>
25783              <name>DF3_COEFF_DATA</name>
25784              <description>Data for writing Coefficient of df3 during the write cycle and read data during the read cycle</description>
25785              <bitRange>[31:16]</bitRange>
25786              <access>read-write</access>
25787            </field>
25788          </fields>
25789        </register>
25790        <register>
25791          <name>AUXADC_BIQUAD0_COEFF_0</name>
25792          <description>Register holding the coefficients for BIQUAD0 operation.</description>
25793          <addressOffset>0x210</addressOffset>
25794          <size>32</size>
25795          <access>read-write</access>
25796          <resetValue>0x81B23F27</resetValue>
25797          <resetMask>0xFFFFFFFF</resetMask>
25798          <fields>
25799            <field>
25800              <name>BQ0_NUM1_COEFF</name>
25801              <description>Coefficient for biquad0_num1</description>
25802              <bitRange>[15:0]</bitRange>
25803              <access>read-write</access>
25804            </field>
25805            <field>
25806              <name>BQ0_NUM2_COEFF</name>
25807              <description>Coefficient for biquad0_num2</description>
25808              <bitRange>[31:16]</bitRange>
25809              <access>read-write</access>
25810            </field>
25811          </fields>
25812        </register>
25813        <register>
25814          <name>AUXADC_BIQUAD0_COEFF_1</name>
25815          <description>Register holding the coefficients for BIQUAD0 operation.</description>
25816          <addressOffset>0x214</addressOffset>
25817          <size>32</size>
25818          <access>read-write</access>
25819          <resetValue>0x3F27</resetValue>
25820          <resetMask>0xFFFF</resetMask>
25821          <fields>
25822            <field>
25823              <name>BQ0_NUM3_COEFF</name>
25824              <description>Coefficient for biquad0_num1</description>
25825              <bitRange>[15:0]</bitRange>
25826              <access>read-write</access>
25827            </field>
25828          </fields>
25829        </register>
25830        <register>
25831          <name>AUXADC_BIQUAD0_COEFF_2</name>
25832          <description>Register holding the coefficients for BIQUAD0 operation.</description>
25833          <addressOffset>0x218</addressOffset>
25834          <size>32</size>
25835          <access>read-write</access>
25836          <resetValue>0x3E5181B5</resetValue>
25837          <resetMask>0xFFFFFFFF</resetMask>
25838          <fields>
25839            <field>
25840              <name>BQ0_DEN2_COEFF</name>
25841              <description>Coefficient for biquad0_num1</description>
25842              <bitRange>[15:0]</bitRange>
25843              <access>read-write</access>
25844            </field>
25845            <field>
25846              <name>BQ0_DEN3_COEFF</name>
25847              <description>Coefficient for biquad0_num2</description>
25848              <bitRange>[31:16]</bitRange>
25849              <access>read-write</access>
25850            </field>
25851          </fields>
25852        </register>
25853        <register>
25854          <name>AUXADC_BIQUAD1_COEFF_0</name>
25855          <description>Register holding the coefficients for BIQUAD1 operation.</description>
25856          <addressOffset>0x21C</addressOffset>
25857          <size>32</size>
25858          <access>read-write</access>
25859          <resetValue>0x4CCF</resetValue>
25860          <resetMask>0xFFFFFFFF</resetMask>
25861          <fields>
25862            <field>
25863              <name>BQ1_NUM1_COEFF</name>
25864              <description>Coefficient for biquad1_num1</description>
25865              <bitRange>[15:0]</bitRange>
25866              <access>read-write</access>
25867            </field>
25868            <field>
25869              <name>BQ1_NUM2_COEFF</name>
25870              <description>Coefficient for biquad1_num2</description>
25871              <bitRange>[31:16]</bitRange>
25872              <access>read-write</access>
25873            </field>
25874          </fields>
25875        </register>
25876        <register>
25877          <name>AUXADC_BIQUAD1_COEFF_1</name>
25878          <description>Register holding the coefficients for BIQUAD1 operation.</description>
25879          <addressOffset>0x220</addressOffset>
25880          <size>32</size>
25881          <access>read-write</access>
25882          <resetValue>0x0</resetValue>
25883          <resetMask>0xFFFF</resetMask>
25884          <fields>
25885            <field>
25886              <name>BQ1_NUM3_COEFF</name>
25887              <description>Coefficient for biquad1_num1</description>
25888              <bitRange>[15:0]</bitRange>
25889              <access>read-write</access>
25890            </field>
25891          </fields>
25892        </register>
25893        <register>
25894          <name>AUXADC_BIQUAD1_COEFF_2</name>
25895          <description>Register holding the coefficients for BIQUAD1 operation.</description>
25896          <addressOffset>0x224</addressOffset>
25897          <size>32</size>
25898          <access>read-write</access>
25899          <resetValue>0x0</resetValue>
25900          <resetMask>0xFFFFFFFF</resetMask>
25901          <fields>
25902            <field>
25903              <name>BQ1_DEN2_COEFF</name>
25904              <description>Coefficient for biquad1_num1</description>
25905              <bitRange>[15:0]</bitRange>
25906              <access>read-write</access>
25907            </field>
25908            <field>
25909              <name>BQ1_DEN3_COEFF</name>
25910              <description>Coefficient for biquad1_num2</description>
25911              <bitRange>[31:16]</bitRange>
25912              <access>read-write</access>
25913            </field>
25914          </fields>
25915        </register>
25916        <register>
25917          <name>AUXADC_BIQUAD2_COEFF_0</name>
25918          <description>Register holding the coefficients for BIQUAD2 operation.</description>
25919          <addressOffset>0x228</addressOffset>
25920          <size>32</size>
25921          <access>read-write</access>
25922          <resetValue>0x4000</resetValue>
25923          <resetMask>0xFFFFFFFF</resetMask>
25924          <fields>
25925            <field>
25926              <name>BQ2_NUM1_COEFF</name>
25927              <description>Coefficient for biquad2_num1</description>
25928              <bitRange>[15:0]</bitRange>
25929              <access>read-write</access>
25930            </field>
25931            <field>
25932              <name>BQ2_NUM2_COEFF</name>
25933              <description>Coefficient for biquad2_num2</description>
25934              <bitRange>[31:16]</bitRange>
25935              <access>read-write</access>
25936            </field>
25937          </fields>
25938        </register>
25939        <register>
25940          <name>AUXADC_BIQUAD2_COEFF_1</name>
25941          <description>Register holding the coefficients for BIQUAD2 operation.</description>
25942          <addressOffset>0x22C</addressOffset>
25943          <size>32</size>
25944          <access>read-write</access>
25945          <resetValue>0x0</resetValue>
25946          <resetMask>0xFFFF</resetMask>
25947          <fields>
25948            <field>
25949              <name>BQ2_NUM3_COEFF</name>
25950              <description>Coefficient for biquad2_num1</description>
25951              <bitRange>[15:0]</bitRange>
25952              <access>read-write</access>
25953            </field>
25954          </fields>
25955        </register>
25956        <register>
25957          <name>AUXADC_BIQUAD2_COEFF_2</name>
25958          <description>Register holding the coefficients for BIQUAD2 operation.</description>
25959          <addressOffset>0x230</addressOffset>
25960          <size>32</size>
25961          <access>read-write</access>
25962          <resetValue>0x0</resetValue>
25963          <resetMask>0xFFFFFFFF</resetMask>
25964          <fields>
25965            <field>
25966              <name>BQ2_DEN2_COEFF</name>
25967              <description>Coefficient for biquad2_num1</description>
25968              <bitRange>[15:0]</bitRange>
25969              <access>read-write</access>
25970            </field>
25971            <field>
25972              <name>BQ2_DEN3_COEFF</name>
25973              <description>Coefficient for biquad2_num2</description>
25974              <bitRange>[31:16]</bitRange>
25975              <access>read-write</access>
25976            </field>
25977          </fields>
25978        </register>
25979        <register>
25980          <name>AUXADC_BIQUAD3_COEFF_0</name>
25981          <description>Register holding the coefficients for BIQUAD3 operation.</description>
25982          <addressOffset>0x234</addressOffset>
25983          <size>32</size>
25984          <access>read-write</access>
25985          <resetValue>0x4000</resetValue>
25986          <resetMask>0xFFFFFFFF</resetMask>
25987          <fields>
25988            <field>
25989              <name>BQ3_NUM1_COEFF</name>
25990              <description>Coefficient for biquad3_num1</description>
25991              <bitRange>[15:0]</bitRange>
25992              <access>read-write</access>
25993            </field>
25994            <field>
25995              <name>BQ3_NUM2_COEFF</name>
25996              <description>Coefficient for biquad3_num2</description>
25997              <bitRange>[31:16]</bitRange>
25998              <access>read-write</access>
25999            </field>
26000          </fields>
26001        </register>
26002        <register>
26003          <name>AUXADC_BIQUAD3_COEFF_1</name>
26004          <description>Register holding the coefficients for BIQUAD3 operation.</description>
26005          <addressOffset>0x238</addressOffset>
26006          <size>32</size>
26007          <access>read-write</access>
26008          <resetValue>0x0</resetValue>
26009          <resetMask>0xFFFF</resetMask>
26010          <fields>
26011            <field>
26012              <name>BQ3_NUM3_COEFF</name>
26013              <description>'Coefficient for biquad3_num1</description>
26014              <bitRange>[15:0]</bitRange>
26015              <access>read-write</access>
26016            </field>
26017          </fields>
26018        </register>
26019        <register>
26020          <name>AUXADC_BIQUAD3_COEFF_2</name>
26021          <description>Register holding the coefficients for BIQUAD3 operation.</description>
26022          <addressOffset>0x23C</addressOffset>
26023          <size>32</size>
26024          <access>read-write</access>
26025          <resetValue>0x0</resetValue>
26026          <resetMask>0xFFFFFFFF</resetMask>
26027          <fields>
26028            <field>
26029              <name>BQ3_DEN2_COEFF</name>
26030              <description>Coefficient for biquad3_num1</description>
26031              <bitRange>[15:0]</bitRange>
26032              <access>read-write</access>
26033            </field>
26034            <field>
26035              <name>BQ3_DEN3_COEFF</name>
26036              <description>Coefficient for biquad3_num2</description>
26037              <bitRange>[31:16]</bitRange>
26038              <access>read-write</access>
26039            </field>
26040          </fields>
26041        </register>
26042        <register>
26043          <name>AUXADC_BIQUAD4_COEFF_0</name>
26044          <description>Register holding the coefficients for BIQUAD4 operation.</description>
26045          <addressOffset>0x240</addressOffset>
26046          <size>32</size>
26047          <access>read-write</access>
26048          <resetValue>0x4000</resetValue>
26049          <resetMask>0xFFFFFFFF</resetMask>
26050          <fields>
26051            <field>
26052              <name>BQ4_NUM1_COEFF</name>
26053              <description>Coefficient for biquad4_num1</description>
26054              <bitRange>[15:0]</bitRange>
26055              <access>read-write</access>
26056            </field>
26057            <field>
26058              <name>BQ4_NUM2_COEFF</name>
26059              <description>Coefficient for biquad4_num2</description>
26060              <bitRange>[31:16]</bitRange>
26061              <access>read-write</access>
26062            </field>
26063          </fields>
26064        </register>
26065        <register>
26066          <name>AUXADC_BIQUAD4_COEFF_1</name>
26067          <description>Register holding the coefficients for BIQUAD4 operation.</description>
26068          <addressOffset>0x244</addressOffset>
26069          <size>32</size>
26070          <access>read-write</access>
26071          <resetValue>0x0</resetValue>
26072          <resetMask>0xFFFF</resetMask>
26073          <fields>
26074            <field>
26075              <name>BQ4_NUM3_COEFF</name>
26076              <description>Coefficient for biquad4_num1</description>
26077              <bitRange>[15:0]</bitRange>
26078              <access>read-write</access>
26079            </field>
26080          </fields>
26081        </register>
26082        <register>
26083          <name>AUXADC_BIQUAD4_COEFF_2</name>
26084          <description>Register holding the coefficients for BIQUAD4 operation.</description>
26085          <addressOffset>0x248</addressOffset>
26086          <size>32</size>
26087          <access>read-write</access>
26088          <resetValue>0x0</resetValue>
26089          <resetMask>0xFFFFFFFF</resetMask>
26090          <fields>
26091            <field>
26092              <name>BQ4_DEN2_COEFF</name>
26093              <description>Coefficient for biquad4_num1</description>
26094              <bitRange>[15:0]</bitRange>
26095              <access>read-write</access>
26096            </field>
26097            <field>
26098              <name>BQ4_DEN3_COEFF</name>
26099              <description>Coefficient for biquad4_num2</description>
26100              <bitRange>[31:16]</bitRange>
26101              <access>read-write</access>
26102            </field>
26103          </fields>
26104        </register>
26105        <register>
26106          <name>AUXADC_CIC_STATUS</name>
26107          <description>Status of the CIC in AuxAdcDecim block</description>
26108          <addressOffset>0x250</addressOffset>
26109          <size>32</size>
26110          <access>read-write</access>
26111          <resetValue>0x0</resetValue>
26112          <resetMask>0x10000</resetMask>
26113          <fields>
26114            <field>
26115              <name>CIC</name>
26116              <description>Computed cic value</description>
26117              <bitRange>[15:0]</bitRange>
26118              <access>read-only</access>
26119            </field>
26120            <field>
26121              <name>LATCH_ON_TIMER</name>
26122              <description>Latches continously by default but when set to 1 it latches on timer</description>
26123              <bitRange>[16:16]</bitRange>
26124              <access>read-write</access>
26125            </field>
26126          </fields>
26127        </register>
26128        <register>
26129          <name>AUXADC_DF1_STATUS</name>
26130          <description>Status of the DF1 FIR Filter in AuxAdcDecim block</description>
26131          <addressOffset>0x254</addressOffset>
26132          <size>32</size>
26133          <access>read-only</access>
26134          <resetValue>0x0</resetValue>
26135          <resetMask>0x0</resetMask>
26136          <fields>
26137            <field>
26138              <name>DF1</name>
26139              <description>Computed df1 value</description>
26140              <bitRange>[15:0]</bitRange>
26141              <access>read-only</access>
26142            </field>
26143          </fields>
26144        </register>
26145        <register>
26146          <name>AUXADC_DF2_STATUS</name>
26147          <description>Status of the DF2 FIR Filter in AuxAdcDecim block</description>
26148          <addressOffset>0x258</addressOffset>
26149          <size>32</size>
26150          <access>read-only</access>
26151          <resetValue>0x0</resetValue>
26152          <resetMask>0x0</resetMask>
26153          <fields>
26154            <field>
26155              <name>DF2</name>
26156              <description>Computed df2 value</description>
26157              <bitRange>[15:0]</bitRange>
26158              <access>read-only</access>
26159            </field>
26160          </fields>
26161        </register>
26162        <register>
26163          <name>AUXADC_DF3_STATUS</name>
26164          <description>Status of the DF3 FIR Filter in AuxAdcDecim block</description>
26165          <addressOffset>0x25C</addressOffset>
26166          <size>32</size>
26167          <access>read-only</access>
26168          <resetValue>0x0</resetValue>
26169          <resetMask>0x0</resetMask>
26170          <fields>
26171            <field>
26172              <name>DF3</name>
26173              <description>Computed df3 value</description>
26174              <bitRange>[15:0]</bitRange>
26175              <access>read-only</access>
26176            </field>
26177          </fields>
26178        </register>
26179        <register>
26180          <name>AUXADC_BIQUAD_STATUS</name>
26181          <description>Status of the BIQUAD IIR  Filter in AuxAdcDecim block</description>
26182          <addressOffset>0x260</addressOffset>
26183          <size>32</size>
26184          <access>read-only</access>
26185          <resetValue>0x0</resetValue>
26186          <resetMask>0x0</resetMask>
26187          <fields>
26188            <field>
26189              <name>BQ</name>
26190              <description>Computed bq value</description>
26191              <bitRange>[15:0]</bitRange>
26192              <access>read-only</access>
26193            </field>
26194          </fields>
26195        </register>
26196      </registers>
26197    </peripheral>
26198    <peripheral>
26199      <name>SCB0</name>
26200      <description>Serial Communications Block (SPI/UART/I2C)</description>
26201      <headerStructName>SCB</headerStructName>
26202      <baseAddress>0x40590000</baseAddress>
26203      <addressBlock>
26204        <offset>0</offset>
26205        <size>65536</size>
26206        <usage>registers</usage>
26207      </addressBlock>
26208      <registers>
26209        <register>
26210          <name>CTRL</name>
26211          <description>Generic control</description>
26212          <addressOffset>0x0</addressOffset>
26213          <size>32</size>
26214          <access>read-write</access>
26215          <resetValue>0x300400F</resetValue>
26216          <resetMask>0x9303D70F</resetMask>
26217          <fields>
26218            <field>
26219              <name>OVS</name>
26220              <description>N/A</description>
26221              <bitRange>[3:0]</bitRange>
26222              <access>read-write</access>
26223            </field>
26224            <field>
26225              <name>EC_AM_MODE</name>
26226              <description>Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI). In internally clocked mode, the serial interface protocols run off the peripheral clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. Externally clocked mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported.
26227
26228In UART mode this field should be '0'.</description>
26229              <bitRange>[8:8]</bitRange>
26230              <access>read-write</access>
26231            </field>
26232            <field>
26233              <name>EC_OP_MODE</name>
26234              <description>Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode, the serial interface protocols run off the peripheral clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. Externally clocked operation mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode AND EZ mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. The maximum SPI slave, EZ mode bitrate is 48 Mbps (transmission and IO delays outside the IP will degrade the effective bitrate).
26235
26236In UART mode this field should be '0'.</description>
26237              <bitRange>[9:9]</bitRange>
26238              <access>read-write</access>
26239            </field>
26240            <field>
26241              <name>EZ_MODE</name>
26242              <description>Non EZ mode ('0') or EZ mode ('1'). In EZ mode, a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory address, a write memory data element or a read memory data element. EZ mode is only used for synchronous serial interface protocols: SPI and I2C. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported and the transmitter should use continuous data frames; i.e. data frames mot separated by slave deselection. This mode is only applicable to slave functionality. In EZ mode, the slave can read from and write to an addressable memory structure of up to 256 bytes. In EZ mode, data frames should 8-bit in size and should be transmitted and received with the Most Significant Bit (MSB) first.
26243
26244In UART mode this field should be '0'.</description>
26245              <bitRange>[10:10]</bitRange>
26246              <access>read-write</access>
26247            </field>
26248            <field>
26249              <name>CMD_RESP_MODE</name>
26250              <description>Determines CMD_RESP mode of operation:
26251'0': CMD_RESP mode disabled.
26252'1': CMD_RESP mode enabled (also requires EC_AM_MODE and EC_OP_MODE to be set to '1').</description>
26253              <bitRange>[12:12]</bitRange>
26254              <access>read-write</access>
26255            </field>
26256            <field>
26257              <name>MEM_WIDTH</name>
26258              <description>Determines the number of bits per FIFO data element, depending on physical SRAM cell data width.
26259On M0S8/MXS40S platform, the SRAM data width is 16 bit, so WORD (2) is not supported.
26260On MXS40E platform, the SRAM data width is 32 bits.</description>
26261              <bitRange>[15:14]</bitRange>
26262              <access>read-write</access>
26263              <enumeratedValues>
26264                <enumeratedValue>
26265                  <name>BYTE</name>
26266                  <description>8-bit FIFO data elements.
26267This mode provides the biggest amount of FIFO entries, but  TX_CTRL.DATA_WIDTH and RX_CTRL.DATA_WIDTH are restricted to [0, 7].</description>
26268                  <value>0</value>
26269                </enumeratedValue>
26270                <enumeratedValue>
26271                  <name>HALFWORD</name>
26272                  <description>16-bit FIFO data elements.
26273TX_CTRL.DATA_WIDTH and RX_CTRL.DATA_WIDTH are restricted to [0, 15].</description>
26274                  <value>1</value>
26275                </enumeratedValue>
26276                <enumeratedValue>
26277                  <name>WORD</name>
26278                  <description>32-bit FIFO data elements.
26279This mode provides the smallest amount of FIFO entries, but TX_CTRL.DATA_WIDTH and RX_CTRL.DATA_WIDTH can be in a range of [0, 31].</description>
26280                  <value>2</value>
26281                </enumeratedValue>
26282                <enumeratedValue>
26283                  <name>RSVD</name>
26284                  <description>N/A</description>
26285                  <value>3</value>
26286                </enumeratedValue>
26287              </enumeratedValues>
26288            </field>
26289            <field>
26290              <name>ADDR_ACCEPT</name>
26291              <description>Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0').
26292
26293In I2C mode, this field is used to allow the slave to put the received slave address or general call address in the RX FIFO. Note that a received matching address is put in the RX FIFO when ADDR_ACCEPT is '1' for both I2C read and write transfers.
26294
26295In multi-processor UART receiver mode, this field is used to allow the receiver to put the received address in the RX FIFO. Note: non-matching addresses are never put in the RX FIFO.</description>
26296              <bitRange>[16:16]</bitRange>
26297              <access>read-write</access>
26298            </field>
26299            <field>
26300              <name>BLOCK</name>
26301              <description>Only used in externally clocked mode. If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide, this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0'). IF BLOCK is '0' and the accesses collide, MMIO read operations return 0xffff:ffff and MMIO write operations are ignored. Colliding accesses are registered as interrupt causes: field BLOCKED of MMIO registers INTR_TX and INTR_RX.</description>
26302              <bitRange>[17:17]</bitRange>
26303              <access>read-write</access>
26304            </field>
26305            <field>
26306              <name>MODE</name>
26307              <description>N/A</description>
26308              <bitRange>[25:24]</bitRange>
26309              <access>read-write</access>
26310              <enumeratedValues>
26311                <enumeratedValue>
26312                  <name>I2C</name>
26313                  <description>Inter-Integrated Circuits (I2C) mode.</description>
26314                  <value>0</value>
26315                </enumeratedValue>
26316                <enumeratedValue>
26317                  <name>SPI</name>
26318                  <description>Serial Peripheral Interface (SPI) mode.</description>
26319                  <value>1</value>
26320                </enumeratedValue>
26321                <enumeratedValue>
26322                  <name>UART</name>
26323                  <description>Universal Asynchronous Receiver/Transmitter (UART) mode.</description>
26324                  <value>2</value>
26325                </enumeratedValue>
26326              </enumeratedValues>
26327            </field>
26328            <field>
26329              <name>EC_ACCESS</name>
26330              <description>used to enable I2CS_EC or SPIS_EC access to internal SRAM memory.
263310: enable clock_scb_en, has no effect on ec_busy_pp
263321: disable clock_scb_en, enable ec_busy_pp (grant I2CS_EC or SPIS_EC access)
26333
26334Before going to deepsleep this field should be set to 1.
26335when waking up from DeepSleep power mode, and PLL is locked (clk_scb is at expected frequency), this filed should be set to 0.</description>
26336              <bitRange>[28:28]</bitRange>
26337              <access>read-write</access>
26338            </field>
26339            <field>
26340              <name>ENABLED</name>
26341              <description>IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as follows:
26342- Program protocol specific information using SPI_CTRL, UART_CTRL (and UART_TX_CTRL and UART_RX_CTRL) or I2C_CTRL. This includes selection of a submode, master/slave functionality and transmitter/receiver functionality when applicable.
26343- Program generic transmitter (TX_CTRL) and receiver (RX_CTRL) information. This includes enabling of the transmitter and receiver functionality.
26344- Program transmitter FIFO (TX_FIFO_CTRL) and receiver FIFO (RX_FIFO_CTRL) information.
26345- Program CTRL to enable IP, select the specific operation mode and oversampling factor.
26346Generally hen the IP is enabled, no control information should be changed. Changes should be made AFTER disabling the IP, e.g. to modify the operation mode (from I2C to SPI) or to go from externally to internally clocked. The change takes effect after the IP is re-enabled. Note that disabling the IP will cause re-initialization of the design and associated state is lost (e.g. FIFO content).
26347
26348Specific to SPI master case,  when SCB is idle,  below registers can be changed without disabling SCB block,
26349      TX_CTRL
26350      TX_FIFO_CTRL
26351      RX_CTRL
26352      RX_FIFO_CTRL
26353      SPI_CTRL.SSEL,</description>
26354              <bitRange>[31:31]</bitRange>
26355              <access>read-write</access>
26356            </field>
26357          </fields>
26358        </register>
26359        <register>
26360          <name>STATUS</name>
26361          <description>Generic status</description>
26362          <addressOffset>0x4</addressOffset>
26363          <size>32</size>
26364          <access>read-only</access>
26365          <resetValue>0x0</resetValue>
26366          <resetMask>0x0</resetMask>
26367          <fields>
26368            <field>
26369              <name>EC_BUSY</name>
26370              <description>Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a blocked SW access) or bus errors being generated). Note that the INTR_TX.BLOCKED and INTR_RX.BLOCKED interrupt causes are used to indicate whether a SW access was actually blocked by externally clocked logic.</description>
26371              <bitRange>[0:0]</bitRange>
26372              <access>read-only</access>
26373            </field>
26374          </fields>
26375        </register>
26376        <register>
26377          <name>CMD_RESP_CTRL</name>
26378          <description>Command/response control</description>
26379          <addressOffset>0x8</addressOffset>
26380          <size>32</size>
26381          <access>read-write</access>
26382          <resetValue>0x0</resetValue>
26383          <resetMask>0x1FF01FF</resetMask>
26384          <fields>
26385            <field>
26386              <name>BASE_RD_ADDR</name>
26387              <description>I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode read transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode read transfer (CTRL.MODE is SPI): at the start of a read transfer BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers.</description>
26388              <bitRange>[8:0]</bitRange>
26389              <access>read-write</access>
26390            </field>
26391            <field>
26392              <name>BASE_WR_ADDR</name>
26393              <description>I2C/SPI write base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode write transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode write transfer (CTRL.MODE is SPI): at the start of a write transfer BASE_WE_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers.</description>
26394              <bitRange>[24:16]</bitRange>
26395              <access>read-write</access>
26396            </field>
26397          </fields>
26398        </register>
26399        <register>
26400          <name>CMD_RESP_STATUS</name>
26401          <description>Command/response status</description>
26402          <addressOffset>0xC</addressOffset>
26403          <size>32</size>
26404          <access>read-only</access>
26405          <resetValue>0x0</resetValue>
26406          <resetMask>0x0</resetMask>
26407          <fields>
26408            <field>
26409              <name>CURR_RD_ADDR</name>
26410              <description>I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximum memory buffer address).
26411
26412The field is used to determine how many bytes have been read (# bytes = CURR_RD_ADDR - CMD_RESP_CTRL.BASE_RD_ADDR).
26413
26414This field is reliable during when there is no bus transfer. This field is potentially unreliable when there is a bus transfer bus transfer: when CMD_RESP_EC_BUSY is '0', the field is reliable.</description>
26415              <bitRange>[8:0]</bitRange>
26416              <access>read-only</access>
26417            </field>
26418            <field>
26419              <name>CURR_WR_ADDR</name>
26420              <description>I2C/SPI write current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximum memory buffer address).
26421
26422The field is used to determine how many bytes have been written (# bytes = CURR_WR_ADDR - CMD_RESP_CTRL.BASE_WR_ADDR).
26423
26424This field is reliable during when there is no bus transfer. This field is potentially unreliable when there is a bus transfer bus transfer: when CMD_RESP_EC_BUSY is '0', the field is reliable.</description>
26425              <bitRange>[24:16]</bitRange>
26426              <access>read-only</access>
26427            </field>
26428            <field>
26429              <name>CMD_RESP_EC_BUS_BUSY</name>
26430              <description>Indicates whether there is an ongoing bus transfer to the IP.
26431'0': no ongoing bus transfer.
26432'1': ongoing bus transfer.
26433
26434For SPI, the field is '1' when the slave is selected.
26435
26436For I2C, the field is set to '1' at a I2C START/RESTART. In case of an address match, the  field is set to '0' on a I2C STOP. In case of NO address match, the field is set to '0' after the failing address match.</description>
26437              <bitRange>[30:30]</bitRange>
26438              <access>read-only</access>
26439            </field>
26440            <field>
26441              <name>CMD_RESP_EC_BUSY</name>
26442              <description>Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:
26443- When there is no ongoing bus transfer, CMD_RESP_EC_BUSY is '0' (reliable).
26444- When there is a ongoing bus transfer, CMD_RESP_EC_BUSY is '0' (reliable), when the CURR_RD_ADDR and CURR_WR_ADDR are not being updated by the HW.
26445- When there is a ongoing bus transfer, CMD_RESP_EC_BUSY is '1' (not reliable), when the CURR_RD_ADDR or CURR_WR_ADDR are being updated by the HW.
26446   Note that this update lasts one I2C clock cycle, or two SPI clock cycles.</description>
26447              <bitRange>[31:31]</bitRange>
26448              <access>read-only</access>
26449            </field>
26450          </fields>
26451        </register>
26452        <register>
26453          <name>SPI_CTRL</name>
26454          <description>SPI control</description>
26455          <addressOffset>0x20</addressOffset>
26456          <size>32</size>
26457          <access>read-write</access>
26458          <resetValue>0x3000010</resetValue>
26459          <resetMask>0x8F017F3F</resetMask>
26460          <fields>
26461            <field>
26462              <name>SSEL_CONTINUOUS</name>
26463              <description>Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode, both continuous and non-continuous SPI data transfers are supported independent of this field.
26464
26465When continuous transfers are enabled individual data frame transfers are not necessarily separated by slave deselection (as indicated by the level or pulse on the SELECT line): if the TX FIFO has multiple data frames, data frames are send out without slave deselection.
26466
26467When continuous transfers are not enabled individual data frame transfers are always separated by slave deselection: data frames are always separated by slave deselection.</description>
26468              <bitRange>[0:0]</bitRange>
26469              <access>read-write</access>
26470            </field>
26471            <field>
26472              <name>SELECT_PRECEDE</name>
26473              <description>Only used in SPI Texas Instruments' submode.
26474
26475When '1', the data frame start indication is a pulse on the SELECT line that precedes the transfer of the first data frame bit.
26476
26477When '0', the data frame start indication is a pulse on the SELECT line that coincides with the transfer of the first data frame bit.</description>
26478              <bitRange>[1:1]</bitRange>
26479              <access>read-write</access>
26480            </field>
26481            <field>
26482              <name>CPHA</name>
26483              <description>Indicates the clock phase. This field, together with the CPOL field, indicates when MOSI data is driven and MISO data is captured:
26484- Motorola mode 0. CPOL is '0', CPHA is '0': MOSI  is driven on a falling edge of SCLK. MISO is captured on a rising edge of SCLK.
26485- Motorola mode 1. CPOL is '0', CPHA is '1': MOSI  is driven on a rising edge of SCLK. MISO is captured on a falling edge of SCLK.
26486- Motorola mode 2. CPOL is '1', CPHA is '0': MOSI  is driven on a rising edge of SCLK. MISO is captured on a falling edge of SCLK.
26487- Motorola mode 3. CPOL is '1', CPHA is '1': MOSI  is driven on a falling edge of SCLK. MISO is captured on a rising edge of SCLK.
26488
26489In SPI Motorola submode, all four CPOL/CPHA modes are valid.
26490in SPI NS submode, only CPOL=0 CPHA=0 mode is valid.
26491in SPI TI submode, only CPOL=0 CPHA=1 mode is valid.</description>
26492              <bitRange>[2:2]</bitRange>
26493              <access>read-write</access>
26494            </field>
26495            <field>
26496              <name>CPOL</name>
26497              <description>Indicates the clock polarity. This field, together with the CPHA field, indicates when MOSI data is driven and MISO data is captured:
26498- CPOL is '0': SCLK is '0' when not transmitting data.
26499- CPOL is '1': SCLK is '1' when not transmitting data.</description>
26500              <bitRange>[3:3]</bitRange>
26501              <access>read-write</access>
26502            </field>
26503            <field>
26504              <name>LATE_SAMPLE</name>
26505              <description>Changes the SCLK edge on which MISO is captured in master mode, or MOSI is captured in slave mode.
26506
26507When '0', the default applies,
26508for Motorola as determined by CPOL and CPHA,
26509for Texas Instruments on the falling edge of SCLK(CPOL is '0' and CPHA is '1'),
26510for National Semiconductors on the rising edge of SCLK(CPOL is '0' and CPHA is '0').
26511
26512When '1', the alternate clock edge is used (which comes half a SPI SCLK period later).
26513for master, applicable to all Motorola, TI and National Semiconductors flavors, and CPOL/CPHA timing mdoes.
26514for slave, applicable to Motorola flavor only, and CPHA=0 timing modes only, and internally-clocked mode only.
26515
26516Late sampling addresses the round trip delay associated with transmitting SCLK from the master to the slave and transmitting MISO from the slave to the master.</description>
26517              <bitRange>[4:4]</bitRange>
26518              <access>read-write</access>
26519            </field>
26520            <field>
26521              <name>SCLK_CONTINUOUS</name>
26522              <description>Only applicable in master mode.
26523'0': SCLK is generated, when the SPI master is enabled and data is transmitted.
26524'1': SCLK is generated, when the SPI master is enabled. This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality.</description>
26525              <bitRange>[5:5]</bitRange>
26526              <access>read-write</access>
26527            </field>
26528            <field>
26529              <name>SSEL_POLARITY0</name>
26530              <description>Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:
26531'0': slave select is low/'0' active.
26532'1': slave select is high/'1' active.
26533For Texas Instruments submode:
26534'0': high/'1' active precede/coincide pulse.
26535'1': low/'0' active precede/coincide pulse.</description>
26536              <bitRange>[8:8]</bitRange>
26537              <access>read-write</access>
26538            </field>
26539            <field>
26540              <name>SSEL_POLARITY1</name>
26541              <description>Slave select polarity.</description>
26542              <bitRange>[9:9]</bitRange>
26543              <access>read-write</access>
26544            </field>
26545            <field>
26546              <name>SSEL_POLARITY2</name>
26547              <description>Slave select polarity.</description>
26548              <bitRange>[10:10]</bitRange>
26549              <access>read-write</access>
26550            </field>
26551            <field>
26552              <name>SSEL_POLARITY3</name>
26553              <description>Slave select polarity.</description>
26554              <bitRange>[11:11]</bitRange>
26555              <access>read-write</access>
26556            </field>
26557            <field>
26558              <name>SSEL_SETUP_DEL</name>
26559              <description>Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MOSI bit).
26560'0': 0.75 SPI clock cycles
26561'1': 1.75 SPI clock cycles
26562Only applies in SPI MOTOROLA submode and when SCLK_CONTINUOUS=0, CTRL.OVS&gt;=3.
26563
26564above are ideal case at SCB block level, and there is inaccuracy of one clk_scb cycle.</description>
26565              <bitRange>[12:12]</bitRange>
26566              <access>read-write</access>
26567            </field>
26568            <field>
26569              <name>SSEL_HOLD_DEL</name>
26570              <description>Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MOSI bit, and SELECT deactivation).
26571'0': 0.75 SPI clock cycles
26572'1': 1.75 SPI clock cycles
26573Only applies in SPI MOTOROLA submode and when SCLK_CONTINUOUS=0, CTRL.OVS&gt;=3.
26574
26575above are ideal case at SCB block level, and there is inaccuracy of one clk_scb cycle.</description>
26576              <bitRange>[13:13]</bitRange>
26577              <access>read-write</access>
26578            </field>
26579            <field>
26580              <name>SSEL_INTER_FRAME_DEL</name>
26581              <description>Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation).
26582'0': 1.5 SPI clock cycles
26583'1': 2.5 SPI clock cycles
26584Only applies in SPI MOTOROLA submode and when SPI_CTRL.SSEL_CONTINUOUS=0, CTRL.OVS&gt;=3.
26585
26586above are ideal case at SCB block level, and there is inaccuracy of one clk_scb cycle.</description>
26587              <bitRange>[14:14]</bitRange>
26588              <access>read-write</access>
26589            </field>
26590            <field>
26591              <name>LOOPBACK</name>
26592              <description>Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode.
26593'0': the SPI master MISO line 'spi_miso_in' is connected to the SPI MISO pin.
26594'1': the SPI master MISO line 'spi_miso_in' is connected to the SPI master MOSI line 'spi_mosi_out'. In other words, in loopback mode the SPI master receives on MISO what it transmits on MOSI.</description>
26595              <bitRange>[16:16]</bitRange>
26596              <access>read-write</access>
26597            </field>
26598            <field>
26599              <name>MODE</name>
26600              <description>N/A</description>
26601              <bitRange>[25:24]</bitRange>
26602              <access>read-write</access>
26603              <enumeratedValues>
26604                <enumeratedValue>
26605                  <name>SPI_MOTOROLA</name>
26606                  <description>SPI Motorola submode. In master mode, when not transmitting data (SELECT is inactive), SCLK is stable at CPOL. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive.</description>
26607                  <value>0</value>
26608                </enumeratedValue>
26609                <enumeratedValue>
26610                  <name>SPI_TI</name>
26611                  <description>SPI Texas Instruments submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive; i.e. no pulse is generated.</description>
26612                  <value>1</value>
26613                </enumeratedValue>
26614                <enumeratedValue>
26615                  <name>SPI_NS</name>
26616                  <description>SPI National Semiconductors submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive.</description>
26617                  <value>2</value>
26618                </enumeratedValue>
26619              </enumeratedValues>
26620            </field>
26621            <field>
26622              <name>SSEL</name>
26623              <description>Selects one of the four incoming/outgoing SPI slave select signals:
26624- 0: Slave 0, SSEL[0].
26625- 1: Slave 1, SSEL[1].
26626- 2: Slave 2, SSEL[2].
26627- 3: Slave 3, SSEL[3].
26628The IP should be disabled when changes are made to this field.</description>
26629              <bitRange>[27:26]</bitRange>
26630              <access>read-write</access>
26631            </field>
26632            <field>
26633              <name>MASTER_MODE</name>
26634              <description>Master ('1') or slave ('0') mode. In master mode, transmission will commence on availability of data frames in the TX FIFO. In slave mode, when selected and there is no data frame in the TX FIFO, the slave will transmit all '1's. In both master and slave modes, received data frames will be lost if the RX FIFO is full.</description>
26635              <bitRange>[31:31]</bitRange>
26636              <access>read-write</access>
26637            </field>
26638          </fields>
26639        </register>
26640        <register>
26641          <name>SPI_STATUS</name>
26642          <description>SPI status</description>
26643          <addressOffset>0x24</addressOffset>
26644          <size>32</size>
26645          <access>read-only</access>
26646          <resetValue>0x0</resetValue>
26647          <resetMask>0x0</resetMask>
26648          <fields>
26649            <field>
26650              <name>BUS_BUSY</name>
26651              <description>SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes, the busy bit is '1', when the slave selection is activated. For TI submode, the busy bit is '1' from the time the preceding/coinciding slave select is activated for the first transmitted data frame, till the last MOSI/MISO bit of the last data frame is transmitted.</description>
26652              <bitRange>[0:0]</bitRange>
26653              <access>read-only</access>
26654            </field>
26655            <field>
26656              <name>SPI_EC_BUSY</name>
26657              <description>Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are reliable.</description>
26658              <bitRange>[1:1]</bitRange>
26659              <access>read-only</access>
26660            </field>
26661            <field>
26662              <name>CURR_EZ_ADDR</name>
26663              <description>SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1'), as clock domain synchronization is not performed in the design.</description>
26664              <bitRange>[15:8]</bitRange>
26665              <access>read-only</access>
26666            </field>
26667            <field>
26668              <name>BASE_EZ_ADDR</name>
26669              <description>SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design.</description>
26670              <bitRange>[23:16]</bitRange>
26671              <access>read-only</access>
26672            </field>
26673          </fields>
26674        </register>
26675        <register>
26676          <name>SPI_TX_CTRL</name>
26677          <description>SPI transmitter control</description>
26678          <addressOffset>0x28</addressOffset>
26679          <size>32</size>
26680          <access>read-write</access>
26681          <resetValue>0x0</resetValue>
26682          <resetMask>0x10030</resetMask>
26683          <fields>
26684            <field>
26685              <name>PARITY</name>
26686              <description>Parity bit. When '0', the transmitter generates an even parity. When '1', the transmitter generates an odd parity.</description>
26687              <bitRange>[4:4]</bitRange>
26688              <access>read-write</access>
26689            </field>
26690            <field>
26691              <name>PARITY_ENABLED</name>
26692              <description>Parity generation enabled ('1') or not ('0').</description>
26693              <bitRange>[5:5]</bitRange>
26694              <access>read-write</access>
26695            </field>
26696            <field>
26697              <name>MOSI_IDLE_HIGH</name>
26698              <description>SPI master MOSI output level when SELECT output inactive,
266990: retain the level of last data bit
267001: change to high,
26701   (MOSI level is high, before the first data bit time, and after data bit time, defined SSEL/SCLK driving edge with CPOL/CPHA)</description>
26702              <bitRange>[16:16]</bitRange>
26703              <access>read-write</access>
26704            </field>
26705          </fields>
26706        </register>
26707        <register>
26708          <name>SPI_RX_CTRL</name>
26709          <description>SPI receiver control</description>
26710          <addressOffset>0x2C</addressOffset>
26711          <size>32</size>
26712          <access>read-write</access>
26713          <resetValue>0x0</resetValue>
26714          <resetMask>0x130</resetMask>
26715          <fields>
26716            <field>
26717              <name>PARITY</name>
26718              <description>Parity bit. When '0', the receiver expects an even parity. When '1', the receiver expects an odd parity.</description>
26719              <bitRange>[4:4]</bitRange>
26720              <access>read-write</access>
26721            </field>
26722            <field>
26723              <name>PARITY_ENABLED</name>
26724              <description>Parity checking enabled ('1') or not ('0').</description>
26725              <bitRange>[5:5]</bitRange>
26726              <access>read-write</access>
26727            </field>
26728            <field>
26729              <name>DROP_ON_PARITY_ERROR</name>
26730              <description>Behavior when a parity check fails. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost.</description>
26731              <bitRange>[8:8]</bitRange>
26732              <access>read-write</access>
26733            </field>
26734          </fields>
26735        </register>
26736        <register>
26737          <name>UART_CTRL</name>
26738          <description>UART control</description>
26739          <addressOffset>0x40</addressOffset>
26740          <size>32</size>
26741          <access>read-write</access>
26742          <resetValue>0x3000000</resetValue>
26743          <resetMask>0x3010000</resetMask>
26744          <fields>
26745            <field>
26746              <name>LOOPBACK</name>
26747              <description>Local loopback control (does NOT affect the information on the pins). When '0', the transmitter TX line 'uart_tx_out' is connected to the TX pin and the receiver RX line 'uart_rx_in' is connected to the RX pin. When '1', the transmitter TX line 'uart_tx_out' is connected to the receiver RX line 'uart_rx_in'. A similar connections scheme is followed for 'uart_rts_out' and 'uart_cts_in'.
26748
26749This allows a SCB UART transmitter to communicate with its receiver counterpart.</description>
26750              <bitRange>[16:16]</bitRange>
26751              <access>read-write</access>
26752            </field>
26753            <field>
26754              <name>MODE</name>
26755              <description>N/A</description>
26756              <bitRange>[25:24]</bitRange>
26757              <access>read-write</access>
26758              <enumeratedValues>
26759                <enumeratedValue>
26760                  <name>UART_STD</name>
26761                  <description>Standard UART submode.</description>
26762                  <value>0</value>
26763                </enumeratedValue>
26764                <enumeratedValue>
26765                  <name>UART_SMARTCARD</name>
26766                  <description>SmartCard (ISO7816) submode. Support for negative acknowledgement (NACK) on the receiver side and retransmission on the transmitter side.</description>
26767                  <value>1</value>
26768                </enumeratedValue>
26769                <enumeratedValue>
26770                  <name>UART_IRDA</name>
26771                  <description>Infrared Data Association (IrDA) submode. Return to Zero modulation scheme.</description>
26772                  <value>2</value>
26773                </enumeratedValue>
26774              </enumeratedValues>
26775            </field>
26776          </fields>
26777        </register>
26778        <register>
26779          <name>UART_TX_CTRL</name>
26780          <description>UART transmitter control</description>
26781          <addressOffset>0x44</addressOffset>
26782          <size>32</size>
26783          <access>read-write</access>
26784          <resetValue>0x2</resetValue>
26785          <resetMask>0x137</resetMask>
26786          <fields>
26787            <field>
26788              <name>STOP_BITS</name>
26789              <description>Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period.</description>
26790              <bitRange>[2:0]</bitRange>
26791              <access>read-write</access>
26792            </field>
26793            <field>
26794              <name>PARITY</name>
26795              <description>Parity bit. When '0', the transmitter generates an even parity. When '1', the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes.</description>
26796              <bitRange>[4:4]</bitRange>
26797              <access>read-write</access>
26798            </field>
26799            <field>
26800              <name>PARITY_ENABLED</name>
26801              <description>Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode, parity generation is always enabled through hardware. In IrDA submode, parity generation is always disabled through hardware</description>
26802              <bitRange>[5:5]</bitRange>
26803              <access>read-write</access>
26804            </field>
26805            <field>
26806              <name>RETRY_ON_NACK</name>
26807              <description>When '1', a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode.</description>
26808              <bitRange>[8:8]</bitRange>
26809              <access>read-write</access>
26810            </field>
26811          </fields>
26812        </register>
26813        <register>
26814          <name>UART_RX_CTRL</name>
26815          <description>UART receiver control</description>
26816          <addressOffset>0x48</addressOffset>
26817          <size>32</size>
26818          <access>read-write</access>
26819          <resetValue>0xA0002</resetValue>
26820          <resetMask>0x10F3777</resetMask>
26821          <fields>
26822            <field>
26823              <name>STOP_BITS</name>
26824              <description>Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period.
26825
26826Note that in case of a stop bits error, the successive data frames may get lost as the receiver needs to resynchronize its start bit detection. The amount of lost data frames depends on both the amount of stop bits, the idle ('1') time between data frames and the data frame value.</description>
26827              <bitRange>[2:0]</bitRange>
26828              <access>read-write</access>
26829            </field>
26830            <field>
26831              <name>PARITY</name>
26832              <description>Parity bit. When '0', the receiver expects an even parity. When '1', the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes.</description>
26833              <bitRange>[4:4]</bitRange>
26834              <access>read-write</access>
26835            </field>
26836            <field>
26837              <name>PARITY_ENABLED</name>
26838              <description>Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode, parity checking is always enabled through hardware. In IrDA submode, parity checking is always disabled through hardware.</description>
26839              <bitRange>[5:5]</bitRange>
26840              <access>read-write</access>
26841            </field>
26842            <field>
26843              <name>POLARITY</name>
26844              <description>Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality.</description>
26845              <bitRange>[6:6]</bitRange>
26846              <access>read-write</access>
26847            </field>
26848            <field>
26849              <name>DROP_ON_PARITY_ERROR</name>
26850              <description>Behavior when a parity check fails. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames may be dropped with this field).</description>
26851              <bitRange>[8:8]</bitRange>
26852              <access>read-write</access>
26853            </field>
26854            <field>
26855              <name>DROP_ON_FRAME_ERROR</name>
26856              <description>Behavior when an error is detected in a start or stop period. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost.</description>
26857              <bitRange>[9:9]</bitRange>
26858              <access>read-write</access>
26859            </field>
26860            <field>
26861              <name>MP_MODE</name>
26862              <description>Multi-processor mode. When '1', multi-processor mode is enabled. In this mode, RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode, the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is '0'). A received address is matched with RX_MATCH.DATA and RX_MATCH.MASK. In the case of a match, subsequent received data are sent to the RX FIFO. In the case of NO match, subsequent received data are dropped.</description>
26863              <bitRange>[10:10]</bitRange>
26864              <access>read-write</access>
26865            </field>
26866            <field>
26867              <name>LIN_MODE</name>
26868              <description>Only applicable in standard UART submode. When '1', the receiver performs break detection and baud rate detection on the incoming data. First, break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies the minimum required amount of bit periods. Successful break detection sets the INTR_RX.BREAK_DETECT interrupt cause to '1'. Second, baud rate detection counts the amount of peripheral clock periods that are use to receive the synchronization byte (0x55; least significant bit first). The count is available through UART_RX_STATUS.BR_COUNTER. Successful baud rate detection sets the INTR_RX.BAUD_DETECT interrupt cause to '1' (BR_COUNTER is reliable). This functionality is used to synchronize/refine the receiver clock to the transmitter clock. The receiver software can use the BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte.</description>
26869              <bitRange>[12:12]</bitRange>
26870              <access>read-write</access>
26871            </field>
26872            <field>
26873              <name>SKIP_START</name>
26874              <description>Only applicable in standard UART submode. When '1', the receiver skips start bit detection for the first received data frame. Instead, it synchronizes on the first received data frame bit, which should be a '1'. This functionality is intended for wake up from DeepSleep when receiving a data frame. The transition from idle ('1') to START ('0') on the RX line is used to wake up the CPU. The transition detection (and the associated wake up functionality) is performed by the GPIO2 IP. The woken up CPU will enable the SCB's UART receiver functionality. Once enabled, it is assumed that the START bit is ongoing (the CPU wakeup and SCB enable time should be less than the START bit period). The SCB will synchronize to a '0' to '1' transition, which indicates the first data frame bit is received (first data frame bit should be '1'). After synchronization to the first data frame bit, the SCB will resume normal UART functionality: subsequent data frames will be synchronized on the receipt of a START bit.</description>
26875              <bitRange>[13:13]</bitRange>
26876              <access>read-write</access>
26877            </field>
26878            <field>
26879              <name>BREAK_WIDTH</name>
26880              <description>Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once, the break is detected, the INTR_RX.BREAK_DETECT bit is set to '1'. Note that break detection precedes baud rate detection, which is used to synchronize/refine the receiver clock to the transmitter clock. As a result, break detection operates with an unsynchronized/unrefined receiver clock. Therefore, the receiver's definition of a bit period is imprecise and the setting of this field should take this imprecision into account. The LIN standard also accounts for this imprecision: a LIN start bit followed by 8 data bits allows for up to 9 consecutive '0' bit periods during regular transmission, whereas the LIN break detection should be at least 13 consecutive '0' bit periods. This provides for a margin of 4 bit periods. Therefore, the default value of this field is set to 10, representing a minimal break field with of 10+1 = 11 bit periods; a value in between the 9 consecutive bit periods of a regular transmission and the 13 consecutive bit periods of a break field. This provides for slight imprecisions of the receiver clock wrt. the transmitter clock. There should not be a need to program this field to any value other than its default value.</description>
26881              <bitRange>[19:16]</bitRange>
26882              <access>read-write</access>
26883            </field>
26884            <field>
26885              <name>BREAK_LEVEL</name>
26886              <description>0: low level pulse detection, like Break field in LIN protocol
268871: high level pulse detection, like IFS field in CXPI protocol, or idle line state in UART</description>
26888              <bitRange>[24:24]</bitRange>
26889              <access>read-write</access>
26890            </field>
26891          </fields>
26892        </register>
26893        <register>
26894          <name>UART_RX_STATUS</name>
26895          <description>UART receiver status</description>
26896          <addressOffset>0x4C</addressOffset>
26897          <size>32</size>
26898          <access>read-only</access>
26899          <resetValue>0x0</resetValue>
26900          <resetMask>0x0</resetMask>
26901          <fields>
26902            <field>
26903              <name>BR_COUNTER</name>
26904              <description>Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of peripheral clock periods that constitute a bit period. This field has valid data when INTR_RX.BAUD_DETECT is set to '1'.</description>
26905              <bitRange>[11:0]</bitRange>
26906              <access>read-only</access>
26907            </field>
26908          </fields>
26909        </register>
26910        <register>
26911          <name>UART_FLOW_CTRL</name>
26912          <description>UART flow control</description>
26913          <addressOffset>0x50</addressOffset>
26914          <size>32</size>
26915          <access>read-write</access>
26916          <resetValue>0x0</resetValue>
26917          <resetMask>0x30100FF</resetMask>
26918          <fields>
26919            <field>
26920              <name>TRIGGER_LEVEL</name>
26921              <description>Trigger level. When the receiver FIFO has less entries than the amount of this field, a Ready To Send (RTS) output signal 'uart_rts_out' is activated. By setting this field to '0', flow control is effectively SW disabled (may be useful for debug purposes).</description>
26922              <bitRange>[7:0]</bitRange>
26923              <access>read-write</access>
26924            </field>
26925            <field>
26926              <name>RTS_POLARITY</name>
26927              <description>Polarity of the RTS output signal 'uart_rts_out':
26928'0': RTS is low/'0' active; 'uart_rts_out' is '0' when active and 'uart_rts_out' is '1' when inactive.
26929'1': RTS is high/'1' active; 'uart_rts_out' is '1' when active and 'uart_rts_out' is '0' when inactive.
26930
26931During IP reset (Hibernate system power mode), 'uart_rts_out' is '1'. This represents an inactive state assuming a low/'0' active polarity.</description>
26932              <bitRange>[16:16]</bitRange>
26933              <access>read-write</access>
26934            </field>
26935            <field>
26936              <name>CTS_POLARITY</name>
26937              <description>Polarity of the CTS input signal 'uart_cts_in':
26938'0': CTS is low/'0' active; 'uart_cts_in' is '0' when active and 'uart_cts_in' is '1' when inactive.
26939'1': CTS is high/'1' active; 'uart_cts_in' is '1' when active and 'uart_cts_in' is '0' when inactive.</description>
26940              <bitRange>[24:24]</bitRange>
26941              <access>read-write</access>
26942            </field>
26943            <field>
26944              <name>CTS_ENABLED</name>
26945              <description>Enable use of CTS input signal 'uart_cts_in' by the UART transmitter:
26946'0': Disabled. The UART transmitter ignores 'uart_cts_in', and transmits when a data frame is available for transmission in the TX FIFO or the TX shift register.
26947'1': Enabled. The UART transmitter uses 'uart_cts_in' to qualify the transmission of data. It transmits when 'uart_cts_in' is active and a data frame is available for transmission in the TX FIFO or the TX shift register.
26948
26949If UART_CTRL.LOOPBACK is '1', 'uart_cts_in' is connected to 'uart_rts_out' in the IP (both signals are subjected to signal polarity changes as indicated by RTS_POLARITY and CTS_POLARITY).</description>
26950              <bitRange>[25:25]</bitRange>
26951              <access>read-write</access>
26952            </field>
26953          </fields>
26954        </register>
26955        <register>
26956          <name>I2C_CTRL</name>
26957          <description>I2C control</description>
26958          <addressOffset>0x60</addressOffset>
26959          <size>32</size>
26960          <access>read-write</access>
26961          <resetValue>0xFB88</resetValue>
26962          <resetMask>0xC001FBFF</resetMask>
26963          <fields>
26964            <field>
26965              <name>HIGH_PHASE_OVS</name>
26966              <description>Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. The valid range is [5, 15] with input signal median filtering and [4, 15] without input signal median filtering.
26967
26968The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the IP clock wrt. the regular interface (IF) high time to guarantee functional correct behavior. With input signal median filtering, the IF high time should be &gt;= 6 IP clock cycles and &lt;= 16 IP clock cycles. Without input signal median filtering, the IF high time should be &gt;= 5 IP clock cycles and &lt;= 16 IP clock cycles.</description>
26969              <bitRange>[3:0]</bitRange>
26970              <access>read-write</access>
26971            </field>
26972            <field>
26973              <name>LOW_PHASE_OVS</name>
26974              <description>Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period. The valid range is [7, 15] with input signal median filtering and [6, 15] without input signal median filtering.
26975
26976The field is mainly used in master mode. In slave mode, there is a frequency requirement for the IP clock wrt. the regular (no stretching) interface (IF) low time to guarantee functional correct behavior. With input signal median filtering, the IF low time should be &gt;= 8 IP clock cycles and &lt;= 16 IP clock cycles. Without input signal median filtering, the IF low time should be &gt;= 7 IP clock cycles and &lt;= 16 IP clock cycles.
26977
26978in slave mode, this field is used to define number of clk_scb cycles for tSU-DAT timing (from ACK/NACK/data ready, to SCL rising edge (released from I2C slave clock stretching))</description>
26979              <bitRange>[7:4]</bitRange>
26980              <access>read-write</access>
26981            </field>
26982            <field>
26983              <name>M_READY_DATA_ACK</name>
26984              <description>When '1', a received data element by the master is immediately ACK'd when the receiver FIFO is not full.</description>
26985              <bitRange>[8:8]</bitRange>
26986              <access>read-write</access>
26987            </field>
26988            <field>
26989              <name>M_NOT_READY_DATA_NACK</name>
26990              <description>for I2C master, the NACKed byte should be properly received. it write  the data byte, before ACK/NACK decision.
26991
26992When '1',
26993if a received data element byte is written, and the receiver FIFO become full, the master send out NACK .
26994if the reciever FIFO is full (the received data byte cannot be written), it stretch SCL(extend SCL low phase) until the receiver FIFO changes to not full, to write the last byte, then send out NACK.
26995
26996When '0', clock stretching is used instead (till the receiver FIFO is no longer full).</description>
26997              <bitRange>[9:9]</bitRange>
26998              <access>read-write</access>
26999            </field>
27000            <field>
27001              <name>S_GENERAL_IGNORE</name>
27002              <description>When '1', a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure.</description>
27003              <bitRange>[11:11]</bitRange>
27004              <access>read-write</access>
27005            </field>
27006            <field>
27007              <name>S_READY_ADDR_ACK</name>
27008              <description>When '1', a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode, this field should be set to '1'.</description>
27009              <bitRange>[12:12]</bitRange>
27010              <access>read-write</access>
27011            </field>
27012            <field>
27013              <name>S_READY_DATA_ACK</name>
27014              <description>When '1', a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode, this field should be set to '1'.</description>
27015              <bitRange>[13:13]</bitRange>
27016              <access>read-write</access>
27017            </field>
27018            <field>
27019              <name>S_NOT_READY_ADDR_NACK</name>
27020              <description>For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when:
27021- EC_AM is '0', EC_OP is '0' and non EZ mode.
27022Functionality is as follows:
27023- 1: a received (matching) slave address is immediately NACK'd when the receiver FIFO is full.
27024- 0: clock stretching is performed (till the receiver FIFO is no longer full).
27025
27026For externally clocked logic (EC_AM is '1') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when (NOT used when EC_AM is '1' and EC_OP is '1' and address match and EZ mode):
27027- EC_AM is '1' and EC_OP is '0'.
27028- EC_AM is '1' and general call address match.
27029- EC_AM is '1' and non EZ mode.
27030Functionality is as follows:
27031- 1: a received (matching or general) slave address is always immediately NACK'd. There are two possibilities: 1). the internally clocked logic is enabled (we are in Active system power mode) and it handles the rest of the current transfer. In this case the I2C master will not observe the NACK. 2). the internally clocked logic is not enabled (we are in DeepSleep system power mode). In this case the I2C master will observe the NACK and may retry the transfer in the future (which gives the internally clocked logic the time to wake up from DeepSleep system power mode).
27032- 0: clock stretching is performed (till the internally clocked logic takes over). The internally clocked logic will handle the ongoing transfer as soon as it is enabled.</description>
27033              <bitRange>[14:14]</bitRange>
27034              <access>read-write</access>
27035            </field>
27036            <field>
27037              <name>S_NOT_READY_DATA_NACK</name>
27038              <description>For internally clocked logic only. Only used when:
27039- non EZ mode.
27040Functionality is as follows:
27041- 1: a received data element byte the slave is immediately NACK'd when the receiver FIFO is full.
27042- 0: clock stretching is performed (till the receiver FIFO is no longer full).</description>
27043              <bitRange>[15:15]</bitRange>
27044              <access>read-write</access>
27045            </field>
27046            <field>
27047              <name>LOOPBACK</name>
27048              <description>Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0', the I2C SCL and SDA lines are connected to the I2C SCL and SDA pins. When '1', I2C SCL and SDA lines are routed internally in the peripheral, and as a result unaffected by other I2C devices. This allows a SCB I2C peripheral to address itself.</description>
27049              <bitRange>[16:16]</bitRange>
27050              <access>read-write</access>
27051            </field>
27052            <field>
27053              <name>SLAVE_MODE</name>
27054              <description>Slave mode enabled ('1') or not ('0').</description>
27055              <bitRange>[30:30]</bitRange>
27056              <access>read-write</access>
27057            </field>
27058            <field>
27059              <name>MASTER_MODE</name>
27060              <description>Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself.</description>
27061              <bitRange>[31:31]</bitRange>
27062              <access>read-write</access>
27063            </field>
27064          </fields>
27065        </register>
27066        <register>
27067          <name>I2C_STATUS</name>
27068          <description>I2C status</description>
27069          <addressOffset>0x64</addressOffset>
27070          <size>32</size>
27071          <access>read-only</access>
27072          <resetValue>0x0</resetValue>
27073          <resetMask>0x1000035</resetMask>
27074          <fields>
27075            <field>
27076              <name>BUS_BUSY</name>
27077              <description>I2C bus is busy. The bus is considered busy ('1'), from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0'), from the time a STOP is detected. If the IP is disabled, BUS_BUSY is '0'. After enabling the IP, it takes time for the BUS_BUSY to detect a busy bus. This time is the maximum high time of the SCL line. For a 100 kHz interface frequency, this maximum high time may last roughly 5 us (half a bit period).
27078
27079For single master systems, BUS_BUSY does not have to be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START (no bus collisions).
27080
27081For multi-master systems, BUS_BUSY can be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START_ON_IDLE (to prevent bus collisions).</description>
27082              <bitRange>[0:0]</bitRange>
27083              <access>read-only</access>
27084            </field>
27085            <field>
27086              <name>I2C_EC_BUSY</name>
27087              <description>Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and CURR_EZ_ADDR are reliable.</description>
27088              <bitRange>[1:1]</bitRange>
27089              <access>read-only</access>
27090            </field>
27091            <field>
27092              <name>I2CS_IC_BUSY</name>
27093              <description>Indicates whether the internally clocked slave logic is being accessed by external I2C master.
27094--set at ADDR_MATCH
27095--clear at START/RESET, STOP detection, or BUS_ERROR
27096This bit can be used by SW to determine whether I2CS_IC is busy before entering DeepSleep.</description>
27097              <bitRange>[2:2]</bitRange>
27098              <access>read-only</access>
27099            </field>
27100            <field>
27101              <name>S_READ</name>
27102              <description>I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START, REPEATED START, STOP or an address, this field is '0''.</description>
27103              <bitRange>[4:4]</bitRange>
27104              <access>read-only</access>
27105            </field>
27106            <field>
27107              <name>M_READ</name>
27108              <description>I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START, REPEATED START, STOP or an address, this field is '0''.</description>
27109              <bitRange>[5:5]</bitRange>
27110              <access>read-only</access>
27111            </field>
27112            <field>
27113              <name>CURR_EZ_ADDR</name>
27114              <description>I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1'), as clock domain synchronization is not performed in the design.</description>
27115              <bitRange>[15:8]</bitRange>
27116              <access>read-only</access>
27117            </field>
27118            <field>
27119              <name>BASE_EZ_ADDR</name>
27120              <description>I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design.</description>
27121              <bitRange>[23:16]</bitRange>
27122              <access>read-only</access>
27123            </field>
27124            <field>
27125              <name>HS_MODE</name>
27126              <description>this is to indicate I2C Hs-mode transfer,
27127it is set, after 'Start, master-code, NACK'' pattern,
27128   for I2CM,    at SCL falling edge, (INTR_M.I2C_HS_ENTER triggers),
27129   for I2CS_IC, at SCL falling edge, (INTR_S.I2C_HS_ENTER triggers),
27130   for I2CS_EC, at SCL rising  edge, after 2-DFF synchronization delay, when CTRL.EC_AM =1, AND CTRL.EC_ACCESS =0,
27131it is cleared when Stop pattern is detected,
27132   for I2CM,    INTR_M.I2C_HS_EXIT triggers,
27133   for I2CS_IC, INTR_S.I2C_HS_EXIT triggers,
27134   for I2CS_EC, there is no respective interrupt.</description>
27135              <bitRange>[24:24]</bitRange>
27136              <access>read-only</access>
27137            </field>
27138          </fields>
27139        </register>
27140        <register>
27141          <name>I2C_M_CMD</name>
27142          <description>I2C master command</description>
27143          <addressOffset>0x68</addressOffset>
27144          <size>32</size>
27145          <access>read-write</access>
27146          <resetValue>0x0</resetValue>
27147          <resetMask>0x1F</resetMask>
27148          <fields>
27149            <field>
27150              <name>M_START</name>
27151              <description>When '1', transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START is transmitted when the master state machine is not in the default state, but is working on an ongoing transaction. The REPEATED START can only be transmitted after a NACK or ACK has been received for a transmitted data element or after a NACK has been transmitted for a received data element. When this action is performed, the hardware sets this field to '0'.</description>
27152              <bitRange>[0:0]</bitRange>
27153              <access>read-write</access>
27154            </field>
27155            <field>
27156              <name>M_START_ON_IDLE</name>
27157              <description>When '1', transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0', note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result, bus idle detection is only functional after at least one I2C bus transfer has been detected on the bus (default/reset value of BUSY is '0') . A START is only transmitted when the master state machine is in the default state. When this action is performed, the hardware sets this field to '0'.</description>
27158              <bitRange>[1:1]</bitRange>
27159              <access>read-write</access>
27160            </field>
27161            <field>
27162              <name>M_ACK</name>
27163              <description>When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'.</description>
27164              <bitRange>[2:2]</bitRange>
27165              <access>read-write</access>
27166            </field>
27167            <field>
27168              <name>M_NACK</name>
27169              <description>for I2C master, the NACKed byte should be properly received. it write  the data byte, before ACK/NACK decision.
27170
27171When '1', attempt to transmit a negative acknowledgement (NACK).
27172if the reciever FIFO is full (the received data byte cannot be written), it stretch SCL(extend SCL low phase) until the receiver FIFO changes to not full, to write the last byte, then send out NACK.
27173
27174When this action is performed, the hardware sets this field to '0'.</description>
27175              <bitRange>[3:3]</bitRange>
27176              <access>read-write</access>
27177            </field>
27178            <field>
27179              <name>M_STOP</name>
27180              <description>When '1', attempt to transmit a STOP. When this action is performed, the hardware sets this field to '0'.
27181 I2C_M_CMD.M_START has a higher priority than this command: in situations where both a STOP and a REPEATED START could be transmitted, M_START takes precedence over M_STOP.</description>
27182              <bitRange>[4:4]</bitRange>
27183              <access>read-write</access>
27184            </field>
27185          </fields>
27186        </register>
27187        <register>
27188          <name>I2C_S_CMD</name>
27189          <description>I2C slave command</description>
27190          <addressOffset>0x6C</addressOffset>
27191          <size>32</size>
27192          <access>read-write</access>
27193          <resetValue>0x0</resetValue>
27194          <resetMask>0x107</resetMask>
27195          <fields>
27196            <field>
27197              <name>S_ACK</name>
27198              <description>When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode).</description>
27199              <bitRange>[0:0]</bitRange>
27200              <access>read-write</access>
27201            </field>
27202            <field>
27203              <name>S_NACK</name>
27204              <description>When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'.  In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher priority than I2C_S_CMD.S_ACK, I2C_CTRL.S_READY_ADDR_ACK or I2C_CTRL.S_READY_DATA_ACK.</description>
27205              <bitRange>[1:1]</bitRange>
27206              <access>read-write</access>
27207            </field>
27208            <field>
27209              <name>S_TX_ONES_ON_EMPTY</name>
27210              <description>When '1', attempt to send ones when TX_FIFO is empty.
27211
27212Once hardware starts to send ones, it will continue send ones until NACK is received, regardless of TX_FIFO status (even if new data is written into TX_FIFO).
27213
27214This bit is used to avoid stretching SCL, which is not expected for some master devices.</description>
27215              <bitRange>[2:2]</bitRange>
27216              <access>read-write</access>
27217            </field>
27218            <field>
27219              <name>S_STRETCH_HS</name>
27220              <description>When '1', attempt to stretch SCL at time t1, SCL falling edge after 'START, Master-code, NACK' pattern is detected.
27221
27222When I2C_CTRL.HS_ENABLED is set, it should be set; after wakeup from DeepSleep power mode, it should also be set.
27223
27224When INTR_S.I2C_HS_ENTER triggers, firmware configure clk_scb to meet I2C Hs-mode timing requirements, then firmware can clear this bit.</description>
27225              <bitRange>[8:8]</bitRange>
27226              <access>read-write</access>
27227            </field>
27228          </fields>
27229        </register>
27230        <register>
27231          <name>I2C_CFG</name>
27232          <description>I2C configuration</description>
27233          <addressOffset>0x70</addressOffset>
27234          <size>32</size>
27235          <access>read-write</access>
27236          <resetValue>0x2A1013</resetValue>
27237          <resetMask>0x303F1313</resetMask>
27238          <fields>
27239            <field>
27240              <name>SDA_IN_FILT_TRIM</name>
27241              <description>Trim bits for 'i2c_sda_in' 50 ns filter.
27242for M0S8 platform, see s8i2cs BROS (001-59539) for more details on the trim bit values.
27243For MXS40 platform, only the Least Significant Bit (LSB) is used, see s40iolib BROS (002-02511) for more details on the trim bit values.</description>
27244              <bitRange>[1:0]</bitRange>
27245              <access>read-write</access>
27246            </field>
27247            <field>
27248              <name>SDA_IN_FILT_SEL</name>
27249              <description>Selection of 'i2c_sda_in' filter delay:
27250'0': 0 ns.
27251'1: 50 ns (filter enabled).</description>
27252              <bitRange>[4:4]</bitRange>
27253              <access>read-write</access>
27254            </field>
27255            <field>
27256              <name>SCL_IN_FILT_TRIM</name>
27257              <description>Trim bits for 'i2c_scl_in' 50 ns filter.
27258for M0S8 platform, see s8i2cs BROS (001-59539) for more details on the trim bit values.
27259For MXS40 platform, only the Least Significant Bit (LSB) is used, see s40iolib BROS (002-02511) for more details on the trim bit values.</description>
27260              <bitRange>[9:8]</bitRange>
27261              <access>read-write</access>
27262            </field>
27263            <field>
27264              <name>SCL_IN_FILT_SEL</name>
27265              <description>Selection of 'i2c_scl_in' filter delay:
27266'0': 0 ns.
27267'1: 50 ns (filter enabled).</description>
27268              <bitRange>[12:12]</bitRange>
27269              <access>read-write</access>
27270            </field>
27271            <field>
27272              <name>SDA_OUT_FILT0_TRIM</name>
27273              <description>Trim bits for 'i2c_sda_out' 50 ns filter 0.
27274for M0S8 platform, see s8i2cs BROS (001-59539) for more details on the trim bit values.
27275For MXS40 platform, only the Least Significant Bit (LSB) is used, see s40iolib BROS (002-02511) for more details on the trim bit values.</description>
27276              <bitRange>[17:16]</bitRange>
27277              <access>read-write</access>
27278            </field>
27279            <field>
27280              <name>SDA_OUT_FILT1_TRIM</name>
27281              <description>Trim bits for 'i2c_sda_out' 50 ns filter 1.
27282for M0S8 platform, see s8i2cs BROS (001-59539) for more details on the trim bit values.
27283For MXS40 platform, only the Least Significant Bit (LSB) is used, see s40iolib BROS (002-02511) for more details on the trim bit values.</description>
27284              <bitRange>[19:18]</bitRange>
27285              <access>read-write</access>
27286            </field>
27287            <field>
27288              <name>SDA_OUT_FILT2_TRIM</name>
27289              <description>Trim bits for 'i2c_sda_out' 50 ns filter 2.
27290for M0S8 platform, see s8i2cs BROS (001-59539) for more details on the trim bit values.
27291For MXS40 platform, only the Least Significant Bit (LSB) is used, see s40iolib BROS (002-02511) for more details on the trim bit values.</description>
27292              <bitRange>[21:20]</bitRange>
27293              <access>read-write</access>
27294            </field>
27295            <field>
27296              <name>SDA_OUT_FILT_SEL</name>
27297              <description>Selection of cumulative 'i2c_sda_out' filter delay:
27298'0': 0 ns.
27299'1': 50 ns (filter 0 enabled).
27300'2': 100 ns (filters 0 and 1 enabled).
27301'3': 150 ns (filters 0, 1 and 2 enabled).</description>
27302              <bitRange>[29:28]</bitRange>
27303              <access>read-write</access>
27304            </field>
27305          </fields>
27306        </register>
27307        <register>
27308          <name>I2C_STRETCH_CTRL</name>
27309          <description>I2C stretch control</description>
27310          <addressOffset>0x74</addressOffset>
27311          <size>32</size>
27312          <access>read-write</access>
27313          <resetValue>0x0</resetValue>
27314          <resetMask>0xF</resetMask>
27315          <fields>
27316            <field>
27317              <name>STRETCH_THRESHOLD</name>
27318              <description>stretch threthold.
27319Typically it is the SCL turaound delay (including IO cell delay, SCL rise time, analog filter delay), in number of clk_scb cycles.
27320
27321When STRETCH_COUNT is higher than this STRETCH_THRESHOLD, STRETCH_DETECTED will be set.
27322
27323STRETCH_DETECTED should be less than 'HOVS-2', HOVS means I2C_CTRL.HIGH_PHASE_OVS, or I2C_CTRL_HS.HOVS_HS.</description>
27324              <bitRange>[3:0]</bitRange>
27325              <access>read-write</access>
27326            </field>
27327          </fields>
27328        </register>
27329        <register>
27330          <name>I2C_STRETCH_STATUS</name>
27331          <description>I2C stretch status</description>
27332          <addressOffset>0x78</addressOffset>
27333          <size>32</size>
27334          <access>read-only</access>
27335          <resetValue>0x0</resetValue>
27336          <resetMask>0x13F</resetMask>
27337          <fields>
27338            <field>
27339              <name>STRETCH_COUNT</name>
27340              <description>stretch count.
27341Started when I2C device start to drive high phase on internal SCL output signal, stalled when it detected high level on SCL input signal.</description>
27342              <bitRange>[3:0]</bitRange>
27343              <access>read-only</access>
27344            </field>
27345            <field>
27346              <name>STRETCH_DETECTED</name>
27347              <description>stretch detected.
27348Set when I2C rising edge comes later than expected (suppressed by another master or slave), and STRETCH_COUNT is higher than STRETCH_THRESHOLD.</description>
27349              <bitRange>[4:4]</bitRange>
27350              <access>read-only</access>
27351            </field>
27352            <field>
27353              <name>SYNC_DETECTED</name>
27354              <description>synchronization detected.
27355Set when I2C falling edge comes in earler than expected (suppressed by another I2C master during synchronization).</description>
27356              <bitRange>[5:5]</bitRange>
27357              <access>read-only</access>
27358            </field>
27359            <field>
27360              <name>STRETCHING</name>
27361              <description>I2C SCL is stretched by this block (DUT),
27362for I2C master, this can happen when  TX FIFO is empty, or RX_FIFO is full, or ACK/NACK is not decided, or RESTART/STOP is not decided.
27363For I2C slave, this can heppend,  TX FIFO is empty, or RX_FIFO is full, or ACK/NACK is not decided.</description>
27364              <bitRange>[8:8]</bitRange>
27365              <access>read-only</access>
27366            </field>
27367          </fields>
27368        </register>
27369        <register>
27370          <name>I2C_CTRL_HS</name>
27371          <description>I2C control for High-Speed mode</description>
27372          <addressOffset>0x80</addressOffset>
27373          <size>32</size>
27374          <access>read-write</access>
27375          <resetValue>0x88</resetValue>
27376          <resetMask>0x800000FF</resetMask>
27377          <fields>
27378            <field>
27379              <name>HOVS_HS</name>
27380              <description>Serial I2C interface high phase oversampling factor for I2C Hs-mode. HOVS_HS + 1 peripheral clock periods constitute the high phase of a bit period.
27381
27382Hardware switch from I2C_CTRL.HIGH_PHASE_OVS to this value automacitcally, at time t1; and switch back time tFS (when STOP  detected).
27383
27384Firmware configure clk_scb frequency properly between t1 and tH.</description>
27385              <bitRange>[3:0]</bitRange>
27386              <access>read-write</access>
27387            </field>
27388            <field>
27389              <name>LOVS_HS</name>
27390              <description>Serial I2C interface low phase oversampling factor for I2C Hs-mode. LOVS_HS + 1 peripheral clock periods constitute the low phase of a bit period.
27391
27392Hardware switch from I2C_CTRL.LOW_PHASE_OVS to this value automacitcally, at time t1; and switch back time tFS (when STOP  detected).
27393
27394Firmware configure clk_scb frequency properly between t1 and tH.</description>
27395              <bitRange>[7:4]</bitRange>
27396              <access>read-write</access>
27397            </field>
27398            <field>
27399              <name>HS_ENABLED</name>
27400              <description>0': I2C Hs-mode is disabled,
27401'1': I2C Hs-mode is enabled,
27402
27403when I2C Hs-mode is disabled and the IP is in I2C slave mode, hardware response to incoming Hs-mode transfers are undefined.
27404
27405When I2C Hs-mode is disabled and the IP is in I2C master mode, firmware should not generate Hs-mode transfers.</description>
27406              <bitRange>[31:31]</bitRange>
27407              <access>read-write</access>
27408            </field>
27409          </fields>
27410        </register>
27411        <register>
27412          <name>TX_CTRL</name>
27413          <description>Transmitter control</description>
27414          <addressOffset>0x200</addressOffset>
27415          <size>32</size>
27416          <access>read-write</access>
27417          <resetValue>0x20107</resetValue>
27418          <resetMask>0x3011F</resetMask>
27419          <fields>
27420            <field>
27421              <name>DATA_WIDTH</name>
27422              <description>Dataframe width, depending on CTRL.MEM_WIDTH.
27423DATA_WIDTH + 1 is the amount of bits in a transmitted data frame.
27424This number does not include start, parity and stop bits.
27425For UART mode, the valid range is [3, 8].
27426For SPI, the valid range is [3, 31].
27427For I2C the only valid value is 7.
27428In EZ mode (for both SPI and I2C), the only valid value is 7.</description>
27429              <bitRange>[4:0]</bitRange>
27430              <access>read-write</access>
27431            </field>
27432            <field>
27433              <name>MSB_FIRST</name>
27434              <description>Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'.</description>
27435              <bitRange>[8:8]</bitRange>
27436              <access>read-write</access>
27437            </field>
27438            <field>
27439              <name>OPEN_DRAIN</name>
27440              <description>Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'.
27441'0': Normal operation mode. Typically, this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by a single IO cell. In this operation mode, for an IO cell 'xxx' that is used as an output, the 'xxx_out_en' output enable signal is typically constant '1' the 'xxx_out' output is the outputted value. In other words, in normal operation mode, the 'xxx_out' output is used to control the IO cell output value: 'xxx_out' is '0' to drive an IO cell output value of '0' and 'xxx_out' is '1' to drive an IO cell output value of '1'.
27442'1': Open drain operation mode. Typically this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by multiple IO cells (possibly on multiple chips). In this operation mode, for and IO cell 'xxx' that is used as an output, the 'xxx_out_en' output controls the outputted value. Typically, open drain operation mode drives low/'0' and the 'xxx_out' output is constant '1'. In other words, in open drain operation mode, the 'xxx_out_en' output is used to control the IO cell output value: in drive low/'0' mode: 'xxx_out_en' is '1' (drive enabled) to drive an IO cell output value of '0' and 'xxx_out_en' is '1' (drive disabled) to not drive an IO cell output value (another IO cell can drive the wire/line or a pull up results in a wire/line value '1').
27443
27444The open drain mode is supported for:
27445- UART mode, 'uart_tx' IO cell.
27446- SPI mode, 'spi_miso' IO cell.
27447
27448this bit is not applicable to I2C mode, 'i2c_scl' and 'i2c_sda' IO cells.</description>
27449              <bitRange>[16:16]</bitRange>
27450              <access>read-write</access>
27451            </field>
27452            <field>
27453              <name>OPEN_DRAIN_SCL</name>
27454              <description>Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'.
27455'0': Normal operation mode. Typically, this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by a single IO cell. In this operation mode, for an IO cell 'xxx' that is used as an output, the 'xxx_out_en' output enable signal is typically constant '1' the 'xxx_out' output is the outputted value. In other words, in normal operation mode, the 'xxx_out' output is used to control the IO cell output value: 'xxx_out' is '0' to drive an IO cell output value of '0' and 'xxx_out' is '1' to drive an IO cell output value of '1'.
27456
27457'1': Open drain operation mode. Typically this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by multiple IO cells (possibly on multiple chips). In this operation mode, for and IO cell 'xxx' that is used as an output, the 'xxx_out_en' output controls the outputted value. Typically, open drain operation mode drives low/'0' and the 'xxx_out' output is constant '1'. In other words, in open drain operation mode, the 'xxx_out_en' output is used to control the IO cell output value: in drive low/'0' mode: 'xxx_out_en' is '1' (drive enabled) to drive an IO cell output value of '0' and 'xxx_out_en' is '1' (drive disabled) to not drive an IO cell output value (another IO cell can drive the wire/line or a pull up results in a wire/line value '1').
27458
27459this bit is applicable to I2C SCL only.
27460I2C SDA always work in open-drain mode.
27461
27462this is not applicable to M0S8, which does not need special control in SCB for open-drain drive mode.</description>
27463              <bitRange>[17:17]</bitRange>
27464              <access>read-write</access>
27465            </field>
27466          </fields>
27467        </register>
27468        <register>
27469          <name>TX_FIFO_CTRL</name>
27470          <description>Transmitter FIFO control</description>
27471          <addressOffset>0x204</addressOffset>
27472          <size>32</size>
27473          <access>read-write</access>
27474          <resetValue>0x0</resetValue>
27475          <resetMask>0x300FF</resetMask>
27476          <fields>
27477            <field>
27478              <name>TRIGGER_LEVEL</name>
27479              <description>Trigger level. When the transmitter FIFO has less entries than the number of this field, a transmitter trigger event INTR_TX.TRIGGER is generated.</description>
27480              <bitRange>[7:0]</bitRange>
27481              <access>read-write</access>
27482            </field>
27483            <field>
27484              <name>CLEAR</name>
27485              <description>When '1', the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period.</description>
27486              <bitRange>[16:16]</bitRange>
27487              <access>read-write</access>
27488            </field>
27489            <field>
27490              <name>FREEZE</name>
27491              <description>When '1', hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer.</description>
27492              <bitRange>[17:17]</bitRange>
27493              <access>read-write</access>
27494            </field>
27495          </fields>
27496        </register>
27497        <register>
27498          <name>TX_FIFO_STATUS</name>
27499          <description>Transmitter FIFO status</description>
27500          <addressOffset>0x208</addressOffset>
27501          <size>32</size>
27502          <access>read-only</access>
27503          <resetValue>0x0</resetValue>
27504          <resetMask>0xFFFF81FF</resetMask>
27505          <fields>
27506            <field>
27507              <name>USED</name>
27508              <description>Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2).</description>
27509              <bitRange>[8:0]</bitRange>
27510              <access>read-only</access>
27511            </field>
27512            <field>
27513              <name>SR_VALID</name>
27514              <description>Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working register and holds the data frame that is currently transmitted (when the protocol state machine is transmitting a data frame) or the data frame that is transmitted next (when the protocol state machine is not transmitting a data frame).</description>
27515              <bitRange>[15:15]</bitRange>
27516              <access>read-only</access>
27517            </field>
27518            <field>
27519              <name>RD_PTR</name>
27520              <description>FIFO read pointer: FIFO location from which a data frame is read by the hardware.</description>
27521              <bitRange>[23:16]</bitRange>
27522              <access>read-only</access>
27523            </field>
27524            <field>
27525              <name>WR_PTR</name>
27526              <description>FIFO write pointer: FIFO location at which a new data frame is written.</description>
27527              <bitRange>[31:24]</bitRange>
27528              <access>read-only</access>
27529            </field>
27530          </fields>
27531        </register>
27532        <register>
27533          <name>TX_FIFO_WR</name>
27534          <description>Transmitter FIFO write</description>
27535          <addressOffset>0x240</addressOffset>
27536          <size>32</size>
27537          <access>write-only</access>
27538          <resetValue>0x0</resetValue>
27539          <resetMask>0xFFFFFFFF</resetMask>
27540          <fields>
27541            <field>
27542              <name>DATA</name>
27543              <description>Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0', only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1', only DATA[15:0] are used.
27544
27545A write to a full TX FIFO sets INTR_TX.OVERFLOW to '1'.</description>
27546              <bitRange>[31:0]</bitRange>
27547              <access>write-only</access>
27548            </field>
27549          </fields>
27550        </register>
27551        <register>
27552          <name>RX_CTRL</name>
27553          <description>Receiver control</description>
27554          <addressOffset>0x300</addressOffset>
27555          <size>32</size>
27556          <access>read-write</access>
27557          <resetValue>0x107</resetValue>
27558          <resetMask>0x31F</resetMask>
27559          <fields>
27560            <field>
27561              <name>DATA_WIDTH</name>
27562              <description>Dataframe width, depending on CTRL.MEM_WIDTH.
27563DATA_WIDTH + 1 is the expected amount of bits in received data frame.
27564This number does not include start, parity and stop bits.
27565For UART mode, the valid range is [3, 8].
27566For SPI, the valid range is [3, 31].
27567For I2C the only valid value is 7.
27568In EZ mode (for both SPI and I2C), the only valid value is 7.</description>
27569              <bitRange>[4:0]</bitRange>
27570              <access>read-write</access>
27571            </field>
27572            <field>
27573              <name>MSB_FIRST</name>
27574              <description>Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'.</description>
27575              <bitRange>[8:8]</bitRange>
27576              <access>read-write</access>
27577            </field>
27578            <field>
27579              <name>MEDIAN</name>
27580              <description>Median filter. When '1', a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However, its requires higher oversampling values. For UART IrDA submode, this field should always be '1'.</description>
27581              <bitRange>[9:9]</bitRange>
27582              <access>read-write</access>
27583            </field>
27584          </fields>
27585        </register>
27586        <register>
27587          <name>RX_FIFO_CTRL</name>
27588          <description>Receiver FIFO control</description>
27589          <addressOffset>0x304</addressOffset>
27590          <size>32</size>
27591          <access>read-write</access>
27592          <resetValue>0x0</resetValue>
27593          <resetMask>0x300FF</resetMask>
27594          <fields>
27595            <field>
27596              <name>TRIGGER_LEVEL</name>
27597              <description>Trigger level. When the receiver FIFO has more entries than the number of this field, a receiver trigger event INTR_RX.TRIGGER is generated.</description>
27598              <bitRange>[7:0]</bitRange>
27599              <access>read-write</access>
27600            </field>
27601            <field>
27602              <name>CLEAR</name>
27603              <description>When '1', the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period.</description>
27604              <bitRange>[16:16]</bitRange>
27605              <access>read-write</access>
27606            </field>
27607            <field>
27608              <name>FREEZE</name>
27609              <description>When '1', hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer.</description>
27610              <bitRange>[17:17]</bitRange>
27611              <access>read-write</access>
27612            </field>
27613          </fields>
27614        </register>
27615        <register>
27616          <name>RX_FIFO_STATUS</name>
27617          <description>Receiver FIFO status</description>
27618          <addressOffset>0x308</addressOffset>
27619          <size>32</size>
27620          <access>read-only</access>
27621          <resetValue>0x0</resetValue>
27622          <resetMask>0xFFFF81FF</resetMask>
27623          <fields>
27624            <field>
27625              <name>USED</name>
27626              <description>Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR  (EZ_DATA_NR/2).</description>
27627              <bitRange>[8:0]</bitRange>
27628              <access>read-only</access>
27629            </field>
27630            <field>
27631              <name>SR_VALID</name>
27632              <description>Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register is a working register and holds the data frame that is currently being received (when the protocol state machine is receiving a data frame).</description>
27633              <bitRange>[15:15]</bitRange>
27634              <access>read-only</access>
27635            </field>
27636            <field>
27637              <name>RD_PTR</name>
27638              <description>FIFO read pointer: FIFO location from which a data frame is read.</description>
27639              <bitRange>[23:16]</bitRange>
27640              <access>read-only</access>
27641            </field>
27642            <field>
27643              <name>WR_PTR</name>
27644              <description>FIFO write pointer: FIFO location at which a new data frame is written by the hardware.</description>
27645              <bitRange>[31:24]</bitRange>
27646              <access>read-only</access>
27647            </field>
27648          </fields>
27649        </register>
27650        <register>
27651          <name>RX_MATCH</name>
27652          <description>Slave address and mask</description>
27653          <addressOffset>0x310</addressOffset>
27654          <size>32</size>
27655          <access>read-write</access>
27656          <resetValue>0x0</resetValue>
27657          <resetMask>0xFF00FF</resetMask>
27658          <fields>
27659            <field>
27660              <name>ADDR</name>
27661              <description>Slave device address.
27662
27663In UART multi-processor mode, all 8 bits are used.
27664
27665In I2C slave mode, only bits 7 down to 1 are used. This reflects the organization of the first transmitted byte in a I2C transfer: the first 7 bits represent the address of the addressed slave, and the last 1 bit is a read/write indicator ('0': write, '1': read).</description>
27666              <bitRange>[7:0]</bitRange>
27667              <access>read-write</access>
27668            </field>
27669            <field>
27670              <name>MASK</name>
27671              <description>Slave device address mask. This field is a mask that specifies which of the ADDR field bits in the ADDR field take part in the matching of the slave address: MATCH = ((ADDR &amp; MASK) == ('slave address' &amp; MASK)).</description>
27672              <bitRange>[23:16]</bitRange>
27673              <access>read-write</access>
27674            </field>
27675          </fields>
27676        </register>
27677        <register>
27678          <name>RX_FIFO_RD</name>
27679          <description>Receiver FIFO read</description>
27680          <addressOffset>0x340</addressOffset>
27681          <size>32</size>
27682          <access>read-only</access>
27683          <resetValue>0x0</resetValue>
27684          <resetMask>0x0</resetMask>
27685          <fields>
27686            <field>
27687              <name>DATA</name>
27688              <description>Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0', only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1', only DATA[15:0] are used.
27689
27690This register has a side effect when read by software: a data frame is removed from the FIFO. This may be undesirable during debug; i.e. a read during debug should NOT have a side effect. To this end, the IP uses the AHB-Lite 'hmaster[3:0]' input signal. When this signal is '1' in the address cycle of a bus transfer, a read transfer will not have a side effect. As a result, a read from this register will not remove a data frame from the FIFO. As a result, a read from this register behaves as a read from the SCB_RX_FIFO_RD_SILENT register.
27691
27692A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'.</description>
27693              <bitRange>[31:0]</bitRange>
27694              <access>read-only</access>
27695            </field>
27696          </fields>
27697        </register>
27698        <register>
27699          <name>RX_FIFO_RD_SILENT</name>
27700          <description>Receiver FIFO read silent</description>
27701          <addressOffset>0x344</addressOffset>
27702          <size>32</size>
27703          <access>read-only</access>
27704          <resetValue>0x0</resetValue>
27705          <resetMask>0x0</resetMask>
27706          <fields>
27707            <field>
27708              <name>DATA</name>
27709              <description>Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0', only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1', only DATA[15:0] are used
27710
27711A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'.</description>
27712              <bitRange>[31:0]</bitRange>
27713              <access>read-only</access>
27714            </field>
27715          </fields>
27716        </register>
27717        <register>
27718          <name>INTR_CAUSE</name>
27719          <description>Active clocked interrupt signal</description>
27720          <addressOffset>0xE00</addressOffset>
27721          <size>32</size>
27722          <access>read-only</access>
27723          <resetValue>0x0</resetValue>
27724          <resetMask>0x3F</resetMask>
27725          <fields>
27726            <field>
27727              <name>M</name>
27728              <description>Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0.</description>
27729              <bitRange>[0:0]</bitRange>
27730              <access>read-only</access>
27731            </field>
27732            <field>
27733              <name>S</name>
27734              <description>Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0.</description>
27735              <bitRange>[1:1]</bitRange>
27736              <access>read-only</access>
27737            </field>
27738            <field>
27739              <name>TX</name>
27740              <description>Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0.</description>
27741              <bitRange>[2:2]</bitRange>
27742              <access>read-only</access>
27743            </field>
27744            <field>
27745              <name>RX</name>
27746              <description>Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0.</description>
27747              <bitRange>[3:3]</bitRange>
27748              <access>read-only</access>
27749            </field>
27750            <field>
27751              <name>I2C_EC</name>
27752              <description>Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0.</description>
27753              <bitRange>[4:4]</bitRange>
27754              <access>read-only</access>
27755            </field>
27756            <field>
27757              <name>SPI_EC</name>
27758              <description>Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0.</description>
27759              <bitRange>[5:5]</bitRange>
27760              <access>read-only</access>
27761            </field>
27762          </fields>
27763        </register>
27764        <register>
27765          <name>INTR_I2C_EC</name>
27766          <description>Externally clocked I2C interrupt request</description>
27767          <addressOffset>0xE80</addressOffset>
27768          <size>32</size>
27769          <access>read-write</access>
27770          <resetValue>0x0</resetValue>
27771          <resetMask>0xF</resetMask>
27772          <fields>
27773            <field>
27774              <name>WAKE_UP</name>
27775              <description>Wake up request. Active on incoming slave request (with address match).
27776
27777Only used when EC_AM is '1'.</description>
27778              <bitRange>[0:0]</bitRange>
27779              <access>read-write</access>
27780            </field>
27781            <field>
27782              <name>EZ_STOP</name>
27783              <description>STOP detection. Activated on the end of a every transfer (I2C STOP).
27784
27785Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'.</description>
27786              <bitRange>[1:1]</bitRange>
27787              <access>read-write</access>
27788            </field>
27789            <field>
27790              <name>EZ_WRITE_STOP</name>
27791              <description>STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a  transfer that only writes the base address does NOT activate this event.
27792
27793Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'.</description>
27794              <bitRange>[2:2]</bitRange>
27795              <access>read-write</access>
27796            </field>
27797            <field>
27798              <name>EZ_READ_STOP</name>
27799              <description>STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from.
27800
27801Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'.</description>
27802              <bitRange>[3:3]</bitRange>
27803              <access>read-write</access>
27804            </field>
27805          </fields>
27806        </register>
27807        <register>
27808          <name>INTR_I2C_EC_MASK</name>
27809          <description>Externally clocked I2C interrupt mask</description>
27810          <addressOffset>0xE88</addressOffset>
27811          <size>32</size>
27812          <access>read-write</access>
27813          <resetValue>0x0</resetValue>
27814          <resetMask>0xF</resetMask>
27815          <fields>
27816            <field>
27817              <name>WAKE_UP</name>
27818              <description>Mask bit for corresponding bit in interrupt request register.</description>
27819              <bitRange>[0:0]</bitRange>
27820              <access>read-write</access>
27821            </field>
27822            <field>
27823              <name>EZ_STOP</name>
27824              <description>Mask bit for corresponding bit in interrupt request register.</description>
27825              <bitRange>[1:1]</bitRange>
27826              <access>read-write</access>
27827            </field>
27828            <field>
27829              <name>EZ_WRITE_STOP</name>
27830              <description>Mask bit for corresponding bit in interrupt request register.</description>
27831              <bitRange>[2:2]</bitRange>
27832              <access>read-write</access>
27833            </field>
27834            <field>
27835              <name>EZ_READ_STOP</name>
27836              <description>Mask bit for corresponding bit in interrupt request register.</description>
27837              <bitRange>[3:3]</bitRange>
27838              <access>read-write</access>
27839            </field>
27840          </fields>
27841        </register>
27842        <register>
27843          <name>INTR_I2C_EC_MASKED</name>
27844          <description>Externally clocked I2C interrupt masked</description>
27845          <addressOffset>0xE8C</addressOffset>
27846          <size>32</size>
27847          <access>read-only</access>
27848          <resetValue>0x0</resetValue>
27849          <resetMask>0xF</resetMask>
27850          <fields>
27851            <field>
27852              <name>WAKE_UP</name>
27853              <description>Logical and of corresponding request and mask bits.</description>
27854              <bitRange>[0:0]</bitRange>
27855              <access>read-only</access>
27856            </field>
27857            <field>
27858              <name>EZ_STOP</name>
27859              <description>Logical and of corresponding request and mask bits.</description>
27860              <bitRange>[1:1]</bitRange>
27861              <access>read-only</access>
27862            </field>
27863            <field>
27864              <name>EZ_WRITE_STOP</name>
27865              <description>Logical and of corresponding request and mask bits.</description>
27866              <bitRange>[2:2]</bitRange>
27867              <access>read-only</access>
27868            </field>
27869            <field>
27870              <name>EZ_READ_STOP</name>
27871              <description>Logical and of corresponding request and mask bits.</description>
27872              <bitRange>[3:3]</bitRange>
27873              <access>read-only</access>
27874            </field>
27875          </fields>
27876        </register>
27877        <register>
27878          <name>INTR_SPI_EC</name>
27879          <description>Externally clocked SPI interrupt request</description>
27880          <addressOffset>0xEC0</addressOffset>
27881          <size>32</size>
27882          <access>read-write</access>
27883          <resetValue>0x0</resetValue>
27884          <resetMask>0xF</resetMask>
27885          <fields>
27886            <field>
27887              <name>WAKE_UP</name>
27888              <description>Wake up request. Active on incoming slave request when externally clocked selection is '1'.
27889
27890Only used when EC_AM is '1'.</description>
27891              <bitRange>[0:0]</bitRange>
27892              <access>read-write</access>
27893            </field>
27894            <field>
27895              <name>EZ_STOP</name>
27896              <description>STOP detection. Activated on the end of a every transfer (SPI deselection).
27897
27898Only available in EZ and CMD_RESP mode and when EC_OP is '1'.</description>
27899              <bitRange>[1:1]</bitRange>
27900              <access>read-write</access>
27901            </field>
27902            <field>
27903              <name>EZ_WRITE_STOP</name>
27904              <description>STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a  transfer that only writes the base address does NOT activate this event.
27905
27906Only used in EZ and CMD_RESP modes and when EC_OP is '1'.</description>
27907              <bitRange>[2:2]</bitRange>
27908              <access>read-write</access>
27909            </field>
27910            <field>
27911              <name>EZ_READ_STOP</name>
27912              <description>STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from.
27913
27914Only used in EZ and CMD_RESP modes and when EC_OP is '1'.</description>
27915              <bitRange>[3:3]</bitRange>
27916              <access>read-write</access>
27917            </field>
27918          </fields>
27919        </register>
27920        <register>
27921          <name>INTR_SPI_EC_MASK</name>
27922          <description>Externally clocked SPI interrupt mask</description>
27923          <addressOffset>0xEC8</addressOffset>
27924          <size>32</size>
27925          <access>read-write</access>
27926          <resetValue>0x0</resetValue>
27927          <resetMask>0xF</resetMask>
27928          <fields>
27929            <field>
27930              <name>WAKE_UP</name>
27931              <description>Mask bit for corresponding bit in interrupt request register.</description>
27932              <bitRange>[0:0]</bitRange>
27933              <access>read-write</access>
27934            </field>
27935            <field>
27936              <name>EZ_STOP</name>
27937              <description>Mask bit for corresponding bit in interrupt request register.</description>
27938              <bitRange>[1:1]</bitRange>
27939              <access>read-write</access>
27940            </field>
27941            <field>
27942              <name>EZ_WRITE_STOP</name>
27943              <description>Mask bit for corresponding bit in interrupt request register.</description>
27944              <bitRange>[2:2]</bitRange>
27945              <access>read-write</access>
27946            </field>
27947            <field>
27948              <name>EZ_READ_STOP</name>
27949              <description>Mask bit for corresponding bit in interrupt request register.</description>
27950              <bitRange>[3:3]</bitRange>
27951              <access>read-write</access>
27952            </field>
27953          </fields>
27954        </register>
27955        <register>
27956          <name>INTR_SPI_EC_MASKED</name>
27957          <description>Externally clocked SPI interrupt masked</description>
27958          <addressOffset>0xECC</addressOffset>
27959          <size>32</size>
27960          <access>read-only</access>
27961          <resetValue>0x0</resetValue>
27962          <resetMask>0xF</resetMask>
27963          <fields>
27964            <field>
27965              <name>WAKE_UP</name>
27966              <description>Logical and of corresponding request and mask bits.</description>
27967              <bitRange>[0:0]</bitRange>
27968              <access>read-only</access>
27969            </field>
27970            <field>
27971              <name>EZ_STOP</name>
27972              <description>Logical and of corresponding request and mask bits.</description>
27973              <bitRange>[1:1]</bitRange>
27974              <access>read-only</access>
27975            </field>
27976            <field>
27977              <name>EZ_WRITE_STOP</name>
27978              <description>Logical and of corresponding request and mask bits.</description>
27979              <bitRange>[2:2]</bitRange>
27980              <access>read-only</access>
27981            </field>
27982            <field>
27983              <name>EZ_READ_STOP</name>
27984              <description>Logical and of corresponding request and mask bits.</description>
27985              <bitRange>[3:3]</bitRange>
27986              <access>read-only</access>
27987            </field>
27988          </fields>
27989        </register>
27990        <register>
27991          <name>INTR_M</name>
27992          <description>Master interrupt request</description>
27993          <addressOffset>0xF00</addressOffset>
27994          <size>32</size>
27995          <access>read-write</access>
27996          <resetValue>0x0</resetValue>
27997          <resetMask>0x3000317</resetMask>
27998          <fields>
27999            <field>
28000              <name>I2C_ARB_LOST</name>
28001              <description>I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line.
28002
28003The Firmware should clear the TX FIFO, to re-do this transfer.</description>
28004              <bitRange>[0:0]</bitRange>
28005              <access>read-write</access>
28006            </field>
28007            <field>
28008              <name>I2C_NACK</name>
28009              <description>I2C master negative acknowledgement. Set to '1', when the master receives a NACK (typically after the master transmitted the slave address or TX data).</description>
28010              <bitRange>[1:1]</bitRange>
28011              <access>read-write</access>
28012            </field>
28013            <field>
28014              <name>I2C_ACK</name>
28015              <description>I2C master acknowledgement. Set to '1', when the master receives a ACK (typically after the master transmitted the slave address or TX data).</description>
28016              <bitRange>[2:2]</bitRange>
28017              <access>read-write</access>
28018            </field>
28019            <field>
28020              <name>I2C_STOP</name>
28021              <description>I2C master STOP. Set to '1', when the master has transmitted a STOP.</description>
28022              <bitRange>[4:4]</bitRange>
28023              <access>read-write</access>
28024            </field>
28025            <field>
28026              <name>I2C_BUS_ERROR</name>
28027              <description>I2C master bus error (unexpected detection of START or STOP condition).</description>
28028              <bitRange>[8:8]</bitRange>
28029              <access>read-write</access>
28030            </field>
28031            <field>
28032              <name>SPI_DONE</name>
28033              <description>SPI master transfer done event: all data frames in the transmit FIFO are sent, the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty), and SPI select output pin is deselected.</description>
28034              <bitRange>[9:9]</bitRange>
28035              <access>read-write</access>
28036            </field>
28037            <field>
28038              <name>I2C_HS_ENTER</name>
28039              <description>entered I2C Hs-mode, at time t1, SCL falling edge after 'START, 8-bit master code (0000_1XXX), NACK' sequence.</description>
28040              <bitRange>[24:24]</bitRange>
28041              <access>read-write</access>
28042            </field>
28043            <field>
28044              <name>I2C_HS_EXIT</name>
28045              <description>exited I2C Hs-mode, after STOP detection.</description>
28046              <bitRange>[25:25]</bitRange>
28047              <access>read-write</access>
28048            </field>
28049          </fields>
28050        </register>
28051        <register>
28052          <name>INTR_M_SET</name>
28053          <description>Master interrupt set request</description>
28054          <addressOffset>0xF04</addressOffset>
28055          <size>32</size>
28056          <access>read-write</access>
28057          <resetValue>0x0</resetValue>
28058          <resetMask>0x3000317</resetMask>
28059          <fields>
28060            <field>
28061              <name>I2C_ARB_LOST</name>
28062              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28063              <bitRange>[0:0]</bitRange>
28064              <access>read-write</access>
28065            </field>
28066            <field>
28067              <name>I2C_NACK</name>
28068              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28069              <bitRange>[1:1]</bitRange>
28070              <access>read-write</access>
28071            </field>
28072            <field>
28073              <name>I2C_ACK</name>
28074              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28075              <bitRange>[2:2]</bitRange>
28076              <access>read-write</access>
28077            </field>
28078            <field>
28079              <name>I2C_STOP</name>
28080              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28081              <bitRange>[4:4]</bitRange>
28082              <access>read-write</access>
28083            </field>
28084            <field>
28085              <name>I2C_BUS_ERROR</name>
28086              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28087              <bitRange>[8:8]</bitRange>
28088              <access>read-write</access>
28089            </field>
28090            <field>
28091              <name>SPI_DONE</name>
28092              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28093              <bitRange>[9:9]</bitRange>
28094              <access>read-write</access>
28095            </field>
28096            <field>
28097              <name>I2C_HS_ENTER</name>
28098              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28099              <bitRange>[24:24]</bitRange>
28100              <access>read-write</access>
28101            </field>
28102            <field>
28103              <name>I2C_HS_EXIT</name>
28104              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28105              <bitRange>[25:25]</bitRange>
28106              <access>read-write</access>
28107            </field>
28108          </fields>
28109        </register>
28110        <register>
28111          <name>INTR_M_MASK</name>
28112          <description>Master interrupt mask</description>
28113          <addressOffset>0xF08</addressOffset>
28114          <size>32</size>
28115          <access>read-write</access>
28116          <resetValue>0x0</resetValue>
28117          <resetMask>0x3000317</resetMask>
28118          <fields>
28119            <field>
28120              <name>I2C_ARB_LOST</name>
28121              <description>Mask bit for corresponding bit in interrupt request register.</description>
28122              <bitRange>[0:0]</bitRange>
28123              <access>read-write</access>
28124            </field>
28125            <field>
28126              <name>I2C_NACK</name>
28127              <description>Mask bit for corresponding bit in interrupt request register.</description>
28128              <bitRange>[1:1]</bitRange>
28129              <access>read-write</access>
28130            </field>
28131            <field>
28132              <name>I2C_ACK</name>
28133              <description>Mask bit for corresponding bit in interrupt request register.</description>
28134              <bitRange>[2:2]</bitRange>
28135              <access>read-write</access>
28136            </field>
28137            <field>
28138              <name>I2C_STOP</name>
28139              <description>Mask bit for corresponding bit in interrupt request register.</description>
28140              <bitRange>[4:4]</bitRange>
28141              <access>read-write</access>
28142            </field>
28143            <field>
28144              <name>I2C_BUS_ERROR</name>
28145              <description>Mask bit for corresponding bit in interrupt request register.</description>
28146              <bitRange>[8:8]</bitRange>
28147              <access>read-write</access>
28148            </field>
28149            <field>
28150              <name>SPI_DONE</name>
28151              <description>Mask bit for corresponding bit in interrupt request register.</description>
28152              <bitRange>[9:9]</bitRange>
28153              <access>read-write</access>
28154            </field>
28155            <field>
28156              <name>I2C_HS_ENTER</name>
28157              <description>Mask bit for corresponding bit in interrupt request register.</description>
28158              <bitRange>[24:24]</bitRange>
28159              <access>read-write</access>
28160            </field>
28161            <field>
28162              <name>I2C_HS_EXIT</name>
28163              <description>Mask bit for corresponding bit in interrupt request register.</description>
28164              <bitRange>[25:25]</bitRange>
28165              <access>read-write</access>
28166            </field>
28167          </fields>
28168        </register>
28169        <register>
28170          <name>INTR_M_MASKED</name>
28171          <description>Master interrupt masked request</description>
28172          <addressOffset>0xF0C</addressOffset>
28173          <size>32</size>
28174          <access>read-only</access>
28175          <resetValue>0x0</resetValue>
28176          <resetMask>0x3000317</resetMask>
28177          <fields>
28178            <field>
28179              <name>I2C_ARB_LOST</name>
28180              <description>Logical and of corresponding request and mask bits.</description>
28181              <bitRange>[0:0]</bitRange>
28182              <access>read-only</access>
28183            </field>
28184            <field>
28185              <name>I2C_NACK</name>
28186              <description>Logical and of corresponding request and mask bits.</description>
28187              <bitRange>[1:1]</bitRange>
28188              <access>read-only</access>
28189            </field>
28190            <field>
28191              <name>I2C_ACK</name>
28192              <description>Logical and of corresponding request and mask bits.</description>
28193              <bitRange>[2:2]</bitRange>
28194              <access>read-only</access>
28195            </field>
28196            <field>
28197              <name>I2C_STOP</name>
28198              <description>Logical and of corresponding request and mask bits.</description>
28199              <bitRange>[4:4]</bitRange>
28200              <access>read-only</access>
28201            </field>
28202            <field>
28203              <name>I2C_BUS_ERROR</name>
28204              <description>Logical and of corresponding request and mask bits.</description>
28205              <bitRange>[8:8]</bitRange>
28206              <access>read-only</access>
28207            </field>
28208            <field>
28209              <name>SPI_DONE</name>
28210              <description>Logical and of corresponding request and mask bits.</description>
28211              <bitRange>[9:9]</bitRange>
28212              <access>read-only</access>
28213            </field>
28214            <field>
28215              <name>I2C_HS_ENTER</name>
28216              <description>Logical and of corresponding request and mask bits.</description>
28217              <bitRange>[24:24]</bitRange>
28218              <access>read-only</access>
28219            </field>
28220            <field>
28221              <name>I2C_HS_EXIT</name>
28222              <description>Logical and of corresponding request and mask bits.</description>
28223              <bitRange>[25:25]</bitRange>
28224              <access>read-only</access>
28225            </field>
28226          </fields>
28227        </register>
28228        <register>
28229          <name>INTR_S</name>
28230          <description>Slave interrupt request</description>
28231          <addressOffset>0xF40</addressOffset>
28232          <size>32</size>
28233          <access>read-write</access>
28234          <resetValue>0x0</resetValue>
28235          <resetMask>0x3010FFF</resetMask>
28236          <fields>
28237            <field>
28238              <name>I2C_ARB_LOST</name>
28239              <description>I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur, it represents erroneous I2C bus behavior. In case of lost arbitration, the I2C slave state machine abort the ongoing transfer.
28240
28241The Firmware should clear the TX FIFO, to re-do this transfer.</description>
28242              <bitRange>[0:0]</bitRange>
28243              <access>read-write</access>
28244            </field>
28245            <field>
28246              <name>I2C_NACK</name>
28247              <description>I2C slave negative acknowledgement received. Set to '1', when the slave receives a NACK (typically after the slave transmitted TX data).</description>
28248              <bitRange>[1:1]</bitRange>
28249              <access>read-write</access>
28250            </field>
28251            <field>
28252              <name>I2C_ACK</name>
28253              <description>I2C slave acknowledgement received. Set to '1', when the slave receives a ACK (typically after the slave transmitted TX data).</description>
28254              <bitRange>[2:2]</bitRange>
28255              <access>read-write</access>
28256            </field>
28257            <field>
28258              <name>I2C_WRITE_STOP</name>
28259              <description>I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address.
28260
28261In non EZ mode, the event is detected on any I2C write transfer intended for this slave. Note that a I2C write address intended for the slave (address is matching and a it is a write transfer) will result in a I2C_WRITE_STOP event independent of whether the I2C address is ACK'd or NACK'd.
28262
28263In EZ mode, the event is detected only on I2C write transfers that have EZ data written to the memory structure (an I2C write transfer that only communicates an I2C address and EZ address, will not result in this event being detected).
28264
28265this is not applicable when address in previous transfer is master-code.</description>
28266              <bitRange>[3:3]</bitRange>
28267              <access>read-write</access>
28268            </field>
28269            <field>
28270              <name>I2C_STOP</name>
28271              <description>I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address.
28272
28273The event is detected on any I2C transfer intended for this slave. Note that a I2C address intended for the slave (address is matching) will result in a I2C_STOP event independent of whether the I2C address is ACK'd or NACK'd.
28274
28275this is not applicable when address in previous transfer is master-code.</description>
28276              <bitRange>[4:4]</bitRange>
28277              <access>read-write</access>
28278            </field>
28279            <field>
28280              <name>I2C_START</name>
28281              <description>I2C slave START received. Set to '1', when START or REPEATED START event is detected.
28282
28283In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') AND clock stretching is performed  (I2C_CTRL.S_NOT_READY_ADDR_NACK is '0'), this field is NOT set. The Firmware should use INTR_S_EC.WAKE_UP, INTR_S.I2C_ADDR_MATCH and INTR_S.I2C_GENERAL.</description>
28284              <bitRange>[5:5]</bitRange>
28285              <access>read-write</access>
28286            </field>
28287            <field>
28288              <name>I2C_ADDR_MATCH</name>
28289              <description>I2C slave matching address received. If CTRL.ADDR_ACCEPT, the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected.</description>
28290              <bitRange>[6:6]</bitRange>
28291              <access>read-write</access>
28292            </field>
28293            <field>
28294              <name>I2C_GENERAL</name>
28295              <description>I2C slave general call address received.  If CTRL.ADDR_ACCEPT, the received address 0x00 (including the R/W bit) is available in the RX FIFO.   In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected.</description>
28296              <bitRange>[7:7]</bitRange>
28297              <access>read-write</access>
28298            </field>
28299            <field>
28300              <name>I2C_BUS_ERROR</name>
28301              <description>I2C slave bus error (unexpected detection of START or STOP condition). This should not occur, it represents erroneous I2C bus behavior. In case of a bus error, the I2C slave state machine abort the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error.</description>
28302              <bitRange>[8:8]</bitRange>
28303              <access>read-write</access>
28304            </field>
28305            <field>
28306              <name>SPI_EZ_WRITE_STOP</name>
28307              <description>SPI slave deselected after a write EZ SPI transfer occurred.</description>
28308              <bitRange>[9:9]</bitRange>
28309              <access>read-write</access>
28310            </field>
28311            <field>
28312              <name>SPI_EZ_STOP</name>
28313              <description>SPI slave deselected after any EZ SPI transfer occurred.</description>
28314              <bitRange>[10:10]</bitRange>
28315              <access>read-write</access>
28316            </field>
28317            <field>
28318              <name>SPI_BUS_ERROR</name>
28319              <description>SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error.</description>
28320              <bitRange>[11:11]</bitRange>
28321              <access>read-write</access>
28322            </field>
28323            <field>
28324              <name>I2C_RESTART</name>
28325              <description>I2C slave RESTART received.
28326Set to '1', when REPEATED START event is detected.
28327
28328In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') AND clock stretching is performed  (I2C_CTRL.S_NOT_READY_ADDR_NACK is '0'), this field is NOT set.
28329
28330this is not applicable when address in previous transfer is master-code.</description>
28331              <bitRange>[16:16]</bitRange>
28332              <access>read-write</access>
28333            </field>
28334            <field>
28335              <name>I2C_HS_ENTER</name>
28336              <description>entered I2C Hs-mode, at time t1, SCL falling edge after 'START, 8-bit master code (0000_1XXX), NACK' sequence.</description>
28337              <bitRange>[24:24]</bitRange>
28338              <access>read-write</access>
28339            </field>
28340            <field>
28341              <name>I2C_HS_EXIT</name>
28342              <description>exited I2C Hs-mode, after STOP detection.</description>
28343              <bitRange>[25:25]</bitRange>
28344              <access>read-write</access>
28345            </field>
28346          </fields>
28347        </register>
28348        <register>
28349          <name>INTR_S_SET</name>
28350          <description>Slave interrupt set request</description>
28351          <addressOffset>0xF44</addressOffset>
28352          <size>32</size>
28353          <access>read-write</access>
28354          <resetValue>0x0</resetValue>
28355          <resetMask>0x3010FFF</resetMask>
28356          <fields>
28357            <field>
28358              <name>I2C_ARB_LOST</name>
28359              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28360              <bitRange>[0:0]</bitRange>
28361              <access>read-write</access>
28362            </field>
28363            <field>
28364              <name>I2C_NACK</name>
28365              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28366              <bitRange>[1:1]</bitRange>
28367              <access>read-write</access>
28368            </field>
28369            <field>
28370              <name>I2C_ACK</name>
28371              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28372              <bitRange>[2:2]</bitRange>
28373              <access>read-write</access>
28374            </field>
28375            <field>
28376              <name>I2C_WRITE_STOP</name>
28377              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28378              <bitRange>[3:3]</bitRange>
28379              <access>read-write</access>
28380            </field>
28381            <field>
28382              <name>I2C_STOP</name>
28383              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28384              <bitRange>[4:4]</bitRange>
28385              <access>read-write</access>
28386            </field>
28387            <field>
28388              <name>I2C_START</name>
28389              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28390              <bitRange>[5:5]</bitRange>
28391              <access>read-write</access>
28392            </field>
28393            <field>
28394              <name>I2C_ADDR_MATCH</name>
28395              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28396              <bitRange>[6:6]</bitRange>
28397              <access>read-write</access>
28398            </field>
28399            <field>
28400              <name>I2C_GENERAL</name>
28401              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28402              <bitRange>[7:7]</bitRange>
28403              <access>read-write</access>
28404            </field>
28405            <field>
28406              <name>I2C_BUS_ERROR</name>
28407              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28408              <bitRange>[8:8]</bitRange>
28409              <access>read-write</access>
28410            </field>
28411            <field>
28412              <name>SPI_EZ_WRITE_STOP</name>
28413              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28414              <bitRange>[9:9]</bitRange>
28415              <access>read-write</access>
28416            </field>
28417            <field>
28418              <name>SPI_EZ_STOP</name>
28419              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28420              <bitRange>[10:10]</bitRange>
28421              <access>read-write</access>
28422            </field>
28423            <field>
28424              <name>SPI_BUS_ERROR</name>
28425              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28426              <bitRange>[11:11]</bitRange>
28427              <access>read-write</access>
28428            </field>
28429            <field>
28430              <name>I2C_RESTART</name>
28431              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28432              <bitRange>[16:16]</bitRange>
28433              <access>read-write</access>
28434            </field>
28435            <field>
28436              <name>I2C_HS_ENTER</name>
28437              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28438              <bitRange>[24:24]</bitRange>
28439              <access>read-write</access>
28440            </field>
28441            <field>
28442              <name>I2C_HS_EXIT</name>
28443              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28444              <bitRange>[25:25]</bitRange>
28445              <access>read-write</access>
28446            </field>
28447          </fields>
28448        </register>
28449        <register>
28450          <name>INTR_S_MASK</name>
28451          <description>Slave interrupt mask</description>
28452          <addressOffset>0xF48</addressOffset>
28453          <size>32</size>
28454          <access>read-write</access>
28455          <resetValue>0x0</resetValue>
28456          <resetMask>0x3010FFF</resetMask>
28457          <fields>
28458            <field>
28459              <name>I2C_ARB_LOST</name>
28460              <description>Mask bit for corresponding bit in interrupt request register.</description>
28461              <bitRange>[0:0]</bitRange>
28462              <access>read-write</access>
28463            </field>
28464            <field>
28465              <name>I2C_NACK</name>
28466              <description>Mask bit for corresponding bit in interrupt request register.</description>
28467              <bitRange>[1:1]</bitRange>
28468              <access>read-write</access>
28469            </field>
28470            <field>
28471              <name>I2C_ACK</name>
28472              <description>Mask bit for corresponding bit in interrupt request register.</description>
28473              <bitRange>[2:2]</bitRange>
28474              <access>read-write</access>
28475            </field>
28476            <field>
28477              <name>I2C_WRITE_STOP</name>
28478              <description>Mask bit for corresponding bit in interrupt request register.</description>
28479              <bitRange>[3:3]</bitRange>
28480              <access>read-write</access>
28481            </field>
28482            <field>
28483              <name>I2C_STOP</name>
28484              <description>Mask bit for corresponding bit in interrupt request register.</description>
28485              <bitRange>[4:4]</bitRange>
28486              <access>read-write</access>
28487            </field>
28488            <field>
28489              <name>I2C_START</name>
28490              <description>Mask bit for corresponding bit in interrupt request register.</description>
28491              <bitRange>[5:5]</bitRange>
28492              <access>read-write</access>
28493            </field>
28494            <field>
28495              <name>I2C_ADDR_MATCH</name>
28496              <description>Mask bit for corresponding bit in interrupt request register.</description>
28497              <bitRange>[6:6]</bitRange>
28498              <access>read-write</access>
28499            </field>
28500            <field>
28501              <name>I2C_GENERAL</name>
28502              <description>Mask bit for corresponding bit in interrupt request register.</description>
28503              <bitRange>[7:7]</bitRange>
28504              <access>read-write</access>
28505            </field>
28506            <field>
28507              <name>I2C_BUS_ERROR</name>
28508              <description>Mask bit for corresponding bit in interrupt request register.</description>
28509              <bitRange>[8:8]</bitRange>
28510              <access>read-write</access>
28511            </field>
28512            <field>
28513              <name>SPI_EZ_WRITE_STOP</name>
28514              <description>Mask bit for corresponding bit in interrupt request register.</description>
28515              <bitRange>[9:9]</bitRange>
28516              <access>read-write</access>
28517            </field>
28518            <field>
28519              <name>SPI_EZ_STOP</name>
28520              <description>Mask bit for corresponding bit in interrupt request register.</description>
28521              <bitRange>[10:10]</bitRange>
28522              <access>read-write</access>
28523            </field>
28524            <field>
28525              <name>SPI_BUS_ERROR</name>
28526              <description>Mask bit for corresponding bit in interrupt request register.</description>
28527              <bitRange>[11:11]</bitRange>
28528              <access>read-write</access>
28529            </field>
28530            <field>
28531              <name>I2C_RESTART</name>
28532              <description>Mask bit for corresponding bit in interrupt request register.</description>
28533              <bitRange>[16:16]</bitRange>
28534              <access>read-write</access>
28535            </field>
28536            <field>
28537              <name>I2C_HS_ENTER</name>
28538              <description>Mask bit for corresponding bit in interrupt request register.</description>
28539              <bitRange>[24:24]</bitRange>
28540              <access>read-write</access>
28541            </field>
28542            <field>
28543              <name>I2C_HS_EXIT</name>
28544              <description>Mask bit for corresponding bit in interrupt request register.</description>
28545              <bitRange>[25:25]</bitRange>
28546              <access>read-write</access>
28547            </field>
28548          </fields>
28549        </register>
28550        <register>
28551          <name>INTR_S_MASKED</name>
28552          <description>Slave interrupt masked request</description>
28553          <addressOffset>0xF4C</addressOffset>
28554          <size>32</size>
28555          <access>read-only</access>
28556          <resetValue>0x0</resetValue>
28557          <resetMask>0x3010FFF</resetMask>
28558          <fields>
28559            <field>
28560              <name>I2C_ARB_LOST</name>
28561              <description>Logical and of corresponding request and mask bits.</description>
28562              <bitRange>[0:0]</bitRange>
28563              <access>read-only</access>
28564            </field>
28565            <field>
28566              <name>I2C_NACK</name>
28567              <description>Logical and of corresponding request and mask bits.</description>
28568              <bitRange>[1:1]</bitRange>
28569              <access>read-only</access>
28570            </field>
28571            <field>
28572              <name>I2C_ACK</name>
28573              <description>Logical and of corresponding request and mask bits.</description>
28574              <bitRange>[2:2]</bitRange>
28575              <access>read-only</access>
28576            </field>
28577            <field>
28578              <name>I2C_WRITE_STOP</name>
28579              <description>Logical and of corresponding request and mask bits.</description>
28580              <bitRange>[3:3]</bitRange>
28581              <access>read-only</access>
28582            </field>
28583            <field>
28584              <name>I2C_STOP</name>
28585              <description>Logical and of corresponding request and mask bits.</description>
28586              <bitRange>[4:4]</bitRange>
28587              <access>read-only</access>
28588            </field>
28589            <field>
28590              <name>I2C_START</name>
28591              <description>Logical and of corresponding request and mask bits.</description>
28592              <bitRange>[5:5]</bitRange>
28593              <access>read-only</access>
28594            </field>
28595            <field>
28596              <name>I2C_ADDR_MATCH</name>
28597              <description>Logical and of corresponding request and mask bits.</description>
28598              <bitRange>[6:6]</bitRange>
28599              <access>read-only</access>
28600            </field>
28601            <field>
28602              <name>I2C_GENERAL</name>
28603              <description>Logical and of corresponding request and mask bits.</description>
28604              <bitRange>[7:7]</bitRange>
28605              <access>read-only</access>
28606            </field>
28607            <field>
28608              <name>I2C_BUS_ERROR</name>
28609              <description>Logical and of corresponding request and mask bits.</description>
28610              <bitRange>[8:8]</bitRange>
28611              <access>read-only</access>
28612            </field>
28613            <field>
28614              <name>SPI_EZ_WRITE_STOP</name>
28615              <description>Logical and of corresponding request and mask bits.</description>
28616              <bitRange>[9:9]</bitRange>
28617              <access>read-only</access>
28618            </field>
28619            <field>
28620              <name>SPI_EZ_STOP</name>
28621              <description>Logical and of corresponding request and mask bits.</description>
28622              <bitRange>[10:10]</bitRange>
28623              <access>read-only</access>
28624            </field>
28625            <field>
28626              <name>SPI_BUS_ERROR</name>
28627              <description>Logical and of corresponding request and mask bits.</description>
28628              <bitRange>[11:11]</bitRange>
28629              <access>read-only</access>
28630            </field>
28631            <field>
28632              <name>I2C_RESTART</name>
28633              <description>Logical and of corresponding request and mask bits.</description>
28634              <bitRange>[16:16]</bitRange>
28635              <access>read-only</access>
28636            </field>
28637            <field>
28638              <name>I2C_HS_ENTER</name>
28639              <description>Logical and of corresponding request and mask bits.</description>
28640              <bitRange>[24:24]</bitRange>
28641              <access>read-only</access>
28642            </field>
28643            <field>
28644              <name>I2C_HS_EXIT</name>
28645              <description>Logical and of corresponding request and mask bits.</description>
28646              <bitRange>[25:25]</bitRange>
28647              <access>read-only</access>
28648            </field>
28649          </fields>
28650        </register>
28651        <register>
28652          <name>INTR_TX</name>
28653          <description>Transmitter interrupt request</description>
28654          <addressOffset>0xF80</addressOffset>
28655          <size>32</size>
28656          <access>read-write</access>
28657          <resetValue>0x0</resetValue>
28658          <resetMask>0x7F3</resetMask>
28659          <fields>
28660            <field>
28661              <name>TRIGGER</name>
28662              <description>Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL.
28663
28664Only used in FIFO mode.</description>
28665              <bitRange>[0:0]</bitRange>
28666              <access>read-write</access>
28667            </field>
28668            <field>
28669              <name>NOT_FULL</name>
28670              <description>TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)
28671MEM_WIDTH is '0': # entries != FF_DATA_NR.
28672MEM_WIDTH is '1': # entries != FF_DATA_NR/2.
28673MEM_WIDTH is '2': # entries != FF_DATA_NR/4.
28674
28675Only used in FIFO mode.</description>
28676              <bitRange>[1:1]</bitRange>
28677              <access>read-write</access>
28678            </field>
28679            <field>
28680              <name>EMPTY</name>
28681              <description>TX FIFO is empty; i.e. it has 0 entries.
28682
28683Only used in FIFO mode.</description>
28684              <bitRange>[4:4]</bitRange>
28685              <access>read-write</access>
28686            </field>
28687            <field>
28688              <name>OVERFLOW</name>
28689              <description>Attempt to write to a full TX FIFO.
28690
28691Only used in FIFO mode.</description>
28692              <bitRange>[5:5]</bitRange>
28693              <access>read-write</access>
28694            </field>
28695            <field>
28696              <name>UNDERFLOW</name>
28697              <description>Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and EMPTY is '1'.
28698
28699Only used in FIFO mode.</description>
28700              <bitRange>[6:6]</bitRange>
28701              <access>read-write</access>
28702            </field>
28703            <field>
28704              <name>BLOCKED</name>
28705              <description>AHB-Lite write transfer can not get access to the EZ memory (EZ data access), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'.</description>
28706              <bitRange>[7:7]</bitRange>
28707              <access>read-write</access>
28708            </field>
28709            <field>
28710              <name>UART_NACK</name>
28711              <description>UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1', when event is detected. Write with '1' to clear bit.</description>
28712              <bitRange>[8:8]</bitRange>
28713              <access>read-write</access>
28714            </field>
28715            <field>
28716              <name>UART_DONE</name>
28717              <description>UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO, and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1', when event is detected. Write with '1' to clear bit.</description>
28718              <bitRange>[9:9]</bitRange>
28719              <access>read-write</access>
28720            </field>
28721            <field>
28722              <name>UART_ARB_LOST</name>
28723              <description>UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to '1', when event is detected. Write with '1' to clear bit.</description>
28724              <bitRange>[10:10]</bitRange>
28725              <access>read-write</access>
28726            </field>
28727          </fields>
28728        </register>
28729        <register>
28730          <name>INTR_TX_SET</name>
28731          <description>Transmitter interrupt set request</description>
28732          <addressOffset>0xF84</addressOffset>
28733          <size>32</size>
28734          <access>read-write</access>
28735          <resetValue>0x0</resetValue>
28736          <resetMask>0x7F3</resetMask>
28737          <fields>
28738            <field>
28739              <name>TRIGGER</name>
28740              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28741              <bitRange>[0:0]</bitRange>
28742              <access>read-write</access>
28743            </field>
28744            <field>
28745              <name>NOT_FULL</name>
28746              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28747              <bitRange>[1:1]</bitRange>
28748              <access>read-write</access>
28749            </field>
28750            <field>
28751              <name>EMPTY</name>
28752              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28753              <bitRange>[4:4]</bitRange>
28754              <access>read-write</access>
28755            </field>
28756            <field>
28757              <name>OVERFLOW</name>
28758              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28759              <bitRange>[5:5]</bitRange>
28760              <access>read-write</access>
28761            </field>
28762            <field>
28763              <name>UNDERFLOW</name>
28764              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28765              <bitRange>[6:6]</bitRange>
28766              <access>read-write</access>
28767            </field>
28768            <field>
28769              <name>BLOCKED</name>
28770              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28771              <bitRange>[7:7]</bitRange>
28772              <access>read-write</access>
28773            </field>
28774            <field>
28775              <name>UART_NACK</name>
28776              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28777              <bitRange>[8:8]</bitRange>
28778              <access>read-write</access>
28779            </field>
28780            <field>
28781              <name>UART_DONE</name>
28782              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28783              <bitRange>[9:9]</bitRange>
28784              <access>read-write</access>
28785            </field>
28786            <field>
28787              <name>UART_ARB_LOST</name>
28788              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28789              <bitRange>[10:10]</bitRange>
28790              <access>read-write</access>
28791            </field>
28792          </fields>
28793        </register>
28794        <register>
28795          <name>INTR_TX_MASK</name>
28796          <description>Transmitter interrupt mask</description>
28797          <addressOffset>0xF88</addressOffset>
28798          <size>32</size>
28799          <access>read-write</access>
28800          <resetValue>0x0</resetValue>
28801          <resetMask>0x7F3</resetMask>
28802          <fields>
28803            <field>
28804              <name>TRIGGER</name>
28805              <description>Mask bit for corresponding bit in interrupt request register.</description>
28806              <bitRange>[0:0]</bitRange>
28807              <access>read-write</access>
28808            </field>
28809            <field>
28810              <name>NOT_FULL</name>
28811              <description>Mask bit for corresponding bit in interrupt request register.</description>
28812              <bitRange>[1:1]</bitRange>
28813              <access>read-write</access>
28814            </field>
28815            <field>
28816              <name>EMPTY</name>
28817              <description>Mask bit for corresponding bit in interrupt request register.</description>
28818              <bitRange>[4:4]</bitRange>
28819              <access>read-write</access>
28820            </field>
28821            <field>
28822              <name>OVERFLOW</name>
28823              <description>Mask bit for corresponding bit in interrupt request register.</description>
28824              <bitRange>[5:5]</bitRange>
28825              <access>read-write</access>
28826            </field>
28827            <field>
28828              <name>UNDERFLOW</name>
28829              <description>Mask bit for corresponding bit in interrupt request register.</description>
28830              <bitRange>[6:6]</bitRange>
28831              <access>read-write</access>
28832            </field>
28833            <field>
28834              <name>BLOCKED</name>
28835              <description>Mask bit for corresponding bit in interrupt request register.</description>
28836              <bitRange>[7:7]</bitRange>
28837              <access>read-write</access>
28838            </field>
28839            <field>
28840              <name>UART_NACK</name>
28841              <description>Mask bit for corresponding bit in interrupt request register.</description>
28842              <bitRange>[8:8]</bitRange>
28843              <access>read-write</access>
28844            </field>
28845            <field>
28846              <name>UART_DONE</name>
28847              <description>Mask bit for corresponding bit in interrupt request register.</description>
28848              <bitRange>[9:9]</bitRange>
28849              <access>read-write</access>
28850            </field>
28851            <field>
28852              <name>UART_ARB_LOST</name>
28853              <description>Mask bit for corresponding bit in interrupt request register.</description>
28854              <bitRange>[10:10]</bitRange>
28855              <access>read-write</access>
28856            </field>
28857          </fields>
28858        </register>
28859        <register>
28860          <name>INTR_TX_MASKED</name>
28861          <description>Transmitter interrupt masked request</description>
28862          <addressOffset>0xF8C</addressOffset>
28863          <size>32</size>
28864          <access>read-only</access>
28865          <resetValue>0x0</resetValue>
28866          <resetMask>0x7F3</resetMask>
28867          <fields>
28868            <field>
28869              <name>TRIGGER</name>
28870              <description>Logical and of corresponding request and mask bits.</description>
28871              <bitRange>[0:0]</bitRange>
28872              <access>read-only</access>
28873            </field>
28874            <field>
28875              <name>NOT_FULL</name>
28876              <description>Logical and of corresponding request and mask bits.</description>
28877              <bitRange>[1:1]</bitRange>
28878              <access>read-only</access>
28879            </field>
28880            <field>
28881              <name>EMPTY</name>
28882              <description>Logical and of corresponding request and mask bits.</description>
28883              <bitRange>[4:4]</bitRange>
28884              <access>read-only</access>
28885            </field>
28886            <field>
28887              <name>OVERFLOW</name>
28888              <description>Logical and of corresponding request and mask bits.</description>
28889              <bitRange>[5:5]</bitRange>
28890              <access>read-only</access>
28891            </field>
28892            <field>
28893              <name>UNDERFLOW</name>
28894              <description>Logical and of corresponding request and mask bits.</description>
28895              <bitRange>[6:6]</bitRange>
28896              <access>read-only</access>
28897            </field>
28898            <field>
28899              <name>BLOCKED</name>
28900              <description>Logical and of corresponding request and mask bits.</description>
28901              <bitRange>[7:7]</bitRange>
28902              <access>read-only</access>
28903            </field>
28904            <field>
28905              <name>UART_NACK</name>
28906              <description>Logical and of corresponding request and mask bits.</description>
28907              <bitRange>[8:8]</bitRange>
28908              <access>read-only</access>
28909            </field>
28910            <field>
28911              <name>UART_DONE</name>
28912              <description>Logical and of corresponding request and mask bits.</description>
28913              <bitRange>[9:9]</bitRange>
28914              <access>read-only</access>
28915            </field>
28916            <field>
28917              <name>UART_ARB_LOST</name>
28918              <description>Logical and of corresponding request and mask bits.</description>
28919              <bitRange>[10:10]</bitRange>
28920              <access>read-only</access>
28921            </field>
28922          </fields>
28923        </register>
28924        <register>
28925          <name>INTR_RX</name>
28926          <description>Receiver interrupt request</description>
28927          <addressOffset>0xFC0</addressOffset>
28928          <size>32</size>
28929          <access>read-write</access>
28930          <resetValue>0x0</resetValue>
28931          <resetMask>0xFED</resetMask>
28932          <fields>
28933            <field>
28934              <name>TRIGGER</name>
28935              <description>More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL.
28936
28937Only used in FIFO mode.</description>
28938              <bitRange>[0:0]</bitRange>
28939              <access>read-write</access>
28940            </field>
28941            <field>
28942              <name>NOT_EMPTY</name>
28943              <description>RX FIFO is not empty.
28944
28945Only used in FIFO mode.</description>
28946              <bitRange>[2:2]</bitRange>
28947              <access>read-write</access>
28948            </field>
28949            <field>
28950              <name>FULL</name>
28951              <description>RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)
28952MEM_WIDTH is '0': # entries == FF_DATA_NR.
28953MEM_WIDTH is '1': # entries == FF_DATA_NR/2.
28954MEM_WIDTH is '2': # entries == FF_DATA_NR/4.
28955
28956Only used in FIFO mode.</description>
28957              <bitRange>[3:3]</bitRange>
28958              <access>read-write</access>
28959            </field>
28960            <field>
28961              <name>OVERFLOW</name>
28962              <description>Attempt to write to a full RX FIFO. Note: in I2C mode, the OVERFLOW is set when a data frame is received and the RX FIFO is full, independent of whether it is ACK'd or NACK'd.
28963
28964Only used in FIFO mode.</description>
28965              <bitRange>[5:5]</bitRange>
28966              <access>read-write</access>
28967            </field>
28968            <field>
28969              <name>UNDERFLOW</name>
28970              <description>Attempt to read from an empty RX FIFO.
28971
28972Only used in FIFO mode.</description>
28973              <bitRange>[6:6]</bitRange>
28974              <access>read-write</access>
28975            </field>
28976            <field>
28977              <name>BLOCKED</name>
28978              <description>AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'.</description>
28979              <bitRange>[7:7]</bitRange>
28980              <access>read-write</access>
28981            </field>
28982            <field>
28983              <name>FRAME_ERROR</name>
28984              <description>Frame error in received data frame. Set to '1', when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:
28985Start bit error: after the detection of the beginning of a start bit period (RX line changes from '1' to '0'), the middle of the start bit period is sampled erroneously (RX line is '1').  Note: a start bit error is detected BEFORE a data frame is received.
28986Stop bit error: the RX line is sampled as '0', but a '1' was expected. Note: a stop bit error may result in failure to receive successive data frame(s). Note: a stop bit error is detected AFTER a data frame is received.
28987
28988A stop bit error is detected after a data frame is received, and the UART_RX_CTL.DROP_ON_FRAME_ERROR field specifies whether the received frame is dropped or send to the RX FIFO. If UART_RX_CTL.DROP_ON_FRAME_ERROR is '1', the received data frame is dropped. If UART_RX_CTL.DROP_ON_FRAME_ERROR is '0', the received data frame is send to the RX FIFO. Note that Firmware can only identify the erroneous data frame in the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data frame into the RX FIFO; i.e. the RX FIFO does not have error flags to tag erroneous data frames.</description>
28989              <bitRange>[8:8]</bitRange>
28990              <access>read-write</access>
28991            </field>
28992            <field>
28993              <name>PARITY_ERROR</name>
28994              <description>Parity error in received data frame. Set to '1', when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1', the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0', the received frame is send to the RX FIFO. In SmartCard submode, negatively acknowledged data frames generate a parity error. Note that Firmware can only identify the erroneous data frame in the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data frame into the RX FIFO.</description>
28995              <bitRange>[9:9]</bitRange>
28996              <access>read-write</access>
28997            </field>
28998            <field>
28999              <name>BAUD_DETECT</name>
29000              <description>LIN baudrate detection is completed.  The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte. Set to '1', when event is detected. Write with '1' to clear bit.</description>
29001              <bitRange>[10:10]</bitRange>
29002              <access>read-write</access>
29003            </field>
29004            <field>
29005              <name>BREAK_DETECT</name>
29006              <description>Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and LIN submodes. For the UART standard submodes, ongoing receipt of data frames is NOT affected; i.e. Firmware is expected to take the proper action. For the LIN submode, possible ongoing receipt of a data frame is stopped and the (partially) received data frame is dropped and baud rate detection is started. Set to '1', when event is detected. Write with '1' to clear bit.</description>
29007              <bitRange>[11:11]</bitRange>
29008              <access>read-write</access>
29009            </field>
29010          </fields>
29011        </register>
29012        <register>
29013          <name>INTR_RX_SET</name>
29014          <description>Receiver interrupt set request</description>
29015          <addressOffset>0xFC4</addressOffset>
29016          <size>32</size>
29017          <access>read-write</access>
29018          <resetValue>0x0</resetValue>
29019          <resetMask>0xFED</resetMask>
29020          <fields>
29021            <field>
29022              <name>TRIGGER</name>
29023              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
29024              <bitRange>[0:0]</bitRange>
29025              <access>read-write</access>
29026            </field>
29027            <field>
29028              <name>NOT_EMPTY</name>
29029              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
29030              <bitRange>[2:2]</bitRange>
29031              <access>read-write</access>
29032            </field>
29033            <field>
29034              <name>FULL</name>
29035              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
29036              <bitRange>[3:3]</bitRange>
29037              <access>read-write</access>
29038            </field>
29039            <field>
29040              <name>OVERFLOW</name>
29041              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
29042              <bitRange>[5:5]</bitRange>
29043              <access>read-write</access>
29044            </field>
29045            <field>
29046              <name>UNDERFLOW</name>
29047              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
29048              <bitRange>[6:6]</bitRange>
29049              <access>read-write</access>
29050            </field>
29051            <field>
29052              <name>BLOCKED</name>
29053              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
29054              <bitRange>[7:7]</bitRange>
29055              <access>read-write</access>
29056            </field>
29057            <field>
29058              <name>FRAME_ERROR</name>
29059              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
29060              <bitRange>[8:8]</bitRange>
29061              <access>read-write</access>
29062            </field>
29063            <field>
29064              <name>PARITY_ERROR</name>
29065              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
29066              <bitRange>[9:9]</bitRange>
29067              <access>read-write</access>
29068            </field>
29069            <field>
29070              <name>BAUD_DETECT</name>
29071              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
29072              <bitRange>[10:10]</bitRange>
29073              <access>read-write</access>
29074            </field>
29075            <field>
29076              <name>BREAK_DETECT</name>
29077              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
29078              <bitRange>[11:11]</bitRange>
29079              <access>read-write</access>
29080            </field>
29081          </fields>
29082        </register>
29083        <register>
29084          <name>INTR_RX_MASK</name>
29085          <description>Receiver interrupt mask</description>
29086          <addressOffset>0xFC8</addressOffset>
29087          <size>32</size>
29088          <access>read-write</access>
29089          <resetValue>0x0</resetValue>
29090          <resetMask>0xFED</resetMask>
29091          <fields>
29092            <field>
29093              <name>TRIGGER</name>
29094              <description>Mask bit for corresponding bit in interrupt request register.</description>
29095              <bitRange>[0:0]</bitRange>
29096              <access>read-write</access>
29097            </field>
29098            <field>
29099              <name>NOT_EMPTY</name>
29100              <description>Mask bit for corresponding bit in interrupt request register.</description>
29101              <bitRange>[2:2]</bitRange>
29102              <access>read-write</access>
29103            </field>
29104            <field>
29105              <name>FULL</name>
29106              <description>Mask bit for corresponding bit in interrupt request register.</description>
29107              <bitRange>[3:3]</bitRange>
29108              <access>read-write</access>
29109            </field>
29110            <field>
29111              <name>OVERFLOW</name>
29112              <description>Mask bit for corresponding bit in interrupt request register.</description>
29113              <bitRange>[5:5]</bitRange>
29114              <access>read-write</access>
29115            </field>
29116            <field>
29117              <name>UNDERFLOW</name>
29118              <description>Mask bit for corresponding bit in interrupt request register.</description>
29119              <bitRange>[6:6]</bitRange>
29120              <access>read-write</access>
29121            </field>
29122            <field>
29123              <name>BLOCKED</name>
29124              <description>Mask bit for corresponding bit in interrupt request register.</description>
29125              <bitRange>[7:7]</bitRange>
29126              <access>read-write</access>
29127            </field>
29128            <field>
29129              <name>FRAME_ERROR</name>
29130              <description>Mask bit for corresponding bit in interrupt request register.</description>
29131              <bitRange>[8:8]</bitRange>
29132              <access>read-write</access>
29133            </field>
29134            <field>
29135              <name>PARITY_ERROR</name>
29136              <description>Mask bit for corresponding bit in interrupt request register.</description>
29137              <bitRange>[9:9]</bitRange>
29138              <access>read-write</access>
29139            </field>
29140            <field>
29141              <name>BAUD_DETECT</name>
29142              <description>Mask bit for corresponding bit in interrupt request register.</description>
29143              <bitRange>[10:10]</bitRange>
29144              <access>read-write</access>
29145            </field>
29146            <field>
29147              <name>BREAK_DETECT</name>
29148              <description>Mask bit for corresponding bit in interrupt request register.</description>
29149              <bitRange>[11:11]</bitRange>
29150              <access>read-write</access>
29151            </field>
29152          </fields>
29153        </register>
29154        <register>
29155          <name>INTR_RX_MASKED</name>
29156          <description>Receiver interrupt masked request</description>
29157          <addressOffset>0xFCC</addressOffset>
29158          <size>32</size>
29159          <access>read-only</access>
29160          <resetValue>0x0</resetValue>
29161          <resetMask>0xFED</resetMask>
29162          <fields>
29163            <field>
29164              <name>TRIGGER</name>
29165              <description>Logical and of corresponding request and mask bits.</description>
29166              <bitRange>[0:0]</bitRange>
29167              <access>read-only</access>
29168            </field>
29169            <field>
29170              <name>NOT_EMPTY</name>
29171              <description>Logical and of corresponding request and mask bits.</description>
29172              <bitRange>[2:2]</bitRange>
29173              <access>read-only</access>
29174            </field>
29175            <field>
29176              <name>FULL</name>
29177              <description>Logical and of corresponding request and mask bits.</description>
29178              <bitRange>[3:3]</bitRange>
29179              <access>read-only</access>
29180            </field>
29181            <field>
29182              <name>OVERFLOW</name>
29183              <description>Logical and of corresponding request and mask bits.</description>
29184              <bitRange>[5:5]</bitRange>
29185              <access>read-only</access>
29186            </field>
29187            <field>
29188              <name>UNDERFLOW</name>
29189              <description>Logical and of corresponding request and mask bits.</description>
29190              <bitRange>[6:6]</bitRange>
29191              <access>read-only</access>
29192            </field>
29193            <field>
29194              <name>BLOCKED</name>
29195              <description>Logical and of corresponding request and mask bits.</description>
29196              <bitRange>[7:7]</bitRange>
29197              <access>read-only</access>
29198            </field>
29199            <field>
29200              <name>FRAME_ERROR</name>
29201              <description>Logical and of corresponding request and mask bits.</description>
29202              <bitRange>[8:8]</bitRange>
29203              <access>read-only</access>
29204            </field>
29205            <field>
29206              <name>PARITY_ERROR</name>
29207              <description>Logical and of corresponding request and mask bits.</description>
29208              <bitRange>[9:9]</bitRange>
29209              <access>read-only</access>
29210            </field>
29211            <field>
29212              <name>BAUD_DETECT</name>
29213              <description>Logical and of corresponding request and mask bits.</description>
29214              <bitRange>[10:10]</bitRange>
29215              <access>read-only</access>
29216            </field>
29217            <field>
29218              <name>BREAK_DETECT</name>
29219              <description>Logical and of corresponding request and mask bits.</description>
29220              <bitRange>[11:11]</bitRange>
29221              <access>read-only</access>
29222            </field>
29223          </fields>
29224        </register>
29225      </registers>
29226    </peripheral>
29227    <peripheral derivedFrom="SCB0">
29228      <name>SCB1</name>
29229      <baseAddress>0x405A0000</baseAddress>
29230    </peripheral>
29231    <peripheral derivedFrom="SCB0">
29232      <name>SCB2</name>
29233      <baseAddress>0x405B0000</baseAddress>
29234    </peripheral>
29235    <peripheral>
29236      <name>EFUSE</name>
29237      <description>EFUSE MXS40 registers</description>
29238      <baseAddress>0x40810000</baseAddress>
29239      <addressBlock>
29240        <offset>0</offset>
29241        <size>512</size>
29242        <usage>registers</usage>
29243      </addressBlock>
29244      <registers>
29245        <register>
29246          <name>CTL</name>
29247          <description>Control</description>
29248          <addressOffset>0x0</addressOffset>
29249          <size>32</size>
29250          <access>read-write</access>
29251          <resetValue>0x0</resetValue>
29252          <resetMask>0x80000001</resetMask>
29253          <fields>
29254            <field>
29255              <name>LOCK_CC312_REGION</name>
29256              <description>CC312 lock - when set  locks 8 bytes beyond the end of the PROT_MASTER defined space for read access.</description>
29257              <bitRange>[0:0]</bitRange>
29258              <access>read-write</access>
29259            </field>
29260            <field>
29261              <name>ENABLED</name>
29262              <description>IP enable:
29263'0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled.
29264'1': Enabled.</description>
29265              <bitRange>[31:31]</bitRange>
29266              <access>read-write</access>
29267            </field>
29268          </fields>
29269        </register>
29270        <register>
29271          <name>CMD</name>
29272          <description>Command</description>
29273          <addressOffset>0x110</addressOffset>
29274          <size>32</size>
29275          <access>read-write</access>
29276          <resetValue>0x1</resetValue>
29277          <resetMask>0x800F1F71</resetMask>
29278          <fields>
29279            <field>
29280              <name>BIT_DATA</name>
29281              <description>Bit data. This field specifies the bit value that is to be programmed into the eFUSE macro array. The address of the bit is specified by the BIT_ADDR, BYTE_ADDR, and MACRO_ADDR fields.</description>
29282              <bitRange>[0:0]</bitRange>
29283              <access>read-write</access>
29284            </field>
29285            <field>
29286              <name>BIT_ADDR</name>
29287              <description>Bit address. This field specifies a bit within a Byte.</description>
29288              <bitRange>[6:4]</bitRange>
29289              <access>read-write</access>
29290            </field>
29291            <field>
29292              <name>BYTE_ADDR</name>
29293              <description>Byte address. This field specifies a Byte within a eFUSE macro (each macro has 32 B).</description>
29294              <bitRange>[12:8]</bitRange>
29295              <access>read-write</access>
29296            </field>
29297            <field>
29298              <name>MACRO_ADDR</name>
29299              <description>Macro address. This field specifies an eFUSE macro.</description>
29300              <bitRange>[19:16]</bitRange>
29301              <access>read-write</access>
29302            </field>
29303            <field>
29304              <name>START</name>
29305              <description>FW sets this field to '1' to start a program operation. HW sets this field to '0' to indicate that the operation has completed.
29306
29307Note: it is good practice to verify the result of a program operation by reading back a programmed eFUSE memory location. Programming can only change an eFUSE memory bit from '0' to '1'; i.e. a programming operation is a 'one-off' operation for each eFUSE memory bit: once a bit is changed to '1', it can NEVER be changed back to '0' as a hardware fuse is blown.
29308
29309Programming a memory bit to '1' requires blowing a fuse and requires an eFUSE macro operation. Therefore, this programmiong operation takes time (as specified by the SEQ_PROGRAM_CTL reguisters). Programming amemory bit to '0' does not require an eFUSE macro operation (it is the default eFUSE macro state). Therefore, this programming operation is almost instantaneous.
29310
29311Note: during a program operation, a read operation can not be performed. An AHB-Lite read transfer to the eFUSE memory during a program operation results in an AHB-Lite bus error.</description>
29312              <bitRange>[31:31]</bitRange>
29313              <access>read-write</access>
29314            </field>
29315          </fields>
29316        </register>
29317        <register>
29318          <name>SEQ_DEFAULT</name>
29319          <description>Sequencer Default value</description>
29320          <addressOffset>0x120</addressOffset>
29321          <size>32</size>
29322          <access>read-write</access>
29323          <resetValue>0x1D0000</resetValue>
29324          <resetMask>0x7F0000</resetMask>
29325          <fields>
29326            <field>
29327              <name>STROBE_A</name>
29328              <description>Specifies value of eFUSE control signal strobe_f</description>
29329              <bitRange>[16:16]</bitRange>
29330              <access>read-write</access>
29331            </field>
29332            <field>
29333              <name>STROBE_B</name>
29334              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
29335              <bitRange>[17:17]</bitRange>
29336              <access>read-write</access>
29337            </field>
29338            <field>
29339              <name>STROBE_C</name>
29340              <description>Specifies value of eFUSE control signal strobe_c</description>
29341              <bitRange>[18:18]</bitRange>
29342              <access>read-write</access>
29343            </field>
29344            <field>
29345              <name>STROBE_D</name>
29346              <description>Specifies value of eFUSE control signal strobe_d</description>
29347              <bitRange>[19:19]</bitRange>
29348              <access>read-write</access>
29349            </field>
29350            <field>
29351              <name>STROBE_E</name>
29352              <description>Specifies value of eFUSE control signal strobe_e</description>
29353              <bitRange>[20:20]</bitRange>
29354              <access>read-write</access>
29355            </field>
29356            <field>
29357              <name>STROBE_F</name>
29358              <description>Specifies value of eFUSE control signal strobe_f</description>
29359              <bitRange>[21:21]</bitRange>
29360              <access>read-write</access>
29361            </field>
29362            <field>
29363              <name>STROBE_G</name>
29364              <description>Specifies value of eFUSE control signal strobe_g</description>
29365              <bitRange>[22:22]</bitRange>
29366              <access>read-write</access>
29367            </field>
29368          </fields>
29369        </register>
29370        <register>
29371          <name>SEQ_READ_CTL_0</name>
29372          <description>Sequencer read control 0</description>
29373          <addressOffset>0x140</addressOffset>
29374          <size>32</size>
29375          <access>read-write</access>
29376          <resetValue>0x150006</resetValue>
29377          <resetMask>0x807F03FF</resetMask>
29378          <fields>
29379            <field>
29380              <name>CYCLES</name>
29381              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
29382              <bitRange>[9:0]</bitRange>
29383              <access>read-write</access>
29384            </field>
29385            <field>
29386              <name>STROBE_A</name>
29387              <description>Specifies value of eFUSE control signal strobe_f</description>
29388              <bitRange>[16:16]</bitRange>
29389              <access>read-write</access>
29390            </field>
29391            <field>
29392              <name>STROBE_B</name>
29393              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
29394              <bitRange>[17:17]</bitRange>
29395              <access>read-write</access>
29396            </field>
29397            <field>
29398              <name>STROBE_C</name>
29399              <description>Specifies value of eFUSE control signal strobe_c</description>
29400              <bitRange>[18:18]</bitRange>
29401              <access>read-write</access>
29402            </field>
29403            <field>
29404              <name>STROBE_D</name>
29405              <description>Specifies value of eFUSE control signal strobe_d</description>
29406              <bitRange>[19:19]</bitRange>
29407              <access>read-write</access>
29408            </field>
29409            <field>
29410              <name>STROBE_E</name>
29411              <description>Specifies value of eFUSE control signal strobe_e</description>
29412              <bitRange>[20:20]</bitRange>
29413              <access>read-write</access>
29414            </field>
29415            <field>
29416              <name>STROBE_F</name>
29417              <description>Specifies value of eFUSE control signal strobe_f</description>
29418              <bitRange>[21:21]</bitRange>
29419              <access>read-write</access>
29420            </field>
29421            <field>
29422              <name>STROBE_G</name>
29423              <description>Specifies value of eFUSE control signal strobe_g</description>
29424              <bitRange>[22:22]</bitRange>
29425              <access>read-write</access>
29426            </field>
29427            <field>
29428              <name>DONE</name>
29429              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
29430              <bitRange>[31:31]</bitRange>
29431              <access>read-write</access>
29432            </field>
29433          </fields>
29434        </register>
29435        <register>
29436          <name>SEQ_READ_CTL_1</name>
29437          <description>Sequencer read control 1</description>
29438          <addressOffset>0x144</addressOffset>
29439          <size>32</size>
29440          <access>read-write</access>
29441          <resetValue>0x140001</resetValue>
29442          <resetMask>0x807F03FF</resetMask>
29443          <fields>
29444            <field>
29445              <name>CYCLES</name>
29446              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
29447              <bitRange>[9:0]</bitRange>
29448              <access>read-write</access>
29449            </field>
29450            <field>
29451              <name>STROBE_A</name>
29452              <description>Specifies value of eFUSE control signal strobe_f</description>
29453              <bitRange>[16:16]</bitRange>
29454              <access>read-write</access>
29455            </field>
29456            <field>
29457              <name>STROBE_B</name>
29458              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
29459              <bitRange>[17:17]</bitRange>
29460              <access>read-write</access>
29461            </field>
29462            <field>
29463              <name>STROBE_C</name>
29464              <description>Specifies value of eFUSE control signal strobe_c</description>
29465              <bitRange>[18:18]</bitRange>
29466              <access>read-write</access>
29467            </field>
29468            <field>
29469              <name>STROBE_D</name>
29470              <description>Specifies value of eFUSE control signal strobe_d</description>
29471              <bitRange>[19:19]</bitRange>
29472              <access>read-write</access>
29473            </field>
29474            <field>
29475              <name>STROBE_E</name>
29476              <description>Specifies value of eFUSE control signal strobe_e</description>
29477              <bitRange>[20:20]</bitRange>
29478              <access>read-write</access>
29479            </field>
29480            <field>
29481              <name>STROBE_F</name>
29482              <description>Specifies value of eFUSE control signal strobe_f</description>
29483              <bitRange>[21:21]</bitRange>
29484              <access>read-write</access>
29485            </field>
29486            <field>
29487              <name>STROBE_G</name>
29488              <description>Specifies value of eFUSE control signal strobe_g</description>
29489              <bitRange>[22:22]</bitRange>
29490              <access>read-write</access>
29491            </field>
29492            <field>
29493              <name>DONE</name>
29494              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
29495              <bitRange>[31:31]</bitRange>
29496              <access>read-write</access>
29497            </field>
29498          </fields>
29499        </register>
29500        <register>
29501          <name>SEQ_READ_CTL_2</name>
29502          <description>Sequencer read control 2</description>
29503          <addressOffset>0x148</addressOffset>
29504          <size>32</size>
29505          <access>read-write</access>
29506          <resetValue>0x540001</resetValue>
29507          <resetMask>0x807F03FF</resetMask>
29508          <fields>
29509            <field>
29510              <name>CYCLES</name>
29511              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
29512              <bitRange>[9:0]</bitRange>
29513              <access>read-write</access>
29514            </field>
29515            <field>
29516              <name>STROBE_A</name>
29517              <description>Specifies value of eFUSE control signal strobe_f</description>
29518              <bitRange>[16:16]</bitRange>
29519              <access>read-write</access>
29520            </field>
29521            <field>
29522              <name>STROBE_B</name>
29523              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
29524              <bitRange>[17:17]</bitRange>
29525              <access>read-write</access>
29526            </field>
29527            <field>
29528              <name>STROBE_C</name>
29529              <description>Specifies value of eFUSE control signal strobe_c</description>
29530              <bitRange>[18:18]</bitRange>
29531              <access>read-write</access>
29532            </field>
29533            <field>
29534              <name>STROBE_D</name>
29535              <description>Specifies value of eFUSE control signal strobe_d</description>
29536              <bitRange>[19:19]</bitRange>
29537              <access>read-write</access>
29538            </field>
29539            <field>
29540              <name>STROBE_E</name>
29541              <description>Specifies value of eFUSE control signal strobe_e</description>
29542              <bitRange>[20:20]</bitRange>
29543              <access>read-write</access>
29544            </field>
29545            <field>
29546              <name>STROBE_F</name>
29547              <description>Specifies value of eFUSE control signal strobe_f</description>
29548              <bitRange>[21:21]</bitRange>
29549              <access>read-write</access>
29550            </field>
29551            <field>
29552              <name>STROBE_G</name>
29553              <description>Specifies value of eFUSE control signal strobe_g</description>
29554              <bitRange>[22:22]</bitRange>
29555              <access>read-write</access>
29556            </field>
29557            <field>
29558              <name>DONE</name>
29559              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
29560              <bitRange>[31:31]</bitRange>
29561              <access>read-write</access>
29562            </field>
29563          </fields>
29564        </register>
29565        <register>
29566          <name>SEQ_READ_CTL_3</name>
29567          <description>Sequencer read control 3</description>
29568          <addressOffset>0x14C</addressOffset>
29569          <size>32</size>
29570          <access>read-write</access>
29571          <resetValue>0x560001</resetValue>
29572          <resetMask>0x807F03FF</resetMask>
29573          <fields>
29574            <field>
29575              <name>CYCLES</name>
29576              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
29577              <bitRange>[9:0]</bitRange>
29578              <access>read-write</access>
29579            </field>
29580            <field>
29581              <name>STROBE_A</name>
29582              <description>Specifies value of eFUSE control signal strobe_f</description>
29583              <bitRange>[16:16]</bitRange>
29584              <access>read-write</access>
29585            </field>
29586            <field>
29587              <name>STROBE_B</name>
29588              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
29589              <bitRange>[17:17]</bitRange>
29590              <access>read-write</access>
29591            </field>
29592            <field>
29593              <name>STROBE_C</name>
29594              <description>Specifies value of eFUSE control signal strobe_c</description>
29595              <bitRange>[18:18]</bitRange>
29596              <access>read-write</access>
29597            </field>
29598            <field>
29599              <name>STROBE_D</name>
29600              <description>Specifies value of eFUSE control signal strobe_d</description>
29601              <bitRange>[19:19]</bitRange>
29602              <access>read-write</access>
29603            </field>
29604            <field>
29605              <name>STROBE_E</name>
29606              <description>Specifies value of eFUSE control signal strobe_e</description>
29607              <bitRange>[20:20]</bitRange>
29608              <access>read-write</access>
29609            </field>
29610            <field>
29611              <name>STROBE_F</name>
29612              <description>Specifies value of eFUSE control signal strobe_f</description>
29613              <bitRange>[21:21]</bitRange>
29614              <access>read-write</access>
29615            </field>
29616            <field>
29617              <name>STROBE_G</name>
29618              <description>Specifies value of eFUSE control signal strobe_g</description>
29619              <bitRange>[22:22]</bitRange>
29620              <access>read-write</access>
29621            </field>
29622            <field>
29623              <name>DONE</name>
29624              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
29625              <bitRange>[31:31]</bitRange>
29626              <access>read-write</access>
29627            </field>
29628          </fields>
29629        </register>
29630        <register>
29631          <name>SEQ_READ_CTL_4</name>
29632          <description>Sequencer read control 4</description>
29633          <addressOffset>0x150</addressOffset>
29634          <size>32</size>
29635          <access>read-write</access>
29636          <resetValue>0x540001</resetValue>
29637          <resetMask>0x807F03FF</resetMask>
29638          <fields>
29639            <field>
29640              <name>CYCLES</name>
29641              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
29642              <bitRange>[9:0]</bitRange>
29643              <access>read-write</access>
29644            </field>
29645            <field>
29646              <name>STROBE_A</name>
29647              <description>Specifies value of eFUSE control signal strobe_f</description>
29648              <bitRange>[16:16]</bitRange>
29649              <access>read-write</access>
29650            </field>
29651            <field>
29652              <name>STROBE_B</name>
29653              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
29654              <bitRange>[17:17]</bitRange>
29655              <access>read-write</access>
29656            </field>
29657            <field>
29658              <name>STROBE_C</name>
29659              <description>Specifies value of eFUSE control signal strobe_c</description>
29660              <bitRange>[18:18]</bitRange>
29661              <access>read-write</access>
29662            </field>
29663            <field>
29664              <name>STROBE_D</name>
29665              <description>Specifies value of eFUSE control signal strobe_d</description>
29666              <bitRange>[19:19]</bitRange>
29667              <access>read-write</access>
29668            </field>
29669            <field>
29670              <name>STROBE_E</name>
29671              <description>Specifies value of eFUSE control signal strobe_e</description>
29672              <bitRange>[20:20]</bitRange>
29673              <access>read-write</access>
29674            </field>
29675            <field>
29676              <name>STROBE_F</name>
29677              <description>Specifies value of eFUSE control signal strobe_f</description>
29678              <bitRange>[21:21]</bitRange>
29679              <access>read-write</access>
29680            </field>
29681            <field>
29682              <name>STROBE_G</name>
29683              <description>Specifies value of eFUSE control signal strobe_g</description>
29684              <bitRange>[22:22]</bitRange>
29685              <access>read-write</access>
29686            </field>
29687            <field>
29688              <name>DONE</name>
29689              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
29690              <bitRange>[31:31]</bitRange>
29691              <access>read-write</access>
29692            </field>
29693          </fields>
29694        </register>
29695        <register>
29696          <name>SEQ_READ_CTL_5</name>
29697          <description>Sequencer read control 5</description>
29698          <addressOffset>0x154</addressOffset>
29699          <size>32</size>
29700          <access>read-write</access>
29701          <resetValue>0x140001</resetValue>
29702          <resetMask>0x807F03FF</resetMask>
29703          <fields>
29704            <field>
29705              <name>CYCLES</name>
29706              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
29707              <bitRange>[9:0]</bitRange>
29708              <access>read-write</access>
29709            </field>
29710            <field>
29711              <name>STROBE_A</name>
29712              <description>Specifies value of eFUSE control signal strobe_f</description>
29713              <bitRange>[16:16]</bitRange>
29714              <access>read-write</access>
29715            </field>
29716            <field>
29717              <name>STROBE_B</name>
29718              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
29719              <bitRange>[17:17]</bitRange>
29720              <access>read-write</access>
29721            </field>
29722            <field>
29723              <name>STROBE_C</name>
29724              <description>Specifies value of eFUSE control signal strobe_c</description>
29725              <bitRange>[18:18]</bitRange>
29726              <access>read-write</access>
29727            </field>
29728            <field>
29729              <name>STROBE_D</name>
29730              <description>Specifies value of eFUSE control signal strobe_d</description>
29731              <bitRange>[19:19]</bitRange>
29732              <access>read-write</access>
29733            </field>
29734            <field>
29735              <name>STROBE_E</name>
29736              <description>Specifies value of eFUSE control signal strobe_e</description>
29737              <bitRange>[20:20]</bitRange>
29738              <access>read-write</access>
29739            </field>
29740            <field>
29741              <name>STROBE_F</name>
29742              <description>Specifies value of eFUSE control signal strobe_f</description>
29743              <bitRange>[21:21]</bitRange>
29744              <access>read-write</access>
29745            </field>
29746            <field>
29747              <name>STROBE_G</name>
29748              <description>Specifies value of eFUSE control signal strobe_g</description>
29749              <bitRange>[22:22]</bitRange>
29750              <access>read-write</access>
29751            </field>
29752            <field>
29753              <name>DONE</name>
29754              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
29755              <bitRange>[31:31]</bitRange>
29756              <access>read-write</access>
29757            </field>
29758          </fields>
29759        </register>
29760        <register>
29761          <name>SEQ_READ_CTL_6</name>
29762          <description>Sequencer read control 6</description>
29763          <addressOffset>0x158</addressOffset>
29764          <size>32</size>
29765          <access>read-write</access>
29766          <resetValue>0x80150006</resetValue>
29767          <resetMask>0x807F03FF</resetMask>
29768          <fields>
29769            <field>
29770              <name>CYCLES</name>
29771              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
29772              <bitRange>[9:0]</bitRange>
29773              <access>read-write</access>
29774            </field>
29775            <field>
29776              <name>STROBE_A</name>
29777              <description>Specifies value of eFUSE control signal strobe_f</description>
29778              <bitRange>[16:16]</bitRange>
29779              <access>read-write</access>
29780            </field>
29781            <field>
29782              <name>STROBE_B</name>
29783              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
29784              <bitRange>[17:17]</bitRange>
29785              <access>read-write</access>
29786            </field>
29787            <field>
29788              <name>STROBE_C</name>
29789              <description>Specifies value of eFUSE control signal strobe_c</description>
29790              <bitRange>[18:18]</bitRange>
29791              <access>read-write</access>
29792            </field>
29793            <field>
29794              <name>STROBE_D</name>
29795              <description>Specifies value of eFUSE control signal strobe_d</description>
29796              <bitRange>[19:19]</bitRange>
29797              <access>read-write</access>
29798            </field>
29799            <field>
29800              <name>STROBE_E</name>
29801              <description>Specifies value of eFUSE control signal strobe_e</description>
29802              <bitRange>[20:20]</bitRange>
29803              <access>read-write</access>
29804            </field>
29805            <field>
29806              <name>STROBE_F</name>
29807              <description>Specifies value of eFUSE control signal strobe_f</description>
29808              <bitRange>[21:21]</bitRange>
29809              <access>read-write</access>
29810            </field>
29811            <field>
29812              <name>STROBE_G</name>
29813              <description>Specifies value of eFUSE control signal strobe_g</description>
29814              <bitRange>[22:22]</bitRange>
29815              <access>read-write</access>
29816            </field>
29817            <field>
29818              <name>DONE</name>
29819              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
29820              <bitRange>[31:31]</bitRange>
29821              <access>read-write</access>
29822            </field>
29823          </fields>
29824        </register>
29825        <register>
29826          <name>SEQ_READ_CTL_7</name>
29827          <description>Sequencer read control 7</description>
29828          <addressOffset>0x15C</addressOffset>
29829          <size>32</size>
29830          <access>read-write</access>
29831          <resetValue>0x801D0001</resetValue>
29832          <resetMask>0x807F03FF</resetMask>
29833          <fields>
29834            <field>
29835              <name>CYCLES</name>
29836              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
29837              <bitRange>[9:0]</bitRange>
29838              <access>read-write</access>
29839            </field>
29840            <field>
29841              <name>STROBE_A</name>
29842              <description>Specifies value of eFUSE control signal strobe_f</description>
29843              <bitRange>[16:16]</bitRange>
29844              <access>read-write</access>
29845            </field>
29846            <field>
29847              <name>STROBE_B</name>
29848              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
29849              <bitRange>[17:17]</bitRange>
29850              <access>read-write</access>
29851            </field>
29852            <field>
29853              <name>STROBE_C</name>
29854              <description>Specifies value of eFUSE control signal strobe_c</description>
29855              <bitRange>[18:18]</bitRange>
29856              <access>read-write</access>
29857            </field>
29858            <field>
29859              <name>STROBE_D</name>
29860              <description>Specifies value of eFUSE control signal strobe_d</description>
29861              <bitRange>[19:19]</bitRange>
29862              <access>read-write</access>
29863            </field>
29864            <field>
29865              <name>STROBE_E</name>
29866              <description>Specifies value of eFUSE control signal strobe_e</description>
29867              <bitRange>[20:20]</bitRange>
29868              <access>read-write</access>
29869            </field>
29870            <field>
29871              <name>STROBE_F</name>
29872              <description>Specifies value of eFUSE control signal strobe_f</description>
29873              <bitRange>[21:21]</bitRange>
29874              <access>read-write</access>
29875            </field>
29876            <field>
29877              <name>STROBE_G</name>
29878              <description>Specifies value of eFUSE control signal strobe_g</description>
29879              <bitRange>[22:22]</bitRange>
29880              <access>read-write</access>
29881            </field>
29882            <field>
29883              <name>DONE</name>
29884              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
29885              <bitRange>[31:31]</bitRange>
29886              <access>read-write</access>
29887            </field>
29888          </fields>
29889        </register>
29890        <register>
29891          <name>SEQ_PROGRAM_CTL_0</name>
29892          <description>Sequencer program control 0</description>
29893          <addressOffset>0x160</addressOffset>
29894          <size>32</size>
29895          <access>read-write</access>
29896          <resetValue>0x150006</resetValue>
29897          <resetMask>0x807F03FF</resetMask>
29898          <fields>
29899            <field>
29900              <name>CYCLES</name>
29901              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
29902              <bitRange>[9:0]</bitRange>
29903              <access>read-write</access>
29904            </field>
29905            <field>
29906              <name>STROBE_A</name>
29907              <description>Specifies value of eFUSE control signal strobe_a</description>
29908              <bitRange>[16:16]</bitRange>
29909              <access>read-write</access>
29910            </field>
29911            <field>
29912              <name>STROBE_B</name>
29913              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
29914              <bitRange>[17:17]</bitRange>
29915              <access>read-write</access>
29916            </field>
29917            <field>
29918              <name>STROBE_C</name>
29919              <description>Specifies value of eFUSE control signal strobe_c</description>
29920              <bitRange>[18:18]</bitRange>
29921              <access>read-write</access>
29922            </field>
29923            <field>
29924              <name>STROBE_D</name>
29925              <description>Specifies value of eFUSE control signal strobe_d</description>
29926              <bitRange>[19:19]</bitRange>
29927              <access>read-write</access>
29928            </field>
29929            <field>
29930              <name>STROBE_E</name>
29931              <description>Specifies value of eFUSE control signal strobe_e</description>
29932              <bitRange>[20:20]</bitRange>
29933              <access>read-write</access>
29934            </field>
29935            <field>
29936              <name>STROBE_F</name>
29937              <description>Specifies value of eFUSE control signal strobe_f</description>
29938              <bitRange>[21:21]</bitRange>
29939              <access>read-write</access>
29940            </field>
29941            <field>
29942              <name>STROBE_G</name>
29943              <description>Specifies value of eFUSE control signal strobe_g</description>
29944              <bitRange>[22:22]</bitRange>
29945              <access>read-write</access>
29946            </field>
29947            <field>
29948              <name>DONE</name>
29949              <description>When set to 1 indicates that the Program cycle ends when the current cycle count reaches 0.</description>
29950              <bitRange>[31:31]</bitRange>
29951              <access>read-write</access>
29952            </field>
29953          </fields>
29954        </register>
29955        <register>
29956          <name>SEQ_PROGRAM_CTL_1</name>
29957          <description>Sequencer program control 1</description>
29958          <addressOffset>0x164</addressOffset>
29959          <size>32</size>
29960          <access>read-write</access>
29961          <resetValue>0x35000B</resetValue>
29962          <resetMask>0x807F03FF</resetMask>
29963          <fields>
29964            <field>
29965              <name>CYCLES</name>
29966              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
29967              <bitRange>[9:0]</bitRange>
29968              <access>read-write</access>
29969            </field>
29970            <field>
29971              <name>STROBE_A</name>
29972              <description>Specifies value of eFUSE control signal strobe_a</description>
29973              <bitRange>[16:16]</bitRange>
29974              <access>read-write</access>
29975            </field>
29976            <field>
29977              <name>STROBE_B</name>
29978              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
29979              <bitRange>[17:17]</bitRange>
29980              <access>read-write</access>
29981            </field>
29982            <field>
29983              <name>STROBE_C</name>
29984              <description>Specifies value of eFUSE control signal strobe_c</description>
29985              <bitRange>[18:18]</bitRange>
29986              <access>read-write</access>
29987            </field>
29988            <field>
29989              <name>STROBE_D</name>
29990              <description>Specifies value of eFUSE control signal strobe_d</description>
29991              <bitRange>[19:19]</bitRange>
29992              <access>read-write</access>
29993            </field>
29994            <field>
29995              <name>STROBE_E</name>
29996              <description>Specifies value of eFUSE control signal strobe_e</description>
29997              <bitRange>[20:20]</bitRange>
29998              <access>read-write</access>
29999            </field>
30000            <field>
30001              <name>STROBE_F</name>
30002              <description>Specifies value of eFUSE control signal strobe_f</description>
30003              <bitRange>[21:21]</bitRange>
30004              <access>read-write</access>
30005            </field>
30006            <field>
30007              <name>STROBE_G</name>
30008              <description>Specifies value of eFUSE control signal strobe_g</description>
30009              <bitRange>[22:22]</bitRange>
30010              <access>read-write</access>
30011            </field>
30012            <field>
30013              <name>DONE</name>
30014              <description>When set to 1 indicates that the Program cycle ends when the current cycle count reaches 0.</description>
30015              <bitRange>[31:31]</bitRange>
30016              <access>read-write</access>
30017            </field>
30018          </fields>
30019        </register>
30020        <register>
30021          <name>SEQ_PROGRAM_CTL_2</name>
30022          <description>Sequencer program control 2</description>
30023          <addressOffset>0x168</addressOffset>
30024          <size>32</size>
30025          <access>read-write</access>
30026          <resetValue>0x240001</resetValue>
30027          <resetMask>0x807F03FF</resetMask>
30028          <fields>
30029            <field>
30030              <name>CYCLES</name>
30031              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
30032              <bitRange>[9:0]</bitRange>
30033              <access>read-write</access>
30034            </field>
30035            <field>
30036              <name>STROBE_A</name>
30037              <description>Specifies value of eFUSE control signal strobe_a</description>
30038              <bitRange>[16:16]</bitRange>
30039              <access>read-write</access>
30040            </field>
30041            <field>
30042              <name>STROBE_B</name>
30043              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
30044              <bitRange>[17:17]</bitRange>
30045              <access>read-write</access>
30046            </field>
30047            <field>
30048              <name>STROBE_C</name>
30049              <description>Specifies value of eFUSE control signal strobe_c</description>
30050              <bitRange>[18:18]</bitRange>
30051              <access>read-write</access>
30052            </field>
30053            <field>
30054              <name>STROBE_D</name>
30055              <description>Specifies value of eFUSE control signal strobe_d</description>
30056              <bitRange>[19:19]</bitRange>
30057              <access>read-write</access>
30058            </field>
30059            <field>
30060              <name>STROBE_E</name>
30061              <description>Specifies value of eFUSE control signal strobe_e</description>
30062              <bitRange>[20:20]</bitRange>
30063              <access>read-write</access>
30064            </field>
30065            <field>
30066              <name>STROBE_F</name>
30067              <description>Specifies value of eFUSE control signal strobe_f</description>
30068              <bitRange>[21:21]</bitRange>
30069              <access>read-write</access>
30070            </field>
30071            <field>
30072              <name>STROBE_G</name>
30073              <description>Specifies value of eFUSE control signal strobe_g</description>
30074              <bitRange>[22:22]</bitRange>
30075              <access>read-write</access>
30076            </field>
30077            <field>
30078              <name>DONE</name>
30079              <description>When set to 1 indicates that the Program cycle ends when the current cycle count reaches 0.</description>
30080              <bitRange>[31:31]</bitRange>
30081              <access>read-write</access>
30082            </field>
30083          </fields>
30084        </register>
30085        <register>
30086          <name>SEQ_PROGRAM_CTL_3</name>
30087          <description>Sequencer program control 3</description>
30088          <addressOffset>0x16C</addressOffset>
30089          <size>32</size>
30090          <access>read-write</access>
30091          <resetValue>0x26001E</resetValue>
30092          <resetMask>0x807F03FF</resetMask>
30093          <fields>
30094            <field>
30095              <name>CYCLES</name>
30096              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
30097              <bitRange>[9:0]</bitRange>
30098              <access>read-write</access>
30099            </field>
30100            <field>
30101              <name>STROBE_A</name>
30102              <description>Specifies value of eFUSE control signal strobe_a</description>
30103              <bitRange>[16:16]</bitRange>
30104              <access>read-write</access>
30105            </field>
30106            <field>
30107              <name>STROBE_B</name>
30108              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
30109              <bitRange>[17:17]</bitRange>
30110              <access>read-write</access>
30111            </field>
30112            <field>
30113              <name>STROBE_C</name>
30114              <description>Specifies value of eFUSE control signal strobe_c</description>
30115              <bitRange>[18:18]</bitRange>
30116              <access>read-write</access>
30117            </field>
30118            <field>
30119              <name>STROBE_D</name>
30120              <description>Specifies value of eFUSE control signal strobe_d</description>
30121              <bitRange>[19:19]</bitRange>
30122              <access>read-write</access>
30123            </field>
30124            <field>
30125              <name>STROBE_E</name>
30126              <description>Specifies value of eFUSE control signal strobe_e</description>
30127              <bitRange>[20:20]</bitRange>
30128              <access>read-write</access>
30129            </field>
30130            <field>
30131              <name>STROBE_F</name>
30132              <description>Specifies value of eFUSE control signal strobe_f</description>
30133              <bitRange>[21:21]</bitRange>
30134              <access>read-write</access>
30135            </field>
30136            <field>
30137              <name>STROBE_G</name>
30138              <description>Specifies value of eFUSE control signal strobe_g</description>
30139              <bitRange>[22:22]</bitRange>
30140              <access>read-write</access>
30141            </field>
30142            <field>
30143              <name>DONE</name>
30144              <description>When set to 1 indicates that the Program cycle ends when the current cycle count reaches 0.</description>
30145              <bitRange>[31:31]</bitRange>
30146              <access>read-write</access>
30147            </field>
30148          </fields>
30149        </register>
30150        <register>
30151          <name>SEQ_PROGRAM_CTL_4</name>
30152          <description>Sequencer program control 4</description>
30153          <addressOffset>0x170</addressOffset>
30154          <size>32</size>
30155          <access>read-write</access>
30156          <resetValue>0x240001</resetValue>
30157          <resetMask>0x807F03FF</resetMask>
30158          <fields>
30159            <field>
30160              <name>CYCLES</name>
30161              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
30162              <bitRange>[9:0]</bitRange>
30163              <access>read-write</access>
30164            </field>
30165            <field>
30166              <name>STROBE_A</name>
30167              <description>Specifies value of eFUSE control signal strobe_a</description>
30168              <bitRange>[16:16]</bitRange>
30169              <access>read-write</access>
30170            </field>
30171            <field>
30172              <name>STROBE_B</name>
30173              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
30174              <bitRange>[17:17]</bitRange>
30175              <access>read-write</access>
30176            </field>
30177            <field>
30178              <name>STROBE_C</name>
30179              <description>Specifies value of eFUSE control signal strobe_c</description>
30180              <bitRange>[18:18]</bitRange>
30181              <access>read-write</access>
30182            </field>
30183            <field>
30184              <name>STROBE_D</name>
30185              <description>Specifies value of eFUSE control signal strobe_d</description>
30186              <bitRange>[19:19]</bitRange>
30187              <access>read-write</access>
30188            </field>
30189            <field>
30190              <name>STROBE_E</name>
30191              <description>Specifies value of eFUSE control signal strobe_e</description>
30192              <bitRange>[20:20]</bitRange>
30193              <access>read-write</access>
30194            </field>
30195            <field>
30196              <name>STROBE_F</name>
30197              <description>Specifies value of eFUSE control signal strobe_f</description>
30198              <bitRange>[21:21]</bitRange>
30199              <access>read-write</access>
30200            </field>
30201            <field>
30202              <name>STROBE_G</name>
30203              <description>Specifies value of eFUSE control signal strobe_g</description>
30204              <bitRange>[22:22]</bitRange>
30205              <access>read-write</access>
30206            </field>
30207            <field>
30208              <name>DONE</name>
30209              <description>When set to 1 indicates that the Program cycle ends when the current cycle count reaches 0.</description>
30210              <bitRange>[31:31]</bitRange>
30211              <access>read-write</access>
30212            </field>
30213          </fields>
30214        </register>
30215        <register>
30216          <name>SEQ_PROGRAM_CTL_5</name>
30217          <description>Sequencer program control 5</description>
30218          <addressOffset>0x174</addressOffset>
30219          <size>32</size>
30220          <access>read-write</access>
30221          <resetValue>0x340001</resetValue>
30222          <resetMask>0x807F03FF</resetMask>
30223          <fields>
30224            <field>
30225              <name>CYCLES</name>
30226              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
30227              <bitRange>[9:0]</bitRange>
30228              <access>read-write</access>
30229            </field>
30230            <field>
30231              <name>STROBE_A</name>
30232              <description>Specifies value of eFUSE control signal strobe_a</description>
30233              <bitRange>[16:16]</bitRange>
30234              <access>read-write</access>
30235            </field>
30236            <field>
30237              <name>STROBE_B</name>
30238              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
30239              <bitRange>[17:17]</bitRange>
30240              <access>read-write</access>
30241            </field>
30242            <field>
30243              <name>STROBE_C</name>
30244              <description>Specifies value of eFUSE control signal strobe_c</description>
30245              <bitRange>[18:18]</bitRange>
30246              <access>read-write</access>
30247            </field>
30248            <field>
30249              <name>STROBE_D</name>
30250              <description>Specifies value of eFUSE control signal strobe_d</description>
30251              <bitRange>[19:19]</bitRange>
30252              <access>read-write</access>
30253            </field>
30254            <field>
30255              <name>STROBE_E</name>
30256              <description>Specifies value of eFUSE control signal strobe_e</description>
30257              <bitRange>[20:20]</bitRange>
30258              <access>read-write</access>
30259            </field>
30260            <field>
30261              <name>STROBE_F</name>
30262              <description>Specifies value of eFUSE control signal strobe_f</description>
30263              <bitRange>[21:21]</bitRange>
30264              <access>read-write</access>
30265            </field>
30266            <field>
30267              <name>STROBE_G</name>
30268              <description>Specifies value of eFUSE control signal strobe_g</description>
30269              <bitRange>[22:22]</bitRange>
30270              <access>read-write</access>
30271            </field>
30272            <field>
30273              <name>DONE</name>
30274              <description>When set to 1 indicates that the Program cycle ends when the current cycle count reaches 0.</description>
30275              <bitRange>[31:31]</bitRange>
30276              <access>read-write</access>
30277            </field>
30278          </fields>
30279        </register>
30280        <register>
30281          <name>SEQ_PROGRAM_CTL_6</name>
30282          <description>Sequencer program control 6</description>
30283          <addressOffset>0x178</addressOffset>
30284          <size>32</size>
30285          <access>read-write</access>
30286          <resetValue>0x350001</resetValue>
30287          <resetMask>0x807F03FF</resetMask>
30288          <fields>
30289            <field>
30290              <name>CYCLES</name>
30291              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
30292              <bitRange>[9:0]</bitRange>
30293              <access>read-write</access>
30294            </field>
30295            <field>
30296              <name>STROBE_A</name>
30297              <description>Specifies value of eFUSE control signal strobe_a</description>
30298              <bitRange>[16:16]</bitRange>
30299              <access>read-write</access>
30300            </field>
30301            <field>
30302              <name>STROBE_B</name>
30303              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
30304              <bitRange>[17:17]</bitRange>
30305              <access>read-write</access>
30306            </field>
30307            <field>
30308              <name>STROBE_C</name>
30309              <description>Specifies value of eFUSE control signal strobe_c</description>
30310              <bitRange>[18:18]</bitRange>
30311              <access>read-write</access>
30312            </field>
30313            <field>
30314              <name>STROBE_D</name>
30315              <description>Specifies value of eFUSE control signal strobe_d</description>
30316              <bitRange>[19:19]</bitRange>
30317              <access>read-write</access>
30318            </field>
30319            <field>
30320              <name>STROBE_E</name>
30321              <description>Specifies value of eFUSE control signal strobe_e</description>
30322              <bitRange>[20:20]</bitRange>
30323              <access>read-write</access>
30324            </field>
30325            <field>
30326              <name>STROBE_F</name>
30327              <description>Specifies value of eFUSE control signal strobe_f</description>
30328              <bitRange>[21:21]</bitRange>
30329              <access>read-write</access>
30330            </field>
30331            <field>
30332              <name>STROBE_G</name>
30333              <description>Specifies value of eFUSE control signal strobe_g</description>
30334              <bitRange>[22:22]</bitRange>
30335              <access>read-write</access>
30336            </field>
30337            <field>
30338              <name>DONE</name>
30339              <description>When set to 1 indicates that the Program cycle ends when the current cycle count reaches 0.</description>
30340              <bitRange>[31:31]</bitRange>
30341              <access>read-write</access>
30342            </field>
30343          </fields>
30344        </register>
30345        <register>
30346          <name>SEQ_PROGRAM_CTL_7</name>
30347          <description>Sequencer program control 7</description>
30348          <addressOffset>0x17C</addressOffset>
30349          <size>32</size>
30350          <access>read-write</access>
30351          <resetValue>0x80150006</resetValue>
30352          <resetMask>0x807F03FF</resetMask>
30353          <fields>
30354            <field>
30355              <name>CYCLES</name>
30356              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
30357              <bitRange>[9:0]</bitRange>
30358              <access>read-write</access>
30359            </field>
30360            <field>
30361              <name>STROBE_A</name>
30362              <description>Specifies value of eFUSE control signal strobe_a</description>
30363              <bitRange>[16:16]</bitRange>
30364              <access>read-write</access>
30365            </field>
30366            <field>
30367              <name>STROBE_B</name>
30368              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
30369              <bitRange>[17:17]</bitRange>
30370              <access>read-write</access>
30371            </field>
30372            <field>
30373              <name>STROBE_C</name>
30374              <description>Specifies value of eFUSE control signal strobe_c</description>
30375              <bitRange>[18:18]</bitRange>
30376              <access>read-write</access>
30377            </field>
30378            <field>
30379              <name>STROBE_D</name>
30380              <description>Specifies value of eFUSE control signal strobe_d</description>
30381              <bitRange>[19:19]</bitRange>
30382              <access>read-write</access>
30383            </field>
30384            <field>
30385              <name>STROBE_E</name>
30386              <description>Specifies value of eFUSE control signal strobe_e</description>
30387              <bitRange>[20:20]</bitRange>
30388              <access>read-write</access>
30389            </field>
30390            <field>
30391              <name>STROBE_F</name>
30392              <description>Specifies value of eFUSE control signal strobe_f</description>
30393              <bitRange>[21:21]</bitRange>
30394              <access>read-write</access>
30395            </field>
30396            <field>
30397              <name>STROBE_G</name>
30398              <description>Specifies value of eFUSE control signal strobe_g</description>
30399              <bitRange>[22:22]</bitRange>
30400              <access>read-write</access>
30401            </field>
30402            <field>
30403              <name>DONE</name>
30404              <description>When set to 1 indicates that the Program cycle ends when the current cycle count reaches 0.</description>
30405              <bitRange>[31:31]</bitRange>
30406              <access>read-write</access>
30407            </field>
30408          </fields>
30409        </register>
30410        <register>
30411          <name>BOOTROW</name>
30412          <description>Content of Boot Row latches at power-on-reset</description>
30413          <addressOffset>0x180</addressOffset>
30414          <size>32</size>
30415          <access>read-only</access>
30416          <resetValue>0x0</resetValue>
30417          <resetMask>0x0</resetMask>
30418          <fields>
30419            <field>
30420              <name>BOOT_ROW_DATA</name>
30421              <description>Contains the Boot Row data held by the Boot Row latches.</description>
30422              <bitRange>[31:0]</bitRange>
30423              <access>read-only</access>
30424            </field>
30425          </fields>
30426        </register>
30427      </registers>
30428    </peripheral>
30429    <peripheral>
30430      <name>SMIF0</name>
30431      <description>Serial Memory Interface</description>
30432      <headerStructName>SMIF</headerStructName>
30433      <baseAddress>0x40890000</baseAddress>
30434      <addressBlock>
30435        <offset>0</offset>
30436        <size>65536</size>
30437        <usage>registers</usage>
30438      </addressBlock>
30439      <registers>
30440        <register>
30441          <name>CTL</name>
30442          <description>Control</description>
30443          <addressOffset>0x0</addressOffset>
30444          <size>32</size>
30445          <access>read-write</access>
30446          <resetValue>0x503400</resetValue>
30447          <resetMask>0x83F77FF1</resetMask>
30448          <fields>
30449            <field>
30450              <name>XIP_MODE</name>
30451              <description>Mode of operation.
30452
30453Note: this field should only be changed when the IP is disabled or when STATUS.BUSY is '0' and SW should not be executing from the XIP interface or MMIO interface.</description>
30454              <bitRange>[0:0]</bitRange>
30455              <access>read-write</access>
30456              <enumeratedValues>
30457                <enumeratedValue>
30458                  <name>MMIO_MODE</name>
30459                  <description>'0': MMIO mode. Individual MMIO accesses to TX and RX FIFOs are used to generate a sequence of SPI transfers. This mode of operation allows for large flexibility in terms of the SPI transfers that can be generated.</description>
30460                  <value>0</value>
30461                </enumeratedValue>
30462                <enumeratedValue>
30463                  <name>ARB_MODE</name>
30464                  <description>''1': Arbitration mode. Arbitrates XIP vs. MMIO accesses such that any ongoing, pending, or 'merged' transactions on XIP always take priority over any MMIO accesses to the device.  However, if an MMIO access is in process it cannot be interrupted until it completes (as defined by sending the 'last command' via TX_CMD_MMIO_FIFO_WR).  If MMIO accesses are not happening at all, though, then the XIP accesses endure no extra arbitration latency.</description>
30465                  <value>1</value>
30466                </enumeratedValue>
30467              </enumeratedValues>
30468            </field>
30469            <field>
30470              <name>CLOCK_IF_TX_SEL</name>
30471              <description>Specifies device interface transmitter clock options.
30472'0': SDR. Memory interface clock 'spihb_clk_out' is divided (by 2) interface clock 'clk_if', memory interface data signals are driven by divided (by 2) interface clock 'clk_if' with different phase than 'spihb_clk_out'.
30473Results in driving memory interface data signals at falling 'spihb_clk_out' edge.
30474'1': DDR. Memory interface clock 'spihb_clk_out' is divided (by 2) inverted interface clock 'clk_if_inv', memory interface data signals are driven with interface clock 'clk_if'.
30475Results in driving memory interface data signals 90 degrees before rising and falling 'spihb_clk_out' edge.</description>
30476              <bitRange>[4:4]</bitRange>
30477              <access>read-write</access>
30478            </field>
30479            <field>
30480              <name>DELAY_LINE_SEL</name>
30481              <description>Specifies the delay line used for RX data capturing with
30482- output / feedback clock based capturing (when CLOCK_IF_RX_SEL = [0..3] and DELAY_TAP_ENABLED = 1)
30483- internal clock based capturing (when CLOCK_IF_RX_SEL = [4..5], INT_CLOCK_CAPTURE_PRESENT = 1 and DELAY_TAP_ENABLED = 1)
30484- RWDS based capturing (when CLOCK_IF_RX_SEL = [6..7])</description>
30485              <bitRange>[7:5]</bitRange>
30486              <access>read-write</access>
30487            </field>
30488            <field>
30489              <name>DELAY_TAP_ENABLED</name>
30490              <description>Delay Line Tap Enable.
30491'0': Disabled. The delay line tap selections specified in registers DELAY_TAP_SEL or INT_CLOCK_DELAY_TAP_SEL0/1 are not used. The read data is directly captured by the RX data FIFO capture clock as specified by CLOCK_IF_RX_SEL and INT_CLOCK_CAPTURE_CYCLE.
30492'1': Enabled. The delay line tap selections specified in registers DELAY_TAP_SEL or INT_CLOCK_DELAY_TAP_SEL0/1 are used.
30493If the output / feedback clock based capture scheme (CLOCK_IF_RX_SEL = [0..3]) or the RWDS based capture scheme (CLOCK_IF_RX_SEL = [6..7]) is selected then the register DELAY_TAP_SEL is used to select the capture clock. If the internal clock based capture scheme (CLOCK_IF_RX_SEL = [4..5] and INT_CLOCK_CAPTURE_PRESENT = 1) is selected then the registers INT_CLOCK_DELAY_TAP_SEL0/1 are used to select the capture clock per data bit line (read data is captured by the capture logic and afterwards transferred to the RX data FIFO).</description>
30494              <bitRange>[8:8]</bitRange>
30495              <access>read-write</access>
30496            </field>
30497            <field>
30498              <name>INT_CLOCK_DL_ENABLED</name>
30499              <description>Data Learning Enable for internal RX clock based on Data Learning Pattern. Only applies when CLOCK_IF_RX_SEL = [4..5] for selecting the internal clock based capture scheme and when DELAY_TAP_ENABLED = 1.  Must be set to 0 otherwise.
30500'0': Disabled. The delay line tap selections specified in registers INT_CLOCK_DELAY_TAP_SEL0/1 are not modified by HW.
30501'1': Enabled. The delay linle tap selections specified in registers INT_CLOCK_DELAY_TAP_SEL0/1 are modified by HW based on the data learning pattern. From all capture clock delay line taps producing a match between the expected data learning pattern in register DLP and the captured data learning pattern from the memory device the middle one is selected.</description>
30502              <bitRange>[9:9]</bitRange>
30503              <access>read-write</access>
30504            </field>
30505            <field>
30506              <name>INT_CLOCK_CAPTURE_CYCLE</name>
30507              <description>N/A</description>
30508              <bitRange>[11:10]</bitRange>
30509              <access>read-write</access>
30510            </field>
30511            <field>
30512              <name>CLOCK_IF_RX_SEL</name>
30513              <description>N/A</description>
30514              <bitRange>[14:12]</bitRange>
30515              <access>read-write</access>
30516            </field>
30517            <field>
30518              <name>DESELECT_DELAY</name>
30519              <description>Specifies the minimum duration of SPI deselection ('spi_select_out[]' is high/'1') in between SPI transfers:
30520'0': 1 memory interface clock cycle.
30521'1': 2 memory interface clock cycles.
30522'2': 3 memory interface clock cycles.
30523'3': 4 memory interface clock cycles.
30524'4': 5 memory interface clock cycles.
30525'5': 6 memory interface clock cycles.
30526'6': 7 memory interface clock cycles.
30527'7': 8 memory interface clock cycles.
30528
30529During SPI deselection, 'spi_select_out[]' are '1'/inactive, 'spi_data_out[]' are '1' and 'spi_clk_out' is '0'/inactive.</description>
30530              <bitRange>[18:16]</bitRange>
30531              <access>read-write</access>
30532            </field>
30533            <field>
30534              <name>SELECT_SETUP_DELAY</name>
30535              <description>Specifies the duration between 'spi_select_out[]' becomes low/'0') to 1st 'spi_clk_out' edge:
30536'0': 0 memory interface clock cycles + min. duration (see below).
30537'1': 1 memory interface clock cycle   + min. duration (see below).
30538'2': 2 memory interface clock cycles + min. duration (see below).
30539'3': 3 memory interface clock cycles + min. duration (see below).
30540
30541In addition to the number of cycles selected here there is a min. duration of:
30542- 1 memory interface clock cycle (= 2 clk_if cycle) for SDR timing (CLOCK_IF_TX_SEL = 0)
30543- 1/4 memory interface clock cycle (= 1/2 clk_if cycle) for DDR timing (CLOCK_IF_TX_SEL = 1)</description>
30544              <bitRange>[21:20]</bitRange>
30545              <access>read-write</access>
30546            </field>
30547            <field>
30548              <name>SELECT_HOLD_DELAY</name>
30549              <description>Specifies the duration between last 'spi_clk_out' edge to 'spi_select_out[]' becomes high/'1'):
30550'0': 0 memory interface clock cycles + min. duration (see below).
30551'1': 1 memory interface clock cycle   + min. duration (see below).
30552'2': 2 memory interface clock cycles + min. duration (see below).
30553'3': 3 memory interface clock cycles + min. duration (see below).
30554
30555In addition to the number of cycles selected here there is a min. duration of:
30556- 1/2 memory interface clock cycle (= 1 clk_if cycles) for SDR timing (CLOCK_IF_TX_SEL = 0)
30557- 1/4 memory interface clock cycle (= 1/2 clk_if cycle) for DDR timing (CLOCK_IF_TX_SEL = 1)</description>
30558              <bitRange>[23:22]</bitRange>
30559              <access>read-write</access>
30560            </field>
30561            <field>
30562              <name>BLOCK</name>
30563              <description>Specifies what happens for MMIO interface read accesses to an empty RX data FIFO or to a full TX format/data FIFO.
30564
30565This field is not used for test controller accesses.</description>
30566              <bitRange>[24:24]</bitRange>
30567              <access>read-write</access>
30568              <enumeratedValues>
30569                <enumeratedValue>
30570                  <name>BUS_ERROR</name>
30571                  <description>0': Generate an AHB-Lite bus error. This option is useful when SW decides to use polling on STATUS.TR_BUSY to determine if a interface transfer is no longer busy (transfer is completed). This option adds SW complexity, but limits the number of AHB-Lite wait states (and limits ISR latency).</description>
30572                  <value>0</value>
30573                </enumeratedValue>
30574                <enumeratedValue>
30575                  <name>WAIT_STATES</name>
30576                  <description>1': Introduce wait states. This setting potentially locks up the AHB-Lite infrastructure and may increase the CPU interrupt latency.This option is useful when SW performs TX/RX data FIFO accesses immediately after a command is setup using the TX format FIFO. This option has low SW complexity, but may result in a significant number of AHB-Lite wait states (and may increase ISR latency).  This can be particularly true if ARB_MODE=1 and an MMIO access must wait a potentially long time behind a XIP access.</description>
30577                  <value>1</value>
30578                </enumeratedValue>
30579              </enumeratedValues>
30580            </field>
30581            <field>
30582              <name>CLOCK_IF_SEL</name>
30583              <description>Specifies the clock source for 'clk_if'.  Must be 0 (clk_hf) before entering DeepSleep; can be returned to 1 (clk_pll) afterwards.
30584'0': clk_hf is used to create clk_if
30585'1': clk_pll is used to create clk_if</description>
30586              <bitRange>[25:25]</bitRange>
30587              <access>read-write</access>
30588            </field>
30589            <field>
30590              <name>ENABLED</name>
30591              <description>IP enable:
30592'0': Disabled. All non-retention registers are reset to their default value when the IP is disabled. When the IP is disabled, the XIP accesses produce AHB-Lite bus errors and AXI error responses.
30593'1': Enabled.
30594
30595Notes:
30596- Before disabling or resetting the IP, SW should ensure that the IP is NOT busy (STATUS.BUSY is '0'), otherwise illegal interface transfers may occur.
30597- After CTL.ENABLED is set to 1 it takes up to 20 clk_if cycles until the memory interface registers are realeased from reset.</description>
30598              <bitRange>[31:31]</bitRange>
30599              <access>read-write</access>
30600              <enumeratedValues>
30601                <enumeratedValue>
30602                  <name>DISABLED</name>
30603                  <description>N/A</description>
30604                  <value>0</value>
30605                </enumeratedValue>
30606                <enumeratedValue>
30607                  <name>ENABLED</name>
30608                  <description>N/A</description>
30609                  <value>1</value>
30610                </enumeratedValue>
30611              </enumeratedValues>
30612            </field>
30613          </fields>
30614        </register>
30615        <register>
30616          <name>STATUS</name>
30617          <description>Status</description>
30618          <addressOffset>0x4</addressOffset>
30619          <size>32</size>
30620          <access>read-only</access>
30621          <resetValue>0x0</resetValue>
30622          <resetMask>0x0</resetMask>
30623          <fields>
30624            <field>
30625              <name>BUSY</name>
30626              <description>AHB Cache, AXI interface, cryptography, XIP, device interface, MPC (if present) initialization, or any other key logic busy in the IP:
30627'0': not busy
30628'1': busy
30629When BUSY is '0', the IP can be safely disabled without:
30630- the potential loss of transient write data.
30631- the potential risk of aborting an inflight SPI device interface transfer.
30632- disrupting MPC (if present) initialization
30633When BUSY is '0', the mode of operation (ARB_MODE or MMIO_MODE) can be safely changed.</description>
30634              <bitRange>[31:31]</bitRange>
30635              <access>read-only</access>
30636            </field>
30637          </fields>
30638        </register>
30639        <register>
30640          <name>TX_CMD_FIFO_STATUS</name>
30641          <description>Transmitter command FIFO status</description>
30642          <addressOffset>0x44</addressOffset>
30643          <size>32</size>
30644          <access>read-only</access>
30645          <resetValue>0x0</resetValue>
30646          <resetMask>0xF</resetMask>
30647          <fields>
30648            <field>
30649              <name>USED4</name>
30650              <description>Number of entries that are used in the TX command FIFO. Legal range: [0, 8].</description>
30651              <bitRange>[3:0]</bitRange>
30652              <access>read-only</access>
30653            </field>
30654          </fields>
30655        </register>
30656        <register>
30657          <name>TX_CMD_MMIO_FIFO_STATUS</name>
30658          <description>Transmitter command MMIO FIFO status</description>
30659          <addressOffset>0x48</addressOffset>
30660          <size>32</size>
30661          <access>read-only</access>
30662          <resetValue>0x0</resetValue>
30663          <resetMask>0xF</resetMask>
30664          <fields>
30665            <field>
30666              <name>USED4</name>
30667              <description>Number of entries that are used in the TX command MMIO FIFO. Legal range: [0, 8].</description>
30668              <bitRange>[3:0]</bitRange>
30669              <access>read-only</access>
30670            </field>
30671          </fields>
30672        </register>
30673        <register>
30674          <name>TX_CMD_MMIO_FIFO_WR</name>
30675          <description>Transmitter command MMIO FIFO write</description>
30676          <addressOffset>0x50</addressOffset>
30677          <size>32</size>
30678          <access>write-only</access>
30679          <resetValue>0x0</resetValue>
30680          <resetMask>0x7FFFFFF</resetMask>
30681          <fields>
30682            <field>
30683              <name>DATA27</name>
30684              <description>N/A</description>
30685              <bitRange>[26:0]</bitRange>
30686              <access>write-only</access>
30687            </field>
30688          </fields>
30689        </register>
30690        <register>
30691          <name>TX_DATA_MMIO_FIFO_CTL</name>
30692          <description>Transmitter data MMIO FIFO control</description>
30693          <addressOffset>0x80</addressOffset>
30694          <size>32</size>
30695          <access>read-write</access>
30696          <resetValue>0x0</resetValue>
30697          <resetMask>0x7</resetMask>
30698          <fields>
30699            <field>
30700              <name>TX_TRIGGER_LEVEL</name>
30701              <description>Determines when the TX data MMIO FIFO 'tr_tx_req' trigger is activated:
30702- Trigger is active when TX_DATA_MMIO FIFO_STATUS.USED &lt;= TRIGGER_LEVEL.</description>
30703              <bitRange>[2:0]</bitRange>
30704              <access>read-write</access>
30705            </field>
30706          </fields>
30707        </register>
30708        <register>
30709          <name>TX_DATA_FIFO_STATUS</name>
30710          <description>Transmitter data FIFO status</description>
30711          <addressOffset>0x84</addressOffset>
30712          <size>32</size>
30713          <access>read-only</access>
30714          <resetValue>0x0</resetValue>
30715          <resetMask>0xF</resetMask>
30716          <fields>
30717            <field>
30718              <name>USED4</name>
30719              <description>Number of entries that are used in the TX data FIFO. Legal range: [0, 8].</description>
30720              <bitRange>[3:0]</bitRange>
30721              <access>read-only</access>
30722            </field>
30723          </fields>
30724        </register>
30725        <register>
30726          <name>TX_DATA_MMIO_FIFO_STATUS</name>
30727          <description>Transmitter data MMIO FIFO status</description>
30728          <addressOffset>0x88</addressOffset>
30729          <size>32</size>
30730          <access>read-only</access>
30731          <resetValue>0x0</resetValue>
30732          <resetMask>0xF</resetMask>
30733          <fields>
30734            <field>
30735              <name>USED4</name>
30736              <description>Number of entries that are used in the TX data MMIO FIFO. Legal range: [0, 8].</description>
30737              <bitRange>[3:0]</bitRange>
30738              <access>read-only</access>
30739            </field>
30740          </fields>
30741        </register>
30742        <register>
30743          <name>TX_DATA_MMIO_FIFO_WR1</name>
30744          <description>Transmitter data MMIO FIFO write</description>
30745          <addressOffset>0x90</addressOffset>
30746          <size>32</size>
30747          <access>write-only</access>
30748          <resetValue>0x0</resetValue>
30749          <resetMask>0xFF</resetMask>
30750          <fields>
30751            <field>
30752              <name>DATA0</name>
30753              <description>TX data (written to TX data MMIO FIFO).</description>
30754              <bitRange>[7:0]</bitRange>
30755              <access>write-only</access>
30756            </field>
30757          </fields>
30758        </register>
30759        <register>
30760          <name>TX_DATA_MMIO_FIFO_WR2</name>
30761          <description>Transmitter data MMIO FIFO write</description>
30762          <addressOffset>0x94</addressOffset>
30763          <size>32</size>
30764          <access>write-only</access>
30765          <resetValue>0x0</resetValue>
30766          <resetMask>0xFFFF</resetMask>
30767          <fields>
30768            <field>
30769              <name>DATA0</name>
30770              <description>TX data (written to TX data MMIO FIFO, first byte).</description>
30771              <bitRange>[7:0]</bitRange>
30772              <access>write-only</access>
30773            </field>
30774            <field>
30775              <name>DATA1</name>
30776              <description>TX data (written to TX data MMIO FIFO, second byte).</description>
30777              <bitRange>[15:8]</bitRange>
30778              <access>write-only</access>
30779            </field>
30780          </fields>
30781        </register>
30782        <register>
30783          <name>TX_DATA_MMIO_FIFO_WR4</name>
30784          <description>Transmitter data MMIO FIFO write</description>
30785          <addressOffset>0x98</addressOffset>
30786          <size>32</size>
30787          <access>write-only</access>
30788          <resetValue>0x0</resetValue>
30789          <resetMask>0xFFFFFFFF</resetMask>
30790          <fields>
30791            <field>
30792              <name>DATA0</name>
30793              <description>TX data (written to TX data MMIO FIFO, first byte).</description>
30794              <bitRange>[7:0]</bitRange>
30795              <access>write-only</access>
30796            </field>
30797            <field>
30798              <name>DATA1</name>
30799              <description>TX data (written to TX data MMIO FIFO, second byte).</description>
30800              <bitRange>[15:8]</bitRange>
30801              <access>write-only</access>
30802            </field>
30803            <field>
30804              <name>DATA2</name>
30805              <description>TX data (written to TX data MMIO FIFO, third byte).</description>
30806              <bitRange>[23:16]</bitRange>
30807              <access>write-only</access>
30808            </field>
30809            <field>
30810              <name>DATA3</name>
30811              <description>TX data (written to TX data MMIO FIFO, fourth byte).</description>
30812              <bitRange>[31:24]</bitRange>
30813              <access>write-only</access>
30814            </field>
30815          </fields>
30816        </register>
30817        <register>
30818          <name>TX_DATA_MMIO_FIFO_WR1ODD</name>
30819          <description>Transmitter data MMIO FIFO write</description>
30820          <addressOffset>0x9C</addressOffset>
30821          <size>32</size>
30822          <access>write-only</access>
30823          <resetValue>0x0</resetValue>
30824          <resetMask>0xFF</resetMask>
30825          <fields>
30826            <field>
30827              <name>DATA0</name>
30828              <description>TX data (written to TX data MMIO FIFO).</description>
30829              <bitRange>[7:0]</bitRange>
30830              <access>write-only</access>
30831            </field>
30832          </fields>
30833        </register>
30834        <register>
30835          <name>RX_DATA_MMIO_FIFO_CTL</name>
30836          <description>Receiver data MMIO FIFO control</description>
30837          <addressOffset>0xC0</addressOffset>
30838          <size>32</size>
30839          <access>read-write</access>
30840          <resetValue>0x0</resetValue>
30841          <resetMask>0x7</resetMask>
30842          <fields>
30843            <field>
30844              <name>RX_TRIGGER_LEVEL</name>
30845              <description>Determines when RX data FIFO 'tr_rx_req' trigger is activated:
30846- Trigger is active when RX_DATA_MMIO_FIFO_STATUS.USED &gt; TRIGGER_LEVEL.</description>
30847              <bitRange>[2:0]</bitRange>
30848              <access>read-write</access>
30849            </field>
30850          </fields>
30851        </register>
30852        <register>
30853          <name>RX_DATA_MMIO_FIFO_STATUS</name>
30854          <description>Receiver data MMIO FIFO status</description>
30855          <addressOffset>0xC4</addressOffset>
30856          <size>32</size>
30857          <access>read-only</access>
30858          <resetValue>0x0</resetValue>
30859          <resetMask>0xF</resetMask>
30860          <fields>
30861            <field>
30862              <name>USED4</name>
30863              <description>Number of entries that are used in the RX data MMIO FIFO. Legal range: [0, 8].</description>
30864              <bitRange>[3:0]</bitRange>
30865              <access>read-only</access>
30866            </field>
30867          </fields>
30868        </register>
30869        <register>
30870          <name>RX_DATA_FIFO_STATUS</name>
30871          <description>Receiver data FIFO status</description>
30872          <addressOffset>0xC8</addressOffset>
30873          <size>32</size>
30874          <access>read-only</access>
30875          <resetValue>0x0</resetValue>
30876          <resetMask>0x10F</resetMask>
30877          <fields>
30878            <field>
30879              <name>USED4</name>
30880              <description>Number of entries that are used in the RX data FIFO. Legal range: [0, 8].</description>
30881              <bitRange>[3:0]</bitRange>
30882              <access>read-only</access>
30883            </field>
30884            <field>
30885              <name>RX_SR_USED</name>
30886              <description>Data available in RX Shift Register, i.e. completely read from RX data FIFO.</description>
30887              <bitRange>[8:8]</bitRange>
30888              <access>read-only</access>
30889            </field>
30890          </fields>
30891        </register>
30892        <register>
30893          <name>RX_DATA_MMIO_FIFO_RD1</name>
30894          <description>Receiver data MMIO FIFO read</description>
30895          <addressOffset>0xD0</addressOffset>
30896          <size>32</size>
30897          <access>read-only</access>
30898          <resetValue>0x0</resetValue>
30899          <resetMask>0xFF</resetMask>
30900          <fields>
30901            <field>
30902              <name>DATA0</name>
30903              <description>RX data (read from RX data FIFO).</description>
30904              <bitRange>[7:0]</bitRange>
30905              <access>read-only</access>
30906            </field>
30907          </fields>
30908        </register>
30909        <register>
30910          <name>RX_DATA_MMIO_FIFO_RD2</name>
30911          <description>Receiver data MMIO FIFO read</description>
30912          <addressOffset>0xD4</addressOffset>
30913          <size>32</size>
30914          <access>read-only</access>
30915          <resetValue>0x0</resetValue>
30916          <resetMask>0xFFFF</resetMask>
30917          <fields>
30918            <field>
30919              <name>DATA0</name>
30920              <description>RX data (read from RX data FIFO, first byte).</description>
30921              <bitRange>[7:0]</bitRange>
30922              <access>read-only</access>
30923            </field>
30924            <field>
30925              <name>DATA1</name>
30926              <description>RX data (read from RX data FIFO, second byte).</description>
30927              <bitRange>[15:8]</bitRange>
30928              <access>read-only</access>
30929            </field>
30930          </fields>
30931        </register>
30932        <register>
30933          <name>RX_DATA_MMIO_FIFO_RD4</name>
30934          <description>Receiver data MMIO FIFO read</description>
30935          <addressOffset>0xD8</addressOffset>
30936          <size>32</size>
30937          <access>read-only</access>
30938          <resetValue>0x0</resetValue>
30939          <resetMask>0xFFFFFFFF</resetMask>
30940          <fields>
30941            <field>
30942              <name>DATA0</name>
30943              <description>RX data (read from RX data FIFO, first byte).</description>
30944              <bitRange>[7:0]</bitRange>
30945              <access>read-only</access>
30946            </field>
30947            <field>
30948              <name>DATA1</name>
30949              <description>RX data (read from RX data FIFO, second byte).</description>
30950              <bitRange>[15:8]</bitRange>
30951              <access>read-only</access>
30952            </field>
30953            <field>
30954              <name>DATA2</name>
30955              <description>RX data (read from RX data FIFO, third byte).</description>
30956              <bitRange>[23:16]</bitRange>
30957              <access>read-only</access>
30958            </field>
30959            <field>
30960              <name>DATA3</name>
30961              <description>RX data (read from RX data FIFO, fourth byte).</description>
30962              <bitRange>[31:24]</bitRange>
30963              <access>read-only</access>
30964            </field>
30965          </fields>
30966        </register>
30967        <register>
30968          <name>RX_DATA_MMIO_FIFO_RD1_SILENT</name>
30969          <description>Receiver data MMIO FIFO silent read</description>
30970          <addressOffset>0xE0</addressOffset>
30971          <size>32</size>
30972          <access>read-only</access>
30973          <resetValue>0x0</resetValue>
30974          <resetMask>0xFF</resetMask>
30975          <fields>
30976            <field>
30977              <name>DATA0</name>
30978              <description>RX data (read from RX data FIFO).</description>
30979              <bitRange>[7:0]</bitRange>
30980              <access>read-only</access>
30981            </field>
30982          </fields>
30983        </register>
30984        <cluster>
30985          <name>SMIF_CRYPTO</name>
30986          <description>Cryptography registers (one set for each key)</description>
30987          <addressOffset>0x00000200</addressOffset>
30988          <register>
30989            <name>CRYPTO_CMD</name>
30990            <description>Cryptography command</description>
30991            <addressOffset>0x0</addressOffset>
30992            <size>32</size>
30993            <access>read-write</access>
30994            <resetValue>0x0</resetValue>
30995            <resetMask>0x1</resetMask>
30996            <fields>
30997              <field>
30998                <name>START</name>
30999                <description>SW sets this field to '1' to start an AES-128 forward block cipher operation (on CRYPTO_INPUT0-3). HW sets this field to '0' to indicate that the operation has completed. Once completed, the result of the operation can be read from CRYPTO_OUTPUT0, ..., CRYPTO_OUTPUT3.
31000
31001The operation takes roughly 13 clk_mem clock cycles.
31002
31003This register is only applicable for MMIO accesses and only in MMIO_MODE.  XIP accesses are encrypted on-the-fly in ARB_MODE and thus do not use this register.  Because XIP has exclusive access to the crypto engine in ARB_MODE, MMIO encryption is not available in that mode.  As such if encryption is needed for MMIO accesses in ARB_MODE that encryption must be done by other means (i.e., chip level crypto).</description>
31004                <bitRange>[0:0]</bitRange>
31005                <access>read-write</access>
31006              </field>
31007            </fields>
31008          </register>
31009          <register>
31010            <name>CRYPTO_ADDR</name>
31011            <description>Cryptography base address</description>
31012            <addressOffset>0x4</addressOffset>
31013            <size>32</size>
31014            <access>read-write</access>
31015            <resetValue>0x0</resetValue>
31016            <resetMask>0xFFFFFF00</resetMask>
31017            <fields>
31018              <field>
31019                <name>ADDR</name>
31020                <description>Only applies to XIP accesses.
31021
31022Specifies the base address of the memory region that will have cryptography applied on XIP accesses with a unique key. If this region overlaps with another key's region, the lower numbered key is used (i.e., crypto key 0 has the highest priority).  If the region is 2^m Bytes, ADDR MUST be a multiple of 2^m.
31023
31024The most significant bit fields are constants and set based on the SMIF_XIP_ADDR parameter. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), ADDR[31:24] = SMIF_XIP_ADDR[31:24].
31025
31026Note that in order for cryptogrpahy to be applied the DEVICE.CTL.CRYPTO_EN must be set to 1 as well for any devices that share this region.</description>
31027                <bitRange>[31:8]</bitRange>
31028                <access>read-write</access>
31029              </field>
31030            </fields>
31031          </register>
31032          <register>
31033            <name>CRYPTO_MASK</name>
31034            <description>Cryptography mask</description>
31035            <addressOffset>0x8</addressOffset>
31036            <size>32</size>
31037            <access>read-write</access>
31038            <resetValue>0x0</resetValue>
31039            <resetMask>0xFFFFFF00</resetMask>
31040            <fields>
31041              <field>
31042                <name>MASK</name>
31043                <description>Only applies to XIP accesses.
31044
31045Specifies the size of the memory region whose base address is determined by CRYPTO_ADDR. All '1' bits are used to compare the incoming transfer request address A[31:0] with the address as specified in CRYPTO_ADDR.ADDR: Address A is in the cryptography region when (A[31:8] &amp; MASK[31:8]) == CRYPTO_ADDR.ADDR[31:8].
31046
31047The most significant bit fields are constants and set to'1'. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK  is 0xff00:0000 (16 MB XIP memory region), MASK[31:24] = 0xff.</description>
31048                <bitRange>[31:8]</bitRange>
31049                <access>read-write</access>
31050              </field>
31051            </fields>
31052          </register>
31053          <register>
31054            <name>CRYPTO_SUBREGION</name>
31055            <description>Cryptography subregion disable</description>
31056            <addressOffset>0xC</addressOffset>
31057            <size>32</size>
31058            <access>read-write</access>
31059            <resetValue>0x0</resetValue>
31060            <resetMask>0xFF</resetMask>
31061            <fields>
31062              <field>
31063                <name>SUBREGION_DISABLE</name>
31064                <description>Only applies to XIP accesses.
31065
31066The cryptography region for this key as determined by CRYPTO_ADDR and CRYPTO_MASK is further divided into 8 equal subregions.  e.g., if a 1 MB region is specified then the 8 subregions will be 128 KB.  If SUBREGION_DISABLE=0 then cryptography will be performed on that subregion (assuming any associated DEVICE.CTL.CRYPTO_EN=1).  Otherwise if SUBREGION_DISABLE=1 then cryptography is not applied.  Note that setting all SUBREGION_DISABLE bits to 1 will effectively disable this key.
31067
31068The encryption decision and the associated key are locked in at the beginning of a memory access and will apply until the end of such atomic accesses. Therefore, it is the user's responsibility to ensure memory accesses do not span across (sub)regions that have different keys and/or cypto enabled/disabled differently across such (sub)regions.</description>
31069                <bitRange>[7:0]</bitRange>
31070                <access>read-write</access>
31071              </field>
31072            </fields>
31073          </register>
31074          <register>
31075            <name>CRYPTO_INPUT0</name>
31076            <description>Cryptography input 0</description>
31077            <addressOffset>0x20</addressOffset>
31078            <size>32</size>
31079            <access>read-write</access>
31080            <resetValue>0x0</resetValue>
31081            <resetMask>0x0</resetMask>
31082            <fields>
31083              <field>
31084                <name>INPUT_LSB</name>
31085                <description>Plaintext PT[3:0] = CRYPTO_INPUT0.INPUT_LSB.</description>
31086                <bitRange>[3:0]</bitRange>
31087                <access>read-write</access>
31088              </field>
31089              <field>
31090                <name>INPUT_MSB</name>
31091                <description>Plaintext PT[31:4] = CRYPTO_INPUT0.INPUT_MSB.</description>
31092                <bitRange>[31:4]</bitRange>
31093                <access>read-write</access>
31094              </field>
31095            </fields>
31096          </register>
31097          <register>
31098            <name>CRYPTO_INPUT1</name>
31099            <description>Cryptography input 1</description>
31100            <addressOffset>0x24</addressOffset>
31101            <size>32</size>
31102            <access>read-write</access>
31103            <resetValue>0x0</resetValue>
31104            <resetMask>0x0</resetMask>
31105            <fields>
31106              <field>
31107                <name>INPUT</name>
31108                <description>Plaintext PT[63:32] = CRYPTO_INPUT1.INPUT[31:0].</description>
31109                <bitRange>[31:0]</bitRange>
31110                <access>read-write</access>
31111              </field>
31112            </fields>
31113          </register>
31114          <register>
31115            <name>CRYPTO_INPUT2</name>
31116            <description>Cryptography input 2</description>
31117            <addressOffset>0x28</addressOffset>
31118            <size>32</size>
31119            <access>read-write</access>
31120            <resetValue>0x0</resetValue>
31121            <resetMask>0x0</resetMask>
31122            <fields>
31123              <field>
31124                <name>INPUT</name>
31125                <description>Plaintext PT[95:64] = CRYPTO_INPUT2.INPUT[31:0].</description>
31126                <bitRange>[31:0]</bitRange>
31127                <access>read-write</access>
31128              </field>
31129            </fields>
31130          </register>
31131          <register>
31132            <name>CRYPTO_INPUT3</name>
31133            <description>Cryptography input 3</description>
31134            <addressOffset>0x2C</addressOffset>
31135            <size>32</size>
31136            <access>read-write</access>
31137            <resetValue>0x0</resetValue>
31138            <resetMask>0x0</resetMask>
31139            <fields>
31140              <field>
31141                <name>INPUT</name>
31142                <description>Plaintext PT[127:96] = CRYPTO_INPUT3.INPUT[31:0].</description>
31143                <bitRange>[31:0]</bitRange>
31144                <access>read-write</access>
31145              </field>
31146            </fields>
31147          </register>
31148          <register>
31149            <name>CRYPTO_KEY0</name>
31150            <description>Cryptography key 0</description>
31151            <addressOffset>0x40</addressOffset>
31152            <size>32</size>
31153            <access>write-only</access>
31154            <resetValue>0x0</resetValue>
31155            <resetMask>0x0</resetMask>
31156            <fields>
31157              <field>
31158                <name>KEY</name>
31159                <description>Four Bytes of the key KEY[31:0] = CRYPTO_KEY0.KEY[31:0].</description>
31160                <bitRange>[31:0]</bitRange>
31161                <access>write-only</access>
31162              </field>
31163            </fields>
31164          </register>
31165          <register>
31166            <name>CRYPTO_KEY1</name>
31167            <description>Cryptography key 1</description>
31168            <addressOffset>0x44</addressOffset>
31169            <size>32</size>
31170            <access>write-only</access>
31171            <resetValue>0x0</resetValue>
31172            <resetMask>0x0</resetMask>
31173            <fields>
31174              <field>
31175                <name>KEY</name>
31176                <description>Four Bytes of the key KEY[63:32] = CRYPTO_KEY1.KEY[31:0].</description>
31177                <bitRange>[31:0]</bitRange>
31178                <access>write-only</access>
31179              </field>
31180            </fields>
31181          </register>
31182          <register>
31183            <name>CRYPTO_KEY2</name>
31184            <description>Cryptography key 2</description>
31185            <addressOffset>0x48</addressOffset>
31186            <size>32</size>
31187            <access>write-only</access>
31188            <resetValue>0x0</resetValue>
31189            <resetMask>0x0</resetMask>
31190            <fields>
31191              <field>
31192                <name>KEY</name>
31193                <description>Four Bytes of the key KEY[95:64] = CRYPTO_KEY2.KEY[31:0].</description>
31194                <bitRange>[31:0]</bitRange>
31195                <access>write-only</access>
31196              </field>
31197            </fields>
31198          </register>
31199          <register>
31200            <name>CRYPTO_KEY3</name>
31201            <description>Cryptography key 3</description>
31202            <addressOffset>0x4C</addressOffset>
31203            <size>32</size>
31204            <access>write-only</access>
31205            <resetValue>0x0</resetValue>
31206            <resetMask>0x0</resetMask>
31207            <fields>
31208              <field>
31209                <name>KEY</name>
31210                <description>Four Bytes of the key KEY[127:96] = CRYPTO_KEY3.KEY[31:0].</description>
31211                <bitRange>[31:0]</bitRange>
31212                <access>write-only</access>
31213              </field>
31214            </fields>
31215          </register>
31216          <register>
31217            <name>CRYPTO_OUTPUT0</name>
31218            <description>Cryptography output 0</description>
31219            <addressOffset>0x60</addressOffset>
31220            <size>32</size>
31221            <access>read-write</access>
31222            <resetValue>0x0</resetValue>
31223            <resetMask>0x0</resetMask>
31224            <fields>
31225              <field>
31226                <name>OUTPUT</name>
31227                <description>Four Bytes of the ciphertext CT[31:0] = CRYPTO_OUTPUT0.OUTPUT[31:0].</description>
31228                <bitRange>[31:0]</bitRange>
31229                <access>read-write</access>
31230              </field>
31231            </fields>
31232          </register>
31233          <register>
31234            <name>CRYPTO_OUTPUT1</name>
31235            <description>Cryptography output 1</description>
31236            <addressOffset>0x64</addressOffset>
31237            <size>32</size>
31238            <access>read-write</access>
31239            <resetValue>0x0</resetValue>
31240            <resetMask>0x0</resetMask>
31241            <fields>
31242              <field>
31243                <name>OUTPUT</name>
31244                <description>Four Bytes of the ciphertext CT[63:32] = CRYPTO_OUTPUT1.OUTPUT[31:0].</description>
31245                <bitRange>[31:0]</bitRange>
31246                <access>read-write</access>
31247              </field>
31248            </fields>
31249          </register>
31250          <register>
31251            <name>CRYPTO_OUTPUT2</name>
31252            <description>Cryptography output 2</description>
31253            <addressOffset>0x68</addressOffset>
31254            <size>32</size>
31255            <access>read-write</access>
31256            <resetValue>0x0</resetValue>
31257            <resetMask>0x0</resetMask>
31258            <fields>
31259              <field>
31260                <name>OUTPUT</name>
31261                <description>Four Bytes of the ciphertext CT[95:64] = CRYPTO_OUTPUT2.OUTPUT[31:0].</description>
31262                <bitRange>[31:0]</bitRange>
31263                <access>read-write</access>
31264              </field>
31265            </fields>
31266          </register>
31267          <register>
31268            <name>CRYPTO_OUTPUT3</name>
31269            <description>Cryptography output 3</description>
31270            <addressOffset>0x6C</addressOffset>
31271            <size>32</size>
31272            <access>read-write</access>
31273            <resetValue>0x0</resetValue>
31274            <resetMask>0x0</resetMask>
31275            <fields>
31276              <field>
31277                <name>OUTPUT</name>
31278                <description>Four Bytes of the ciphertext CT[127:96] = CRYPTO_OUTPUT3.OUTPUT[31:0].</description>
31279                <bitRange>[31:0]</bitRange>
31280                <access>read-write</access>
31281              </field>
31282            </fields>
31283          </register>
31284        </cluster>
31285        <register>
31286          <name>INTR</name>
31287          <description>Interrupt register</description>
31288          <addressOffset>0x7C0</addressOffset>
31289          <size>32</size>
31290          <access>read-write</access>
31291          <resetValue>0x0</resetValue>
31292          <resetMask>0x3113F</resetMask>
31293          <fields>
31294            <field>
31295              <name>TR_TX_REQ</name>
31296              <description>Activated when a TX data MMIO FIFO trigger 'tr_tx_req' is activated.</description>
31297              <bitRange>[0:0]</bitRange>
31298              <access>read-write</access>
31299            </field>
31300            <field>
31301              <name>TR_RX_REQ</name>
31302              <description>Activated when a RX data MMIO FIFO trigger 'tr_rx_req' is activated.</description>
31303              <bitRange>[1:1]</bitRange>
31304              <access>read-write</access>
31305            </field>
31306            <field>
31307              <name>XIP_ALIGNMENT_ERROR</name>
31308              <description>Activated on a XIP access, when:
31309- a write transfer is requested
31310and
31311- Dual-Quad SPI mode (selected device's ADDR_CTL.DIV2 is '1') is selected or
31312- Octal SPI DDR mode (selected device's DATA_CTL.DDR_MODE = '1' and DATA_CTL.WIDTH = '3') or Hyperbus mode (selected device's ADDR_CTL.SIZE3 = '7') is selected without memory write byte masking (selected device's WR_DUMMY_CTL.RWDS_EN = '0')
31313and
31314- the AHB-Lite / AXI bus transfer address is not a multiple of '2' or
31315- the requested AHB-Lite / AXI bus transfer size is NOT a multiple of '2'.
31316
31317Additionally, it is activated on a XIP access when the selected memory device does not support write byte masking (WR_DUMMY_CTL.RWDS_EN=0) and an AXI transfer occurs with not all of the AXI write strobes ('wstrb') enabled according to the transfer size ('assize').
31318
31319Note: In dual-quad SPI mode (ADDR_CTL.DIV is '1'), each memory device contributes a 4-bit nibble for read data or write data. Write accesses are only possible if the request address is a multiple of 2 and the number of requested Bytes is a multiple of 2. Octal SPI DDR mode or Hyperbus mode are 16-bit word based protocols, writing single bytes is only possible when write byte masking is supported (via RWDS). Read accesses are always possible by extending the transfer size and / or aligning the address as needed and discarding the non-relevant byte(s).</description>
31320              <bitRange>[2:2]</bitRange>
31321              <access>read-write</access>
31322            </field>
31323            <field>
31324              <name>TX_CMD_FIFO_OVERFLOW</name>
31325              <description>Activated on an AHB-Lite write transfer to the TX command MMIO FIFO (TX_CMD_MMIO_FIFO_WR) with not enough free entries available.</description>
31326              <bitRange>[3:3]</bitRange>
31327              <access>read-write</access>
31328            </field>
31329            <field>
31330              <name>TX_DATA_FIFO_OVERFLOW</name>
31331              <description>Activated on an AHB-Lite write transfer to the TX data MMIO FIFO (TX_DATA_MMIO_FIFO_WR1, TX_DATA_MMIO_FIFO_WR2, TX_DATA_MMIO_FIFO_WR4, TX_DATA_MMIO_FIFO_WR1ODD) with not enough free entries available.</description>
31332              <bitRange>[4:4]</bitRange>
31333              <access>read-write</access>
31334            </field>
31335            <field>
31336              <name>RX_DATA_MMIO_FIFO_UNDERFLOW</name>
31337              <description>Activated on an AHB-Lite read transfer from the RX data MMIO FIFO (RX_DATA_MMIO_FIFO_RD1, RX_DATA_MMIO_FIFO_RD2, RX_DATA_MMIO_FIFO_RD4) with not enough entries available. Only activated for NON test bus controller transfers.</description>
31338              <bitRange>[5:5]</bitRange>
31339              <access>read-write</access>
31340            </field>
31341            <field>
31342              <name>DL_FAIL</name>
31343              <description>Data Learning Failed (no DLP match found on at least one of the input data lines when CTL.INT_CLOCK_DL_ENABLED = 1).</description>
31344              <bitRange>[8:8]</bitRange>
31345              <access>read-write</access>
31346            </field>
31347            <field>
31348              <name>DL_WARNING</name>
31349              <description>Data Learning Warning (for at least one input data line less then DLP.DL_WARNING_LEVEL delay line taps resulted in a correct DLP capturing when CTL.INT_CLOCK_DL_ENABLED = 1).  This interrupt will be suppressed, though, if DL_FAIL also occurs during the same DLP evaluation cycle.</description>
31350              <bitRange>[12:12]</bitRange>
31351              <access>read-write</access>
31352            </field>
31353            <field>
31354              <name>CRC_ERROR</name>
31355              <description>CRC Error. A read transfer data CRC check failed.</description>
31356              <bitRange>[16:16]</bitRange>
31357              <access>read-write</access>
31358            </field>
31359            <field>
31360              <name>FS_STATUS_ERROR</name>
31361              <description>Functional Safety Status Error. A read transfer Functional Safety Status check failed (see definition in DEVICE_ver2.RD_CRC_CTL.STATUS_CHECK_MASK and DEVICE_ver2.RD_CRC_CTL.STATUS_CHECK_MASK_POL).</description>
31362              <bitRange>[17:17]</bitRange>
31363              <access>read-write</access>
31364            </field>
31365          </fields>
31366        </register>
31367        <register>
31368          <name>INTR_SET</name>
31369          <description>Interrupt set register</description>
31370          <addressOffset>0x7C4</addressOffset>
31371          <size>32</size>
31372          <access>read-write</access>
31373          <resetValue>0x0</resetValue>
31374          <resetMask>0x3113F</resetMask>
31375          <fields>
31376            <field>
31377              <name>TR_TX_REQ</name>
31378              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
31379              <bitRange>[0:0]</bitRange>
31380              <access>read-write</access>
31381            </field>
31382            <field>
31383              <name>TR_RX_REQ</name>
31384              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
31385              <bitRange>[1:1]</bitRange>
31386              <access>read-write</access>
31387            </field>
31388            <field>
31389              <name>XIP_ALIGNMENT_ERROR</name>
31390              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
31391              <bitRange>[2:2]</bitRange>
31392              <access>read-write</access>
31393            </field>
31394            <field>
31395              <name>TX_CMD_FIFO_OVERFLOW</name>
31396              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
31397              <bitRange>[3:3]</bitRange>
31398              <access>read-write</access>
31399            </field>
31400            <field>
31401              <name>TX_DATA_FIFO_OVERFLOW</name>
31402              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
31403              <bitRange>[4:4]</bitRange>
31404              <access>read-write</access>
31405            </field>
31406            <field>
31407              <name>RX_DATA_MMIO_FIFO_UNDERFLOW</name>
31408              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
31409              <bitRange>[5:5]</bitRange>
31410              <access>read-write</access>
31411            </field>
31412            <field>
31413              <name>DL_FAIL</name>
31414              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
31415              <bitRange>[8:8]</bitRange>
31416              <access>read-write</access>
31417            </field>
31418            <field>
31419              <name>DL_WARNING</name>
31420              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
31421              <bitRange>[12:12]</bitRange>
31422              <access>read-write</access>
31423            </field>
31424            <field>
31425              <name>CRC_ERROR</name>
31426              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
31427              <bitRange>[16:16]</bitRange>
31428              <access>read-write</access>
31429            </field>
31430            <field>
31431              <name>FS_STATUS_ERROR</name>
31432              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
31433              <bitRange>[17:17]</bitRange>
31434              <access>read-write</access>
31435            </field>
31436          </fields>
31437        </register>
31438        <register>
31439          <name>INTR_MASK</name>
31440          <description>Interrupt mask register</description>
31441          <addressOffset>0x7C8</addressOffset>
31442          <size>32</size>
31443          <access>read-write</access>
31444          <resetValue>0x0</resetValue>
31445          <resetMask>0x3113F</resetMask>
31446          <fields>
31447            <field>
31448              <name>TR_TX_REQ</name>
31449              <description>Mask bit for corresponding bit in interrupt request register.</description>
31450              <bitRange>[0:0]</bitRange>
31451              <access>read-write</access>
31452            </field>
31453            <field>
31454              <name>TR_RX_REQ</name>
31455              <description>Mask bit for corresponding bit in interrupt request register.</description>
31456              <bitRange>[1:1]</bitRange>
31457              <access>read-write</access>
31458            </field>
31459            <field>
31460              <name>XIP_ALIGNMENT_ERROR</name>
31461              <description>Mask bit for corresponding bit in interrupt request register.</description>
31462              <bitRange>[2:2]</bitRange>
31463              <access>read-write</access>
31464            </field>
31465            <field>
31466              <name>TX_CMD_FIFO_OVERFLOW</name>
31467              <description>Mask bit for corresponding bit in interrupt request register.</description>
31468              <bitRange>[3:3]</bitRange>
31469              <access>read-write</access>
31470            </field>
31471            <field>
31472              <name>TX_DATA_FIFO_OVERFLOW</name>
31473              <description>Mask bit for corresponding bit in interrupt request register.</description>
31474              <bitRange>[4:4]</bitRange>
31475              <access>read-write</access>
31476            </field>
31477            <field>
31478              <name>RX_DATA_MMIO_FIFO_UNDERFLOW</name>
31479              <description>Mask bit for corresponding bit in interrupt request register.</description>
31480              <bitRange>[5:5]</bitRange>
31481              <access>read-write</access>
31482            </field>
31483            <field>
31484              <name>DL_FAIL</name>
31485              <description>Mask bit for corresponding bit in interrupt request register.</description>
31486              <bitRange>[8:8]</bitRange>
31487              <access>read-write</access>
31488            </field>
31489            <field>
31490              <name>DL_WARNING</name>
31491              <description>Mask bit for corresponding bit in interrupt request register.</description>
31492              <bitRange>[12:12]</bitRange>
31493              <access>read-write</access>
31494            </field>
31495            <field>
31496              <name>CRC_ERROR</name>
31497              <description>Mask bit for corresponding bit in interrupt request register.</description>
31498              <bitRange>[16:16]</bitRange>
31499              <access>read-write</access>
31500            </field>
31501            <field>
31502              <name>FS_STATUS_ERROR</name>
31503              <description>Mask bit for corresponding bit in interrupt request register.</description>
31504              <bitRange>[17:17]</bitRange>
31505              <access>read-write</access>
31506            </field>
31507          </fields>
31508        </register>
31509        <register>
31510          <name>INTR_MASKED</name>
31511          <description>Interrupt masked register</description>
31512          <addressOffset>0x7CC</addressOffset>
31513          <size>32</size>
31514          <access>read-only</access>
31515          <resetValue>0x0</resetValue>
31516          <resetMask>0x3113F</resetMask>
31517          <fields>
31518            <field>
31519              <name>TR_TX_REQ</name>
31520              <description>Logical and of corresponding request and mask bits.</description>
31521              <bitRange>[0:0]</bitRange>
31522              <access>read-only</access>
31523            </field>
31524            <field>
31525              <name>TR_RX_REQ</name>
31526              <description>Logical and of corresponding request and mask bits.</description>
31527              <bitRange>[1:1]</bitRange>
31528              <access>read-only</access>
31529            </field>
31530            <field>
31531              <name>XIP_ALIGNMENT_ERROR</name>
31532              <description>Logical and of corresponding request and mask bits.</description>
31533              <bitRange>[2:2]</bitRange>
31534              <access>read-only</access>
31535            </field>
31536            <field>
31537              <name>TX_CMD_FIFO_OVERFLOW</name>
31538              <description>Logical and of corresponding request and mask bits.</description>
31539              <bitRange>[3:3]</bitRange>
31540              <access>read-only</access>
31541            </field>
31542            <field>
31543              <name>TX_DATA_FIFO_OVERFLOW</name>
31544              <description>Logical and of corresponding request and mask bits.</description>
31545              <bitRange>[4:4]</bitRange>
31546              <access>read-only</access>
31547            </field>
31548            <field>
31549              <name>RX_DATA_MMIO_FIFO_UNDERFLOW</name>
31550              <description>Logical and of corresponding request and mask bits.</description>
31551              <bitRange>[5:5]</bitRange>
31552              <access>read-only</access>
31553            </field>
31554            <field>
31555              <name>DL_FAIL</name>
31556              <description>Logical and of corresponding request and mask bits.</description>
31557              <bitRange>[8:8]</bitRange>
31558              <access>read-only</access>
31559            </field>
31560            <field>
31561              <name>DL_WARNING</name>
31562              <description>Logical and of corresponding request and mask bits.</description>
31563              <bitRange>[12:12]</bitRange>
31564              <access>read-only</access>
31565            </field>
31566            <field>
31567              <name>CRC_ERROR</name>
31568              <description>Logical and of corresponding request and mask bits.</description>
31569              <bitRange>[16:16]</bitRange>
31570              <access>read-only</access>
31571            </field>
31572            <field>
31573              <name>FS_STATUS_ERROR</name>
31574              <description>Logical and of corresponding request and mask bits.</description>
31575              <bitRange>[17:17]</bitRange>
31576              <access>read-only</access>
31577            </field>
31578          </fields>
31579        </register>
31580        <register>
31581          <name>INTR_CAUSE</name>
31582          <description>Distinguishes normal vs. MPC interrupt</description>
31583          <addressOffset>0x7D0</addressOffset>
31584          <size>32</size>
31585          <access>read-only</access>
31586          <resetValue>0x0</resetValue>
31587          <resetMask>0x3</resetMask>
31588          <fields>
31589            <field>
31590              <name>NORMAL</name>
31591              <description>Reflects the state of interrupt_normal (which is the OR of the elements in the normal INTR_MASKED)</description>
31592              <bitRange>[0:0]</bitRange>
31593              <access>read-only</access>
31594            </field>
31595            <field>
31596              <name>MPC</name>
31597              <description>Reflects the state of interrupt_mpc (which is the OR of the elements in the MPC'S INTR_MASKED)</description>
31598              <bitRange>[1:1]</bitRange>
31599              <access>read-only</access>
31600            </field>
31601          </fields>
31602        </register>
31603        <cluster>
31604          <dim>2</dim>
31605          <dimIncrement>128</dimIncrement>
31606          <name>DEVICE[%s]</name>
31607          <description>Device (only used for XIP acceses)</description>
31608          <addressOffset>0x00000800</addressOffset>
31609          <register>
31610            <name>CTL</name>
31611            <description>Control</description>
31612            <addressOffset>0x0</addressOffset>
31613            <size>32</size>
31614            <access>read-write</access>
31615            <resetValue>0x0</resetValue>
31616            <resetMask>0xFFFFF311</resetMask>
31617            <fields>
31618              <field>
31619                <name>WR_EN</name>
31620                <description>Write enable:
31621'0': write transfers are not allowed to this device. An attempt to write to this device results in an AHB-Lite bus error.
31622'1': write transfers are allowed to this device.</description>
31623                <bitRange>[0:0]</bitRange>
31624                <access>read-write</access>
31625              </field>
31626              <field>
31627                <name>CRYPTO_EN</name>
31628                <description>Cryptography on read/write accesses:
31629'0': disabled.
31630'1': enabled.</description>
31631                <bitRange>[4:4]</bitRange>
31632                <access>read-write</access>
31633              </field>
31634              <field>
31635                <name>DATA_SEL</name>
31636                <description>Specifies the connection of the IP's data lines (spi_data[0], ..., spi_data[7]) to the device's data lines (SI/IO0, SO/IO1, IO2, IO3, IO4, IO5, IO6, IO7):
31637'0': spi_data[0] = IO0, spi_data[1] = IO1, ..., spi_data[7] = IO7. This value is allowed for single, dual, quad, dual quad and octal SPI modes. This value must be used for the first device in dual quad SPI mode. This value must be used for octal SPI mode.
31638'1': spi_data[2] = IO0, spi_data[3] = IO1. This value is only allowed for single and dual SPI modes.
31639'2': spi_data[4] = IO0, spi_data[5] = IO1, ..., spi_data[7] = IO3. This value is only allowed for single, dual, quad and dual quad  SPI modes. In dual quad SPI mode, this value must be used for the second device.
31640'3': spi_data[6] = IO0, spi_data[7] = IO1. This value is only allowed for single and dual SPI modes.</description>
31641                <bitRange>[9:8]</bitRange>
31642                <access>read-write</access>
31643              </field>
31644              <field>
31645                <name>MERGE_TIMEOUT</name>
31646                <description>Continuous transfer merge timeout in clk_mem cycles. This limits the standby time of the memory interface, i.e. the time the memory device is selected but no data is transferred.
31647The counting of the merge timeout period is done in the XIP block using clk_mem cycles. It starts when the last TX or RX byte is transferred to or from the data FIFOs.
31648After this period the memory device is deselected. A later transfer, even from a continuous address, starts with the overhead phases (command, address, mode, dummy cycles).</description>
31649                <bitRange>[14:12]</bitRange>
31650                <access>read-write</access>
31651                <enumeratedValues>
31652                  <enumeratedValue>
31653                    <name>_1_cycle</name>
31654                    <description>Timeout after 1 clk_mem cycle.
31655That means transfers will only be merged if the continuous transfer request is already available when the previous transfer is finished.</description>
31656                    <value>0</value>
31657                  </enumeratedValue>
31658                  <enumeratedValue>
31659                    <name>_16_cycles</name>
31660                    <description>Timeout after 2^4 = 16 clk_mem cycles.
31661At a clk_mem frequency of 200MHz this means 80ns.</description>
31662                    <value>1</value>
31663                  </enumeratedValue>
31664                  <enumeratedValue>
31665                    <name>_256_cycles</name>
31666                    <description>Timeout after 2^8 = 256 clk_mem cycles.
31667At a clk_mem frequency of 200MHz this means ~1.3us.</description>
31668                    <value>2</value>
31669                  </enumeratedValue>
31670                  <enumeratedValue>
31671                    <name>_4096_cycles</name>
31672                    <description>Timeout after 2^12 = 4096 clk_mem cycles.
31673At a clk_mem frequency of 200MHz this means ~20us.</description>
31674                    <value>3</value>
31675                  </enumeratedValue>
31676                  <enumeratedValue>
31677                    <name>_65536_cycles</name>
31678                    <description>Timeout after 2^16 = 65536 clk_mem cycles.
31679At a clk_mem frequency of 200MHz this means ~330us.</description>
31680                    <value>4</value>
31681                  </enumeratedValue>
31682                  <enumeratedValue>
31683                    <name>RSVD5</name>
31684                    <description>N/A</description>
31685                    <value>5</value>
31686                  </enumeratedValue>
31687                  <enumeratedValue>
31688                    <name>RSVD6</name>
31689                    <description>N/A</description>
31690                    <value>6</value>
31691                  </enumeratedValue>
31692                  <enumeratedValue>
31693                    <name>RSVD7</name>
31694                    <description>N/A</description>
31695                    <value>7</value>
31696                  </enumeratedValue>
31697                </enumeratedValues>
31698              </field>
31699              <field>
31700                <name>MERGE_EN</name>
31701                <description>Continous transfer merge enable:
31702'0': Disabled. No merging of transfers is done. Longest possible memory transfer is 16 Byte.
31703'1': Enabled. Merging of continous transfers is done. This skips the overhead (command, address, mode, dummy cycles) for a continuous (linear sequential) transfer.</description>
31704                <bitRange>[15:15]</bitRange>
31705                <access>read-write</access>
31706              </field>
31707              <field>
31708                <name>TOTAL_TIMEOUT</name>
31709                <description>Total transfer timeout in clk_mem cycles.
31710The counting of the total timout period is done in the XIP block using clk_mem cycles. It starts when the first command of a new (not merged) transaction is transferred to the TX command FIFO causing the interface logic to select the memory.
31711After this period the memory device is deselected.
31712
31713This feature is needed for RAM devices requiring refresh cycles. The value needs to be derived from the RAMs maximum transaction length time (tCMS) minus the time of transferring 2x16byte data block (data granularity of the XIP ports is 16byte, 1 16byte block transfer outstanding, another available for merging). If the result in negative, MERGE_EN must be set to '0'.
31714
31715Example: RAM device tCMS = 4us, interface clock frequency = 100MHz: total transfer timeout is 4us - 2x16x10ns = 3680ns.
31716With clk_mem frequency of 200MHz the TOTAL_TIMEOUT value is 3680/5 = 736.
31717
31718Note: In the unlikely case that the total transfer timeout is used (usually for RAM devices) while the page boundary crossing latency generation is enabled via RD_BOUND_CTL.PRESENT (usually for FLASH devices) the additional time needs to taken into account.</description>
31719                <bitRange>[29:16]</bitRange>
31720                <access>read-write</access>
31721              </field>
31722              <field>
31723                <name>TOTAL_TIMEOUT_EN</name>
31724                <description>Total transfer timeout enable.
31725'0': Disabled. There is no limit for the total transfer time. The continuous transfer merge timeout for limiting the idle time of the memory interface still applies.
31726'1': Enabled. The maximum total transfer time is limited by field TOTAL_TIMEOUT.</description>
31727                <bitRange>[30:30]</bitRange>
31728                <access>read-write</access>
31729              </field>
31730              <field>
31731                <name>ENABLED</name>
31732                <description>Device enable:
31733'0': Disabled.
31734'1': Enabled.</description>
31735                <bitRange>[31:31]</bitRange>
31736                <access>read-write</access>
31737              </field>
31738            </fields>
31739          </register>
31740          <register>
31741            <name>ADDR</name>
31742            <description>Device region base address</description>
31743            <addressOffset>0x8</addressOffset>
31744            <size>32</size>
31745            <access>read-write</access>
31746            <resetValue>0x0</resetValue>
31747            <resetMask>0x0</resetMask>
31748            <fields>
31749              <field>
31750                <name>ADDR</name>
31751                <description>Specifies the base address of the device region. If the device region is 2^m Bytes, ADDR MUST be a multiple of 2^m.
31752
31753In dual quad SPI data transfer, the two devices should have the same ADDR and MASK register settings. The device control information (ADDR_CTL, RD_CMD_CTL, etc.) are provided by the MMIO control registers of the device with the lowest index.
31754
31755The most significant bit fields are constants and set based on the SMIF_XIP_ADDR parameter. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), ADDR[31:24] = SMIF_XIP_ADDR[31:24].</description>
31756                <bitRange>[31:8]</bitRange>
31757                <access>read-write</access>
31758              </field>
31759            </fields>
31760          </register>
31761          <register>
31762            <name>MASK</name>
31763            <description>Device region mask</description>
31764            <addressOffset>0xC</addressOffset>
31765            <size>32</size>
31766            <access>read-write</access>
31767            <resetValue>0x0</resetValue>
31768            <resetMask>0x0</resetMask>
31769            <fields>
31770              <field>
31771                <name>MASK</name>
31772                <description>Specifies the size of the device region. All '1' bits are used to compare the incoming transfer request address A[31:0] with the address as specified in ADDR.ADDR: Address A is in the device when (A[31:8] &amp; MASK[31:8]) == ADDR.ADDR[31:8].
31773
31774The most significant bit fields are constants and set to'1'. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK  is 0xff00:0000 (16 MB XIP memory region), MASK[31:24] = 0xff.
31775
31776Note: a transfer request that is not in any device region results in an AHB-Lite bus error.</description>
31777                <bitRange>[31:8]</bitRange>
31778                <access>read-write</access>
31779              </field>
31780            </fields>
31781          </register>
31782          <register>
31783            <name>ADDR_CTL</name>
31784            <description>Address control</description>
31785            <addressOffset>0x20</addressOffset>
31786            <size>32</size>
31787            <access>read-write</access>
31788            <resetValue>0x0</resetValue>
31789            <resetMask>0x107</resetMask>
31790            <fields>
31791              <field>
31792                <name>SIZE3</name>
31793                <description>N/A</description>
31794                <bitRange>[2:0]</bitRange>
31795                <access>read-write</access>
31796              </field>
31797              <field>
31798                <name>DIV2</name>
31799                <description>Specifies if the AHB-Lite bus transfer address is divided by 2 or not:
31800'0': No divide by 2.
31801'1': Divide by 2.
31802
31803This functionality is used for read and write operation in XIP, dual quad SPI mode; i.e. this DIV2 must be set to '1' in dual quad SPI mode.
31804If DIV2 is set to '1', the memory does not support write masking (WR_DUMMY_CTL.RWDS_EN = '0'), and in this configuration a write transfer is requested and the write transfer request address is NOT a multiple of 2 or the requested number of Bytes to be written is not a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated.</description>
31805                <bitRange>[8:8]</bitRange>
31806                <access>read-write</access>
31807              </field>
31808            </fields>
31809          </register>
31810          <register>
31811            <name>DELAY_TAP_SEL</name>
31812            <description>RX Clock Delay Tap Select Register</description>
31813            <addressOffset>0x2C</addressOffset>
31814            <size>32</size>
31815            <access>read-write</access>
31816            <resetValue>0x1</resetValue>
31817            <resetMask>0xFF</resetMask>
31818            <fields>
31819              <field>
31820                <name>SEL</name>
31821                <description>Delay line tap selection in output / feedback clock based capture scheme (CLOCK_IF_RX_SEL = [0..3]) and RWDS capture scheme (CLOCK_IF_RX_SEL = [6..7]). This is used to shift the strobe signal into the data eye.
31822
31823Any 2 devices connected in a dual quad SPI arrangement must set this register equivalently.
31824
31825Note: DELAY_TAP_SEL must not be changed while STATUS.BUSY=1.</description>
31826                <bitRange>[7:0]</bitRange>
31827                <access>read-write</access>
31828              </field>
31829            </fields>
31830          </register>
31831          <register>
31832            <name>RD_STATUS</name>
31833            <description>Read status</description>
31834            <addressOffset>0x30</addressOffset>
31835            <size>32</size>
31836            <access>read-only</access>
31837            <resetValue>0x0</resetValue>
31838            <resetMask>0xFF</resetMask>
31839            <fields>
31840              <field>
31841                <name>FS_STATUS</name>
31842                <description>Provides the Functional Safety Status Register of the memory received with the last read transfer.</description>
31843                <bitRange>[7:0]</bitRange>
31844                <access>read-only</access>
31845              </field>
31846            </fields>
31847          </register>
31848          <register>
31849            <name>RD_CMD_CTL</name>
31850            <description>Read command control</description>
31851            <addressOffset>0x40</addressOffset>
31852            <size>32</size>
31853            <access>read-write</access>
31854            <resetValue>0x0</resetValue>
31855            <resetMask>0xC007FFFF</resetMask>
31856            <fields>
31857              <field>
31858                <name>CODE</name>
31859                <description>Command byte code.</description>
31860                <bitRange>[7:0]</bitRange>
31861                <access>read-write</access>
31862              </field>
31863              <field>
31864                <name>CODEH</name>
31865                <description>Command high byte code.
31866This field specifies the most significant command byte, sent before the least significant command byte (CODE). It is only used when PRESENT2 = '2'.</description>
31867                <bitRange>[15:8]</bitRange>
31868                <access>read-write</access>
31869              </field>
31870              <field>
31871                <name>WIDTH</name>
31872                <description>Width of data transfer:
31873'0': 1 bit/cycle (single data transfer).
31874'1': 2 bits/cycle (dual data transfer).
31875'2': 4 bits/cycle (quad data transfer).
31876'3': 8 bits/cycle (octal data transfer).</description>
31877                <bitRange>[17:16]</bitRange>
31878                <access>read-write</access>
31879              </field>
31880              <field>
31881                <name>DDR_MODE</name>
31882                <description>Mode of transfer rate:
31883'0': SDR mode
31884'1': DDR mode</description>
31885                <bitRange>[18:18]</bitRange>
31886                <access>read-write</access>
31887              </field>
31888              <field>
31889                <name>PRESENT2</name>
31890                <description>Presence of command field:
31891'0': not present
31892'1': present (1 Byte)
31893'2': present (2 Byte for OPI)
31894
31895Note: For octal data transfer with DDR mode (WIDTH='3' and DDR_MODE='1') either the HB protocol needs to be selected (by ADDR_CTL.SIZE3='7') or this field needs to be set to PRESENT2='2'.</description>
31896                <bitRange>[31:30]</bitRange>
31897                <access>read-write</access>
31898              </field>
31899            </fields>
31900          </register>
31901          <register>
31902            <name>RD_ADDR_CTL</name>
31903            <description>Read address control</description>
31904            <addressOffset>0x44</addressOffset>
31905            <size>32</size>
31906            <access>read-write</access>
31907            <resetValue>0x0</resetValue>
31908            <resetMask>0x70000</resetMask>
31909            <fields>
31910              <field>
31911                <name>WIDTH</name>
31912                <description>Width of transfer.</description>
31913                <bitRange>[17:16]</bitRange>
31914                <access>read-write</access>
31915              </field>
31916              <field>
31917                <name>DDR_MODE</name>
31918                <description>Mode of transfer rate.</description>
31919                <bitRange>[18:18]</bitRange>
31920                <access>read-write</access>
31921              </field>
31922            </fields>
31923          </register>
31924          <register>
31925            <name>RD_MODE_CTL</name>
31926            <description>Read mode control</description>
31927            <addressOffset>0x48</addressOffset>
31928            <size>32</size>
31929            <access>read-write</access>
31930            <resetValue>0x0</resetValue>
31931            <resetMask>0xC007FFFF</resetMask>
31932            <fields>
31933              <field>
31934                <name>CODE</name>
31935                <description>Mode byte code.
31936Note: If a mode field is present (PRESENT='1') for octal data transfer with DDR mode (WIDTH='3' and DDR_MODE='1') the CODE is sent twice.</description>
31937                <bitRange>[7:0]</bitRange>
31938                <access>read-write</access>
31939              </field>
31940              <field>
31941                <name>CODEH</name>
31942                <description>Mode high byte code.
31943This field specifies the most significant mode byte, sent before the least significant mode byte (CODE). It is only used when PRESENT2 = '2'.</description>
31944                <bitRange>[15:8]</bitRange>
31945                <access>read-write</access>
31946              </field>
31947              <field>
31948                <name>WIDTH</name>
31949                <description>Width of transfer.</description>
31950                <bitRange>[17:16]</bitRange>
31951                <access>read-write</access>
31952              </field>
31953              <field>
31954                <name>DDR_MODE</name>
31955                <description>Mode of transfer rate.</description>
31956                <bitRange>[18:18]</bitRange>
31957                <access>read-write</access>
31958              </field>
31959              <field>
31960                <name>PRESENT2</name>
31961                <description>Presence of mode field:
31962'0': not present
31963'1': present (1 Byte)
31964'2': present (2 Byte for OPI)
31965
31966Note: For octal data transfer with DDR mode (WIDTH='3' and DDR_MODE='1') this field needs to be set to PRESENT2='2' to generate a mode field (or to PRESENT2='0').</description>
31967                <bitRange>[31:30]</bitRange>
31968                <access>read-write</access>
31969              </field>
31970            </fields>
31971          </register>
31972          <register>
31973            <name>RD_DUMMY_CTL</name>
31974            <description>Read dummy control</description>
31975            <addressOffset>0x4C</addressOffset>
31976            <size>32</size>
31977            <access>read-write</access>
31978            <resetValue>0x0</resetValue>
31979            <resetMask>0xC000001F</resetMask>
31980            <fields>
31981              <field>
31982                <name>SIZE5</name>
31983                <description>Number of dummy cycles (minus 1):
31984'0': 1 cycles
31985...
31986'31': 32 cycles.
31987
31988Note: this field specifies dummy cycles, not dummy Bytes!</description>
31989                <bitRange>[4:0]</bitRange>
31990                <access>read-write</access>
31991              </field>
31992              <field>
31993                <name>PRESENT2</name>
31994                <description>Presence of dummy cycles:
31995'0': not present
31996'1': present
31997'2': present - Dummy cycles are doubled when RWDS refresh indicator is high during CA cycle. (HyperRAM variable latency mode)
31998
31999Notes:
32000- If CLOCK_IF_TX_SEL = '0' for transmitting command, address and mode fields in SDR mode (driving data between falling edges of spihb_clk_out) and the memory is driving read data in DDR mode (based on memory type and transmitted command), then there must be at least 1 latency / dummy cycle specified (RD_DUMMY_CTL.PRESENT2 &gt; 0') to prevent controller and memory driving data signals at the same time.
32001The same is true for the theoretical (practically irrelevant case) of transmitting at least one of the command, address and mode fields in DDR mode but receiving data from the memory in SDR mode.
32002
32003- When using the RWDS / DQS based capturing scheme (CTL.CLK_IF_RX_SEL=[6,7]), then there is a minimum number of latency / dummy cycles required (RD_DUMMY_CTL.PRESENT2 &gt; 0). For the Hyperbus protocol (DDR_CTL.SIZE3=7) at least 1 latency / dummy cycle has to be specified, for SPI with DQS capturing at least 2 latency / dummy cycles need to be selected (RD_DUMMY_CTL.SIZE5 &gt; 0, exception see following note).
32004
32005- In case of falling edge RWDS / DQS capturing (CTL.CLOCK_IF_RX_SEL = '6') and SDR mode, SW should reduce the number of dummy cycles by 1 compared to the latency cycles required by the memory device.
32006
32007-DDR read commands need at least one dummy cycle
32008
32009-For Hyperbus, set RD DUMMY_CTL.SIZE5=initial latency cycles-2</description>
32010                <bitRange>[31:30]</bitRange>
32011                <access>read-write</access>
32012              </field>
32013            </fields>
32014          </register>
32015          <register>
32016            <name>RD_DATA_CTL</name>
32017            <description>Read data control</description>
32018            <addressOffset>0x50</addressOffset>
32019            <size>32</size>
32020            <access>read-write</access>
32021            <resetValue>0x0</resetValue>
32022            <resetMask>0x70000</resetMask>
32023            <fields>
32024              <field>
32025                <name>WIDTH</name>
32026                <description>Width of transfer.</description>
32027                <bitRange>[17:16]</bitRange>
32028                <access>read-write</access>
32029              </field>
32030              <field>
32031                <name>DDR_MODE</name>
32032                <description>Mode of transfer rate.</description>
32033                <bitRange>[18:18]</bitRange>
32034                <access>read-write</access>
32035              </field>
32036            </fields>
32037          </register>
32038          <register>
32039            <name>RD_CRC_CTL</name>
32040            <description>Read Bus CRC control</description>
32041            <addressOffset>0x54</addressOffset>
32042            <size>32</size>
32043            <access>read-write</access>
32044            <resetValue>0xFF00</resetValue>
32045            <resetMask>0xDFFFFFFF</resetMask>
32046            <fields>
32047              <field>
32048                <name>STATUS_CHECK_MASK</name>
32049                <description>Specifies which of the Functional Safety Status field bits are checked. There is 1 mask bit for each Functional Safety Status bit.
32050'0': The associated Functional Safety Status bit is not checked.
32051'1': The associated Functional Safety Status bit is checked. If the received Funciontal Safety Status bit = Functional Safety Status Error Polarity (STATUS_ERROR_POLARITY), then a Functional Safety Status error interrupt and a XIP bus error response is generated.</description>
32052                <bitRange>[7:0]</bitRange>
32053                <access>read-write</access>
32054              </field>
32055              <field>
32056                <name>STATUS_ERROR_POL</name>
32057                <description>Specifies the polarity of the Functional Safety Status field bits. There is 1 polarity bit for each Functional Safety Status bit.
32058'0': The associated Functional Safety Status bit is active-low.
32059'1': The associated Functional Safety Status bit is active-high.</description>
32060                <bitRange>[15:8]</bitRange>
32061                <access>read-write</access>
32062              </field>
32063              <field>
32064                <name>DATA_CRC_INPUT_SIZE</name>
32065                <description>Number of input data bytes for CRC generation (minus 1), i.e. number of data bytes over which the data CRC field is generated (minus 1):
32066'0': 1 byte
32067...
32068'255': 256 bytes.
32069
32070Note: For octal data transfer with DDR mode (RD_DATA_CTL.WIDTH='3' and RD_DATA_CTL.DDR_MODE='1') the number of bytes for CRC generation must be even (i.e. DATA_CRC_INPUT_SIZE must be odd).</description>
32071                <bitRange>[23:16]</bitRange>
32072                <access>read-write</access>
32073              </field>
32074              <field>
32075                <name>CMD_ADDR_CRC_WIDTH</name>
32076                <description>Width of command / address CRC field.</description>
32077                <bitRange>[25:24]</bitRange>
32078                <access>read-write</access>
32079              </field>
32080              <field>
32081                <name>CMD_ADDR_CRC_DDR_MODE</name>
32082                <description>Mode of transfer rate of command / address CRC field.</description>
32083                <bitRange>[26:26]</bitRange>
32084                <access>read-write</access>
32085              </field>
32086              <field>
32087                <name>CMD_ADDR_CRC_INPUT</name>
32088                <description>Specifies which fields are included in the command / address CRC generation.
32089'0': The command / address CRC field is generated over the address and (if present) mode fields only.
32090'1': The command / address CRC field is generated over the command, address and (if present) mode fields.</description>
32091                <bitRange>[27:27]</bitRange>
32092                <access>read-write</access>
32093              </field>
32094              <field>
32095                <name>DATA_CRC_CHECK</name>
32096                <description>N/A</description>
32097                <bitRange>[28:28]</bitRange>
32098                <access>read-write</access>
32099              </field>
32100              <field>
32101                <name>CMD_ADDR_CRC_PRESENT</name>
32102                <description>Presence of command / address CRC field:
32103'0': not present
32104'1': present
32105
32106Note: For octal data transfer with DDR mode (RD_CRC_CTL.WIDTH='3' and RD_CRC_CTL.DDR_MODE='1') the command / address CRC byte is sent twice, otherwise the command / address CRC byte is only sent once.</description>
32107                <bitRange>[30:30]</bitRange>
32108                <access>read-write</access>
32109              </field>
32110              <field>
32111                <name>DATA_CRC_PRESENT</name>
32112                <description>Presence of data CRC field:
32113'0': not present
32114'1': present
32115
32116Note: Width and data transfer mode (SDR or DDR) of read data CRC fields are the same as for the associated read data fields, i.e. are specified by RD_DATA_CTL.WIDTH and RD_DATA_CTL.DDR_MODE.</description>
32117                <bitRange>[31:31]</bitRange>
32118                <access>read-write</access>
32119              </field>
32120            </fields>
32121          </register>
32122          <register>
32123            <name>RD_BOUND_CTL</name>
32124            <description>Read boundary control</description>
32125            <addressOffset>0x58</addressOffset>
32126            <size>32</size>
32127            <access>read-write</access>
32128            <resetValue>0x100000</resetValue>
32129            <resetMask>0x9033001F</resetMask>
32130            <fields>
32131              <field>
32132                <name>SIZE5</name>
32133                <description>Number of base latency cycles (minus 1) used for calculating the number of fist page boundary crossing latency cycles:
32134'0': base_latency = 1 cycles
32135...
32136'31': base_latency = 32 cycles.
32137
32138The actual latency cycles when crossing the first page boundary depend on the start address of the transaction and is calculated as follows:
32139if ((page_size - base_latency) &lt; Start_Addr &amp; (sub_page_size - 1))
32140  { ((Start_Addr &amp; (sub_page_size - 1)) - page_size + base_latency) }
32141else
32142  { 0 }</description>
32143                <bitRange>[4:0]</bitRange>
32144                <access>read-write</access>
32145              </field>
32146              <field>
32147                <name>SUB_PAGE_SIZE</name>
32148                <description>Specifies the size of a memory sub page 'sub_page_size'.
32149'0': sub_page_size = 8   words = 16 bytes (default).
32150'1': sub_page_size = 16 words = 32 bytes.
32151'2': sub_page_size = 32 words = 64 bytes.
32152'3': sub_page_size = 64 words = 128 bytes.</description>
32153                <bitRange>[17:16]</bitRange>
32154                <access>read-write</access>
32155              </field>
32156              <field>
32157                <name>SUB_PAGE_NR</name>
32158                <description>Specifies the number of sub pages per page.
32159'0': 1 sub pages per page, i.e. page_size = sub_page_size
32160'1': 2 sub pages per page, i.e. page_size = 2 x sub_page_size
32161'2': 4 sub pages per page, i.e. page_size = 4 x sub_page_size
32162'3': 8 sub pages per page, i.e. page_size = 8 x sub_page_size</description>
32163                <bitRange>[21:20]</bitRange>
32164                <access>read-write</access>
32165              </field>
32166              <field>
32167                <name>SUBSEQ_BOUND_EN</name>
32168                <description>Enable subsequent page boundary latency cycles.
32169'0': Disabled.
32170The page crossing latency cycles are only generated when crossing the first page boundary (i.e. the first time when the SUB_PAGE_NRth sub page boundary is crossed, e.g. with 2 sub pages per page when the 2nd sub page boundary is crossed).
32171'1': Enabled.
32172The page crossing latency cycles are generated when crossing the first and subsequent page boundaries (i.e. every time when a SUB_PAGE_NRth sub page boundary is crossed, e.g. with 2 sub pages per page when the 2nd, 4th, 6th, ... sub page boundary is crossed).
32173
32174Note: This only applies when the number of base latency cycles (SIZE5+1) is greater than the size of a page (base_latency &gt; page_size).  Must be set to 0 otherwise.</description>
32175                <bitRange>[28:28]</bitRange>
32176                <access>read-write</access>
32177              </field>
32178              <field>
32179                <name>PRESENT</name>
32180                <description>Presence of first page boundary latency cycles:
32181'0': not present
32182'1': present</description>
32183                <bitRange>[31:31]</bitRange>
32184                <access>read-write</access>
32185              </field>
32186            </fields>
32187          </register>
32188          <register>
32189            <name>WR_CMD_CTL</name>
32190            <description>Write command control</description>
32191            <addressOffset>0x60</addressOffset>
32192            <size>32</size>
32193            <access>read-write</access>
32194            <resetValue>0x0</resetValue>
32195            <resetMask>0xC007FFFF</resetMask>
32196            <fields>
32197              <field>
32198                <name>CODE</name>
32199                <description>Command byte code.</description>
32200                <bitRange>[7:0]</bitRange>
32201                <access>read-write</access>
32202              </field>
32203              <field>
32204                <name>CODEH</name>
32205                <description>Command high byte code.
32206This field specifies the most significant command byte, sent before the least significant command byte (CODE). It is only used when PRESENT2 = '2'.</description>
32207                <bitRange>[15:8]</bitRange>
32208                <access>read-write</access>
32209              </field>
32210              <field>
32211                <name>WIDTH</name>
32212                <description>Width of transfer.</description>
32213                <bitRange>[17:16]</bitRange>
32214                <access>read-write</access>
32215              </field>
32216              <field>
32217                <name>DDR_MODE</name>
32218                <description>Mode of transfer rate.</description>
32219                <bitRange>[18:18]</bitRange>
32220                <access>read-write</access>
32221              </field>
32222              <field>
32223                <name>PRESENT2</name>
32224                <description>Presence of command field:
32225'0': not present
32226'1': present (1 Byte)
32227'2': present (2 Byte for OPI)
32228
32229Note: For octal data transfer with DDR mode (WIDTH='3' and DDR_MODE='1') either the HB protocol needs to be selected (by ADDR_CTL.SIZE3='7') or this field needs to be set to PRESENT2='2'.</description>
32230                <bitRange>[31:30]</bitRange>
32231                <access>read-write</access>
32232              </field>
32233            </fields>
32234          </register>
32235          <register>
32236            <name>WR_ADDR_CTL</name>
32237            <description>Write address control</description>
32238            <addressOffset>0x64</addressOffset>
32239            <size>32</size>
32240            <access>read-write</access>
32241            <resetValue>0x0</resetValue>
32242            <resetMask>0x70000</resetMask>
32243            <fields>
32244              <field>
32245                <name>WIDTH</name>
32246                <description>Width of transfer.</description>
32247                <bitRange>[17:16]</bitRange>
32248                <access>read-write</access>
32249              </field>
32250              <field>
32251                <name>DDR_MODE</name>
32252                <description>Mode of transfer rate.</description>
32253                <bitRange>[18:18]</bitRange>
32254                <access>read-write</access>
32255              </field>
32256            </fields>
32257          </register>
32258          <register>
32259            <name>WR_MODE_CTL</name>
32260            <description>Write mode control</description>
32261            <addressOffset>0x68</addressOffset>
32262            <size>32</size>
32263            <access>read-write</access>
32264            <resetValue>0x0</resetValue>
32265            <resetMask>0xC007FFFF</resetMask>
32266            <fields>
32267              <field>
32268                <name>CODE</name>
32269                <description>Mode byte code.</description>
32270                <bitRange>[7:0]</bitRange>
32271                <access>read-write</access>
32272              </field>
32273              <field>
32274                <name>CODEH</name>
32275                <description>Mode high byte code.
32276This field specifies the most significant mode byte, sent before the least significant mode byte (CODE). It is only used when PRESENT2 = '2'.</description>
32277                <bitRange>[15:8]</bitRange>
32278                <access>read-write</access>
32279              </field>
32280              <field>
32281                <name>WIDTH</name>
32282                <description>Width of transfer.</description>
32283                <bitRange>[17:16]</bitRange>
32284                <access>read-write</access>
32285              </field>
32286              <field>
32287                <name>DDR_MODE</name>
32288                <description>Mode of transfer rate.</description>
32289                <bitRange>[18:18]</bitRange>
32290                <access>read-write</access>
32291              </field>
32292              <field>
32293                <name>PRESENT2</name>
32294                <description>Presence of mode field:
32295'0': not present
32296'1': present (1 Byte)
32297'2': present (2 Byte for OPI)
32298
32299Note: For octal data transfer with DDR mode (WIDTH='3' and DDR_MODE='1') this field needs to be set to PRESENT2='2' to generate a mode field (or to PRESENT2='0').</description>
32300                <bitRange>[31:30]</bitRange>
32301                <access>read-write</access>
32302              </field>
32303            </fields>
32304          </register>
32305          <register>
32306            <name>WR_DUMMY_CTL</name>
32307            <description>Write dummy control</description>
32308            <addressOffset>0x6C</addressOffset>
32309            <size>32</size>
32310            <access>read-write</access>
32311            <resetValue>0x0</resetValue>
32312            <resetMask>0xC002001F</resetMask>
32313            <fields>
32314              <field>
32315                <name>SIZE5</name>
32316                <description>Number of dummy cycles (minus 1):
32317'0': 1 cycles
32318...
32319'31': 32 cycles.</description>
32320                <bitRange>[4:0]</bitRange>
32321                <access>read-write</access>
32322              </field>
32323              <field>
32324                <name>RWDS_EN</name>
32325                <description>Read-Write-Data-Strobe Enable. Specifies whether the RWDS output signal should be driven starting in the last dummy cycle until DESELECT. This is needed for write transactions with byte masking via RWDS (e.g. Hyperbus).
32326'0': do not drive RWDS output
32327'1': drive RWDS output starting in last dummy cycle until DESELECT
32328
32329Note: this field is located in the WR_DUMMY_CTL register (and not in the WR_DATA_CTL register) since the RWDS signal needs to be driven already in the last dummy cycle.</description>
32330                <bitRange>[17:17]</bitRange>
32331                <access>read-write</access>
32332              </field>
32333              <field>
32334                <name>PRESENT2</name>
32335                <description>Presence of dummy cycles:
32336'0': not present
32337'1': present
32338'2': present - Dummy cycles are doubled when RWDS refresh indicator is high during CA cycle. (HyperRAM variable latency mode)</description>
32339                <bitRange>[31:30]</bitRange>
32340                <access>read-write</access>
32341              </field>
32342            </fields>
32343          </register>
32344          <register>
32345            <name>WR_DATA_CTL</name>
32346            <description>Write data control</description>
32347            <addressOffset>0x70</addressOffset>
32348            <size>32</size>
32349            <access>read-write</access>
32350            <resetValue>0x0</resetValue>
32351            <resetMask>0x70000</resetMask>
32352            <fields>
32353              <field>
32354                <name>WIDTH</name>
32355                <description>Width of transfer.</description>
32356                <bitRange>[17:16]</bitRange>
32357                <access>read-write</access>
32358              </field>
32359              <field>
32360                <name>DDR_MODE</name>
32361                <description>Mode of transfer rate.</description>
32362                <bitRange>[18:18]</bitRange>
32363                <access>read-write</access>
32364              </field>
32365            </fields>
32366          </register>
32367          <register>
32368            <name>WR_CRC_CTL</name>
32369            <description>Write Bus CRC control</description>
32370            <addressOffset>0x74</addressOffset>
32371            <size>32</size>
32372            <access>read-write</access>
32373            <resetValue>0x0</resetValue>
32374            <resetMask>0xCFFF0000</resetMask>
32375            <fields>
32376              <field>
32377                <name>DATA_CRC_INPUT_SIZE</name>
32378                <description>Number of input data bytes for CRC generation (minus 1), i.e. number of data bytes over which the data CRC field is generated (minus 1):
32379'0': 1 byte
32380...
32381'255': 256 bytes.
32382
32383Note: For octal data transfer with DDR mode (WR_DATA_CTL.WIDTH='3' and WR_DATA_CTL.DDR_MODE='1') the number of bytes for CRC generation must be even (i.e. DATA_CRC_INPUT_SIZE must be odd).</description>
32384                <bitRange>[23:16]</bitRange>
32385                <access>read-write</access>
32386              </field>
32387              <field>
32388                <name>CMD_ADDR_CRC_WIDTH</name>
32389                <description>Width of command / address CRC field.</description>
32390                <bitRange>[25:24]</bitRange>
32391                <access>read-write</access>
32392              </field>
32393              <field>
32394                <name>CMD_ADDR_CRC_DDR_MODE</name>
32395                <description>Mode of transfer rate of command / address CRC field.</description>
32396                <bitRange>[26:26]</bitRange>
32397                <access>read-write</access>
32398              </field>
32399              <field>
32400                <name>CMD_ADDR_CRC_INPUT</name>
32401                <description>Specifies which fields are included in the command / address CRC generation.
32402'0': The command / address CRC field is generated over the address and (if present) mode fields only.
32403'1': The command / address CRC field is generated over the command, address and (if present) mode fields.</description>
32404                <bitRange>[27:27]</bitRange>
32405                <access>read-write</access>
32406              </field>
32407              <field>
32408                <name>CMD_ADDR_CRC_PRESENT</name>
32409                <description>Presence of command / address CRC field:
32410'0': not present
32411'1': present
32412
32413Note: For octal data transfer with DDR mode (RD_CRC_CTL.WIDTH='3' and RD_CRC_CTL.DDR_MODE='1') the command / address CRC byte is sent twice, otherwise the command / address CRC byte is only sent once.</description>
32414                <bitRange>[30:30]</bitRange>
32415                <access>read-write</access>
32416              </field>
32417              <field>
32418                <name>DATA_CRC_PRESENT</name>
32419                <description>Presence of data CRC field:
32420'0': not present
32421'1': present
32422
32423Note: Width and data transfer mode (SDR or DDR) of read data CRC fields are the same as for the associated read data fields, i.e. are specified by RD_DATA_CTL.WIDTH and RD_DATA_CTL.DDR_MODE.
32424
32425Note: For octal data transfer with DDR mode (RD_DATA_CTL.WIDTH='3' and RD_DATA_CTL.DDR_MODE='1') the data CRC byte is sent twice, otherwise the data CRC byte is only sent once.</description>
32426                <bitRange>[31:31]</bitRange>
32427                <access>read-write</access>
32428              </field>
32429            </fields>
32430          </register>
32431        </cluster>
32432        <cluster>
32433          <name>MPC</name>
32434          <description>MPC Memory Protection Controller registers</description>
32435          <addressOffset>0x00001000</addressOffset>
32436          <register>
32437            <name>CFG</name>
32438            <description>Config register with error response, RegionID PPC_MPC_MAIN is the security owner PC. The error response configuration is located in CFG.RESPONSE, only one such configuration exists applying to all protection contexts in the system.</description>
32439            <addressOffset>0x0</addressOffset>
32440            <size>32</size>
32441            <access>read-write</access>
32442            <resetValue>0x0</resetValue>
32443            <resetMask>0x10</resetMask>
32444            <fields>
32445              <field>
32446                <name>RESPONSE</name>
32447                <description>Response Configuration for Security and PC violations
324480: Read-Zero Write Ignore (RAZ/WI)
324491: Bus Error</description>
32450                <bitRange>[4:4]</bitRange>
32451                <access>read-write</access>
32452              </field>
32453            </fields>
32454          </register>
32455          <register>
32456            <name>INTR</name>
32457            <description>Interrupt</description>
32458            <addressOffset>0x10</addressOffset>
32459            <size>32</size>
32460            <access>read-write</access>
32461            <resetValue>0x0</resetValue>
32462            <resetMask>0x1</resetMask>
32463            <fields>
32464              <field>
32465                <name>VIOLATION</name>
32466                <description>HW sets this field to '1', when a security violation is detected.
32467SW writes '1' to this field to clear</description>
32468                <bitRange>[0:0]</bitRange>
32469                <access>read-write</access>
32470              </field>
32471            </fields>
32472          </register>
32473          <register>
32474            <name>INTR_SET</name>
32475            <description>Interrupt set</description>
32476            <addressOffset>0x14</addressOffset>
32477            <size>32</size>
32478            <access>read-write</access>
32479            <resetValue>0x0</resetValue>
32480            <resetMask>0x1</resetMask>
32481            <fields>
32482              <field>
32483                <name>VIOLATION</name>
32484                <description>SW write this field with '1' to set INTR register (a write of '0' has no effect).</description>
32485                <bitRange>[0:0]</bitRange>
32486                <access>read-write</access>
32487              </field>
32488            </fields>
32489          </register>
32490          <register>
32491            <name>INTR_MASK</name>
32492            <description>Interrupt mask</description>
32493            <addressOffset>0x18</addressOffset>
32494            <size>32</size>
32495            <access>read-write</access>
32496            <resetValue>0x0</resetValue>
32497            <resetMask>0x1</resetMask>
32498            <fields>
32499              <field>
32500                <name>VIOLATION</name>
32501                <description>Mask for corresponding field in INTR register.</description>
32502                <bitRange>[0:0]</bitRange>
32503                <access>read-write</access>
32504              </field>
32505            </fields>
32506          </register>
32507          <register>
32508            <name>INTR_MASKED</name>
32509            <description>Interrupt masked</description>
32510            <addressOffset>0x1C</addressOffset>
32511            <size>32</size>
32512            <access>read-only</access>
32513            <resetValue>0x0</resetValue>
32514            <resetMask>0x1</resetMask>
32515            <fields>
32516              <field>
32517                <name>VIOLATION</name>
32518                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
32519                <bitRange>[0:0]</bitRange>
32520                <access>read-only</access>
32521              </field>
32522            </fields>
32523          </register>
32524          <register>
32525            <name>INTR_INFO1</name>
32526            <description>Infor about violation</description>
32527            <addressOffset>0x20</addressOffset>
32528            <size>32</size>
32529            <access>read-only</access>
32530            <resetValue>0x0</resetValue>
32531            <resetMask>0xFFFFFFFF</resetMask>
32532            <fields>
32533              <field>
32534                <name>VALUE</name>
32535                <description>Full address of the access that caused violation</description>
32536                <bitRange>[31:0]</bitRange>
32537                <access>read-only</access>
32538              </field>
32539            </fields>
32540          </register>
32541          <register>
32542            <name>INTR_INFO2</name>
32543            <description>Infor about violation</description>
32544            <addressOffset>0x24</addressOffset>
32545            <size>32</size>
32546            <access>read-only</access>
32547            <resetValue>0x0</resetValue>
32548            <resetMask>0xCF07FFFF</resetMask>
32549            <fields>
32550              <field>
32551                <name>HMASTER</name>
32552                <description>The master ID of the master that made the access causing the violation (taken from the AHB HMASTER signal)</description>
32553                <bitRange>[15:0]</bitRange>
32554                <access>read-only</access>
32555              </field>
32556              <field>
32557                <name>HNONSEC</name>
32558                <description>The security status of the access address causing the violation (taken from the AHB5 HNONSEC signal).</description>
32559                <bitRange>[16:16]</bitRange>
32560                <access>read-only</access>
32561              </field>
32562              <field>
32563                <name>CFG_NS</name>
32564                <description>The secure/non-secure configuration of the block access attempt causing the violation.</description>
32565                <bitRange>[17:17]</bitRange>
32566                <access>read-only</access>
32567              </field>
32568              <field>
32569                <name>HWRITE</name>
32570                <description>The R/W status from which the violating access was made.</description>
32571                <bitRange>[18:18]</bitRange>
32572                <access>read-only</access>
32573              </field>
32574              <field>
32575                <name>HAUSER</name>
32576                <description>The protection context from which the violating access was made (taken from the AHB5 HAUSER signal).</description>
32577                <bitRange>[27:24]</bitRange>
32578                <access>read-only</access>
32579              </field>
32580              <field>
32581                <name>SECURITY_VIOLATION</name>
32582                <description>This bit is set when a secure access was done to a non-secure block of memory, or a non-secure access was done to a secure block of memory.</description>
32583                <bitRange>[30:30]</bitRange>
32584                <access>read-only</access>
32585              </field>
32586              <field>
32587                <name>ACCESS_VIOLATION</name>
32588                <description>This bit is set when a read or write transaction was done from a protection context that does not have access to this block of memory.</description>
32589                <bitRange>[31:31]</bitRange>
32590                <access>read-only</access>
32591              </field>
32592            </fields>
32593          </register>
32594          <register>
32595            <name>CTRL</name>
32596            <description>Control register with lock bit and auto-increment only (Separate CTRL for each PC depends on access_pc)</description>
32597            <addressOffset>0x100</addressOffset>
32598            <size>32</size>
32599            <access>read-write</access>
32600            <resetValue>0x100</resetValue>
32601            <resetMask>0x80000100</resetMask>
32602            <fields>
32603              <field>
32604                <name>AUTO_INC</name>
32605                <description>Auto-increment BLK_IDX by 1 for this protection context as a side effect of each read/write access to BLK_LUT</description>
32606                <bitRange>[8:8]</bitRange>
32607                <access>read-write</access>
32608              </field>
32609              <field>
32610                <name>LOCK</name>
32611                <description>Security lockdown for this protection context. Software can set this bit but not clear it once set.  When set, write operations to BLK_LUT are not possible  from this protection context. Setting LOCK also blocks writes to CTRL itself (for that PC copy). All writes are ignored.</description>
32612                <bitRange>[31:31]</bitRange>
32613                <access>read-write</access>
32614              </field>
32615            </fields>
32616          </register>
32617          <register>
32618            <name>BLK_MAX</name>
32619            <description>Max value of block-based index register</description>
32620            <addressOffset>0x104</addressOffset>
32621            <size>32</size>
32622            <access>read-only</access>
32623            <resetValue>0x0</resetValue>
32624            <resetMask>0xFFFFFFFF</resetMask>
32625            <fields>
32626              <field>
32627                <name>VALUE</name>
32628                <description>Maximum value of block-based index register.  The number and size blocks in an MPC is design time configurable and for embedded memories defaults to covering the entire memory using 4kB blocks; See product datasheet for details on protection of external memories.</description>
32629                <bitRange>[31:0]</bitRange>
32630                <access>read-only</access>
32631              </field>
32632            </fields>
32633          </register>
32634          <register>
32635            <name>BLK_CFG</name>
32636            <description>Block size &amp; initialization in progress</description>
32637            <addressOffset>0x108</addressOffset>
32638            <size>32</size>
32639            <access>read-only</access>
32640            <resetValue>0x80000000</resetValue>
32641            <resetMask>0x8000000F</resetMask>
32642            <fields>
32643              <field>
32644                <name>BLOCK_SIZE</name>
32645                <description>Block size of individually protected blocks (0: 32B, 1: 64B, ... up to 15: 1MB)
32646Block size= (1&lt;&lt;(BLOCK_SIZE+5))
32647The number and size blocks in an MPC is design time configurable and for embedded memories defaults to covering the entire memory using 4kB blocks; see product datasheet for details on protection of external memories.</description>
32648                <bitRange>[3:0]</bitRange>
32649                <access>read-only</access>
32650              </field>
32651              <field>
32652                <name>INIT_IN_PROGRESS</name>
32653                <description>During initialization INIT_IN_PROGRESS is '1' and MMIO register accesses to BLK_LUT is blocked (BLK_IDX increment is also ignored). The block attributes are retained in DeepSleep (and obviously Active) power mode. Initialization is only required from a power mode in which the block attributes are not retained. E.g., initialization is required for a cold boot (after a Power-on-Reset).
32654HW initializes the block attributes: the NS attributes are set to '0' (secure), the R attributes are set to '1' (read access allowed) and the W attributes are set to '1' (write access allowed). During initialization, the MPC supports memory accesses (memory accesses are NOT blocked) with the initialization block attribute values as mentioned above. This e.g. allows MPC initialization to proceed in parallel with boot program memory accesses (as opposed to serializing the two), improving device boot time.
32655HW initializes the block attributes NS to 1 in case SECEXT = 0.</description>
32656                <bitRange>[31:31]</bitRange>
32657                <access>read-only</access>
32658              </field>
32659            </fields>
32660          </register>
32661          <register>
32662            <name>BLK_IDX</name>
32663            <description>Index of 32-block group accessed through BLK_LUT (Separate IDX for each PC depending on access_pc)</description>
32664            <addressOffset>0x10C</addressOffset>
32665            <size>32</size>
32666            <access>read-write</access>
32667            <resetValue>0x0</resetValue>
32668            <resetMask>0xFFFFFFFF</resetMask>
32669            <fields>
32670              <field>
32671                <name>VALUE</name>
32672                <description>Index value for accessing block-based lookup table using BLK_LUT. Programming out of LUT range is an user error and it loops back to '0' once overflow occurs.</description>
32673                <bitRange>[31:0]</bitRange>
32674                <access>read-write</access>
32675              </field>
32676            </fields>
32677          </register>
32678          <register>
32679            <name>BLK_LUT</name>
32680            <description>NS status for 32 blocks at BLK_IDX with PC=&lt;access_pc&gt;</description>
32681            <addressOffset>0x110</addressOffset>
32682            <size>32</size>
32683            <access>read-write</access>
32684            <resetValue>0x0</resetValue>
32685            <resetMask>0xFFFFFFFF</resetMask>
32686            <fields>
32687              <field>
32688                <name>ATTR_NS0</name>
32689                <description>NS bit for block 0 based on BLK_IDX</description>
32690                <bitRange>[0:0]</bitRange>
32691                <access>read-write</access>
32692              </field>
32693              <field>
32694                <name>ATTR_NS1</name>
32695                <description>NS bit for block 1 based on BLK_IDX</description>
32696                <bitRange>[1:1]</bitRange>
32697                <access>read-write</access>
32698              </field>
32699              <field>
32700                <name>ATTR_NS2</name>
32701                <description>NS bit for block 2 based on BLK_IDX</description>
32702                <bitRange>[2:2]</bitRange>
32703                <access>read-write</access>
32704              </field>
32705              <field>
32706                <name>ATTR_NS3</name>
32707                <description>NS bit for block 3 based on BLK_IDX</description>
32708                <bitRange>[3:3]</bitRange>
32709                <access>read-write</access>
32710              </field>
32711              <field>
32712                <name>ATTR_NS4</name>
32713                <description>NS bit for block 4 based on BLK_IDX</description>
32714                <bitRange>[4:4]</bitRange>
32715                <access>read-write</access>
32716              </field>
32717              <field>
32718                <name>ATTR_NS5</name>
32719                <description>NS bit for block 5 based on BLK_IDX</description>
32720                <bitRange>[5:5]</bitRange>
32721                <access>read-write</access>
32722              </field>
32723              <field>
32724                <name>ATTR_NS6</name>
32725                <description>NS bit for block 6 based on BLK_IDX</description>
32726                <bitRange>[6:6]</bitRange>
32727                <access>read-write</access>
32728              </field>
32729              <field>
32730                <name>ATTR_NS7</name>
32731                <description>NS bit for block 7 based on BLK_IDX</description>
32732                <bitRange>[7:7]</bitRange>
32733                <access>read-write</access>
32734              </field>
32735              <field>
32736                <name>ATTR_NS8</name>
32737                <description>NS bit for block 8 based on BLK_IDX</description>
32738                <bitRange>[8:8]</bitRange>
32739                <access>read-write</access>
32740              </field>
32741              <field>
32742                <name>ATTR_NS9</name>
32743                <description>NS bit for block 9 based on BLK_IDX</description>
32744                <bitRange>[9:9]</bitRange>
32745                <access>read-write</access>
32746              </field>
32747              <field>
32748                <name>ATTR_NS10</name>
32749                <description>NS bit for block 10 based on BLK_IDX</description>
32750                <bitRange>[10:10]</bitRange>
32751                <access>read-write</access>
32752              </field>
32753              <field>
32754                <name>ATTR_NS11</name>
32755                <description>NS bit for block 11 based on BLK_IDX</description>
32756                <bitRange>[11:11]</bitRange>
32757                <access>read-write</access>
32758              </field>
32759              <field>
32760                <name>ATTR_NS12</name>
32761                <description>NS bit for block 12 based on BLK_IDX</description>
32762                <bitRange>[12:12]</bitRange>
32763                <access>read-write</access>
32764              </field>
32765              <field>
32766                <name>ATTR_NS13</name>
32767                <description>NS bit for block 13 based on BLK_IDX</description>
32768                <bitRange>[13:13]</bitRange>
32769                <access>read-write</access>
32770              </field>
32771              <field>
32772                <name>ATTR_NS14</name>
32773                <description>NS bit for block 14 based on BLK_IDX</description>
32774                <bitRange>[14:14]</bitRange>
32775                <access>read-write</access>
32776              </field>
32777              <field>
32778                <name>ATTR_NS15</name>
32779                <description>NS bit for block 15 based on BLK_IDX</description>
32780                <bitRange>[15:15]</bitRange>
32781                <access>read-write</access>
32782              </field>
32783              <field>
32784                <name>ATTR_NS16</name>
32785                <description>NS bit for block 16 based on BLK_IDX</description>
32786                <bitRange>[16:16]</bitRange>
32787                <access>read-write</access>
32788              </field>
32789              <field>
32790                <name>ATTR_NS17</name>
32791                <description>NS bit for block 17 based on BLK_IDX</description>
32792                <bitRange>[17:17]</bitRange>
32793                <access>read-write</access>
32794              </field>
32795              <field>
32796                <name>ATTR_NS18</name>
32797                <description>NS bit for block 18 based on BLK_IDX</description>
32798                <bitRange>[18:18]</bitRange>
32799                <access>read-write</access>
32800              </field>
32801              <field>
32802                <name>ATTR_NS19</name>
32803                <description>NS bit for block 19 based on BLK_IDX</description>
32804                <bitRange>[19:19]</bitRange>
32805                <access>read-write</access>
32806              </field>
32807              <field>
32808                <name>ATTR_NS20</name>
32809                <description>NS bit for block 20 based on BLK_IDX</description>
32810                <bitRange>[20:20]</bitRange>
32811                <access>read-write</access>
32812              </field>
32813              <field>
32814                <name>ATTR_NS21</name>
32815                <description>NS bit for block 21 based on BLK_IDX</description>
32816                <bitRange>[21:21]</bitRange>
32817                <access>read-write</access>
32818              </field>
32819              <field>
32820                <name>ATTR_NS22</name>
32821                <description>NS bit for block 22 based on BLK_IDX</description>
32822                <bitRange>[22:22]</bitRange>
32823                <access>read-write</access>
32824              </field>
32825              <field>
32826                <name>ATTR_NS23</name>
32827                <description>NS bit for block 23 based on BLK_IDX</description>
32828                <bitRange>[23:23]</bitRange>
32829                <access>read-write</access>
32830              </field>
32831              <field>
32832                <name>ATTR_NS24</name>
32833                <description>NS bit for block 24 based on BLK_IDX</description>
32834                <bitRange>[24:24]</bitRange>
32835                <access>read-write</access>
32836              </field>
32837              <field>
32838                <name>ATTR_NS25</name>
32839                <description>NS bit for block 25 based on BLK_IDX</description>
32840                <bitRange>[25:25]</bitRange>
32841                <access>read-write</access>
32842              </field>
32843              <field>
32844                <name>ATTR_NS26</name>
32845                <description>NS bit for block 26 based on BLK_IDX</description>
32846                <bitRange>[26:26]</bitRange>
32847                <access>read-write</access>
32848              </field>
32849              <field>
32850                <name>ATTR_NS27</name>
32851                <description>NS bit for block 27 based on BLK_IDX</description>
32852                <bitRange>[27:27]</bitRange>
32853                <access>read-write</access>
32854              </field>
32855              <field>
32856                <name>ATTR_NS28</name>
32857                <description>NS bit for block 28 based on BLK_IDX</description>
32858                <bitRange>[28:28]</bitRange>
32859                <access>read-write</access>
32860              </field>
32861              <field>
32862                <name>ATTR_NS29</name>
32863                <description>NS bit for block 29 based on BLK_IDX</description>
32864                <bitRange>[29:29]</bitRange>
32865                <access>read-write</access>
32866              </field>
32867              <field>
32868                <name>ATTR_NS30</name>
32869                <description>NS bit for block 30 based on BLK_IDX</description>
32870                <bitRange>[30:30]</bitRange>
32871                <access>read-write</access>
32872              </field>
32873              <field>
32874                <name>ATTR_NS31</name>
32875                <description>NS bit for block 31 based on BLK_IDX</description>
32876                <bitRange>[31:31]</bitRange>
32877                <access>read-write</access>
32878              </field>
32879            </fields>
32880          </register>
32881          <register>
32882            <name>ROT_CTRL</name>
32883            <description>Control register with lock bit and auto-increment only</description>
32884            <addressOffset>0x200</addressOffset>
32885            <size>32</size>
32886            <access>read-write</access>
32887            <resetValue>0x100</resetValue>
32888            <resetMask>0x80000100</resetMask>
32889            <fields>
32890              <field>
32891                <name>AUTO_INC</name>
32892                <description>Auto-increment BLK_IDX by 1 for each read/write of ROT_BLK_LUT</description>
32893                <bitRange>[8:8]</bitRange>
32894                <access>read-write</access>
32895              </field>
32896              <field>
32897                <name>LOCK</name>
32898                <description>Security lockdown for the root-of-trust configuration registers. Software can set this bit but not clear it once set.  When set, write operations to ROT_BLK_LUT are not possible. Write is ignored.</description>
32899                <bitRange>[31:31]</bitRange>
32900                <access>read-write</access>
32901              </field>
32902            </fields>
32903          </register>
32904          <register>
32905            <name>ROT_CFG</name>
32906            <description>Sets block-size to match memory size (external memory only)</description>
32907            <addressOffset>0x204</addressOffset>
32908            <size>32</size>
32909            <access>read-write</access>
32910            <resetValue>0x0</resetValue>
32911            <resetMask>0xF</resetMask>
32912            <fields>
32913              <field>
32914                <name>BLOCK_SIZE</name>
32915                <description>Block size of individually protected blocks (0: 32B, 1: 64B, ...up to 15:1 MB)
32916Block size= (1&lt;&lt;(BLOCK_SIZE+5))
32917The number and size blocks in an MPC is design time configurable and for external memories defaults to covering the entire memory using 4kB blocks; see product datasheet for details on protection of external memories.</description>
32918                <bitRange>[3:0]</bitRange>
32919                <access>read-write</access>
32920              </field>
32921            </fields>
32922          </register>
32923          <register>
32924            <name>ROT_BLK_MAX</name>
32925            <description>Max value of block-based index register for ROT</description>
32926            <addressOffset>0x208</addressOffset>
32927            <size>32</size>
32928            <access>read-only</access>
32929            <resetValue>0x0</resetValue>
32930            <resetMask>0xFFFFFFFF</resetMask>
32931            <fields>
32932              <field>
32933                <name>VALUE</name>
32934                <description>Maximum value of block-based index register.  The number and size blocks in an MPC is design time configurable and for embedded memories defaults to covering the entire memory using 4kB blocks; see product datasheet for details on protection of external memories.</description>
32935                <bitRange>[31:0]</bitRange>
32936                <access>read-only</access>
32937              </field>
32938            </fields>
32939          </register>
32940          <register>
32941            <name>ROT_BLK_CFG</name>
32942            <description>Same as BLK_CFG</description>
32943            <addressOffset>0x20C</addressOffset>
32944            <size>32</size>
32945            <access>read-only</access>
32946            <resetValue>0x80000000</resetValue>
32947            <resetMask>0x8000000F</resetMask>
32948            <fields>
32949              <field>
32950                <name>BLOCK_SIZE</name>
32951                <description>Block size of individually protected blocks (0: 32B, 1: 64B, ...up to 15:1MB)
32952Block size= (1&lt;&lt;(BLOCK_SIZE+5))
32953The number and size blocks in an MPC is design time configurable and for embedded memories defaults to covering the entire memory using 4kB blocks; see product datasheet for details on protection of external memories.</description>
32954                <bitRange>[3:0]</bitRange>
32955                <access>read-only</access>
32956              </field>
32957              <field>
32958                <name>INIT_IN_PROGRESS</name>
32959                <description>During initialization INIT_IN_PROGRESS is '1' and MMIO register accesses to ROT_BLK_LUT is RAZWI. The block attributes are retained in DeepSleep (and obviously Active) power mode. Initialization is only required from a power mode in which the block attributes are not retained. E.g., initialization is required for a cold boot (after a Power-on-Reset).
32960HW initializes the block attributes: the NS attributes are set to '0' (secure), the R attributes are set to '1' (read access allowed) and the W attributes are set to '1' (write access allowed). During initialization, the MPC supports memory accesses (memory accesses are NOT blocked) with the initialization block attribute values as mentioned above. This e.g. allows MPC initialization to proceed in parallel with boot program memory accesses (as opposed to serializing the two), improving device boot time.
32961HW initializes the block attributes NS to 1 in case SECEXT = 0.</description>
32962                <bitRange>[31:31]</bitRange>
32963                <access>read-only</access>
32964              </field>
32965            </fields>
32966          </register>
32967          <register>
32968            <name>ROT_BLK_IDX</name>
32969            <description>Index of 8-block group accessed through ROT_BLK_LUT_*</description>
32970            <addressOffset>0x210</addressOffset>
32971            <size>32</size>
32972            <access>read-write</access>
32973            <resetValue>0x0</resetValue>
32974            <resetMask>0xFFFFFFFF</resetMask>
32975            <fields>
32976              <field>
32977                <name>VALUE</name>
32978                <description>Index value for accessing block-based lookup table using ROT_BLK_LUT. Programming out of LUT range is an user error and it loops back to '0' once overflow occurs.</description>
32979                <bitRange>[31:0]</bitRange>
32980                <access>read-write</access>
32981              </field>
32982            </fields>
32983          </register>
32984          <register>
32985            <name>ROT_BLK_PC</name>
32986            <description>Protection context of 8-block group accesses through ROT_BLK_LUT</description>
32987            <addressOffset>0x214</addressOffset>
32988            <size>32</size>
32989            <access>read-write</access>
32990            <resetValue>0x0</resetValue>
32991            <resetMask>0xF</resetMask>
32992            <fields>
32993              <field>
32994                <name>PC</name>
32995                <description>Specify PC values for ROT_BLK_IDX and ROT_BLK_LUT</description>
32996                <bitRange>[3:0]</bitRange>
32997                <access>read-write</access>
32998              </field>
32999            </fields>
33000          </register>
33001          <register>
33002            <name>ROT_BLK_LUT</name>
33003            <description>(R,W,NS) bits for 8 blocks at ROT_BLK_IDX for PC=ROT_BKL_PC</description>
33004            <addressOffset>0x218</addressOffset>
33005            <size>32</size>
33006            <access>read-write</access>
33007            <resetValue>0x0</resetValue>
33008            <resetMask>0x77777777</resetMask>
33009            <fields>
33010              <field>
33011                <name>ATTR0</name>
33012                <description>W/R/NS bits for block 0 indicated by ROT_BLK_IDX for ROT_BLK_PC PC</description>
33013                <bitRange>[2:0]</bitRange>
33014                <access>read-write</access>
33015              </field>
33016              <field>
33017                <name>ATTR1</name>
33018                <description>W/R/NS bits for block 1 indicated by ROT_BLK_IDX for ROT_BLK_PC PC</description>
33019                <bitRange>[6:4]</bitRange>
33020                <access>read-write</access>
33021              </field>
33022              <field>
33023                <name>ATTR2</name>
33024                <description>W/R/NS bits for block 2 indicated by ROT_BLK_IDX for ROT_BLK_PC PC</description>
33025                <bitRange>[10:8]</bitRange>
33026                <access>read-write</access>
33027              </field>
33028              <field>
33029                <name>ATTR3</name>
33030                <description>W/R/NS bits for block 3 indicated by ROT_BLK_IDX for ROT_BLK_PC PC</description>
33031                <bitRange>[14:12]</bitRange>
33032                <access>read-write</access>
33033              </field>
33034              <field>
33035                <name>ATTR4</name>
33036                <description>W/R/NS bits for block 4 indicated by ROT_BLK_IDX for ROT_BLK_PC PC</description>
33037                <bitRange>[18:16]</bitRange>
33038                <access>read-write</access>
33039              </field>
33040              <field>
33041                <name>ATTR5</name>
33042                <description>W/R/NS bits for block 5 indicated by ROT_BLK_IDX for ROT_BLK_PC PC</description>
33043                <bitRange>[22:20]</bitRange>
33044                <access>read-write</access>
33045              </field>
33046              <field>
33047                <name>ATTR6</name>
33048                <description>W/R/NS bits for block 6 indicated by ROT_BLK_IDX for ROT_BLK_PC PC</description>
33049                <bitRange>[26:24]</bitRange>
33050                <access>read-write</access>
33051              </field>
33052              <field>
33053                <name>ATTR7</name>
33054                <description>W/R/NS bits for block 7 indicated by ROT_BLK_IDX for ROT_BLK_PC PC</description>
33055                <bitRange>[30:28]</bitRange>
33056                <access>read-write</access>
33057              </field>
33058            </fields>
33059          </register>
33060        </cluster>
33061      </registers>
33062    </peripheral>
33063    <peripheral>
33064      <name>TDM0</name>
33065      <description>TDM</description>
33066      <headerStructName>TDM</headerStructName>
33067      <baseAddress>0x408C0000</baseAddress>
33068      <addressBlock>
33069        <offset>0</offset>
33070        <size>65536</size>
33071        <usage>registers</usage>
33072      </addressBlock>
33073      <registers>
33074        <cluster>
33075          <name>TDM_STRUCT</name>
33076          <description>TDM structure</description>
33077          <addressOffset>0x00008000</addressOffset>
33078          <cluster>
33079            <name>TDM_TX_STRUCT</name>
33080            <description>TDM TX structure</description>
33081            <addressOffset>0x00000000</addressOffset>
33082            <register>
33083              <name>TX_CTL</name>
33084              <description>TX control</description>
33085              <addressOffset>0x0</addressOffset>
33086              <size>32</size>
33087              <access>read-write</access>
33088              <resetValue>0x10000</resetValue>
33089              <resetMask>0x8001300F</resetMask>
33090              <fields>
33091                <field>
33092                  <name>WORD_SIZE</name>
33093                  <description>PCM word size:
33094'0': 8 bit.
33095'1': 10 bit.
33096'2': 12 bit.
33097'3': 14 bit.
33098'4': 16 bit.
33099'5': 18 bit.
33100'6': 20 bit.
33101'7': 24 bit.
33102'8': 32 bit.
33103'9'-'15': Undefined.</description>
33104                  <bitRange>[3:0]</bitRange>
33105                  <access>read-write</access>
33106                  <enumeratedValues>
33107                    <enumeratedValue>
33108                      <name>SIZE_8</name>
33109                      <description>N/A</description>
33110                      <value>0</value>
33111                    </enumeratedValue>
33112                    <enumeratedValue>
33113                      <name>SIZE_10</name>
33114                      <description>N/A</description>
33115                      <value>1</value>
33116                    </enumeratedValue>
33117                    <enumeratedValue>
33118                      <name>SIZE_12</name>
33119                      <description>N/A</description>
33120                      <value>2</value>
33121                    </enumeratedValue>
33122                    <enumeratedValue>
33123                      <name>SIZE_14</name>
33124                      <description>N/A</description>
33125                      <value>3</value>
33126                    </enumeratedValue>
33127                    <enumeratedValue>
33128                      <name>SIZE_16</name>
33129                      <description>N/A</description>
33130                      <value>4</value>
33131                    </enumeratedValue>
33132                    <enumeratedValue>
33133                      <name>SIZE_18</name>
33134                      <description>N/A</description>
33135                      <value>5</value>
33136                    </enumeratedValue>
33137                    <enumeratedValue>
33138                      <name>SIZE_20</name>
33139                      <description>N/A</description>
33140                      <value>6</value>
33141                    </enumeratedValue>
33142                    <enumeratedValue>
33143                      <name>SIZE_24</name>
33144                      <description>N/A</description>
33145                      <value>7</value>
33146                    </enumeratedValue>
33147                    <enumeratedValue>
33148                      <name>SIZE_32</name>
33149                      <description>N/A</description>
33150                      <value>8</value>
33151                    </enumeratedValue>
33152                  </enumeratedValues>
33153                </field>
33154                <field>
33155                  <name>FORMAT</name>
33156                  <description>Format:
33157'0': Left-aligned delayed.
33158'1': Left-aligned.
33159'2': Right-aligned delayed.
33160'3': Right-aligned.</description>
33161                  <bitRange>[13:12]</bitRange>
33162                  <access>read-write</access>
33163                  <enumeratedValues>
33164                    <enumeratedValue>
33165                      <name>LEFT_DELAYED</name>
33166                      <description>N/A</description>
33167                      <value>0</value>
33168                    </enumeratedValue>
33169                    <enumeratedValue>
33170                      <name>LEFT</name>
33171                      <description>N/A</description>
33172                      <value>1</value>
33173                    </enumeratedValue>
33174                    <enumeratedValue>
33175                      <name>RIGHT_DELAYED</name>
33176                      <description>N/A</description>
33177                      <value>2</value>
33178                    </enumeratedValue>
33179                    <enumeratedValue>
33180                      <name>RIGHT</name>
33181                      <description>N/A</description>
33182                      <value>3</value>
33183                    </enumeratedValue>
33184                  </enumeratedValues>
33185                </field>
33186                <field>
33187                  <name>MS</name>
33188                  <description>Master/slave setting:
33189'0': Slave.
33190- External transmitter 'tdm_tx_sck_in' and transmitter 'tdm_tx_fsync_in'.
33191'1': Master.
33192- Interface clock 'clk_if' is used to generate transmitter 'tdm_tx_sck_out' and transmitter 'tdm_tx_fsync_out'.</description>
33193                  <bitRange>[16:16]</bitRange>
33194                  <access>read-write</access>
33195                  <enumeratedValues>
33196                    <enumeratedValue>
33197                      <name>SLAVE</name>
33198                      <description>N/A</description>
33199                      <value>0</value>
33200                    </enumeratedValue>
33201                    <enumeratedValue>
33202                      <name>MASTER</name>
33203                      <description>N/A</description>
33204                      <value>1</value>
33205                    </enumeratedValue>
33206                  </enumeratedValues>
33207                </field>
33208                <field>
33209                  <name>ENABLED</name>
33210                  <description>Transmitter (TX) enable:
33211'0': Disabled. All non-retained MMIO registers (e.g. the TX_FIFO_STATUS and INTR_TX registers) have their fields reset to their default value.
33212'1': Enabled.
33213
33214Note: when all transmitters and receivers are disabled, the SRAMs are driven into low power mode, if supported by the SRAM. When exiting such low power mode software needs to allow for a certain power up time before SRAM can be used, i.e. before ACTIVE can be asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register (or equivalent for platforms other than MXS40).</description>
33215                  <bitRange>[31:31]</bitRange>
33216                  <access>read-write</access>
33217                </field>
33218              </fields>
33219            </register>
33220            <register>
33221              <name>TX_IF_CTL</name>
33222              <description>TX interface control</description>
33223              <addressOffset>0x10</addressOffset>
33224              <size>32</size>
33225              <access>read-write</access>
33226              <resetValue>0x1F018707</resetValue>
33227              <resetMask>0x9F1FB7FF</resetMask>
33228              <fields>
33229                <field>
33230                  <name>CLOCK_DIV</name>
33231                  <description>Interface clock divider (legal range [1, 255]). The TDM interface 'tdm_tx_sck_out' output signal is defined as clk_if / (CLOCK_DIV + 1). CLOCK_DIV should be set to an odd value ({1, 3, 5, ..., 255}), to ensure a 50/50 percent duty cycle  clock.
33232
33233Note: Used in master configuration only.</description>
33234                  <bitRange>[7:0]</bitRange>
33235                  <access>read-write</access>
33236                </field>
33237                <field>
33238                  <name>CLOCK_SEL</name>
33239                  <description>Interface clock 'clk_if' selection:
33240'0': SRSS clock clk_if_srss[0].
33241'1': SRSS clock clk_if_srss[1].
33242'2': SRSS clock clk_if_srss[2].
33243'3': SRSS clock clk_if_srss[3].
33244'4': Master interface clock 'tdm_tx_mck_in'.
33245'5'-'7': undefined.
33246
33247Note: the application is always required to program this field to a value different from the default.</description>
33248                  <bitRange>[10:8]</bitRange>
33249                  <access>read-write</access>
33250                  <enumeratedValues>
33251                    <enumeratedValue>
33252                      <name>SEL_SRSS_CLOCK0</name>
33253                      <description>N/A</description>
33254                      <value>0</value>
33255                    </enumeratedValue>
33256                    <enumeratedValue>
33257                      <name>SEL_SRSS_CLOCK1</name>
33258                      <description>N/A</description>
33259                      <value>1</value>
33260                    </enumeratedValue>
33261                    <enumeratedValue>
33262                      <name>SEL_SRSS_CLOCK2</name>
33263                      <description>N/A</description>
33264                      <value>2</value>
33265                    </enumeratedValue>
33266                    <enumeratedValue>
33267                      <name>SEL_SRSS_CLOCK3</name>
33268                      <description>N/A</description>
33269                      <value>3</value>
33270                    </enumeratedValue>
33271                    <enumeratedValue>
33272                      <name>SEL_TDM_TX_MCK_IN</name>
33273                      <description>N/A</description>
33274                      <value>4</value>
33275                    </enumeratedValue>
33276                  </enumeratedValues>
33277                </field>
33278                <field>
33279                  <name>SCK_POLARITY</name>
33280                  <description>Clock polarity:
33281'0': Clock signal is used 'as is'.
33282'1': Clock signal is inverted.
33283
33284Note: Used in BOTH master and slave configurations.</description>
33285                  <bitRange>[12:12]</bitRange>
33286                  <access>read-write</access>
33287                </field>
33288                <field>
33289                  <name>FSYNC_POLARITY</name>
33290                  <description>Channel synchronization polarity:
33291'0': Channel synchronization signal is used 'as is'.
33292'1': Channel synchronization signal is inverted.
33293
33294Note: Used in BOTH master and slave configurations.</description>
33295                  <bitRange>[13:13]</bitRange>
33296                  <access>read-write</access>
33297                </field>
33298                <field>
33299                  <name>FSYNC_FORMAT</name>
33300                  <description>Channel synchronization pulse format:
33301'0': Duration of a single bit period.
33302'1': Duration of the first channel.</description>
33303                  <bitRange>[15:15]</bitRange>
33304                  <access>read-write</access>
33305                  <enumeratedValues>
33306                    <enumeratedValue>
33307                      <name>BIT_PERIOD</name>
33308                      <description>N/A</description>
33309                      <value>0</value>
33310                    </enumeratedValue>
33311                    <enumeratedValue>
33312                      <name>CH_PERIOD</name>
33313                      <description>N/A</description>
33314                      <value>1</value>
33315                    </enumeratedValue>
33316                  </enumeratedValues>
33317                </field>
33318                <field>
33319                  <name>CH_NR</name>
33320                  <description>Number of channels in the frame:
33321'0': Undefined/illegal.
33322'1': 2 channels.
33323'2': 3 channels.
33324...
33325'31': 32 channels.
33326
33327Note: the field value chould be less than CH_NR (the number of support channels).
33328
33329Note: the TX_CH_CTL.CH_EN fields can be used to enable/disable indvidual channels.</description>
33330                  <bitRange>[20:16]</bitRange>
33331                  <access>read-write</access>
33332                </field>
33333                <field>
33334                  <name>CH_SIZE</name>
33335                  <description>Channel size:
33336'0'-'2': Undefined/illegal.
33337'3': 4 bits.
33338...
33339'31': 32 bits.
33340
33341Note: if TX_CTL.WORD_SIZE is greater than CH_SIZE, the more significant bits of the word are transmitted and the lesser significant bits of the word are dropped.</description>
33342                  <bitRange>[28:24]</bitRange>
33343                  <access>read-write</access>
33344                  <enumeratedValues>
33345                    <enumeratedValue>
33346                      <name>SIZE_1</name>
33347                      <description>N/A</description>
33348                      <value>0</value>
33349                    </enumeratedValue>
33350                    <enumeratedValue>
33351                      <name>SIZE_2</name>
33352                      <description>N/A</description>
33353                      <value>1</value>
33354                    </enumeratedValue>
33355                    <enumeratedValue>
33356                      <name>SIZE_32</name>
33357                      <description>N/A</description>
33358                      <value>31</value>
33359                    </enumeratedValue>
33360                  </enumeratedValues>
33361                </field>
33362                <field>
33363                  <name>I2S_MODE</name>
33364                  <description>I2S mode setting:
33365'0': TDM mode.
33366'1': I2S mode.</description>
33367                  <bitRange>[31:31]</bitRange>
33368                  <access>read-write</access>
33369                  <enumeratedValues>
33370                    <enumeratedValue>
33371                      <name>TDM</name>
33372                      <description>N/A</description>
33373                      <value>0</value>
33374                    </enumeratedValue>
33375                    <enumeratedValue>
33376                      <name>I2S</name>
33377                      <description>N/A</description>
33378                      <value>1</value>
33379                    </enumeratedValue>
33380                  </enumeratedValues>
33381                </field>
33382              </fields>
33383            </register>
33384            <register>
33385              <name>TX_CH_CTL</name>
33386              <description>TX channel control</description>
33387              <addressOffset>0x14</addressOffset>
33388              <size>32</size>
33389              <access>read-write</access>
33390              <resetValue>0x0</resetValue>
33391              <resetMask>0xFFFFFFFF</resetMask>
33392              <fields>
33393                <field>
33394                  <name>CH_EN</name>
33395                  <description>Channel enables: channel i is controlled by CH_EN[i].
33396'0': Disabled. The TX FIFO does not produce channel i words and the transmitted channel i words on the interface are not driven (the output enable of the 'tdm_tx_sd_out' output signal is not driven).
33397'1': Enabled.
33398
33399Note: Only bit 0 through TX_IF_CTL.CH_NR may be set to '1'; i.e. only channels that are present in the frame can be enabled.</description>
33400                  <bitRange>[31:0]</bitRange>
33401                  <access>read-write</access>
33402                </field>
33403              </fields>
33404            </register>
33405            <register>
33406              <name>TX_TEST_CTL</name>
33407              <description>TX test control</description>
33408              <addressOffset>0x20</addressOffset>
33409              <size>32</size>
33410              <access>read-write</access>
33411              <resetValue>0x0</resetValue>
33412              <resetMask>0x80000000</resetMask>
33413              <fields>
33414                <field>
33415                  <name>ENABLED</name>
33416                  <description>Test mode enable.
33417'0': Disabled. Functional mode.
33418- Transmitter tx_sck_in = IOSS tdm_tx_sck_in.
33419- Transmitter tx_fsync_in = IOSS tdm_tx_fsync_in.
33420- Receiver rx_sd_in = IOSS tdm_rx_sd_in.
33421'1': Enabled. Test mode (intended to be used with (slave transmitter, master receiver) configuration).
33422- Transmitter tx_sck_in = Receiver tdm_rx_sck_out.
33423- Transmitter tx_fsync_in = Receiver tdm_rx_fsync_out.
33424- Receiver rx_sd_in = Transmitter tdm_tx_sd_out.
33425
33426Note: TX_TEST_CTL.ENABLED and RX_TEST_CTL.ENABLED should not be set to '1' simultaneously.</description>
33427                  <bitRange>[31:31]</bitRange>
33428                  <access>read-write</access>
33429                  <enumeratedValues>
33430                    <enumeratedValue>
33431                      <name>FUNCTIONAL</name>
33432                      <description>N/A</description>
33433                      <value>0</value>
33434                    </enumeratedValue>
33435                    <enumeratedValue>
33436                      <name>TEST</name>
33437                      <description>N/A</description>
33438                      <value>1</value>
33439                    </enumeratedValue>
33440                  </enumeratedValues>
33441                </field>
33442              </fields>
33443            </register>
33444            <register>
33445              <name>TX_ROUTE_CTL</name>
33446              <description>TX route control</description>
33447              <addressOffset>0x24</addressOffset>
33448              <size>32</size>
33449              <access>read-write</access>
33450              <resetValue>0x0</resetValue>
33451              <resetMask>0x3</resetMask>
33452              <fields>
33453                <field>
33454                  <name>MODE</name>
33455                  <description>Controls routing to the TX slave signalling inputs (FSYNC/SCK):
33456'0': TX slave signaling indipendent from RX signaling:
33457- Transmitter tx_sck_in = IOSS tdm_tx_sck_in
33458- Transmitter tx_fsync_in = IOSS tdm_tx_fsync_in
33459'1': TX slave signalling inputs driven by RX Slave:
33460- Transmitter tx_sck_in = IOSS tdm_rx_sck_in
33461- Transmitter tx_fsync_in = IOSS tdm_rx_fsync_in
33462'2': TX slave signalling inputs driven by RX Master:
33463- Transmitter tx_sck_in = receiver tdm_rx_sck_out
33464- Transmitter tx_fsync_in = receiver tdm_rx_fsync_out
33465
33466Note: MODE=0 is the default behaviour. MODE=1 or 2 is intended to allow the TX slave to share the same signaling used by the RX. This feature can be used to reduce the number of IO pins necessary to connect to an external codec supporting common TX/RX signaling.
33467
33468Note: when MODE=1 or 2, TX_TEST_CTL.ENABLED and RX_TEST_CTL.ENABLED should not be set to '1'.</description>
33469                  <bitRange>[1:0]</bitRange>
33470                  <access>read-write</access>
33471                  <enumeratedValues>
33472                    <enumeratedValue>
33473                      <name>TX_IN_DRIVEN_BY_IOSS_TX_IN</name>
33474                      <description>N/A</description>
33475                      <value>0</value>
33476                    </enumeratedValue>
33477                    <enumeratedValue>
33478                      <name>TX_IN_DRIVEN_BY_IOSS_RX_IN</name>
33479                      <description>N/A</description>
33480                      <value>1</value>
33481                    </enumeratedValue>
33482                    <enumeratedValue>
33483                      <name>TX_IN_DRIVEN_BY_RX_OUT</name>
33484                      <description>N/A</description>
33485                      <value>2</value>
33486                    </enumeratedValue>
33487                  </enumeratedValues>
33488                </field>
33489              </fields>
33490            </register>
33491            <register>
33492              <name>TX_FIFO_CTL</name>
33493              <description>TX FIFO control</description>
33494              <addressOffset>0x80</addressOffset>
33495              <size>32</size>
33496              <access>read-write</access>
33497              <resetValue>0x0</resetValue>
33498              <resetMask>0xF007F</resetMask>
33499              <fields>
33500                <field>
33501                  <name>TRIGGER_LEVEL</name>
33502                  <description>Trigger level. When the TX FIFO has less entries than the number of this field, a transmitter trigger event is generated:
33503- INTR_TX.FIFO_TRIGGER = (# FIFO entries &lt; TRIGGER_LEVEL)</description>
33504                  <bitRange>[6:0]</bitRange>
33505                  <access>read-write</access>
33506                </field>
33507                <field>
33508                  <name>MUTE</name>
33509                  <description>Mute functionality:
33510'0': HW uses TX FIFO data.
33511'1': HW uses a constant PCM data value of '0'. Mute does advance the FIFO read pointer.
33512
33513Note: HW ensures that mute functionality synchronizes on the first channel of a frame to ensure that either all or none of the frame's channels are muted.</description>
33514                  <bitRange>[16:16]</bitRange>
33515                  <access>read-write</access>
33516                </field>
33517                <field>
33518                  <name>FREEZE</name>
33519                  <description>Freeze functionality:
33520'0': HW uses TX FIFO data and advances the FIFO read pointer.
33521'1': HW uses a constant PCM data value of '0' or the previous channel PCM data is replayed. Freeze does not advance the FIFO read pointer (the FIFO data is not used).
33522
33523Note: HW ensures that freeze functionality synchronizes on the first channel of a frame to ensure that PCM data of one channel is not misassigned to another channel. As a result, the freeze functionality can be activated at any time.
33524
33525Note: This functionality is intended for debugging purposes.</description>
33526                  <bitRange>[17:17]</bitRange>
33527                  <access>read-write</access>
33528                </field>
33529                <field>
33530                  <name>ACTIVE</name>
33531                  <description>Activate functionality:
33532'0': Transmitter off. The FIFO_UNDERFLOW interrupt cause will not be activated.
33533'1': Transmitter on. The FIFO_UNDERFLOW interrupt may be activated (when an underflow event occurs).
33534
33535Note: This functionality is intended for startup purposes.</description>
33536                  <bitRange>[18:18]</bitRange>
33537                  <access>read-write</access>
33538                </field>
33539                <field>
33540                  <name>REPLAY</name>
33541                  <description>Replay functionality (used when FREEZE is '1' or in case of a FIFO underflow event):
33542'0': HW uses a constant PCM data value of '0'.
33543'1': HW uses the previous PCM data value.</description>
33544                  <bitRange>[19:19]</bitRange>
33545                  <access>read-write</access>
33546                </field>
33547              </fields>
33548            </register>
33549            <register>
33550              <name>TX_FIFO_STATUS</name>
33551              <description>TX FIFO status</description>
33552              <addressOffset>0x84</addressOffset>
33553              <size>32</size>
33554              <access>read-only</access>
33555              <resetValue>0x0</resetValue>
33556              <resetMask>0x7F7F00FF</resetMask>
33557              <fields>
33558                <field>
33559                  <name>USED</name>
33560                  <description>Number of used/occupied entries in the TX FIFO. The field value is in the range [0, 128]. When '0', the FIFO is empty. When '128', the FIFO is full.</description>
33561                  <bitRange>[7:0]</bitRange>
33562                  <access>read-only</access>
33563                </field>
33564                <field>
33565                  <name>RD_PTR</name>
33566                  <description>TX FIFO read pointer: FIFO location from which a data is read.
33567
33568Note: This functionality is intended for debugging purposes.</description>
33569                  <bitRange>[22:16]</bitRange>
33570                  <access>read-only</access>
33571                </field>
33572                <field>
33573                  <name>WR_PTR</name>
33574                  <description>TX FIFO write pointer: FIFO location at which a new data is written by the hardware.
33575
33576Note: This functionality is intended for debugging purposes.</description>
33577                  <bitRange>[30:24]</bitRange>
33578                  <access>read-only</access>
33579                </field>
33580              </fields>
33581            </register>
33582            <register>
33583              <name>TX_FIFO_WR</name>
33584              <description>TX FIFO write</description>
33585              <addressOffset>0x88</addressOffset>
33586              <size>32</size>
33587              <access>write-only</access>
33588              <resetValue>0x0</resetValue>
33589              <resetMask>0xFFFFFFFF</resetMask>
33590              <fields>
33591                <field>
33592                  <name>DATA</name>
33593                  <description>Data (PCM sample) written to the TX FIFO. Writing adds the data to the TX FIFO; i.e. behavior is similar to that of a PUSH operation (TX_FIFO_STATUS.WR_PTR is incremented and TX_FIFO_STATUS.USED is incremented). The write data (DATA) should be right aligned when it is written to the FIFO entry (data[31:0]):
33594- 8 bit, data[31:0] = DATA[7:0] &lt;&lt; 24.
33595- 10 bit, data[31:0] = DATA[9:0] &lt;&lt; 22.
33596- 12 bit, data[31:0] = DATA[11:0] &lt;&lt; 20.
33597- 14 bit, data[31:0] = DATA[13:0] &lt;&lt; 18.
33598- 16 bit, data[31:0] = DATA[15:0] &lt;&lt; 16.
33599- 18 bit, data[31:0] = DATA[17:0] &lt;&lt; 14.
33600- 20 bit, data[31:0] = DATA[19:0] &lt;&lt; 12.
33601- 24 bit, data[31:0] = DATA[23:0] &lt;&lt; 8.
33602- 32 bit, data[31:0] = DATA[31:0].
33603
33604Note: Writing to a full TX FIFO activates INTR.TX_FIFO_OVERFLOW.</description>
33605                  <bitRange>[31:0]</bitRange>
33606                  <access>write-only</access>
33607                </field>
33608              </fields>
33609            </register>
33610            <register>
33611              <name>INTR_TX</name>
33612              <description>Interrupt</description>
33613              <addressOffset>0xC0</addressOffset>
33614              <size>32</size>
33615              <access>read-write</access>
33616              <resetValue>0x0</resetValue>
33617              <resetMask>0x107</resetMask>
33618              <fields>
33619                <field>
33620                  <name>FIFO_TRIGGER</name>
33621                  <description>HW sets this field to '1', when a TX trigger is generated.</description>
33622                  <bitRange>[0:0]</bitRange>
33623                  <access>read-write</access>
33624                </field>
33625                <field>
33626                  <name>FIFO_OVERFLOW</name>
33627                  <description>HW sets this field to '1', when writing to a full TX FIFO (TX_FIFO_STATUS.USED is '128').</description>
33628                  <bitRange>[1:1]</bitRange>
33629                  <access>read-write</access>
33630                </field>
33631                <field>
33632                  <name>FIFO_UNDERFLOW</name>
33633                  <description>HW sets this field to '1', when reading from an (almost) empty TX FIFO (TX_FIFO_STATUS.USED &lt; 'number of enabled channels per frame'). This is referred to as an underflow event.
33634
33635Note: HW ensures that either all or none of the frame's channels are transmitted. In a TX FIFO underflow situation, HW replays previous PCM data or uses a constant PCM data value of '0'.</description>
33636                  <bitRange>[2:2]</bitRange>
33637                  <access>read-write</access>
33638                </field>
33639                <field>
33640                  <name>IF_UNDERFLOW</name>
33641                  <description>HW sets this field to '1', when PCM samples are not generated in time for the interface logic (interface underflow). This may be an indication that the IP system frequency is too low wrt. the interface frequency (a SW configuration error). The interface underflow is a non-recoverable error and requires SW disabling of the channel (a SW write to INTR_TX.IF_UNDERFLOW does not resolve the interface underflow).
33642
33643Note: This functionality is intended for debug purposes.</description>
33644                  <bitRange>[8:8]</bitRange>
33645                  <access>read-write</access>
33646                </field>
33647              </fields>
33648            </register>
33649            <register>
33650              <name>INTR_TX_SET</name>
33651              <description>Interrupt set</description>
33652              <addressOffset>0xC4</addressOffset>
33653              <size>32</size>
33654              <access>read-write</access>
33655              <resetValue>0x0</resetValue>
33656              <resetMask>0x107</resetMask>
33657              <fields>
33658                <field>
33659                  <name>FIFO_TRIGGER</name>
33660                  <description>Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect).</description>
33661                  <bitRange>[0:0]</bitRange>
33662                  <access>read-write</access>
33663                </field>
33664                <field>
33665                  <name>FIFO_OVERFLOW</name>
33666                  <description>Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect).</description>
33667                  <bitRange>[1:1]</bitRange>
33668                  <access>read-write</access>
33669                </field>
33670                <field>
33671                  <name>FIFO_UNDERFLOW</name>
33672                  <description>Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect).</description>
33673                  <bitRange>[2:2]</bitRange>
33674                  <access>read-write</access>
33675                </field>
33676                <field>
33677                  <name>IF_UNDERFLOW</name>
33678                  <description>Write this field with '1' to set corresponding INTR_TX field (a write of '0' has no effect).</description>
33679                  <bitRange>[8:8]</bitRange>
33680                  <access>read-write</access>
33681                </field>
33682              </fields>
33683            </register>
33684            <register>
33685              <name>INTR_TX_MASK</name>
33686              <description>Interrupt mask</description>
33687              <addressOffset>0xC8</addressOffset>
33688              <size>32</size>
33689              <access>read-write</access>
33690              <resetValue>0x0</resetValue>
33691              <resetMask>0x107</resetMask>
33692              <fields>
33693                <field>
33694                  <name>FIFO_TRIGGER</name>
33695                  <description>Mask for corresponding field in INTR_TX register.</description>
33696                  <bitRange>[0:0]</bitRange>
33697                  <access>read-write</access>
33698                </field>
33699                <field>
33700                  <name>FIFO_OVERFLOW</name>
33701                  <description>Mask for corresponding field in INTR_TX register.</description>
33702                  <bitRange>[1:1]</bitRange>
33703                  <access>read-write</access>
33704                </field>
33705                <field>
33706                  <name>FIFO_UNDERFLOW</name>
33707                  <description>Mask for corresponding field in INTR_TX register.</description>
33708                  <bitRange>[2:2]</bitRange>
33709                  <access>read-write</access>
33710                </field>
33711                <field>
33712                  <name>IF_UNDERFLOW</name>
33713                  <description>Mask for corresponding field in INTR_TX register.</description>
33714                  <bitRange>[8:8]</bitRange>
33715                  <access>read-write</access>
33716                </field>
33717              </fields>
33718            </register>
33719            <register>
33720              <name>INTR_TX_MASKED</name>
33721              <description>Interrupt masked</description>
33722              <addressOffset>0xCC</addressOffset>
33723              <size>32</size>
33724              <access>read-only</access>
33725              <resetValue>0x0</resetValue>
33726              <resetMask>0x107</resetMask>
33727              <fields>
33728                <field>
33729                  <name>FIFO_TRIGGER</name>
33730                  <description>Logical AND of corresponding INTR_TX and INTR_TX_MASK fields.</description>
33731                  <bitRange>[0:0]</bitRange>
33732                  <access>read-only</access>
33733                </field>
33734                <field>
33735                  <name>FIFO_OVERFLOW</name>
33736                  <description>Logical AND of corresponding INTR_TX and INTR_TX_MASK fields.</description>
33737                  <bitRange>[1:1]</bitRange>
33738                  <access>read-only</access>
33739                </field>
33740                <field>
33741                  <name>FIFO_UNDERFLOW</name>
33742                  <description>Logical AND of corresponding INTR_TX and INTR_TX_MASK fields.</description>
33743                  <bitRange>[2:2]</bitRange>
33744                  <access>read-only</access>
33745                </field>
33746                <field>
33747                  <name>IF_UNDERFLOW</name>
33748                  <description>Logical AND of corresponding INTR_TX and INTR_TX_MASK fields.</description>
33749                  <bitRange>[8:8]</bitRange>
33750                  <access>read-only</access>
33751                </field>
33752              </fields>
33753            </register>
33754          </cluster>
33755          <cluster>
33756            <name>TDM_RX_STRUCT</name>
33757            <description>TDM RX structure</description>
33758            <addressOffset>0x00000100</addressOffset>
33759            <register>
33760              <name>RX_CTL</name>
33761              <description>RX control</description>
33762              <addressOffset>0x0</addressOffset>
33763              <size>32</size>
33764              <access>read-write</access>
33765              <resetValue>0x100</resetValue>
33766              <resetMask>0x8001310F</resetMask>
33767              <fields>
33768                <field>
33769                  <name>WORD_SIZE</name>
33770                  <description>PCM word size:
33771'0': 8 bit.
33772'1': 10 bit.
33773'2': 12 bit.
33774'3': 14 bit.
33775'4': 16 bit.
33776'5': 18 bit.
33777'6': 20 bit.
33778'7': 24 bit.
33779'8': 32 bit.
33780'9'-'15': Undefined.</description>
33781                  <bitRange>[3:0]</bitRange>
33782                  <access>read-write</access>
33783                  <enumeratedValues>
33784                    <enumeratedValue>
33785                      <name>SIZE_8</name>
33786                      <description>N/A</description>
33787                      <value>0</value>
33788                    </enumeratedValue>
33789                    <enumeratedValue>
33790                      <name>SIZE_10</name>
33791                      <description>N/A</description>
33792                      <value>1</value>
33793                    </enumeratedValue>
33794                    <enumeratedValue>
33795                      <name>SIZE_12</name>
33796                      <description>N/A</description>
33797                      <value>2</value>
33798                    </enumeratedValue>
33799                    <enumeratedValue>
33800                      <name>SIZE_14</name>
33801                      <description>N/A</description>
33802                      <value>3</value>
33803                    </enumeratedValue>
33804                    <enumeratedValue>
33805                      <name>SIZE_16</name>
33806                      <description>N/A</description>
33807                      <value>4</value>
33808                    </enumeratedValue>
33809                    <enumeratedValue>
33810                      <name>SIZE_18</name>
33811                      <description>N/A</description>
33812                      <value>5</value>
33813                    </enumeratedValue>
33814                    <enumeratedValue>
33815                      <name>SIZE_20</name>
33816                      <description>N/A</description>
33817                      <value>6</value>
33818                    </enumeratedValue>
33819                    <enumeratedValue>
33820                      <name>SIZE_24</name>
33821                      <description>N/A</description>
33822                      <value>7</value>
33823                    </enumeratedValue>
33824                    <enumeratedValue>
33825                      <name>SIZE_32</name>
33826                      <description>N/A</description>
33827                      <value>8</value>
33828                    </enumeratedValue>
33829                  </enumeratedValues>
33830                </field>
33831                <field>
33832                  <name>WORD_SIGN_EXTEND</name>
33833                  <description>Word extension:
33834'0': zero extension.
33835'1': sign extension.</description>
33836                  <bitRange>[8:8]</bitRange>
33837                  <access>read-write</access>
33838                  <enumeratedValues>
33839                    <enumeratedValue>
33840                      <name>ZERO_EXTEND</name>
33841                      <description>N/A</description>
33842                      <value>0</value>
33843                    </enumeratedValue>
33844                    <enumeratedValue>
33845                      <name>SIGN_EXTEND</name>
33846                      <description>N/A</description>
33847                      <value>1</value>
33848                    </enumeratedValue>
33849                  </enumeratedValues>
33850                </field>
33851                <field>
33852                  <name>FORMAT</name>
33853                  <description>Format:
33854'0': Left-aligned delayed.
33855'1': Left-aligned.
33856'2': Right-aligned delayed.
33857'3': Right-aligned.</description>
33858                  <bitRange>[13:12]</bitRange>
33859                  <access>read-write</access>
33860                  <enumeratedValues>
33861                    <enumeratedValue>
33862                      <name>LEFT_DELAYED</name>
33863                      <description>N/A</description>
33864                      <value>0</value>
33865                    </enumeratedValue>
33866                    <enumeratedValue>
33867                      <name>LEFT</name>
33868                      <description>N/A</description>
33869                      <value>1</value>
33870                    </enumeratedValue>
33871                    <enumeratedValue>
33872                      <name>RIGHT_DELAYED</name>
33873                      <description>N/A</description>
33874                      <value>2</value>
33875                    </enumeratedValue>
33876                    <enumeratedValue>
33877                      <name>RIGHT</name>
33878                      <description>N/A</description>
33879                      <value>3</value>
33880                    </enumeratedValue>
33881                  </enumeratedValues>
33882                </field>
33883                <field>
33884                  <name>MS</name>
33885                  <description>Master/slave setting:
33886'0': Slave.
33887- External receiver 'tdm_rx_sck_in' and receiver 'tdm_rx_fsync_in'.
33888'1': Master.
33889- Interface clock 'clk_if' is used to generate receiver 'tdm_rx_sck_out' and receiver 'tdm_rx_fsync_out'.</description>
33890                  <bitRange>[16:16]</bitRange>
33891                  <access>read-write</access>
33892                  <enumeratedValues>
33893                    <enumeratedValue>
33894                      <name>SLAVE</name>
33895                      <description>N/A</description>
33896                      <value>0</value>
33897                    </enumeratedValue>
33898                    <enumeratedValue>
33899                      <name>MASTER</name>
33900                      <description>N/A</description>
33901                      <value>1</value>
33902                    </enumeratedValue>
33903                  </enumeratedValues>
33904                </field>
33905                <field>
33906                  <name>ENABLED</name>
33907                  <description>Receiver (RX) enable:
33908'0': Disabled. All non-retained MMIO registers (e.g. the RX_FIFO_STATUS and INTR_RX registers) have their fields reset to their default value.
33909'1': Enabled.
33910
33911Note: when all transmitters and receivers are disabled, the SRAMs are driven into low power mode, if supported by the SRAM. When exiting such low power mode software needs to allow for a certain power up time before SRAM can be used, i.e. before ACTIVE can be asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register (or equivalent for platforms other than MXS40).</description>
33912                  <bitRange>[31:31]</bitRange>
33913                  <access>read-write</access>
33914                </field>
33915              </fields>
33916            </register>
33917            <register>
33918              <name>RX_IF_CTL</name>
33919              <description>RX interface control</description>
33920              <addressOffset>0x10</addressOffset>
33921              <size>32</size>
33922              <access>read-write</access>
33923              <resetValue>0x1F018707</resetValue>
33924              <resetMask>0xFF1FF7FF</resetMask>
33925              <fields>
33926                <field>
33927                  <name>CLOCK_DIV</name>
33928                  <description>Interface clock divider (legal range [1, 255]). The TDM interface 'tdm_rx_sck_out' output signals is defined as clk_if / (CLOCK_DIV + 1). CLOCK_DIV should be set to an odd value ({1, 3, 5, ..., 255}), to ensure a 50/50 percent duty cycle  clock.
33929
33930Note: Used in master configuration only.
33931
33932Note: Due to delays in the IO SubSystem (specifically the IO cells), the maximum TDM interface clock 'tdm_rx_sck_out' may be restricted. As a result, the maximum bitrate is less than the theoretical maximum (32 channels, 32 bits per channel and a high Fs of e.g. 48 kHz). This restriction is most applicable to the master, receiver configuration.</description>
33933                  <bitRange>[7:0]</bitRange>
33934                  <access>read-write</access>
33935                </field>
33936                <field>
33937                  <name>CLOCK_SEL</name>
33938                  <description>Interface clock 'clk_if' selection:
33939'0': SRSS clock clk_if_srss[0].
33940'1': SRSS clock clk_if_srss[1].
33941'2': SRSS clock clk_if_srss[2].
33942'3': SRSS clock clk_if_srss[3].
33943'4': Master interface clock 'tdm_rx_mck_in'.
33944'5'-'7': undefined.
33945
33946Note: the application is always required to program this field to a value different from the default.</description>
33947                  <bitRange>[10:8]</bitRange>
33948                  <access>read-write</access>
33949                  <enumeratedValues>
33950                    <enumeratedValue>
33951                      <name>SEL_SRSS_CLOCK0</name>
33952                      <description>N/A</description>
33953                      <value>0</value>
33954                    </enumeratedValue>
33955                    <enumeratedValue>
33956                      <name>SEL_SRSS_CLOCK1</name>
33957                      <description>N/A</description>
33958                      <value>1</value>
33959                    </enumeratedValue>
33960                    <enumeratedValue>
33961                      <name>SEL_SRSS_CLOCK2</name>
33962                      <description>N/A</description>
33963                      <value>2</value>
33964                    </enumeratedValue>
33965                    <enumeratedValue>
33966                      <name>SEL_SRSS_CLOCK3</name>
33967                      <description>N/A</description>
33968                      <value>3</value>
33969                    </enumeratedValue>
33970                    <enumeratedValue>
33971                      <name>SEL_TDM_RX_MCK_IN</name>
33972                      <description>N/A</description>
33973                      <value>4</value>
33974                    </enumeratedValue>
33975                  </enumeratedValues>
33976                </field>
33977                <field>
33978                  <name>SCK_POLARITY</name>
33979                  <description>Clock polarity:
33980'0': Clock signal is used 'as is'.
33981'1': Clock signal is inverted.
33982
33983Note: Used in BOTH master and slave configurations.</description>
33984                  <bitRange>[12:12]</bitRange>
33985                  <access>read-write</access>
33986                </field>
33987                <field>
33988                  <name>FSYNC_POLARITY</name>
33989                  <description>Channel synchronization polarity:
33990'0': Channel synchronization signal is used 'as is'.
33991'1': Channel synchronization signal is inverted.
33992
33993Note: Used in BOTH master and slave configurations.</description>
33994                  <bitRange>[13:13]</bitRange>
33995                  <access>read-write</access>
33996                </field>
33997                <field>
33998                  <name>LATE_SAMPLE</name>
33999                  <description>Interface late sample sample delay:
34000Slave configuration (RX_CTL.MS is '0').
34001'0': Sample PCM bit value on rising edge (SCK_POLARITY is '0') or falling edge (SCK_POLARITY is '1') of receiver 'rx_sck_in'.
34002'1': Sample PCM bit value on falling edge  (SCK_POLARITY is '0') or rising edge (SCK_POLARITY is '1') of receiver 'rx_sck_in' (half a cycle delay).
34003
34004Master configuration (RX_CTL.MS is '1').
34005'0': Sample PCM bit value on rising edge (SCK_POLARITY is '0') or falling edge (SCK_POLARITY is '1') of receiver 'rx_sck_out'.
34006'1': Sample PCM bit value on falling edge  (SCK_POLARITY is '0') or rising edge (SCK_POLARITY is '1') of receiver 'rx_sck_out' (half a cycle delay).
34007
34008Note: This field can be set to '1' when the roundtrip delay is large (typically) in a master receiver configuration.</description>
34009                  <bitRange>[14:14]</bitRange>
34010                  <access>read-write</access>
34011                  <enumeratedValues>
34012                    <enumeratedValue>
34013                      <name>RISING</name>
34014                      <description>N/A</description>
34015                      <value>0</value>
34016                    </enumeratedValue>
34017                    <enumeratedValue>
34018                      <name>FALLING</name>
34019                      <description>N/A</description>
34020                      <value>1</value>
34021                    </enumeratedValue>
34022                  </enumeratedValues>
34023                </field>
34024                <field>
34025                  <name>FSYNC_FORMAT</name>
34026                  <description>Channel synchronization pulse format:
34027'0': Duration of a single bit period.
34028'1': Duration of the first channel.</description>
34029                  <bitRange>[15:15]</bitRange>
34030                  <access>read-write</access>
34031                  <enumeratedValues>
34032                    <enumeratedValue>
34033                      <name>BIT_PERIOD</name>
34034                      <description>N/A</description>
34035                      <value>0</value>
34036                    </enumeratedValue>
34037                    <enumeratedValue>
34038                      <name>CH_PERIOD</name>
34039                      <description>N/A</description>
34040                      <value>1</value>
34041                    </enumeratedValue>
34042                  </enumeratedValues>
34043                </field>
34044                <field>
34045                  <name>CH_NR</name>
34046                  <description>Number of channels in the frame:
34047'0': Undefined/illegal.
34048'1': 2 channels.
34049'2': 3 channels.
34050...
34051'31': 32 channels.
34052
34053Note: the field value chould be less than CH_NR (the number of support channels).
34054
34055Note: the RX_CH_CTL.CH_EN fields can be used to enable/disable indvidual channels.</description>
34056                  <bitRange>[20:16]</bitRange>
34057                  <access>read-write</access>
34058                </field>
34059                <field>
34060                  <name>CH_SIZE</name>
34061                  <description>Channel size:
34062'0'-'2': Undefined/illegal.
34063'3': 4 bits.
34064...
34065'31': 32 bits.
34066
34067Note: if RX_CTL.WORD_SIZE is greater than CH_SIZE, the lesser significant bits of the word are filled with '0's.</description>
34068                  <bitRange>[28:24]</bitRange>
34069                  <access>read-write</access>
34070                  <enumeratedValues>
34071                    <enumeratedValue>
34072                      <name>SIZE_1</name>
34073                      <description>N/A</description>
34074                      <value>0</value>
34075                    </enumeratedValue>
34076                    <enumeratedValue>
34077                      <name>SIZE_2</name>
34078                      <description>N/A</description>
34079                      <value>1</value>
34080                    </enumeratedValue>
34081                    <enumeratedValue>
34082                      <name>SIZE_32</name>
34083                      <description>N/A</description>
34084                      <value>31</value>
34085                    </enumeratedValue>
34086                  </enumeratedValues>
34087                </field>
34088                <field>
34089                  <name>LATE_CAPTURE</name>
34090                  <description>Extra delay (in 'rx_sck_out' cycles) for capturing 'tdm_rx_sd_in':
34091'0': no extra delay
34092'1': 1 cycle extra delay
34093'2': 2 cycles extra delay
34094'3': 3 cycles extra delay
34095
34096Note: the value of this field pushes further out the capturing edges used by the receiver to sample 'tdm_rx_sd_in'. This function is intended to support very large round-trip delays in a master receiver configuration, where the delay at the receiver between 'tdm_rx_fsync_out' and the arrival of the first bit on 'tdm_rx_sd_in' is multiple clock cycles.</description>
34097                  <bitRange>[30:29]</bitRange>
34098                  <access>read-write</access>
34099                  <enumeratedValues>
34100                    <enumeratedValue>
34101                      <name>EXTRA_DELAY_0</name>
34102                      <description>N/A</description>
34103                      <value>0</value>
34104                    </enumeratedValue>
34105                    <enumeratedValue>
34106                      <name>EXTRA_DELAY_1</name>
34107                      <description>N/A</description>
34108                      <value>1</value>
34109                    </enumeratedValue>
34110                    <enumeratedValue>
34111                      <name>EXTRA_DELAY_2</name>
34112                      <description>N/A</description>
34113                      <value>2</value>
34114                    </enumeratedValue>
34115                    <enumeratedValue>
34116                      <name>EXTRA_DELAY_3</name>
34117                      <description>N/A</description>
34118                      <value>3</value>
34119                    </enumeratedValue>
34120                  </enumeratedValues>
34121                </field>
34122                <field>
34123                  <name>I2S_MODE</name>
34124                  <description>I2S mode setting:
34125'0': TDM mode.
34126'1': I2S mode.</description>
34127                  <bitRange>[31:31]</bitRange>
34128                  <access>read-write</access>
34129                  <enumeratedValues>
34130                    <enumeratedValue>
34131                      <name>TDM</name>
34132                      <description>N/A</description>
34133                      <value>0</value>
34134                    </enumeratedValue>
34135                    <enumeratedValue>
34136                      <name>I2S</name>
34137                      <description>N/A</description>
34138                      <value>1</value>
34139                    </enumeratedValue>
34140                  </enumeratedValues>
34141                </field>
34142              </fields>
34143            </register>
34144            <register>
34145              <name>RX_CH_CTL</name>
34146              <description>RX channel control</description>
34147              <addressOffset>0x14</addressOffset>
34148              <size>32</size>
34149              <access>read-write</access>
34150              <resetValue>0x0</resetValue>
34151              <resetMask>0xFFFFFFFF</resetMask>
34152              <fields>
34153                <field>
34154                  <name>CH_EN</name>
34155                  <description>Channel enables: channel i is controlled by CH_EN[i].
34156'0': Disabled. The RX FIFO does not consume channel i words and the received channel i words on the interface are discarded.
34157'1': Enabled..
34158
34159Note: Only bit 0 through RX_IF_CTL.CH_NR may be set to '1'; i.e. only channels that are present in the frame can be enabled.</description>
34160                  <bitRange>[31:0]</bitRange>
34161                  <access>read-write</access>
34162                </field>
34163              </fields>
34164            </register>
34165            <register>
34166              <name>RX_TEST_CTL</name>
34167              <description>RX test control</description>
34168              <addressOffset>0x20</addressOffset>
34169              <size>32</size>
34170              <access>read-write</access>
34171              <resetValue>0x0</resetValue>
34172              <resetMask>0x80000000</resetMask>
34173              <fields>
34174                <field>
34175                  <name>ENABLED</name>
34176                  <description>Test mode enable.
34177'0': Disabled. Functional mode.
34178- Receiver rx_sck_in = IOSS tdm_rx_sck_in.
34179- Receiver rx_fsync_in = IOSS tdm_rx_fsync_in.
34180- Receiver rx_sd_in = IOSS tdm_rx_sd_in.
34181'1': Enabled. Test mode (intended to be used with (master transmitter, slave receiver) configuration).
34182- Receiver rx_sck_in = Transmitter tdm_tx_sck_out.
34183- Receiver rx_fsync_in = Transmitter tdm_tx_fsync_out.
34184- Receiver rx_sd_in = Transmitter tdm_tx_sd_out.
34185
34186Note: TX_TEST_CTL.ENABLED and RX_TEST_CTL.ENABLED should not be set to '1' simultaneously.</description>
34187                  <bitRange>[31:31]</bitRange>
34188                  <access>read-write</access>
34189                  <enumeratedValues>
34190                    <enumeratedValue>
34191                      <name>FUNCTIONAL</name>
34192                      <description>N/A</description>
34193                      <value>0</value>
34194                    </enumeratedValue>
34195                    <enumeratedValue>
34196                      <name>TEST</name>
34197                      <description>N/A</description>
34198                      <value>1</value>
34199                    </enumeratedValue>
34200                  </enumeratedValues>
34201                </field>
34202              </fields>
34203            </register>
34204            <register>
34205              <name>RX_ROUTE_CTL</name>
34206              <description>RX route control</description>
34207              <addressOffset>0x24</addressOffset>
34208              <size>32</size>
34209              <access>read-write</access>
34210              <resetValue>0x0</resetValue>
34211              <resetMask>0x3</resetMask>
34212              <fields>
34213                <field>
34214                  <name>MODE</name>
34215                  <description>Controls routing to the RX slave signalling inputs (FSYNC/SCK):
34216'0': RX slave signaling indipendent from TX signaling:
34217- Receiver rx_sck_in = IOSS tdm_rx_sck_in
34218- Receiver rx_fsync_in = IOSS tdm_rx_fsync_in
34219'1': RX slave signalling inputs driven by TX Slave:
34220- Receiver rx_sck_in = IOSS tdm_tx_sck_in
34221- Receiver rx_fsync_in = IOSS tdm_tx_fsync_in
34222'2': RX slave signalling inputs driven by TX Master:
34223- Receiver rx_sck_in = transmitter tdm_tx_sck_out
34224- Receiver rx_fsync_in = transmitter tdm_tx_fsync_out
34225
34226Note: MODE=0 is the default behaviour. MODE=1 or 2 is intended to allow the RX slave to share the same signaling used by the TX. This feature can be used to reduce the number of IO pins necessary to connect to an external codec supporting common TX/RX signaling.
34227
34228Note: when MODE=1 or 2, TX_TEST_CTL.ENABLED and RX_TEST_CTL.ENABLED should not be set to '1'.</description>
34229                  <bitRange>[1:0]</bitRange>
34230                  <access>read-write</access>
34231                  <enumeratedValues>
34232                    <enumeratedValue>
34233                      <name>RX_IN_DRIVEN_BY_IOSS_RX_IN</name>
34234                      <description>N/A</description>
34235                      <value>0</value>
34236                    </enumeratedValue>
34237                    <enumeratedValue>
34238                      <name>RX_IN_DRIVEN_BY_IOSS_TX_IN</name>
34239                      <description>N/A</description>
34240                      <value>1</value>
34241                    </enumeratedValue>
34242                    <enumeratedValue>
34243                      <name>RX_IN_DRIVEN_BY_TX_OUT</name>
34244                      <description>N/A</description>
34245                      <value>2</value>
34246                    </enumeratedValue>
34247                  </enumeratedValues>
34248                </field>
34249              </fields>
34250            </register>
34251            <register>
34252              <name>RX_FIFO_CTL</name>
34253              <description>RX FIFO control</description>
34254              <addressOffset>0x80</addressOffset>
34255              <size>32</size>
34256              <access>read-write</access>
34257              <resetValue>0x0</resetValue>
34258              <resetMask>0x6007F</resetMask>
34259              <fields>
34260                <field>
34261                  <name>TRIGGER_LEVEL</name>
34262                  <description>Trigger level. When the RX FIFO has more entries than the number of this field, a receiver trigger event is generated:
34263- INTR_RX.FIFO_TRIGGER = (# FIFO entries &gt; TRIGGER_LEVEL)</description>
34264                  <bitRange>[6:0]</bitRange>
34265                  <access>read-write</access>
34266                </field>
34267                <field>
34268                  <name>FREEZE</name>
34269                  <description>Freeze functionality:
34270'0': HW writes to the RX FIFO and advances the FIFO write pointer.
34271'1': HW writes from the RX FIFO have no effect: freeze will not advance the FIFO write pointer.
34272
34273Note: HW ensures that freeze functionality synchronizes on the first channel of a frame to ensure that PCM data of one channel is not misassigned to another channel. As a result, the freeze functionality can be activated at any time.
34274
34275Note: This functionality is intended for debugging purposes.</description>
34276                  <bitRange>[17:17]</bitRange>
34277                  <access>read-write</access>
34278                </field>
34279                <field>
34280                  <name>ACTIVE</name>
34281                  <description>Activate functionality:
34282'0': Receiver off. The FIFO_OVERFLOW interrupt cause will not be activated.
34283'1': Receiver on. The FIFO_OVERFLOW interrupt may be activated (when an overflow event occurs).
34284
34285Note: This functionality is intended for stopping purposes.</description>
34286                  <bitRange>[18:18]</bitRange>
34287                  <access>read-write</access>
34288                </field>
34289              </fields>
34290            </register>
34291            <register>
34292              <name>RX_FIFO_STATUS</name>
34293              <description>RX FIFO status</description>
34294              <addressOffset>0x84</addressOffset>
34295              <size>32</size>
34296              <access>read-only</access>
34297              <resetValue>0x0</resetValue>
34298              <resetMask>0x7F7F00FF</resetMask>
34299              <fields>
34300                <field>
34301                  <name>USED</name>
34302                  <description>Number of used/occupied entries in the RX FIFO. The field value is in the range [0, 128]. When '0', the FIFO is empty. When '128', the FIFO is full.</description>
34303                  <bitRange>[7:0]</bitRange>
34304                  <access>read-only</access>
34305                </field>
34306                <field>
34307                  <name>RD_PTR</name>
34308                  <description>RX FIFO read pointer: FIFO location from which a data is read.
34309
34310Note: This functionality is intended for debugging purposes.</description>
34311                  <bitRange>[22:16]</bitRange>
34312                  <access>read-only</access>
34313                </field>
34314                <field>
34315                  <name>WR_PTR</name>
34316                  <description>RX FIFO write pointer: FIFO location at which a new data is written by the hardware.
34317
34318Note: This functionality is intended for debugging purposes.</description>
34319                  <bitRange>[30:24]</bitRange>
34320                  <access>read-only</access>
34321                </field>
34322              </fields>
34323            </register>
34324            <register>
34325              <name>RX_FIFO_RD</name>
34326              <description>RX FIFO read</description>
34327              <addressOffset>0x88</addressOffset>
34328              <size>32</size>
34329              <access>read-only</access>
34330              <resetValue>0x0</resetValue>
34331              <resetMask>0xFFFFFFFF</resetMask>
34332              <fields>
34333                <field>
34334                  <name>DATA</name>
34335                  <description>Data (PCM sample) read from the RX FIFO. Reading removes the data from the RX FIFO; i.e. behavior is similar to that of a POP operation (RX_FIFO_STATUS.RD_PTR is incremented and RX_FIFO_STATUS.USED is decremented). The read data (DATA) is right aligned (unused bit positions follow the specified sign extension per RX_CTL.WORD_SIGN_EXTEND) when it is read from the FIFO entry (data[31:0]):
34336- 8 bit, DATA[7:0] = data[31:24].
34337- 10 bit, DATA[9:0] = data[31:22].
34338- 12 bit, DATA[11:0] = data[31:20].
34339- 14 bit, DATA[13:0] = data[31:18].
34340- 16 bit, DATA[15:0] = data[31:16].
34341- 18 bit, DATA[17:0] = data[31:14].
34342- 20 bit, DATA[19:0] = data[31:12].
34343- 24 bit, DATA[23:0] = data[31:8].
34344- 32 bit, DATA[31:0] = data[31:0].
34345
34346Note: Reading from an empty RX FIFO activates INTR_RX.FIFO_UNDERFLOW.</description>
34347                  <bitRange>[31:0]</bitRange>
34348                  <access>read-only</access>
34349                </field>
34350              </fields>
34351            </register>
34352            <register>
34353              <name>RX_FIFO_RD_SILENT</name>
34354              <description>RX FIFO silent read</description>
34355              <addressOffset>0x8C</addressOffset>
34356              <size>32</size>
34357              <access>read-only</access>
34358              <resetValue>0x0</resetValue>
34359              <resetMask>0xFFFFFFFF</resetMask>
34360              <fields>
34361                <field>
34362                  <name>DATA</name>
34363                  <description>N/A</description>
34364                  <bitRange>[31:0]</bitRange>
34365                  <access>read-only</access>
34366                </field>
34367              </fields>
34368            </register>
34369            <register>
34370              <name>INTR_RX</name>
34371              <description>Interrupt</description>
34372              <addressOffset>0xC0</addressOffset>
34373              <size>32</size>
34374              <access>read-write</access>
34375              <resetValue>0x0</resetValue>
34376              <resetMask>0x107</resetMask>
34377              <fields>
34378                <field>
34379                  <name>FIFO_TRIGGER</name>
34380                  <description>HW sets this field to '1', when a RX trigger is generated.</description>
34381                  <bitRange>[0:0]</bitRange>
34382                  <access>read-write</access>
34383                </field>
34384                <field>
34385                  <name>FIFO_OVERFLOW</name>
34386                  <description>HW sets this field to '1', when writing to a (almost) full RX FIFO (128 -RX_FIFO_STATUS.USED &lt; 'number of enabled channels per frame'). This is referred to as an overflow event.
34387
34388Note: HW ensures that either all or none of the frame's channels are received. In a RX FIFO overflow situation, HW discards received PCM data values.</description>
34389                  <bitRange>[1:1]</bitRange>
34390                  <access>read-write</access>
34391                </field>
34392                <field>
34393                  <name>FIFO_UNDERFLOW</name>
34394                  <description>HW sets this field to '1', when reading from an empty RX FIFO (RX_FIFO_STATUS.USED is '0').</description>
34395                  <bitRange>[2:2]</bitRange>
34396                  <access>read-write</access>
34397                </field>
34398                <field>
34399                  <name>IF_OVERFLOW</name>
34400                  <description>HW sets this field to '1', when PCM samples are generated too fast by the interface logic (interface overflow). This may be an indication that the IP system frequency is too low wrt. the interface frequency (a SW configuration error). The interface overflow is a non-recoverable error and requires SW disabling of the channel (a SW write to INTR_RX.IF_OVERFLOW does not resolve the interface underflow).
34401
34402Note: This functionality is intended for debug purposes.</description>
34403                  <bitRange>[8:8]</bitRange>
34404                  <access>read-write</access>
34405                </field>
34406              </fields>
34407            </register>
34408            <register>
34409              <name>INTR_RX_SET</name>
34410              <description>Interrupt set</description>
34411              <addressOffset>0xC4</addressOffset>
34412              <size>32</size>
34413              <access>read-write</access>
34414              <resetValue>0x0</resetValue>
34415              <resetMask>0x107</resetMask>
34416              <fields>
34417                <field>
34418                  <name>FIFO_TRIGGER</name>
34419                  <description>Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect).</description>
34420                  <bitRange>[0:0]</bitRange>
34421                  <access>read-write</access>
34422                </field>
34423                <field>
34424                  <name>FIFO_OVERFLOW</name>
34425                  <description>Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect).</description>
34426                  <bitRange>[1:1]</bitRange>
34427                  <access>read-write</access>
34428                </field>
34429                <field>
34430                  <name>FIFO_UNDERFLOW</name>
34431                  <description>Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect).</description>
34432                  <bitRange>[2:2]</bitRange>
34433                  <access>read-write</access>
34434                </field>
34435                <field>
34436                  <name>IF_OVERFLOW</name>
34437                  <description>Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect).</description>
34438                  <bitRange>[8:8]</bitRange>
34439                  <access>read-write</access>
34440                </field>
34441              </fields>
34442            </register>
34443            <register>
34444              <name>INTR_RX_MASK</name>
34445              <description>Interrupt mask</description>
34446              <addressOffset>0xC8</addressOffset>
34447              <size>32</size>
34448              <access>read-write</access>
34449              <resetValue>0x0</resetValue>
34450              <resetMask>0x107</resetMask>
34451              <fields>
34452                <field>
34453                  <name>FIFO_TRIGGER</name>
34454                  <description>Mask for corresponding field in INTR_RX register.</description>
34455                  <bitRange>[0:0]</bitRange>
34456                  <access>read-write</access>
34457                </field>
34458                <field>
34459                  <name>FIFO_OVERFLOW</name>
34460                  <description>Mask for corresponding field in INTR_RX register.</description>
34461                  <bitRange>[1:1]</bitRange>
34462                  <access>read-write</access>
34463                </field>
34464                <field>
34465                  <name>FIFO_UNDERFLOW</name>
34466                  <description>Mask for corresponding field in INTR_RX register.</description>
34467                  <bitRange>[2:2]</bitRange>
34468                  <access>read-write</access>
34469                </field>
34470                <field>
34471                  <name>IF_OVERFLOW</name>
34472                  <description>Mask for corresponding field in INTR_RX register.</description>
34473                  <bitRange>[8:8]</bitRange>
34474                  <access>read-write</access>
34475                </field>
34476              </fields>
34477            </register>
34478            <register>
34479              <name>INTR_RX_MASKED</name>
34480              <description>Interrupt masked</description>
34481              <addressOffset>0xCC</addressOffset>
34482              <size>32</size>
34483              <access>read-only</access>
34484              <resetValue>0x0</resetValue>
34485              <resetMask>0x107</resetMask>
34486              <fields>
34487                <field>
34488                  <name>FIFO_TRIGGER</name>
34489                  <description>Logical AND of corresponding INTR_RX and INTR_RX_MASK fields.</description>
34490                  <bitRange>[0:0]</bitRange>
34491                  <access>read-only</access>
34492                </field>
34493                <field>
34494                  <name>FIFO_OVERFLOW</name>
34495                  <description>Logical AND of corresponding INTR_RX and INTR_RX_MASK fields.</description>
34496                  <bitRange>[1:1]</bitRange>
34497                  <access>read-only</access>
34498                </field>
34499                <field>
34500                  <name>FIFO_UNDERFLOW</name>
34501                  <description>Logical AND of corresponding INTR_RX and INTR_RX_MASK fields.</description>
34502                  <bitRange>[2:2]</bitRange>
34503                  <access>read-only</access>
34504                </field>
34505                <field>
34506                  <name>IF_OVERFLOW</name>
34507                  <description>Logical AND of corresponding INTR_RX and INTR_RX_MASK fields.</description>
34508                  <bitRange>[8:8]</bitRange>
34509                  <access>read-only</access>
34510                </field>
34511              </fields>
34512            </register>
34513          </cluster>
34514        </cluster>
34515      </registers>
34516    </peripheral>
34517    <peripheral>
34518      <name>PDM0</name>
34519      <description>PDM</description>
34520      <headerStructName>PDM</headerStructName>
34521      <baseAddress>0x408D0000</baseAddress>
34522      <addressBlock>
34523        <offset>0</offset>
34524        <size>65536</size>
34525        <usage>registers</usage>
34526      </addressBlock>
34527      <registers>
34528        <register>
34529          <name>CTL</name>
34530          <description>Control</description>
34531          <addressOffset>0x0</addressOffset>
34532          <size>32</size>
34533          <access>read-write</access>
34534          <resetValue>0x0</resetValue>
34535          <resetMask>0xFF</resetMask>
34536          <fields>
34537            <field>
34538              <name>ACTIVE</name>
34539              <description>Activate functionality (1 bit for each channel):
34540'0': Reception disabled. The FIFO_OVERFLOW interrupt cause will not be activated.
34541'1': Reception enabled. The FIFO_OVERFLOW interrupt may be activated (when an overflow event occurs).
34542
34543Note: This functionality is intended for startup purposes. Typically, the startup sequence is as follows:
34544- global registers CLOCK_CTL, ROUTE_CTL, TEST_CTL, FIR*_COEFF* are initialized
34545- One or more structures are enabled (structure specific CTL.ENABLED register field is set to '1').
34546- The structures are initialized (structure specific MMIO registers are written).
34547- The structures are activated. This last step is performed by writing the CTL or CTL_SET MMIO registers, or on a rising edge ('0' to '1' transition) of a receiver's 'tr_activate' input trigger.
34548
34549Note: on a rising edge ('0' to '1' transition) of a receiver's 'tr_activate' input trigger, its associated CTL.ACTIVE field is set to '1'. This allows HW based synchronization of PDM receiver activation based on system triggers. Implementation note: the trigger is synchronized on the receiver clock with the receiver reset (this requires the receiver to be enabled; i.e. CTL.ENABLED is '1').
34550
34551Note: if CTL_CLR.ACTIVE[i] is written to '1' at the same time a rising edge of 'tr_activate[i]' occurs, CTL.ACTIVE[i] is set to '1' (i.e. trigger takes precedence).</description>
34552              <bitRange>[7:0]</bitRange>
34553              <access>read-write</access>
34554            </field>
34555          </fields>
34556        </register>
34557        <register>
34558          <name>CTL_CLR</name>
34559          <description>Control clear</description>
34560          <addressOffset>0x4</addressOffset>
34561          <size>32</size>
34562          <access>read-write</access>
34563          <resetValue>0x0</resetValue>
34564          <resetMask>0xFF</resetMask>
34565          <fields>
34566            <field>
34567              <name>ACTIVE</name>
34568              <description>Activate functionality:
34569'0': No effect.
34570'1': Bit is set to '0'.</description>
34571              <bitRange>[7:0]</bitRange>
34572              <access>read-write</access>
34573            </field>
34574          </fields>
34575        </register>
34576        <register>
34577          <name>CTL_SET</name>
34578          <description>Control set</description>
34579          <addressOffset>0x8</addressOffset>
34580          <size>32</size>
34581          <access>read-write</access>
34582          <resetValue>0x0</resetValue>
34583          <resetMask>0xFF</resetMask>
34584          <fields>
34585            <field>
34586              <name>ACTIVE</name>
34587              <description>Activate functionality:
34588'0': No effect.
34589'1': Bit is set to '1'.</description>
34590              <bitRange>[7:0]</bitRange>
34591              <access>read-write</access>
34592            </field>
34593          </fields>
34594        </register>
34595        <register>
34596          <name>CLOCK_CTL</name>
34597          <description>Clock control</description>
34598          <addressOffset>0x10</addressOffset>
34599          <size>32</size>
34600          <access>read-write</access>
34601          <resetValue>0x307</resetValue>
34602          <resetMask>0x103FF</resetMask>
34603          <fields>
34604            <field>
34605              <name>CLOCK_DIV</name>
34606              <description>PDM interface clock divider (legal range [3, 255]). The PDM interface clock clk_pdm ('pdm_clk[]' output signals) is defined as pdm_clk = clk_if / (CLOCK_DIV + 1); i.e. each PDM interface clock cycle equals CLOCK_DIV + 1 clk_if clock cycles. CLOCK_DIV should be set to an odd value ([3, 5, ..., 255]), to ensure a 50/50 percent duty cycle PDM interface clock pdm_clk.
34607'0-2': Illegal value.
34608'3': pdm_clk frequency is 1/4 clk_if frequency (1 pdm_clk cycle consists of 4 clk_if cycles).
34609'4': pdm_clk frequency is 1/5 clk_if frequency. Note: results in a non 50/50 percent duty cycle pdm_clk).
34610...
34611'255': pdm_clk frequency is 1/256 clk_if frequency.</description>
34612              <bitRange>[7:0]</bitRange>
34613              <access>read-write</access>
34614            </field>
34615            <field>
34616              <name>CLOCK_SEL</name>
34617              <description>Interface clock clk_if selection:
34618'0': SRSS clock clk_if_srss.
34619'1': IOSS data input signal 'pdm_data[0]'.
34620'2': IOSS data input signal 'pdm_data[1]'.
34621'3': undefined.
34622
34623Note: when a data input signal is used as a clock source, it cannot be used as a data line.
34624
34625Note: the application is always required to program this field to a value different from the default.</description>
34626              <bitRange>[9:8]</bitRange>
34627              <access>read-write</access>
34628              <enumeratedValues>
34629                <enumeratedValue>
34630                  <name>SEL_SRSS_CLOCK</name>
34631                  <description>N/A</description>
34632                  <value>0</value>
34633                </enumeratedValue>
34634                <enumeratedValue>
34635                  <name>SEL_PDM_DATA0</name>
34636                  <description>N/A</description>
34637                  <value>1</value>
34638                </enumeratedValue>
34639                <enumeratedValue>
34640                  <name>SEL_PDM_DATA1</name>
34641                  <description>N/A</description>
34642                  <value>2</value>
34643                </enumeratedValue>
34644                <enumeratedValue>
34645                  <name>SEL_OR</name>
34646                  <description>N/A</description>
34647                  <value>3</value>
34648                </enumeratedValue>
34649              </enumeratedValues>
34650            </field>
34651            <field>
34652              <name>HALVE</name>
34653              <description>Halve rate sampling:
34654'0': Full rate sampling. The PDM interface clock pdm_clk is as specified by CLOCK_DIV[]. Each captured PDM value is provided once to the CIC filter.
34655'1': Halve rate sampling. The PDM interface clock clk_pdm is as specified by CLOCK_DIV[] divided by two (halve the frequency). Each PDM value is captured twice and provided twice to the CIC filter; i.e. the PDM value is repeated.
34656
34657Note: this field is provided to dynamically change the digital microphone's clock (pdm_clk) without affecting the PDM sample frequency towards the CIC filter. Halving the microphone clock results in lower system power consumption, but does lower audio quality.</description>
34658              <bitRange>[16:16]</bitRange>
34659              <access>read-write</access>
34660              <enumeratedValues>
34661                <enumeratedValue>
34662                  <name>FULL</name>
34663                  <description>N/A</description>
34664                  <value>0</value>
34665                </enumeratedValue>
34666                <enumeratedValue>
34667                  <name>HALVE</name>
34668                  <description>N/A</description>
34669                  <value>1</value>
34670                </enumeratedValue>
34671              </enumeratedValues>
34672            </field>
34673          </fields>
34674        </register>
34675        <register>
34676          <name>ROUTE_CTL</name>
34677          <description>Route control</description>
34678          <addressOffset>0x20</addressOffset>
34679          <size>32</size>
34680          <access>read-write</access>
34681          <resetValue>0x0</resetValue>
34682          <resetMask>0xFF</resetMask>
34683          <fields>
34684            <field>
34685              <name>DATA_SEL</name>
34686              <description>Specifies what IOSS data input signal 'pdm_data[]' is routed to a specific PDM receiver. Each PDM receiver j has a dedicated 1-bit control field: PDM receiver j uses DATA_SEL[j]. The 1-bit field DATA_SEL[j] specification is as follows:
34687'0': PDM receiver j uses data input signal 'pdm_data[j]'.
34688'1': PDM receiver j uses data input signal 'pdm_data[j ^ 1]' (the lower bit of the index is inverted).
34689
34690Routing the same data input signal to two PDM receivers allows for:
34691- A single stereo digital microphone.
34692- Two (mono) digital microphones that share a data line.
34693
34694E.g., if DATA_SEL is 0b00000010, PDM receivers 0 and 1 BOTH use 'pdm_data[0]'.</description>
34695              <bitRange>[7:0]</bitRange>
34696              <access>read-write</access>
34697            </field>
34698          </fields>
34699        </register>
34700        <register>
34701          <name>TEST_CTL</name>
34702          <description>Test control</description>
34703          <addressOffset>0x30</addressOffset>
34704          <size>32</size>
34705          <access>read-write</access>
34706          <resetValue>0x7F0400</resetValue>
34707          <resetMask>0xFFFFFFFF</resetMask>
34708          <fields>
34709            <field>
34710              <name>DRIVE_DELAY_HI</name>
34711              <description>Interface drive delay on the high phase of the PDM interface clock. This field specifies when a PDM value is driven expressed in clk_if clock cycles. DRIVE_DELAY should be set in the range [0, IF_CTL.CLOCK_DIV]:
34712'0': Drive PDM value 1 clk_if cycle after the rising edge of clk_pdm.
34713'1': Drive PDM value 2 clk_if cycles after the rising edge of clk_pdm.
34714...
34715'255': Drive PDM value 256 clk_if cycles after the rising edge of clk_pdm.
34716
34717Note: To drive on the falling edge of the PDM interface clock clk_pdm, DRIVE_DELAY should be set to IF_CTL.CLOCK_DIV/2. To drive on the rising edge of clk_pdm, DRIVE_DELAY should be set to IF_CTL.CLOCK_DIV.</description>
34718              <bitRange>[7:0]</bitRange>
34719              <access>read-write</access>
34720            </field>
34721            <field>
34722              <name>DRIVE_DELAY_LO</name>
34723              <description>Interface drive delay on the low phase of the PDM interface clock. This field specifies when a PDM value is driven expressed in clk_if clock cycles. DRIVE_DELAY should be set in the range [0, IF_CTL.CLOCK_DIV]:
34724'0': Drive PDM value 1 clk_if cycle after the rising edge of clk_pdm.
34725'1': Drive PDM value 2 clk_if cycles after the rising edge of clk_pdm.
34726...
34727'255': Drive PDM value 256 clk_if cycles after the rising edge of clk_pdm.
34728
34729Note: To drive on the falling edge of the PDM interface clock clk_pdm, DRIVE_DELAY should be set to IF_CTL.CLOCK_DIV/2. To drive on the rising edge of clk_pdm, DRIVE_DELAY should be set to IF_CTL.CLOCK_DIV.</description>
34730              <bitRange>[15:8]</bitRange>
34731              <access>read-write</access>
34732            </field>
34733            <field>
34734              <name>MODE_HI</name>
34735              <description>Pattern generator mode on the high phase of the PDM interface clock. This field specifies the type of PDM pattern driven by the generator:
34736'0': constant 0's
34737'1': constant 1's
34738'2': alternating 0's and 1's (clock pattern)
34739'3': sinusoid</description>
34740              <bitRange>[17:16]</bitRange>
34741              <access>read-write</access>
34742              <enumeratedValues>
34743                <enumeratedValue>
34744                  <name>CONSTANT_0</name>
34745                  <description>N/A</description>
34746                  <value>0</value>
34747                </enumeratedValue>
34748                <enumeratedValue>
34749                  <name>CONSTANT_1</name>
34750                  <description>N/A</description>
34751                  <value>1</value>
34752                </enumeratedValue>
34753                <enumeratedValue>
34754                  <name>ALTERNATING</name>
34755                  <description>N/A</description>
34756                  <value>2</value>
34757                </enumeratedValue>
34758                <enumeratedValue>
34759                  <name>SINUSOID</name>
34760                  <description>N/A</description>
34761                  <value>3</value>
34762                </enumeratedValue>
34763              </enumeratedValues>
34764            </field>
34765            <field>
34766              <name>MODE_LO</name>
34767              <description>Pattern generator mode on the low phase of the PDM interface clock. This field specifies the type of pattern driven by the generator:
34768'0': constant 0's
34769'1': constant 1's
34770'2': alternating 0's and 1's (clock pattern)
34771'3': sine wave</description>
34772              <bitRange>[19:18]</bitRange>
34773              <access>read-write</access>
34774              <enumeratedValues>
34775                <enumeratedValue>
34776                  <name>CONSTANT_0</name>
34777                  <description>N/A</description>
34778                  <value>0</value>
34779                </enumeratedValue>
34780                <enumeratedValue>
34781                  <name>CONSTANT_1</name>
34782                  <description>N/A</description>
34783                  <value>1</value>
34784                </enumeratedValue>
34785                <enumeratedValue>
34786                  <name>ALTERNATING</name>
34787                  <description>N/A</description>
34788                  <value>2</value>
34789                </enumeratedValue>
34790                <enumeratedValue>
34791                  <name>SINUSOID</name>
34792                  <description>N/A</description>
34793                  <value>3</value>
34794                </enumeratedValue>
34795              </enumeratedValues>
34796            </field>
34797            <field>
34798              <name>AUDIO_FREQ_DIV</name>
34799              <description>Frequency division factor (legal range [3, 13]) to obtain audio frequency from the PDM clock frequency. This field determines the frequency of the sine wave generated by the pattern generator when MODE=3. The formula is below:
34800
34801Sine wave Frequency = PDM clock frequency / 2p*2^(AUDIO_FREQ_DIV)
34802
34803Example: when PDM clock frequency = 3.072 MHz the audio frequencies obtained for the various values of AUDIO_FREQ_DIV are shown below:
34804
34805'3' : 61.115 kHz
34806'4' : 30.558 kHz
34807'5' : 15.279 kHz
34808'6' : 7.639 kHz
34809'7' : 3.820 kHz
34810'8' : 1.910 kHz
34811'9' : 955 Hz
34812'10' : 477 Hz
34813'11' : 239 Hz
34814'12' : 119 Hz
34815'13' : 60 Hz</description>
34816              <bitRange>[23:20]</bitRange>
34817              <access>read-write</access>
34818              <enumeratedValues>
34819                <enumeratedValue>
34820                  <name>DIV_PDM_FREQ_BY_2PI_x_8</name>
34821                  <description>Example: 3.072 MHz/(2p*8) = 61.115 kHz</description>
34822                  <value>3</value>
34823                </enumeratedValue>
34824                <enumeratedValue>
34825                  <name>DIV_PDM_FREQ_BY_2PI_x_16</name>
34826                  <description>Example: 3.072 MHz/(2p*16) = 30.558 kHz</description>
34827                  <value>4</value>
34828                </enumeratedValue>
34829                <enumeratedValue>
34830                  <name>DIV_PDM_FREQ_BY_2PI_x_8192</name>
34831                  <description>Example: 3.072 MHz/(2p*8192) = 60 Hz</description>
34832                  <value>13</value>
34833                </enumeratedValue>
34834              </enumeratedValues>
34835            </field>
34836            <field>
34837              <name>CH_ENABLED</name>
34838              <description>Pattern generator enable (1 bit for each channel):
34839'0' : disabled, the channel input is taken as normal from external pin pdm_data_in
34840'1' : enabled, the channel input is taken from the pattern generator
34841
34842Note: the pattern generator output is routed to pdm_data_out for testing purposes
34843
34844Note: when all channels are disabled the pattern generator is switched off</description>
34845              <bitRange>[31:24]</bitRange>
34846              <access>read-write</access>
34847            </field>
34848          </fields>
34849        </register>
34850        <register>
34851          <name>FIR0_COEFF0</name>
34852          <description>FIR 0 coefficients 0</description>
34853          <addressOffset>0x100</addressOffset>
34854          <size>32</size>
34855          <access>read-write</access>
34856          <resetValue>0x0</resetValue>
34857          <resetMask>0x0</resetMask>
34858          <fields>
34859            <field>
34860              <name>DATA0</name>
34861              <description>Filter taps 0 and 29 coefficient.</description>
34862              <bitRange>[13:0]</bitRange>
34863              <access>read-write</access>
34864            </field>
34865            <field>
34866              <name>DATA1</name>
34867              <description>Filter taps 1 and 28 coefficient.</description>
34868              <bitRange>[29:16]</bitRange>
34869              <access>read-write</access>
34870            </field>
34871          </fields>
34872        </register>
34873        <register>
34874          <name>FIR0_COEFF1</name>
34875          <description>FIR 0 coefficients 1</description>
34876          <addressOffset>0x104</addressOffset>
34877          <size>32</size>
34878          <access>read-write</access>
34879          <resetValue>0x0</resetValue>
34880          <resetMask>0x0</resetMask>
34881          <fields>
34882            <field>
34883              <name>DATA0</name>
34884              <description>Filter taps 2 and 27 coefficient.</description>
34885              <bitRange>[13:0]</bitRange>
34886              <access>read-write</access>
34887            </field>
34888            <field>
34889              <name>DATA1</name>
34890              <description>Filter taps 3 and 26 coefficient.</description>
34891              <bitRange>[29:16]</bitRange>
34892              <access>read-write</access>
34893            </field>
34894          </fields>
34895        </register>
34896        <register>
34897          <name>FIR0_COEFF2</name>
34898          <description>FIR 0 coefficients 2</description>
34899          <addressOffset>0x108</addressOffset>
34900          <size>32</size>
34901          <access>read-write</access>
34902          <resetValue>0x0</resetValue>
34903          <resetMask>0x0</resetMask>
34904          <fields>
34905            <field>
34906              <name>DATA0</name>
34907              <description>Filter taps 4 and 25 coefficient.</description>
34908              <bitRange>[13:0]</bitRange>
34909              <access>read-write</access>
34910            </field>
34911            <field>
34912              <name>DATA1</name>
34913              <description>Filter taps 5 and 24 coefficient.</description>
34914              <bitRange>[29:16]</bitRange>
34915              <access>read-write</access>
34916            </field>
34917          </fields>
34918        </register>
34919        <register>
34920          <name>FIR0_COEFF3</name>
34921          <description>FIR 0 coefficients 3</description>
34922          <addressOffset>0x10C</addressOffset>
34923          <size>32</size>
34924          <access>read-write</access>
34925          <resetValue>0x0</resetValue>
34926          <resetMask>0x0</resetMask>
34927          <fields>
34928            <field>
34929              <name>DATA0</name>
34930              <description>Filter taps 6 and 23 coefficient.</description>
34931              <bitRange>[13:0]</bitRange>
34932              <access>read-write</access>
34933            </field>
34934            <field>
34935              <name>DATA1</name>
34936              <description>Filter taps 7 and 22 coefficient.</description>
34937              <bitRange>[29:16]</bitRange>
34938              <access>read-write</access>
34939            </field>
34940          </fields>
34941        </register>
34942        <register>
34943          <name>FIR0_COEFF4</name>
34944          <description>FIR 0 coefficients 4</description>
34945          <addressOffset>0x110</addressOffset>
34946          <size>32</size>
34947          <access>read-write</access>
34948          <resetValue>0x0</resetValue>
34949          <resetMask>0x0</resetMask>
34950          <fields>
34951            <field>
34952              <name>DATA0</name>
34953              <description>Filter taps 8 and 21 coefficient.</description>
34954              <bitRange>[13:0]</bitRange>
34955              <access>read-write</access>
34956            </field>
34957            <field>
34958              <name>DATA1</name>
34959              <description>Filter taps 9 and 20 coefficient.</description>
34960              <bitRange>[29:16]</bitRange>
34961              <access>read-write</access>
34962            </field>
34963          </fields>
34964        </register>
34965        <register>
34966          <name>FIR0_COEFF5</name>
34967          <description>FIR 0 coefficients 5</description>
34968          <addressOffset>0x114</addressOffset>
34969          <size>32</size>
34970          <access>read-write</access>
34971          <resetValue>0x0</resetValue>
34972          <resetMask>0x0</resetMask>
34973          <fields>
34974            <field>
34975              <name>DATA0</name>
34976              <description>Filter taps 10 and 19 coefficient.</description>
34977              <bitRange>[13:0]</bitRange>
34978              <access>read-write</access>
34979            </field>
34980            <field>
34981              <name>DATA1</name>
34982              <description>Filter taps 11 and 18 coefficient.</description>
34983              <bitRange>[29:16]</bitRange>
34984              <access>read-write</access>
34985            </field>
34986          </fields>
34987        </register>
34988        <register>
34989          <name>FIR0_COEFF6</name>
34990          <description>FIR 0 coefficients 6</description>
34991          <addressOffset>0x118</addressOffset>
34992          <size>32</size>
34993          <access>read-write</access>
34994          <resetValue>0x0</resetValue>
34995          <resetMask>0x0</resetMask>
34996          <fields>
34997            <field>
34998              <name>DATA0</name>
34999              <description>Filter taps 12 and 17 coefficient.</description>
35000              <bitRange>[13:0]</bitRange>
35001              <access>read-write</access>
35002            </field>
35003            <field>
35004              <name>DATA1</name>
35005              <description>Filter taps 13 and 16 coefficient.</description>
35006              <bitRange>[29:16]</bitRange>
35007              <access>read-write</access>
35008            </field>
35009          </fields>
35010        </register>
35011        <register>
35012          <name>FIR0_COEFF7</name>
35013          <description>FIR 0 coefficients 7</description>
35014          <addressOffset>0x11C</addressOffset>
35015          <size>32</size>
35016          <access>read-write</access>
35017          <resetValue>0x0</resetValue>
35018          <resetMask>0x0</resetMask>
35019          <fields>
35020            <field>
35021              <name>DATA0</name>
35022              <description>Filter tap 14 coefficient.</description>
35023              <bitRange>[13:0]</bitRange>
35024              <access>read-write</access>
35025            </field>
35026            <field>
35027              <name>DATA1</name>
35028              <description>Filter tap 15 coefficient.</description>
35029              <bitRange>[29:16]</bitRange>
35030              <access>read-write</access>
35031            </field>
35032          </fields>
35033        </register>
35034        <register>
35035          <name>FIR1_COEFF0</name>
35036          <description>FIR 1 coefficients 0</description>
35037          <addressOffset>0x140</addressOffset>
35038          <size>32</size>
35039          <access>read-write</access>
35040          <resetValue>0x153FFE</resetValue>
35041          <resetMask>0x3FFF3FFF</resetMask>
35042          <fields>
35043            <field>
35044              <name>DATA0</name>
35045              <description>Filter taps 0 and 54 coefficient (default value -2).</description>
35046              <bitRange>[13:0]</bitRange>
35047              <access>read-write</access>
35048            </field>
35049            <field>
35050              <name>DATA1</name>
35051              <description>Filter taps 1 and 53 coefficient (default value 21).</description>
35052              <bitRange>[29:16]</bitRange>
35053              <access>read-write</access>
35054            </field>
35055          </fields>
35056        </register>
35057        <register>
35058          <name>FIR1_COEFF1</name>
35059          <description>FIR 1 coefficients 1</description>
35060          <addressOffset>0x144</addressOffset>
35061          <size>32</size>
35062          <access>read-write</access>
35063          <resetValue>0x3FEF001A</resetValue>
35064          <resetMask>0x3FFF3FFF</resetMask>
35065          <fields>
35066            <field>
35067              <name>DATA0</name>
35068              <description>Filter taps 2 and 52 coefficient (default value 26).</description>
35069              <bitRange>[13:0]</bitRange>
35070              <access>read-write</access>
35071            </field>
35072            <field>
35073              <name>DATA1</name>
35074              <description>Filter taps 3 and 51 coefficient (default value -17).</description>
35075              <bitRange>[29:16]</bitRange>
35076              <access>read-write</access>
35077            </field>
35078          </fields>
35079        </register>
35080        <register>
35081          <name>FIR1_COEFF2</name>
35082          <description>FIR 1 coefficients 2</description>
35083          <addressOffset>0x148</addressOffset>
35084          <size>32</size>
35085          <access>read-write</access>
35086          <resetValue>0x193FD7</resetValue>
35087          <resetMask>0x3FFF3FFF</resetMask>
35088          <fields>
35089            <field>
35090              <name>DATA0</name>
35091              <description>Filter taps 4 and 50 coefficient (default value -41).</description>
35092              <bitRange>[13:0]</bitRange>
35093              <access>read-write</access>
35094            </field>
35095            <field>
35096              <name>DATA1</name>
35097              <description>Filter taps 5 and 49 coefficient (default value 25).</description>
35098              <bitRange>[29:16]</bitRange>
35099              <access>read-write</access>
35100            </field>
35101          </fields>
35102        </register>
35103        <register>
35104          <name>FIR1_COEFF3</name>
35105          <description>FIR 1 coefficients 3</description>
35106          <addressOffset>0x14C</addressOffset>
35107          <size>32</size>
35108          <access>read-write</access>
35109          <resetValue>0x3FDF0044</resetValue>
35110          <resetMask>0x3FFF3FFF</resetMask>
35111          <fields>
35112            <field>
35113              <name>DATA0</name>
35114              <description>Filter taps 6 and 48 coefficient (default value 68).</description>
35115              <bitRange>[13:0]</bitRange>
35116              <access>read-write</access>
35117            </field>
35118            <field>
35119              <name>DATA1</name>
35120              <description>Filter taps 7 and 47 coefficient (default value -33).</description>
35121              <bitRange>[29:16]</bitRange>
35122              <access>read-write</access>
35123            </field>
35124          </fields>
35125        </register>
35126        <register>
35127          <name>FIR1_COEFF4</name>
35128          <description>FIR 1 coefficients 4</description>
35129          <addressOffset>0x150</addressOffset>
35130          <size>32</size>
35131          <access>read-write</access>
35132          <resetValue>0x293F95</resetValue>
35133          <resetMask>0x3FFF3FFF</resetMask>
35134          <fields>
35135            <field>
35136              <name>DATA0</name>
35137              <description>Filter taps 8 and 46 coefficient (default value -107).</description>
35138              <bitRange>[13:0]</bitRange>
35139              <access>read-write</access>
35140            </field>
35141            <field>
35142              <name>DATA1</name>
35143              <description>Filter taps 9 and 45 coefficient (default value 41).</description>
35144              <bitRange>[29:16]</bitRange>
35145              <access>read-write</access>
35146            </field>
35147          </fields>
35148        </register>
35149        <register>
35150          <name>FIR1_COEFF5</name>
35151          <description>FIR 1 coefficients 5</description>
35152          <addressOffset>0x154</addressOffset>
35153          <size>32</size>
35154          <access>read-write</access>
35155          <resetValue>0x3FD000A0</resetValue>
35156          <resetMask>0x3FFF3FFF</resetMask>
35157          <fields>
35158            <field>
35159              <name>DATA0</name>
35160              <description>Filter taps 10 and 44 coefficient (default value 160).</description>
35161              <bitRange>[13:0]</bitRange>
35162              <access>read-write</access>
35163            </field>
35164            <field>
35165              <name>DATA1</name>
35166              <description>Filter taps 11 and 43 coefficient (default value -48).</description>
35167              <bitRange>[29:16]</bitRange>
35168              <access>read-write</access>
35169            </field>
35170          </fields>
35171        </register>
35172        <register>
35173          <name>FIR1_COEFF6</name>
35174          <description>FIR 1 coefficients 6</description>
35175          <addressOffset>0x158</addressOffset>
35176          <size>32</size>
35177          <access>read-write</access>
35178          <resetValue>0x363F1A</resetValue>
35179          <resetMask>0x3FFF3FFF</resetMask>
35180          <fields>
35181            <field>
35182              <name>DATA0</name>
35183              <description>Filter taps 12 and 42 coefficient (default value -230).</description>
35184              <bitRange>[13:0]</bitRange>
35185              <access>read-write</access>
35186            </field>
35187            <field>
35188              <name>DATA1</name>
35189              <description>Filter taps 13 and 41 coefficient (default value 54).</description>
35190              <bitRange>[29:16]</bitRange>
35191              <access>read-write</access>
35192            </field>
35193          </fields>
35194        </register>
35195        <register>
35196          <name>FIR1_COEFF7</name>
35197          <description>FIR 1 coefficients 7</description>
35198          <addressOffset>0x15C</addressOffset>
35199          <size>32</size>
35200          <access>read-write</access>
35201          <resetValue>0x3FC80145</resetValue>
35202          <resetMask>0x3FFF3FFF</resetMask>
35203          <fields>
35204            <field>
35205              <name>DATA0</name>
35206              <description>Filter taps 14 and 40 coefficient (default value 325).</description>
35207              <bitRange>[13:0]</bitRange>
35208              <access>read-write</access>
35209            </field>
35210            <field>
35211              <name>DATA1</name>
35212              <description>Filter taps 15 and 39 coefficient (default value -56).</description>
35213              <bitRange>[29:16]</bitRange>
35214              <access>read-write</access>
35215            </field>
35216          </fields>
35217        </register>
35218        <register>
35219          <name>FIR1_COEFF8</name>
35220          <description>FIR 1 coefficients 8</description>
35221          <addressOffset>0x160</addressOffset>
35222          <size>32</size>
35223          <access>read-write</access>
35224          <resetValue>0x333E3B</resetValue>
35225          <resetMask>0x3FFF3FFF</resetMask>
35226          <fields>
35227            <field>
35228              <name>DATA0</name>
35229              <description>Filter taps 16 and 38 coefficient (default value -453).</description>
35230              <bitRange>[13:0]</bitRange>
35231              <access>read-write</access>
35232            </field>
35233            <field>
35234              <name>DATA1</name>
35235              <description>Filter taps 17 and 37 coefficient (default value 51).</description>
35236              <bitRange>[29:16]</bitRange>
35237              <access>read-write</access>
35238            </field>
35239          </fields>
35240        </register>
35241        <register>
35242          <name>FIR1_COEFF9</name>
35243          <description>FIR 1 coefficients 9</description>
35244          <addressOffset>0x164</addressOffset>
35245          <size>32</size>
35246          <access>read-write</access>
35247          <resetValue>0x3FE10277</resetValue>
35248          <resetMask>0x3FFF3FFF</resetMask>
35249          <fields>
35250            <field>
35251              <name>DATA0</name>
35252              <description>Filter taps 18 and 36 coefficient (default value 631).</description>
35253              <bitRange>[13:0]</bitRange>
35254              <access>read-write</access>
35255            </field>
35256            <field>
35257              <name>DATA1</name>
35258              <description>Filter taps 19 and 35 coefficient (default value -31).</description>
35259              <bitRange>[29:16]</bitRange>
35260              <access>read-write</access>
35261            </field>
35262          </fields>
35263        </register>
35264        <register>
35265          <name>FIR1_COEFF10</name>
35266          <description>FIR 1 coefficients 10</description>
35267          <addressOffset>0x168</addressOffset>
35268          <size>32</size>
35269          <access>read-write</access>
35270          <resetValue>0x3FEB3C82</resetValue>
35271          <resetMask>0x3FFF3FFF</resetMask>
35272          <fields>
35273            <field>
35274              <name>DATA0</name>
35275              <description>Filter taps 20 and 34 coefficient (default value -894).</description>
35276              <bitRange>[13:0]</bitRange>
35277              <access>read-write</access>
35278            </field>
35279            <field>
35280              <name>DATA1</name>
35281              <description>Filter taps 21 and 33 coefficient (default value -21).</description>
35282              <bitRange>[29:16]</bitRange>
35283              <access>read-write</access>
35284            </field>
35285          </fields>
35286        </register>
35287        <register>
35288          <name>FIR1_COEFF11</name>
35289          <description>FIR 1 coefficients 11</description>
35290          <addressOffset>0x16C</addressOffset>
35291          <size>32</size>
35292          <access>read-write</access>
35293          <resetValue>0xAC052E</resetValue>
35294          <resetMask>0x3FFF3FFF</resetMask>
35295          <fields>
35296            <field>
35297              <name>DATA0</name>
35298              <description>Filter taps 22 and 32 coefficient (default value 1326).</description>
35299              <bitRange>[13:0]</bitRange>
35300              <access>read-write</access>
35301            </field>
35302            <field>
35303              <name>DATA1</name>
35304              <description>Filter taps 23 and 31 coefficient (default value 172).</description>
35305              <bitRange>[29:16]</bitRange>
35306              <access>read-write</access>
35307            </field>
35308          </fields>
35309        </register>
35310        <register>
35311          <name>FIR1_COEFF12</name>
35312          <description>FIR 1 coefficients 12</description>
35313          <addressOffset>0x170</addressOffset>
35314          <size>32</size>
35315          <access>read-write</access>
35316          <resetValue>0x3CFE3771</resetValue>
35317          <resetMask>0x3FFF3FFF</resetMask>
35318          <fields>
35319            <field>
35320              <name>DATA0</name>
35321              <description>Filter taps 24 and 30 coefficient (default value -2191).</description>
35322              <bitRange>[13:0]</bitRange>
35323              <access>read-write</access>
35324            </field>
35325            <field>
35326              <name>DATA1</name>
35327              <description>Filter taps 25 and 29 coefficient (default value -770).</description>
35328              <bitRange>[29:16]</bitRange>
35329              <access>read-write</access>
35330            </field>
35331          </fields>
35332        </register>
35333        <register>
35334          <name>FIR1_COEFF13</name>
35335          <description>FIR 1 coefficients 13</description>
35336          <addressOffset>0x174</addressOffset>
35337          <size>32</size>
35338          <access>read-write</access>
35339          <resetValue>0x1FFF12FB</resetValue>
35340          <resetMask>0x3FFF3FFF</resetMask>
35341          <fields>
35342            <field>
35343              <name>DATA0</name>
35344              <description>Filter taps 26 and 28 coefficient (default value 4859).</description>
35345              <bitRange>[13:0]</bitRange>
35346              <access>read-write</access>
35347            </field>
35348            <field>
35349              <name>DATA1</name>
35350              <description>Filter taps 27 (center tap) coefficient (default value 8191).</description>
35351              <bitRange>[29:16]</bitRange>
35352              <access>read-write</access>
35353            </field>
35354          </fields>
35355        </register>
35356        <cluster>
35357          <dim>2</dim>
35358          <dimIncrement>256</dimIncrement>
35359          <name>CH[%s]</name>
35360          <description>PDM RX structure</description>
35361          <addressOffset>0x00008000</addressOffset>
35362          <register>
35363            <name>CTL</name>
35364            <description>Control</description>
35365            <addressOffset>0x0</addressOffset>
35366            <size>32</size>
35367            <access>read-write</access>
35368            <resetValue>0x100</resetValue>
35369            <resetMask>0x8000010F</resetMask>
35370            <fields>
35371              <field>
35372                <name>WORD_SIZE</name>
35373                <description>PCM word size:
35374'0': 8 bit.
35375'1': 10 bit.
35376'2': 12 bit.
35377'3': 14 bit.
35378'4': 16 bit.
35379'5': 18 bit.
35380'6': 20 bit.
35381'7': 24 bit.
35382'8': 32 bit.
35383'9'-'15': Undefined.</description>
35384                <bitRange>[3:0]</bitRange>
35385                <access>read-write</access>
35386                <enumeratedValues>
35387                  <enumeratedValue>
35388                    <name>SIZE_8</name>
35389                    <description>N/A</description>
35390                    <value>0</value>
35391                  </enumeratedValue>
35392                  <enumeratedValue>
35393                    <name>SIZE_10</name>
35394                    <description>N/A</description>
35395                    <value>1</value>
35396                  </enumeratedValue>
35397                  <enumeratedValue>
35398                    <name>SIZE_12</name>
35399                    <description>N/A</description>
35400                    <value>2</value>
35401                  </enumeratedValue>
35402                  <enumeratedValue>
35403                    <name>SIZE_14</name>
35404                    <description>N/A</description>
35405                    <value>3</value>
35406                  </enumeratedValue>
35407                  <enumeratedValue>
35408                    <name>SIZE_16</name>
35409                    <description>N/A</description>
35410                    <value>4</value>
35411                  </enumeratedValue>
35412                  <enumeratedValue>
35413                    <name>SIZE_18</name>
35414                    <description>N/A</description>
35415                    <value>5</value>
35416                  </enumeratedValue>
35417                  <enumeratedValue>
35418                    <name>SIZE_20</name>
35419                    <description>N/A</description>
35420                    <value>6</value>
35421                  </enumeratedValue>
35422                  <enumeratedValue>
35423                    <name>SIZE_24</name>
35424                    <description>N/A</description>
35425                    <value>7</value>
35426                  </enumeratedValue>
35427                  <enumeratedValue>
35428                    <name>SIZE_32</name>
35429                    <description>N/A</description>
35430                    <value>8</value>
35431                  </enumeratedValue>
35432                </enumeratedValues>
35433              </field>
35434              <field>
35435                <name>WORD_SIGN_EXTEND</name>
35436                <description>Word extension:
35437'0': zero extension.
35438'1': sign extension.</description>
35439                <bitRange>[8:8]</bitRange>
35440                <access>read-write</access>
35441                <enumeratedValues>
35442                  <enumeratedValue>
35443                    <name>ZERO_EXTEND</name>
35444                    <description>N/A</description>
35445                    <value>0</value>
35446                  </enumeratedValue>
35447                  <enumeratedValue>
35448                    <name>SIGN_EXTEND</name>
35449                    <description>N/A</description>
35450                    <value>1</value>
35451                  </enumeratedValue>
35452                </enumeratedValues>
35453              </field>
35454              <field>
35455                <name>ENABLED</name>
35456                <description>Receiver enable:
35457'0': Disabled. If a receiver is disabled, all non-retained MMIO registers (e.g. the RX_FIFO_STATUS and INTR_RX registers) have their fields reset to their default value.
35458
35459'1': Enabled.
35460
35461Note: when all receivers are disabled, the SRAMs are driven into low power mode, if supported by the SRAM. When exiting such low power mode software needs to allow for a certain power up time before SRAM can be used, i.e. before ACTIVE can be asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register.</description>
35462                <bitRange>[31:31]</bitRange>
35463                <access>read-write</access>
35464              </field>
35465            </fields>
35466          </register>
35467          <register>
35468            <name>IF_CTL</name>
35469            <description>Interface control</description>
35470            <addressOffset>0x10</addressOffset>
35471            <size>32</size>
35472            <access>read-write</access>
35473            <resetValue>0x3</resetValue>
35474            <resetMask>0xFF</resetMask>
35475            <fields>
35476              <field>
35477                <name>SAMPLE_DELAY</name>
35478                <description>Interface sample delay. This field specifies when a PDM value is captured, expressed in clk_if clock cycles.
35479
35480When CLOCK_CTL.HALVE=0:
35481'0': Capture PDM value 1 clk_if cycle after the rising edge of clk_pdm.
35482'1': Capture PDM value 2 clk_if cycles after the rising edge of clk_pdm.
35483...
35484'255': Capture PDM value 256 clk_if cycles after the rising edge of clk_pdm.
35485
35486When CLOCK_CTL.HALVE=1:
35487'0': Capture PDM value 1 and 2 clk_if cycles after the rising edge of clk_pdm.
35488'1': Capture PDM value 3 and 4 clk_if cycles after the rising edge of clk_pdm.
35489...
35490'255': Capture PDM value 511 and 512 clk_if cycles after the rising edge of clk_pdm.
35491
35492SAMPLE_DELAY should be set such that the clk_if capture edge is at the middle point between pdm_clk_out edges. Under ideal conditions the middle point is 1/4 of the PDM interface period for the first/even/left channel, and 3/4 of the PDM interface period for the second/odd/right channel, which corresponds to the following programmings:
35493
35494SAMPLE_DELAY(left)=((CLOCK_DIV+1)/4) - 1
35495SAMPLE_DELAY(right)=(3*(CLOCK_DIV+1)/4) - 1
35496
35497In practice, due to the roundtrip delay, SAMPLE_DELAY may be set to a later point with respect to the ideal middle point.
35498
35499Note: in all cases a SAMPLE_DELAY value that brings the capture edge close to the pdm_clk_out edges should be avoided.</description>
35500                <bitRange>[7:0]</bitRange>
35501                <access>read-write</access>
35502              </field>
35503            </fields>
35504          </register>
35505          <register>
35506            <name>CIC_CTL</name>
35507            <description>CIC control</description>
35508            <addressOffset>0x14</addressOffset>
35509            <size>32</size>
35510            <access>read-write</access>
35511            <resetValue>0x4</resetValue>
35512            <resetMask>0x7</resetMask>
35513            <fields>
35514              <field>
35515                <name>DECIM_CODE</name>
35516                <description>CIC filter decimation. The CIC filter PCM frequency is a fraction of the PDM frequency:
35517'0': CIC filter PCM frequency is 1/2 * PDM frequency. CIC PCM values are in the range [-0x10, 0x10].
35518'1': CIC filter PCM frequency is 1/4 * PDM frequency. CIC PCM values are in the range [-0x200, 0x200].
35519'2': CIC filter PCM frequency is 1/8 * PDM frequency. CIC PCM values are in the range [-0x4000, 0x4000].
35520'3': CIC filter PCM frequency is 1/16 * PDM frequency. CIC PCM values are in the range [-0x80000, 0x80000].
35521'4': CIC filter PCM frequency is 1/32 * PDM frequency. CIC PCM values are in the range [-0x1000000, 0x1000000].
35522'5'-'7': Illegal values.
35523
35524Note: The CIC filter functionality includes offsetting logic to ensure that 'digital silence' on the PDM interface (an alternating pattern of '0', '1', '0', '1' ... PDM  values) results in CIC filter PCM values of '0'. Similarly, a pattern of '0', '0', '0', ... PDM values results in minimum CIC PCM value (-0x100:0000 when DECIMATION is '4') and a pattern of '1', '1', '1', ... PDM values results in maximum CIC PCM value (0x100:0000 when DECIMATION is '4').
35525
35526Note: The desired 'clk_sys' frequency is a function of the PDM interface clock, the CIC filter decimation (CIC_CTL.DECIM_CODE[]) and the FIR filter decimation (FIR_CTL.DECIM_CODE[]).</description>
35527                <bitRange>[2:0]</bitRange>
35528                <access>read-write</access>
35529                <enumeratedValues>
35530                  <enumeratedValue>
35531                    <name>DECIM_2</name>
35532                    <description>N/A</description>
35533                    <value>0</value>
35534                  </enumeratedValue>
35535                  <enumeratedValue>
35536                    <name>DECIM_4</name>
35537                    <description>N/A</description>
35538                    <value>1</value>
35539                  </enumeratedValue>
35540                  <enumeratedValue>
35541                    <name>DECIM_8</name>
35542                    <description>N/A</description>
35543                    <value>2</value>
35544                  </enumeratedValue>
35545                  <enumeratedValue>
35546                    <name>DECIM_16</name>
35547                    <description>N/A</description>
35548                    <value>3</value>
35549                  </enumeratedValue>
35550                  <enumeratedValue>
35551                    <name>DECIM_32</name>
35552                    <description>This is the default value and the most realistic value (together with the value '3'). Typically, an overall decimation (or oversample rate (OSR)) of 64 is used, and this is achieved with the default CIC and FIR decimation values.</description>
35553                    <value>4</value>
35554                  </enumeratedValue>
35555                </enumeratedValues>
35556              </field>
35557            </fields>
35558          </register>
35559          <register>
35560            <name>FIR0_CTL</name>
35561            <description>FIR 0 control</description>
35562            <addressOffset>0x18</addressOffset>
35563            <size>32</size>
35564            <access>read-write</access>
35565            <resetValue>0x0</resetValue>
35566            <resetMask>0x80001F07</resetMask>
35567            <fields>
35568              <field>
35569                <name>DECIM3</name>
35570                <description>FIR filter decimation. The FIR filter PCM frequency is a fraction of the CIC filter PCM frequency:
35571'0': FIR 0 filter PCM frequency is 1 * CIC filter PCM frequency. The FIR 0 filter is performed for every CIC filter PCM sample.
35572'1': FIR 0 filter PCM frequency is 1/2 * CIC filter PCM frequency. The FIR 0 filter is performed for every second CIC filter PCM sample.
35573'2': FIR 0 filter PCM frequency is 1/3 * CIC filter PCM frequency. The FIR 0 filter is performed for every third CIC filter PCM sample.
35574'3': FIR 0 filter PCM frequency is 1/4 * CIC filter PCM frequency. The FIR 0 filter is performed for every fourth CIC filter PCM sample.
35575'4': FIR 0 filter PCM frequency is 1/5 * CIC filter PCM frequency. The FIR 0 filter is performed for every fifth CIC filter PCM sample.</description>
35576                <bitRange>[2:0]</bitRange>
35577                <access>read-write</access>
35578                <enumeratedValues>
35579                  <enumeratedValue>
35580                    <name>DECIM_1</name>
35581                    <description>N/A</description>
35582                    <value>0</value>
35583                  </enumeratedValue>
35584                  <enumeratedValue>
35585                    <name>DECIM_2</name>
35586                    <description>N/A</description>
35587                    <value>1</value>
35588                  </enumeratedValue>
35589                  <enumeratedValue>
35590                    <name>DECIM_3</name>
35591                    <description>N/A</description>
35592                    <value>2</value>
35593                  </enumeratedValue>
35594                  <enumeratedValue>
35595                    <name>DECIM_4</name>
35596                    <description>N/A</description>
35597                    <value>3</value>
35598                  </enumeratedValue>
35599                  <enumeratedValue>
35600                    <name>DECIM_5</name>
35601                    <description>N/A</description>
35602                    <value>4</value>
35603                  </enumeratedValue>
35604                </enumeratedValues>
35605              </field>
35606              <field>
35607                <name>SCALE</name>
35608                <description>FIR 0 filter PCM scaling. FIR 0 filter PCM values (fir0_pcm[44:0]) are scaled (right shifted, rounded and clipped) to 26-bit signed PCM values (fir0_scaled_pcm[25:0]). These 26-bit PCM values are input to the FIR 1 filter. SCALE specifies the right shift amount (and performs a rounding):
35609'0': fir0_scaled_pcm = CLIP26 (fir0_pcm[44:0]).
35610'1': fir0_scaled_pcm = CLIP26 (fir0_pcm[44:1] + fir0_pcm[0]).
35611...
35612'31': fir0_scaled_pcm = CLIP26 (fir0_pcm[44:31] + fir0_pcm[30]).
35613
35614With CLIP26(a) defined as:
35615   if      (a &gt;= 0x1ff:ffff) result =  0x1ff:ffff;
35616   else if (a &lt; -0x200:0000) result = -0x200:0000;
35617   else                      result = a;
35618
35619Note: Clipping is not necessary for larger SCALE values, as the scaled value is guarneteed to be within the 26-bit signed integer range.</description>
35620                <bitRange>[12:8]</bitRange>
35621                <access>read-write</access>
35622                <enumeratedValues>
35623                  <enumeratedValue>
35624                    <name>SCALE_0</name>
35625                    <description>N/A</description>
35626                    <value>0</value>
35627                  </enumeratedValue>
35628                  <enumeratedValue>
35629                    <name>SCALE_1</name>
35630                    <description>N/A</description>
35631                    <value>1</value>
35632                  </enumeratedValue>
35633                  <enumeratedValue>
35634                    <name>SCALE_31</name>
35635                    <description>N/A</description>
35636                    <value>31</value>
35637                  </enumeratedValue>
35638                </enumeratedValues>
35639              </field>
35640              <field>
35641                <name>ENABLED</name>
35642                <description>FIR 0 filter coefficient enable (does NOT effect FIR filter scaling and FIR filter decimation):
35643'0': Disabled. The middle FIR filter coefficient (16th coefficient, or tap 15 in [0:29] range) is '1' and all other FIR filter coefficients are '0'; i.e. the FIR filter is a pass through filter and the filter gain is '1'.
35644   fir0_pcm[44:0] = cic_pcm[25:0] (with sign extension)
35645'1': Enabled.
35646
35647Note: This filter is disabled by default, and typically only used for sample frequencies (Fs) of 8 and 16 kHz.</description>
35648                <bitRange>[31:31]</bitRange>
35649                <access>read-write</access>
35650              </field>
35651            </fields>
35652          </register>
35653          <register>
35654            <name>FIR1_CTL</name>
35655            <description>FIR 1 control</description>
35656            <addressOffset>0x1C</addressOffset>
35657            <size>32</size>
35658            <access>read-write</access>
35659            <resetValue>0x80000F01</resetValue>
35660            <resetMask>0x80001F03</resetMask>
35661            <fields>
35662              <field>
35663                <name>DECIM2</name>
35664                <description>FIR 1 filter decimation. The FIR filter PCM frequency is a fraction of the FIR0 filter PCM frequency:
35665'0': FIR 1 filter PCM frequency is 1 * FIR 0 filter PCM frequency. The FIR filter is performed for every FIR 0 filter PCM sample.
35666'1': FIR 1 filter PCM frequency is 1/2 * FIR 0 filter PCM frequency. The FIR filter is performed for every second FIR 0 filter PCM sample.
35667'2': FIR 1 filter PCM frequency is 1/3 * FIR 0 filter PCM frequency. The FIR filter is performed for every third FIR 0 filter PCM sample.
35668'3': FIR 1 filter PCM frequency is 1/4 * FIR 0 filter PCM frequency. The FIR filter is performed for every fourth FIR 0 filter PCM sample.</description>
35669                <bitRange>[1:0]</bitRange>
35670                <access>read-write</access>
35671                <enumeratedValues>
35672                  <enumeratedValue>
35673                    <name>DECIM_1</name>
35674                    <description>N/A</description>
35675                    <value>0</value>
35676                  </enumeratedValue>
35677                  <enumeratedValue>
35678                    <name>DECIM_2</name>
35679                    <description>N/A</description>
35680                    <value>1</value>
35681                  </enumeratedValue>
35682                  <enumeratedValue>
35683                    <name>DECIM_3</name>
35684                    <description>N/A</description>
35685                    <value>2</value>
35686                  </enumeratedValue>
35687                  <enumeratedValue>
35688                    <name>DECIM_4</name>
35689                    <description>N/A</description>
35690                    <value>3</value>
35691                  </enumeratedValue>
35692                </enumeratedValues>
35693              </field>
35694              <field>
35695                <name>SCALE</name>
35696                <description>FIR 1 filter PCM scaling. FIR filter PCM values (fir1_pcm[43:0]) are scaled (right shifted, rounded and clipped) to 24-bit signed PCM values (fir1_scaled_pcm[23:0]). These 24-bit PCM values are input to the DC blocker. SCALE specifies the right shift amount (and performs a rounding):
35697'0': fir1_scaled_pcm = CLIP24 (fir1_pcm[43:0]).
35698'1': fir1_scaled_pcm = CLIP24 (fir1_pcm[43:1] + fir1_pcm[0]).
35699...
35700'31': fir1_scaled_pcm = CLIP24 (fir1_pcm[43:31] + fir1_pcm[30]).
35701
35702With CLIP24(a) defined as:
35703   if      (a &gt;= 0x7f:ffff) result =  0x7f:ffff;
35704   else if (a &lt; -0x80:0000) result = -0x80:0000;
35705   else                     result = a;
35706
35707Note: Clipping is not necessary for larger SCALE values, as the scaled value is guarneteed to be within the 24-bit signed integer range.</description>
35708                <bitRange>[12:8]</bitRange>
35709                <access>read-write</access>
35710                <enumeratedValues>
35711                  <enumeratedValue>
35712                    <name>SCALE_0</name>
35713                    <description>N/A</description>
35714                    <value>0</value>
35715                  </enumeratedValue>
35716                  <enumeratedValue>
35717                    <name>SCALE_1</name>
35718                    <description>N/A</description>
35719                    <value>1</value>
35720                  </enumeratedValue>
35721                  <enumeratedValue>
35722                    <name>SCALE_31</name>
35723                    <description>N/A</description>
35724                    <value>31</value>
35725                  </enumeratedValue>
35726                </enumeratedValues>
35727              </field>
35728              <field>
35729                <name>ENABLED</name>
35730                <description>FIR 1 filter coefficient enable (does NOT effect FIR filter scaling and FIR filter decimation):
35731'0': Disabled. The middle FIR filter coefficient (28th coefficient, or tap 27 in [0:54] range) is '1' and all other FIR filter coefficients are '0'; i.e. the FIR filter is a pass through filter and the filter gain is '1'.
35732   fir1_pcm[43:0] = fir0_scaled_pcm[25:0] (with sign extension)
35733'1': Enabled.
35734
35735Note: Disabling of the filter functionality is provided for debug purposes.</description>
35736                <bitRange>[31:31]</bitRange>
35737                <access>read-write</access>
35738              </field>
35739            </fields>
35740          </register>
35741          <register>
35742            <name>DC_BLOCK_CTL</name>
35743            <description>DC block control</description>
35744            <addressOffset>0x20</addressOffset>
35745            <size>32</size>
35746            <access>read-write</access>
35747            <resetValue>0x80000001</resetValue>
35748            <resetMask>0x80000007</resetMask>
35749            <fields>
35750              <field>
35751                <name>CODE</name>
35752                <description>DC blocker coefficient. The DC blocker is defined as:
35753
35754dc_block_state_scaled(n-1) =
35755       dc_block_state(n-1)
35756     - (dc_block_state(n-1) &gt;&gt; (12-CODE))
35757dc_block_state(n)          = CLIP37 (
35758       2^13 * (fir1_scaled_pcm(n) - fir1_scaled_pcm(n-1))
35759     + dc_block_state_scaled(n-1))
35760dc_block_pcm(n)            = dc_block_state(n) &gt;&gt; 13
35761
35762This first step is a scaling step of the DC block state. It effectively multiplies the DC block state with a variable 'alpha' that is close to '1':
35763'0': alpha = 1 - (1/2^(12-0)) = 0.999755859.
35764'1': alpha = 1 - (1/2^(12-1)) = 0.999511719.
35765'2': alpha = 1 - (1/2^(12-2)) = 0.999023438.
35766'3': alpha = 1 - (1/2^(12-3)) = 0.998046875.
35767'4': alpha = 1 - (1/2^(12-4)) = 0.99609375.
35768'5': alpha = 1 - (1/2^(12-5)) = 0.9921875.
35769'6': alpha = 1 - (1/2^(12-6)) = 0.984375.
35770'7': alpha = 1 - (1/2^(12-7)) = 0.96875.</description>
35771                <bitRange>[2:0]</bitRange>
35772                <access>read-write</access>
35773                <enumeratedValues>
35774                  <enumeratedValue>
35775                    <name>CODE_1</name>
35776                    <description>N/A</description>
35777                    <value>0</value>
35778                  </enumeratedValue>
35779                  <enumeratedValue>
35780                    <name>CODE_2</name>
35781                    <description>N/A</description>
35782                    <value>1</value>
35783                  </enumeratedValue>
35784                  <enumeratedValue>
35785                    <name>CODE_4</name>
35786                    <description>N/A</description>
35787                    <value>2</value>
35788                  </enumeratedValue>
35789                  <enumeratedValue>
35790                    <name>CODE_8</name>
35791                    <description>N/A</description>
35792                    <value>3</value>
35793                  </enumeratedValue>
35794                  <enumeratedValue>
35795                    <name>CODE_16</name>
35796                    <description>N/A</description>
35797                    <value>4</value>
35798                  </enumeratedValue>
35799                  <enumeratedValue>
35800                    <name>CODE_32</name>
35801                    <description>N/A</description>
35802                    <value>5</value>
35803                  </enumeratedValue>
35804                  <enumeratedValue>
35805                    <name>CODE_64</name>
35806                    <description>N/A</description>
35807                    <value>6</value>
35808                  </enumeratedValue>
35809                  <enumeratedValue>
35810                    <name>CODE_128</name>
35811                    <description>N/A</description>
35812                    <value>7</value>
35813                  </enumeratedValue>
35814                </enumeratedValues>
35815              </field>
35816              <field>
35817                <name>ENABLED</name>
35818                <description>DC blocker enable:
35819'0': Disabled. The functionality is defined as:
35820dc_block_pcm(n) = fir1_scaled_pcm(n)
35821'1': Enabled. The functionality is as specified by the CODE field.
35822
35823Note: disabling of the DC blocker filter functionality is provided for debug purposes.</description>
35824                <bitRange>[31:31]</bitRange>
35825                <access>read-write</access>
35826              </field>
35827            </fields>
35828          </register>
35829          <register>
35830            <name>RX_FIFO_CTL</name>
35831            <description>RX FIFO control</description>
35832            <addressOffset>0x80</addressOffset>
35833            <size>32</size>
35834            <access>read-write</access>
35835            <resetValue>0x0</resetValue>
35836            <resetMask>0x2003F</resetMask>
35837            <fields>
35838              <field>
35839                <name>TRIGGER_LEVEL</name>
35840                <description>Trigger level. When the RX FIFO has more entries than the number of this field, a receiver trigger event is generated:
35841- INTR_RX.FIFO_TRIGGER = (# FIFO entries &gt; TRIGGER_LEVEL)</description>
35842                <bitRange>[5:0]</bitRange>
35843                <access>read-write</access>
35844                <enumeratedValues>
35845                  <enumeratedValue>
35846                    <name>EMPTY</name>
35847                    <description>N/A</description>
35848                    <value>0</value>
35849                  </enumeratedValue>
35850                  <enumeratedValue>
35851                    <name>USED_1</name>
35852                    <description>N/A</description>
35853                    <value>1</value>
35854                  </enumeratedValue>
35855                  <enumeratedValue>
35856                    <name>USED_63</name>
35857                    <description>N/A</description>
35858                    <value>63</value>
35859                  </enumeratedValue>
35860                </enumeratedValues>
35861              </field>
35862              <field>
35863                <name>FREEZE</name>
35864                <description>Freeze functionality:
35865'0': HW writes to the RX FIFO and advances the FIFO write pointer.
35866'1': HW writes from the RX FIFO have no effect: freeze will not advance the FIFO write pointer.
35867
35868Note: This functionality is intended for debugging purposes.</description>
35869                <bitRange>[17:17]</bitRange>
35870                <access>read-write</access>
35871              </field>
35872            </fields>
35873          </register>
35874          <register>
35875            <name>RX_FIFO_STATUS</name>
35876            <description>RX FIFO status</description>
35877            <addressOffset>0x84</addressOffset>
35878            <size>32</size>
35879            <access>read-only</access>
35880            <resetValue>0x0</resetValue>
35881            <resetMask>0x3F3F007F</resetMask>
35882            <fields>
35883              <field>
35884                <name>USED</name>
35885                <description>Number of used/occupied entries in the RX FIFO. The field value is in the range [0, 64]. When '0', the FIFO is empty. When '64', the FIFO is full.</description>
35886                <bitRange>[6:0]</bitRange>
35887                <access>read-only</access>
35888              </field>
35889              <field>
35890                <name>RD_PTR</name>
35891                <description>RX FIFO read pointer: FIFO location from which a data is read.
35892
35893Note: This functionality is intended for debugging purposes.</description>
35894                <bitRange>[21:16]</bitRange>
35895                <access>read-only</access>
35896              </field>
35897              <field>
35898                <name>WR_PTR</name>
35899                <description>RX FIFO write pointer: FIFO location at which a new data is written by the hardware.
35900
35901Note: This functionality is intended for debugging purposes.</description>
35902                <bitRange>[29:24]</bitRange>
35903                <access>read-only</access>
35904              </field>
35905            </fields>
35906          </register>
35907          <register>
35908            <name>RX_FIFO_RD</name>
35909            <description>RX FIFO read</description>
35910            <addressOffset>0x88</addressOffset>
35911            <size>32</size>
35912            <access>read-only</access>
35913            <resetValue>0x0</resetValue>
35914            <resetMask>0xFFFFFFFF</resetMask>
35915            <fields>
35916              <field>
35917                <name>DATA</name>
35918                <description>Data (PCM sample) read from the RX FIFO. Reading removes the data from the RX FIFO; i.e. behavior is similar to that of a POP operation (RX_FIFO_STATUS.RD_PTR is incremented and RX_FIFO_STATUS.USED is decremented). The read data (DATA) is right aligned (unused bit positions follow the specified sign extension per CTL.WORD_SIGN_EXTEND) when it is read from the FIFO entry (data[23:0]):
35919- 8 bit, DATA[7:0] = data[23:16].
35920- 10 bit, DATA[9:0] = data[23:14].
35921- 12 bit, DATA[11:0] = data[23:12].
35922- 14 bit, DATA[13:0] = data[23:10].
35923- 16 bit, DATA[15:0] = data[23:8].
35924- 18 bit, DATA[17:0] = data[23:6].
35925- 20 bit, DATA[19:0] = data[23:4].
35926- 24 bit, DATA[23:0] = data[23:0].
35927- 32 bit, DATA[31:0] = data[23:0] &lt;&lt; 8.
35928
35929Note: Reading from an empty RX FIFO activates INTR_RX.FIFO_UNDERFLOW.</description>
35930                <bitRange>[31:0]</bitRange>
35931                <access>read-only</access>
35932              </field>
35933            </fields>
35934          </register>
35935          <register>
35936            <name>RX_FIFO_RD_SILENT</name>
35937            <description>RX FIFO silent read</description>
35938            <addressOffset>0x8C</addressOffset>
35939            <size>32</size>
35940            <access>read-only</access>
35941            <resetValue>0x0</resetValue>
35942            <resetMask>0xFFFFFFFF</resetMask>
35943            <fields>
35944              <field>
35945                <name>DATA</name>
35946                <description>Data (PCM sample) read from the RX FIFO. Reading will NOT remove the data  from the RX FIFO; i.e. behavior is similar to that of a PEEK operation. See RX_FIFO_RD for data alignment.
35947
35948Note: Reading from an empty RX FIFO activates INTR.RX_FIFO_UNDERFLOW (the read returns 0xffff:ffff).
35949
35950Note: This functionality is intended for debugging purposes.</description>
35951                <bitRange>[31:0]</bitRange>
35952                <access>read-only</access>
35953              </field>
35954            </fields>
35955          </register>
35956          <register>
35957            <name>INTR_RX</name>
35958            <description>Interrupt</description>
35959            <addressOffset>0xC0</addressOffset>
35960            <size>32</size>
35961            <access>read-write</access>
35962            <resetValue>0x0</resetValue>
35963            <resetMask>0x117</resetMask>
35964            <fields>
35965              <field>
35966                <name>FIFO_TRIGGER</name>
35967                <description>HW sets this field to '1', when a RX trigger is generated.</description>
35968                <bitRange>[0:0]</bitRange>
35969                <access>read-write</access>
35970              </field>
35971              <field>
35972                <name>FIFO_OVERFLOW</name>
35973                <description>HW sets this field to '1', when writing to a full RX FIFO (RX_FIFO_STATUS.USED is '64').</description>
35974                <bitRange>[1:1]</bitRange>
35975                <access>read-write</access>
35976              </field>
35977              <field>
35978                <name>FIFO_UNDERFLOW</name>
35979                <description>HW sets this field to '1', when reading from an empty RX FIFO (RX_FIFO_STATUS.USED is '0').</description>
35980                <bitRange>[2:2]</bitRange>
35981                <access>read-write</access>
35982              </field>
35983              <field>
35984                <name>FIR_OVERFLOW</name>
35985                <description>HW sets this field to '1', when CIC filter PCM samples are produced at a faster rate than the FIR filter can process them. This is an indication that the IP system frequency is too low.
35986
35987Note: This functionality is intended for debugging purposes.</description>
35988                <bitRange>[4:4]</bitRange>
35989                <access>read-write</access>
35990              </field>
35991              <field>
35992                <name>IF_OVERFLOW</name>
35993                <description>HW sets this field to '1', when PDM samples are generated too fast by the interface logic (interface overflow). This may be an indication that the IP system frequency is too low wrt. the interface frequency (a SW configuration error). The interface overflow is a non-recoverable error and requires SW disabling (CTL.ENABLED) of the receiver clearing INTR_RX.IF_OVERFLOW to '0' does not resolve the interface underflow).
35994
35995Note: This functionality is intended for debug purposes.</description>
35996                <bitRange>[8:8]</bitRange>
35997                <access>read-write</access>
35998              </field>
35999            </fields>
36000          </register>
36001          <register>
36002            <name>INTR_RX_SET</name>
36003            <description>Interrupt set</description>
36004            <addressOffset>0xC4</addressOffset>
36005            <size>32</size>
36006            <access>read-write</access>
36007            <resetValue>0x0</resetValue>
36008            <resetMask>0x117</resetMask>
36009            <fields>
36010              <field>
36011                <name>FIFO_TRIGGER</name>
36012                <description>Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect).</description>
36013                <bitRange>[0:0]</bitRange>
36014                <access>read-write</access>
36015              </field>
36016              <field>
36017                <name>FIFO_OVERFLOW</name>
36018                <description>Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect).</description>
36019                <bitRange>[1:1]</bitRange>
36020                <access>read-write</access>
36021              </field>
36022              <field>
36023                <name>FIFO_UNDERFLOW</name>
36024                <description>Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect).</description>
36025                <bitRange>[2:2]</bitRange>
36026                <access>read-write</access>
36027              </field>
36028              <field>
36029                <name>FIR_OVERFLOW</name>
36030                <description>Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect).</description>
36031                <bitRange>[4:4]</bitRange>
36032                <access>read-write</access>
36033              </field>
36034              <field>
36035                <name>IF_OVERFLOW</name>
36036                <description>Write this field with '1' to set corresponding INTR_RX field (a write of '0' has no effect).</description>
36037                <bitRange>[8:8]</bitRange>
36038                <access>read-write</access>
36039              </field>
36040            </fields>
36041          </register>
36042          <register>
36043            <name>INTR_RX_MASK</name>
36044            <description>Interrupt mask</description>
36045            <addressOffset>0xC8</addressOffset>
36046            <size>32</size>
36047            <access>read-write</access>
36048            <resetValue>0x0</resetValue>
36049            <resetMask>0x117</resetMask>
36050            <fields>
36051              <field>
36052                <name>FIFO_TRIGGER</name>
36053                <description>Mask for corresponding field in INTR_RX register.</description>
36054                <bitRange>[0:0]</bitRange>
36055                <access>read-write</access>
36056              </field>
36057              <field>
36058                <name>FIFO_OVERFLOW</name>
36059                <description>Mask for corresponding field in INTR_RX register.</description>
36060                <bitRange>[1:1]</bitRange>
36061                <access>read-write</access>
36062              </field>
36063              <field>
36064                <name>FIFO_UNDERFLOW</name>
36065                <description>Mask for corresponding field in INTR_RX register.</description>
36066                <bitRange>[2:2]</bitRange>
36067                <access>read-write</access>
36068              </field>
36069              <field>
36070                <name>FIR_OVERFLOW</name>
36071                <description>Mask for corresponding field in INTR_RX register.</description>
36072                <bitRange>[4:4]</bitRange>
36073                <access>read-write</access>
36074              </field>
36075              <field>
36076                <name>IF_OVERFLOW</name>
36077                <description>Mask for corresponding field in INTR_RX register.</description>
36078                <bitRange>[8:8]</bitRange>
36079                <access>read-write</access>
36080              </field>
36081            </fields>
36082          </register>
36083          <register>
36084            <name>INTR_RX_MASKED</name>
36085            <description>Interrupt masked</description>
36086            <addressOffset>0xCC</addressOffset>
36087            <size>32</size>
36088            <access>read-only</access>
36089            <resetValue>0x0</resetValue>
36090            <resetMask>0x117</resetMask>
36091            <fields>
36092              <field>
36093                <name>FIFO_TRIGGER</name>
36094                <description>Logical AND of corresponding INTR_RX and INTR_RX_MASK fields.</description>
36095                <bitRange>[0:0]</bitRange>
36096                <access>read-only</access>
36097              </field>
36098              <field>
36099                <name>FIFO_OVERFLOW</name>
36100                <description>Logical AND of corresponding INTR_RX and INTR_RX_MASK fields.</description>
36101                <bitRange>[1:1]</bitRange>
36102                <access>read-only</access>
36103              </field>
36104              <field>
36105                <name>FIFO_UNDERFLOW</name>
36106                <description>Logical AND of corresponding INTR_RX and INTR_RX_MASK fields.</description>
36107                <bitRange>[2:2]</bitRange>
36108                <access>read-only</access>
36109              </field>
36110              <field>
36111                <name>FIR_OVERFLOW</name>
36112                <description>Logical AND of corresponding INTR_RX and INTR_RX_MASK fields.</description>
36113                <bitRange>[4:4]</bitRange>
36114                <access>read-only</access>
36115              </field>
36116              <field>
36117                <name>IF_OVERFLOW</name>
36118                <description>Logical AND of corresponding INTR_RX and INTR_RX_MASK fields.</description>
36119                <bitRange>[8:8]</bitRange>
36120                <access>read-only</access>
36121              </field>
36122            </fields>
36123          </register>
36124        </cluster>
36125      </registers>
36126    </peripheral>
36127    <peripheral>
36128      <name>MXKEYSCAN</name>
36129      <description>0</description>
36130      <baseAddress>0x40920000</baseAddress>
36131      <addressBlock>
36132        <offset>0</offset>
36133        <size>4096</size>
36134        <usage>registers</usage>
36135      </addressBlock>
36136      <registers>
36137        <register>
36138          <name>KEYSCAN_CTL</name>
36139          <description>Keyscan Control Reg</description>
36140          <addressOffset>0x0</addressOffset>
36141          <size>32</size>
36142          <access>read-write</access>
36143          <resetValue>0x79FCC</resetValue>
36144          <resetMask>0x7FFDD</resetMask>
36145          <fields>
36146            <field>
36147              <name>KS_EN</name>
36148              <description>Enable the key scan module for keyboard function; specifically, the desired clock to the keyscan module is enabled.</description>
36149              <bitRange>[0:0]</bitRange>
36150              <access>read-write</access>
36151            </field>
36152            <field>
36153              <name>GHOST_EN</name>
36154              <description>Enable ghost detection</description>
36155              <bitRange>[2:2]</bitRange>
36156              <access>read-write</access>
36157            </field>
36158            <field>
36159              <name>KS_INT_EN</name>
36160              <description>This bit enables the keyscan block to wake the MCU module if key is detected.</description>
36161              <bitRange>[3:3]</bitRange>
36162              <access>read-write</access>
36163            </field>
36164            <field>
36165              <name>KYS_RST_EN</name>
36166              <description>Enable the reset of the debounce counters with kys_reported_clr bit; the reset clears the following registers: read/write counters for the event FIFO, debounce buffers, debouce counters, debouce up/down registers, cycle tracking registers and the keyscan read counter. For reset to take effect, the following two bits have to be set during clock unfreeze: this kys_rst_en and the 'reported_clear_kys' bit (note: ks_en can be at either states).</description>
36167              <bitRange>[4:4]</bitRange>
36168              <access>read-write</access>
36169            </field>
36170            <field>
36171              <name>RC_EXT</name>
36172              <description>Programmable idle duration between column scans.  For example, rc_ext[1:0] = 1 will provide 1 clock cycle idle time of no column scan. This is to alleviate the problem of slow RC delay on some of the keyboard design. The valid values for rc_ext are 1, 2, and 3 (default)</description>
36173              <bitRange>[7:6]</bitRange>
36174              <access>read-write</access>
36175            </field>
36176            <field>
36177              <name>RCTC_ROW</name>
36178              <description>set the number of rows of the key matrx; program to one less than the number of row in the keyboard.(default 7)</description>
36179              <bitRange>[10:8]</bitRange>
36180              <access>read-write</access>
36181            </field>
36182            <field>
36183              <name>RCTC_COLUMN</name>
36184              <description>set the number of columns of the key matrx; program to one less than the number of column in the keyboard (default 19)</description>
36185              <bitRange>[15:11]</bitRange>
36186              <access>read-write</access>
36187            </field>
36188            <field>
36189              <name>PULL_HIGH</name>
36190              <description>used to pull the columns high after each column scan to alleviate slow rise-time due to a large key matrix capacitance;default is on.</description>
36191              <bitRange>[16:16]</bitRange>
36192              <access>read-write</access>
36193            </field>
36194            <field>
36195              <name>KSI_DRV_HIGH</name>
36196              <description>(THIS IS NOT USED and implemented in RTL) when in keyboard application this bit enables KSI rows to be outputs and driven high to accelerate the pull-up resistor effect for avoiding false key detection due to otherwise slow rising node</description>
36197              <bitRange>[17:17]</bitRange>
36198              <access>read-write</access>
36199            </field>
36200            <field>
36201              <name>KYSCLK_STAYON</name>
36202              <description>the keyscan clock will stay on when set; otherwise, the clock will be gated off by when no activity is detected</description>
36203              <bitRange>[18:18]</bitRange>
36204              <access>read-write</access>
36205            </field>
36206          </fields>
36207        </register>
36208        <register>
36209          <name>DEBOUNCE</name>
36210          <description>Debounce (micro/macro)</description>
36211          <addressOffset>0x4</addressOffset>
36212          <size>32</size>
36213          <access>read-write</access>
36214          <resetValue>0x333</resetValue>
36215          <resetMask>0x3FF</resetMask>
36216          <fields>
36217            <field>
36218              <name>MD_DEBOUNCE</name>
36219              <description>macro down debounce count</description>
36220              <bitRange>[3:0]</bitRange>
36221              <access>read-write</access>
36222            </field>
36223            <field>
36224              <name>MU_DEBOUNCE</name>
36225              <description>macro up debounce count</description>
36226              <bitRange>[7:4]</bitRange>
36227              <access>read-write</access>
36228            </field>
36229            <field>
36230              <name>U_DEBOUNCE</name>
36231              <description>set the micro debounce count</description>
36232              <bitRange>[9:8]</bitRange>
36233              <access>read-write</access>
36234            </field>
36235          </fields>
36236        </register>
36237        <register>
36238          <name>KEYFIFO_CNT</name>
36239          <description>Number of entries in Key FIFO</description>
36240          <addressOffset>0x8</addressOffset>
36241          <size>32</size>
36242          <access>read-only</access>
36243          <resetValue>0x0</resetValue>
36244          <resetMask>0x1F</resetMask>
36245          <fields>
36246            <field>
36247              <name>KEYFIFO_CNT</name>
36248              <description>This register indicates the number of event that is ready for firmware access in the keycode event FIFO. Firmware to read this register before accessing the keycode event FIFO register. For example, a 1 on this register indicates that there is one event in the keycode event FIFO, so firmware can issue a read to the keycode event FIFO once. This number of key event is the accumulative key event count that is latched at the end of each hardware scan frame in a buffer register, it is then transferred to this event register when the 'freeze' is issued; its value is cleared when 'reported_clear_kys' bit is set in the mia_ctl_adr register.
36249Note:
36250Overflow condition (more than 20 keys detected in the scan cycle) may occur before the whole frame is scanned. If the 'overflow' bit is set and the keyfifo_cnt_adr register contains value that is less than 20, firmware needs to read this register a 2nd time. The balance of the event count will be automatically loaded into this register when the firmware issued 'reported_clear_kys' and 'unfreeze' if the hardware scan frame where overflow occurred has completed. However, perform a kys_rst_en maybe a better</description>
36251              <bitRange>[4:0]</bitRange>
36252              <access>read-only</access>
36253            </field>
36254          </fields>
36255        </register>
36256        <register>
36257          <name>KEYFIFO</name>
36258          <description>KEYFIFO values</description>
36259          <addressOffset>0xC</addressOffset>
36260          <size>32</size>
36261          <access>read-only</access>
36262          <resetValue>0x0</resetValue>
36263          <resetMask>0xC00000FF</resetMask>
36264          <fields>
36265            <field>
36266              <name>KEYFIFO</name>
36267              <description>contains detected key index; the event FIFO is 20-byte deep. After power up reset or soft reset defined by the 'kys_rst_en' bit, the event FIFO will contain 0xFF values.</description>
36268              <bitRange>[7:0]</bitRange>
36269              <access>read-only</access>
36270            </field>
36271            <field>
36272              <name>TRACK_SCAN_CYCLE</name>
36273              <description>a 1 or 0 value that indicates the hardware scan cycle that the key was detected; any key detected in the same hardware scan cycle will have the same track_cycle value. It toggles between 0 &amp; 1 whenever a key in a scan cycle is detected; in other words, this value doesn't change when there is no key detected in the current scan cycle</description>
36274              <bitRange>[30:30]</bitRange>
36275              <access>read-only</access>
36276            </field>
36277            <field>
36278              <name>KEY_UP_DOWN</name>
36279              <description>indicator of key up (1) or down (0) for each key entry in the FIFO. Each of these bits are associated with the key code at bit[7:0].</description>
36280              <bitRange>[31:31]</bitRange>
36281              <access>read-only</access>
36282            </field>
36283          </fields>
36284        </register>
36285        <register>
36286          <name>MIA_CTL</name>
36287          <description>MIA CTL (legacy)</description>
36288          <addressOffset>0x14</addressOffset>
36289          <size>32</size>
36290          <access>read-write</access>
36291          <resetValue>0x0</resetValue>
36292          <resetMask>0x7</resetMask>
36293          <fields>
36294            <field>
36295              <name>FREEZE_MIA</name>
36296              <description>This bit when set will latch the accumulated key event count for firmware to access via the keyfifo_cnt_adr. After setting the freeze' bit, firmware needs to poll the 'clkrc_freezed' bit (synchronized to the 24MHz clock in hardware) in the 'mia_status_adr' register until it goes high, at which time read access to keyfifo_cnt &amp; keyfifo_adr can proceed. After read access, firmware need to set this bit to low. The typical latency for freeze is 2.5 cycle of the 128KHz clock ~ 19.5us. Note: the clock in the keyscan module is not stopped when the freeze bit is set.</description>
36297              <bitRange>[0:0]</bitRange>
36298              <access>read-write</access>
36299            </field>
36300            <field>
36301              <name>REPORTED_CLEAR_KYS</name>
36302              <description>After reading the MIA registers, firmware set this bit to instruct the MIA keyscan module to clear the keycode status, ghost status, &amp; other internal registers. It is important that firmware clears and sets the bit properly (Read/write by uP). It is important to note that this bit only takes effect when the unfreeze occurs - it is a logical AND between this bit and the unfreeze that clears the registers. Therefore, it is advise that the firmware enters into any 'freeze operation' with the 'reported_clear_kys' bit cleared. (read/writable by uP, read only by MIA)</description>
36303              <bitRange>[1:1]</bitRange>
36304              <access>read-write</access>
36305            </field>
36306            <field>
36307              <name>CLK_LF_SEL</name>
36308              <description>There is a potential bug when CLK_LF_SEL=1, based on the internals of the mxtk_clk_dividere used, and the output of the divider could be stuck.  Please don't change this register unless there is a desperate need to debug the CLK_MF and switch over to only CLK_LF. ORIGINAL desicription: [Run the mxkeyscan internal processor at 32.786kHz, which will only work for small keypad sizes, and is an extreme way to lower power.  Default is to use the 2MHz clk_mf source from the IMO]</description>
36309              <bitRange>[2:2]</bitRange>
36310              <access>read-write</access>
36311            </field>
36312          </fields>
36313        </register>
36314        <register>
36315          <name>MIA_STATUS</name>
36316          <description>MIA STAUS (Legacy)</description>
36317          <addressOffset>0x18</addressOffset>
36318          <size>32</size>
36319          <access>read-only</access>
36320          <resetValue>0x0</resetValue>
36321          <resetMask>0x6F</resetMask>
36322          <fields>
36323            <field>
36324              <name>MIA_CLOCK_FREEZED_STATUS</name>
36325              <description>Firmware needs to poll this bit when trying to access/read the MIA registers. When this bit is high, the 'freeze' (bit 1 of the ksctl_adr register) is successful. Read access may proceed, otherwise, firmware has to wait and poll this bit until it is high. This bit is write by MIA and readable by the uP.</description>
36326              <bitRange>[0:0]</bitRange>
36327              <access>read-only</access>
36328            </field>
36329            <field>
36330              <name>KEYCODE_SET_STATUS</name>
36331              <description>(Note: these bits can be read anytime, no need to freeze the MIA clock)
36332
36333keycode_set indiates that the there is event in the key event FIFO.</description>
36334              <bitRange>[1:1]</bitRange>
36335              <access>read-only</access>
36336            </field>
36337            <field>
36338              <name>OVERFLOW_STATUS</name>
36339              <description>(Note: these bits can be read anytime, no need to freeze the MIA clock)
36340key FIFO overflow: The 20-byte key event FIFO overflows; more than 16 keys are pressed during current scan interval.</description>
36341              <bitRange>[2:2]</bitRange>
36342              <access>read-only</access>
36343            </field>
36344            <field>
36345              <name>GHOST_STATUS</name>
36346              <description>(Note: these bits can be read anytime, no need to freeze the MIA clock)
36347Ghost: indicates the ghost keys are detected; 0xF5 is inserted in the event FIFO. Refer to keyscan_ctl_adr for ghost enable bit.</description>
36348              <bitRange>[3:3]</bitRange>
36349              <access>read-only</access>
36350            </field>
36351            <field>
36352              <name>KYS_INT_SYNC_STATUS</name>
36353              <description>(Note: these bits can be read anytime, no need to freeze the MIA clock)
36354
36355kys_int_sync: status indicating that the keyscan interrupt is set. Refer to keyscan_ctl_adr for keyscan interruptenable - ks_int_en.</description>
36356              <bitRange>[5:5]</bitRange>
36357              <access>read-only</access>
36358            </field>
36359            <field>
36360              <name>CLK_G_TO_KYS_DBG</name>
36361              <description>Debug status bit, poll this to see if the clock toggles and the divider is working.  Double synced to clk_sys domain as an observe point also should help dft</description>
36362              <bitRange>[6:6]</bitRange>
36363              <access>read-only</access>
36364            </field>
36365          </fields>
36366        </register>
36367        <register>
36368          <name>KSI_USED</name>
36369          <description>Number of input key rows</description>
36370          <addressOffset>0x1C</addressOffset>
36371          <size>32</size>
36372          <access>read-write</access>
36373          <resetValue>0x7</resetValue>
36374          <resetMask>0x7</resetMask>
36375          <fields>
36376            <field>
36377              <name>KSI_USED</name>
36378              <description>define the number of row used for Keyscan; this definition is the same as that of the rctc register defined in MIA keyscan_ctl_adr[10:8]</description>
36379              <bitRange>[2:0]</bitRange>
36380              <access>read-write</access>
36381            </field>
36382          </fields>
36383        </register>
36384        <register>
36385          <name>INTR</name>
36386          <description>Interrupt</description>
36387          <addressOffset>0x20</addressOffset>
36388          <size>32</size>
36389          <access>read-write</access>
36390          <resetValue>0x0</resetValue>
36391          <resetMask>0x3</resetMask>
36392          <fields>
36393            <field>
36394              <name>KEY_EDGE</name>
36395              <description>HW sets this field to '1', when a INTERRUPT_KEY_EDGE trigger is generated.</description>
36396              <bitRange>[0:0]</bitRange>
36397              <access>read-write</access>
36398            </field>
36399            <field>
36400              <name>FIFO_THRESH</name>
36401              <description>HW sets this field to '1', when a INTERRUPT_FIFO_THRESH trigger is generated.</description>
36402              <bitRange>[1:1]</bitRange>
36403              <access>read-write</access>
36404            </field>
36405          </fields>
36406        </register>
36407        <register>
36408          <name>INTR_SET</name>
36409          <description>Interrupt set</description>
36410          <addressOffset>0x24</addressOffset>
36411          <size>32</size>
36412          <access>read-write</access>
36413          <resetValue>0x0</resetValue>
36414          <resetMask>0x3</resetMask>
36415          <fields>
36416            <field>
36417              <name>KEY_EDGE</name>
36418              <description>Write this field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
36419              <bitRange>[0:0]</bitRange>
36420              <access>read-write</access>
36421            </field>
36422            <field>
36423              <name>FIFO_THRESH</name>
36424              <description>Write this field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
36425              <bitRange>[1:1]</bitRange>
36426              <access>read-write</access>
36427            </field>
36428          </fields>
36429        </register>
36430        <register>
36431          <name>INTR_MASK</name>
36432          <description>Interrupt mask</description>
36433          <addressOffset>0x28</addressOffset>
36434          <size>32</size>
36435          <access>read-write</access>
36436          <resetValue>0x0</resetValue>
36437          <resetMask>0x3</resetMask>
36438          <fields>
36439            <field>
36440              <name>KEY_EDGE</name>
36441              <description>Mask for corresponding field in INTR register.</description>
36442              <bitRange>[0:0]</bitRange>
36443              <access>read-write</access>
36444            </field>
36445            <field>
36446              <name>FIFO_THRESH</name>
36447              <description>Mask for corresponding field in INTR register.</description>
36448              <bitRange>[1:1]</bitRange>
36449              <access>read-write</access>
36450            </field>
36451          </fields>
36452        </register>
36453        <register>
36454          <name>INTR_MASKED</name>
36455          <description>Interrupt mask</description>
36456          <addressOffset>0x2C</addressOffset>
36457          <size>32</size>
36458          <access>read-only</access>
36459          <resetValue>0x0</resetValue>
36460          <resetMask>0x3</resetMask>
36461          <fields>
36462            <field>
36463              <name>KEY_EDGE</name>
36464              <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
36465              <bitRange>[0:0]</bitRange>
36466              <access>read-only</access>
36467            </field>
36468            <field>
36469              <name>FIFO_THRESH</name>
36470              <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
36471              <bitRange>[1:1]</bitRange>
36472              <access>read-only</access>
36473            </field>
36474          </fields>
36475        </register>
36476      </registers>
36477    </peripheral>
36478    <peripheral>
36479      <name>BTSS</name>
36480      <description>MXS40BLE52SS IP</description>
36481      <baseAddress>0x42000000</baseAddress>
36482      <addressBlock>
36483        <offset>0</offset>
36484        <size>16777216</size>
36485        <usage>registers</usage>
36486      </addressBlock>
36487      <registers>
36488        <cluster>
36489          <name>DATA_RAM_IPC</name>
36490          <description>N/A</description>
36491          <addressOffset>0x00600000</addressOffset>
36492          <register>
36493            <name>MXIPC_0_ACQUIRE</name>
36494            <description>N/A</description>
36495            <addressOffset>0x80000</addressOffset>
36496            <size>32</size>
36497            <access>read-write</access>
36498            <resetValue>0x0</resetValue>
36499            <resetMask>0x80000000</resetMask>
36500            <fields>
36501              <field>
36502                <name>MXIPC_0_ACQUIRE_P</name>
36503                <description>User/privileged access control:
36504'0': user mode.
36505'1': privileged mode.
36506
36507This field is set with the user/privileged access control of the access that successfully acquired the lock.</description>
36508                <bitRange>[0:0]</bitRange>
36509                <access>read-only</access>
36510              </field>
36511              <field>
36512                <name>MXIPC_0_ACQUIRE_NS</name>
36513                <description>Secure/non-secure access control:
36514'0': secure.
36515'1': non-secure.
36516
36517This field is set with the secure/non-secure access control of the access that successfully acquired the lock.</description>
36518                <bitRange>[1:1]</bitRange>
36519                <access>read-only</access>
36520              </field>
36521              <field>
36522                <name>MXIPC_0_ACQUIRE_PC</name>
36523                <description>This field specifies the protection context that successfully acquired the lock.</description>
36524                <bitRange>[7:4]</bitRange>
36525                <access>read-only</access>
36526              </field>
36527              <field>
36528                <name>MXIPC_0_ACQUIRE_MS</name>
36529                <description>This field specifies the bus master identifier ({HMASTER[MASTER_WIDTH-2:0], HMASTER[MASTER_WIDTH}) that successfully acquired the lock. (MASTER_WIDTH = 4)</description>
36530                <bitRange>[15:8]</bitRange>
36531                <access>read-only</access>
36532              </field>
36533              <field>
36534                <name>MXIPC_0_ACQUIRE_SUCCESS</name>
36535                <description>Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED):
36536'0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access.
36537'1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access.
36538
36539Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value).</description>
36540                <bitRange>[31:31]</bitRange>
36541                <access>read-write</access>
36542              </field>
36543            </fields>
36544          </register>
36545          <register>
36546            <name>MXIPC_0_RELEASE</name>
36547            <description>N/A</description>
36548            <addressOffset>0x80004</addressOffset>
36549            <size>32</size>
36550            <access>read-write</access>
36551            <resetValue>0x0</resetValue>
36552            <resetMask>0xFFFFFFFF</resetMask>
36553            <fields>
36554              <field>
36555                <name>MXIPC_0_RELEASE</name>
36556                <description>Writing this field releases a lock and allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'.
36557
36558SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field.</description>
36559                <bitRange>[31:0]</bitRange>
36560                <access>read-write</access>
36561              </field>
36562            </fields>
36563          </register>
36564          <register>
36565            <name>MXIPC_0_NOTIFY</name>
36566            <description>N/A</description>
36567            <addressOffset>0x80008</addressOffset>
36568            <size>32</size>
36569            <access>read-write</access>
36570            <resetValue>0x0</resetValue>
36571            <resetMask>0xFFFFFFFF</resetMask>
36572            <fields>
36573              <field>
36574                <name>MXIPC_0_NOTIFY</name>
36575                <description>This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'.
36576
36577SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field.</description>
36578                <bitRange>[31:0]</bitRange>
36579                <access>read-write</access>
36580              </field>
36581            </fields>
36582          </register>
36583          <register>
36584            <name>MXIPC_0_DATA0</name>
36585            <description>N/A</description>
36586            <addressOffset>0x8000C</addressOffset>
36587            <size>32</size>
36588            <access>read-write</access>
36589            <resetValue>0x0</resetValue>
36590            <resetMask>0xFFFFFFFF</resetMask>
36591            <fields>
36592              <field>
36593                <name>MXIPC_0_DATA0</name>
36594                <description>This field holds a 32-bit data element that is associated with the IPC structure.</description>
36595                <bitRange>[31:0]</bitRange>
36596                <access>read-write</access>
36597              </field>
36598            </fields>
36599          </register>
36600          <register>
36601            <name>MXIPC_0_DATA1</name>
36602            <description>N/A</description>
36603            <addressOffset>0x80010</addressOffset>
36604            <size>32</size>
36605            <access>read-write</access>
36606            <resetValue>0x0</resetValue>
36607            <resetMask>0xFFFFFFFF</resetMask>
36608            <fields>
36609              <field>
36610                <name>MXIPC_0_DATA1</name>
36611                <description>This field holds a 32-bit data element that is associated with the IPC structure.</description>
36612                <bitRange>[31:0]</bitRange>
36613                <access>read-write</access>
36614              </field>
36615            </fields>
36616          </register>
36617          <register>
36618            <name>MXIPC_0_LOCK_STATUS</name>
36619            <description>N/A</description>
36620            <addressOffset>0x8001C</addressOffset>
36621            <size>32</size>
36622            <access>read-only</access>
36623            <resetValue>0x0</resetValue>
36624            <resetMask>0x80000000</resetMask>
36625            <fields>
36626              <field>
36627                <name>MXIPC_0_LOCK_STATUS_P</name>
36628                <description>This field specifies the user/privileged access control:
36629'0': user mode.
36630'1': privileged mode.</description>
36631                <bitRange>[0:0]</bitRange>
36632                <access>read-only</access>
36633              </field>
36634              <field>
36635                <name>MXIPC_0_LOCK_STATUS_NS</name>
36636                <description>This field specifies the secure/non-secure access control:
36637'0': secure.
36638'1': non-secure.</description>
36639                <bitRange>[1:1]</bitRange>
36640                <access>read-only</access>
36641              </field>
36642              <field>
36643                <name>MXIPC_0_LOCK_STATUS_PC</name>
36644                <description>This field specifies the protection context that successfully acquired the lock.</description>
36645                <bitRange>[7:4]</bitRange>
36646                <access>read-only</access>
36647              </field>
36648              <field>
36649                <name>MXIPC_0_LOCK_STATUS_MS</name>
36650                <description>This field specifies the bus master identifier ({HMASTER[MASTER_WIDTH-2:0], HMASTER[MASTER_WIDTH}) that successfully acquired the lock. (MASTER_WIDTH = 4)</description>
36651                <bitRange>[15:8]</bitRange>
36652                <access>read-only</access>
36653              </field>
36654              <field>
36655                <name>MXIPC_0_LOCK_STATUS_ACQUIRED</name>
36656                <description>Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1'). If zero, P, NS, PC, and MS are not valid.</description>
36657                <bitRange>[31:31]</bitRange>
36658                <access>read-only</access>
36659              </field>
36660            </fields>
36661          </register>
36662          <register>
36663            <name>MXIPC_1_ACQUIRE</name>
36664            <description>N/A</description>
36665            <addressOffset>0x80020</addressOffset>
36666            <size>32</size>
36667            <access>read-write</access>
36668            <resetValue>0x0</resetValue>
36669            <resetMask>0x80000000</resetMask>
36670            <fields>
36671              <field>
36672                <name>MXIPC_1_ACQUIRE_P</name>
36673                <description>User/privileged access control:
36674'0': user mode.
36675'1': privileged mode.
36676
36677This field is set with the user/privileged access control of the access that successfully acquired the lock.</description>
36678                <bitRange>[0:0]</bitRange>
36679                <access>read-only</access>
36680              </field>
36681              <field>
36682                <name>MXIPC_1_ACQUIRE_NS</name>
36683                <description>Secure/non-secure access control:
36684'0': secure.
36685'1': non-secure.
36686
36687This field is set with the secure/non-secure access control of the access that successfully acquired the lock.</description>
36688                <bitRange>[1:1]</bitRange>
36689                <access>read-only</access>
36690              </field>
36691              <field>
36692                <name>MXIPC_1_ACQUIRE_PC</name>
36693                <description>This field specifies the protection context that successfully acquired the lock.</description>
36694                <bitRange>[7:4]</bitRange>
36695                <access>read-only</access>
36696              </field>
36697              <field>
36698                <name>MXIPC_1_ACQUIRE_MS</name>
36699                <description>This field specifies the bus master identifier ({HMASTER[MASTER_WIDTH-2:0], HMASTER[MASTER_WIDTH}) that successfully acquired the lock. (MASTER_WIDTH = 4)</description>
36700                <bitRange>[15:8]</bitRange>
36701                <access>read-only</access>
36702              </field>
36703              <field>
36704                <name>MXIPC_1_ACQUIRE_SUCCESS</name>
36705                <description>Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED):
36706'0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access.
36707'1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access.
36708
36709Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value).</description>
36710                <bitRange>[31:31]</bitRange>
36711                <access>read-write</access>
36712              </field>
36713            </fields>
36714          </register>
36715          <register>
36716            <name>MXIPC_1_RELEASE</name>
36717            <description>N/A</description>
36718            <addressOffset>0x80024</addressOffset>
36719            <size>32</size>
36720            <access>read-write</access>
36721            <resetValue>0x0</resetValue>
36722            <resetMask>0xFFFFFFFF</resetMask>
36723            <fields>
36724              <field>
36725                <name>MXIPC_1_RELEASE</name>
36726                <description>Writing this field releases a lock and allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'.
36727
36728SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field.</description>
36729                <bitRange>[31:0]</bitRange>
36730                <access>read-write</access>
36731              </field>
36732            </fields>
36733          </register>
36734          <register>
36735            <name>MXIPC_1_NOTIFY</name>
36736            <description>N/A</description>
36737            <addressOffset>0x80028</addressOffset>
36738            <size>32</size>
36739            <access>read-write</access>
36740            <resetValue>0x0</resetValue>
36741            <resetMask>0xFFFFFFFF</resetMask>
36742            <fields>
36743              <field>
36744                <name>MXIPC_1_NOTIFY</name>
36745                <description>This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'.
36746
36747SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field.</description>
36748                <bitRange>[31:0]</bitRange>
36749                <access>read-write</access>
36750              </field>
36751            </fields>
36752          </register>
36753          <register>
36754            <name>MXIPC_1_DATA0</name>
36755            <description>N/A</description>
36756            <addressOffset>0x8002C</addressOffset>
36757            <size>32</size>
36758            <access>read-write</access>
36759            <resetValue>0x0</resetValue>
36760            <resetMask>0xFFFFFFFF</resetMask>
36761            <fields>
36762              <field>
36763                <name>MXIPC_1_DATA0</name>
36764                <description>This field holds a 32-bit data element that is associated with the IPC structure.</description>
36765                <bitRange>[31:0]</bitRange>
36766                <access>read-write</access>
36767              </field>
36768            </fields>
36769          </register>
36770          <register>
36771            <name>MXIPC_1_DATA1</name>
36772            <description>N/A</description>
36773            <addressOffset>0x80030</addressOffset>
36774            <size>32</size>
36775            <access>read-write</access>
36776            <resetValue>0x0</resetValue>
36777            <resetMask>0xFFFFFFFF</resetMask>
36778            <fields>
36779              <field>
36780                <name>MXIPC_1_DATA1</name>
36781                <description>This field holds a 32-bit data element that is associated with the IPC structure.</description>
36782                <bitRange>[31:0]</bitRange>
36783                <access>read-write</access>
36784              </field>
36785            </fields>
36786          </register>
36787          <register>
36788            <name>MXIPC_1_LOCK_STATUS</name>
36789            <description>N/A</description>
36790            <addressOffset>0x8003C</addressOffset>
36791            <size>32</size>
36792            <access>read-only</access>
36793            <resetValue>0x0</resetValue>
36794            <resetMask>0x80000000</resetMask>
36795            <fields>
36796              <field>
36797                <name>MXIPC_1_LOCK_STATUS_P</name>
36798                <description>This field specifies the user/privileged access control:
36799'0': user mode.
36800'1': privileged mode.</description>
36801                <bitRange>[0:0]</bitRange>
36802                <access>read-only</access>
36803              </field>
36804              <field>
36805                <name>MXIPC_1_LOCK_STATUS_NS</name>
36806                <description>This field specifies the secure/non-secure access control:
36807'0': secure.
36808'1': non-secure.</description>
36809                <bitRange>[1:1]</bitRange>
36810                <access>read-only</access>
36811              </field>
36812              <field>
36813                <name>MXIPC_1_LOCK_STATUS_PC</name>
36814                <description>This field specifies the protection context that successfully acquired the lock.</description>
36815                <bitRange>[7:4]</bitRange>
36816                <access>read-only</access>
36817              </field>
36818              <field>
36819                <name>MXIPC_1_LOCK_STATUS_MS</name>
36820                <description>This field specifies the bus master identifier ({HMASTER[MASTER_WIDTH-2:0], HMASTER[MASTER_WIDTH}) that successfully acquired the lock. (MASTER_WIDTH = 4)</description>
36821                <bitRange>[15:8]</bitRange>
36822                <access>read-only</access>
36823              </field>
36824              <field>
36825                <name>MXIPC_1_LOCK_STATUS_ACQUIRED</name>
36826                <description>Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1'). If zero, P, NS, PC, and MS are not valid.</description>
36827                <bitRange>[31:31]</bitRange>
36828                <access>read-only</access>
36829              </field>
36830            </fields>
36831          </register>
36832          <register>
36833            <name>MXIPC_2_ACQUIRE</name>
36834            <description>N/A</description>
36835            <addressOffset>0x80040</addressOffset>
36836            <size>32</size>
36837            <access>read-write</access>
36838            <resetValue>0x0</resetValue>
36839            <resetMask>0x80000000</resetMask>
36840            <fields>
36841              <field>
36842                <name>MXIPC_2_ACQUIRE_P</name>
36843                <description>User/privileged access control:
36844'0': user mode.
36845'1': privileged mode.
36846
36847This field is set with the user/privileged access control of the access that successfully acquired the lock.</description>
36848                <bitRange>[0:0]</bitRange>
36849                <access>read-only</access>
36850              </field>
36851              <field>
36852                <name>MXIPC_2_ACQUIRE_NS</name>
36853                <description>Secure/non-secure access control:
36854'0': secure.
36855'1': non-secure.
36856
36857This field is set with the secure/non-secure access control of the access that successfully acquired the lock.</description>
36858                <bitRange>[1:1]</bitRange>
36859                <access>read-only</access>
36860              </field>
36861              <field>
36862                <name>MXIPC_2_ACQUIRE_PC</name>
36863                <description>This field specifies the protection context that successfully acquired the lock.</description>
36864                <bitRange>[7:4]</bitRange>
36865                <access>read-only</access>
36866              </field>
36867              <field>
36868                <name>MXIPC_2_ACQUIRE_MS</name>
36869                <description>This field specifies the bus master identifier ({HMASTER[MASTER_WIDTH-2:0], HMASTER[MASTER_WIDTH}) that successfully acquired the lock. (MASTER_WIDTH = 4)</description>
36870                <bitRange>[15:8]</bitRange>
36871                <access>read-only</access>
36872              </field>
36873              <field>
36874                <name>MXIPC_2_ACQUIRE_SUCCESS</name>
36875                <description>Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED):
36876'0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access.
36877'1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access.
36878
36879Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value).</description>
36880                <bitRange>[31:31]</bitRange>
36881                <access>read-write</access>
36882              </field>
36883            </fields>
36884          </register>
36885          <register>
36886            <name>MXIPC_2_RELEASE</name>
36887            <description>N/A</description>
36888            <addressOffset>0x80044</addressOffset>
36889            <size>32</size>
36890            <access>read-write</access>
36891            <resetValue>0x0</resetValue>
36892            <resetMask>0xFFFFFFFF</resetMask>
36893            <fields>
36894              <field>
36895                <name>MXIPC_2_RELEASE</name>
36896                <description>Writing this field releases a lock and allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'.
36897
36898SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field.</description>
36899                <bitRange>[31:0]</bitRange>
36900                <access>read-write</access>
36901              </field>
36902            </fields>
36903          </register>
36904          <register>
36905            <name>MXIPC_2_NOTIFY</name>
36906            <description>N/A</description>
36907            <addressOffset>0x80048</addressOffset>
36908            <size>32</size>
36909            <access>read-write</access>
36910            <resetValue>0x0</resetValue>
36911            <resetMask>0xFFFFFFFF</resetMask>
36912            <fields>
36913              <field>
36914                <name>MXIPC_2_NOTIFY</name>
36915                <description>This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'.
36916
36917SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field.</description>
36918                <bitRange>[31:0]</bitRange>
36919                <access>read-write</access>
36920              </field>
36921            </fields>
36922          </register>
36923          <register>
36924            <name>MXIPC_2_DATA0</name>
36925            <description>N/A</description>
36926            <addressOffset>0x8004C</addressOffset>
36927            <size>32</size>
36928            <access>read-write</access>
36929            <resetValue>0x0</resetValue>
36930            <resetMask>0xFFFFFFFF</resetMask>
36931            <fields>
36932              <field>
36933                <name>MXIPC_2_DATA0</name>
36934                <description>This field holds a 32-bit data element that is associated with the IPC structure.</description>
36935                <bitRange>[31:0]</bitRange>
36936                <access>read-write</access>
36937              </field>
36938            </fields>
36939          </register>
36940          <register>
36941            <name>MXIPC_2_DATA1</name>
36942            <description>N/A</description>
36943            <addressOffset>0x80050</addressOffset>
36944            <size>32</size>
36945            <access>read-write</access>
36946            <resetValue>0x0</resetValue>
36947            <resetMask>0xFFFFFFFF</resetMask>
36948            <fields>
36949              <field>
36950                <name>MXIPC_2_DATA1</name>
36951                <description>This field holds a 32-bit data element that is associated with the IPC structure.</description>
36952                <bitRange>[31:0]</bitRange>
36953                <access>read-write</access>
36954              </field>
36955            </fields>
36956          </register>
36957          <register>
36958            <name>MXIPC_2_LOCK_STATUS</name>
36959            <description>N/A</description>
36960            <addressOffset>0x8005C</addressOffset>
36961            <size>32</size>
36962            <access>read-only</access>
36963            <resetValue>0x0</resetValue>
36964            <resetMask>0x80000000</resetMask>
36965            <fields>
36966              <field>
36967                <name>MXIPC_2_LOCK_STATUS_P</name>
36968                <description>This field specifies the user/privileged access control:
36969'0': user mode.
36970'1': privileged mode.</description>
36971                <bitRange>[0:0]</bitRange>
36972                <access>read-only</access>
36973              </field>
36974              <field>
36975                <name>MXIPC_2_LOCK_STATUS_NS</name>
36976                <description>This field specifies the secure/non-secure access control:
36977'0': secure.
36978'1': non-secure.</description>
36979                <bitRange>[1:1]</bitRange>
36980                <access>read-only</access>
36981              </field>
36982              <field>
36983                <name>MXIPC_2_LOCK_STATUS_PC</name>
36984                <description>This field specifies the protection context that successfully acquired the lock.</description>
36985                <bitRange>[7:4]</bitRange>
36986                <access>read-only</access>
36987              </field>
36988              <field>
36989                <name>MXIPC_2_LOCK_STATUS_MS</name>
36990                <description>This field specifies the bus master identifier ({HMASTER[MASTER_WIDTH-2:0], HMASTER[MASTER_WIDTH}) that successfully acquired the lock. (MASTER_WIDTH = 4)</description>
36991                <bitRange>[15:8]</bitRange>
36992                <access>read-only</access>
36993              </field>
36994              <field>
36995                <name>MXIPC_2_LOCK_STATUS_ACQUIRED</name>
36996                <description>Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1'). If zero, P, NS, PC, and MS are not valid.</description>
36997                <bitRange>[31:31]</bitRange>
36998                <access>read-only</access>
36999              </field>
37000            </fields>
37001          </register>
37002          <register>
37003            <name>MXIPC_3_ACQUIRE</name>
37004            <description>N/A</description>
37005            <addressOffset>0x80060</addressOffset>
37006            <size>32</size>
37007            <access>read-write</access>
37008            <resetValue>0x0</resetValue>
37009            <resetMask>0x80000000</resetMask>
37010            <fields>
37011              <field>
37012                <name>MXIPC_3_ACQUIRE_P</name>
37013                <description>User/privileged access control:
37014'0': user mode.
37015'1': privileged mode.
37016
37017This field is set with the user/privileged access control of the access that successfully acquired the lock.</description>
37018                <bitRange>[0:0]</bitRange>
37019                <access>read-only</access>
37020              </field>
37021              <field>
37022                <name>MXIPC_3_ACQUIRE_NS</name>
37023                <description>Secure/non-secure access control:
37024'0': secure.
37025'1': non-secure.
37026
37027This field is set with the secure/non-secure access control of the access that successfully acquired the lock.</description>
37028                <bitRange>[1:1]</bitRange>
37029                <access>read-only</access>
37030              </field>
37031              <field>
37032                <name>MXIPC_3_ACQUIRE_PC</name>
37033                <description>This field specifies the protection context that successfully acquired the lock.</description>
37034                <bitRange>[7:4]</bitRange>
37035                <access>read-only</access>
37036              </field>
37037              <field>
37038                <name>MXIPC_3_ACQUIRE_MS</name>
37039                <description>This field specifies the bus master identifier ({HMASTER[MASTER_WIDTH-2:0], HMASTER[MASTER_WIDTH}) that successfully acquired the lock. (MASTER_WIDTH = 4)</description>
37040                <bitRange>[15:8]</bitRange>
37041                <access>read-only</access>
37042              </field>
37043              <field>
37044                <name>MXIPC_3_ACQUIRE_SUCCESS</name>
37045                <description>Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED):
37046'0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access.
37047'1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access.
37048
37049Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value).</description>
37050                <bitRange>[31:31]</bitRange>
37051                <access>read-write</access>
37052              </field>
37053            </fields>
37054          </register>
37055          <register>
37056            <name>MXIPC_3_RELEASE</name>
37057            <description>N/A</description>
37058            <addressOffset>0x80064</addressOffset>
37059            <size>32</size>
37060            <access>read-write</access>
37061            <resetValue>0x0</resetValue>
37062            <resetMask>0xFFFFFFFF</resetMask>
37063            <fields>
37064              <field>
37065                <name>MXIPC_3_RELEASE</name>
37066                <description>Writing this field releases a lock and allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'.
37067
37068SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field.</description>
37069                <bitRange>[31:0]</bitRange>
37070                <access>read-write</access>
37071              </field>
37072            </fields>
37073          </register>
37074          <register>
37075            <name>MXIPC_3_NOTIFY</name>
37076            <description>N/A</description>
37077            <addressOffset>0x80068</addressOffset>
37078            <size>32</size>
37079            <access>read-write</access>
37080            <resetValue>0x0</resetValue>
37081            <resetMask>0xFFFFFFFF</resetMask>
37082            <fields>
37083              <field>
37084                <name>MXIPC_3_NOTIFY</name>
37085                <description>This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'.
37086
37087SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field.</description>
37088                <bitRange>[31:0]</bitRange>
37089                <access>read-write</access>
37090              </field>
37091            </fields>
37092          </register>
37093          <register>
37094            <name>MXIPC_3_DATA0</name>
37095            <description>N/A</description>
37096            <addressOffset>0x8006C</addressOffset>
37097            <size>32</size>
37098            <access>read-write</access>
37099            <resetValue>0x0</resetValue>
37100            <resetMask>0xFFFFFFFF</resetMask>
37101            <fields>
37102              <field>
37103                <name>MXIPC_3_DATA0</name>
37104                <description>This field holds a 32-bit data element that is associated with the IPC structure.</description>
37105                <bitRange>[31:0]</bitRange>
37106                <access>read-write</access>
37107              </field>
37108            </fields>
37109          </register>
37110          <register>
37111            <name>MXIPC_3_DATA1</name>
37112            <description>N/A</description>
37113            <addressOffset>0x80070</addressOffset>
37114            <size>32</size>
37115            <access>read-write</access>
37116            <resetValue>0x0</resetValue>
37117            <resetMask>0xFFFFFFFF</resetMask>
37118            <fields>
37119              <field>
37120                <name>MXIPC_3_DATA1</name>
37121                <description>This field holds a 32-bit data element that is associated with the IPC structure.</description>
37122                <bitRange>[31:0]</bitRange>
37123                <access>read-write</access>
37124              </field>
37125            </fields>
37126          </register>
37127          <register>
37128            <name>MXIPC_3_LOCK_STATUS</name>
37129            <description>N/A</description>
37130            <addressOffset>0x8007C</addressOffset>
37131            <size>32</size>
37132            <access>read-only</access>
37133            <resetValue>0x0</resetValue>
37134            <resetMask>0x80000000</resetMask>
37135            <fields>
37136              <field>
37137                <name>MXIPC_3_LOCK_STATUS_P</name>
37138                <description>This field specifies the user/privileged access control:
37139'0': user mode.
37140'1': privileged mode.</description>
37141                <bitRange>[0:0]</bitRange>
37142                <access>read-only</access>
37143              </field>
37144              <field>
37145                <name>MXIPC_3_LOCK_STATUS_NS</name>
37146                <description>This field specifies the secure/non-secure access control:
37147'0': secure.
37148'1': non-secure.</description>
37149                <bitRange>[1:1]</bitRange>
37150                <access>read-only</access>
37151              </field>
37152              <field>
37153                <name>MXIPC_3_LOCK_STATUS_PC</name>
37154                <description>This field specifies the protection context that successfully acquired the lock.</description>
37155                <bitRange>[7:4]</bitRange>
37156                <access>read-only</access>
37157              </field>
37158              <field>
37159                <name>MXIPC_3_LOCK_STATUS_MS</name>
37160                <description>This field specifies the bus master identifier ({HMASTER[MASTER_WIDTH-2:0], HMASTER[MASTER_WIDTH}) that successfully acquired the lock. (MASTER_WIDTH = 4)</description>
37161                <bitRange>[15:8]</bitRange>
37162                <access>read-only</access>
37163              </field>
37164              <field>
37165                <name>MXIPC_3_LOCK_STATUS_ACQUIRED</name>
37166                <description>Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1'). If zero, P, NS, PC, and MS are not valid.</description>
37167                <bitRange>[31:31]</bitRange>
37168                <access>read-only</access>
37169              </field>
37170            </fields>
37171          </register>
37172          <register>
37173            <name>MXIPC_INTR_0</name>
37174            <description>N/A</description>
37175            <addressOffset>0x81000</addressOffset>
37176            <size>32</size>
37177            <access>read-write</access>
37178            <resetValue>0x0</resetValue>
37179            <resetMask>0xFFFFFFFF</resetMask>
37180            <fields>
37181              <field>
37182                <name>MXIPC_INTR_0_MXIPC_INTR_0_RELEASE_______</name>
37183                <description>These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.</description>
37184                <bitRange>[15:0]</bitRange>
37185                <access>read-write</access>
37186              </field>
37187              <field>
37188                <name>MXIPC_INTR_0_MXIPC_INTR_0_NOTIFY</name>
37189                <description>These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.</description>
37190                <bitRange>[31:16]</bitRange>
37191                <access>read-write</access>
37192              </field>
37193            </fields>
37194          </register>
37195          <register>
37196            <name>MXIPC_INTR_0_SET</name>
37197            <description>N/A</description>
37198            <addressOffset>0x81004</addressOffset>
37199            <size>32</size>
37200            <access>read-write</access>
37201            <resetValue>0x0</resetValue>
37202            <resetMask>0xFFFFFFFF</resetMask>
37203            <fields>
37204              <field>
37205                <name>MXIPC_INTR_0_SET_MXIPC_INTR_0_SET_RELEASE_______</name>
37206                <description>SW writes a '1' to this field to set the corresponding field in the INTR register.</description>
37207                <bitRange>[15:0]</bitRange>
37208                <access>read-write</access>
37209              </field>
37210              <field>
37211                <name>MXIPC_INTR_0_SET_MXIPC_INTR_0_SET_NOTIFY</name>
37212                <description>SW writes a '1' to this field to set the corresponding field in the INTR register.</description>
37213                <bitRange>[31:16]</bitRange>
37214                <access>read-write</access>
37215              </field>
37216            </fields>
37217          </register>
37218          <register>
37219            <name>MXIPC_INTR_0_MASK</name>
37220            <description>N/A</description>
37221            <addressOffset>0x81008</addressOffset>
37222            <size>32</size>
37223            <access>read-write</access>
37224            <resetValue>0x0</resetValue>
37225            <resetMask>0xFFFFFFFF</resetMask>
37226            <fields>
37227              <field>
37228                <name>MXIPC_INTR_0_MASK_MXIPC_INTR_0_MASK_RELEASE_______</name>
37229                <description>Mask bit for corresponding field in the INTR register.</description>
37230                <bitRange>[15:0]</bitRange>
37231                <access>read-write</access>
37232              </field>
37233              <field>
37234                <name>MXIPC_INTR_0_MASK_MXIPC_INTR_0_MASK_NOTIFY</name>
37235                <description>Mask bit for corresponding field in the INTR register.</description>
37236                <bitRange>[31:16]</bitRange>
37237                <access>read-write</access>
37238              </field>
37239            </fields>
37240          </register>
37241          <register>
37242            <name>MXIPC_INTR_0_MASKED</name>
37243            <description>N/A</description>
37244            <addressOffset>0x8100C</addressOffset>
37245            <size>32</size>
37246            <access>read-only</access>
37247            <resetValue>0x0</resetValue>
37248            <resetMask>0xFFFFFFFF</resetMask>
37249            <fields>
37250              <field>
37251                <name>MXIPC_INTR_0_MASKED_MXIPC_INTR_0_MASKED_RELEASE_______</name>
37252                <description>Logical and of corresponding request and mask bits.</description>
37253                <bitRange>[15:0]</bitRange>
37254                <access>read-only</access>
37255              </field>
37256              <field>
37257                <name>MXIPC_INTR_0_MASKED_MXIPC_INTR_0_MASKED_NOTIFY</name>
37258                <description>Logical and of corresponding INTR and INTR_MASK fields.</description>
37259                <bitRange>[31:16]</bitRange>
37260                <access>read-only</access>
37261              </field>
37262            </fields>
37263          </register>
37264          <register>
37265            <name>MXIPC_INTR_1</name>
37266            <description>N/A</description>
37267            <addressOffset>0x81020</addressOffset>
37268            <size>32</size>
37269            <access>read-write</access>
37270            <resetValue>0x0</resetValue>
37271            <resetMask>0xFFFFFFFF</resetMask>
37272            <fields>
37273              <field>
37274                <name>MXIPC_INTR_1_MXIPC_INTR_1_RELEASE_______</name>
37275                <description>These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.</description>
37276                <bitRange>[15:0]</bitRange>
37277                <access>read-write</access>
37278              </field>
37279              <field>
37280                <name>MXIPC_INTR_1_MXIPC_INTR_1_NOTIFY</name>
37281                <description>These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.</description>
37282                <bitRange>[31:16]</bitRange>
37283                <access>read-write</access>
37284              </field>
37285            </fields>
37286          </register>
37287          <register>
37288            <name>MXIPC_INTR_1_SET</name>
37289            <description>N/A</description>
37290            <addressOffset>0x81024</addressOffset>
37291            <size>32</size>
37292            <access>read-write</access>
37293            <resetValue>0x0</resetValue>
37294            <resetMask>0xFFFFFFFF</resetMask>
37295            <fields>
37296              <field>
37297                <name>MXIPC_INTR_1_SET_MXIPC_INTR_1_SET_RELEASE_______</name>
37298                <description>SW writes a '1' to this field to set the corresponding field in the INTR register.</description>
37299                <bitRange>[15:0]</bitRange>
37300                <access>read-write</access>
37301              </field>
37302              <field>
37303                <name>MXIPC_INTR_1_SET_MXIPC_INTR_1_SET_NOTIFY</name>
37304                <description>SW writes a '1' to this field to set the corresponding field in the INTR register.</description>
37305                <bitRange>[31:16]</bitRange>
37306                <access>read-write</access>
37307              </field>
37308            </fields>
37309          </register>
37310          <register>
37311            <name>MXIPC_INTR_1_MASK</name>
37312            <description>N/A</description>
37313            <addressOffset>0x81028</addressOffset>
37314            <size>32</size>
37315            <access>read-write</access>
37316            <resetValue>0x0</resetValue>
37317            <resetMask>0xFFFFFFFF</resetMask>
37318            <fields>
37319              <field>
37320                <name>MXIPC_INTR_1_MASK_MXIPC_INTR_1_MASK_RELEASE_______</name>
37321                <description>Mask bit for corresponding field in the INTR register.</description>
37322                <bitRange>[15:0]</bitRange>
37323                <access>read-write</access>
37324              </field>
37325              <field>
37326                <name>MXIPC_INTR_1_MASK_MXIPC_INTR_1_MASK_NOTIFY</name>
37327                <description>Mask bit for corresponding field in the INTR register.</description>
37328                <bitRange>[31:16]</bitRange>
37329                <access>read-write</access>
37330              </field>
37331            </fields>
37332          </register>
37333          <register>
37334            <name>MXIPC_INTR_1_MASKED</name>
37335            <description>N/A</description>
37336            <addressOffset>0x8102C</addressOffset>
37337            <size>32</size>
37338            <access>read-only</access>
37339            <resetValue>0x0</resetValue>
37340            <resetMask>0xFFFFFFFF</resetMask>
37341            <fields>
37342              <field>
37343                <name>MXIPC_INTR_1_MASKED_MXIPC_INTR_1_MASKED_RELEASE_______</name>
37344                <description>Logical and of corresponding request and mask bits.</description>
37345                <bitRange>[15:0]</bitRange>
37346                <access>read-only</access>
37347              </field>
37348              <field>
37349                <name>MXIPC_INTR_1_MASKED_MXIPC_INTR_1_MASKED_NOTIFY</name>
37350                <description>Logical and of corresponding INTR and INTR_MASK fields.</description>
37351                <bitRange>[31:16]</bitRange>
37352                <access>read-only</access>
37353              </field>
37354            </fields>
37355          </register>
37356        </cluster>
37357      </registers>
37358    </peripheral>
37359  </peripherals>
37360</device>